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verbs.h
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verbs.h
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/*
* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
* Copyright (c) 2004, 2011-2012 Intel Corporation. All rights reserved.
* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
* Copyright (c) 2005 PathScale, Inc. All rights reserved.
* Copyright (c) 2020 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef INFINIBAND_VERBS_H
#define INFINIBAND_VERBS_H
#include <stdint.h>
#include <pthread.h>
#include <stddef.h>
#include <errno.h>
#include <string.h>
#include <linux/types.h>
#include <linux/if_ether.h>
#include <sys/types.h>
#include <infiniband/verbs_api.h>
#ifdef __cplusplus
#include <limits>
#endif
#if __GNUC__ >= 3
# define __attribute_const __attribute__((const))
#else
# define __attribute_const
#endif
#ifdef __cplusplus
extern "C" {
#endif
union ibv_gid {
uint8_t raw[16];
struct {
__be64 subnet_prefix;
__be64 interface_id;
} global;
};
enum ibv_gid_type {
IBV_GID_TYPE_IB,
IBV_GID_TYPE_ROCE_V1,
IBV_GID_TYPE_ROCE_V2,
};
struct ibv_gid_entry {
union ibv_gid gid;
uint32_t gid_index;
uint32_t port_num;
uint32_t gid_type; /* enum ibv_gid_type */
uint32_t ndev_ifindex;
};
#define vext_field_avail(type, fld, sz) (offsetof(type, fld) < (sz))
#ifdef __cplusplus
#define __VERBS_ABI_IS_EXTENDED ((void *)std::numeric_limits<uintptr_t>::max())
#else
#define __VERBS_ABI_IS_EXTENDED ((void *)UINTPTR_MAX)
#endif
enum ibv_node_type {
IBV_NODE_UNKNOWN = -1,
IBV_NODE_CA = 1,
IBV_NODE_SWITCH,
IBV_NODE_ROUTER,
IBV_NODE_RNIC,
IBV_NODE_USNIC,
IBV_NODE_USNIC_UDP,
IBV_NODE_UNSPECIFIED,
};
enum ibv_transport_type {
IBV_TRANSPORT_UNKNOWN = -1,
IBV_TRANSPORT_IB = 0,
IBV_TRANSPORT_IWARP,
IBV_TRANSPORT_USNIC,
IBV_TRANSPORT_USNIC_UDP,
IBV_TRANSPORT_UNSPECIFIED,
};
enum ibv_device_cap_flags {
IBV_DEVICE_RESIZE_MAX_WR = 1,
IBV_DEVICE_BAD_PKEY_CNTR = 1 << 1,
IBV_DEVICE_BAD_QKEY_CNTR = 1 << 2,
IBV_DEVICE_RAW_MULTI = 1 << 3,
IBV_DEVICE_AUTO_PATH_MIG = 1 << 4,
IBV_DEVICE_CHANGE_PHY_PORT = 1 << 5,
IBV_DEVICE_UD_AV_PORT_ENFORCE = 1 << 6,
IBV_DEVICE_CURR_QP_STATE_MOD = 1 << 7,
IBV_DEVICE_SHUTDOWN_PORT = 1 << 8,
IBV_DEVICE_INIT_TYPE = 1 << 9,
IBV_DEVICE_PORT_ACTIVE_EVENT = 1 << 10,
IBV_DEVICE_SYS_IMAGE_GUID = 1 << 11,
IBV_DEVICE_RC_RNR_NAK_GEN = 1 << 12,
IBV_DEVICE_SRQ_RESIZE = 1 << 13,
IBV_DEVICE_N_NOTIFY_CQ = 1 << 14,
IBV_DEVICE_MEM_WINDOW = 1 << 17,
IBV_DEVICE_UD_IP_CSUM = 1 << 18,
IBV_DEVICE_XRC = 1 << 20,
IBV_DEVICE_MEM_MGT_EXTENSIONS = 1 << 21,
IBV_DEVICE_MEM_WINDOW_TYPE_2A = 1 << 23,
IBV_DEVICE_MEM_WINDOW_TYPE_2B = 1 << 24,
IBV_DEVICE_RC_IP_CSUM = 1 << 25,
IBV_DEVICE_RAW_IP_CSUM = 1 << 26,
IBV_DEVICE_MANAGED_FLOW_STEERING = 1 << 29
};
enum ibv_fork_status {
IBV_FORK_DISABLED,
IBV_FORK_ENABLED,
IBV_FORK_UNNEEDED,
};
/*
* Can't extended above ibv_device_cap_flags enum as in some systems/compilers
* enum range is limited to 4 bytes.
*/
#define IBV_DEVICE_RAW_SCATTER_FCS (1ULL << 34)
#define IBV_DEVICE_PCI_WRITE_END_PADDING (1ULL << 36)
enum ibv_atomic_cap {
IBV_ATOMIC_NONE,
IBV_ATOMIC_HCA,
IBV_ATOMIC_GLOB
};
struct ibv_alloc_dm_attr {
size_t length;
uint32_t log_align_req;
uint32_t comp_mask;
};
enum ibv_dm_mask {
IBV_DM_MASK_HANDLE = 1 << 0,
};
struct ibv_dm {
struct ibv_context *context;
int (*memcpy_to_dm)(struct ibv_dm *dm, uint64_t dm_offset,
const void *host_addr, size_t length);
int (*memcpy_from_dm)(void *host_addr, struct ibv_dm *dm,
uint64_t dm_offset, size_t length);
uint32_t comp_mask;
uint32_t handle;
};
struct ibv_device_attr {
char fw_ver[64];
__be64 node_guid;
__be64 sys_image_guid;
uint64_t max_mr_size;
uint64_t page_size_cap;
uint32_t vendor_id;
uint32_t vendor_part_id;
uint32_t hw_ver;
int max_qp;
int max_qp_wr;
unsigned int device_cap_flags;
int max_sge;
int max_sge_rd;
int max_cq;
int max_cqe;
int max_mr;
int max_pd;
int max_qp_rd_atom;
int max_ee_rd_atom;
int max_res_rd_atom;
int max_qp_init_rd_atom;
int max_ee_init_rd_atom;
enum ibv_atomic_cap atomic_cap;
int max_ee;
int max_rdd;
int max_mw;
int max_raw_ipv6_qp;
int max_raw_ethy_qp;
int max_mcast_grp;
int max_mcast_qp_attach;
int max_total_mcast_qp_attach;
int max_ah;
int max_fmr;
int max_map_per_fmr;
int max_srq;
int max_srq_wr;
int max_srq_sge;
uint16_t max_pkeys;
uint8_t local_ca_ack_delay;
uint8_t phys_port_cnt;
};
/* An extensible input struct for possible future extensions of the
* ibv_query_device_ex verb. */
struct ibv_query_device_ex_input {
uint32_t comp_mask;
};
enum ibv_odp_transport_cap_bits {
IBV_ODP_SUPPORT_SEND = 1 << 0,
IBV_ODP_SUPPORT_RECV = 1 << 1,
IBV_ODP_SUPPORT_WRITE = 1 << 2,
IBV_ODP_SUPPORT_READ = 1 << 3,
IBV_ODP_SUPPORT_ATOMIC = 1 << 4,
IBV_ODP_SUPPORT_SRQ_RECV = 1 << 5,
};
struct ibv_odp_caps {
uint64_t general_caps;
struct {
uint32_t rc_odp_caps;
uint32_t uc_odp_caps;
uint32_t ud_odp_caps;
} per_transport_caps;
};
enum ibv_odp_general_caps {
IBV_ODP_SUPPORT = 1 << 0,
IBV_ODP_SUPPORT_IMPLICIT = 1 << 1,
};
struct ibv_tso_caps {
uint32_t max_tso;
uint32_t supported_qpts;
};
/* RX Hash function flags */
enum ibv_rx_hash_function_flags {
IBV_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
};
/*
* RX Hash fields enable to set which incoming packet's field should
* participates in RX Hash. Each flag represent certain packet's field,
* when the flag is set the field that is represented by the flag will
* participate in RX Hash calculation.
* Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
* and *TCP and *UDP flags can't be enabled together on the same QP.
*/
enum ibv_rx_hash_fields {
IBV_RX_HASH_SRC_IPV4 = 1 << 0,
IBV_RX_HASH_DST_IPV4 = 1 << 1,
IBV_RX_HASH_SRC_IPV6 = 1 << 2,
IBV_RX_HASH_DST_IPV6 = 1 << 3,
IBV_RX_HASH_SRC_PORT_TCP = 1 << 4,
IBV_RX_HASH_DST_PORT_TCP = 1 << 5,
IBV_RX_HASH_SRC_PORT_UDP = 1 << 6,
IBV_RX_HASH_DST_PORT_UDP = 1 << 7,
IBV_RX_HASH_IPSEC_SPI = 1 << 8,
IBV_RX_HASH_INNER = (1UL << 31),
};
struct ibv_rss_caps {
uint32_t supported_qpts;
uint32_t max_rwq_indirection_tables;
uint32_t max_rwq_indirection_table_size;
uint64_t rx_hash_fields_mask; /* enum ibv_rx_hash_fields */
uint8_t rx_hash_function; /* enum ibv_rx_hash_function_flags */
};
struct ibv_packet_pacing_caps {
uint32_t qp_rate_limit_min;
uint32_t qp_rate_limit_max; /* In kbps */
uint32_t supported_qpts;
};
enum ibv_raw_packet_caps {
IBV_RAW_PACKET_CAP_CVLAN_STRIPPING = 1 << 0,
IBV_RAW_PACKET_CAP_SCATTER_FCS = 1 << 1,
IBV_RAW_PACKET_CAP_IP_CSUM = 1 << 2,
IBV_RAW_PACKET_CAP_DELAY_DROP = 1 << 3,
};
enum ibv_tm_cap_flags {
IBV_TM_CAP_RC = 1 << 0,
};
struct ibv_tm_caps {
/* Max size of rendezvous request header */
uint32_t max_rndv_hdr_size;
/* Max number of tagged buffers in a TM-SRQ matching list */
uint32_t max_num_tags;
/* From enum ibv_tm_cap_flags */
uint32_t flags;
/* Max number of outstanding list operations */
uint32_t max_ops;
/* Max number of SGEs in a tagged buffer */
uint32_t max_sge;
};
struct ibv_cq_moderation_caps {
uint16_t max_cq_count;
uint16_t max_cq_period; /* in micro seconds */
};
enum ibv_pci_atomic_op_size {
IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP = 1 << 0,
IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP = 1 << 1,
IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP = 1 << 2,
};
/*
* Bitmask for supported operation sizes
* Use enum ibv_pci_atomic_op_size
*/
struct ibv_pci_atomic_caps {
uint16_t fetch_add;
uint16_t swap;
uint16_t compare_swap;
};
struct ibv_device_attr_ex {
struct ibv_device_attr orig_attr;
uint32_t comp_mask;
struct ibv_odp_caps odp_caps;
uint64_t completion_timestamp_mask;
uint64_t hca_core_clock;
uint64_t device_cap_flags_ex;
struct ibv_tso_caps tso_caps;
struct ibv_rss_caps rss_caps;
uint32_t max_wq_type_rq;
struct ibv_packet_pacing_caps packet_pacing_caps;
uint32_t raw_packet_caps; /* Use ibv_raw_packet_caps */
struct ibv_tm_caps tm_caps;
struct ibv_cq_moderation_caps cq_mod_caps;
uint64_t max_dm_size;
struct ibv_pci_atomic_caps pci_atomic_caps;
uint32_t xrc_odp_caps;
uint32_t phys_port_cnt_ex;
};
enum ibv_mtu {
IBV_MTU_256 = 1,
IBV_MTU_512 = 2,
IBV_MTU_1024 = 3,
IBV_MTU_2048 = 4,
IBV_MTU_4096 = 5
};
enum ibv_port_state {
IBV_PORT_NOP = 0,
IBV_PORT_DOWN = 1,
IBV_PORT_INIT = 2,
IBV_PORT_ARMED = 3,
IBV_PORT_ACTIVE = 4,
IBV_PORT_ACTIVE_DEFER = 5
};
enum {
IBV_LINK_LAYER_UNSPECIFIED,
IBV_LINK_LAYER_INFINIBAND,
IBV_LINK_LAYER_ETHERNET,
};
enum ibv_port_cap_flags {
IBV_PORT_SM = 1 << 1,
IBV_PORT_NOTICE_SUP = 1 << 2,
IBV_PORT_TRAP_SUP = 1 << 3,
IBV_PORT_OPT_IPD_SUP = 1 << 4,
IBV_PORT_AUTO_MIGR_SUP = 1 << 5,
IBV_PORT_SL_MAP_SUP = 1 << 6,
IBV_PORT_MKEY_NVRAM = 1 << 7,
IBV_PORT_PKEY_NVRAM = 1 << 8,
IBV_PORT_LED_INFO_SUP = 1 << 9,
IBV_PORT_SYS_IMAGE_GUID_SUP = 1 << 11,
IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12,
IBV_PORT_EXTENDED_SPEEDS_SUP = 1 << 14,
IBV_PORT_CAP_MASK2_SUP = 1 << 15,
IBV_PORT_CM_SUP = 1 << 16,
IBV_PORT_SNMP_TUNNEL_SUP = 1 << 17,
IBV_PORT_REINIT_SUP = 1 << 18,
IBV_PORT_DEVICE_MGMT_SUP = 1 << 19,
IBV_PORT_VENDOR_CLASS_SUP = 1 << 20,
IBV_PORT_DR_NOTICE_SUP = 1 << 21,
IBV_PORT_CAP_MASK_NOTICE_SUP = 1 << 22,
IBV_PORT_BOOT_MGMT_SUP = 1 << 23,
IBV_PORT_LINK_LATENCY_SUP = 1 << 24,
IBV_PORT_CLIENT_REG_SUP = 1 << 25,
IBV_PORT_IP_BASED_GIDS = 1 << 26
};
enum ibv_port_cap_flags2 {
IBV_PORT_SET_NODE_DESC_SUP = 1 << 0,
IBV_PORT_INFO_EXT_SUP = 1 << 1,
IBV_PORT_VIRT_SUP = 1 << 2,
IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP = 1 << 3,
IBV_PORT_LINK_WIDTH_2X_SUP = 1 << 4,
IBV_PORT_LINK_SPEED_HDR_SUP = 1 << 5,
IBV_PORT_LINK_SPEED_NDR_SUP = 1 << 10,
IBV_PORT_LINK_SPEED_XDR_SUP = 1 << 12,
};
struct ibv_port_attr {
enum ibv_port_state state;
enum ibv_mtu max_mtu;
enum ibv_mtu active_mtu;
int gid_tbl_len;
uint32_t port_cap_flags;
uint32_t max_msg_sz;
uint32_t bad_pkey_cntr;
uint32_t qkey_viol_cntr;
uint16_t pkey_tbl_len;
uint16_t lid;
uint16_t sm_lid;
uint8_t lmc;
uint8_t max_vl_num;
uint8_t sm_sl;
uint8_t subnet_timeout;
uint8_t init_type_reply;
uint8_t active_width;
uint8_t active_speed;
uint8_t phys_state;
uint8_t link_layer;
uint8_t flags;
uint16_t port_cap_flags2;
uint32_t active_speed_ex;
};
enum ibv_event_type {
IBV_EVENT_CQ_ERR,
IBV_EVENT_QP_FATAL,
IBV_EVENT_QP_REQ_ERR,
IBV_EVENT_QP_ACCESS_ERR,
IBV_EVENT_COMM_EST,
IBV_EVENT_SQ_DRAINED,
IBV_EVENT_PATH_MIG,
IBV_EVENT_PATH_MIG_ERR,
IBV_EVENT_DEVICE_FATAL,
IBV_EVENT_PORT_ACTIVE,
IBV_EVENT_PORT_ERR,
IBV_EVENT_LID_CHANGE,
IBV_EVENT_PKEY_CHANGE,
IBV_EVENT_SM_CHANGE,
IBV_EVENT_SRQ_ERR,
IBV_EVENT_SRQ_LIMIT_REACHED,
IBV_EVENT_QP_LAST_WQE_REACHED,
IBV_EVENT_CLIENT_REREGISTER,
IBV_EVENT_GID_CHANGE,
IBV_EVENT_WQ_FATAL,
};
struct ibv_async_event {
union {
struct ibv_cq *cq;
struct ibv_qp *qp;
struct ibv_srq *srq;
struct ibv_wq *wq;
int port_num;
} element;
enum ibv_event_type event_type;
};
enum ibv_wc_status {
IBV_WC_SUCCESS,
IBV_WC_LOC_LEN_ERR,
IBV_WC_LOC_QP_OP_ERR,
IBV_WC_LOC_EEC_OP_ERR,
IBV_WC_LOC_PROT_ERR,
IBV_WC_WR_FLUSH_ERR,
IBV_WC_MW_BIND_ERR,
IBV_WC_BAD_RESP_ERR,
IBV_WC_LOC_ACCESS_ERR,
IBV_WC_REM_INV_REQ_ERR,
IBV_WC_REM_ACCESS_ERR,
IBV_WC_REM_OP_ERR,
IBV_WC_RETRY_EXC_ERR,
IBV_WC_RNR_RETRY_EXC_ERR,
IBV_WC_LOC_RDD_VIOL_ERR,
IBV_WC_REM_INV_RD_REQ_ERR,
IBV_WC_REM_ABORT_ERR,
IBV_WC_INV_EECN_ERR,
IBV_WC_INV_EEC_STATE_ERR,
IBV_WC_FATAL_ERR,
IBV_WC_RESP_TIMEOUT_ERR,
IBV_WC_GENERAL_ERR,
IBV_WC_TM_ERR,
IBV_WC_TM_RNDV_INCOMPLETE,
};
const char *ibv_wc_status_str(enum ibv_wc_status status);
enum ibv_wc_opcode {
IBV_WC_SEND,
IBV_WC_RDMA_WRITE,
IBV_WC_RDMA_READ,
IBV_WC_COMP_SWAP,
IBV_WC_FETCH_ADD,
IBV_WC_BIND_MW,
IBV_WC_LOCAL_INV,
IBV_WC_TSO,
IBV_WC_FLUSH,
IBV_WC_ATOMIC_WRITE = 9,
/*
* Set value of IBV_WC_RECV so consumers can test if a completion is a
* receive by testing (opcode & IBV_WC_RECV).
*/
IBV_WC_RECV = 1 << 7,
IBV_WC_RECV_RDMA_WITH_IMM,
IBV_WC_TM_ADD,
IBV_WC_TM_DEL,
IBV_WC_TM_SYNC,
IBV_WC_TM_RECV,
IBV_WC_TM_NO_TAG,
IBV_WC_DRIVER1,
IBV_WC_DRIVER2,
IBV_WC_DRIVER3,
};
enum {
IBV_WC_IP_CSUM_OK_SHIFT = 2
};
enum ibv_create_cq_wc_flags {
IBV_WC_EX_WITH_BYTE_LEN = 1 << 0,
IBV_WC_EX_WITH_IMM = 1 << 1,
IBV_WC_EX_WITH_QP_NUM = 1 << 2,
IBV_WC_EX_WITH_SRC_QP = 1 << 3,
IBV_WC_EX_WITH_SLID = 1 << 4,
IBV_WC_EX_WITH_SL = 1 << 5,
IBV_WC_EX_WITH_DLID_PATH_BITS = 1 << 6,
IBV_WC_EX_WITH_COMPLETION_TIMESTAMP = 1 << 7,
IBV_WC_EX_WITH_CVLAN = 1 << 8,
IBV_WC_EX_WITH_FLOW_TAG = 1 << 9,
IBV_WC_EX_WITH_TM_INFO = 1 << 10,
IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK = 1 << 11,
};
enum {
IBV_WC_STANDARD_FLAGS = IBV_WC_EX_WITH_BYTE_LEN |
IBV_WC_EX_WITH_IMM |
IBV_WC_EX_WITH_QP_NUM |
IBV_WC_EX_WITH_SRC_QP |
IBV_WC_EX_WITH_SLID |
IBV_WC_EX_WITH_SL |
IBV_WC_EX_WITH_DLID_PATH_BITS
};
enum {
IBV_CREATE_CQ_SUP_WC_FLAGS = IBV_WC_STANDARD_FLAGS |
IBV_WC_EX_WITH_COMPLETION_TIMESTAMP |
IBV_WC_EX_WITH_CVLAN |
IBV_WC_EX_WITH_FLOW_TAG |
IBV_WC_EX_WITH_TM_INFO |
IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK
};
enum ibv_wc_flags {
IBV_WC_GRH = 1 << 0,
IBV_WC_WITH_IMM = 1 << 1,
IBV_WC_IP_CSUM_OK = 1 << IBV_WC_IP_CSUM_OK_SHIFT,
IBV_WC_WITH_INV = 1 << 3,
IBV_WC_TM_SYNC_REQ = 1 << 4,
IBV_WC_TM_MATCH = 1 << 5,
IBV_WC_TM_DATA_VALID = 1 << 6,
};
struct ibv_wc {
uint64_t wr_id;
enum ibv_wc_status status;
enum ibv_wc_opcode opcode;
uint32_t vendor_err;
uint32_t byte_len;
/* When (wc_flags & IBV_WC_WITH_IMM): Immediate data in network byte order.
* When (wc_flags & IBV_WC_WITH_INV): Stores the invalidated rkey.
*/
union {
__be32 imm_data;
uint32_t invalidated_rkey;
};
uint32_t qp_num;
uint32_t src_qp;
unsigned int wc_flags;
uint16_t pkey_index;
uint16_t slid;
uint8_t sl;
uint8_t dlid_path_bits;
};
enum ibv_access_flags {
IBV_ACCESS_LOCAL_WRITE = 1,
IBV_ACCESS_REMOTE_WRITE = (1<<1),
IBV_ACCESS_REMOTE_READ = (1<<2),
IBV_ACCESS_REMOTE_ATOMIC = (1<<3),
IBV_ACCESS_MW_BIND = (1<<4),
IBV_ACCESS_ZERO_BASED = (1<<5),
IBV_ACCESS_ON_DEMAND = (1<<6),
IBV_ACCESS_HUGETLB = (1<<7),
IBV_ACCESS_FLUSH_GLOBAL = (1 << 8),
IBV_ACCESS_FLUSH_PERSISTENT = (1 << 9),
IBV_ACCESS_RELAXED_ORDERING = IBV_ACCESS_OPTIONAL_FIRST,
};
struct ibv_mw_bind_info {
struct ibv_mr *mr;
uint64_t addr;
uint64_t length;
unsigned int mw_access_flags; /* use ibv_access_flags */
};
struct ibv_pd {
struct ibv_context *context;
uint32_t handle;
};
struct ibv_td_init_attr {
uint32_t comp_mask;
};
struct ibv_td {
struct ibv_context *context;
};
enum ibv_xrcd_init_attr_mask {
IBV_XRCD_INIT_ATTR_FD = 1 << 0,
IBV_XRCD_INIT_ATTR_OFLAGS = 1 << 1,
IBV_XRCD_INIT_ATTR_RESERVED = 1 << 2
};
struct ibv_xrcd_init_attr {
uint32_t comp_mask;
int fd;
int oflags;
};
struct ibv_xrcd {
struct ibv_context *context;
};
enum ibv_rereg_mr_flags {
IBV_REREG_MR_CHANGE_TRANSLATION = (1 << 0),
IBV_REREG_MR_CHANGE_PD = (1 << 1),
IBV_REREG_MR_CHANGE_ACCESS = (1 << 2),
IBV_REREG_MR_FLAGS_SUPPORTED = ((IBV_REREG_MR_CHANGE_ACCESS << 1) - 1)
};
struct ibv_mr {
struct ibv_context *context;
struct ibv_pd *pd;
void *addr;
size_t length;
uint32_t handle;
uint32_t lkey;
uint32_t rkey;
};
enum ibv_mw_type {
IBV_MW_TYPE_1 = 1,
IBV_MW_TYPE_2 = 2
};
struct ibv_mw {
struct ibv_context *context;
struct ibv_pd *pd;
uint32_t rkey;
uint32_t handle;
enum ibv_mw_type type;
};
struct ibv_global_route {
union ibv_gid dgid;
uint32_t flow_label;
uint8_t sgid_index;
uint8_t hop_limit;
uint8_t traffic_class;
};
struct ibv_grh {
__be32 version_tclass_flow;
__be16 paylen;
uint8_t next_hdr;
uint8_t hop_limit;
union ibv_gid sgid;
union ibv_gid dgid;
};
enum ibv_rate {
IBV_RATE_MAX = 0,
IBV_RATE_2_5_GBPS = 2,
IBV_RATE_5_GBPS = 5,
IBV_RATE_10_GBPS = 3,
IBV_RATE_20_GBPS = 6,
IBV_RATE_30_GBPS = 4,
IBV_RATE_40_GBPS = 7,
IBV_RATE_60_GBPS = 8,
IBV_RATE_80_GBPS = 9,
IBV_RATE_120_GBPS = 10,
IBV_RATE_14_GBPS = 11,
IBV_RATE_56_GBPS = 12,
IBV_RATE_112_GBPS = 13,
IBV_RATE_168_GBPS = 14,
IBV_RATE_25_GBPS = 15,
IBV_RATE_100_GBPS = 16,
IBV_RATE_200_GBPS = 17,
IBV_RATE_300_GBPS = 18,
IBV_RATE_28_GBPS = 19,
IBV_RATE_50_GBPS = 20,
IBV_RATE_400_GBPS = 21,
IBV_RATE_600_GBPS = 22,
IBV_RATE_800_GBPS = 23,
IBV_RATE_1200_GBPS = 24,
};
/**
* ibv_rate_to_mult - Convert the IB rate enum to a multiple of the
* base rate of 2.5 Gbit/sec. For example, IBV_RATE_5_GBPS will be
* converted to 2, since 5 Gbit/sec is 2 * 2.5 Gbit/sec.
* @rate: rate to convert.
*/
int __attribute_const ibv_rate_to_mult(enum ibv_rate rate);
/**
* mult_to_ibv_rate - Convert a multiple of 2.5 Gbit/sec to an IB rate enum.
* @mult: multiple to convert.
*/
enum ibv_rate __attribute_const mult_to_ibv_rate(int mult);
/**
* ibv_rate_to_mbps - Convert the IB rate enum to Mbit/sec.
* For example, IBV_RATE_5_GBPS will return the value 5000.
* @rate: rate to convert.
*/
int __attribute_const ibv_rate_to_mbps(enum ibv_rate rate);
/**
* mbps_to_ibv_rate - Convert a Mbit/sec value to an IB rate enum.
* @mbps: value to convert.
*/
enum ibv_rate __attribute_const mbps_to_ibv_rate(int mbps);
struct ibv_ah_attr {
struct ibv_global_route grh;
uint16_t dlid;
uint8_t sl;
uint8_t src_path_bits;
uint8_t static_rate;
uint8_t is_global;
uint8_t port_num;
};
enum ibv_srq_attr_mask {
IBV_SRQ_MAX_WR = 1 << 0,
IBV_SRQ_LIMIT = 1 << 1
};
struct ibv_srq_attr {
uint32_t max_wr;
uint32_t max_sge;
uint32_t srq_limit;
};
struct ibv_srq_init_attr {
void *srq_context;
struct ibv_srq_attr attr;
};
enum ibv_srq_type {
IBV_SRQT_BASIC,
IBV_SRQT_XRC,
IBV_SRQT_TM,
};
enum ibv_srq_init_attr_mask {
IBV_SRQ_INIT_ATTR_TYPE = 1 << 0,
IBV_SRQ_INIT_ATTR_PD = 1 << 1,
IBV_SRQ_INIT_ATTR_XRCD = 1 << 2,
IBV_SRQ_INIT_ATTR_CQ = 1 << 3,
IBV_SRQ_INIT_ATTR_TM = 1 << 4,
IBV_SRQ_INIT_ATTR_RESERVED = 1 << 5,
};
struct ibv_tm_cap {
uint32_t max_num_tags;
uint32_t max_ops;
};
struct ibv_srq_init_attr_ex {
void *srq_context;
struct ibv_srq_attr attr;
uint32_t comp_mask;
enum ibv_srq_type srq_type;
struct ibv_pd *pd;
struct ibv_xrcd *xrcd;
struct ibv_cq *cq;
struct ibv_tm_cap tm_cap;
};
enum ibv_wq_type {
IBV_WQT_RQ
};
enum ibv_wq_init_attr_mask {
IBV_WQ_INIT_ATTR_FLAGS = 1 << 0,
IBV_WQ_INIT_ATTR_RESERVED = 1 << 1,
};
enum ibv_wq_flags {
IBV_WQ_FLAGS_CVLAN_STRIPPING = 1 << 0,
IBV_WQ_FLAGS_SCATTER_FCS = 1 << 1,
IBV_WQ_FLAGS_DELAY_DROP = 1 << 2,
IBV_WQ_FLAGS_PCI_WRITE_END_PADDING = 1 << 3,
IBV_WQ_FLAGS_RESERVED = 1 << 4,
};
struct ibv_wq_init_attr {
void *wq_context;
enum ibv_wq_type wq_type;
uint32_t max_wr;
uint32_t max_sge;
struct ibv_pd *pd;
struct ibv_cq *cq;
uint32_t comp_mask; /* Use ibv_wq_init_attr_mask */
uint32_t create_flags; /* use ibv_wq_flags */
};
enum ibv_wq_state {
IBV_WQS_RESET,
IBV_WQS_RDY,
IBV_WQS_ERR,
IBV_WQS_UNKNOWN
};
enum ibv_wq_attr_mask {
IBV_WQ_ATTR_STATE = 1 << 0,
IBV_WQ_ATTR_CURR_STATE = 1 << 1,
IBV_WQ_ATTR_FLAGS = 1 << 2,
IBV_WQ_ATTR_RESERVED = 1 << 3,
};
struct ibv_wq_attr {
/* enum ibv_wq_attr_mask */
uint32_t attr_mask;
/* Move the WQ to this state */
enum ibv_wq_state wq_state;
/* Assume this is the current WQ state */
enum ibv_wq_state curr_wq_state;
uint32_t flags; /* Use ibv_wq_flags */
uint32_t flags_mask; /* Use ibv_wq_flags */
};
/*
* Receive Work Queue Indirection Table.
* It's used in order to distribute incoming packets between different
* Receive Work Queues. Associating Receive WQs with different CPU cores
* allows one to workload the traffic between different CPU cores.
* The Indirection Table can contain only WQs of type IBV_WQT_RQ.
*/
struct ibv_rwq_ind_table {
struct ibv_context *context;
int ind_tbl_handle;
int ind_tbl_num;
uint32_t comp_mask;
};
enum ibv_ind_table_init_attr_mask {
IBV_CREATE_IND_TABLE_RESERVED = (1 << 0)
};
/*
* Receive Work Queue Indirection Table attributes
*/
struct ibv_rwq_ind_table_init_attr {
uint32_t log_ind_tbl_size;
/* Each entry is a pointer to a Receive Work Queue */
struct ibv_wq **ind_tbl;
uint32_t comp_mask;
};
enum ibv_qp_type {
IBV_QPT_RC = 2,
IBV_QPT_UC,
IBV_QPT_UD,
IBV_QPT_RAW_PACKET = 8,
IBV_QPT_XRC_SEND = 9,
IBV_QPT_XRC_RECV,
IBV_QPT_DRIVER = 0xff,
};
struct ibv_qp_cap {
uint32_t max_send_wr;
uint32_t max_recv_wr;
uint32_t max_send_sge;
uint32_t max_recv_sge;
uint32_t max_inline_data;
};
struct ibv_qp_init_attr {
void *qp_context;
struct ibv_cq *send_cq;
struct ibv_cq *recv_cq;
struct ibv_srq *srq;
struct ibv_qp_cap cap;
enum ibv_qp_type qp_type;
int sq_sig_all;
};
enum ibv_qp_init_attr_mask {
IBV_QP_INIT_ATTR_PD = 1 << 0,
IBV_QP_INIT_ATTR_XRCD = 1 << 1,
IBV_QP_INIT_ATTR_CREATE_FLAGS = 1 << 2,
IBV_QP_INIT_ATTR_MAX_TSO_HEADER = 1 << 3,
IBV_QP_INIT_ATTR_IND_TABLE = 1 << 4,
IBV_QP_INIT_ATTR_RX_HASH = 1 << 5,
IBV_QP_INIT_ATTR_SEND_OPS_FLAGS = 1 << 6,
};
enum ibv_qp_create_flags {
IBV_QP_CREATE_BLOCK_SELF_MCAST_LB = 1 << 1,
IBV_QP_CREATE_SCATTER_FCS = 1 << 8,
IBV_QP_CREATE_CVLAN_STRIPPING = 1 << 9,
IBV_QP_CREATE_SOURCE_QPN = 1 << 10,
IBV_QP_CREATE_PCI_WRITE_END_PADDING = 1 << 11,
};
enum ibv_qp_create_send_ops_flags {
IBV_QP_EX_WITH_RDMA_WRITE = 1 << 0,
IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM = 1 << 1,
IBV_QP_EX_WITH_SEND = 1 << 2,
IBV_QP_EX_WITH_SEND_WITH_IMM = 1 << 3,
IBV_QP_EX_WITH_RDMA_READ = 1 << 4,
IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP = 1 << 5,
IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD = 1 << 6,
IBV_QP_EX_WITH_LOCAL_INV = 1 << 7,
IBV_QP_EX_WITH_BIND_MW = 1 << 8,
IBV_QP_EX_WITH_SEND_WITH_INV = 1 << 9,
IBV_QP_EX_WITH_TSO = 1 << 10,
IBV_QP_EX_WITH_FLUSH = 1 << 11,
IBV_QP_EX_WITH_ATOMIC_WRITE = 1 << 12,
};
struct ibv_rx_hash_conf {
/* enum ibv_rx_hash_function_flags */
uint8_t rx_hash_function;
uint8_t rx_hash_key_len;
uint8_t *rx_hash_key;
/* enum ibv_rx_hash_fields */
uint64_t rx_hash_fields_mask;
};
struct ibv_qp_init_attr_ex {
void *qp_context;
struct ibv_cq *send_cq;
struct ibv_cq *recv_cq;
struct ibv_srq *srq;
struct ibv_qp_cap cap;
enum ibv_qp_type qp_type;
int sq_sig_all;
uint32_t comp_mask;
struct ibv_pd *pd;
struct ibv_xrcd *xrcd;
uint32_t create_flags;
uint16_t max_tso_header;
struct ibv_rwq_ind_table *rwq_ind_tbl;
struct ibv_rx_hash_conf rx_hash_conf;
uint32_t source_qpn;
/* See enum ibv_qp_create_send_ops_flags */
uint64_t send_ops_flags;
};
enum ibv_qp_open_attr_mask {
IBV_QP_OPEN_ATTR_NUM = 1 << 0,
IBV_QP_OPEN_ATTR_XRCD = 1 << 1,
IBV_QP_OPEN_ATTR_CONTEXT = 1 << 2,
IBV_QP_OPEN_ATTR_TYPE = 1 << 3,
IBV_QP_OPEN_ATTR_RESERVED = 1 << 4
};