When I build project with "--with-ethernet" I got "Liftoff!" screen

[fatihakalan]

Hey, I want to build litex project with ethernet peripheral. I succesfully builded project and generated bit file. I'm trying to loading boot.json file but I got this error.

How do I solve this any idea ? I try the changing --sys-clk 50MHz, 75 MHz ,100MHz but didn't worked. Also I was compiled with 100 MHz memtest is failed.

building command: python3 -m litex_boards.targets.efinix_trion_t120_bga576_dev_kit --with-ethernet --eth-ip ETH_IP --eth-phy=1 --sys-clk-freq 50e6 --build --load

[Beauxrel]

Have you gotten the serial boot to work?

[fatihakalan]

Yeah, I'm using serial boot way this command (litex_term --images=images/boot.json /dev/ttyUSBX) and I got BIOS menu. I run the reboot command but then stuck Liftoff screen

[Beauxrel]

I see these clock values

io = [
# Clk
("clk40", 0, Pins("P19"), IOStandard("3.3_V_LVTTL/LVCMOS")),
("clk50", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL/LVCMOS")),
("clk20", 0, Pins("AA9"), IOStandard("3.3_V_LVTTL/LVCMOS")),
("clk74_25", 0, Pins("J9"), IOStandard("3.3_V_LVTTL/_LVCMOS")),

have you tried clock 40, 20 or 74.25?

[Beauxrel]

Please let me know if that worked for you. @fatihakalan

[fatihakalan]

Thanks for reply first of all but I try now didn't work. 40, 20 or 74.25 MHz clocks. and also when ı give to 74.25 I get PLL error. In the other clocks I succesfully loading ".bit" file but linux doesn't boot succesfully. What should I do ? @Beauxrel

[Beauxrel]

What happens if you build with <./make.py board=efinix_trion_t120_bga576_dev_kit --with-ethernet --eth-ip ETH_IP --eth-phy=1 --sys-clk-freq 50e6 --build --load>

[Beauxrel]

from the linux-on-litex folder @fatihakalan

[Beauxrel]

Some of those commands may not be acceptable, but building the SoC from the make.py file is how I always do it.

[fatihakalan]

I get this error when I run "./make.py --board=efinix_trion_t120_bga576_dev_kit --with-ethernet --eth-ip ETH_IP --eth-phy=1 --sys-clk-freq 50e6 --build --load"

• make.py: error: unrecognized arguments: --with-ethernet --eth-ip ETH_IP --eth-phy=1 --sys-clk-freq 50e6
• @Beauxrel

[fatihakalan]

When I want to add some peripheral to my SoC I follow this repo:https://github.com/litex-hub/litex-boards. make.py command ı guess doesn't work with peripheral did you ever add peripheral parameter ?
@Beauxrel

[Beauxrel]

Can you copy and paste the full make.py file

[fatihakalan]

Efinix Boards
#---------------------------------------------------------------------------------------------------

class TrionT120BGA576DevKit(Board):
soc_kwargs = {"l2_size" : 2048} # Use Wishbone and L2 for memory accesses.
def init(self):
from litex_boards.targets import efinix_trion_t120_bga576_dev_kit
Board.init(self, efinix_trion_t120_bga576_dev_kit.BaseSoC, soc_capabilities={

Communication

"serial",
"ethernet",

GPIOs

"leds",
})
I was add "ethernet" option at now trying with this maybe its effected . Normally there no ethernet in communication line just serial

[Beauxrel]

That is excatly what I was going to say, try to include ethernet and build it without all the other commands ./make.p board= --sys-clk-freq 50e6 --build --load

[fatihakalan]

Okay I'm trying to directly build but "--load" doesn't work. I'm using OpenFPGALoader to boot .bit file. Do you think any effect ? And I let you know my output.

[Beauxrel]

Is the bit file being generated?

[fatihakalan]

Yeah it is being created I'm waitig to finish

[fatihakalan]

it is succesfully booting .bit file and also linux but there are no ethernet as like eth0 when I run ifconfig command.

[Beauxrel]

In your efinix_trion_t120_bga576_dev_kit.py file try setting
with_ethernet, with_etherbone and eth_phy

class BaseSoC(SoCCore):
def init(self, sys_clk_freq=75e6,
with_spi_flash = False,
with_ethernet = False, <- true
with_etherbone = False,<- true
eth_phy = 0, <- 1
eth_ip = "192.168.1.50",
with_led_chaser = True,
**kwargs):
platform = efinix_trion_t120_bga576_dev_kit.Platform()

[Beauxrel]

and running make.py again

[Beauxrel]

looks like base frequency they use is 75MHz

[fatihakalan]

yeah base frequency 75 MHz .I'm trying now actually ı remember ı was tried this way but didn't work. I let you know output

[Beauxrel]

@fatihakalan Im thinking you may only need to set 1 of them to true, the if statement later is only only needs 1. I would choose "with_ethernet"

[fatihakalan]

okay I'm trying all of true and if it's fail ım gonna try case one of them is true (withethernet). But where is the if statement you mentioned about.

[Beauxrel]

`Ethernet / Etherbone

    if with_ethernet or with_etherbone:
        self.ethphy = LiteEthPHYRGMII(
            platform           = platform,
            clock_pads         = platform.request("eth_clocks", eth_phy),
            pads               = platform.request("eth", eth_phy),
            with_hw_init_reset = False)
        if with_ethernet:
            self.add_ethernet(phy=self.ethphy, software_debug=False)
        if with_etherbone:
            self.add_etherbone(phy=self.ethphy)

        # FIXME: Avoid this.
        platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").tx)
        platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").rx)
        platform.toolchain.excluded_ios.append(platform.lookup_request("eth").tx_data)
        platform.toolchain.excluded_ios.append(platform.lookup_request("eth").rx_data)
        platform.toolchain.excluded_ios.append(platform.lookup_request("eth").mdio)

`

[fatihakalan]

Okay, I got it I'm gonna try thanks

[fatihakalan]

When I changed

with_ethernet = False, <- true
with_etherbone = False,<- true
eth_phy = 0, <- 1

there are no eth0 @Beauxrel

[fatihakalan]

I tried this
with_ethernet = true
with_etherbone = False
eth_phy = 0,

but doesn't work. There are no eth0 @Beauxrel

[Beauxrel]

Looks like there was a push 3 hours ago for your board using PMOD RMII

https://www.waveshare.com/lan8720-eth-board.htm

litex-hub/litex-boards@2d3b81a