From 15c6f89b1a75c8dda50fb6b8ad1f139e728a78bf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 Jul 2024 09:52:23 +0200 Subject: [PATCH] #570: Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007. --- litex_boards/platforms/digilent_arty.py | 10 ++++++ litex_boards/platforms/digilent_genesys2.py | 36 ++++++++++--------- litex_boards/targets/digilent_arty.py | 31 ++++++----------- litex_boards/targets/digilent_genesys2.py | 38 ++++++++------------- 4 files changed, 54 insertions(+), 61 deletions(-) diff --git a/litex_boards/platforms/digilent_arty.py b/litex_boards/platforms/digilent_arty.py index 2037e8a96..ec99c8844 100644 --- a/litex_boards/platforms/digilent_arty.py +++ b/litex_boards/platforms/digilent_arty.py @@ -332,6 +332,16 @@ def numato_sdcard_pmod_io(pmod): ] _numato_sdcard_pmod_io = numato_sdcard_pmod_io("pmodd") # SDCARD PMOD on JD. +def can_pmod_io(pmod, n): + return [ + # SN65HVD230 based transceiver on PMOD, https://www.waveshare.com/sn65hvd230-can-board.htm. + ("can", n, + Subsignal("tx", Pins(f"{pmod}:2")), + Subsignal("rx", Pins(f"{pmod}:3")), + IOStandard("LVCMOS33"), + ), + ] + # Platform ----------------------------------------------------------------------------------------- class Platform(Xilinx7SeriesPlatform): diff --git a/litex_boards/platforms/digilent_genesys2.py b/litex_boards/platforms/digilent_genesys2.py index 6851ecd16..2307539a4 100644 --- a/litex_boards/platforms/digilent_genesys2.py +++ b/litex_boards/platforms/digilent_genesys2.py @@ -141,27 +141,29 @@ _connectors = [ ("HPC", { - "DP0_C2M_P": "Y2", - "DP0_C2M_N": "Y1", - "DP0_M2C_P": "AA4", - "DP0_M2C_N": "AA3", - "GBTCLK0_M2C_P": "L8", - "GBTCLK0_M2C_N": "L7", - } - ), - ("pmodc", { - "pmodc1": "AC26", - "pmodc2": "AJ27", - "pmodc3": "AH30", - "pmodc4": "AK29", - "pmodc5": "AD26", - "pmodc6": "AG30", - "pmodc7": "AK30", - "pmodc8": "AK28", + "DP0_C2M_P" : "Y2", + "DP0_C2M_N" : "Y1", + "DP0_M2C_P" : "AA4", + "DP0_M2C_N" : "AA3", + "GBTCLK0_M2C_P" : "L8", + "GBTCLK0_M2C_N" : "L7", } ), + ("pmodc", "AC26 AJ27 AH30 AK29 AD26 AG30 AK30 AK28"), ] +# PMODS -------------------------------------------------------------------------------------------- + +def can_pmod_io(pmod, n): + return [ + # SN65HVD230 based transceiver on PMOD, https://www.waveshare.com/sn65hvd230-can-board.htm. + ("can", n, + Subsignal("tx", Pins(f"{pmod}:2")), + Subsignal("rx", Pins(f"{pmod}:3")), + IOStandard("LVCMOS33"), + ), + ] + # Platform ----------------------------------------------------------------------------------------- class Platform(Xilinx7SeriesPlatform): diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 5e10c7b4a..6521ced64 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -31,8 +31,6 @@ from litedram.phy import s7ddrphy from liteeth.phy.mii import LiteEthPHYMII -from litex.build.generic_platform import Subsignal, Pins, IOStandard -from ctucan import CTUCAN, CTUCANWishboneWrapper # CRG ---------------------------------------------------------------------------------------------- @@ -85,6 +83,7 @@ def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6, with_spi_flash = False, with_buttons = False, with_pmod_gpio = False, + with_can = False, **kwargs): platform = digilent_arty.Platform(variant=variant, toolchain=toolchain) @@ -184,14 +183,14 @@ def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6, with_irq = self.irq.enabled ) -def can_io(): - return [( - "can", - 0, - Subsignal("rx", Pins("ck_io:ck_io0")), - Subsignal("tx", Pins("ck_io:ck_io1")), - IOStandard("LVCMOS33"), - )] + # CAN -------------------------------------------------------------------------------------- + if with_can: + from litex.soc.cores.can.ctu_can_fd import CTUCANFD + self.platform.add_extension(digilent_arty.can_pmod_io("pmodc", 0)) + self.can0 = CTUCANFD(platform, platform.request("can", 0)) + self.bus.add_slave("can0", self.can0.bus, SoCRegion(origin=0xb0010000, size=0x10000, mode="rw", cached=False)) + self.irq.add("can0") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -214,7 +213,7 @@ def main(): parser.add_target_argument("--sdcard-adapter", help="SDCard PMOD adapter (digilent or numato).") parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).") parser.add_target_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test. - parser.add_target_argument("--with-ctucan", action="store_true", help="Enable CTUCAN.") + parser.add_target_argument("--with-can", action="store_true", help="Enable CAN support (Through CTU-CAN-FD Core and SN65HVD230 'PMOD'.") args = parser.parse_args() assert not (args.with_etherbone and args.eth_dynamic_ip) @@ -233,18 +232,10 @@ def main(): with_usb = args.with_usb, with_spi_flash = args.with_spi_flash, with_pmod_gpio = args.with_pmod_gpio, - with_ctucan = args.with_ctucan, + with_can = args.with_can, **parser.soc_argdict ) - if args.with_ctucan: - soc.platform.add_extension(can_io()) - can_pads = soc.platform.request("can") - soc.submodules.can = CTUCAN(soc.platform, can_pads, "vhdl") - soc.add_memory_region("can", None, soc.can.wbwrapper.size, type=[]) - soc.add_wb_slave(soc.bus.regions["can"].origin, soc.can.wbwrapper.bus) - soc.add_interrupt("can") - if args.sdcard_adapter == "numato": soc.platform.add_extension(digilent_arty._numato_sdcard_pmod_io) else: diff --git a/litex_boards/targets/digilent_genesys2.py b/litex_boards/targets/digilent_genesys2.py index 6953248a0..aaaf95ba6 100755 --- a/litex_boards/targets/digilent_genesys2.py +++ b/litex_boards/targets/digilent_genesys2.py @@ -13,6 +13,7 @@ from litex_boards.platforms import digilent_genesys2 from litex.soc.cores.clock import * +from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -21,11 +22,6 @@ from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII -from litex.build.generic_platform import Subsignal, Pins, IOStandard -from ctucan import CTUCAN, CTUCANWishboneWrapper -from litex.soc.integration.soc import SoCRegion - - # CRG ---------------------------------------------------------------------------------------------- @@ -55,6 +51,7 @@ def __init__(self, sys_clk_freq=100e6, with_ethernet = False, with_etherbone = False, with_led_chaser = True, + with_can = False, **kwargs): platform = digilent_genesys2.Platform() @@ -90,16 +87,17 @@ def __init__(self, sys_clk_freq=100e6, if with_led_chaser: self.leds = LedChaser( pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) + sys_clk_freq = sys_clk_freq, + ) + + # CAN -------------------------------------------------------------------------------------- + if with_can: + from litex.soc.cores.can.ctu_can_fd import CTUCANFD + self.platform.add_extension(digilent_genesys2.can_pmod_io("pmodc", 0)) + self.can0 = CTUCANFD(platform, platform.request("can", 0)) + self.bus.add_slave("can0", self.can0.bus, SoCRegion(origin=0xb0010000, size=0x10000, mode="rw", cached=False)) + self.irq.add("can0") -def can_io(): - return [( - "can", - 0, - Subsignal("rx", Pins("pmodc:pmodc1")), - Subsignal("tx", Pins("pmodc:pmodc2")), - IOStandard("LVCMOS33"), - )] # Build -------------------------------------------------------------------------------------------- def main(): @@ -112,25 +110,17 @@ def main(): sdopts = parser.target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") - parser.add_target_argument("--with-ctucan", action="store_true", help="Enable CTUCAN.") + parser.add_target_argument("--with-can", action="store_true", help="Enable CAN support (Through CTU-CAN-FD Core and SN65HVD230 'PMOD'.") args = parser.parse_args() soc = BaseSoC( sys_clk_freq = args.sys_clk_freq, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, - with_ctucan = args.with_ctucan, + with_can = args.with_can, **parser.soc_argdict ) - if args.with_ctucan: - soc.platform.add_extension(can_io()) - can_pads = soc.platform.request("can") - soc.submodules.can = CTUCAN(soc.platform, can_pads, "vhdl") - can_region = SoCRegion(origin=soc.mem_map.get("can", None), size=soc.can.wbwrapper.size, cached=False) - soc.bus.add_slave(name="can", slave=soc.can.wbwrapper.bus, region=can_region) - soc.irq.add("can") - if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: