From efd6c8b0aadf1f746463d9039cc8a1a59fffb83b Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 19 Jun 2024 07:48:22 +0200 Subject: [PATCH 1/2] targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU --- litex_boards/targets/alinx_axu2cga.py | 11 ----------- litex_boards/targets/xilinx_kv260.py | 9 --------- litex_boards/targets/xilinx_zcu216.py | 9 --------- 3 files changed, 29 deletions(-) diff --git a/litex_boards/targets/alinx_axu2cga.py b/litex_boards/targets/alinx_axu2cga.py index 31b817555..a08aa6a44 100755 --- a/litex_boards/targets/alinx_axu2cga.py +++ b/litex_boards/targets/alinx_axu2cga.py @@ -77,23 +77,12 @@ def __init__(self, sys_clk_freq=25e6, with_led_chaser=True, **kwargs): if kwargs.get("cpu_type", None) == "zynqmp": kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False - self.mem_map = { - "csr": 0x8000_0000, # Zynq GP0 default - } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXU2CGA", **kwargs) # ZynqMP Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynqmp": self.cpu.config.update(platform.psu_config) - # Connect AXI HPM0 LPD to the SoC - wb_lpd = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(2, 32), - wishbone = wb_lpd, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_lpd) - self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 1 * 1024 * 1024 * 1024) # DDR diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py index 4eec0b76a..c46c512f6 100755 --- a/litex_boards/targets/xilinx_kv260.py +++ b/litex_boards/targets/xilinx_kv260.py @@ -56,8 +56,6 @@ def __init__(self, platform, sys_clk_freq, use_ps7_clk=False): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - mem_map = {"csr": 0xA000_0000} # default GP0 address on ZynqMP - def __init__(self, sys_clk_freq=100e6, **kwargs): platform = xilinx_kv260.Platform() @@ -127,13 +125,6 @@ def __init__(self, sys_clk_freq=100e6, **kwargs): 'PSU__UART1__PERIPHERAL__IO' : 'MIO 36 .. 37', }) - # Connect Zynq AXI master to the SoC - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 2 * 1024 * 1024 * 1024) # DDR diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py index d656ca024..a2b4b12a1 100755 --- a/litex_boards/targets/xilinx_zcu216.py +++ b/litex_boards/targets/xilinx_zcu216.py @@ -46,8 +46,6 @@ def __init__(self, platform, sys_clk_freq, use_ps7_clk=False): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - mem_map = {"csr": 0xA000_0000} # default GP0 address on ZynqMP - def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): platform = xilinx_zcu216.Platform() @@ -108,13 +106,6 @@ def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): 'PSU__UART0__PERIPHERAL__IO' : 'MIO 18 .. 19', }) - # Connect Zynq AXI master to the SoC - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 2 * 1024 * 1024 * 1024) # DDR From 70fb3de96cdf9d7e38051cd278560de08e2c566b Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 19 Jun 2024 07:59:24 +0200 Subject: [PATCH 2/2] targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU --- litex_boards/targets/digilent_arty_z7.py | 14 +++----------- litex_boards/targets/digilent_pynq_z1.py | 8 -------- litex_boards/targets/digilent_zedboard.py | 9 --------- litex_boards/targets/krtkl_snickerdoodle.py | 9 --------- litex_boards/targets/redpitaya.py | 10 ---------- litex_boards/targets/xilinx_zybo_z7.py | 10 ---------- 6 files changed, 3 insertions(+), 57 deletions(-) diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 4c8ef1667..04be70ac0 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -80,15 +80,15 @@ def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=125e6, # CRG -------------------------------------------------------------------------------------- use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000") + if use_ps7_clk: + sys_clk_freq = 100e6 + self.crg = _CRG(platform, sys_clk_freq, use_ps7_clk) # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False - self.mem_map = { - 'csr': 0x4000_0000, # Zynq GP0 default - } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty Z7", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- @@ -101,14 +101,6 @@ def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=125e6, "PCW_FPGA0_PERIPHERAL_FREQMHZ" : sys_clk_freq / 1e6, }) - # Connect AXI GP0 to the SoC - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) - self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) diff --git a/litex_boards/targets/digilent_pynq_z1.py b/litex_boards/targets/digilent_pynq_z1.py index a822137bf..3ef0db76c 100755 --- a/litex_boards/targets/digilent_pynq_z1.py +++ b/litex_boards/targets/digilent_pynq_z1.py @@ -79,14 +79,6 @@ def __init__(self, toolchain="vivado", sys_clk_freq=100e6, os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci") self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci") - # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = 0x43c00000) - self.bus.add_master(master=wb_gp0) - # Video ------------------------------------------------------------------------------------ if with_video_terminal: self.videophy = VideoS7HDMIPHY(platform.request("hdmi_tx"), clock_domain="hdmi") diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index 206e56cc8..9f59d5749 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -50,7 +50,6 @@ def __init__(self, platform, sys_clk_freq, use_ps7_clk=False): class BaseSoC(SoCCore): - mem_map = {"csr": 0x43c0_0000} # default GP0 address on Zynq def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): platform = digilent_zedboard.Platform() @@ -70,14 +69,6 @@ def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): preset="ZedBoard", config={'PCW_FPGA0_PERIPHERAL_FREQMHZ': sys_clk_freq / 1e6}) - # Connect AXI GP0 to the SoC - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) - self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index c78202ccc..a8573294f 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -81,21 +81,12 @@ def __init__(self, variant="z7-10", sys_clk_freq=100e6, if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False - self.mem_map = {"csr": 0x4000_0000} # Zynq GP0 default SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Snickerdoodle", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": load_ps7(self, xci_file) - # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = self.mem_map["csr"]) - self.bus.add_master(master=wb_gp0) - # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py index e4d560fa6..1c34f2e15 100755 --- a/litex_boards/targets/redpitaya.py +++ b/litex_boards/targets/redpitaya.py @@ -62,9 +62,6 @@ def __init__(self, board, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False - self.mem_map = { - 'csr': 0x43c0_0000, # Zynq GP0 default - } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zebboard", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- @@ -75,13 +72,6 @@ def __init__(self, board, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): os.system("cp redpitaya_ps7.txt xci/redpitaya_ps7.xci") self.cpu.set_ps7_xci("xci/redpitaya_ps7.xci") - # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = 0x43c00000) - self.bus.add_master(master=wb_gp0) self.bus.add_region("flash", SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx")) # Leds ------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index 6425780d8..86e344a64 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -57,9 +57,6 @@ def __init__(self, sys_clk_freq=100e6, variant="z7-10", with_ps7=False, with_led if kwargs.get("cpu_type", None) == "zynq7000": kwargs["integrated_sram_size"] = 0x0 kwargs["with_uart"] = False - self.mem_map = { - 'csr': 0x4000_0000, # Zynq GP0 default - } SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7/original Zybo", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- @@ -74,13 +71,6 @@ def __init__(self, sys_clk_freq=100e6, variant="z7-10", with_ps7=False, with_led else: self.cpu.set_ps7(name="ps", config = platform.ps7_config) - # Connect AXI GP0 to the SoC with base address of 0x40000000 (default one) - wb_gp0 = wishbone.Interface() - self.submodules += axi.AXI2Wishbone( - axi = self.cpu.add_axi_gp_master(), - wishbone = wb_gp0, - base_address = 0x40000000) - self.bus.add_master(master=wb_gp0) #TODO memory size dependend on board variant self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"],