diff --git a/litex_boards/platforms/sqrl_xcu1525.py b/litex_boards/platforms/sqrl_xcu1525.py
index b2dbc67f3..4073ad962 100644
--- a/litex_boards/platforms/sqrl_xcu1525.py
+++ b/litex_boards/platforms/sqrl_xcu1525.py
@@ -13,20 +13,24 @@
 _io = [
     # Clk / Rst
     ("clk300", 0,
-        Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
-        Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
+        Subsignal("n", Pins("AY38")),
+        Subsignal("p", Pins("AY37")),
+        IOStandard("DIFF_SSTL12"),
     ),
     ("clk300", 1,
-        Subsignal("n", Pins("AW19"), IOStandard("DIFF_SSTL12")),
-        Subsignal("p", Pins("AW20"), IOStandard("DIFF_SSTL12")),
+        Subsignal("n", Pins("AW19")),
+        Subsignal("p", Pins("AW20")),
+        IOStandard("DIFF_SSTL12"),
     ),
     ("clk300", 2,
-        Subsignal("n", Pins("E32"), IOStandard("DIFF_SSTL12")),
-        Subsignal("p", Pins("F32"), IOStandard("DIFF_SSTL12")),
+        Subsignal("n", Pins("E32")),
+        Subsignal("p", Pins("F32")),
+        IOStandard("DIFF_SSTL12"),
     ),
     ("clk300", 3,
-        Subsignal("n", Pins("H16"), IOStandard("DIFF_SSTL12")),
-        Subsignal("p", Pins("J16"), IOStandard("DIFF_SSTL12")),
+        Subsignal("n", Pins("H16")),
+        Subsignal("p", Pins("J16")),
+        IOStandard("DIFF_SSTL12"),
     ),
 
     # Leds
@@ -259,6 +263,13 @@
     ),
 
     # QSFP-0.
+    ("qsfp0_refclk_rst", 0, Pins("AT22"), IOStandard("LVCMOS12")),
+    ("qsfp0_modskll",    0, Pins("BE16"), IOStandard("LVCMOS12")),
+    ("qsfp0_resetl",     0, Pins("BE17"), IOStandard("LVCMOS12")),
+    ("qsfp0_modprsl",    0, Pins("BE20"), IOStandard("LVCMOS12")),
+    ("qsfp0_intl",       0, Pins("BE21"), IOStandard("LVCMOS12")),
+    ("qsfp0_lpmode",     0, Pins("BD18"), IOStandard("LVCMOS12")),
+    ("qsfp0_fs",         0, Pins("AT20 AU22"), IOStandard("LVCMOS12")),
     ("qsfp0_refclk0", 0,
         Subsignal("p", Pins("M11")),
         Subsignal("n", Pins("M10")),
@@ -299,11 +310,18 @@
     ),
 
     # QSFP-1.
+    ("qsfp1_refclk_rst", 0, Pins("AU20"), IOStandard("LVCMOS12")),
+    ("qsfp1_modskll",    0, Pins("AY20"), IOStandard("LVCMOS12")),
+    ("qsfp1_resetl",     0, Pins("BC18"), IOStandard("LVCMOS12")),
+    ("qsfp1_modprsl",    0, Pins("BC19"), IOStandard("LVCMOS12")),
+    ("qsfp1_intl",       0, Pins("AV21"), IOStandard("LVCMOS12")),
+    ("qsfp1_lpmode",     0, Pins("AV22"), IOStandard("LVCMOS12")),
+    ("qsfp1_fs",         0, Pins("AR22 AU20"), IOStandard("LVCMOS12")),
     ("qsfp1_refclk0", 0,
         Subsignal("p", Pins("T11")),
         Subsignal("n", Pins("T10")),
     ),
-    ("qsfp2_refclk1", 0,
+    ("qsfp1_refclk1", 0,
         Subsignal("p", Pins("P11")),
         Subsignal("n", Pins("P10")),
     ),