From 5cdf159eea7d1b76d01e35766a19a0c90ec66e87 Mon Sep 17 00:00:00 2001
From: Chris Lattner <clattner@nondot.org>
Date: Sat, 28 Aug 2021 21:18:58 -0700
Subject: [PATCH] [ExportVerilog] Make isVerilogExpression available to the
 Prepare pass, NFC.

---
 lib/Translation/ExportVerilog/ExportVerilog.cpp        | 9 ++++++---
 lib/Translation/ExportVerilog/ExportVerilogInternals.h | 6 ++++++
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/lib/Translation/ExportVerilog/ExportVerilog.cpp b/lib/Translation/ExportVerilog/ExportVerilog.cpp
index b612ec5f2554..1c2d29691b68 100644
--- a/lib/Translation/ExportVerilog/ExportVerilog.cpp
+++ b/lib/Translation/ExportVerilog/ExportVerilog.cpp
@@ -72,7 +72,11 @@ static bool isDuplicatableNullaryExpression(Operation *op) {
   return false;
 }
 
-static bool isVerilogExpression(Operation *op) {
+/// This predicate returns true if the specified operation is considered a
+/// potentially inlinable Verilog expression.  These nodes always have a single
+/// result, but may have side effects (e.g. `sv.verbatim.expr.se`).
+/// MemoryEffects should be checked if a client cares.
+bool ExportVerilog::isVerilogExpression(Operation *op) {
   // These are SV dialect expressions.
   if (isa<ReadInOutOp>(op) || isa<ArrayIndexInOutOp>(op))
     return true;
@@ -1548,12 +1552,11 @@ void NameCollector::collectNames(Block &block) {
   // Loop over all of the results of all of the ops.  Anything that defines a
   // value needs to be noticed.
   for (auto &op : block) {
-    bool isExpr = isVerilogExpression(&op);
-
     // Instances and interface instances are handled in prepareHWModule.
     if (isa<InstanceOp, InterfaceInstanceOp>(op))
       continue;
 
+    bool isExpr = isVerilogExpression(&op);
     for (auto result : op.getResults()) {
       // If this is an expression emitted inline or unused, it doesn't need a
       // name.
diff --git a/lib/Translation/ExportVerilog/ExportVerilogInternals.h b/lib/Translation/ExportVerilog/ExportVerilogInternals.h
index 7b57f7c7c515..9880f38d6117 100644
--- a/lib/Translation/ExportVerilog/ExportVerilogInternals.h
+++ b/lib/Translation/ExportVerilog/ExportVerilogInternals.h
@@ -130,6 +130,12 @@ static inline bool isConstantExpression(Operation *op) {
   return isa<hw::ConstantOp, sv::ConstantXOp, sv::ConstantZOp>(op);
 }
 
+/// This predicate returns true if the specified operation is considered a
+/// potentially inlinable Verilog expression.  These nodes always have a single
+/// result, but may have side effects (e.g. `sv.verbatim.expr.se`).
+/// MemoryEffects should be checked if a client cares.
+bool isVerilogExpression(Operation *op);
+
 /// For each module we emit, do a prepass over the structure, pre-lowering and
 /// otherwise rewriting operations we don't want to emit.
 void prepareHWModule(Block &block, ModuleNameManager &names,