From c36806edd2dc944c26e4d0d3c1cd8b35413bdcb4 Mon Sep 17 00:00:00 2001
From: Andrew Young <youngar17@gmail.com>
Date: Thu, 10 Oct 2024 23:50:57 -0700
Subject: [PATCH] [FIRRTL] InferWidths: remove unused function argument

---
 lib/Dialect/FIRRTL/Transforms/InferWidths.cpp | 23 +++++++++----------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp b/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
index 54fca4d87ce9..3897a39efd53 100644
--- a/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
+++ b/lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
@@ -1223,7 +1223,7 @@ class InferenceMapping {
   /// Declare all the variables in the value. If the value is a ground type,
   /// there is a single variable declared.  If the value is an aggregate type,
   /// it sets up variables for each unknown width.
-  void declareVars(Value value, Location loc, bool isDerived = false);
+  void declareVars(Value value, bool isDerived = false);
 
   /// Assign the constraint expressions of the fields in the `result` argument
   /// as the max of expressions in the `rhs` and `lhs` arguments. Both fields
@@ -1307,7 +1307,7 @@ LogicalResult InferenceMapping::map(CircuitOp op) {
   for (auto module : op.getOps<FModuleOp>())
     for (auto arg : module.getArguments()) {
       solver.setCurrentContextInfo(FieldRef(arg, 0));
-      declareVars(arg, module.getLoc());
+      declareVars(arg);
     }
 
   for (auto module : op.getOps<FModuleOp>()) {
@@ -1399,16 +1399,15 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
       .Case<InvalidValueOp>([&](auto op) {
         // We must duplicate the invalid value for each use, since each use can
         // be inferred to a different width.
-        declareVars(op.getResult(), op.getLoc(), /*isDerived=*/true);
+        declareVars(op.getResult(), /*isDerived=*/true);
       })
-      .Case<WireOp, RegOp>(
-          [&](auto op) { declareVars(op.getResult(), op.getLoc()); })
+      .Case<WireOp, RegOp>([&](auto op) { declareVars(op.getResult()); })
       .Case<RegResetOp>([&](auto op) {
         // The original Scala code also constrains the reset signal to be at
         // least 1 bit wide. We don't do this here since the MLIR FIRRTL
         // dialect enforces the reset signal to be an async reset or a
         // `uint<1>`.
-        declareVars(op.getResult(), op.getLoc());
+        declareVars(op.getResult());
         // Contrain the register to be greater than or equal to the reset
         // signal.
         constrainTypes(op.getResult(), op.getResetValue());
@@ -1647,7 +1646,7 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
         // Create constraint variables for all ports.
         unsigned nonDebugPort = 0;
         for (const auto &result : llvm::enumerate(op.getResults())) {
-          declareVars(result.value(), op.getLoc());
+          declareVars(result.value());
           if (!type_isa<RefType>(result.value().getType()))
             nonDebugPort = result.index();
         }
@@ -1702,15 +1701,15 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
       })
 
       .Case<RefSendOp>([&](auto op) {
-        declareVars(op.getResult(), op.getLoc());
+        declareVars(op.getResult());
         constrainTypes(op.getResult(), op.getBase(), true);
       })
       .Case<RefResolveOp>([&](auto op) {
-        declareVars(op.getResult(), op.getLoc());
+        declareVars(op.getResult());
         constrainTypes(op.getResult(), op.getRef(), true);
       })
       .Case<RefCastOp>([&](auto op) {
-        declareVars(op.getResult(), op.getLoc());
+        declareVars(op.getResult());
         constrainTypes(op.getResult(), op.getInput(), true);
       })
       .Case<RWProbeOp>([&](auto op) {
@@ -1735,7 +1734,7 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
         for (Value result : op.getResults()) {
           auto ty = result.getType();
           if (type_isa<FIRRTLType>(ty))
-            declareVars(result, op.getLoc());
+            declareVars(result);
         }
       })
       .Default([&](auto op) {
@@ -1753,7 +1752,7 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
 
 /// Declare free variables for the type of a value, and associate the resulting
 /// set of variables with that value.
-void InferenceMapping::declareVars(Value value, Location loc, bool isDerived) {
+void InferenceMapping::declareVars(Value value, bool isDerived) {
   // Declare a variable for every unknown width in the type. If this is a Bundle
   // type or a FVector type, we will have to potentially create many variables.
   unsigned fieldID = 0;