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DNBArchImplI386.cpp
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DNBArchImplI386.cpp
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//===-- DNBArchImplI386.cpp -------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// Created by Greg Clayton on 6/25/07.
//
//===----------------------------------------------------------------------===//
#if defined(__i386__) || defined(__x86_64__)
#include <sys/cdefs.h>
#include "DNBLog.h"
#include "MacOSX/i386/DNBArchImplI386.h"
#include "MachProcess.h"
#include "MachThread.h"
extern "C" bool CPUHasAVX(); // Defined over in DNBArchImplX86_64.cpp
extern "C" bool CPUHasAVX512f(); // Defined over in DNBArchImplX86_64.cpp
#if defined(LLDB_DEBUGSERVER_RELEASE) || defined(LLDB_DEBUGSERVER_DEBUG)
enum debugState { debugStateUnknown, debugStateOff, debugStateOn };
static debugState sFPUDebugState = debugStateUnknown;
static debugState sAVXForceState = debugStateUnknown;
static bool DebugFPURegs() {
if (sFPUDebugState == debugStateUnknown) {
if (getenv("DNB_DEBUG_FPU_REGS"))
sFPUDebugState = debugStateOn;
else
sFPUDebugState = debugStateOff;
}
return (sFPUDebugState == debugStateOn);
}
static bool ForceAVXRegs() {
if (sFPUDebugState == debugStateUnknown) {
if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS"))
sAVXForceState = debugStateOn;
else
sAVXForceState = debugStateOff;
}
return (sAVXForceState == debugStateOn);
}
#define DEBUG_FPU_REGS (DebugFPURegs())
#define FORCE_AVX_REGS (ForceAVXRegs())
#else
#define DEBUG_FPU_REGS (0)
#define FORCE_AVX_REGS (0)
#endif
enum {
gpr_eax = 0,
gpr_ebx = 1,
gpr_ecx = 2,
gpr_edx = 3,
gpr_edi = 4,
gpr_esi = 5,
gpr_ebp = 6,
gpr_esp = 7,
gpr_ss = 8,
gpr_eflags = 9,
gpr_eip = 10,
gpr_cs = 11,
gpr_ds = 12,
gpr_es = 13,
gpr_fs = 14,
gpr_gs = 15,
gpr_ax,
gpr_bx,
gpr_cx,
gpr_dx,
gpr_di,
gpr_si,
gpr_bp,
gpr_sp,
gpr_ah,
gpr_bh,
gpr_ch,
gpr_dh,
gpr_al,
gpr_bl,
gpr_cl,
gpr_dl,
gpr_dil,
gpr_sil,
gpr_bpl,
gpr_spl,
k_num_gpr_regs
};
enum {
fpu_fcw,
fpu_fsw,
fpu_ftw,
fpu_fop,
fpu_ip,
fpu_cs,
fpu_dp,
fpu_ds,
fpu_mxcsr,
fpu_mxcsrmask,
fpu_stmm0,
fpu_stmm1,
fpu_stmm2,
fpu_stmm3,
fpu_stmm4,
fpu_stmm5,
fpu_stmm6,
fpu_stmm7,
fpu_xmm0,
fpu_xmm1,
fpu_xmm2,
fpu_xmm3,
fpu_xmm4,
fpu_xmm5,
fpu_xmm6,
fpu_xmm7,
fpu_ymm0,
fpu_ymm1,
fpu_ymm2,
fpu_ymm3,
fpu_ymm4,
fpu_ymm5,
fpu_ymm6,
fpu_ymm7,
fpu_k0,
fpu_k1,
fpu_k2,
fpu_k3,
fpu_k4,
fpu_k5,
fpu_k6,
fpu_k7,
fpu_zmm0,
fpu_zmm1,
fpu_zmm2,
fpu_zmm3,
fpu_zmm4,
fpu_zmm5,
fpu_zmm6,
fpu_zmm7,
k_num_fpu_regs,
// Aliases
fpu_fctrl = fpu_fcw,
fpu_fstat = fpu_fsw,
fpu_ftag = fpu_ftw,
fpu_fiseg = fpu_cs,
fpu_fioff = fpu_ip,
fpu_foseg = fpu_ds,
fpu_fooff = fpu_dp
};
enum {
exc_trapno,
exc_err,
exc_faultvaddr,
k_num_exc_regs,
};
enum {
ehframe_eax = 0,
ehframe_ecx,
ehframe_edx,
ehframe_ebx,
// On i386 Darwin the eh_frame register numbers for ebp and esp are reversed
// from DWARF.
// It's due to an ancient compiler bug in the output of the eh_frame.
// Specifically, on i386 darwin eh_frame, 4 is ebp, 5 is esp.
// On i386 darwin debug_frame (and debug_info), 4 is esp, 5 is ebp.
ehframe_ebp,
ehframe_esp,
ehframe_esi,
ehframe_edi,
ehframe_eip,
ehframe_eflags
};
enum {
dwarf_eax = 0,
dwarf_ecx,
dwarf_edx,
dwarf_ebx,
dwarf_esp,
dwarf_ebp,
dwarf_esi,
dwarf_edi,
dwarf_eip,
dwarf_eflags,
dwarf_stmm0 = 11,
dwarf_stmm1,
dwarf_stmm2,
dwarf_stmm3,
dwarf_stmm4,
dwarf_stmm5,
dwarf_stmm6,
dwarf_stmm7,
dwarf_xmm0 = 21,
dwarf_xmm1,
dwarf_xmm2,
dwarf_xmm3,
dwarf_xmm4,
dwarf_xmm5,
dwarf_xmm6,
dwarf_xmm7,
dwarf_ymm0 = dwarf_xmm0,
dwarf_ymm1 = dwarf_xmm1,
dwarf_ymm2 = dwarf_xmm2,
dwarf_ymm3 = dwarf_xmm3,
dwarf_ymm4 = dwarf_xmm4,
dwarf_ymm5 = dwarf_xmm5,
dwarf_ymm6 = dwarf_xmm6,
dwarf_ymm7 = dwarf_xmm7,
dwarf_zmm0 = dwarf_xmm0,
dwarf_zmm1 = dwarf_xmm1,
dwarf_zmm2 = dwarf_xmm2,
dwarf_zmm3 = dwarf_xmm3,
dwarf_zmm4 = dwarf_xmm4,
dwarf_zmm5 = dwarf_xmm5,
dwarf_zmm6 = dwarf_xmm6,
dwarf_zmm7 = dwarf_xmm7,
dwarf_k0 = 118,
dwarf_k1,
dwarf_k2,
dwarf_k3,
dwarf_k4,
dwarf_k5,
dwarf_k6,
dwarf_k7,
};
enum {
debugserver_eax = 0,
debugserver_ecx = 1,
debugserver_edx = 2,
debugserver_ebx = 3,
debugserver_esp = 4,
debugserver_ebp = 5,
debugserver_esi = 6,
debugserver_edi = 7,
debugserver_eip = 8,
debugserver_eflags = 9,
debugserver_cs = 10,
debugserver_ss = 11,
debugserver_ds = 12,
debugserver_es = 13,
debugserver_fs = 14,
debugserver_gs = 15,
debugserver_stmm0 = 16,
debugserver_stmm1 = 17,
debugserver_stmm2 = 18,
debugserver_stmm3 = 19,
debugserver_stmm4 = 20,
debugserver_stmm5 = 21,
debugserver_stmm6 = 22,
debugserver_stmm7 = 23,
debugserver_fctrl = 24,
debugserver_fcw = debugserver_fctrl,
debugserver_fstat = 25,
debugserver_fsw = debugserver_fstat,
debugserver_ftag = 26,
debugserver_ftw = debugserver_ftag,
debugserver_fiseg = 27,
debugserver_fpu_cs = debugserver_fiseg,
debugserver_fioff = 28,
debugserver_ip = debugserver_fioff,
debugserver_foseg = 29,
debugserver_fpu_ds = debugserver_foseg,
debugserver_fooff = 30,
debugserver_dp = debugserver_fooff,
debugserver_fop = 31,
debugserver_xmm0 = 32,
debugserver_xmm1 = 33,
debugserver_xmm2 = 34,
debugserver_xmm3 = 35,
debugserver_xmm4 = 36,
debugserver_xmm5 = 37,
debugserver_xmm6 = 38,
debugserver_xmm7 = 39,
debugserver_mxcsr = 40,
debugserver_mm0 = 41,
debugserver_mm1 = 42,
debugserver_mm2 = 43,
debugserver_mm3 = 44,
debugserver_mm4 = 45,
debugserver_mm5 = 46,
debugserver_mm6 = 47,
debugserver_mm7 = 48,
debugserver_ymm0 = debugserver_xmm0,
debugserver_ymm1 = debugserver_xmm1,
debugserver_ymm2 = debugserver_xmm2,
debugserver_ymm3 = debugserver_xmm3,
debugserver_ymm4 = debugserver_xmm4,
debugserver_ymm5 = debugserver_xmm5,
debugserver_ymm6 = debugserver_xmm6,
debugserver_ymm7 = debugserver_xmm7,
debugserver_zmm0 = debugserver_xmm0,
debugserver_zmm1 = debugserver_xmm1,
debugserver_zmm2 = debugserver_xmm2,
debugserver_zmm3 = debugserver_xmm3,
debugserver_zmm4 = debugserver_xmm4,
debugserver_zmm5 = debugserver_xmm5,
debugserver_zmm6 = debugserver_xmm6,
debugserver_zmm7 = debugserver_xmm7,
debugserver_k0 = 118,
debugserver_k1 = 119,
debugserver_k2 = 120,
debugserver_k3 = 121,
debugserver_k4 = 122,
debugserver_k5 = 123,
debugserver_k6 = 124,
debugserver_k7 = 125,
};
uint64_t DNBArchImplI386::GetPC(uint64_t failValue) {
// Get program counter
if (GetGPRState(false) == KERN_SUCCESS)
return m_state.context.gpr.__eip;
return failValue;
}
kern_return_t DNBArchImplI386::SetPC(uint64_t value) {
// Get program counter
kern_return_t err = GetGPRState(false);
if (err == KERN_SUCCESS) {
m_state.context.gpr.__eip = static_cast<uint32_t>(value);
err = SetGPRState();
}
return err == KERN_SUCCESS;
}
uint64_t DNBArchImplI386::GetSP(uint64_t failValue) {
// Get stack pointer
if (GetGPRState(false) == KERN_SUCCESS)
return m_state.context.gpr.__esp;
return failValue;
}
// Uncomment the value below to verify the values in the debugger.
//#define DEBUG_GPR_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED
//#define SET_GPR(reg) m_state.context.gpr.__##reg = gpr_##reg
kern_return_t DNBArchImplI386::GetGPRState(bool force) {
if (force || m_state.GetError(e_regSetGPR, Read)) {
#if DEBUG_GPR_VALUES
SET_GPR(eax);
SET_GPR(ebx);
SET_GPR(ecx);
SET_GPR(edx);
SET_GPR(edi);
SET_GPR(esi);
SET_GPR(ebp);
SET_GPR(esp);
SET_GPR(ss);
SET_GPR(eflags);
SET_GPR(eip);
SET_GPR(cs);
SET_GPR(ds);
SET_GPR(es);
SET_GPR(fs);
SET_GPR(gs);
m_state.SetError(e_regSetGPR, Read, 0);
#else
mach_msg_type_number_t count = e_regSetWordSizeGPR;
m_state.SetError(
e_regSetGPR, Read,
::thread_get_state(m_thread->MachPortNumber(), __i386_THREAD_STATE,
(thread_state_t)&m_state.context.gpr, &count));
#endif
}
return m_state.GetError(e_regSetGPR, Read);
}
// Uncomment the value below to verify the values in the debugger.
//#define DEBUG_FPU_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED
kern_return_t DNBArchImplI386::GetFPUState(bool force) {
if (force || m_state.GetError(e_regSetFPU, Read)) {
if (DEBUG_FPU_REGS) {
m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
*(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
*(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
m_state.context.fpu.no_avx.__fpu_ftw = 1;
m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
m_state.context.fpu.no_avx.__fpu_fop = 2;
m_state.context.fpu.no_avx.__fpu_ip = 3;
m_state.context.fpu.no_avx.__fpu_cs = 4;
m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
m_state.context.fpu.no_avx.__fpu_dp = 6;
m_state.context.fpu.no_avx.__fpu_ds = 7;
m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
for (int i = 0; i < 16; ++i) {
if (i < 10) {
m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
} else {
m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
}
m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
}
for (int i = 0; i < sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i)
m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
if (CPUHasAVX() || FORCE_AVX_REGS) {
for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1);
++i)
m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
for (int i = 0; i < 16; ++i) {
m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
}
}
if (CPUHasAVX512f() || FORCE_AVX_REGS) {
for (int i = 0; i < 8; ++i) {
m_state.context.fpu.avx512f.__fpu_k0.__opmask_reg[i] = '0';
m_state.context.fpu.avx512f.__fpu_k1.__opmask_reg[i] = '1';
m_state.context.fpu.avx512f.__fpu_k2.__opmask_reg[i] = '2';
m_state.context.fpu.avx512f.__fpu_k3.__opmask_reg[i] = '3';
m_state.context.fpu.avx512f.__fpu_k4.__opmask_reg[i] = '4';
m_state.context.fpu.avx512f.__fpu_k5.__opmask_reg[i] = '5';
m_state.context.fpu.avx512f.__fpu_k6.__opmask_reg[i] = '6';
m_state.context.fpu.avx512f.__fpu_k7.__opmask_reg[i] = '7';
}
for (int i = 0; i < 32; ++i) {
m_state.context.fpu.avx512f.__fpu_zmmh0.__ymm_reg[i] = '0';
m_state.context.fpu.avx512f.__fpu_zmmh1.__ymm_reg[i] = '1';
m_state.context.fpu.avx512f.__fpu_zmmh2.__ymm_reg[i] = '2';
m_state.context.fpu.avx512f.__fpu_zmmh3.__ymm_reg[i] = '3';
m_state.context.fpu.avx512f.__fpu_zmmh4.__ymm_reg[i] = '4';
m_state.context.fpu.avx512f.__fpu_zmmh5.__ymm_reg[i] = '5';
m_state.context.fpu.avx512f.__fpu_zmmh6.__ymm_reg[i] = '6';
m_state.context.fpu.avx512f.__fpu_zmmh7.__ymm_reg[i] = '7';
}
}
m_state.SetError(e_regSetFPU, Read, 0);
} else {
mach_msg_type_number_t count = e_regSetWordSizeFPU;
int flavor = __i386_FLOAT_STATE;
// On a machine with the AVX512 register set, a process only gets a
// full AVX512 register context after it uses the AVX512 registers;
// if the process has not yet triggered this change, trying to fetch
// the AVX512 registers will fail. Fall through to fetching the AVX
// registers.
if (CPUHasAVX512f() || FORCE_AVX_REGS) {
count = e_regSetWordSizeAVX512f;
flavor = __i386_AVX512F_STATE;
m_state.SetError(e_regSetFPU, Read,
::thread_get_state(m_thread->MachPortNumber(), flavor,
(thread_state_t)&m_state.context.fpu,
&count));
DNBLogThreadedIf(LOG_THREAD,
"::thread_get_state (0x%4.4x, %u, &fpu, %u => 0x%8.8x",
m_thread->MachPortNumber(), flavor, (uint32_t)count,
m_state.GetError(e_regSetFPU, Read));
if (m_state.GetError(e_regSetFPU, Read) == KERN_SUCCESS)
return m_state.GetError(e_regSetFPU, Read);
}
if (CPUHasAVX()) {
count = e_regSetWordSizeAVX;
flavor = __i386_AVX_STATE;
}
m_state.SetError(e_regSetFPU, Read,
::thread_get_state(m_thread->MachPortNumber(), flavor,
(thread_state_t)&m_state.context.fpu,
&count));
DNBLogThreadedIf(LOG_THREAD,
"::thread_get_state (0x%4.4x, %u, &fpu, %u => 0x%8.8x",
m_thread->MachPortNumber(), flavor, (uint32_t)count,
m_state.GetError(e_regSetFPU, Read));
}
}
return m_state.GetError(e_regSetFPU, Read);
}
kern_return_t DNBArchImplI386::GetEXCState(bool force) {
if (force || m_state.GetError(e_regSetEXC, Read)) {
mach_msg_type_number_t count = e_regSetWordSizeEXC;
m_state.SetError(
e_regSetEXC, Read,
::thread_get_state(m_thread->MachPortNumber(), __i386_EXCEPTION_STATE,
(thread_state_t)&m_state.context.exc, &count));
}
return m_state.GetError(e_regSetEXC, Read);
}
kern_return_t DNBArchImplI386::SetGPRState() {
kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
DNBLogThreadedIf(
LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u "
"(SetGPRState() for stop_count = %u)",
m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
m_state.SetError(e_regSetGPR, Write,
::thread_set_state(m_thread->MachPortNumber(),
__i386_THREAD_STATE,
(thread_state_t)&m_state.context.gpr,
e_regSetWordSizeGPR));
return m_state.GetError(e_regSetGPR, Write);
}
kern_return_t DNBArchImplI386::SetFPUState() {
if (DEBUG_FPU_REGS) {
m_state.SetError(e_regSetFPU, Write, 0);
return m_state.GetError(e_regSetFPU, Write);
} else {
int flavor = __i386_FLOAT_STATE;
mach_msg_type_number_t count = e_regSetWordSizeFPU;
if (CPUHasAVX512f() || FORCE_AVX_REGS) {
flavor = __i386_AVX512F_STATE;
count = e_regSetWordSizeAVX512f;
} else
if (CPUHasAVX()) {
flavor = __i386_AVX_STATE;
count = e_regSetWordSizeAVX;
}
m_state.SetError(e_regSetFPU, Write,
::thread_set_state(m_thread->MachPortNumber(), flavor,
(thread_state_t)&m_state.context.fpu,
count));
return m_state.GetError(e_regSetFPU, Write);
}
}
kern_return_t DNBArchImplI386::SetEXCState() {
m_state.SetError(e_regSetEXC, Write,
::thread_set_state(m_thread->MachPortNumber(),
__i386_EXCEPTION_STATE,
(thread_state_t)&m_state.context.exc,
e_regSetWordSizeEXC));
return m_state.GetError(e_regSetEXC, Write);
}
kern_return_t DNBArchImplI386::GetDBGState(bool force) {
if (force || m_state.GetError(e_regSetDBG, Read)) {
mach_msg_type_number_t count = e_regSetWordSizeDBG;
m_state.SetError(
e_regSetDBG, Read,
::thread_get_state(m_thread->MachPortNumber(), __i386_DEBUG_STATE,
(thread_state_t)&m_state.context.dbg, &count));
}
return m_state.GetError(e_regSetDBG, Read);
}
kern_return_t DNBArchImplI386::SetDBGState(bool also_set_on_task) {
m_state.SetError(e_regSetDBG, Write,
::thread_set_state(m_thread->MachPortNumber(),
__i386_DEBUG_STATE,
(thread_state_t)&m_state.context.dbg,
e_regSetWordSizeDBG));
if (also_set_on_task) {
kern_return_t kret = ::task_set_state(
m_thread->Process()->Task().TaskPort(), __i386_DEBUG_STATE,
(thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG);
if (kret != KERN_SUCCESS)
DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplI386::SetDBGState failed "
"to set debug control register state: "
"0x%8.8x.",
kret);
}
return m_state.GetError(e_regSetDBG, Write);
}
void DNBArchImplI386::ThreadWillResume() {
// Do we need to step this thread? If so, let the mach thread tell us so.
if (m_thread->IsStepping()) {
// This is the primary thread, let the arch do anything it needs
EnableHardwareSingleStep(true);
}
// Reset the debug status register, if necessary, before we resume.
kern_return_t kret = GetDBGState(false);
DNBLogThreadedIf(
LOG_WATCHPOINTS,
"DNBArchImplI386::ThreadWillResume() GetDBGState() => 0x%8.8x.", kret);
if (kret != KERN_SUCCESS)
return;
DBG &debug_state = m_state.context.dbg;
bool need_reset = false;
uint32_t i, num = NumSupportedHardwareWatchpoints();
for (i = 0; i < num; ++i)
if (IsWatchpointHit(debug_state, i))
need_reset = true;
if (need_reset) {
ClearWatchpointHits(debug_state);
kret = SetDBGState(false);
DNBLogThreadedIf(
LOG_WATCHPOINTS,
"DNBArchImplI386::ThreadWillResume() SetDBGState() => 0x%8.8x.", kret);
}
}
bool DNBArchImplI386::ThreadDidStop() {
bool success = true;
m_state.InvalidateAllRegisterStates();
// Are we stepping a single instruction?
if (GetGPRState(true) == KERN_SUCCESS) {
// We are single stepping, was this the primary thread?
if (m_thread->IsStepping()) {
// This was the primary thread, we need to clear the trace
// bit if so.
success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
} else {
// The MachThread will automatically restore the suspend count
// in ThreadDidStop(), so we don't need to do anything here if
// we weren't the primary thread the last time
}
}
return success;
}
bool DNBArchImplI386::NotifyException(MachException::Data &exc) {
switch (exc.exc_type) {
case EXC_BAD_ACCESS:
break;
case EXC_BAD_INSTRUCTION:
break;
case EXC_ARITHMETIC:
break;
case EXC_EMULATION:
break;
case EXC_SOFTWARE:
break;
case EXC_BREAKPOINT:
if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2) {
// exc_code = EXC_I386_BPT
//
nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS);
if (pc != INVALID_NUB_ADDRESS && pc > 0) {
pc -= 1;
// Check for a breakpoint at one byte prior to the current PC value
// since the PC will be just past the trap.
DNBBreakpoint *bp =
m_thread->Process()->Breakpoints().FindByAddress(pc);
if (bp) {
// Backup the PC for i386 since the trap was taken and the PC
// is at the address following the single byte trap instruction.
if (m_state.context.gpr.__eip > 0) {
m_state.context.gpr.__eip = static_cast<uint32_t>(pc);
// Write the new PC back out
SetGPRState();
}
}
return true;
}
} else if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 1) {
// exc_code = EXC_I386_SGL
//
// Check whether this corresponds to a watchpoint hit event.
// If yes, set the exc_sub_code to the data break address.
nub_addr_t addr = 0;
uint32_t hw_index = GetHardwareWatchpointHit(addr);
if (hw_index != INVALID_NUB_HW_INDEX) {
exc.exc_data[1] = addr;
// Piggyback the hw_index in the exc.data.
exc.exc_data.push_back(hw_index);
}
return true;
}
break;
case EXC_SYSCALL:
break;
case EXC_MACH_SYSCALL:
break;
case EXC_RPC_ALERT:
break;
}
return false;
}
uint32_t DNBArchImplI386::NumSupportedHardwareBreakpoints() {
// Available debug address registers: dr0, dr1, dr2, dr3.
return 4;
}
uint32_t DNBArchImplI386::NumSupportedHardwareWatchpoints() {
// Available debug address registers: dr0, dr1, dr2, dr3.
return 4;
}
static uint32_t size_and_rw_bits(nub_size_t size, bool read, bool write) {
uint32_t rw;
if (read) {
rw = 0x3; // READ or READ/WRITE
} else if (write) {
rw = 0x1; // WRITE
} else {
assert(0 && "read and write cannot both be false");
}
switch (size) {
case 1:
return rw;
case 2:
return (0x1 << 2) | rw;
case 4:
return (0x3 << 2) | rw;
case 8:
return (0x2 << 2) | rw;
}
assert(0 && "invalid size, must be one of 1, 2, 4, or 8");
return 0;
}
void DNBArchImplI386::SetWatchpoint(DBG &debug_state, uint32_t hw_index,
nub_addr_t addr, nub_size_t size, bool read,
bool write) {
// Set both dr7 (debug control register) and dri (debug address register).
// dr7{7-0} encodes the local/gloabl enable bits:
// global enable --. .-- local enable
// | |
// v v
// dr0 -> bits{1-0}
// dr1 -> bits{3-2}
// dr2 -> bits{5-4}
// dr3 -> bits{7-6}
//
// dr7{31-16} encodes the rw/len bits:
// b_x+3, b_x+2, b_x+1, b_x
// where bits{x+1, x} => rw
// 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io
// read-or-write (unused)
// and bits{x+3, x+2} => len
// 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte
//
// dr0 -> bits{19-16}
// dr1 -> bits{23-20}
// dr2 -> bits{27-24}
// dr3 -> bits{31-28}
debug_state.__dr7 |=
(1 << (2 * hw_index) |
size_and_rw_bits(size, read, write) << (16 + 4 * hw_index));
uint32_t addr_32 = addr & 0xffffffff;
switch (hw_index) {
case 0:
debug_state.__dr0 = addr_32;
break;
case 1:
debug_state.__dr1 = addr_32;
break;
case 2:
debug_state.__dr2 = addr_32;
break;
case 3:
debug_state.__dr3 = addr_32;
break;
default:
assert(0 &&
"invalid hardware register index, must be one of 0, 1, 2, or 3");
}
return;
}
void DNBArchImplI386::SetHardwareBreakpoint(DBG &debug_state, uint32_t hw_index,
nub_addr_t addr, nub_size_t size) {
// Set both dr7 (debug control register) and dri (debug address register).
// dr7{7-0} encodes the local/gloabl enable bits:
// global enable --. .-- local enable
// | |
// v v
// dr0 -> bits{1-0}
// dr1 -> bits{3-2}
// dr2 -> bits{5-4}
// dr3 -> bits{7-6}
//
// dr7{31-16} encodes the rw/len bits:
// b_x+3, b_x+2, b_x+1, b_x
// where bits{x+1, x} => rw
// 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io
// read-or-write (unused)
// and bits{x+3, x+2} => len
// 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte
//
// dr0 -> bits{19-16}
// dr1 -> bits{23-20}
// dr2 -> bits{27-24}
// dr3 -> bits{31-28}
debug_state.__dr7 |= (1 << (2 * hw_index) | 0 << (16 + 4 * hw_index));
uint32_t addr_32 = addr & 0xffffffff;
switch (hw_index) {
case 0:
debug_state.__dr0 = addr_32;
break;
case 1:
debug_state.__dr1 = addr_32;
break;
case 2:
debug_state.__dr2 = addr_32;
break;
case 3:
debug_state.__dr3 = addr_32;
break;
default:
assert(0 &&
"invalid hardware register index, must be one of 0, 1, 2, or 3");
}
return;
}
uint32_t DNBArchImplI386::EnableHardwareBreakpoint(nub_addr_t addr,
nub_size_t size,
bool also_set_on_task) {
DNBLogThreadedIf(LOG_BREAKPOINTS,
"DNBArchImplI386::EnableHardwareBreakpoint( addr = "
"0x%8.8llx, size = %llu )",
(uint64_t)addr, (uint64_t)size);
const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
// Read the debug state
kern_return_t kret = GetDBGState(false);
if (kret != KERN_SUCCESS) {
return INVALID_NUB_HW_INDEX;
}
// Check to make sure we have the needed hardware support
uint32_t i = 0;
DBG &debug_state = m_state.context.dbg;
for (i = 0; i < num_hw_breakpoints; ++i) {
if (IsWatchpointVacant(debug_state, i)) {
break;
}
}
// See if we found an available hw breakpoint slot above
if (i < num_hw_breakpoints) {
DNBLogThreadedIf(
LOG_BREAKPOINTS,
"DNBArchImplI386::EnableHardwareBreakpoint( free slot = %u )", i);
StartTransForHWP();
// Modify our local copy of the debug state, first.
SetHardwareBreakpoint(debug_state, i, addr, size);
// Now set the watch point in the inferior.
kret = SetDBGState(also_set_on_task);
DNBLogThreadedIf(LOG_BREAKPOINTS,
"DNBArchImplI386::"
"EnableHardwareBreakpoint() "
"SetDBGState() => 0x%8.8x.",
kret);
if (kret == KERN_SUCCESS) {
DNBLogThreadedIf(
LOG_BREAKPOINTS,
"DNBArchImplI386::EnableHardwareBreakpoint( enabled at slot = %u)",
i);
return i;
}
// Revert to the previous debug state voluntarily. The transaction
// coordinator knows that we have failed.
else {
m_state.context.dbg = GetDBGCheckpoint();
}
} else {
DNBLogThreadedIf(LOG_BREAKPOINTS,
"DNBArchImplI386::EnableHardwareBreakpoint(addr = "
"0x%8.8llx, size = %llu) => all hardware breakpoint "
"resources are being used.",
(uint64_t)addr, (uint64_t)size);
}
return INVALID_NUB_HW_INDEX;
}
bool DNBArchImplI386::DisableHardwareBreakpoint(uint32_t hw_index,
bool also_set_on_task) {
kern_return_t kret = GetDBGState(false);
const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
if (kret == KERN_SUCCESS) {
DBG &debug_state = m_state.context.dbg;
if (hw_index < num_hw_points &&
!IsWatchpointVacant(debug_state, hw_index)) {
StartTransForHWP();
// Modify our local copy of the debug state, first.
ClearWatchpoint(debug_state, hw_index);
// Now disable the watch point in the inferior.
kret = SetDBGState(true);
DNBLogThreadedIf(LOG_WATCHPOINTS,
"DNBArchImplI386::DisableHardwareBreakpoint( %u )",
hw_index);
if (kret == KERN_SUCCESS)
return true;
else // Revert to the previous debug state voluntarily. The transaction
// coordinator knows that we have failed.
m_state.context.dbg = GetDBGCheckpoint();
}
}
return false;
}
void DNBArchImplI386::ClearWatchpoint(DBG &debug_state, uint32_t hw_index) {
debug_state.__dr7 &= ~(3 << (2 * hw_index));
switch (hw_index) {
case 0:
debug_state.__dr0 = 0;
break;
case 1:
debug_state.__dr1 = 0;
break;
case 2:
debug_state.__dr2 = 0;
break;
case 3:
debug_state.__dr3 = 0;
break;
default:
assert(0 &&
"invalid hardware register index, must be one of 0, 1, 2, or 3");
}
return;
}
bool DNBArchImplI386::IsWatchpointVacant(const DBG &debug_state,
uint32_t hw_index) {
// Check dr7 (debug control register) for local/global enable bits:
// global enable --. .-- local enable
// | |
// v v
// dr0 -> bits{1-0}
// dr1 -> bits{3-2}
// dr2 -> bits{5-4}
// dr3 -> bits{7-6}
return (debug_state.__dr7 & (3 << (2 * hw_index))) == 0;
}
// Resets local copy of debug status register to wait for the next debug
// exception.
void DNBArchImplI386::ClearWatchpointHits(DBG &debug_state) {
// See also IsWatchpointHit().
debug_state.__dr6 = 0;
return;
}
bool DNBArchImplI386::IsWatchpointHit(const DBG &debug_state,
uint32_t hw_index) {
// Check dr6 (debug status register) whether a watchpoint hits:
// is watchpoint hit?
// |
// v
// dr0 -> bits{0}
// dr1 -> bits{1}