From 3c2eaf703e323647becbaad6a4677519ebbbb0d0 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland@gmail.com>
Date: Fri, 3 Nov 2023 08:47:40 -0700
Subject: [PATCH] remove scalable build vectors

---
 llvm/lib/CodeGen/GlobalISel/CallLowering.cpp    |  2 +-
 .../lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 17 ++++-------------
 2 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 158049baa8f570..2527b143128967 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -473,7 +473,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
   } else {
     // Vector was split, and elements promoted to a wider type.
     // FIXME: Should handle floating point promotions.
-    LLT BVType = LLT::vector(LLTy.getElementCount(), PartLLT);
+    LLT BVType = LLT::fixed_vector(LLTy.getNumElements(), PartLLT);
     auto BV = B.buildBuildVector(BVType, Regs);
     B.buildTrunc(OrigRegs[0], BV);
   }
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index bc50322293f0ad..80e9c08e850b68 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -1281,19 +1281,10 @@ MachineIRBuilder::buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
                                  SrcOps[0].getLLTTy(*getMRI());
                         }) &&
            "type mismatch in input list");
-    if (DstOps[0].getLLTTy(*getMRI()).isScalable())
-      assert((TypeSize::ScalarTy)SrcOps.size() *
-                     SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() >=
-                 DstOps[0]
-                     .getLLTTy(*getMRI())
-                     .getSizeInBits()
-                     .getKnownMinValue() &&
-             "input scalars does not cover the output vector register");
-    else
-      assert((TypeSize::ScalarTy)SrcOps.size() *
-                     SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
-                 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
-             "input scalars do not exactly cover the output vector register");
+    assert((TypeSize::ScalarTy)SrcOps.size() *
+                   SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
+               DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
+           "input scalars do not exactly cover the output vector register");
     break;
   }
   case TargetOpcode::G_BUILD_VECTOR_TRUNC: {