From 73b8074e68e4b01bd7cb0dd2372af5adc2e89231 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Fri, 20 Sep 2024 13:45:04 +0100
Subject: [PATCH] [AMDGPU] Do not use APInt for simple 64-bit arithmetic. NFC.
 (#109414)

---
 llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp             | 2 +-
 .../lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 6 ++----
 .../lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 6 ++----
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp                    | 8 ++++----
 4 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index d186ef896ea406..d3d5bc924525fc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -1598,7 +1598,7 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
       !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
       !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
     uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
-                    APInt::getAllOnes(32).getZExtValue(); // Size
+                    maskTrailingOnes<uint64_t>(32); // Size
     SDLoc DL(Addr);
 
     const SITargetLowering& Lowering =
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 6c2a6643e67c76..2f5eba47afc27f 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -106,10 +106,8 @@ static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,
                                        const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
 
-  // Our branches take a simm16, but we need two extra bits to account for the
-  // factor of 4.
-  APInt SignedOffset(18, Imm * 4, true);
-  int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
+  // Our branches take a simm16.
+  int64_t Offset = SignExtend64<16>(Imm) * 4 + 4 + Addr;
 
   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))
     return MCDisassembler::Success;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index 37eb0b57fb1537..8044810fdab944 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -130,10 +130,8 @@ class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
       return false;
 
     int64_t Imm = Inst.getOperand(0).getImm();
-    // Our branches take a simm16, but we need two extra bits to account for
-    // the factor of 4.
-    APInt SignedOffset(18, Imm * 4, true);
-    Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
+    // Our branches take a simm16.
+    Target = SignExtend64<16>(Imm) * 4 + Addr + Size;
     return true;
   }
 };
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 163cf42fc4474d..97e8b08270d615 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3401,13 +3401,13 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
     case AMDGPU::sub1:
       return Hi_32(Imm);
     case AMDGPU::lo16:
-      return APInt(16, Imm).getSExtValue();
+      return SignExtend64<16>(Imm);
     case AMDGPU::hi16:
-      return APInt(32, Imm).ashr(16).getSExtValue();
+      return SignExtend64<16>(Imm >> 16);
     case AMDGPU::sub1_lo16:
-      return APInt(16, Hi_32(Imm)).getSExtValue();
+      return SignExtend64<16>(Imm >> 32);
     case AMDGPU::sub1_hi16:
-      return APInt(32, Hi_32(Imm)).ashr(16).getSExtValue();
+      return SignExtend64<16>(Imm >> 48);
     }
   };