From f2d5a1cc010856c635ab39c7f984988f722f0b62 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland@gmail.com>
Date: Wed, 2 Oct 2024 10:59:39 -0700
Subject: [PATCH] fixup! use MRI from RISCVInstructionSelector

---
 llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 815b2e58c012cb8..2b45d3b3ba640bb 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -383,8 +383,6 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
 
 InstructionSelector::ComplexRendererFns
 RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
-  MachineRegisterInfo &MRI =
-      Root.getParent()->getParent()->getParent()->getRegInfo();
   assert(Root.isReg() && "Expected operand to be a Register");
   MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());