diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 364d7e9855e8cf5..f41cf3b32f74e28 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -1551,7 +1551,8 @@ class AnnotatingParser { // Case D. if (Keywords.isVerilogIdentifier(*Prev) && PrevPrev->is(tok::comma)) { const FormatToken *PrevParen = PrevPrev->getPreviousNonComment(); - if (PrevParen->is(tok::r_paren) && PrevParen->MatchingParen && + if (PrevParen && PrevParen->is(tok::r_paren) && + PrevParen->MatchingParen && PrevParen->MatchingParen->is(TT_VerilogInstancePortLParen)) { return true; } diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp index fbaf289fbc4d6df..49d276fc78d81b4 100644 --- a/clang/unittests/Format/FormatTestVerilog.cpp +++ b/clang/unittests/Format/FormatTestVerilog.cpp @@ -964,6 +964,7 @@ TEST_F(FormatTestVerilog, Instantiation) { " .qbar(out1),\n" " .clear(in1),\n" " .preset(in2));"); + verifyNoCrash(", ff1();"); // With breaking between instance ports disabled. auto Style = getDefaultStyle(); Style.VerilogBreakBetweenInstancePorts = false;