Zig builtin

[kassane]

Tip:

+ add setfeature - remove setfeature

e.g.:

Esp32-C3 [RV32IMC]: -mcpu=baseline_rv32-a-d-f
Allwinner D1 [RV64GCV]: -mcpu=baseline_rv64+experimental_v

Show builtin

Command: zig build-obj -target riscv32-freestanding -mcpu=baseline_rv32 --show-builtin

Baseline_rv32:

const std = @import("std");
/// Zig version. When writing code that supports multiple versions of Zig, prefer
/// feature detection (i.e. with `@hasDecl` or `@hasField`) over version checks.
pub const zig_version = std.SemanticVersion.parse("0.10.0-dev.2376+837352078") catch unreachable;
pub const zig_backend = std.builtin.CompilerBackend.stage1;
/// Temporary until self-hosted supports the `cpu.arch` value.
pub const stage2_arch: std.Target.Cpu.Arch = .riscv32;

pub const output_mode = std.builtin.OutputMode.Obj;
pub const link_mode = std.builtin.LinkMode.Static;
pub const is_test = false;
pub const single_threaded = false;
pub const abi = std.Target.Abi.eabi;
pub const cpu: std.Target.Cpu = .{
    .arch = .riscv32,
    .model = &std.Target.riscv.cpu.baseline_rv32,
    .features = std.Target.riscv.featureSet(&[_]std.Target.riscv.Feature{
        .a,
        .c,
        .d,
        .f,
        .m,
    }),
};
pub const os = std.Target.Os{
    .tag = .freestanding,
    .version_range = .{ .none = {} }
};
pub const target = std.Target{
    .cpu = cpu,
    .os = os,
    .abi = abi,
};
pub const object_format = std.Target.ObjectFormat.elf;
pub const mode = std.builtin.Mode.Debug;
pub const link_libc = false;
pub const link_libcpp = false;
pub const have_error_return_tracing = true;
pub const valgrind_support = false;
pub const sanitize_thread = false;
pub const position_independent_code = false;
pub const position_independent_executable = false;
pub const strip_debug_info = false;
pub const code_model = std.builtin.CodeModel.default;

Remove d Feature:

Command: zig build-obj -target riscv32-freestanding -mcpu=baseline_rv32-d --show-builtin

const std = @import("std");
/// Zig version. When writing code that supports multiple versions of Zig, prefer
/// feature detection (i.e. with `@hasDecl` or `@hasField`) over version checks.
pub const zig_version = std.SemanticVersion.parse("0.10.0-dev.2376+837352078") catch unreachable;
pub const zig_backend = std.builtin.CompilerBackend.stage1;
/// Temporary until self-hosted supports the `cpu.arch` value.
pub const stage2_arch: std.Target.Cpu.Arch = .riscv32;

pub const output_mode = std.builtin.OutputMode.Obj;
pub const link_mode = std.builtin.LinkMode.Static;
pub const is_test = false;
pub const single_threaded = false;
pub const abi = std.Target.Abi.eabi;
pub const cpu: std.Target.Cpu = .{
    .arch = .riscv32,
    .model = &std.Target.riscv.cpu.baseline_rv32,
    .features = std.Target.riscv.featureSet(&[_]std.Target.riscv.Feature{
        .a,
        .c,
        .f,
        .m,
    }),
};
pub const os = std.Target.Os{
    .tag = .freestanding,
    .version_range = .{ .none = {} }
};
pub const target = std.Target{
    .cpu = cpu,
    .os = os,
    .abi = abi,
};
pub const object_format = std.Target.ObjectFormat.elf;
pub const mode = std.builtin.Mode.Debug;
pub const link_libc = false;
pub const link_libcpp = false;
pub const have_error_return_tracing = true;
pub const valgrind_support = false;
pub const sanitize_thread = false;
pub const position_independent_code = false;
pub const position_independent_executable = false;
pub const strip_debug_info = false;
pub const code_model = std.builtin.CodeModel.default;

Feature list

Error command: zig build-obj -target riscv32-freestanding -mcpu=baseline_rv32+ --show-builtin

info: Available CPU features for architecture 'riscv32':
 64bit: Implements RV64
 a: 'A' (Atomic Instructions)
 c: 'C' (Compressed Instructions)
 d: 'D' (Double-Precision Floating-Point)
 e: Implements RV32E (provides 16 rather than 32 GPRs)
 experimental_b: 'B' (Bit Manipulation Instructions)
 experimental_v: 'V' (Vector Instructions)
 experimental_zba: 'Zba' (Address calculation 'B' Instructions)
 experimental_zbb: 'Zbb' (Base 'B' Instructions)
 experimental_zbc: 'Zbc' (Carry-Less 'B' Instructions)
 experimental_zbe: 'Zbe' (Extract-Deposit 'B' Instructions)
 experimental_zbf: 'Zbf' (Bit-Field 'B' Instructions)
 experimental_zbm: 'Zbm' (Matrix 'B' Instructions)
 experimental_zbp: 'Zbp' (Permutation 'B' Instructions)
 experimental_zbproposedc: 'Zbproposedc' (Proposed Compressed 'B' Instructions)
 experimental_zbr: 'Zbr' (Polynomial Reduction 'B' Instructions)
 experimental_zbs: 'Zbs' (Single-Bit 'B' Instructions)
 experimental_zbt: 'Zbt' (Ternary 'B' Instructions)
 experimental_zfh: 'Zfh' (Half-Precision Floating-Point)
 experimental_zvamo: 'Zvamo' (Vector AMO Operations)
 experimental_zvlsseg: 'Zvlsseg' (Vector segment load/store instructions)
 f: 'F' (Single-Precision Floating-Point)
 m: 'M' (Integer Multiplication and Division)
 no_rvc_hints: Disable RVC Hint Instructions.
 relax: Enable Linker relaxation.
 reserve_x1: Reserve X1
 reserve_x10: Reserve X10
 reserve_x11: Reserve X11
 reserve_x12: Reserve X12
 reserve_x13: Reserve X13
 reserve_x14: Reserve X14
 reserve_x15: Reserve X15
 reserve_x16: Reserve X16
 reserve_x17: Reserve X17
 reserve_x18: Reserve X18
 reserve_x19: Reserve X19
 reserve_x2: Reserve X2
 reserve_x20: Reserve X20
 reserve_x21: Reserve X21
 reserve_x22: Reserve X22
 reserve_x23: Reserve X23
 reserve_x24: Reserve X24
 reserve_x25: Reserve X25
 reserve_x26: Reserve X26
 reserve_x27: Reserve X27
 reserve_x28: Reserve X28
 reserve_x29: Reserve X29
 reserve_x3: Reserve X3
 reserve_x30: Reserve X30
 reserve_x31: Reserve X31
 reserve_x4: Reserve X4
 reserve_x5: Reserve X5
 reserve_x6: Reserve X6
 reserve_x7: Reserve X7
 reserve_x8: Reserve X8
 reserve_x9: Reserve X9
 save_restore: Enable save/restore.

error: Unknown CPU feature: ''

[lupyuen]

That's super helpful, thanks! :-)

[kassane]

That's super helpful, thanks! :-)

😁 Nice! Any other questions just ask.
If you find any bugs in the toolchain, please contribute to the zig project (PR & issues) there are few experiments with risc-v.

I don't know if you saw this:
BL602 - SVD to Zig

[lupyuen]

I have updated the doc. Thanks! :-)

https://github.com/lupyuen/zig-bl602-nuttx#zig-target

##  Compile the Zig App for BL602 (RV32IMACF with Hardware Floating-Point)
zig build-obj \
    -target riscv32-freestanding-none \
    -mcpu=baseline_rv32-d \
    hello_zig_main.zig