OK. board_late_initialize: revision=0x5720, chip_id=0x30e

lupyuen2 · Aug 31, 2023 · 09e2ee0 · 09e2ee0
1 parent 00a8cc4
commit 09e2ee0
Showing 1 changed file with 12 additions and 0 deletions.
diff --git a/boards/risc-v/jh7110/star64/src/jh7110_appinit.c b/boards/risc-v/jh7110/star64/src/jh7110_appinit.c
@@ -192,19 +192,27 @@ void board_late_initialize(void)
   modifyreg32(0x130200f8, 0, 1 << 31);
   modifyreg32(0x130200fc, 0, 1 << 31);
 
+  up_mdelay(50);////
+
   // Deassert the Resets for Video Output / Display Subsystem
   // Software RESET 1 Address Selector: Offset 0x2fc
   // Clear Bit 11: rstn_u0_dom_vout_top_rstn_dom_vout_top_rstn_vout_src
   modifyreg32(0x130202fc, 1 << 11, 0);  // Addr, Clear Bits, Set Bits
 
+  up_mdelay(50);////
+
   // SYSCRG RESET Status 0: Offset 0x308
   // Clear Bit 26: rstn_u0_sft7110_noc_bus_reset_disp_axi_n
   modifyreg32(0x13020308, 1 << 26, 0);  // Addr, Clear Bits, Set Bits
 
+  up_mdelay(50);////
+
   // Verify that Video Output / Display Subsystem is up
   val = getreg32(0x295C0000);
   DEBUGASSERT(val == 4);
 
+  up_mdelay(50);////
+
   // Enable the Clocks for DC8200 Display Controller (HDMI)
   modifyreg32(0x295C0010, 0, 1 << 31);  // Addr, Clear Bits, Set Bits
   modifyreg32(0x295C0014, 0, 1 << 31);
@@ -215,13 +223,17 @@ void board_late_initialize(void)
   modifyreg32(0x295C0040, 0, 1 << 31);
   modifyreg32(0x295C0044, 0, 1 << 31);
 
+  up_mdelay(50);////
+
   // Deassert the Resets for DC8200 Display Controller (HDMI)
   modifyreg32(
     0x295C0048,  // Addr
     (1 << 0) | (1 << 1) | (1 << 2) | (1 << 9),  // Clear Bits
     0  // Set Bits
   );
 
+  up_mdelay(50);////
+
   // Verify that Hardware Revision and Chip ID are non-zero
   uint32_t revision = getreg32(0x29400024);
   uint32_t chip_id = getreg32(0x29400030);