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3U ADC (Novo) tests & rev1 errata #226

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18 of 33 tasks
gkasprow opened this issue Jun 30, 2017 · 235 comments
Closed
18 of 33 tasks

3U ADC (Novo) tests & rev1 errata #226

gkasprow opened this issue Jun 30, 2017 · 235 comments

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@gkasprow
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gkasprow commented Jun 30, 2017

Revision 1 errata:

  • invert C45, C46, C43
  • add Shottky diodes at the LDO outputs
  • 3mm higher EMC shield on PSU
  • termination LEDs between BNCs
  • connect IC25 pin 5 with pin 8 - now SHDN pin is floating
  • zero index everything
  • add GND and i2C testpoints
  • add front panel handle fixing holes
  • swap BNC connector GND terminals
  • either add ~2mm plastic washers on BNC barrel behind front panel or move BNC connectors 2mm towards FP. This is to enable fixing the BNC connectors to the panel using the screws.
  • Please remove the annotation "This module connects to Kasli ..." and replace it with something like "EEM connector: IO are LVDS, I2C is 3V3 LVCMOS, P3V3_MP up to 20mA, P12V up to 1A."
  • run PI and thermal simulations
  • ADC range not +-10V (reference gain is 2.5 not 2)
  • Consider driving the ADC from a lower impedance. Otherwise, the DC accuracy will depend on sample rate, which is nasty!
  • increase PSU shield height
  • Remove schematic annotation "please make a list of IC names and functions in corner of schematic for easier reading"
  • Make the power budget a nice one like on the ADC/Kasli/Urukil (e.g. show total power dissipation and current draw from the +12V rail).
  • Update the annotation about the EEM connector to match the one on Kasli
  • Label the EEM connector EEM0 on the silk screen and on the schematic
  • @gkasprow Didn't we agree do do the ADC power supplies the same way as the DAC? This isn't so important, as the power dissipation is lower, but we might as well be consistent between the boards...
  • add 100nF caps at the LDO outputs
  • Silk + schematic + panel should be "v1.x" not "rev1.x"
  • add BNC nuts to the BOM

Tests to perform. @gkasprow Feel free to skip any of these tests if they're hard to do/you think they're not worth it!

  • When you make these measurements, please quote/tabulate relevant numbers (e.g. give NSB in nv/rtHz for noise measurements) as well as giving plots!
  • SNR for all gain settings
  • spectrum with full scale and mid scale input signal. It will show us power supply performance.
  • CMRR
  • channel isolation
  • susceptibility to external EMI sources (i.e. neighbouring boards). I will test it with EMC equipment.
  • gain switching.
  • Time-domain response to a FS step (checks slew-rate etc)
  • DC cross-talk
  • If easy, check the board's temp co (say, for 0V and max V inputs, for G=1 and G=100). If this will take too long, feel free to skip it as we can trust the data sheets.
  • Gain versus input signal frequency
  • Harmonics for some sensible input. Say, 25kHz close to full-scale.

ADC boards arrived
3u adc top

@hartytp
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hartytp commented Jul 1, 2017

@gkasprow What tests do you plan to do on this board? If we're going to make a new version with a different ADC, I don't think we need to test this version too carefully.

@hartytp
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hartytp commented Jul 1, 2017

Sounds like a good plan, thanks Greg!

@gkasprow
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gkasprow commented Jul 7, 2017

ADC with shielding boxes
2017-07-07 10 31 40

@gkasprow
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Today I powered it on. The DC/DC converter generates +3/ -2.5V without load (output chokes removed). Will debug it next week.

@gkasprow gkasprow changed the title 3U ADC (Novogorny) tests 3U ADC (Novogorny) tests & rev1 errata Jul 14, 2017
@gkasprow
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power supply works. There were two tantalium capacitor with wrong polarisation.

@gkasprow
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I managed to communicate with devkit and acquire samples but it works only for DC.
I ordered DC890 interface to do AC characterisation. Now switching to Zotino debugging.

@hartytp
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hartytp commented Jul 18, 2017

@gkasprow Thanks for the update. What tests do you want to do before you send us some of the ADC/DAC the boards?

@hartytp
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hartytp commented Jul 18, 2017

(I'm keen to give M-Labs a DAC board asap so that they can write the software for it.)

@gkasprow
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I'd like to test ADC AC performance to if see if gain change works and do multichannel tests at high SPI rate.
DAC supply works correctly. Temperature regulator has some issues with stability - PI controller needs some component value optimisation. Once I connect to the devkit and check functionality, I would be able to send both boards to Mlabs.
Later on I will continue tests when Mlabs ARTIQ support gets ready

@jordens
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jordens commented Jul 18, 2017

In the absence of Kasli, and metlino we'll have to develop with the vhdci carrier and fmc-vhdci and kc705. Do we have them or could you send some as well?

@gkasprow
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Recently batch of fmc-vhdci boards were produced for Joe and shipped to US. There were more boards produced and are kept on stock so you can buy them.
Pls contact @mmroz88

@jbqubit
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jbqubit commented Jul 18, 2017

@jordens I can send you one of the fmc-vhdci I ordered. What address should I use?

@hartytp
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hartytp commented Jul 18, 2017

Thanks @jbqubit

@hartytp
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hartytp commented Jul 18, 2017

@jbqubit Do you have a spare VHDCI_Carrier for @jordens card as well?

@jbqubit
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jbqubit commented Jul 18, 2017

I do not have a spare VHDCI_carrier.

@sbourdeauducq
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Please send the adapter(s) to M-Labs HK, we'll also need them for Zotino.

M-Labs Limited
Workshop 15B 6/F Block B1
17 Ko Fai Road, Yau Tong
Hong Kong
+852-59362721

@jordens
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jordens commented Jul 19, 2017

Might be better to send them to QUARTIQ.

@gkasprow
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gkasprow commented Jul 19, 2017 via email

@hartytp
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hartytp commented Jul 19, 2017

Thanks @gkasprow. NB this has a slightly different pin-out to the new version, due the the reallocating of cc pins...

@jbqubit
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jbqubit commented Jul 19, 2017

@jordens @sbourdeauducq Am I sending qty 1 fmc-vhdci to Hong Kong or Germany?

@jordens
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jordens commented Jul 19, 2017

one to HK.

@jbqubit
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jbqubit commented Jul 19, 2017

One unit shipping to HK today. @sbourdeauducq you'll need a VHDCI cable. #234

@gkasprow
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gkasprow commented Jul 22, 2017

Supply works fine. Just reversed caps caused all the problems. DAC died on one of the boards probably due to reverse biasing. Shottky diodes needed at the LDO outputs to prevent such situation.

@jbqubit
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jbqubit commented Jul 24, 2017

@jordens For reference, what is mailing address of QUARTIQ?

@hartytp
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hartytp commented Jul 31, 2017

@gkasprow What's the status of the tests on the ADC/DAC boards? When do you anticipate being ready to ship the prototypes to us/M-Labs?

@gkasprow
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gkasprow commented Aug 1, 2017 via email

@hartytp
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hartytp commented Aug 1, 2017

Great! Can you also ship us a couple of each to test out, please?

@gkasprow
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gkasprow commented Aug 1, 2017

Once I test them I will do so.

@gkasprow
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@jordens @hartytp I removed the CMC . Here is the plot.
100Hz 10Vpp x1 50R 1.2nF no CNC.txt

@hartytp
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hartytp commented Sep 27, 2017

From a quick look at the text file, that doesn't look any better...

@gkasprow
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It's worth simulating pulse response in SPICE

@hartytp
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hartytp commented Sep 27, 2017

Yes, that sounds like a good idea.

@gkasprow
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@hartytp I simulated it:
obraz

@gkasprow
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After 10us we have 4.998 at the output and 5.017 at the input

@hartytp
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hartytp commented Sep 27, 2017

Are you sure there isn't something funny going on with the signal generator you're using for this measurement?

@gkasprow
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It seems so:
tek00062

@dhslichter
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Yikes! Well, at least that clears up some of the mystery...

@hartytp
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hartytp commented Sep 27, 2017

Good catch @gkasprow. Can you remeasure the step response using a better signal generator, using the RC components on the schematic. If that looks better, we can finish testing of the board.

@hartytp
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hartytp commented Sep 27, 2017

@gkasprow I added your cross-talk measurements to the Wiki. Thanks for taking that data!

@hartytp
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hartytp commented Sep 29, 2017

@gkasprow I'd like to finish testing this board asap, so we can move on to other things like the RF PA.

If you can do it quickly, please could you remeasure the step response with a faster-settling source. If that's a problem/will take too much time, please ship the boards as they are and we'll do this test ourselves.

Either way, let me now what you want to do.

@gkasprow
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gkasprow commented Oct 4, 2017

@hartytp I brought yet another DDS generator - it is powerfull Tektronix AWG5002B. And the square wave it generates is not better than previous one. So it does not make sense to do any tests with these. Probably simple TTL gate would give better shape, but I don't have time to experiment with it.

@hartytp
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hartytp commented Oct 4, 2017

@gkasprow Two suggestions:

  1. Can you do this measurement with G=10? That way you need a 1Vpp signal, which might be easier for your generator. The InAmp settling time for G=10 should be slower than for G=1, so this is a good test anyway.

  2. If that doesn't work, can you measure the large-signal bandwidth using a sinusoid, please? That will check that the settling time is okay.

Otherwise, ship us the boards, and we will make this measurement.

@gkasprow
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gkasprow commented Oct 4, 2017

@dhslichter
100Hz 1Vpp x10.txt

I measured large signal gain:
at 1Vpp and G=10 (-8.1dBFS) : 213kHz (-6dB)
at 2Vpp and G=10 (-1.2dBFS) : 212kHz (-6dB)
at 10Vpp and G=1 (-8.1dBFS) : 214kHz (-6dB)
This is measurement with original RC filter values to be consistent with previous measurements.

@gkasprow
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gkasprow commented Oct 4, 2017

@dhslichter do you want me to apply 1.2nF and 51Ohm filter to all channels or leave as it is now?

@hartytp
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hartytp commented Oct 4, 2017

@gkasprow Great! So the -6dB bandwidth is unchanged for full-scale signals. In that case, the settling-time should be absolutely fine.

Let's close testing for this board here. If that works okay, I'm happy to leave the original RC values in this version -- the next revision will have different driver OpAmp and a different ADC, so there is no point carefully testing drive impedances in this revision.

@hartytp
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hartytp commented Oct 4, 2017

Thanks again for all the hard work on this Greg, I'm really happy with the performance of this board! It's also good to know that this will be okay for Allaki etc.

@gkasprow
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gkasprow commented Oct 4, 2017

measurements for 1nF and 51Ohm RC filter:
100Hz 1Vpp x10 50R 1.2nF.txt

at 1Vpp and G=10 (-7.76dBFS) : 382kHz (-6dB)
at 2.2Vpp and G=10 (-0.9dBFS) : 383kHz (-6dB)
at 10Vpp and G=1 (-7.7dBFS) : 383kHz (-6dB)

@gkasprow
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gkasprow commented Oct 4, 2017

@hartytp btw, Allakis are already assembled, will get them tomorrow.

@hartytp
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hartytp commented Oct 4, 2017

@gkasprow Thanks for the data, good to know that 51R and 1nF works as well.

That's not directly comparable to our previous measurements, since it replaces the 250kHz LPF with a 3MHz LPF. This will have the effect of increasing the ADC noise floor a bit. Let's stick with the original RC components for this revision, and rethink them in the next revision.

NB however: because of the relatively high ADC drive impedance, the DC accuracy will depend on the ADC sample rate, which is a bit nasty! Definitely something to fix next time around.

@hartytp
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hartytp commented Oct 4, 2017

@hartytp btw, Allakis are already assembled, will get them tomorrow.

Great!

@jordens
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jordens commented Oct 4, 2017

If anyone wants to measure the settling time properly, there are a bunch of classic app notes describing different approaches.

@hartytp
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hartytp commented Oct 4, 2017

If anyone wants to measure the settling time properly, there are a bunch of classic app notes describing different approaches.

Sure, it's not that hard -- particularly since this board only has a couple of hundred kHz BW and is only 16-bit. It can also be done with a couple of transistors and a decent voltage source.

Anyway, the data we have is sufficient to show that Novo works to specification, so we can leave further data taking to interested users...

@hartytp
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hartytp commented Oct 4, 2017

Wiki updated.

@dhslichter
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@gkasprow no need to do any additional measurements for my benefit.

@hartytp hartytp mentioned this issue Oct 27, 2017
9 tasks
@jordens jordens added this to the Novo v2.0 milestone Nov 14, 2017
@hartytp hartytp closed this as completed Nov 16, 2017
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