-
Notifications
You must be signed in to change notification settings - Fork 0
/
ALL_CODES.txt
361 lines (262 loc) · 7.47 KB
/
ALL_CODES.txt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
XOR_GATE****************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_gate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
xor_out : out STD_LOGIC);
end xor_gate;
architecture Behavioral of xor_gate is
begin
xor_out <= A xor B;
end Behavioral;
AND_GATE*********************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_gate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
and_out : out STD_LOGIC);
end and_gate;
architecture Behavioral of and_gate is
begin
and_out <= A and B;
end Behavioral;
OR_GATE**********************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
or_out : out STD_LOGIC);
end or_gate;
architecture Behavioral of or_gate is
begin
or_out <= A or B;
end Behavioral;
ONE_BIT_FULL_ADDER*************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity one_bit_adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end one_bit_adder;
architecture Structural of one_bit_adder is
component xor_gate is
port( A : in STD_LOGIC;
B : in STD_LOGIC;
xor_out : out STD_LOGIC);
end component;
component and_gate is
port( A : in STD_LOGIC;
B : in STD_LOGIC;
and_out : out STD_LOGIC);
end component;
component or_gate is
port( A : in STD_LOGIC;
B : in STD_LOGIC;
or_out : out STD_LOGIC);
end component;
signal s1,s2,s3 :STD_LOGIC;
begin
xor1: xor_gate port map ( A , B , s1 );
xor2: xor_gate port map ( s1 , Cin , S );
and1: and_gate port map ( s1 , Cin , s2 );
and2: and_gate port map ( A , B , s3 );
or1: or_gate port map ( s2 , s3 , Cout);
end Structural;
ONE_BIT_FULL_ADDER_SIMULATION*****************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity one_bit_adder_simu is
-- Port ( );
end one_bit_adder_simu;
architecture Behavioral of one_bit_adder_simu is
component one_bit_adder is
port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal A , B , Cin : STD_LOGIC := '0';
signal S , Cout : STD_LOGIC := '0';
begin
uut: one_bit_adder port map ( A=>A , B=>B , Cin=>Cin , S=>S , Cout=>Cout );
process
begin
A <= '0';
B <= '0';
Cin <= '0';
wait for 100ns;
A <= '0';
B <= '0';
Cin <= '1';
wait for 100ns;
A <= '0';
B <= '1';
Cin <= '0';
wait for 100ns;
A <= '0';
B <= '1';
Cin <= '1';
wait for 100ns;
A <= '1';
B <= '0';
Cin <= '0';
wait for 100ns;
A <= '1';
B <= '0';
Cin <= '1';
wait for 100ns;
A <= '1';
B <= '1';
Cin <= '0';
wait for 100ns;
A <= '1';
B <= '1';
Cin <= '1';
wait for 100ns;
end process;
end Behavioral;
FOUR_BIT_FULL_ADDER*************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_bit_adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end four_bit_adder;
architecture Structural of four_bit_adder is
component one_bit_adder is
port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal s1,s2,s3,s4 : STD_LOGIC;
begin
xor1: one_bit_adder port map ( A(0) , B(0) , Cin , S(0) , s1 );
xor2: one_bit_adder port map ( A(1) , B(1) , s1 , S(1) , s2 );
xor3: one_bit_adder port map ( A(2) , B(2) , s2 , S(2) , s3 );
xor4: one_bit_adder port map ( A(3) , B(3) , s3 , S(3) ,Cout );
end Structural;
FOUR_BIT_FULL_ADDER_SIMULATION****************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_bit_adder_simu is
-- Port ( );
end four_bit_adder_simu;
architecture Behavioral of four_bit_adder_simu is
component four_bit_adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end component;
signal A , B , S : STD_LOGIC_VECTOR (3 downto 0) := "0000" ;
signal Cin ,Cout : STD_LOGIC := '0';
begin
uut: four_bit_adder port map ( A=>A , B=>B , Cin=>Cin , S=>S , Cout=>Cout );
process
begin
A <= "0000";
B <= "0000";
Cin <= '0';
wait for 100ns;
A <= "1010";
B <= "0011";
Cin <= '1';
wait for 100ns;
A <= "1100";
B <= "0011";
Cin <= '0';
wait for 100ns;
A <= "0101";
B <= "0000";
Cin <= '1';
wait for 100ns;
A <= "1001";
B <= "0111";
Cin <= '0';
wait for 100ns;
A <= "1101";
B <= "0010";
Cin <= '0';
wait for 100ns;
A <= "1101";
B <= "1110";
Cin <= '1';
wait for 100ns;
A <= "1111";
B <= "1111";
Cin <= '1';
wait for 100ns;
end process;
end Behavioral;
2*1 mux ********************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity two_cross_one_MUX is
Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
sel : in STD_LOGIC;
output : out STD_LOGIC);
end two_cross_one_MUX;
architecture Structural of two_cross_one_MUX is
component and_gate is
port(A : in STD_LOGIC;
B : in STD_LOGIC;
and_out : out STD_LOGIC);
end component;
component or_gate is
port( A : in STD_LOGIC;
B : in STD_LOGIC;
or_out : out STD_LOGIC);
end component;
component not_gate is
port( A : in STD_LOGIC;
not_out : out STD_LOGIC);
end component;
signal s1,s2,s3 :STD_LOGIC;
begin
not1: not_gate port map ( sel , s1 );
and1: and_gate port map ( input(0) , s1 , s2 );
and2: and_gate port map ( input(1) , sel , s3 );
or1: or_gate port map ( s2 , s3 , output );
end Structural;
2*1 simu********************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity two_cross_one_mux_simu is
-- Port ( );
end two_cross_one_mux_simu;
architecture Behavioral of two_cross_one_mux_simu is
component two_cross_one_MUX
Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
sel : in STD_LOGIC;
output : out STD_LOGIC);
end component;
signal input : STD_LOGIC_VECTOR (1 downto 0) := "00;
signal sel,output : STD_LOGIC := '0';
begin
uut: two_cross_one_MUX port map ( input=>input , sel => sel , output => output );
process
begin
input <= "00";
sel <= '0';
wait for 100ns;
input <= "10";
sel <= '1';
wait for 100ns;
input <= "10";
sel <= '0';
wait for 100ns;
end process
end Behavioral;