From 0f0682d00c3961afd1f492ae55f180c5b5502767 Mon Sep 17 00:00:00 2001 From: Masahiro Masuda Date: Thu, 7 Apr 2022 08:17:43 +0900 Subject: [PATCH] rename vnni.py to x86.py --- python/tvm/tir/tensor_intrin/__init__.py | 2 +- python/tvm/tir/tensor_intrin/{vnni.py => x86.py} | 8 ++++---- tests/python/unittest/test_meta_schedule_tune_relay.py | 2 +- tests/python/unittest/test_tir_schedule_tensorize.py | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) rename python/tvm/tir/tensor_intrin/{vnni.py => x86.py} (89%) diff --git a/python/tvm/tir/tensor_intrin/__init__.py b/python/tvm/tir/tensor_intrin/__init__.py index eff2653bee5c..78089517b6cf 100644 --- a/python/tvm/tir/tensor_intrin/__init__.py +++ b/python/tvm/tir/tensor_intrin/__init__.py @@ -16,4 +16,4 @@ # under the License. # pylint: disable=unused-import """Intrinsics for tensorization.""" -from . import vnni +from . import x86 diff --git a/python/tvm/tir/tensor_intrin/vnni.py b/python/tvm/tir/tensor_intrin/x86.py similarity index 89% rename from python/tvm/tir/tensor_intrin/vnni.py rename to python/tvm/tir/tensor_intrin/x86.py index 6f1d77ab8af0..84b86ed6b202 100644 --- a/python/tvm/tir/tensor_intrin/vnni.py +++ b/python/tvm/tir/tensor_intrin/x86.py @@ -23,7 +23,7 @@ @T.prim_func -def dot_product_desc(a: T.handle, b: T.handle, c: T.handle) -> None: +def dot_product_16x4_desc(a: T.handle, b: T.handle, c: T.handle) -> None: A = T.match_buffer(a, (4,), "uint8", offset_factor=1) B = T.match_buffer(b, (16, 4), "int8", offset_factor=1) C = T.match_buffer(c, (16,), "int32", offset_factor=1) @@ -41,7 +41,7 @@ def dot_product_desc(a: T.handle, b: T.handle, c: T.handle) -> None: @T.prim_func -def dot_product_intrin(a: T.handle, b: T.handle, c: T.handle) -> None: +def dot_product_16x4_vnni_impl(a: T.handle, b: T.handle, c: T.handle) -> None: A = T.match_buffer(a, (4,), "uint8", offset_factor=1) B = T.match_buffer(b, (16, 4), "int8", offset_factor=1) C = T.match_buffer(c, (16,), "int32", offset_factor=1) @@ -66,6 +66,6 @@ def dot_product_intrin(a: T.handle, b: T.handle, c: T.handle) -> None: ) -INTRIN_NAME = "dot_16x1x16_uint8_int8_int32_cascadelake" +VNNI_INTRIN = "dot_16x4_vnni" -TensorIntrin.register(INTRIN_NAME, dot_product_desc, dot_product_intrin) +TensorIntrin.register(VNNI_INTRIN, dot_product_16x4_desc, dot_product_16x4_vnni_impl) diff --git a/tests/python/unittest/test_meta_schedule_tune_relay.py b/tests/python/unittest/test_meta_schedule_tune_relay.py index 50f826378c61..fa59badc5da8 100644 --- a/tests/python/unittest/test_meta_schedule_tune_relay.py +++ b/tests/python/unittest/test_meta_schedule_tune_relay.py @@ -42,7 +42,7 @@ from tvm.target.target import Target from tvm.tir.schedule import BlockRV, Schedule from tvm.tir.schedule.trace import Trace -from tvm.tir.tensor_intrin.vnni import INTRIN_NAME as VNNI_INTRIN +from tvm.tir.tensor_intrin.x86 import VNNI_INTRIN logging.basicConfig() diff --git a/tests/python/unittest/test_tir_schedule_tensorize.py b/tests/python/unittest/test_tir_schedule_tensorize.py index 11f19e934e02..548543630145 100644 --- a/tests/python/unittest/test_tir_schedule_tensorize.py +++ b/tests/python/unittest/test_tir_schedule_tensorize.py @@ -22,7 +22,7 @@ from tvm import tir, te from tvm.script import tir as T from tvm.tir.schedule.testing import verify_trace_roundtrip -from tvm.tir.tensor_intrin.vnni import INTRIN_NAME as VNNI_INTRIN +from tvm.tir.tensor_intrin.x86 import VNNI_INTRIN # fmt: off # pylint: disable=no-member,invalid-name,unused-variable,line-too-long,redefined-outer-name,unexpected-keyword-arg,too-many-nested-blocks