From 765ecd7dd2dc8ecd351e1a39bb77205f9e0a60b9 Mon Sep 17 00:00:00 2001 From: mbtaylor1982 Date: Thu, 12 Oct 2023 00:10:29 +0100 Subject: [PATCH] refactoring the CPU FSM outputs --- RTL/CPU_SM/CPU_SM.v | 7 ++-- RTL/CPU_SM/CPU_SM_output.v | 73 +++++++++++++++++++------------------- 2 files changed, 42 insertions(+), 38 deletions(-) diff --git a/RTL/CPU_SM/CPU_SM.v b/RTL/CPU_SM/CPU_SM.v index ef2b803..58737c7 100644 --- a/RTL/CPU_SM/CPU_SM.v +++ b/RTL/CPU_SM/CPU_SM.v @@ -142,6 +142,7 @@ CPU_SM_inputs u_CPU_SM_inputs( .nE (nE), .E (E) ); +/* cpudff1 u_cpudff1( .DSACK (DSACK ), .STERM_ (STERM_ ), @@ -176,6 +177,7 @@ cpudff5 u_cpudff5( .E (E ), .cpudff5_d (cpudff5_d ) ); +*/ CPU_SM_outputs u_CPU_SM_outputs( .DSACK (DSACK ), .nDSACK (nDSACK ), @@ -205,7 +207,8 @@ CPU_SM_outputs u_CPU_SM_outputs( .DIEH_d (DIEH_d ), .DIEL_d (DIEL_d ), .nBRIDGEIN_d (nBRIDGEIN_d ), - .BGACK_d (BGACK_d ) + .BGACK_d (BGACK_d ), + .NEXT_STATE (NEXT_STATE ) ); //clocked reset @@ -293,7 +296,7 @@ assign aCYCLEDONE_ = ~(BGACK_I_ & AS_ & DSACK0_ & DSACK1_ & iSTERM_); assign LASTWORD = (~BOEQ0 & aFLUSHFIFO & FIFOEMPTY); -assign NEXT_STATE = {cpudff5_d, cpudff4_d, cpudff3_d, cpudff2_d, cpudff1_d}; +//assign NEXT_STATE = {cpudff5_d, cpudff4_d, cpudff3_d, cpudff2_d, cpudff1_d}; assign CYCLEDONE = ~nCYCLEDONE; diff --git a/RTL/CPU_SM/CPU_SM_output.v b/RTL/CPU_SM/CPU_SM_output.v index 976f4eb..c500470 100644 --- a/RTL/CPU_SM/CPU_SM_output.v +++ b/RTL/CPU_SM/CPU_SM_output.v @@ -42,11 +42,18 @@ module CPU_SM_outputs ( output DIEH_d, output DIEL_d, output nBRIDGEIN_d, - output BGACK_d + output BGACK_d, + output [4:0] NEXT_STATE ); +//Next-state equations +assign NEXT_STATE[0] = E[12] | E[26] | E[53] | E[27] | E[32] | E[48] | E[55] | E[56] | E[58] | E[60] | E[62] | (E[6] & DSACK) | (E[25] & DSACK) | (E[50] & DSACK) | (E[50] & ~DSACK) | (E[43] & ~STERM_) | (E[46] & ~STERM_) | (E[51] & ~STERM_) | (E[36] & STERM_) | (E[37] & STERM_) | (E[40] & STERM_) | (E[46] & STERM_) | (E[57] & STERM_) | (E[23] & DSACK & STERM_) | (E[24] & ~DSACK & STERM_) | (E[29] & ~DSACK & STERM_) | (E[33] & ~DSACK & STERM_) | (E[43] & ~DSACK & STERM_) | (E[51] & ~DSACK & STERM_); +assign NEXT_STATE[1] = E[1] | E[11] | E[16] | E[17] | E[26] | E[27] | E[31] | E[32] | E[35] | E[55] | E[58] | E[61] | (E[25] & DSACK) | (E[50] & DSACK) | (E[43] & ~STERM_) | (E[46] & ~STERM_) | (E[51] & ~STERM_) | (E[36] & STERM_) | (E[57] & STERM_) | (E[46] & STERM_) | (E[40] & STERM_) | (E[23] & DSACK & STERM_) | (E[33] & ~DSACK & STERM_) | (E[43] & ~DSACK & STERM_) | (E[51] & ~DSACK & STERM_) | (E[29] & ~DSACK & STERM_); +assign NEXT_STATE[2] = E[4] | E[10] | E[21] | E[27] | E[34] | E[32] | E[35] | E[56] | E[62] | E[45] | (E[20] & DSACK) | (E[28] & DSACK) | (E[30] & DSACK) | (E[50] & ~DSACK) | (E[36] & ~STERM_) | (E[33] & ~STERM_) | (E[39] & ~STERM_) | (E[40] & ~STERM_) | (E[42] & ~STERM_) | (E[37] & ~STERM_) | (E[36] & STERM_) | (E[46] & STERM_) | (E[23] & STERM_ & DSACK) | (E[33] & ~DSACK & STERM_) | (E[51] & ~DSACK & STERM_); +assign NEXT_STATE[3] = E[2] | E[3] | E[5] | E[7] | E[8] | E[12] | E[18] | E[19] | E[21] | E[31] | E[34] | E[45] | E[48] | E[55] | E[60] | E[61] | (E[9] & DSACK) | (E[50] & DSACK) | (E[25] & DSACK) | (E[28] & DSACK) | (E[30] & DSACK) | (E[51] & ~STERM_) | (E[46] & ~STERM_) | (E[36] & ~STERM_) | (E[33] & ~STERM_) | (E[39] & ~STERM_) | (E[40] & ~STERM_) | (E[42] & ~STERM_) | (E[43] & ~STERM_) | (E[37] & ~STERM_) | (E[57] & STERM_) | (E[46] & STERM_) | (E[23] & DSACK & STERM_) | (E[51] & ~DSACK & STERM_) | (E[43] & ~DSACK & STERM_); +assign NEXT_STATE[4] = E[5] | E[4] | E[8] | E[11] | E[26] | E[27] | E[32] | E[13] | E[14] | E[15] | E[22] | E[60] | E[61] | E[62] | E[48] | E[53] | E[58] | (E[9] & DSACK) | (E[30] & DSACK) | (E[28] & DSACK) | (E[36] & ~STERM_) | (E[33] & ~STERM_) | (E[39] & ~STERM_) | (E[40] & ~STERM_) | (E[42] & ~STERM_) | (E[37] & ~STERM_) | (E[23] & DSACK & STERM_) | (E[43] & ~DSACK & & STERM_) | (E[57] & STERM_); -assign nINCNI_d = ~(E[32] | E[48] ); +assign nINCNI_d = ~(E[32] | E[48]); //assign INCNI_d = (E[32] | E[48] ); assign nBREQ_d = ~(E[2] | E[3] | E[4] | E[5] | E[7] | E[8] | E[10] | E[11] | E[12] | E[16] | E[17] | E[18] | E[19]); @@ -75,19 +82,13 @@ assign SIZE1_d = (~(SIZE1_X & SIZE1_Y & SIZE1_Z)); //PAS wire PAS_X, PAS_Y; -assign PAS_X = -~(nDSACK & E[50]) & -~( - ~(nE[62] & nE[61] & nE[60] & nE[58]) | - ~(nE[56] & nE[53] & nE[48] & nE[45]) | - ~(nE[34] & nE[26] & nE[21]) -); +assign PAS_X = ~((~DSACK & E[50]) | (E[62] | E[61] | E[60] | E[58] | E[56] | E[53] | E[48] | E[45] | E[34] | E[26] | E[21])); assign PAS_Y = ~( STERM_ & ( - (nDSACK & (E[24] | E[29] | E[33] | E[43] | E[51])) | + (~DSACK & (E[24] | E[29] | E[33] | E[43] | E[51])) | (E[37] | E[40] | E[36] | E[57] | E[46]) ) ); @@ -106,9 +107,9 @@ assign PDS_d = (~(PDS_X & PDS_Y)); //F2CPUL wire F2CPUL_X, F2CPUL_Y, F2CPUL_Z; -assign F2CPUL_X = ((nE[58] & nE[53] & nE[34] & nE[45] & nE[26] & nE[21] ) & ~(~(nE[20] & nE[30] & nE[28] ) & DSACK)); -assign F2CPUL_Y = (~(nSTERM_ & ~(nE[36] & nE[33] & nE[39] & nE[40] & nE[42] & nE[37]))); -assign F2CPUL_Z = (~(((nDSACK & (E[24] | E[29] | E[33] )) | (E[37] | E[40] | E[36] )) & STERM_)); +assign F2CPUL_X = (~(E[58] | E[53] | E[34] | E[45] | E[26] | E[21]) & ~((E[20] | E[30] | E[28]) & DSACK)); +assign F2CPUL_Y = (~(~STERM_ & (E[36] | E[33] | E[39] | E[40] | E[42] | E[37]))); +assign F2CPUL_Z = (~(((~DSACK & (E[24] | E[29] | E[33] )) | (E[37] | E[40] | E[36] )) & STERM_)); assign F2CPUL_d = (~(F2CPUL_X & F2CPUL_Y & F2CPUL_Z)); @@ -116,26 +117,26 @@ assign F2CPUL_d = (~(F2CPUL_X & F2CPUL_Y & F2CPUL_Z)); //F2CPUH wire F2CPUH_X, F2CPUH_Y, F2CPUH_Z; -assign F2CPUH_X = ((nE[58] & nE[34] & nE[45] & nE[26] & nE[21] ) & ~(~(nE[20] & nE[28] ) & DSACK)); -assign F2CPUH_Y = (~(nSTERM_ & ~(nE[36] & nE[33] & nE[39] & nE[37]))); -assign F2CPUH_Z = (~(((nDSACK & (E[24] | E[33] )) | (E[37] | E[36] )) & STERM_)); +assign F2CPUH_X = (~(E[58] | E[34] | E[45] | E[26] | E[21]) & ~((E[20] | E[28]) & DSACK)); +assign F2CPUH_Y = (~(~STERM_ & (E[36] | E[33] | E[39] | E[37]))); +assign F2CPUH_Z = (~(((~DSACK & (E[24] | E[33] )) | (E[37] | E[36] )) & STERM_)); assign F2CPUH_d = (~(F2CPUH_X & F2CPUH_Y & F2CPUH_Z)); //BRIDGEOUT wire BRIDGEOUT_X, BRIDGEOUT_Y, BRIDGEOUT_Z; -assign BRIDGEOUT_X = (nE[53] & ~(E[30] & DSACK)); -assign BRIDGEOUT_Y = (~(nSTERM_ & ~(nE[42] & nE[40] ))); -assign BRIDGEOUT_Z = (~(((nDSACK & E[29] )| E[40] ) & STERM_)); +assign BRIDGEOUT_X = (~E[53] & ~(E[30] & DSACK)); +assign BRIDGEOUT_Y = (~(~STERM_ & (E[42] | E[40]))); +assign BRIDGEOUT_Z = (~(((~DSACK & E[29] )| E[40] ) & STERM_)); assign BRIDGEOUT_d = (~(BRIDGEOUT_X & BRIDGEOUT_Y & BRIDGEOUT_Z)); //PLLW wire PLLW_X, PLLW_Y; -assign PLLW_X = ((nE[35] & nE[56] & nE[48] & nE[60] & nE[61] & nE[62] ) & ~(E[50] & nDSACK)); -assign PLLW_Y = (~((~(~(E[23] & DSACK) & ~(nDSACK & (E[43] | E[51] )))|(E[57] | E[46] )) & STERM_)); +assign PLLW_X = (~(E[35] | E[56] | E[48] | E[60] | E[61] | E[62]) & ~(E[50] & ~DSACK)); +assign PLLW_Y = (~((~(~(E[23] & DSACK) & ~(~DSACK & (E[43] | E[51] )))|(E[57] | E[46] )) & STERM_)); assign PLLW_d = (~(PLLW_X & PLLW_Y)); @@ -145,10 +146,10 @@ assign PLHW_d = ~(~(E[48] | E[60] ) & (~(((nDSACK & E[43] ) | E[57] ) & STERM_) //FIFO COUNTER STROBES wire AA,BB,CC,DD,EE,FF; -assign AA = (~(~(nE[51] & nE[46] & nE[43] ) & nSTERM_)); -assign BB = (~(DSACK & ~(nE[50] & nE[25] & nE[6] )) & nE[55] ); -assign CC = (~(~(nE[9] & nE[30] ) & DSACK)); -assign DD = (~(nSTERM_ & ~(nE[39] & nE[40] & nE[37] & nE[42] ))); +assign AA = (~((E[51] | E[46] | E[43] ) & ~STERM_)); +assign BB = (~(DSACK & (E[50] | E[25] | E[6])) & ~E[55] ); +assign CC = (~((E[9] | E[30]) & DSACK)); +assign DD = (~(~STERM_ & (E[39] | E[40] | E[37] | E[42]))); assign EE = (~(AA & BB & ~RDFIFO_)); assign FF = (~(CC & DD & ~RIFIFO_)); @@ -156,29 +157,29 @@ assign INCFIFO_d = (~(AA & BB & FF)); assign DECFIFO_d = (~(CC & DD & EE)); assign INCNO_d = (~(CC & DD)); -assign nSTOPFLUSH_d = (nE[0] & nE[4] & nE[5] & nE[21] & nE[26] & nE[27] ); -//assign STOPFLUSH_d = (E[0] | E[4] | E[5] | E[21] | E[26] | E[27] ); +assign nSTOPFLUSH_d = ~(E[0] | E[4] | E[5] | E[21] | E[26] | E[27]); +//assign STOPFLUSH_d = (E[0] | E[4] | E[5] | E[21] | E[26] | E[27] ); //DIEH wire DIEH_X, DIEH_Y, DIEH_Z; -assign DIEH_X = ((nE[61] & nE[60] & nE[62] & nE[31] & nE[56] & nE[48] ) & ~(~(nE[25] & nE[50] ) & DSACK) & ~(E[50] & ~DSACK)); -assign DIEH_Y = (~(nSTERM_ & ~(nE[43] & nE[46] & nE[51] ))); -assign DIEH_Z = (~(((nDSACK & (E[51] | E[43] )) |(E[46] | E[57] )) & STERM_)); +assign DIEH_X = ~((E[61] | E[60] | E[62] | E[31] | E[56] | E[48]) | ((E[25] | E[50]) & DSACK) | (E[50] & ~DSACK)); +assign DIEH_Y = (~(~STERM_ & (E[43] | E[46] | E[51]))); +assign DIEH_Z = (~(((~DSACK & (E[51] | E[43] )) |(E[46] | E[57] )) & STERM_)); assign DIEH_d = (~(DIEH_X & DIEH_Y & DIEH_Z)); //DIEL wire DIEL_X, DIEL_Y, DIEL_Z; -assign DIEL_X = ((nE[62] & nE[60] & nE[48] ) & ~(~(nE[25] & nE[6] ) & DSACK)); -assign DIEL_Y = (~(nSTERM_ & ~(nE[43] & nE[46] & nE[51] ))); -assign DIEL_Z = (~(((nDSACK & (E[51] | E[43] )) |(E[46] | E[57] )) & STERM_)); +assign DIEL_X = ~((E[62] | E[60] | E[48]) | ((E[25] | E[6]) & DSACK)); +assign DIEL_Y = (~(~STERM_ & (E[43] | E[46] | E[51] ))); +assign DIEL_Z = (~(((~DSACK & (E[51] | E[43] )) |(E[46] | E[57] )) & STERM_)); -assign DIEL_d = (~(DIEL_X & DIEL_Y & DIEL_Z)); +assign DIEL_d = (~DIEL_X | ~DIEL_Y | ~DIEL_Z); -assign nBRIDGEIN_d = (nE[56] & nE[55] & nE[35] & nE[61] & nE[50] ); -//assign BRIDGEIN_d = ~(E[56] | E[55] | E[35] | E[61] | E[50] ); +assign nBRIDGEIN_d = ~(E[56] | E[55] | E[35] | E[61] | E[50] ); +//assign BRIDGEIN_d = (E[56] | E[55] | E[35] | E[61] | E[50] ); //BGACK wire S2ORS8, BGACK_W, BGACK_X;