[Query] Max Instruction Size for riscv64

[mizanurasif]

Hello, I have a query. I am a developer for Tizen SDK for Visual Studio. For supporting debugging of riscv64 architecture in VS, we are modifying miengine project. While adding code, we found a variable named MaxInstructionSize for each architecture in miengine code.
Example:
case TargetArchitecture.ARM64:
MaxInstructionSize = 8;
Is64BitArch = true;
break;

What might be the MaxInstructionSize for riscv64?

[gregg-miskelly]

Disclaimer: I have never looked at RISC-V instruction set before this question, so I am by no means an expert on RISC-V.

Looking at this specification I think it isn't an entirely answerable question at an architectural level since RISC-V provides for arbitrary sized extensions. That said, the purpose of the MaxInstructionSize is just to aid in disassembly. So, if you know the largest instruction that the underlying debugger that MI Engine is talking to can actually disassemble, then you should use that value.