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spi.core
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spi.core
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CAPI=2:
name: midimaster21b:comm:spi-master:0.1.2
description: A simple SPI master implementation
filesets:
rtl:
files:
- src/rtl/spi_master.vhd
- src/rtl/spi_master_wrapper.vhd
file_type: vhdlSource
depend:
- ==midimaster21b:prim:ddr:0.1.1
tb:
files:
- src/tb/spi_master_tb.sv
file_type: systemVerilogSource
depend: [midimaster21b:bfm:axis, midimaster21b:bfm:spi, midimaster21b:comm:amba-interfaces]
pkg_ip:
files:
- src/tcl/pkg_ip.tcl
file_type: tclSource
targets:
# Special FuseSoC target
default: &default
default_tool: vivado
filesets:
- rtl
- pkg_ip
toplevel: spi_master_wrapper
tools:
vivado:
pnr: none
# Simulation target
sim:
<<: *default
description: Simulate the design
default_tool: xsim
filesets_append:
- tb
toplevel: spi_master_tb
parameters:
CLOCK_PHASE_G:
datatype: int
description: The SPI clock phase of the IP
paramtype: vlogparam
default: 0
CLOCK_POLARITY_G:
datatype: int
description: The SPI clock polarity of the IP
paramtype: vlogparam
default: 0