Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[ENHANCEMENT] Verilog code beautifier #126

Open
wkelsey-apple opened this issue Dec 17, 2020 · 3 comments
Open

[ENHANCEMENT] Verilog code beautifier #126

wkelsey-apple opened this issue Dec 17, 2020 · 3 comments

Comments

@wkelsey-apple
Copy link

This would be super nice to help clean up legacy code!

Python can do it, so I'm assuming that it would be possible with this addon?

@wkelsey-apple
Copy link
Author

trying to add an enhancement....

@wkelsey-apple
Copy link
Author

could you move it to enhancement?

@wkelsey-apple wkelsey-apple reopened this Dec 17, 2020
@SeanMcLoughlin
Copy link

This could be added by using verible and it's auto-format feature to a keybind, or even an "auto-format on save."

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

No branches or pull requests

3 participants