forked from tonioni/WinUAE
-
Notifications
You must be signed in to change notification settings - Fork 0
/
cpuboard.cpp
3118 lines (2861 loc) · 88.8 KB
/
cpuboard.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* UAE - The Un*x Amiga Emulator
*
* Misc accelerator board special features
* Blizzard 1230 IV, 1240/1260, 2040/2060, PPC
* CyberStorm MK1, MK2, MK3, PPC.
* TekMagic
* Warp Engine
*
* And more.
*
* Copyright 2014 Toni Wilen
*
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "memory.h"
#include "zfile.h"
#include "rommgr.h"
#include "autoconf.h"
#include "cpuboard.h"
#include "custom.h"
#include "newcpu.h"
#include "ncr_scsi.h"
#include "ncr9x_scsi.h"
#include "debug.h"
#include "flashrom.h"
#include "uae.h"
#include "uae/ppc.h"
#include "uae/vm.h"
#include "idecontrollers.h"
#include "scsi.h"
#include "cpummu030.h"
#include "devices.h"
// ROM expansion board diagrom call
// 00F83B7C 3.1 A4000
// 00F83B7C 3.0 A1200
// 00F83C96 3.1 A1200
// 00FC4E28 1.3
#define MAPROM_DEBUG 0
#define PPC_IRQ_DEBUG 0
#define CPUBOARD_IO_LOG 0
#define CPUBOARD_IRQ_LOG 0
#define F0_WAITSTATES (2 * CYCLE_UNIT)
// CS MK3/PPC
#define CYBERSTORM_MAPROM_BASE 0xfff00000
#define CSIII_NCR 0xf40000
#define CSIII_BASE 0xf60000
#define CSIII_REG_RESET 0x00 // 0x00
#define CSIII_REG_IRQ 0x01 // 0x08
#define CSIII_REG_WAITSTATE 0x02 // 0x10
#define CSIII_REG_SHADOW 0x03 // 0x18
#define CSIII_REG_LOCK 0x04 // 0x20
#define CSIII_REG_INT 0x05 // 0x28
#define CSIII_REG_IPL_EMU 0x06 // 0x30
#define CSIII_REG_INT_LVL 0x07 // 0x38
// BPPC only
#define BPPC_MAPROM_ON 0x12
#define BPPC_MAPROM_OFF 0x13
#define BPPC_UNLOCK_FLASH 0x92
#define BPPC_LOCK_FLASH 0x93
#define BPPC_MAGIC_UNLOCK_VALUE 0x42
/* bit definitions */
#define P5_SET_CLEAR 0x80
/* REQ_RESET 0x00 */
// M68K can only reset PPC and vice versa
// if P5_SELF_RESET is not active.
#define P5_PPC_RESET 0x10
#define P5_M68K_RESET 0x08
#define P5_AMIGA_RESET 0x04
#define P5_AUX_RESET 0x02
#define P5_SCSI_RESET 0x01
/* REG_IRQ 0x08 */
#define P5_IRQ_SCSI 0x01
#define P5_IRQ_SCSI_EN 0x02
// 0x04
#define P5_IRQ_PPC_1 0x08
#define P5_IRQ_PPC_2 0x10
#define P5_IRQ_PPC_3 0x20 // MOS sets this bit
// 0x40 always cleared
/* REG_WAITSTATE 0x10 */
#define P5_PPC_WRITE 0x08
#define P5_PPC_READ 0x04
#define P5_M68K_WRITE 0x02
#define P5_M68K_READ 0x01
/* REG_SHADOW 0x18 */
#define P5_SELF_RESET 0x40
// 0x20
// 0x10
// 0x08 always set
#define P5_FLASH 0x04 // Flash writable (CSMK3,CSPPC only)
// 0x02 (can be modified even when locked)
#define P5_SHADOW 0x01 // KS MAP ROM (CSMK3,CSPPC only)
/* REG_LOCK 0x20. CSMK3,CSPPC only */
#define P5_MAGIC1 0x60 // REG_SHADOW and flash write protection unlock sequence
#define P5_MAGIC2 0x50
#define P5_MAGIC3 0x30
#define P5_MAGIC4 0x70
// when cleared, another CPU gets either stopped or can't access memory until set again.
#define P5_LOCK_CPU 0x01
/* REG_INT 0x28 */
// 0x40 always set
// 0x20
// 0x10 always set
// 0x08
// 0x04 // MOS sets this bit
#define P5_ENABLE_IPL 0x02
#define P5_INT_MASTER 0x01 // 1=m68k gets interrupts, 0=ppc gets interrupts.
/* IPL_EMU 0x30 */
#define P5_DISABLE_INT 0x40 // if set: all CPU interrupts disabled?
#define P5_M68K_IPL2 0x20
#define P5_M68K_IPL1 0x10
#define P5_M68K_IPL0 0x08
#define P5_M68k_IPL_MASK 0x38
#define P5_PPC_IPL2 0x04
#define P5_PPC_IPL1 0x02
#define P5_PPC_IPL0 0x01
#define P5_PPC_IPL_MASK 0x07
/* INT_LVL 0x38 */
#define P5_LVL7 0x40
#define P5_LVL6 0x20
#define P5_LVL5 0x10
#define P5_LVL4 0x08
#define P5_LVL3 0x04
#define P5_LVL2 0x02
#define P5_LVL1 0x01
#define CS_RAM_BASE 0x08000000
#define BLIZZARDMK4_RAM_BASE_48 0x48000000
#define BLIZZARDMK4_MAPROM_BASE 0x4ff80000
#define BLIZZARDMK2_MAPROM_BASE 0x0ff80000
#define BLIZZARDMK3_MAPROM_BASE 0x1ef80000
#define BLIZZARD_MAPROM_ENABLE 0x80ffff00
#define BLIZZARD_BOARD_DISABLE 0x80fa0000
#define BLIZZARD_BOARD_DISABLE2 0x80f00000
#define CSMK2_2060_BOARD_DISABLE 0x83000000
static int cpuboard_size = -1, cpuboard2_size = -1;
static int configured;
static int blizzard_jit;
static int maprom_state;
static uae_u32 maprom_base;
static int delayed_rom_protect;
static int f0rom_size, earom_size;
static uae_u8 io_reg[64];
static void *flashrom, *flashrom2;
static struct zfile *flashrom_file;
static int flash_unlocked;
static int csmk2_flashaddressing;
static bool blizzardmaprom_bank_mapped, blizzardmaprom2_bank_mapped;
static bool cpuboard_non_byte_ea;
static uae_u16 a2630_io;
static bool ppc_irq_pending;
static void set_ppc_interrupt(void)
{
if (ppc_irq_pending)
return;
#if PPC_IRQ_DEBUG
write_log(_T("set_ppc_interrupt\n"));
#endif
uae_ppc_interrupt(true);
ppc_irq_pending = true;
}
static void clear_ppc_interrupt(void)
{
if (!ppc_irq_pending)
return;
#if PPC_IRQ_DEBUG
write_log(_T("clear_ppc_interrupt\n"));
#endif
uae_ppc_interrupt(false);
ppc_irq_pending = false;
}
static void check_ppc_int_lvl(void)
{
bool m68kint = (io_reg[CSIII_REG_INT] & P5_INT_MASTER) != 0;
bool active = (io_reg[CSIII_REG_IPL_EMU] & P5_DISABLE_INT) == 0;
bool iplemu = (io_reg[CSIII_REG_INT] & P5_ENABLE_IPL) == 0;
if (m68kint && iplemu && active) {
uae_u8 ppcipl = (~io_reg[CSIII_REG_IPL_EMU]) & P5_PPC_IPL_MASK;
if (ppcipl < 7) {
uae_u8 ilvl = (~io_reg[CSIII_REG_INT_LVL]) & 0x7f;
if (ilvl) {
for (int i = ppcipl; i < 7; i++) {
if (ilvl & (1 << i)) {
set_ppc_interrupt();
return;
}
}
}
}
clear_ppc_interrupt();
}
}
bool ppc_interrupt(int new_m68k_ipl)
{
bool m68kint = (io_reg[CSIII_REG_INT] & P5_INT_MASTER) != 0;
bool active = (io_reg[CSIII_REG_IPL_EMU] & P5_DISABLE_INT) == 0;
bool iplemu = (io_reg[CSIII_REG_INT] & P5_ENABLE_IPL) == 0;
if (!active)
return false;
if (!m68kint && iplemu && active) {
uae_u8 ppcipl = (~io_reg[CSIII_REG_IPL_EMU]) & P5_PPC_IPL_MASK;
if (new_m68k_ipl < 0)
new_m68k_ipl = 0;
io_reg[CSIII_REG_IPL_EMU] &= ~P5_M68k_IPL_MASK;
io_reg[CSIII_REG_IPL_EMU] |= (new_m68k_ipl << 3) ^ P5_M68k_IPL_MASK;
if (new_m68k_ipl > ppcipl) {
set_ppc_interrupt();
} else {
clear_ppc_interrupt();
}
}
return m68kint;
}
static bool mapromconfigured(void)
{
if (currprefs.maprom && !currprefs.cpuboard_type)
return true;
if (currprefs.cpuboard_settings & 1)
return true;
return false;
}
void cpuboard_set_flash_unlocked(bool unlocked)
{
flash_unlocked = unlocked;
}
static bool is_blizzard1230mk2(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_1230II);
}
static bool is_blizzard1230mk3(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_1230III);
}
static bool is_blizzard(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_1230IV) || ISCPUBOARDP(p, BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_1260);
}
static bool is_blizzard2060(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_2060);
}
static bool is_csmk1(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_MK1);
}
static bool is_csmk2(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_MK2);
}
static bool is_csmk3(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_MK3) || ISCPUBOARDP(p, BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_PPC);
}
static bool is_blizzardppc(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC);
}
static bool is_ppc(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC) || ISCPUBOARDP(p, BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_PPC);
}
static bool is_tekmagic(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_GVP, BOARD_GVP_SUB_TEKMAGIC);
}
static bool is_a2630(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_COMMODORE, BOARD_COMMODORE_SUB_A26x0);
}
static bool is_harms_3kp(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_HARMS, BOARD_HARMS_SUB_3KPRO);
}
static bool is_dkb_12x0(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_DKB, BOARD_DKB_SUB_12x0);
}
static bool is_dkb_wildfire(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_DKB, BOARD_DKB_SUB_WILDFIRE);
}
static bool is_mtec_ematrix530(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530);
}
static bool is_dce_typhoon2(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_DCE, BOARD_DCE_SUB_TYPHOON2);
}
static bool is_fusionforty(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_RCS, BOARD_RCS_SUB_FUSIONFORTY);
}
static bool is_apollo(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_ACT, BOARD_ACT_SUB_APOLLO);
}
static bool is_kupke(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_KUPKE, 0);
}
static bool is_sx32pro(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_DCE, 0);
}
static bool is_ivsvector(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_IVS, BOARD_IVS_SUB_VECTOR);
}
static bool is_12gauge(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_CSA, BOARD_CSA_SUB_12GAUGE);
}
static bool is_magnum40(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_CSA, BOARD_CSA_SUB_MAGNUM40);
}
static bool is_falcon40(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_MACROSYSTEM, BOARD_MACROSYSTEM_SUB_FALCON040);
}
static bool is_tqm(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_HARDITAL, BOARD_HARDITAL_SUB_TQM);
}
static bool is_a1230s1(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_GVP, BOARD_GVP_SUB_A1230SI);
}
static bool is_a1230s2(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_GVP, BOARD_GVP_SUB_A1230SII);
}
static bool is_quikpak(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_GVP, BOARD_GVP_SUB_QUIKPAK);
}
static bool is_aca500(struct uae_prefs *p)
{
return false; //return ISCPUBOARDP(p, BOARD_IC, BOARD_IC_ACA500);
}
extern addrbank cpuboardmem1_bank;
MEMORY_FUNCTIONS(cpuboardmem1);
static addrbank cpuboardmem1_bank = {
cpuboardmem1_lget, cpuboardmem1_wget, cpuboardmem1_bget,
cpuboardmem1_lput, cpuboardmem1_wput, cpuboardmem1_bput,
cpuboardmem1_xlate, cpuboardmem1_check, NULL, _T("*B"), _T("cpuboard ram"),
cpuboardmem1_lget, cpuboardmem1_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
};
extern addrbank cpuboardmem2_bank;
MEMORY_FUNCTIONS(cpuboardmem2);
static addrbank cpuboardmem2_bank = {
cpuboardmem2_lget, cpuboardmem2_wget, cpuboardmem2_bget,
cpuboardmem2_lput, cpuboardmem2_wput, cpuboardmem2_bput,
cpuboardmem2_xlate, cpuboardmem2_check, NULL, _T("*B"), _T("cpuboard ram #2"),
cpuboardmem2_lget, cpuboardmem2_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
};
DECLARE_MEMORY_FUNCTIONS(blizzardio);
static addrbank blizzardio_bank = {
blizzardio_lget, blizzardio_wget, blizzardio_bget,
blizzardio_lput, blizzardio_wput, blizzardio_bput,
default_xlate, default_check, NULL, NULL, _T("CPUBoard IO"),
blizzardio_wget, blizzardio_bget,
ABFLAG_IO, S_READ, S_WRITE
};
DECLARE_MEMORY_FUNCTIONS(blizzardram);
static addrbank blizzardram_bank = {
blizzardram_lget, blizzardram_wget, blizzardram_bget,
blizzardram_lput, blizzardram_wput, blizzardram_bput,
blizzardram_xlate, blizzardram_check, NULL, NULL, _T("CPUBoard RAM"),
blizzardram_lget, blizzardram_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
};
DECLARE_MEMORY_FUNCTIONS(blizzardea);
static addrbank blizzardea_bank = {
blizzardea_lget, blizzardea_wget, blizzardea_bget,
blizzardea_lput, blizzardea_wput, blizzardea_bput,
blizzardea_xlate, blizzardea_check, NULL, _T("rom_ea"), _T("CPUBoard E9/EA Autoconfig"),
blizzardea_lget, blizzardea_wget,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
DECLARE_MEMORY_FUNCTIONS(blizzarde8);
static addrbank blizzarde8_bank = {
blizzarde8_lget, blizzarde8_wget, blizzarde8_bget,
blizzarde8_lput, blizzarde8_wput, blizzarde8_bput,
blizzarde8_xlate, blizzarde8_check, NULL, NULL, _T("CPUBoard E8 Autoconfig"),
blizzarde8_lget, blizzarde8_wget,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
DECLARE_MEMORY_FUNCTIONS(blizzardf0);
static addrbank blizzardf0_bank = {
blizzardf0_lget, blizzardf0_wget, blizzardf0_bget,
blizzardf0_lput, blizzardf0_wput, blizzardf0_bput,
blizzardf0_xlate, blizzardf0_check, NULL, _T("rom_f0_ppc"), _T("CPUBoard F00000"),
blizzardf0_lget, blizzardf0_wget,
ABFLAG_ROM, S_READ, S_WRITE
};
#if 0
DECLARE_MEMORY_FUNCTIONS(blizzardram_nojit);
static addrbank blizzardram_nojit_bank = {
blizzardram_nojit_lget, blizzardram_nojit_wget, blizzardram_nojit_bget,
blizzardram_nojit_lput, blizzardram_nojit_wput, blizzardram_nojit_bput,
blizzardram_nojit_xlate, blizzardram_nojit_check, NULL, NULL, _T("CPUBoard RAM"),
blizzardram_nojit_lget, blizzardram_nojit_wget,
ABFLAG_RAM | ABFLAG_THREADSAFE, S_READ, S_WRITE
};
#endif
DECLARE_MEMORY_FUNCTIONS(blizzardmaprom);
static addrbank blizzardmaprom_bank = {
blizzardmaprom_lget, blizzardmaprom_wget, blizzardmaprom_bget,
blizzardmaprom_lput, blizzardmaprom_wput, blizzardmaprom_bput,
blizzardmaprom_xlate, blizzardmaprom_check, NULL, _T("maprom"), _T("CPUBoard MAPROM"),
blizzardmaprom_lget, blizzardmaprom_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
DECLARE_MEMORY_FUNCTIONS(blizzardmaprom2);
static addrbank blizzardmaprom2_bank = {
blizzardmaprom2_lget, blizzardmaprom2_wget, blizzardmaprom2_bget,
blizzardmaprom2_lput, blizzardmaprom2_wput, blizzardmaprom2_bput,
blizzardmaprom2_xlate, blizzardmaprom2_check, NULL, _T("maprom2"), _T("CPUBoard MAPROM2"),
blizzardmaprom2_lget, blizzardmaprom2_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
// hack to map F41000 SCSI SCRIPTS RAM to JIT friendly address
void cyberstorm_scsi_ram_put(uaecptr addr, uae_u32 v)
{
addr &= 0xffff;
addr += (CSIII_NCR & 0x7ffff);
blizzardf0_bank.baseaddr[addr] = v;
}
uae_u32 cyberstorm_scsi_ram_get(uaecptr addr)
{
uae_u32 v;
addr &= 0xffff;
addr += (CSIII_NCR & 0x7ffff);
v = blizzardf0_bank.baseaddr[addr];
return v;
}
uae_u8 *REGPARAM2 cyberstorm_scsi_ram_xlate(uaecptr addr)
{
addr &= 0xffff;
addr += (CSIII_NCR & 0x7ffff);
return blizzardf0_bank.baseaddr + addr;
}
int REGPARAM2 cyberstorm_scsi_ram_check(uaecptr a, uae_u32 b)
{
a &= 0xffff;
return a >= 0x1000 && a + b < 0x3000;
}
MEMORY_FUNCTIONS(blizzardram);
#if 0
MEMORY_BGET(blizzardram_nojit);
MEMORY_WGET(blizzardram_nojit);
MEMORY_LGET(blizzardram_nojit);
MEMORY_CHECK(blizzardram_nojit);
MEMORY_XLATE(blizzardram_nojit);
static void REGPARAM2 blizzardram_nojit_lput(uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= blizzardram_nojit_bank.mask;
if (maprom_state && addr >= maprom_base)
return;
m = (uae_u32 *)(blizzardram_nojit_bank.baseaddr + addr);
do_put_mem_long(m, l);
}
static void REGPARAM2 blizzardram_nojit_wput(uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= blizzardram_nojit_bank.mask;
if (maprom_state && addr >= maprom_base)
return;
m = (uae_u16 *)(blizzardram_nojit_bank.baseaddr + addr);
do_put_mem_word(m, w);
}
static void REGPARAM2 blizzardram_nojit_bput(uaecptr addr, uae_u32 b)
{
addr &= blizzardram_nojit_bank.mask;
if (maprom_state && addr >= maprom_base)
return;
blizzardram_nojit_bank.baseaddr[addr] = b;
}
#endif
static void no_rom_protect(void)
{
if (delayed_rom_protect)
return;
delayed_rom_protect = 10;
protect_roms(false);
}
static uae_u8 *writeprotect_addr;
static int writeprotect_size;
static void maprom_unwriteprotect(void)
{
if (!writeprotect_addr)
return;
if (currprefs.cachesize && !currprefs.comptrustlong)
uae_vm_protect(writeprotect_addr, writeprotect_size, UAE_VM_READ_WRITE);
writeprotect_addr = NULL;
}
static void maprom_writeprotect(uae_u8 *addr, int size)
{
maprom_unwriteprotect();
writeprotect_addr = addr;
writeprotect_size = size;
if (currprefs.cachesize && !currprefs.comptrustlong)
uae_vm_protect(addr, size, UAE_VM_READ);
}
MEMORY_BGET(blizzardmaprom2);
MEMORY_WGET(blizzardmaprom2);
MEMORY_LGET(blizzardmaprom2);
MEMORY_CHECK(blizzardmaprom2);
MEMORY_XLATE(blizzardmaprom2);
static void REGPARAM2 blizzardmaprom2_lput(uaecptr addr, uae_u32 l)
{
}
static void REGPARAM2 blizzardmaprom2_wput(uaecptr addr, uae_u32 l)
{
}
static void REGPARAM2 blizzardmaprom2_bput(uaecptr addr, uae_u32 l)
{
}
MEMORY_BGET(blizzardmaprom);
MEMORY_WGET(blizzardmaprom);
MEMORY_LGET(blizzardmaprom);
MEMORY_CHECK(blizzardmaprom);
MEMORY_XLATE(blizzardmaprom);
static void REGPARAM2 blizzardmaprom_lput(uaecptr addr, uae_u32 l)
{
#if MAPROM_DEBUG
write_log(_T("MAPROM LPUT %08x %08x %d %08x\n"), addr, l, maprom_state, M68K_GETPC);
#endif
uae_u32 *m;
if (is_blizzard2060(&currprefs) && !maprom_state)
return;
addr &= blizzardmaprom_bank.mask;
m = (uae_u32 *)(blizzardmaprom_bank.baseaddr + addr);
do_put_mem_long(m, l);
if (maprom_state > 0 && !(addr & 0x80000)) {
no_rom_protect();
m = (uae_u32 *)(kickmem_bank.baseaddr + addr);
do_put_mem_long(m, l);
}
}
static void REGPARAM2 blizzardmaprom_wput(uaecptr addr, uae_u32 w)
{
#if MAPROM_DEBUG
write_log(_T("MAPROM WPUT %08x %08x %d\n"), addr, w, maprom_state);
#endif
uae_u16 *m;
if (is_blizzard2060(&currprefs) && !maprom_state)
return;
addr &= blizzardmaprom_bank.mask;
m = (uae_u16 *)(blizzardmaprom_bank.baseaddr + addr);
do_put_mem_word(m, w);
if (maprom_state > 0 && !(addr & 0x80000)) {
no_rom_protect();
m = (uae_u16 *)(kickmem_bank.baseaddr + addr);
do_put_mem_word(m, w);
}
}
static void REGPARAM2 blizzardmaprom_bput(uaecptr addr, uae_u32 b)
{
#if MAPROM_DEBUG
write_log(_T("MAPROM LPUT %08x %08x %d\n"), addr, b, maprom_state);
#endif
if (is_blizzard2060(&currprefs) && !maprom_state)
return;
addr &= blizzardmaprom_bank.mask;
blizzardmaprom_bank.baseaddr[addr] = b;
if (maprom_state > 0 && !(addr & 0x80000)) {
no_rom_protect();
kickmem_bank.baseaddr[addr] = b;
}
}
MEMORY_CHECK(blizzardea);
MEMORY_XLATE(blizzardea);
static void blizzardf0_slow(int size)
{
if (is_blizzard(&currprefs) || is_blizzardppc(&currprefs) || is_blizzard2060(&currprefs)) {
if (size == 4)
regs.memory_waitstate_cycles += F0_WAITSTATES * 6;
else if (size == 2)
regs.memory_waitstate_cycles += F0_WAITSTATES * 3;
else
regs.memory_waitstate_cycles += F0_WAITSTATES * 1;
}
}
static int REGPARAM2 blizzarde8_check(uaecptr addr, uae_u32 size)
{
return 0;
}
static uae_u8 *REGPARAM2 blizzarde8_xlate(uaecptr addr)
{
return NULL;
}
static uae_u32 REGPARAM2 blizzardf0_bget(uaecptr addr)
{
uae_u8 v;
blizzardf0_slow(1);
if (is_csmk3(&currprefs) || is_blizzardppc(&currprefs)) {
if (flash_unlocked) {
return flash_read(flashrom, addr);
}
} else if (is_csmk2(&currprefs)) {
addr &= 65535;
addr += 65536;
return flash_read(flashrom, addr);
} else if (is_csmk1(&currprefs)) {
addr &= 65535;
addr += 65536;
return flash_read(flashrom, addr);
} else if (is_dkb_wildfire(&currprefs)) {
if (flash_unlocked) {
if (addr & 1)
return flash_read(flashrom2, addr);
else
return flash_read(flashrom, addr);
}
}
addr &= blizzardf0_bank.mask;
v = blizzardf0_bank.baseaddr[addr];
return v;
}
static uae_u32 REGPARAM2 blizzardf0_lget(uaecptr addr)
{
uae_u32 *m;
//write_log(_T("F0 LONGGET %08x\n"), addr);
blizzardf0_slow(4);
addr &= blizzardf0_bank.mask;
m = (uae_u32 *)(blizzardf0_bank.baseaddr + addr);
return do_get_mem_long(m);
}
static uae_u32 REGPARAM2 blizzardf0_wget(uaecptr addr)
{
uae_u16 *m, v;
blizzardf0_slow(2);
if (is_dkb_wildfire(&currprefs) && flash_unlocked) {
v = blizzardf0_bget(addr + 0) << 8;
v |= blizzardf0_bget(addr + 1);
} else {
addr &= blizzardf0_bank.mask;
m = (uae_u16 *)(blizzardf0_bank.baseaddr + addr);
v = do_get_mem_word(m);
}
return v;
}
static void REGPARAM2 blizzardf0_bput(uaecptr addr, uae_u32 b)
{
blizzardf0_slow(1);
if (is_csmk3(&currprefs) || is_blizzardppc(&currprefs)) {
if (flash_unlocked) {
flash_write(flashrom, addr, b);
}
} else if (is_csmk2(&currprefs)) {
addr &= 65535;
addr += 65536;
addr &= ~3;
addr |= csmk2_flashaddressing;
flash_write(flashrom, addr, b);
} else if (is_csmk1(&currprefs)) {
addr &= 65535;
addr += 65536;
flash_write(flashrom, addr, b);
} else if (is_dkb_wildfire(&currprefs)) {
if (flash_unlocked) {
if (addr & 1)
flash_write(flashrom2, addr, b);
else
flash_write(flashrom, addr, b);
}
}
}
static void REGPARAM2 blizzardf0_lput(uaecptr addr, uae_u32 b)
{
blizzardf0_slow(4);
}
static void REGPARAM2 blizzardf0_wput(uaecptr addr, uae_u32 b)
{
blizzardf0_slow(2);
if (is_dkb_wildfire(&currprefs)) {
blizzardf0_bput(addr + 0, b >> 8);
blizzardf0_bput(addr + 1, b >> 0);
}
}
MEMORY_CHECK(blizzardf0);
MEMORY_XLATE(blizzardf0);
static uae_u32 REGPARAM2 blizzardea_lget(uaecptr addr)
{
uae_u32 v = 0;
if (cpuboard_non_byte_ea) {
v = blizzardea_bget(addr + 0) << 24;
v |= blizzardea_bget(addr + 1) << 16;
v |= blizzardea_bget(addr + 2) << 8;
v |= blizzardea_bget(addr + 3) << 0;
}
return v;
}
static uae_u32 REGPARAM2 blizzardea_wget(uaecptr addr)
{
uae_u32 v = 0;
if (cpuboard_non_byte_ea) {
v = blizzardea_bget(addr + 0) << 8;
v |= blizzardea_bget(addr + 1) << 0;
}
return v;
}
static uae_u32 REGPARAM2 blizzardea_bget(uaecptr addr)
{
uae_u8 v = 0;
addr &= blizzardea_bank.mask;
if (is_tekmagic(&currprefs)) {
cpuboard_non_byte_ea = true;
v = cpuboard_ncr710_io_bget(addr);
} else if (is_quikpak(&currprefs)) {
cpuboard_non_byte_ea = true;
v = cpuboard_ncr720_io_bget(addr);
} else if (is_blizzard2060(&currprefs) && addr >= BLIZZARD_2060_SCSI_OFFSET) {
v = cpuboard_ncr9x_scsi_get(addr);
} else if (is_blizzard1230mk2(&currprefs) && addr >= 0x10000 && (currprefs.cpuboard_settings & 2)) {
v = cpuboard_ncr9x_scsi_get(addr);
} else if (is_blizzard(&currprefs)) {
if (addr & BLIZZARD_SCSI_KIT4_SCSI_OFFSET)
v = cpuboard_ncr9x_scsi_get(addr);
else
v = blizzardea_bank.baseaddr[addr];
} else if (is_blizzard1230mk3(&currprefs)) {
if (addr & BLIZZARD_SCSI_KIT3_SCSI_OFFSET)
v = cpuboard_ncr9x_scsi_get(addr);
else
v = blizzardea_bank.baseaddr[addr];
} else if (is_csmk1(&currprefs)) {
if (addr >= CYBERSTORM_MK1_SCSI_OFFSET) {
v = cpuboard_ncr9x_scsi_get(addr);
} else if (flash_active(flashrom, addr)) {
v = flash_read(flashrom, addr);
} else {
v = blizzardea_bank.baseaddr[addr];
}
} else if (is_csmk2(&currprefs)) {
if (addr >= CYBERSTORM_MK2_SCSI_OFFSET) {
v = cpuboard_ncr9x_scsi_get(addr);
} else if (flash_active(flashrom, addr)) {
v = flash_read(flashrom, addr);
} else {
v = blizzardea_bank.baseaddr[addr];
}
} else {
v = blizzardea_bank.baseaddr[addr];
}
return v;
}
static void REGPARAM2 blizzardea_lput(uaecptr addr, uae_u32 l)
{
if (cpuboard_non_byte_ea) {
blizzardea_bput(addr + 0, l >> 24);
blizzardea_bput(addr + 1, l >> 16);
blizzardea_bput(addr + 2, l >> 8);
blizzardea_bput(addr + 3, l >> 0);
}
}
static void REGPARAM2 blizzardea_wput(uaecptr addr, uae_u32 w)
{
if (cpuboard_non_byte_ea) {
blizzardea_bput(addr + 0, w >> 8);
blizzardea_bput(addr + 1, w >> 0);
}
}
static void REGPARAM2 blizzardea_bput(uaecptr addr, uae_u32 b)
{
addr &= blizzardea_bank.mask;
if (is_tekmagic(&currprefs)) {
cpuboard_non_byte_ea = true;
cpuboard_ncr710_io_bput(addr, b);
} else if (is_quikpak(&currprefs)) {
cpuboard_non_byte_ea = true;
cpuboard_ncr720_io_bput(addr, b);
} else if (is_blizzard1230mk2(&currprefs) && addr >= 0x10000 && (currprefs.cpuboard_settings & 2)) {
cpuboard_ncr9x_scsi_put(addr, b);
} else if (is_blizzard2060(&currprefs) && addr >= BLIZZARD_2060_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else if ((is_blizzard(&currprefs)) && addr >= BLIZZARD_SCSI_KIT4_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else if ((is_blizzard1230mk3(&currprefs)) && addr >= BLIZZARD_SCSI_KIT3_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else if (is_csmk1(&currprefs)) {
if (addr >= CYBERSTORM_MK1_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else {
flash_write(flashrom, addr, b);
}
} else if (is_csmk2(&currprefs)) {
if (addr >= CYBERSTORM_MK2_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else {
addr &= ~3;
addr |= csmk2_flashaddressing;
flash_write(flashrom, addr, b);
}
} else if (is_mtec_ematrix530(&currprefs) || is_dce_typhoon2(&currprefs)) {
if (cpuboardmem1_bank.allocated_size < 128 * 1024 * 1024 / 2) {
if (cpuboardmem2_bank.allocated_size)
map_banks(&cpuboardmem2_bank, (0x18000000 + cpuboardmem1_bank.allocated_size) >> 16, cpuboardmem2_bank.allocated_size >> 16, 0);
else
map_banks(&dummy_bank, (0x18000000 + cpuboardmem1_bank.allocated_size) >> 16, cpuboardmem1_bank.allocated_size >> 16, 0);
}
}
}
static void REGPARAM2 blizzarde8_lput(uaecptr addr, uae_u32 b)
{
}
static void REGPARAM2 blizzarde8_wput(uaecptr addr, uae_u32 b)
{
}
static void REGPARAM2 blizzarde8_bput(uaecptr addr, uae_u32 b)
{
b &= 0xff;
addr &= 65535;
if (addr == 0x48 && !configured) {
uae_u32 size = map_banks_z2_autosize(&blizzardea_bank, b);
write_log(_T("Accelerator Z2 board autoconfigured at %02X0000, size %08x\n"), b, size);
configured = 1;
expamem_next (&blizzardea_bank, NULL);
return;
}
if (addr == 0x4c && !configured) {
write_log(_T("Blizzard Z2 SHUT-UP!\n"));
configured = 1;
expamem_next (NULL, NULL);
return;
}
}
static uae_u32 REGPARAM2 blizzarde8_bget(uaecptr addr)
{
uae_u32 v = 0xffff;
v = blizzardea_bank.baseaddr[addr & blizzardea_bank.mask];
return v;
}
static uae_u32 REGPARAM2 blizzarde8_wget(uaecptr addr)
{
uae_u32 v = 0xffff;
v = (blizzardea_bank.baseaddr[addr & blizzardea_bank.mask] << 8) | blizzardea_bank.baseaddr[(addr + 1) & blizzardea_bank.mask];
return v;
}
static uae_u32 REGPARAM2 blizzarde8_lget(uaecptr addr)
{
uae_u32 v = 0xffff;
v = (blizzarde8_wget(addr) << 16) | blizzarde8_wget(addr + 2);
return v;
}
static void blizzard_copymaprom(void)
{
if (!maprom_state) {
reload_roms();
} else {
uae_u8 *src = NULL;
if (is_blizzardppc(&currprefs)) {
src = blizzardram_bank.baseaddr + cpuboard_size - 524288;
} else {
src = blizzardmaprom_bank.baseaddr;
}
if (src) {
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
if (is_blizzard1230mk2(&currprefs) && cpuboard_size >= 64 * 1024 * 1024) {
map_banks(&blizzardmaprom_bank, BLIZZARDMK2_MAPROM_BASE >> 16, 524288 >> 16, 0);
}
if (is_blizzard(&currprefs) && cpuboard_size >= 256 * 1024 * 1024) {
map_banks(&blizzardmaprom_bank, BLIZZARDMK4_MAPROM_BASE >> 16, 524288 >> 16, 0);
}
}
}
static void cyberstorm_copymaprom(void)
{
if (!maprom_state) {
reload_roms();
} else if (blizzardmaprom_bank.baseaddr) {
uae_u8 *src = blizzardmaprom_bank.baseaddr;
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
}
static void cyberstormmk2_copymaprom(void)
{
if (a3000hmem_bank.baseaddr) {
uae_u8 *src = a3000hmem_bank.baseaddr + a3000hmem_bank.allocated_size - 524288;
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
}
static void cyberstormmk1_copymaprom(void)
{
if (blizzardmaprom_bank.baseaddr) {
uae_u8 *src = blizzardmaprom_bank.baseaddr;
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}
}
static void csamagnum40_domaprom(void)
{
if (!maprom_state) {
reload_roms();
} else if (a3000hmem_bank.baseaddr && a3000hmem_bank.allocated_size >= 0x1000000) {
uae_u8 *src = a3000hmem_bank.baseaddr + 0xf80000;
uae_u8 *dst = kickmem_bank.baseaddr;
protect_roms(false);
memcpy(dst, src, 524288);
protect_roms(true);
set_roms_modified();
}