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mx50_rdp.c
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mx50_rdp.c
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/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mx50.h>
#include <asm/arch/mx50_pins.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <asm/sizes.h>
#ifdef CONFIG_IMX_CSPI
#include <imx_spi.h>
#include <asm/arch/imx_spi_pmic.h>
#endif
#if CONFIG_I2C_MXC
#include <i2c.h>
#endif
#ifdef CONFIG_CMD_MMC
#include <mmc.h>
#include <fsl_esdhc.h>
#endif
#ifdef CONFIG_ARCH_MMU
#include <asm/mmu.h>
#include <asm/arch/mmu.h>
#endif
#ifdef CONFIG_CMD_CLOCK
#include <asm/clock.h>
#endif
#ifdef CONFIG_MXC_EPDC
#include <lcd.h>
#endif
#ifdef CONFIG_ANDROID_RECOVERY
#include "../common/recovery.h"
#include <part.h>
#include <ext2fs.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <ubi_uboot.h>
#include <jffs2/load_kernel.h>
#endif
#include "ntx_comm.h"
#include "ntx_comm.c"
#include "ntx_hwconfig.h"
extern NTX_HWCONFIG *gptNtxHwCfg ;
#ifdef CONFIG_I2C_MULTI_BUS//[
I2C_PLATFORM_DATA gtI2C_platform_dataA[] = {
{I2C1_BASE_ADDR,50000,0xfe,0},
{I2C2_BASE_ADDR,200000,0xfe,0},
{I2C3_BASE_ADDR,100000,0xfe,0},
};
unsigned int gdwBusNum=2; //default BUS is I2C3 .
#endif //CONFIG_I2C_MULTI_BUS
DECLARE_GLOBAL_DATA_PTR;
static u32 system_rev;
static enum boot_device boot_dev;
static GPIO_OUT gt_ntx_gpio_spd_en= {
MX50_PIN_ECSPI1_MOSI, // pin name .
IOMUX_CONFIG_ALT1, // pin config .
0, // pad config .
4, // gpio group .
13, // gpio number .
1, // output value .
0, // not inited .
"SPD_EN",
};
static GPIO_KEY_BTN gt_ntx_gpio_home_key= {
MX50_PIN_KEY_ROW0, // pin name .
IOMUX_CONFIG_ALT1, // pin config .
//PAD_CTL_100K_PU|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE|PAD_CTL_DRV_HIGH, // pad config .
0, // pad config .
4, // gpio group .
1, // gpio number .
0, // key down value .
0, // not inited .
"[HOME]",
};
static GPIO_KEY_BTN gt_ntx_gpio_fl_key= {
MX50_PIN_EPDC_BDR0, // pin name .
IOMUX_CONFIG_ALT1, // pin config .
PAD_CTL_100K_PU|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE|PAD_CTL_DRV_HIGH, // pad config .
4, // gpio group .
23, // gpio number .
0, // key down value .
0, // not inited .
"[FL]",
};
static GPIO_KEY_BTN gt_ntx_gpio_hallsensor_key= {
MX50_PIN_SD3_D5, // pin name .
IOMUX_CONFIG_ALT1, // pin config .
0, // pad config .
5, // gpio group .
25, // gpio number .
0, // not inited .
0, // key down value .
"[HALL]",
};
static GPIO_KEY_BTN gt_ntx_gpio_5_15_hallsensor_key= {
MX50_PIN_SD2_D7, // pin name .
IOMUX_CONFIG_ALT1, // pin config .
0, // pad config .
5, // gpio group .
15, // gpio number .
0, // not inited .
0, // key down value .
"[HALL]",
};
GPIO_KEY_BTN * ntx_gpio_keysA[] = {
>_ntx_gpio_home_key,
>_ntx_gpio_fl_key,
// >_ntx_gpio_hallsensor_key,
};
int gi_ntx_gpio_keys=sizeof(ntx_gpio_keysA)/sizeof(ntx_gpio_keysA[0]);
static inline void setup_boot_device(void)
{
uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
switch (bt_mem_ctl) {
case 0x0:
if (bt_mem_type)
boot_dev = ONE_NAND_BOOT;
else
boot_dev = WEIM_NOR_BOOT;
break;
case 0x2:
if (bt_mem_type)
boot_dev = SATA_BOOT;
else
boot_dev = PATA_BOOT;
break;
case 0x3:
if (bt_mem_type)
boot_dev = SPI_NOR_BOOT;
else
boot_dev = I2C_BOOT;
break;
case 0x4:
case 0x5:
boot_dev = SD_BOOT;
break;
case 0x6:
case 0x7:
boot_dev = MMC_BOOT;
break;
case 0x8 ... 0xf:
boot_dev = NAND_BOOT;
break;
default:
boot_dev = UNKNOWN_BOOT;
break;
}
}
enum boot_device get_boot_device(void)
{
return boot_dev;
}
u32 get_board_rev(void)
{
return system_rev;
}
static inline void setup_soc_rev(void)
{
int reg = __REG(ROM_SI_REV);
switch (reg) {
case 0x10:
system_rev = 0x50000 | CHIP_REV_1_0;
break;
case 0x11:
system_rev = 0x50000 | CHIP_REV_1_1_1;
break;
default:
system_rev = 0x50000 | CHIP_REV_1_1_1;
}
}
static inline void set_board_rev(int rev)
{
system_rev |= (rev & 0xF) << 8;
}
static inline void setup_board_rev(void)
{
#if defined(CONFIG_MX50_RD3)
unsigned int reg;
set_board_rev(0x3);
/* IO init for RD3 */
// disable HDMI_PWR
reg = readl(GPIO1_BASE_ADDR + GPIO_DR);
reg &= (~(1<<25));
writel(reg, GPIO1_BASE_ADDR + GPIO_DR);
reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR);
reg |= (1<<25);
writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR);
mxc_request_iomux(MX50_PIN_EIM_RW, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX50_PIN_EIM_RW, 0x84);
#endif
}
static inline void setup_arch_id(void)
{
#if defined(CONFIG_MX50_RDP) || defined(CONFIG_MX50_RD3)
gd->bd->bi_arch_number = MACH_TYPE_MX50_RDP;
#elif defined(CONFIG_MX50_ARM2)
gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2;
#else
# error "Unsupported board!"
#endif
}
inline int is_soc_rev(int rev)
{
return (system_rev & 0xFF) - rev;
}
#ifdef CONFIG_ARCH_MMU
void board_mmu_init(void)
{
unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
unsigned long i;
/*
* Set the TTB register
*/
asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
/*
* Set the Domain Access Control Register
*/
i = ARM_ACCESS_DACR_DEFAULT;
asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
/*
* First clear all TT entries - ie Set them to Faulting
*/
memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
/* Actual Virtual Size Attributes Function */
/* Base Base MB cached? buffered? access permissions */
/* xxx00000 xxx00000 */
X_ARM_MMU_SECTION(0x000, 0x000, 0x10,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* IRAM */
X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* SATA */
X_ARM_MMU_SECTION(0x180, 0x180, 0x100,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* GPU */
X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* periperals */
X_ARM_MMU_SECTION(0x700, 0x700, 0x400,
ARM_CACHEABLE, ARM_BUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
X_ARM_MMU_SECTION(0x700, 0xB00, 0x400,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* iRam */
/* Workaround for arm errata #709718 */
/* Setup PRRR so device is always mapped to non-shared */
asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
i &= (~(3 << 0x10));
asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
/* Enable MMU */
MMU_ON();
}
#endif
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
static void setup_uart(void)
{
unsigned int reg;
#if defined(CONFIG_MX50_RD3)
/* UART3 TXD */
mxc_request_iomux(MX50_PIN_UART3_TXD, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX50_PIN_UART3_TXD, 0x1E4);
/* Enable UART1 */
reg = readl(GPIO6_BASE_ADDR + 0x0);
reg |= (1 << 14);
writel(reg, GPIO6_BASE_ADDR + 0x0);
reg = readl(GPIO6_BASE_ADDR + 0x4);
reg |= (1 << 14);
writel(reg, GPIO6_BASE_ADDR + 0x4);
#endif
#ifdef CONFIG_MX50_E606XX
/* UART2 RXD */
mxc_request_iomux(MX50_PIN_UART2_RXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_UART2_RXD, 0x1E4);
mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
/* UART2 TXD */
mxc_request_iomux(MX50_PIN_UART2_TXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_UART2_TXD, 0x1E4);
#else
/* UART1 RXD */
mxc_request_iomux(MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_UART1_RXD, 0x1E4);
mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
/* UART1 TXD */
mxc_request_iomux(MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_UART1_TXD, 0x1E4);
#endif
}
static void _init_tps65185_power(int iIsWakeup,int iIsActivePwr)
{
char cCmdA[256];
int iCur_I2C_Chn;
//ASSERT(O_pbRegVal);
//
if(!gptNtxHwCfg) {
printf("%s(): cannot init without hwconfig !\n",__FUNCTION__);
return ;
}
if(6==gptNtxHwCfg->m_val.bDisplayCtrl) {
printf("init TPS65185 power ...\n");
iCur_I2C_Chn=(int)(gdwBusNum+1);
// Display controller is MX50+TPS65185 .
// EPD PMIC power ...
// power on the PMIC ...
mxc_request_iomux(MX50_PIN_EIM_CRE,
IOMUX_CONFIG_ALT1);
//mxc_iomux_set_pad(MX50_PIN_EIM_CRE, 0);
{
unsigned int reg;
// set output .
reg = readl(GPIO1_BASE_ADDR + 0x4);
reg |= (0x1 << 27);
writel(reg, GPIO1_BASE_ADDR + 0x4);
// output high .
reg = readl(GPIO1_BASE_ADDR + 0x0);
reg &= ~(0x1 << 27);
writel(reg, GPIO1_BASE_ADDR + 0x0);
udelay(50*1000);
// output high .
reg = readl(GPIO1_BASE_ADDR + 0x0);
reg |= (0x1 << 27);
writel(reg, GPIO1_BASE_ADDR + 0x0);
udelay(50*1000);
}
{
// set PMIC into STANBY mode ...
// EPD_PWRCTRL0 (WAKEUP)
mxc_request_iomux(MX50_PIN_EPDC_PWRCTRL0,
IOMUX_CONFIG_ALT1);
//mxc_iomux_set_pad(MX50_PIN_EPDC_PWRCTRL0, 0);
{
unsigned int reg;
// set output .
reg = readl(GPIO3_BASE_ADDR + 0x4);
reg |= (0x1 << 29);
writel(reg, GPIO3_BASE_ADDR + 0x4);
reg = readl(GPIO3_BASE_ADDR + 0x0);
if(iIsWakeup) {
reg |= (0x1 << 29);
}
else {
reg &= ~(0x1 << 29);
}
writel(reg, GPIO3_BASE_ADDR + 0x0);
}
udelay(50*1000);
}
{
// EPD_PWRCTRL1 (PWRUP)
mxc_request_iomux(MX50_PIN_EPDC_PWRCTRL1,
IOMUX_CONFIG_ALT1);
//mxc_iomux_set_pad(MX50_PIN_EPDC_PWRCTRL1, 0);
{
unsigned int reg;
// set output .
reg = readl(GPIO3_BASE_ADDR + 0x4);
reg |= (0x1 << 30);
writel(reg, GPIO3_BASE_ADDR + 0x4);
reg = readl(GPIO3_BASE_ADDR + 0x0);
if(iIsActivePwr) {
reg |= (0x1 << 30);
}
else {
reg &= ~(0x1 << 30);
}
writel(reg, GPIO3_BASE_ADDR + 0x0);
}
udelay(5*1000);
}
}
}
#ifdef CONFIG_I2C_MXC
static void setup_i2c(unsigned int module_base)
{
int iI2C_Chn=-1;
switch (module_base) {
case I2C1_BASE_ADDR:
iI2C_Chn=1;
/* i2c1 SDA */
mxc_request_iomux(MX50_PIN_I2C1_SDA,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU |
PAD_CTL_HYS_ENABLE|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE);
/* i2c1 SCL */
mxc_request_iomux(MX50_PIN_I2C1_SCL,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU |
PAD_CTL_HYS_ENABLE|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE);
break;
case I2C2_BASE_ADDR:
iI2C_Chn=2;
/* i2c2 SDA */
mxc_request_iomux(MX50_PIN_I2C2_SDA,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C2_SDA,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU |
PAD_CTL_HYS_ENABLE|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE);
/* i2c2 SCL */
mxc_request_iomux(MX50_PIN_I2C2_SCL,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C2_SCL,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU |
PAD_CTL_HYS_ENABLE|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE);
break;
case I2C3_BASE_ADDR:
iI2C_Chn=3;
/* i2c3 SDA */
mxc_request_iomux(MX50_PIN_I2C3_SDA,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C3_SDA,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU |
PAD_CTL_HYS_ENABLE|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE);
/* i2c3 SCL */
mxc_request_iomux(MX50_PIN_I2C3_SCL,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C3_SCL,
PAD_CTL_SRE_FAST |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU |
PAD_CTL_HYS_ENABLE|PAD_CTL_PUE_PULL|PAD_CTL_PKE_ENABLE);
break;
default:
printf("Invalid I2C base: 0x%x\n", module_base);
break;
}
//
// devices power initialize ...
//
if(IS_I2C_CHN_TPS65185(iI2C_Chn)) {
_init_tps65185_power(1,0);
}
}
#endif
#ifdef CONFIG_IMX_CSPI
s32 spi_get_cfg(struct imx_spi_dev_t *dev)
{
switch (dev->slave.cs) {
case 0:
/* PMIC */
dev->base = CSPI3_BASE_ADDR;
dev->freq = 25000000;
dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
dev->ss = 0;
dev->fifo_sz = 32;
dev->us_delay = 0;
break;
case 1:
/* SPI-NOR */
dev->base = CSPI3_BASE_ADDR;
dev->freq = 25000000;
dev->ss_pol = IMX_SPI_ACTIVE_LOW;
dev->ss = 1;
dev->fifo_sz = 32;
dev->us_delay = 0;
break;
default:
printf("Invalid Bus ID!\n");
}
return 0;
}
void spi_io_init(struct imx_spi_dev_t *dev)
{
switch (dev->base) {
case CSPI3_BASE_ADDR:
mxc_request_iomux(MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_CSPI_MOSI, 0x4);
mxc_request_iomux(MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_CSPI_MISO, 0x4);
if (dev->ss == 0) {
/* de-select SS1 of instance: cspi */
mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_CSPI_SS0, 0xE4);
} else if (dev->ss == 1) {
/* de-select SS0 of instance: cspi */
mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_ECSPI1_MOSI, 0xE4);
mxc_iomux_set_input(
MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, 0x1);
}
mxc_request_iomux(MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_CSPI_SCLK, 0x4);
break;
case CSPI2_BASE_ADDR:
case CSPI1_BASE_ADDR:
/* ecspi1-2 fall through */
break;
default:
break;
}
}
#endif
#ifdef CONFIG_NAND_GPMI
void setup_gpmi_nand(void)
{
u32 src_sbmr = readl(SRC_BASE_ADDR + 0x4);
/* Fix for gpmi gatelevel issue */
mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0x00e4);
/* RESETN,WRN,RDN,DATA0~7 Signals iomux*/
/* Check if 1.8v NAND is to be supported */
if ((src_sbmr & 0x00000004) >> 2)
*(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x58) = (0x1 << 13);
/* RESETN */
mxc_request_iomux(MX50_PIN_SD3_WP, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_WP, PAD_CTL_DRV_HIGH);
/* WRN */
mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_CMD, PAD_CTL_DRV_HIGH);
/* RDN */
mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_CLK, PAD_CTL_DRV_HIGH);
/* D0 */
mxc_request_iomux(MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D4, PAD_CTL_DRV_HIGH);
/* D1 */
mxc_request_iomux(MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D5, PAD_CTL_DRV_HIGH);
/* D2 */
mxc_request_iomux(MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D6, PAD_CTL_DRV_HIGH);
/* D3 */
mxc_request_iomux(MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D7, PAD_CTL_DRV_HIGH);
/* D4 */
mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D0, PAD_CTL_DRV_HIGH);
/* D5 */
mxc_request_iomux(MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D1, PAD_CTL_DRV_HIGH);
/* D6 */
mxc_request_iomux(MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D2, PAD_CTL_DRV_HIGH);
/* D7 */
mxc_request_iomux(MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_SD3_D3, PAD_CTL_DRV_HIGH);
/*CE0~3,and other four controls signals muxed on KPP*/
switch ((src_sbmr & 0x00000018) >> 3) {
case 0:
/* Muxed on key */
if ((src_sbmr & 0x00000004) >> 2)
*(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x20) =
(0x1 << 13);
/* CLE */
mxc_request_iomux(MX50_PIN_KEY_COL0, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_COL0, PAD_CTL_DRV_HIGH);
/* ALE */
mxc_request_iomux(MX50_PIN_KEY_ROW0, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_ROW0, PAD_CTL_DRV_HIGH);
/* READY0 */
mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_COL3,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU);
mxc_iomux_set_input(
MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
INPUT_CTL_PATH0);
/* DQS */
mxc_request_iomux(MX50_PIN_KEY_ROW3, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_ROW3, PAD_CTL_DRV_HIGH);
mxc_iomux_set_input(
MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
INPUT_CTL_PATH0);
/* CE0 */
mxc_request_iomux(MX50_PIN_KEY_COL1, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_COL1, PAD_CTL_DRV_HIGH);
/* CE1 */
mxc_request_iomux(MX50_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_ROW1, PAD_CTL_DRV_HIGH);
/* CE2 */
mxc_request_iomux(MX50_PIN_KEY_COL2, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_COL2, PAD_CTL_DRV_HIGH);
/* CE3 */
mxc_request_iomux(MX50_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
break;
case 1:
if ((src_sbmr & 0x00000004) >> 2)
*(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0xc) =
(0x1 << 13);
/* CLE */
mxc_request_iomux(MX50_PIN_EIM_DA8, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA8, PAD_CTL_DRV_HIGH);
/* ALE */
mxc_request_iomux(MX50_PIN_EIM_DA9, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA9, PAD_CTL_DRV_HIGH);
/* READY0 */
mxc_request_iomux(MX50_PIN_EIM_DA14, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA14,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU);
mxc_iomux_set_input(
MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
INPUT_CTL_PATH2);
/* DQS */
mxc_request_iomux(MX50_PIN_EIM_DA15, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA15, PAD_CTL_DRV_HIGH);
mxc_iomux_set_input(
MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
INPUT_CTL_PATH2);
/* CE0 */
mxc_request_iomux(MX50_PIN_EIM_DA10, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA10, PAD_CTL_DRV_HIGH);
/* CE1 */
mxc_request_iomux(MX50_PIN_EIM_DA11, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA11, PAD_CTL_DRV_HIGH);
/* CE2 */
mxc_request_iomux(MX50_PIN_EIM_DA12, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA12, PAD_CTL_DRV_HIGH);
/* CE3 */
mxc_request_iomux(MX50_PIN_EIM_DA13, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA13, PAD_CTL_DRV_HIGH);
break;
case 2:
if ((src_sbmr & 0x00000004) >> 2)
*(u32 *)(IOMUXC_BASE_ADDR + PAD_GRP_START + 0x48) =
(0x1 << 13);
/* CLE */
mxc_request_iomux(MX50_PIN_DISP_D8, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D8, PAD_CTL_DRV_HIGH);
/* ALE */
mxc_request_iomux(MX50_PIN_DISP_D9, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D9, PAD_CTL_DRV_HIGH);
/* READY0 */
mxc_request_iomux(MX50_PIN_DISP_D14, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D14,
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU);
mxc_iomux_set_input(
MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
/* DQS */
mxc_request_iomux(MX50_PIN_DISP_D15, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D15, PAD_CTL_DRV_HIGH);
mxc_iomux_set_input(
MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
INPUT_CTL_PATH1);
/* CE0 */
mxc_request_iomux(MX50_PIN_DISP_D10, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D10, PAD_CTL_DRV_HIGH);
/* CE1 */
mxc_request_iomux(MX50_PIN_EIM_DA11, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_EIM_DA11, PAD_CTL_DRV_HIGH);
/* CE2 */
mxc_request_iomux(MX50_PIN_DISP_D12, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D12, PAD_CTL_DRV_HIGH);
/* CE3 */
mxc_request_iomux(MX50_PIN_DISP_D13, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D13, PAD_CTL_DRV_HIGH);
break;
default:
break;
}
}
#endif
#ifdef CONFIG_MXC_FEC
#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
#define HW_OCOTP_MACn(n) (0x00000250 + (n) * 0x10)
int fec_get_mac_addr(unsigned char *mac)
{
u32 *ocotp_mac_base =
(u32 *)(OCOTP_CTRL_BASE_ADDR + HW_OCOTP_MACn(0));
int i;
for (i = 0; i < 6; ++i, ++ocotp_mac_base)
mac[6 - 1 - i] = readl(++ocotp_mac_base);
return 0;
}
#endif
static void setup_fec(void)
{
volatile unsigned int reg;
#if defined(CONFIG_MX50_RDP)
/* FEC_EN: gpio6-23 set to 0 to enable FEC */
mxc_request_iomux(MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT1);
reg = readl(GPIO6_BASE_ADDR + 0x0);
reg &= ~(1 << 23);
writel(reg, GPIO6_BASE_ADDR + 0x0);
reg = readl(GPIO6_BASE_ADDR + 0x4);
reg |= (1 << 23);
writel(reg, GPIO6_BASE_ADDR + 0x4);
#elif defined(CONFIG_MX50_RD3)
/* FEC_EN: gpio4-15 set to 0 to enable FEC */
mxc_request_iomux(MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT1);
reg = readl(GPIO4_BASE_ADDR + 0x0);
reg |= (1 << 15);
writel(reg, GPIO4_BASE_ADDR + 0x0);
reg = readl(GPIO4_BASE_ADDR + 0x4);
reg |= (1 << 15);
writel(reg, GPIO4_BASE_ADDR + 0x4);
#endif
/*FEC_MDIO*/
mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6);
mxc_iomux_set_pad(MX50_PIN_SSI_RXC, 0xC);
mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
/*FEC_MDC*/
mxc_request_iomux(MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6);
mxc_iomux_set_pad(MX50_PIN_SSI_RXFS, 0x004);
/* FEC RXD1 */
mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D3, 0x0);
mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, 0x0);
/* FEC RXD0 */
mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D4, 0x0);
mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, 0x0);
/* FEC TXD1 */
mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D6, 0x004);
/* FEC TXD0 */
mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D7, 0x004);
/* FEC TX_EN */
mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D5, 0x004);
/* FEC TX_CLK */
mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D0, 0x0);
mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, 0x0);
/* FEC RX_ER */
mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D1, 0x0);
mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, 0);
/* FEC CRS */
mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0);
mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0);
#if defined(CONFIG_MX50_RDP) || defined(CONFIG_MX50_RD3)
/* FEC_RESET_B: gpio4-12 */
mxc_request_iomux(MX50_PIN_ECSPI1_SCLK, IOMUX_CONFIG_ALT1);
reg = readl(GPIO4_BASE_ADDR + 0x0);
reg &= ~(1 << 12);
writel(reg, GPIO4_BASE_ADDR + 0x0);
reg = readl(GPIO4_BASE_ADDR + 0x4);
reg |= (1 << 12);
writel(reg, GPIO4_BASE_ADDR + 0x4);
udelay(500);
reg = readl(GPIO4_BASE_ADDR + 0x0);
reg |= (1 << 12);
writel(reg, GPIO4_BASE_ADDR + 0x0);
#elif defined(CONFIG_MX50_ARM2)
/* phy reset: gpio4-6 */
mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1);
reg = readl(GPIO4_BASE_ADDR + 0x0);
reg &= ~0x40;
writel(reg, GPIO4_BASE_ADDR + 0x0);
reg = readl(GPIO4_BASE_ADDR + 0x4);
reg |= 0x40;
writel(reg, GPIO4_BASE_ADDR + 0x4);
udelay(500);
reg = readl(GPIO4_BASE_ADDR + 0x0);
reg |= 0x40;
writel(reg, GPIO4_BASE_ADDR + 0x0);
#else
# error "Unsupported board!"
#endif
}
#endif
#ifdef CONFIG_CMD_MMC
struct fsl_esdhc_cfg esdhc_cfg[3] = {
{MMC_SDHC1_BASE_ADDR, 1, 1},
{MMC_SDHC2_BASE_ADDR, 1, 1},
{MMC_SDHC3_BASE_ADDR, 1, 1},
};
#ifdef CONFIG_DYNAMIC_MMC_DEVNO
int get_mmc_env_devno(void)
{
uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
int mmc_devno = 0;
switch (soc_sbmr & 0x00300000) {
default:
case 0x0:
mmc_devno = 0;
break;
case 0x00100000:
mmc_devno = 1;
break;
case 0x00200000:
mmc_devno = 2;
break;
}
return mmc_devno;
}
#endif