teensy-tinyfpga-cache.lib

EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_AudioJack3_SwitchTR
#
DEF Connector_AudioJack3_SwitchTR J 0 20 Y Y 1 F N
F0 "J" 0 350 50 H V C CNN
F1 "Connector_AudioJack3_SwitchTR" 0 250 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Jack*
$ENDFPLIST
DRAW
S -200 -200 -250 -300 0 1 10 F
S 100 150 -200 -400 0 1 10 f
P 2 0 1 0 20 -10 30 -30 N
P 2 0 1 0 70 -210 80 -230 N
P 4 0 1 10 0 -200 25 -225 50 -200 100 -200 N
P 4 0 1 0 100 -300 70 -300 70 -210 60 -230 N
P 4 0 1 0 100 -100 20 -100 20 -10 10 -30 N
P 5 0 1 10 -75 -200 -50 -225 -25 -200 -25 0 100 0 N
P 5 0 1 10 100 100 -100 100 -100 -200 -125 -225 -150 -200 N
X ~ R 200 0 100 L 50 50 1 1 P
X ~ RN 200 -100 100 L 50 50 1 1 P
X ~ S 200 100 100 L 50 50 1 1 P
X ~ T 200 -200 100 L 50 50 1 1 P
X ~ TN 200 -300 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x08
#
DEF Connector_Generic_Conn_01x08 J 0 40 Y N 1 F N
F0 "J" 0 400 50 H V C CNN
F1 "Connector_Generic_Conn_01x08" 0 -500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 50 -450 1 1 10 f
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_2 2 -200 200 150 R 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 -200 0 150 R 50 50 1 1 P
X Pin_5 5 -200 -100 150 R 50 50 1 1 P
X Pin_6 6 -200 -200 150 R 50 50 1 1 P
X Pin_7 7 -200 -300 150 R 50 50 1 1 P
X Pin_8 8 -200 -400 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x08_Odd_Even
#
DEF Connector_Generic_Conn_02x08_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x08_Odd_Even" 50 -500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -450 1 1 10 f
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_15 15 -200 -400 150 R 50 50 1 1 P
X Pin_16 16 300 -400 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Ferrite_Bead
#
DEF Device_Ferrite_Bead FB 0 0 N Y 1 F N
F0 "FB" -150 25 50 V V C CNN
F1 "Device_Ferrite_Bead" 150 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Inductor_*
 L_*
 *Ferrite*
$ENDFPLIST
DRAW
P 2 0 1 0 0 -50 0 -48 N
P 2 0 1 0 0 50 0 51 N
P 5 0 1 0 -109 16 -67 89 109 -12 66 -85 -109 16 N
X ~ 1 0 150 100 D 50 50 1 1 P
X ~ 2 0 -150 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Regulator_Linear_MCP1700-2502E_SOT23
#
DEF Regulator_Linear_MCP1700-2502E_SOT23 U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_MCP1700-2502E_SOT23" 0 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 0 225 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS MCP1700-1202E_SOT23 MCP1700-1802E_SOT23 MCP1700-2502E_SOT23 MCP1700-2802E_SOT23 MCP1700-3302E_SOT23 MCP1700-5002E_SOT23
$FPLIST
 SOT?23*
$ENDFPLIST
DRAW
S -200 75 200 -200 0 1 10 f
X GND 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# TinyFPGA_BX_ANALOG_DEVICES_AD5754BREZANALOG_DEVICES_AD5754BREZ_0_0
#
DEF TinyFPGA_BX_ANALOG_DEVICES_AD5754BREZANALOG_DEVICES_AD5754BREZ_0_0 U 0 40 Y Y 1 L N
F0 "U" 0 -100 85 H V L TNN
F1 "TinyFPGA_BX_ANALOG_DEVICES_AD5754BREZANALOG_DEVICES_AD5754BREZ_0_0" 0 0 50 H I C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 -2400 85 0 1 0 AD5754BREZ Normal 0 L T
P 2 1 0 0 0 -2200 0 -200 N
P 2 1 0 0 0 -200 1000 -200 N
P 2 1 0 0 1000 -2200 0 -2200 N
P 2 1 0 0 1000 -200 1000 -2200 N
X AVSS 1 1200 -1500 200 L 50 50 1 0 W
X ~LDAC~ 10 -200 -800 200 R 50 50 1 0 I
X ~CLR~ 11 -200 -900 200 R 50 50 1 0 I
X 1_NC 12 1200 -1200 200 L 50 50 1 0 P
X 2_NC 13 1200 -1300 200 L 50 50 1 0 P
X DVCC 14 -200 -2100 200 R 50 50 1 0 W
X GND 15 1200 -2100 200 L 50 50 1 0 W
X SDO 16 -200 -500 200 R 50 50 1 0 O
X REFIN 17 1200 -800 200 L 50 50 1 0 I
X 1_DAC_GND 18 1200 -1900 200 L 50 50 1 0 W
X 2_DAC_GND 19 1200 -2000 200 L 50 50 1 0 W
X 3_NC 2 -200 -1200 200 R 50 50 1 0 P
X 1_SIG_GND 20 1200 -1700 200 L 50 50 1 0 W
X 2_SIG_GND 21 1200 -1800 200 L 50 50 1 0 W
X VOUTD 22 1200 -600 200 L 50 50 1 0 O
X VOUTC 23 1200 -500 200 L 50 50 1 0 O
X AVDD 24 -200 -1500 200 R 50 50 1 0 W
X EP 25 1200 -1600 200 L 50 50 1 0 P
X VOUTA 3 1200 -300 200 L 50 50 1 0 O
X VOUTB 4 1200 -400 200 L 50 50 1 0 O
X ~2SCOMP~ 5 -200 -1000 200 R 50 50 1 0 I
X 4_NC 6 -200 -1300 200 R 50 50 1 0 P
X ~SYNC~ 7 -200 -600 200 R 50 50 1 0 I
X SCLK 8 -200 -300 200 R 50 50 1 0 I
X SDIN 9 -200 -400 200 R 50 50 1 0 I
ENDDRAW
ENDDEF
#
# TinyFPGA_BX_ANALOG_DEVICES_AD7606BSTZANALOG_DEVICES_AD7606BSTZ_0_0
#
DEF TinyFPGA_BX_ANALOG_DEVICES_AD7606BSTZANALOG_DEVICES_AD7606BSTZ_0_0 U 0 40 Y Y 1 L N
F0 "U" 0 -100 85 H V L TNN
F1 "TinyFPGA_BX_ANALOG_DEVICES_AD7606BSTZANALOG_DEVICES_AD7606BSTZ_0_0" 0 0 50 H I C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 0 -4400 85 0 1 0 AD7606BSTZ Normal 0 L T
P 2 1 0 0 0 -4200 0 -200 N
P 2 1 0 0 0 -200 1400 -200 N
P 2 1 0 0 1400 -4200 0 -4200 N
P 2 1 0 0 1400 -200 1400 -4200 N
X 1_AVCC 1 -200 -3800 200 R 50 50 1 0 W
X CONVST_B 10 -200 -3300 200 R 50 50 1 0 I
X RESET 11 -200 -3000 200 R 50 50 1 0 I
X ~RD~/SCLK 12 -200 -2600 200 R 50 50 1 0 I
X ~CS~ 13 -200 -2700 200 R 50 50 1 0 I
X BUSY 14 -200 -3400 200 R 50 50 1 0 O
X FRSTDATA 15 -200 -3500 200 R 50 50 1 0 T
X DB0 16 -200 -300 200 R 50 50 1 0 B
X DB1 17 -200 -400 200 R 50 50 1 0 B
X DB2 18 -200 -500 200 R 50 50 1 0 B
X DB3 19 -200 -600 200 R 50 50 1 0 B
X 1_AGND 2 1600 -3600 200 L 50 50 1 0 W
X DB4 20 -200 -700 200 R 50 50 1 0 B
X DB5 21 -200 -800 200 R 50 50 1 0 B
X DB6 22 -200 -900 200 R 50 50 1 0 B
X VDRIVE 23 -200 -3700 200 R 50 50 1 0 W
X DB7/DOUTA 24 -200 -1000 200 R 50 50 1 0 B
X DB8/DOUTB 25 -200 -1100 200 R 50 50 1 0 B
X 2_AGND 26 1600 -3700 200 L 50 50 1 0 W
X DB9 27 -200 -1200 200 R 50 50 1 0 B
X DB10 28 -200 -1300 200 R 50 50 1 0 B
X DB11 29 -200 -1400 200 R 50 50 1 0 B
X OS0 3 -200 -2000 200 R 50 50 1 0 I
X DB12 30 -200 -1500 200 R 50 50 1 0 B
X DB13 31 -200 -1600 200 R 50 50 1 0 B
X DB14/HBEN 32 -200 -1700 200 R 50 50 1 0 B
X DB15/BYTE_SEL 33 -200 -1800 200 R 50 50 1 0 B
X REF_SELECT 34 1600 -2900 200 L 50 50 1 0 I
X 3_AGND 35 1600 -3800 200 L 50 50 1 0 W
X 1_REGCAP 36 1600 -2400 200 L 50 50 1 0 O
X 2_AVCC 37 -200 -3900 200 R 50 50 1 0 W
X 3_AVCC 38 -200 -4000 200 R 50 50 1 0 W
X 2_REGCAP 39 1600 -2300 200 L 50 50 1 0 O
X OS1 4 -200 -2100 200 R 50 50 1 0 I
X 4_AGND 40 1600 -3900 200 L 50 50 1 0 W
X 5_AGND 41 1600 -4000 200 L 50 50 1 0 W
X REFIN/REFOUT 42 1600 -3100 200 L 50 50 1 0 B
X 1_REFGND 43 1600 -3300 200 L 50 50 1 0 W
X REFCAPA 44 1600 -2600 200 L 50 50 1 0 O
X REFCAPB 45 1600 -2700 200 L 50 50 1 0 O
X 2_REFGND 46 1600 -3400 200 L 50 50 1 0 W
X 6_AGND 47 1600 -4100 200 L 50 50 1 0 W
X 4_AVCC 48 -200 -4100 200 R 50 50 1 0 W
X V1 49 1600 -300 200 L 50 50 1 0 I
X OS2 5 -200 -2200 200 R 50 50 1 0 I
X V1GND 50 1600 -400 200 L 50 50 1 0 W
X V2 51 1600 -500 200 L 50 50 1 0 I
X V2GND 52 1600 -600 200 L 50 50 1 0 W
X V3 53 1600 -700 200 L 50 50 1 0 I
X V3GND 54 1600 -800 200 L 50 50 1 0 W
X V4 55 1600 -900 200 L 50 50 1 0 I
X V4GND 56 1600 -1000 200 L 50 50 1 0 W
X V5 57 1600 -1100 200 L 50 50 1 0 I
X V5GND 58 1600 -1200 200 L 50 50 1 0 W
X V6 59 1600 -1300 200 L 50 50 1 0 I
X ~PAR~/SERBYTE_SEL 6 -200 -2800 200 R 50 50 1 0 I
X V6GND 60 1600 -1400 200 L 50 50 1 0 W
X V7 61 1600 -1500 200 L 50 50 1 0 I
X V7GND 62 1600 -1600 200 L 50 50 1 0 W
X V8 63 1600 -1700 200 L 50 50 1 0 I
X V8GND 64 1600 -1800 200 L 50 50 1 0 W
X ~STBY~ 7 -200 -2400 200 R 50 50 1 0 I
X RANGE 8 -200 -3100 200 R 50 50 1 0 I
X CONVST_A 9 -200 -3200 200 R 50 50 1 0 I
ENDDRAW
ENDDEF
#
# TinyFPGA_BX_CS42448
#
DEF TinyFPGA_BX_CS42448 U 0 40 Y Y 1 L N
F0 "U" -1300 2450 59 H V L BNN
F1 "TinyFPGA_BX_CS42448" -1300 -2500 59 H V L BNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 1 0 0 -1300 -2400 -1300 2400 N
P 2 1 0 0 -1300 2400 1300 2400 N
P 2 1 0 0 1300 -2400 -1300 -2400 N
P 2 1 0 0 1300 2400 1300 -2400 N
X AD0/~CS~ 1 -1500 -1900 200 R 50 50 1 0 I
X MCLK 10 -1500 -1400 200 R 50 50 1 0 I
X ADC_SDOUT3 11 -1500 -100 200 R 50 50 1 0 O
X ADC_SDOUT2 12 -1500 -200 200 R 50 50 1 0 O
X ADC_SDOUT1 13 -1500 -300 200 R 50 50 1 0 O
X DAC_SDIN4 14 -1500 -700 200 R 50 50 1 0 I
X DAC_SDIN3 15 -1500 -800 200 R 50 50 1 0 I
X DAC_SDIN2 16 -1500 -900 200 R 50 50 1 0 I
X DAC_SDIN1 17 -1500 -1000 200 R 50 50 1 0 I
X DAC_SCLK 18 -1500 -1100 200 R 50 50 1 0 B
X DAC_LRCK 19 -1500 -1200 200 R 50 50 1 0 B
X AD1/CDIN 2 -1500 -1800 200 R 50 50 1 0 I
X AUX_LRCK 20 -1500 100 200 R 50 50 1 0 O
X AUX_SCLK 21 -1500 200 200 R 50 50 1 0 O
X AUX_SDIN 22 -1500 300 200 R 50 50 1 0 I
X DGND@23 23 -200 -2600 200 U 50 50 1 0 W
X VD@24 24 -100 2600 200 D 50 50 1 0 P
X AOUT1- 25 1500 2200 200 L 50 50 1 0 O
X AOUT1+ 26 1500 2300 200 L 50 50 1 0 O
X AOUT2+ 27 1500 2000 200 L 50 50 1 0 O
X AOUT2- 28 1500 1900 200 L 50 50 1 0 O
X AOUT3- 29 1500 1600 200 L 50 50 1 0 O
X ~RST~ 3 -1500 -2300 200 R 50 50 1 0 I
X AOUT3+ 30 1500 1700 200 L 50 50 1 0 O
X AOUT4+ 31 1500 1400 200 L 50 50 1 0 O
X AOUT4- 32 1500 1300 200 L 50 50 1 0 O
X AOUT5- 33 1500 1000 200 L 50 50 1 0 O
X AOUT5+ 34 1500 1100 200 L 50 50 1 0 O
X MUTEC 35 1500 -1500 200 L 50 50 1 0 O
X AOUT6+ 36 1500 800 200 L 50 50 1 0 O
X AOUT6- 37 1500 700 200 L 50 50 1 0 O
X AOUT7- 38 1500 400 200 L 50 50 1 0 O
X AOUT7+ 39 1500 500 200 L 50 50 1 0 O
X VLC 4 -500 2600 200 D 50 50 1 0 I
X AOUT8+ 40 1500 200 200 L 50 50 1 0 O
X AOUT8- 41 1500 100 200 L 50 50 1 0 O
X AGND@42 42 200 -2600 200 U 50 50 1 0 W
X VQ 43 1500 -1800 200 L 50 50 1 0 O
X VA@44 44 300 2600 200 D 50 50 1 0 W
X AIN1- 45 -1500 2200 200 R 50 50 1 0 I
X AIN1+ 46 -1500 2300 200 R 50 50 1 0 I
X AIN2- 47 -1500 1900 200 R 50 50 1 0 I
X AIN2+ 48 -1500 2000 200 R 50 50 1 0 I
X AIN3- 49 -1500 1600 200 R 50 50 1 0 I
X ADC_LRCK 5 -1500 -500 200 R 50 50 1 0 B
X AIN3+ 50 -1500 1700 200 R 50 50 1 0 I
X AIN4- 51 -1500 1300 200 R 50 50 1 0 I
X AIN4+ 52 -1500 1400 200 R 50 50 1 0 I
X VA@53 53 200 2600 200 D 50 50 1 0 W
X FILT+_DAC 54 1500 -2300 200 L 50 50 1 0 O
X FILT+_ADC 55 1500 -2100 200 L 50 50 1 0 O
X AGND@56 56 300 -2600 200 U 50 50 1 0 W
X AIN5-/AIN5B 57 -1500 1000 200 R 50 50 1 0 I
X AIN5+/AIN5A 58 -1500 1100 200 R 50 50 1 0 I
X AIN6-/AIN6B 59 -1500 700 200 R 50 50 1 0 I
X VD@6 6 -200 2600 200 D 50 50 1 0 W
X AIN6+/AIN6A 60 -1500 800 200 R 50 50 1 0 I
X INT 61 -1500 -2100 200 R 50 50 1 0 O
X DGND@62 62 -100 -2600 200 U 50 50 1 0 B
X SCL/CCLK 63 -1500 -1600 200 R 50 50 1 0 I
X SDA/CDOUT 64 -1500 -1700 200 R 50 50 1 0 B
X DGND@7 7 -300 -2600 200 U 50 50 1 0 W
X VLS 8 -400 2600 200 D 50 50 1 0 I
X ADC_SCLK 9 -1500 -400 200 R 50 50 1 0 B
ENDDRAW
ENDDEF
#
# TinyFPGA_BX_tinyfpga_bx
#
DEF TinyFPGA_BX_tinyfpga_bx U 0 40 Y Y 1 F N
F0 "U" -200 100 50 H V C CNN
F1 "TinyFPGA_BX_tinyfpga_bx" 0 0 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 -350 -1500 -350 -50 300 -50 300 -1550 -350 -1550 -350 -1500 N
X GND 1 -450 -150 100 R 50 50 1 1 w
X E1 10 -450 -1050 100 R 50 50 1 1 B
X G2 11 -450 -1150 100 R 50 50 1 1 B
X H1 12 -450 -1250 100 R 50 50 1 1 B
X J1 13 -450 -1350 100 R 50 50 1 1 B
X H2 14 -450 -1450 100 R 50 50 1 1 B
X H9 15 400 -1450 100 L 50 50 1 1 B
X D9 16 400 -1350 100 L 50 50 1 1 B
X D8 17 400 -1250 100 L 50 50 1 1 B
X C9 18 400 -1150 100 L 50 50 1 1 B
X A9 19 400 -1050 100 L 50 50 1 1 B
X A2 2 -450 -250 100 R 50 50 1 1 B
X B8 20 400 -950 100 L 50 50 1 1 B
X A8 21 400 -850 100 L 50 50 1 1 B
X B7 22 400 -750 100 L 50 50 1 1 B
X A7 23 400 -650 100 L 50 50 1 1 B
X B6 24 400 -550 100 L 50 50 1 1 B
X A6 25 400 -450 100 L 50 50 1 1 B
X 3V3 26 400 -350 100 L 50 50 1 1 W
X GND 27 400 -250 100 L 50 50 1 1 w
X VIN 28 400 -150 100 L 50 50 1 1 W
X A1 3 -450 -350 100 R 50 50 1 1 B
X B1 4 -450 -450 100 R 50 50 1 1 B
X C2 5 -450 -550 100 R 50 50 1 1 B
X C1 6 -450 -650 100 R 50 50 1 1 B
X D2 7 -450 -750 100 R 50 50 1 1 B
X D1 8 -450 -850 100 R 50 50 1 1 B
X E2 9 -450 -950 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# power_+12V
#
DEF power_+12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_-12V
#
DEF power_-12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-12V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -12V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# teensy_Teensy4.1
#
DEF teensy_Teensy4.1 U 0 40 Y Y 1 F N
F0 "U" 0 2550 50 H V C CNN
F1 "teensy_Teensy4.1" 0 2450 50 H V C CNN
F2 "" -400 400 50 H I C CNN
F3 "" -400 400 50 H I C CNN
DRAW
T 0 450 1950 40 0 0 0 "(250mA max)" Normal 0 C C
T 0 450 2150 40 0 0 0 "(3.6v to 5.5v)" Normal 0 C C
T 900 -550 -400 50 0 0 0 Device Normal 0 C C
T 900 625 -675 50 0 0 0 Ethernet Normal 0 C C
T 900 -550 -800 50 0 0 0 Host Normal 0 C C
T 900 -625 -800 50 0 0 0 USB Normal 0 C C
T 900 -625 -400 50 0 0 0 USB Normal 0 C C
S -900 2400 900 -1100 0 1 0 N
S -800 -50 -800 -50 0 1 0 N
P 2 0 0 0 -900 -250 900 -250 N
P 2 0 0 0 -700 -1050 -700 -550 N
P 2 0 0 0 -700 -300 -700 -500 N
P 2 0 0 0 700 -375 700 -975 N
X 8_TX2_IN1 10 -1100 1250 200 R 50 50 0 0 B
X 9_OUT1C 11 -1100 1150 200 R 50 50 0 0 B
X 10_CS_MQSR 12 -1100 1050 200 R 50 50 0 0 B
X 11_MOSI_CTX1 13 -1100 950 200 R 50 50 0 0 B
X 12_MISO_MQSL 14 -1100 850 200 R 50 50 0 0 B
X 3V3 15 -1100 750 200 R 50 50 0 0 W
X 24_A10_TX6_SCL2 16 -1100 650 200 R 50 50 0 0 B
X 25_A11_RX6_SDA2 17 -1100 550 200 R 50 50 0 0 B
X 26_A12_MOSI1 18 -1100 450 200 R 50 50 0 0 B
X 27_A13_SCK1 19 -1100 350 200 R 50 50 0 0 B
X 28_RX7 20 -1100 250 200 R 50 50 0 0 B
X 29_TX7 21 -1100 150 200 R 50 50 0 0 B
X 30_CRX3 22 -1100 50 200 R 50 50 0 0 B
X 31_CTX3 23 -1100 -50 200 R 50 50 0 0 B
X 32_OUT1B 24 -1100 -150 200 R 50 50 0 0 B
X 33_MCLK2 25 1100 -150 200 L 50 50 0 0 B
X 34_DAT1_MISO2 26 1100 -50 200 L 50 50 0 0 B
X 35_DAT0_MOSI2 27 1100 50 200 L 50 50 0 0 B
X 36_CLK_CS2 28 1100 150 200 L 50 50 0 0 B
X 37_CMD_SCK2 29 1100 250 200 L 50 50 0 0 B
X 38_DAT3_RX5 30 1100 350 200 L 50 50 0 0 B
X 39_DAT2_TX5 31 1100 450 200 L 50 50 0 0 B
X 40_A16_CS1 32 1100 550 200 L 50 50 0 0 B
X 41_A1_MIS01 33 1100 650 200 L 50 50 0 0 B
X 13_SCK_CRX1_LED 35 1100 850 200 L 50 50 0 0 B
X 14_A0_TX3_SPDIF_OUT 36 1100 950 200 L 50 50 0 0 B
X 15_A1_RX3_SPDIF_IN 37 1100 1050 200 L 50 50 0 0 B
X 16_A2_RX4_SCL1 38 1100 1150 200 L 50 50 0 0 B
X 17_A3_TX4_SDA1 39 1100 1250 200 L 50 50 0 0 B
X 18_A4_SDA0 40 1100 1350 200 L 50 50 0 0 B
X 19_A5_SCL0 41 1100 1450 200 L 50 50 0 0 B
X 20_A6_TX5_LRCLK1 42 1100 1550 200 L 50 50 0 0 B
X 21_A7_RX5_BCLK1 43 1100 1650 200 L 50 50 0 0 B
X 22_A8_CTX1 44 1100 1750 200 L 50 50 0 0 B
X 23_A9_CRX1_MCLK1 45 1100 1850 200 L 50 50 0 0 B
X 3V3 46 1100 1950 200 L 50 50 0 0 W
X GND 47 1100 2050 200 L 50 50 0 0 W
X VIN 48 1100 2150 200 L 50 50 0 0 W
X VUSB 49 1100 2300 200 L 50 50 0 0 w
X 3_LRCLK2 5 -1100 1750 200 R 50 50 0 0 B
X VBAT 50 -300 -1300 200 U 50 50 0 0 W
X 3V3 51 -150 -1300 200 U 50 50 0 0 W
X GND 52 0 -1300 200 U 50 50 0 0 w
X PROGRAM 53 150 -1300 200 U 50 50 0 0 I
X ON_OFF 54 300 -1300 200 U 50 50 0 0 I
X 5V 55 -1100 -600 200 R 50 50 0 0 w
X D- 56 -1100 -700 200 R 50 50 0 0 B
X D+ 57 -1100 -800 200 R 50 50 0 0 B
X GND 58 -1100 -900 200 R 50 50 0 0 W
X GND 59 -1100 -1000 200 R 50 50 0 0 W
X 4_BCLK2 6 -1100 1650 200 R 50 50 0 0 B
X R+ 60 1100 -900 200 L 50 50 0 0 B
X LED 61 1100 -800 200 L 50 50 0 0 B
X T- 62 1100 -700 200 L 50 50 0 0 B
X T+ 63 1100 -600 200 L 50 50 0 0 B
X GND 64 1100 -500 200 L 50 50 0 0 W
X R- 65 1100 -400 200 L 50 50 0 0 B
X D- 66 -1100 -350 200 R 50 50 0 0 B
X D+ 67 -1100 -450 200 R 50 50 0 0 B
X 5_IN2 7 -1100 1550 200 R 50 50 0 0 B
X 6_OUT1D 8 -1100 1450 200 R 50 50 0 0 B
X 7_RX2_OUT1A 9 -1100 1350 200 R 50 50 0 0 B
X GND 1 -1100 2150 200 R 50 50 1 1 W
X 0_RX1_CRX2_CS1 2 -1100 2050 200 R 50 50 1 1 B
X 1_TX1_CTX2_MISO1 3 -1100 1950 200 R 50 50 1 1 B
X GND 34 1100 750 200 L 50 50 1 1 W
X 2_OUT2 4 -1100 1850 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library