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Nitro E1 core

This fpga core implements various functions related to E1 interface used in the telcom world. The relevant specifications here are :

Physical interface can either be using a "fake" PHY, basically directly using FPGA IOs, or using a true LIU.

On the internal side, some native interface is provided, but a higher level one is also provided in the form of a wishbone interface.

Refer to the doc/ subdirectory for complete core documentation.

Limitations

Currently this core was only used on iCE40 and uses some direct SB_IO instances for the IO registers and differential inputs. It would be very easy to adapt those to other FPGA architectures.

License

This core is licensed under the "CERN Open Hardware Licence Version 2 - Weakly Reciprocal" license.

See LICENSE file for full text.