From 036650e0463da4e345357e71ae7a4695b5049cda Mon Sep 17 00:00:00 2001 From: Lu Yahan Date: Mon, 17 Jan 2022 15:57:41 +0800 Subject: [PATCH] deps: V8: backport 77599ffe0a74 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Original commit message: [riscv64] Add block before LoadAddress fix node.js DCHECK failed issue: https://github.com/riscv-collab/v8/issues/514 Change-Id: I07f40e6aca05be3eb7304a43235185fd40ebc1f2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3260979 Reviewed-by: ji qiu Commit-Queue: ji qiu Auto-Submit: Yahan Lu Cr-Commit-Position: refs/heads/main@{#77750} Refs: v8/v8@77599ffe0a74 PR-URL: https://github.com/nodejs/node/pull/41566 Refs: https://github.com/v8/v8/commit/d8dc66f Refs: https://github.com/v8/v8/commit/3cab84c Refs: https://github.com/v8/v8/commit/471f862 Refs: https://github.com/v8/v8/commit/77599ff Reviewed-By: Jiawen Geng Reviewed-By: Michaël Zasso --- common.gypi | 2 +- deps/v8/src/baseline/riscv64/baseline-assembler-riscv64-inl.h | 1 + deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/common.gypi b/common.gypi index 22e35703521a3e..36f789821ed1ff 100644 --- a/common.gypi +++ b/common.gypi @@ -36,7 +36,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.18', + 'v8_embedder_string': '-node.19', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/src/baseline/riscv64/baseline-assembler-riscv64-inl.h b/deps/v8/src/baseline/riscv64/baseline-assembler-riscv64-inl.h index f39f5786469c3b..83afd560b002d0 100644 --- a/deps/v8/src/baseline/riscv64/baseline-assembler-riscv64-inl.h +++ b/deps/v8/src/baseline/riscv64/baseline-assembler-riscv64-inl.h @@ -438,6 +438,7 @@ void BaselineAssembler::Switch(Register reg, int case_value_base, DCHECK(is_int32(imm64)); int32_t Hi20 = (((int32_t)imm64 + 0x800) >> 12); int32_t Lo12 = (int32_t)imm64 << 20 >> 20; + __ BlockTrampolinePoolFor(2); __ auipc(temp, Hi20); // Read PC + Hi20 into t6 __ addi(temp, temp, Lo12); // jump PC + Hi20 + Lo12 diff --git a/deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc b/deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc index 3baa71d1a2e768..4d231adfb4823e 100644 --- a/deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc +++ b/deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc @@ -3485,6 +3485,7 @@ void TurboAssembler::LoadAddress(Register dst, Label* target, if (CalculateOffset(target, &offset, OffsetSize::kOffset32)) { int32_t Hi20 = (((int32_t)offset + 0x800) >> 12); int32_t Lo12 = (int32_t)offset << 20 >> 20; + BlockTrampolinePoolScope block_trampoline_pool(this); auipc(dst, Hi20); addi(dst, dst, Lo12); } else {