diff --git a/sycl/doc/extensions/proposed/sycl_ext_intel_cache_controls.asciidoc b/sycl/doc/extensions/experimental/sycl_ext_intel_cache_controls.asciidoc
similarity index 96%
rename from sycl/doc/extensions/proposed/sycl_ext_intel_cache_controls.asciidoc
rename to sycl/doc/extensions/experimental/sycl_ext_intel_cache_controls.asciidoc
index eb6fe235bc4e..07ee1d3fabfa 100644
--- a/sycl/doc/extensions/proposed/sycl_ext_intel_cache_controls.asciidoc
+++ b/sycl/doc/extensions/experimental/sycl_ext_intel_cache_controls.asciidoc
@@ -36,7 +36,7 @@ https://github.com/intel/llvm/issues
 
 == Dependencies
 
-This extension is written against the SYCL 2020 revision 7 specification.  All
+This extension is written against the SYCL 2020 revision 9 specification.  All
 references below to the "core SYCL specification" or to section numbers in the
 SYCL specification refer to that revision.
 
@@ -49,11 +49,12 @@ This extension depends on the following SYCL extensions:
 
 == Status
 
-This is a proposed extension specification, intended to gather community
-feedback.  Interfaces defined in this specification may not be implemented yet
-or may be in a preliminary state.  The specification itself may also change in
-incompatible ways before it is finalized.  *Shipping software products should
-not rely on APIs defined in this specification.*
+This is an experimental extension specification, intended to provide early
+access to features and gather community feedback.  Interfaces defined in this
+specification are implemented in {dpcpp}, but they are not finalized and may
+change incompatibly in future versions of {dpcpp} without prior notice.
+*Shipping software products should not rely on APIs defined in this
+specification.*
 
 
 == Overview