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jit_uni_pool_kernel.cpp
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/*******************************************************************************
* Copyright 2017-2024 Intel Corporation
* Copyright 2018 YANDEX LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <bitset>
#include "common/dnnl_thread.hpp"
#include "cpu/cpu_pooling_pd.hpp"
#include "cpu/x64/jit_avx512_core_bf16cvt.hpp"
#include "cpu/x64/jit_avx512_core_fp8cvt.hpp"
#include "cpu/x64/jit_uni_pool_kernel.hpp"
namespace dnnl {
namespace impl {
namespace cpu {
namespace x64 {
using namespace Xbyak;
using namespace alg_kind;
#define GET_OFF(field) offsetof(jit_pool_call_s, field)
static bcast_set_t get_supported_bcast_strategies() {
return {broadcasting_strategy_t::scalar, broadcasting_strategy_t::per_oc,
broadcasting_strategy_t::no_broadcast};
}
template <cpu_isa_t isa>
jit_uni_pool_kernel<isa>::~jit_uni_pool_kernel() = default;
template <cpu_isa_t isa>
jit_uni_pool_kernel<isa>::jit_uni_pool_kernel(
const jit_pool_conf_t &ajpp, const memory_desc_t *dst_md)
: jit_generator(jit_name(), isa), jpp(ajpp), bf16_emu_(nullptr) {
if (use_bf16_emulation())
bf16_emu_ = utils::make_unique<bf16_emulation_t>(this,
bf16_emu_reserv_1, bf16_emu_reserv_2, bf16_emu_reserv_3,
bf16_emu_reserv_4, bf16_emu_reserv_5);
bool has_f8_e5m2_binary_postops = false;
bool has_f8_e4m3_binary_postops = false;
if (jpp.with_binary) {
const auto &post_ops = jpp.post_ops;
for (int i = 0; i < post_ops.len(); i++) {
const auto &entry = post_ops.entry_[i];
if (!entry.is_binary()) continue;
has_f8_e5m2_binary_postops
= entry.binary.src1_desc.data_type == data_type::f8_e5m2
|| has_f8_e5m2_binary_postops;
has_f8_e4m3_binary_postops
= entry.binary.src1_desc.data_type == data_type::f8_e4m3
|| has_f8_e4m3_binary_postops;
}
}
if (use_fp8_emulation() || has_f8_e5m2_binary_postops
|| has_f8_e4m3_binary_postops) {
if (utils::one_of(data_type::f8_e5m2, ajpp.src_dt, ajpp.dst_dt)
|| has_f8_e5m2_binary_postops)
f8_e5m2_emu_ = utils::make_unique<fp8_emulation_e5m2_t>(this,
fp8_emu_reserv_1, fp8_emu_reserv_2, fp8_emu_reserv_3,
fp8_tmp_mask, fp8_emu_reg64);
if (utils::one_of(data_type::f8_e4m3, ajpp.src_dt, ajpp.dst_dt)
|| has_f8_e4m3_binary_postops)
f8_e4m3_emu_ = utils::make_unique<fp8_emulation_e4m3_t>(this,
fp8_emu_reserv_1, fp8_emu_reserv_2, fp8_emu_reserv_3,
fp8_emu_reserv_4, fp8_emu_reserv_5, fp8_emu_reg64);
}
if (jpp.with_postops) {
static constexpr bool preserve_gpr = true;
static constexpr bool preserve_vmm = true;
static constexpr bool use_exact_tail_scalar_bcast = false;
static constexpr int sse41_single_block_size
= cpu_isa_traits<sse41>::vlen / sizeof(float);
size_t postop_tail = static_cast<size_t>(jpp.c_tail);
const bool high_half_block_empty = isa == sse41
&& static_cast<size_t>(jpp.c_tail) > sse41_single_block_size;
if (high_half_block_empty) postop_tail -= sse41_single_block_size;
const binary_injector::rhs_arg_static_params_t rhs_sp {
static_cast<std::size_t>(this->xmm4.getIdx()), this->r14,
this->r15, this->r13, preserve_gpr, preserve_vmm,
GET_OFF(post_ops_binary_rhs_arg_vec), GET_OFF(dst_orig),
memory_desc_wrapper(jpp.tag_kind == jit_memory_tag_kind_t::ncsp
? jpp.tmp_md
: *dst_md),
postop_tail, k_c_tail_mask, use_exact_tail_scalar_bcast};
const binary_injector::static_params_t bsp {reg_param,
get_supported_bcast_strategies(), rhs_sp, f8_e5m2_emu_.get(),
f8_e4m3_emu_.get()};
postops_injector_
= utils::make_unique<injector::jit_uni_postops_injector_t<isa>>(
this, jpp.post_ops, bsp);
}
}
static status_t set_binary_postops_formats(
post_ops_t &post_ops, const memory_desc_t *dst_md) {
for (int idx = 0; idx < post_ops.len(); ++idx) {
if (!post_ops.contain(primitive_kind::binary, idx)) continue;
auto &src1_md = post_ops.entry_[idx].binary.src1_desc;
const memory_desc_wrapper src1_mdw(src1_md);
if (!src1_mdw.format_any()) {
if (src1_mdw.is_blocking_desc())
continue;
else
return status::unimplemented;
}
const memory_desc_wrapper dst_mdw(dst_md);
assert(!dst_mdw.format_any());
CHECK(memory_desc_init_by_blocking_desc(
src1_md, dst_mdw.blocking_desc()));
}
return status::success;
}
template <cpu_isa_t isa>
status_t jit_uni_pool_kernel<isa>::init_conf(jit_pool_conf_t &jpp,
memory_tracking::registrar_t &scratchpad, primitive_attr_t &attr,
const pooling_pd_t *ppd) {
const auto &pd = *ppd->desc();
const memory_desc_wrapper src_d(
ppd->is_fwd() ? ppd->src_md() : ppd->diff_src_md());
const memory_desc_wrapper dst_d(
ppd->is_fwd() ? ppd->dst_md() : ppd->diff_dst_md());
const int ndims = src_d.ndims();
jpp.nthr = dnnl_get_max_threads();
jpp.is_training = pd.prop_kind == prop_kind::forward_training;
jpp.is_backward = pd.prop_kind == prop_kind::backward_data;
jpp.id = (ndims == 5) ? src_d.dims()[2] : 1;
jpp.ih = (ndims == 3) ? 1 : src_d.dims()[ndims - 2];
jpp.iw = src_d.dims()[ndims - 1];
jpp.od = (ndims == 5) ? dst_d.dims()[2] : 1;
jpp.ow = dst_d.dims()[ndims - 1];
jpp.oh = (ndims == 3) ? 1 : dst_d.dims()[ndims - 2];
const bool is_avx512 = is_superset(isa, avx512_core);
jpp.ndims = ndims;
jpp.mb = src_d.dims()[0];
jpp.c_without_padding = src_d.dims()[1];
jpp.c_block = is_avx512 ? 16 : 8;
jpp.alg = pd.alg_kind;
jpp.src_dt = jpp.is_backward ? pd.diff_src_desc.data_type
: pd.src_desc.data_type;
jpp.dst_dt = jpp.is_backward ? pd.diff_dst_desc.data_type
: pd.dst_desc.data_type;
jpp.tmp_md = memory_desc_t();
jpp.is_bf16 = (src_d.data_type() == data_type::bf16
&& dst_d.data_type() == data_type::bf16);
jpp.is_f16 = (src_d.data_type() == data_type::f16
&& dst_d.data_type() == data_type::f16);
jpp.is_fp8 = utils::one_of(src_d.data_type(), data_type::f8_e5m2,
data_type::f8_e4m3)
&& utils::one_of(
dst_d.data_type(), data_type::f8_e5m2, data_type::f8_e4m3);
using namespace format_tag;
const auto blocked_fmt_tag = is_avx512
? utils::pick(ndims - 3, nCw16c, nChw16c, nCdhw16c)
: utils::pick(ndims - 3, nCw8c, nChw8c, nCdhw8c);
// src_d.data_type() is equal to dst_d.data_type(). This is checked in init
auto ncsp_fmt_tag = format_tag::undef;
const unsigned int L3_cache_size_per_core
= platform::get_per_core_cache_size(3);
const size_t block_size
= ((size_t)jpp.id * jpp.ih * jpp.iw + jpp.od * jpp.oh * jpp.ow)
* jpp.c_block * types::data_type_size(src_d.data_type());
const bool forward_ncsp_allowed = !jpp.is_backward
&& jpp.c_without_padding > 3
&& ((jpp.ih > 1 && jpp.iw > 1
&& block_size <= L3_cache_size_per_core)
|| utils::one_of(src_d.data_type(), data_type::bf16,
data_type::f16, data_type::f8_e5m2,
data_type::f8_e4m3));
const bool backward_ncsp_allowed = jpp.is_backward
&& ((jpp.ih > 1 && jpp.iw > 1 && jpp.c_without_padding > 1
&& block_size <= L3_cache_size_per_core)
|| (utils::one_of(src_d.data_type(), data_type::bf16,
data_type::f16)
&& !(jpp.alg == pooling_max
&& block_size > L3_cache_size_per_core)));
ncsp_fmt_tag = ((forward_ncsp_allowed || backward_ncsp_allowed) && is_avx512
&& ndims <= 5)
? utils::pick(ndims - 3, ncw, nchw, ncdhw)
: format_tag::undef;
const auto nspc_fmt_tag = (ndims <= 5)
? utils::pick(ndims - 3, nwc, nhwc, ndhwc)
: format_tag::undef;
const auto fmt_tag = src_d.matches_one_of_tag(
blocked_fmt_tag, ncsp_fmt_tag, nspc_fmt_tag);
VDISPATCH_POOLING_IC(
dst_d.matches_tag(fmt_tag), VERBOSE_UNSUPPORTED_TAG_S, "dst");
VDISPATCH_POOLING_IC(
post_ops_ok(jpp, attr, dst_d), VERBOSE_UNSUPPORTED_POSTOP);
if (fmt_tag == ncsp_fmt_tag) {
// transform input to blocked f32, call f32 jit, transform result to
// plain output
jpp.is_bf16 = false;
jpp.is_f16 = false;
jpp.is_fp8 = false;
jpp.dt_size = types::data_type_size(data_type::f32);
jpp.tag_kind = jit_memory_tag_kind_t::ncsp;
// used to initialize binary post-ops
if (ppd->is_fwd() && jpp.with_binary) {
CHECK(memory_desc_init_by_tag(jpp.tmp_md, ndims, dst_d.md_->dims,
data_type::f32, blocked_fmt_tag));
}
} else {
jpp.dt_size = types::data_type_size(src_d.data_type());
jpp.tag_kind = (fmt_tag == nspc_fmt_tag)
? jit_memory_tag_kind_t::nspc
: jit_memory_tag_kind_t::blocked;
}
if (ppd->is_fwd() && jpp.with_binary) {
CHECK(set_binary_postops_formats(attr.post_ops_,
jpp.tag_kind == jit_memory_tag_kind_t::ncsp ? &jpp.tmp_md
: dst_d.md_));
}
jpp.isa = (jpp.is_bf16 && mayiuse(avx512_core_bf16))
? avx512_core_bf16
: ((jpp.is_fp8 && mayiuse(avx512_core_fp16)) ? avx512_core_fp16
: isa);
// disabling verbose dispatch messages for unsupported isa for
// better readability
if (!mayiuse(isa)) return status::unimplemented;
VDISPATCH_POOLING_IC(
(fmt_tag != format_tag::undef), VERBOSE_UNSUPPORTED_TAG);
VDISPATCH_POOLING_IC(IMPLICATION(jpp.is_bf16,
utils::one_of(jpp.isa, avx512_core_bf16,
avx512_core, avx2_vnni_2)),
VERBOSE_ISA_DT_MISMATCH);
VDISPATCH_POOLING_IC(
IMPLICATION(jpp.is_f16,
utils::one_of(jpp.isa, avx512_core_fp16, avx2_vnni_2)),
VERBOSE_ISA_DT_MISMATCH);
VDISPATCH_POOLING_IC(
IMPLICATION(jpp.is_fp8, utils::one_of(jpp.isa, avx512_core_fp16)),
VERBOSE_ISA_DT_MISMATCH);
VDISPATCH_POOLING_IC(
utils::one_of(pd.alg_kind, pooling_max, pooling_avg_include_padding,
pooling_avg_exclude_padding),
VERBOSE_BAD_ALGORITHM);
const bool is_xf16_avx2_vnni_2
= (jpp.is_bf16 || jpp.is_f16) && isa == avx2_vnni_2;
// note: avx2_vnni_2 only supports nxc format
VDISPATCH_POOLING_IC(IMPLICATION(is_xf16_avx2_vnni_2,
jpp.tag_kind == jit_memory_tag_kind_t::nspc),
"isa, format tag mismatch");
// note: avx2_vnni_2 only supports FWD direction
VDISPATCH_POOLING_IC(IMPLICATION(is_xf16_avx2_vnni_2, !jpp.is_backward),
"isa, propagation kind mismatch");
jpp.c = jpp.tag_kind == jit_memory_tag_kind_t::blocked
? utils::rnd_up(jpp.c_without_padding, jpp.c_block)
: jpp.c_without_padding;
if (jpp.tag_kind == jit_memory_tag_kind_t::blocked)
assert(src_d.padded_dims()[1] == jpp.c);
jpp.nb_c = utils::div_up(jpp.c, jpp.c_block);
jpp.c_tail = jpp.c_without_padding % jpp.c_block;
jpp.is_c_padded = jpp.tag_kind == jit_memory_tag_kind_t::blocked
&& src_d.padded_dims()[1] != jpp.c_without_padding;
jpp.stride_d = (ndims == 5) ? pd.strides[0] : 1;
jpp.stride_h = (ndims == 3) ? 1 : pd.strides[ndims - 4];
jpp.stride_w = pd.strides[ndims - 3];
jpp.kd = (ndims == 5) ? pd.kernel[0] : 1;
jpp.kh = (ndims == 3) ? 1 : pd.kernel[ndims - 4];
jpp.kw = pd.kernel[ndims - 3];
jpp.f_pad = (ndims == 5) ? pd.padding[0][0] : 0;
jpp.t_pad = (ndims == 3) ? 0 : pd.padding[0][ndims - 4];
jpp.l_pad = pd.padding[0][ndims - 3];
const int back_pad = calculate_end_padding(
jpp.f_pad, jpp.od, jpp.id, jpp.stride_d, jpp.kd);
const int bottom_pad = calculate_end_padding(
jpp.t_pad, jpp.oh, jpp.ih, jpp.stride_h, jpp.kh);
const int right_pad = calculate_end_padding(
jpp.l_pad, jpp.ow, jpp.iw, jpp.stride_w, jpp.kw);
VDISPATCH_POOLING_IC(
!(jpp.f_pad >= jpp.kd || jpp.t_pad >= jpp.kh || jpp.l_pad >= jpp.kw
|| back_pad >= jpp.kd || bottom_pad >= jpp.kh
|| right_pad >= jpp.kw),
VERBOSE_UNSUPPORTED_PAD_FEATURE, "");
jpp.ind_dt = ppd->workspace_md() ? ppd->workspace_md()->data_type
: data_type::undef;
jpp.simple_alg = jpp.is_training
|| IMPLICATION(jpp.is_backward, jpp.kd <= jpp.stride_d);
jpp.ur = 0;
if (jpp.alg == pooling_max) {
jpp.ur = is_avx512 ? 16 : 4;
if (utils::one_of(isa, avx, avx2, avx2_vnni_2) && jpp.c_tail > 0)
// Additional register needed for tail mask
jpp.ur -= 1;
if (jpp.is_training)
jpp.ur = is_avx512 ? 9 : 3;
else if (jpp.is_backward)
jpp.ur = is_avx512 ? 6 : 3;
} else {
if (jpp.is_backward)
jpp.ur = is_avx512 ? 12 : 6;
else
jpp.ur = is_avx512 ? 24 : 12;
}
if ((jpp.is_bf16 || jpp.is_f16) && isa != avx2_vnni_2) {
jpp.ur = (!isa_has_bf16(jpp.isa))
? jpp.ur - 4 // Free registers for AVX512 emulation
: jpp.ur - 1; // Free register for cvt from bf16/f16 to f32
}
if (jpp.is_fp8) {
// TODO: Optimize the ur if native FP8 support is available
jpp.ur = jpp.ur - 4;
}
assert(jpp.ur > 0);
// select jpp.ur_bc
if (jpp.tag_kind == jit_memory_tag_kind_t::nspc) {
auto min_ur_w = nstl::max(1, utils::div_up(jpp.l_pad, jpp.stride_w));
int min_ur_w1 = utils::div_up(right_pad, jpp.stride_w);
if (min_ur_w < min_ur_w1) { min_ur_w = min_ur_w1; }
jpp.ur_bc = nstl::min(jpp.nb_c, nstl::max(1, jpp.ur / min_ur_w));
//take into account threading - to have enough work for parallelization
float best_eff = 0;
for (int ur_bc = jpp.ur_bc; ur_bc > 0; ur_bc--) {
const auto nb2_c = utils::div_up(jpp.nb_c, ur_bc);
auto work = jpp.is_backward
? (ndims == 5 && jpp.simple_alg ? jpp.od : 1)
: (ndims == 5 ? jpp.od : jpp.oh);
work *= jpp.mb * nb2_c;
auto eff = (float)work / utils::rnd_up(work, jpp.nthr);
if (eff > best_eff) {
best_eff = eff;
jpp.ur_bc = ur_bc;
}
if (eff > 0.9f) break; // Heuristic threshold
}
//take into account cache re-usage after zeroing on backward
if (jpp.is_backward && ndims < 5) {
const int L2 = platform::get_per_core_cache_size(2)
/ sizeof(jpp.dt_size);
int ur_bc = nstl::max(1, L2 / (jpp.kh * jpp.iw * jpp.c_block));
jpp.ur_bc = nstl::min(jpp.ur_bc, ur_bc);
}
jpp.ur_bc_tail = jpp.nb_c % jpp.ur_bc;
} else {
jpp.ur_bc = 1;
jpp.ur_bc_tail = 0;
}
// scratchpad for c_block slice of input and/or output
using namespace memory_tracking::names;
const int nscr = nstl::min(dnnl_get_max_threads(), jpp.mb * jpp.nb_c);
if (jpp.tag_kind == jit_memory_tag_kind_t::ncsp) {
scratchpad.book(key_pool_src_plain2blocked_cvt,
static_cast<size_t>(jpp.c_block) * jpp.id * jpp.ih * jpp.iw
* nscr,
jpp.dt_size);
scratchpad.book(key_pool_dst_plain2blocked_cvt,
static_cast<size_t>(jpp.c_block) * jpp.od * jpp.oh * jpp.ow
* nscr,
jpp.dt_size);
scratchpad.book<uint32_t>(key_pool_ind_plain2blocked_cvt,
static_cast<size_t>(jpp.c_block) * jpp.od * jpp.oh * jpp.ow
* nscr);
}
jpp.post_ops = attr.post_ops_;
return status::success;
}
static int reg_ind(int shift, int bc, int j, int ur_bc, int ur_w) noexcept {
return shift * ur_bc * ur_w + bc * ur_w + j;
};
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::prepare_tail_mask() {
if (is_superset(isa, avx512_core)) {
size_t c_tail_mask = (1ULL << jpp.c_tail) - 1ULL;
mov(tmp_gpr.cvt32(), c_tail_mask);
kmovw(k_c_tail_mask, tmp_gpr.cvt32());
} else if (utils::one_of(isa, avx, avx2, avx2_vnni_2)) {
constexpr int max_words_in_ymm = 8;
// for 'avx2_vnni_2' mask works with 2 x xf16 elements,
// in case of 'c_tail % 2 != 0' load/store an additional word
// for the remaining element.
auto dt_elem_div = isa == avx2_vnni_2 ? 2 : 1;
auto mask_offset = max_words_in_ymm - (jpp.c_tail / dt_elem_div);
auto mask_register
= isa == avx2_vnni_2 ? xmm_c_tail_mask : vmm_c_tail_mask;
static const uint32_t mask[16] = {0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0,
0, 0, 0, 0, 0, 0, 0};
mov(tmp_gpr, reinterpret_cast<size_t>(&mask[mask_offset]));
vmovups(mask_register, ptr[tmp_gpr]);
}
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::put_one_in_vmm() {
mov(tmp_gpr, 1);
uni_broadcast_reg_val(tmp_gpr.getIdx(), vmm_one.getIdx());
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::uni_broadcast_reg_val(
const int reg_idx, const int vmm_idx) {
uni_vmovq(Xmm(vmm_idx), reg64_t(reg_idx));
uni_vpbroadcastd(Vmm(vmm_idx), Xmm(vmm_idx));
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::push_vmm_val(const int idx) {
Vmm val_to_store(idx);
sub(rsp, val_to_store.getBit());
uni_vmovups(ptr[rsp], val_to_store);
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::pop_vmm_val(const int idx) {
Vmm val_to_load(idx);
uni_vmovups(val_to_load, ptr[rsp]);
add(rsp, val_to_load.getBit());
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::load(const int idx,
const reg64_t ®_ptr, const int offset,
const bool is_c_tail_proccessing) {
if (jpp.is_bf16) {
/*TODO: maybe use vpmovzxwd + vpslld,
* in order to free up vmm_idx() register */
if (is_c_tail_proccessing && !jpp.is_c_padded) {
Vmm vmm_to_load = Vmm(idx) | k_c_tail_mask | T_z;
vpmovzxwd(vmm_to_load, ptr[reg_ptr + offset]);
vpslld(vmm_to_load, vmm_to_load, 16);
} else {
vmovups(Ymm(idx), ptr[reg_ptr + offset]);
vpermw(Vmm(idx) | k_mask_cvt | T_z, vmm_idx(), Vmm(idx));
}
} else if (jpp.is_f16) {
Vmm vmm_to_load = is_c_tail_proccessing && !jpp.is_c_padded
? Vmm(idx) | k_c_tail_mask | T_z
: Vmm(idx);
vcvtph2psx(vmm_to_load, ptr[reg_ptr + offset]);
} else if (jpp.is_fp8) {
Vmm vmm_to_load = is_c_tail_proccessing && !jpp.is_c_padded
? Vmm(idx) | k_c_tail_mask | T_z
: Vmm(idx);
if (jpp.src_dt == data_type::f8_e5m2)
f8_e5m2_emu_->vcvt_f8_to_f32(vmm_to_load, ptr[reg_ptr + offset]);
else if (jpp.src_dt == data_type::f8_e4m3)
f8_e4m3_emu_->vcvt_f8_to_f32(vmm_to_load, ptr[reg_ptr + offset]);
} else {
if (is_c_tail_proccessing && !jpp.is_c_padded) {
if (isa == avx || isa == avx2) {
vmaskmovps(Vmm(idx), vmm_c_tail_mask, ptr[reg_ptr + offset]);
} else {
vmovups(Zmm(idx) | k_c_tail_mask | T_z, ptr[reg_ptr + offset]);
}
} else {
uni_vmovups(Vmm(idx), ptr[reg_ptr + offset]);
}
}
}
template <>
inline void jit_uni_pool_kernel<avx2_vnni_2>::load(const int idx,
const reg64_t ®_ptr, const int offset,
const bool is_c_tail_proccessing) {
if (is_c_tail_proccessing) {
vmaskmovps(Xmm(idx), xmm_c_tail_mask, ptr[reg_ptr + offset]);
if (jpp.c_tail % 2 != 0) {
const int tail_pos = jpp.c_tail - 1;
auto word_addr
= ptr[reg_ptr + offset + tail_pos * sizeof(bfloat16_t)];
vpinsrw(Xmm(idx), Xmm(idx), word_addr, tail_pos);
}
}
if (jpp.is_bf16) {
if (is_c_tail_proccessing)
vpmovzxwd(Ymm(idx), Xmm(idx));
else
vpmovzxwd(Ymm(idx), ptr[reg_ptr + offset]);
vpslld(Ymm(idx), Ymm(idx), 16);
} else if (jpp.is_f16) {
if (is_c_tail_proccessing)
vcvtph2ps(Ymm(idx), Xmm(idx));
else
vcvtph2ps(Ymm(idx), ptr[reg_ptr + offset]);
} else
assert(!"invalid data type");
}
template <>
inline void jit_uni_pool_kernel<sse41>::load(const int idx,
const reg64_t ®_ptr, const int offset,
const bool is_c_tail_proccessing) {
if (is_c_tail_proccessing && !jpp.is_c_padded) {
for (int i = 0; i < jpp.c_tail % (jpp.c_block / 2); i++)
pinsrd(Xmm(idx), ptr[reg_ptr + offset + i * jpp.dt_size], i);
} else
uni_vmovups(Vmm(idx), ptr[reg_ptr + offset]);
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::store(const int idx,
const reg64_t ®_ptr, const int offset,
const bool is_c_tail_proccessing) {
if (jpp.is_bf16 || jpp.is_f16) {
if (is_c_tail_proccessing) {
if (jpp.is_c_padded) {
vmovdqu16(Ymm(idx) | k_c_tail_mask | T_z, Ymm(idx));
vmovups(yword[reg_ptr + offset], Ymm(idx));
} else
vmovdqu16(ptr[reg_ptr + offset] | k_c_tail_mask, Ymm(idx));
} else
vmovups(yword[reg_ptr + offset], Ymm(idx));
} else if (jpp.is_fp8) {
if (is_c_tail_proccessing) {
if (jpp.is_c_padded) {
vmovdqu8(Xmm(idx) | k_c_tail_mask | T_z, Xmm(idx));
vmovdqu8(yword[reg_ptr + offset], Xmm(idx));
} else
vmovdqu8(ptr[reg_ptr + offset] | k_c_tail_mask, Xmm(idx));
} else
vmovdqu8(yword[reg_ptr + offset], Xmm(idx));
} else {
if (is_c_tail_proccessing) {
if (!jpp.is_c_padded) {
if (isa == avx || isa == avx2)
vmaskmovps(
ptr[reg_ptr + offset], vmm_c_tail_mask, Vmm(idx));
else
vmovups(ptr[reg_ptr + offset] | k_c_tail_mask, Zmm(idx));
} else {
if (jpp.with_postops) {
if (isa == avx || isa == avx2) {
uni_vxorps(ymm_tmp_1, ymm_tmp_1, ymm_tmp_1);
uni_vblendvps(
Vmm(idx), ymm_tmp_1, Vmm(idx), vmm_c_tail_mask);
} else
uni_vmovups(Vmm(idx) | k_c_tail_mask | T_z, Vmm(idx));
}
uni_vmovups(vmmword[reg_ptr + offset], Vmm(idx));
}
} else
uni_vmovups(vmmword[reg_ptr + offset], Vmm(idx));
}
}
template <>
inline void jit_uni_pool_kernel<avx2_vnni_2>::store(const int idx,
const reg64_t ®_ptr, const int offset,
const bool is_c_tail_proccessing) {
if (jpp.is_bf16 || jpp.is_f16) {
if (is_c_tail_proccessing) {
vmaskmovps(ptr[reg_ptr + offset], xmm_c_tail_mask, Xmm(idx));
if (jpp.c_tail % 2 != 0) {
const int tail_pos = jpp.c_tail - 1;
auto word_addr = ptr[reg_ptr + offset + tail_pos * 2];
vpextrw(word_addr, Xmm(idx), tail_pos);
}
} else
vmovups(xword[reg_ptr + offset], Xmm(idx));
} else
assert(!"datatype not supported");
}
template <>
inline void jit_uni_pool_kernel<sse41>::store(const int idx,
const reg64_t ®_ptr, const int offset,
const bool is_c_tail_proccessing) {
if (is_c_tail_proccessing) {
if (!jpp.is_c_padded) {
for (int i = 0; i < jpp.c_tail % (jpp.c_block / 2); i++)
pextrd(ptr[reg_ptr + offset + i * jpp.dt_size], Xmm(idx), i);
} else {
if (jpp.with_postops) {
static constexpr auto xmm_half = 4;
const auto tail_size = (jpp.c_without_padding > jpp.c_block)
? jpp.c_without_padding % (jpp.c - jpp.c_block)
: jpp.c_without_padding;
const auto tail_size_real = (tail_size >= xmm_half)
? tail_size - xmm_half
: tail_size;
uni_vxorps(xmm_tmp_1, xmm_tmp_1, xmm_tmp_1);
if (tail_size <= xmm_half && sse_high_half) {
// just zero out upper half padding and don't write anything else
uni_vmovups(vmmword[reg_ptr + offset], xmm_tmp_1);
return;
}
if ((tail_size < xmm_half && !sse_high_half)
|| (tail_size > xmm_half && sse_high_half)) {
std::bitset<8> tail_mask((1 << tail_size_real) - 1);
tail_mask.flip();
uni_vblendps(Vmm(idx), Vmm(idx), xmm_tmp_1,
tail_mask.to_ulong());
}
}
uni_vmovups(vmmword[reg_ptr + offset], Vmm(idx));
}
} else
uni_vmovups(vmmword[reg_ptr + offset], Vmm(idx));
}
template <cpu_isa_t isa>
bool jit_uni_pool_kernel<isa>::post_ops_ok(jit_pool_conf_t &jpp,
const primitive_attr_t &attr, const memory_desc_wrapper &dst_d) {
const auto &post_ops = attr.post_ops_;
const auto &entries = post_ops.entry_;
jpp.with_postops = false;
jpp.with_eltwise = false;
jpp.with_binary = false;
if (!jpp.is_backward) {
for (const auto &entry : entries) {
if (entry.is_eltwise()) {
const auto alg = entry.eltwise.alg;
jpp.with_eltwise = eltwise_injector::is_supported(
isa, alg, data_type::f32);
} else if (entry.is_binary()) {
const bool is_bf16_ok = IMPLICATION(
entry.binary.src1_desc.data_type == data_type::bf16,
utils::one_of(isa, avx512_core, avx2_vnni_2));
const bool is_f16_ok = IMPLICATION(
entry.binary.src1_desc.data_type == data_type::f16,
utils::one_of(isa, avx512_core_fp16, avx2_vnni_2));
const bool is_fp8_ok = IMPLICATION(
utils::one_of(entry.binary.src1_desc.data_type,
data_type::f8_e5m2, data_type::f8_e4m3),
utils::one_of(isa, avx512_core_fp16));
if (!(is_bf16_ok && is_f16_ok && is_fp8_ok)) return false;
jpp.with_binary = true;
} else
return false;
}
jpp.with_postops = jpp.with_eltwise || jpp.with_binary;
}
return binary_injector::binary_args_broadcast_supported(
post_ops, dst_d, get_supported_bcast_strategies());
}
template <cpu_isa_t isa>
void jit_uni_pool_kernel<isa>::apply_postops(int ur_bc, int ur_w, int c_block,
const std::function<bool(int, bool)> &is_tail_predicate) {
binary_injector::rhs_arg_dynamic_params_t rhs_arg_params;
const int end_idx = vmm_idx_upper_bound() + 1;
const int start_idx = end_idx - (ur_bc * ur_w);
const bool sse41_postops_disabled
= isa == sse41 && disable_postops_when_sse_high_half_processed_;
if (end_idx - start_idx == 0) return;
if (jpp.with_binary && !sse41_postops_disabled) {
const int c_off = (jpp.tag_kind == jit_memory_tag_kind_t::nspc)
? jpp.c
: c_block;
if (jpp.tag_kind == jit_memory_tag_kind_t::ncsp) {
mov(tmp_gpr, reg_output);
sub(tmp_gpr, ptr[reg_param + GET_OFF(dst)]);
add(tmp_gpr, ptr[reg_param + GET_OFF(dst_po_helper)]);
}
for (int jj = 0; jj < ur_w; jj++) {
for (int bci = 0; bci < ur_bc; bci++) {
const auto vmm_idx
= vreg(reg_ind(0, bci, jj, ur_bc, ur_w)).getIdx();
const size_t output_offset
= jpp.dt_size * (jj * c_off + bci * c_block);
rhs_arg_params.vmm_idx_to_out_reg.emplace(vmm_idx,
jpp.tag_kind == jit_memory_tag_kind_t::ncsp
? tmp_gpr
: reg_output);
rhs_arg_params.vmm_idx_to_out_elem_off_val.emplace(
vmm_idx, output_offset);
if (is_tail_predicate
&& is_tail_predicate(
bci, true /*process_with_postops*/)) {
rhs_arg_params.vmm_tail_idx_.emplace(vmm_idx);
}
}
}
}
postops_injector_->compute_vector_range(start_idx, end_idx, rhs_arg_params);
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::maybe_recalculate_divisor(
int jj, int ur_w, int pad_l, int pad_r, bool with_c_tail_proccessing) {
if (jpp.alg == pooling_avg_exclude_padding) {
int kw = jpp.kw;
int stride_w = jpp.stride_w;
int non_zero_kw = kw;
non_zero_kw -= nstl::max(0, pad_l - jj * stride_w);
non_zero_kw -= nstl::max(0, pad_r - (ur_w - 1 - jj) * stride_w);
if (non_zero_kw != prev_kw) {
mov(tmp_gpr, float2int((float)non_zero_kw));
uni_vmovq(xmm_tmp, tmp_gpr);
uni_vbroadcastss(vmm_tmp, xmm_tmp);
if (with_c_tail_proccessing
&& (utils::one_of(isa, avx, avx2, avx2_vnni_2))) {
push_vmm_val(vmm_c_tail_mask.getIdx());
uni_broadcast_reg_val(
reg_ker_area_h.getIdx(), vmm_ker_area_h.getIdx());
}
uni_vmulps(vmm_tmp, vmm_tmp, vmm_ker_area_h);
if (with_c_tail_proccessing
&& (utils::one_of(isa, avx, avx2, avx2_vnni_2))) {
pop_vmm_val(vmm_c_tail_mask.getIdx());
}
prev_kw = non_zero_kw;
}
}
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::avg_step(int ur_w, int ur_bc, int pad_l,
int pad_r, bool with_c_tail_proccessing) {
auto iw = jpp.iw;
auto kw = jpp.kw;
auto stride_w = jpp.stride_w;
auto c_block = jpp.c_block;
auto dt_size = jpp.dt_size;
const int c_off
= (jpp.tag_kind == jit_memory_tag_kind_t::nspc) ? jpp.c : c_block;
Label kd_label, kh_label;
const auto is_tail_processing = [&](int bc,
bool process_with_postops = false) {
if (isa == sse41 && (!jpp.is_c_padded || process_with_postops)) {
return with_c_tail_proccessing && bc == (ur_bc - 1)
&& ((jpp.c_tail > (jpp.c_block / 2) && sse_high_half)
|| (jpp.c_tail < (jpp.c_block / 2)
&& !sse_high_half));
} else
return with_c_tail_proccessing && bc == (ur_bc - 1);
};
for (int jj = 0; jj < ur_w; jj++) {
if (jpp.is_backward)
maybe_recalculate_divisor(
jj, ur_w, pad_l, pad_r, with_c_tail_proccessing);
for (int bci = 0; bci < ur_bc; bci++) {
const auto accr_i = reg_ind(0, bci, jj, ur_bc, ur_w);
auto accvr = vreg(accr_i);
if (jpp.is_backward) {
auto output_offset = dt_size * (jj * c_off + bci * c_block);
load(accvr.getIdx(), reg_output, output_offset,
is_tail_processing(bci));
uni_vdivps(accvr, accvr, vmm_tmp);
} else {
uni_vpxor(accvr, accvr, accvr);
}
}
}
if (jpp.simple_alg && jpp.ndims == 5) {
push(reg_input);
push(reg_output);
mov(aux_reg_input_d, reg_input);
mov(ki, ptr[reg_param + GET_OFF(kd_padding)]);
L(kd_label);
mov(aux_reg_input, aux_reg_input_d);
} else {
mov(aux_reg_input, reg_input);
}
xor_(kj, kj);
L(kh_label);
{
for (int ki = 0; ki < kw; ki++) {
int jj_start = nstl::max(0, utils::div_up(pad_l - ki, stride_w));
int jj_end = ur_w
- utils::div_up(
nstl::max(0, ki + pad_r - (kw - 1)), stride_w);
for_(int jj = jj_start; jj < jj_end; jj++)
for (int bci = 0; bci < ur_bc; bci++) {
const auto accvr = vreg(reg_ind(0, bci, jj, ur_bc, ur_w));
const auto inpr_i = reg_ind(1, bci, jj, ur_bc, ur_w);
auto inpvr = vreg(inpr_i);
int aux_input_offset
= (ki + jj * stride_w - pad_l) * c_off + bci * c_block;
if (aux_input_offset >= iw * c_off) continue;
int input_offset = dt_size * aux_input_offset;
if (jpp.is_backward) {
auto inpyr = yreg(inpr_i);
load(reg_idx(inpr_i), aux_reg_input, input_offset,
is_tail_processing(bci));
uni_vaddps(inpvr, inpvr, accvr);
if (jpp.is_bf16) {
if (!isa_has_bf16(jpp.isa))
bf16_emu_->vcvtneps2bf16(inpyr, zreg(inpr_i));
else
vcvtneps2bf16(inpyr, inpvr);
} else if (jpp.is_f16) {
vcvtps2ph(inpyr, inpvr, _op_mxcsr);
} else if (jpp.is_fp8) {
auto inpxr = xreg(inpr_i);
if (jpp.src_dt == data_type::f8_e5m2)
f8_e5m2_emu_->vcvt_f32_to_f8(inpxr, zreg(inpr_i));
else if (jpp.src_dt == data_type::f8_e4m3)
f8_e4m3_emu_->vcvt_f32_to_f8(inpxr, zreg(inpr_i));
}
store(reg_idx(inpr_i), aux_reg_input, input_offset,
is_tail_processing(bci));
} else {
if (jpp.is_bf16 || jpp.is_f16 || jpp.is_fp8
|| is_tail_processing(bci)
|| (isa == sse41
&& c_off % (jpp.c_block / 2) != 0)) {
load(vmm_tmp_1.getIdx(), aux_reg_input, input_offset,
is_tail_processing(bci));
uni_vaddps(accvr, accvr, vmm_tmp_1);
} else {
uni_vaddps(accvr, accvr,
ptr[aux_reg_input + input_offset]);
}
}
}
}
add(aux_reg_input, jpp.dt_size * iw * c_off);
inc(kj);
cmp(kj, reg_kh);
jl(kh_label, T_NEAR);
}
if (jpp.simple_alg && jpp.ndims == 5) {
add(aux_reg_input_d, jpp.dt_size * jpp.ih * iw * c_off);
dec(ki);
cmp(ki, 0);
jg(kd_label, T_NEAR);
pop(reg_output);
pop(reg_input);
}
if (!jpp.is_backward) {
for (int jj = 0; jj < ur_w; jj++) {
maybe_recalculate_divisor(
jj, ur_w, pad_l, pad_r, with_c_tail_proccessing);
for (int bci = 0; bci < ur_bc; bci++) {
const auto accr_i = reg_ind(0, bci, jj, ur_bc, ur_w);
const auto accvr = vreg(accr_i);
uni_vdivps(accvr, accvr, vmm_tmp);
}
}
if (jpp.with_postops)
apply_postops(ur_bc, ur_w, c_block, is_tail_processing);
for (int jj = 0; jj < ur_w; jj++) {
for (int bci = 0; bci < ur_bc; bci++) {
const auto accr_i = reg_ind(0, bci, jj, ur_bc, ur_w);
const auto accvr = vreg(accr_i);
const auto output_offset
= dt_size * (jj * c_off + bci * c_block);
const auto accyr = yreg(accr_i);
if (jpp.is_bf16) {
if (isa == avx2_vnni_2) {
auto accxr = xreg(accr_i);
vcvtneps2bf16(accxr, accyr, Xbyak::VexEncoding);
} else {
const auto acczr = zreg(accr_i);
if (!isa_has_bf16(jpp.isa))
bf16_emu_->vcvtneps2bf16(accyr, acczr);
else
vcvtneps2bf16(accyr, accvr);
}
} else if (jpp.is_f16) {
if (isa == avx2_vnni_2) {
auto accxr = xreg(accr_i);
vcvtps2ph(accxr, accyr, _op_mxcsr);
} else
vcvtps2ph(accyr, accvr, _op_mxcsr);
} else if (jpp.is_fp8) {
const auto accxr = xreg(accr_i);
if (jpp.src_dt == data_type::f8_e5m2)
f8_e5m2_emu_->vcvt_f32_to_f8(accxr, accvr);
else if (jpp.src_dt == data_type::f8_e4m3)
f8_e4m3_emu_->vcvt_f32_to_f8(accxr, accvr);
}
store(reg_idx(accr_i), reg_output, output_offset,
is_tail_processing(bci));
}
}
}
}
template <cpu_isa_t isa>
inline void jit_uni_pool_kernel<isa>::max_step_fwd(int ur_w, int ur_bc,
int pad_l, int pad_r, bool with_c_tail_proccessing) {
int iw = jpp.iw;
int kw = jpp.kw;
int stride_w = jpp.stride_w;
int c_block = jpp.c_block;
const int c_off
= (jpp.tag_kind == jit_memory_tag_kind_t::nspc) ? jpp.c : c_block;
Label kd_label, kh_label;
auto is_tail_processing = [&](int bc, bool process_with_postops = false) {
if (isa == sse41 && (!jpp.is_c_padded || process_with_postops)) {
return with_c_tail_proccessing && bc == (ur_bc - 1)
&& ((jpp.c_tail > (jpp.c_block / 2) && sse_high_half)
|| (jpp.c_tail < (jpp.c_block / 2)
&& !sse_high_half));
} else
return with_c_tail_proccessing && bc == (ur_bc - 1);
};
mov(tmp_gpr, float2int(nstl::numeric_limits<float>::lowest()));
uni_vmovq(xmm_tmp, tmp_gpr);
uni_vbroadcastss(vmm_tmp, xmm_tmp);
for_(int jj = 0; jj < ur_w; jj++)
for (int bci = 0; bci < ur_bc; bci++) {
const auto accvr = vreg(reg_ind(0, bci, jj, ur_bc, ur_w));
uni_vmovups(accvr, vmm_tmp);
if (jpp.is_training) {
const auto indvr = vreg(reg_ind(2, bci, jj, ur_bc, ur_w));
uni_vpxor(indvr, indvr, indvr);
}
}
if (jpp.is_training) {
uni_vmovq(xmm_tmp, reg_k_shift);
uni_vpbroadcastd(vmm_k_offset, xmm_tmp);
}
if (jpp.ndims == 5) {
push(reg_input);
push(reg_output);
mov(aux_reg_input_d, reg_input);