From 9451474816c2e0cbfa107f0bee761cdff2c7a64d Mon Sep 17 00:00:00 2001 From: Robin Pedersen Date: Mon, 11 Sep 2023 15:35:08 +0200 Subject: [PATCH 1/2] csv2json: only repeat certain empty cells Signed-off-by: Robin Pedersen --- bin/csv2json | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/bin/csv2json b/bin/csv2json index b218fa80b3..883ec5fdce 100755 --- a/bin/csv2json +++ b/bin/csv2json @@ -57,11 +57,16 @@ csv_reader = csv.DictReader(csv_file) csv_rows = [] csv_row_previous = None +def should_fill_cell(cell_value, previous_row, row_key): + cell_is_empty = not cell_value + previous_row_exists = previous_row + column_should_repeat = row_key in ['Feature', 'Verification Goal'] + return cell_is_empty and previous_row_exists and column_should_repeat + for row in csv_reader: for key, value in row.items(): - if not value and csv_row_previous: + if should_fill_cell(value, csv_row_previous, key): row[key] = csv_row_previous[key] - # TODO not for "link-to-cov" etc csv_rows.append(row) csv_row_previous = row From 0c89e6775d945bde580bd87d3a963d98f411997d Mon Sep 17 00:00:00 2001 From: Robin Pedersen Date: Mon, 11 Sep 2023 15:45:51 +0200 Subject: [PATCH 2/2] csv2json: apply to 40s vplans Signed-off-by: Robin Pedersen --- .../Zc/RV32Zc_Extension_Instructions.json | 1598 ++++++++++ .../debug-trace/CV32E40XS_debug.json | 2706 +++++++++++++++++ .../Simulation/interrupts/CV32E40SX_CLIC.json | 1663 ++++++++++ .../micro_architecture/CV32E40SX_fencei.json | 422 +++ .../CV32E40SX_PMA_VerifPlan.json | 866 ++++++ .../privileged_spec/CV32E40S_PMP.json | 1718 +++++++++++ .../privileged_spec/CV32E40S_UserMode.json | 830 +++++ .../Simulation/xsecure/xsecure_vplan.json | 2114 +++++++++++++ 8 files changed, 11917 insertions(+) create mode 100644 cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json create mode 100644 cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json create mode 100644 cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json create mode 100644 cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json create mode 100644 cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json create mode 100644 cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json create mode 100644 cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json create mode 100644 cv32e40s/docs/VerifPlans/Simulation/xsecure/xsecure_vplan.json diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json new file mode 100644 index 0000000000..d6425f6acc --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json @@ -0,0 +1,1598 @@ +[ + { + "Requirement Location": "Zc 1.0.1 ace0ee", + "Feature": "Zca", + "Sub Feature": "c.f*", + "Feature Description": "floating point load stores shall decode as illegal", + "Verification Goal": "Verify that all variations of these instructions decode as illegal \nCross check with instructions used in Zcmp/t", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zca", + "Sub Feature": "c.*", + "Feature Description": "The remaining instructions in the C extension shall be verified, follow existing C extension verification plan", + "Verification Goal": "Verified in C extension ", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lbu", + "Feature Description": "Load unsigned byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lhu", + "Feature Description": "Load unsigned halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lh", + "Feature Description": "Load signed halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sb", + "Feature Description": "Store byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rs1 == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sh", + "Feature Description": "Store halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rs1 == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.zext.b", + "Feature Description": "Zero extend byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sext.b", + "Feature Description": "Sign extend byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.zext.h", + "Feature Description": "Zero extend halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sext.h", + "Feature Description": "Sign extend halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.not", + "Feature Description": "Bitwise not, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.mul", + "Feature Description": "Multiply, 16-bit encoding", + "Verification Goal": "M_EXT=M_NONE shall result in c.mul decoding as an illegal instruction", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rsd == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.push", + "Feature Description": "Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify instruction with watchpoint triggers on data address ", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. (the order might change)\n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.pop", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify instruction with watchpoint triggers on data address ", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.popret", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.popretz", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.mva01s", + "Feature Description": "Move a0-a1 into two registers of s0-s7", + "Verification Goal": "Verify all possible variatons of sreg1, sreg2. Note that sreg1 = sreg2 is illegal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.mvsa01", + "Feature Description": "Move two s0-s7 registers into a0-a1", + "Verification Goal": "Verify all possible variatons of sreg1, sreg2.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "cm.jt", + "Feature Description": "jump via table without link", + "Verification Goal": "Verify all possible variations of index", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "cm.jalt", + "Feature Description": "jump via table and link to ra", + "Verification Goal": "Verify all possible variations of index", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "JVT CSR", + "Feature Description": "Table Jump base vector and control register", + "Verification Goal": "csr stateen bit 2 controls user mode access, if bit is not set, cm.jt and cm.jalt should decode as illegal.\nAccess also controlled with smstateen, illegal if not enabled.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT is used as base for jt/jalt", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump 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+ "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from 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"Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" 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"Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump 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"Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" 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+ }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json new file mode 100644 index 0000000000..a9ef9f1b7c --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json @@ -0,0 +1,2706 @@ +[ + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1\ncause = 1\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug cod\n\nEnsure exception routine is not enterred", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "Are Lee's corner cases handled in this vplan?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug cod\n\nEnsure exception routine is not enterred", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_with_ebreakm\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_with_ebreakm\nA :uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "Is Mike's gh issue handled in this vplan?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1\ncause = 1\n\n40S, same is true for \"dcsr.ebreaku\".\n", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary exception code\nVerify that:\nCore switches into debug mode.\nPC of EBREAK instruction must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "Is the PMA overrule handled in this vplan?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary exception code\nVerify that:\nCore switches into debug mode.\nPC of EBREAK instruction must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "N/A: Hard to detect that we are executing an exception handler.\nCovered in debug_test with ISS enabled.\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "Note: From OE about counters, \"vi burde ogs\u00e5 ha assert som sjekker at vi IKKE teller n\u00e5 countinhibit, sleep, eller stopcount... de assertionene jeg har endre sjekker bare at de teller... vet du om vi har andre sjekker p\u00e5 dette?\"", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter ebreak exception", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0.\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0.\n\nVerify that:\nCore does not switch to debug mode, but exception routine is entered as normal.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter ebreak exception", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0.\n\nVerify that:\nCore does not switch to debug mode, but exception routine is entered as normal.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_regular_nodebug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_regular_nodebug)\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception\nA: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter ebreak exception during single stepping", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0.\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary single stepping code\n\nVerify that:\nCore switches into debug mode.\nDPC set to handler.\nDebug cause must be step (unless something else happened simultaneously).\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_known_miscompares\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter ebreak exception during single stepping", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary single stepping code\n\nVerify that:\nCore switches into debug mode.\nDPC set to handler.\nDebug cause must be step (unless something else happened simultaneously).\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_step_nodebug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_step_nodebug)\n\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception\nA: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "CV32E40P doc rev 46711ac", + "Requirement Location": "Debug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "External debug event", + "Feature Description": "Debug mode can be entered by asserting the external signal debug_req_i\ncause is set to = 3 (also see verification goal)", + "Verification Goal": "Assert debug_req_i while executing arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=debugger(0x3))\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert debug_req_i while executing arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=debugger(0x3))\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_debug_mode_pc\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_haltreq\nA: uvmt_cv32_tb.u_debug_assert.a_debug_req_taken", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "CV32E40P doc rev 46711ac\n\nRISCV-V External Debug Support Version 0.13.2", + "Requirement Location": "Debug chapter \n\n\n\nChapter 5", + "Feature": "Trigger module", + "Sub Feature": "Trigger module match event", + "Feature Description": "The core contains a trigger module with a configurable number of trigger register capable of triggering on i.a. instruction address match.\nSelect mcontrol6 for a trigger and enable instruction matching\nWrite breakpoint addr to tdata2 register\ncause = 2", + "Verification Goal": "Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored.\n\nEnter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2]\nExit debug mode (dret instruction)\nVerify that core enters debug mode on breakpoint addr\nCurrent PC is saved to DPC\nCause of debug must be saved to DCSR (cause=2)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored.\n\nEnter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2]\nExit debug mode (dret instruction)\nVerify that core enters debug mode on breakpoint addr\nCurrent PC is saved to DPC\nCause of debug must be saved to DCSR (cause=2)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "CV32E40P doc rev 46711ac\n\nRISCV-V External Debug Support Version 0.13.2", + "Requirement Location": "Debug chapter \n\n\n\nChapter 5", + "Feature": "Trigger module", + "Sub Feature": "Trigger module match event", + "Feature Description": "When trigger module is disabled, no trigger should fire even though the PC matches the address in tdata2.", + "Verification Goal": "Enter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1\nExit debug mode (dret instruction)\nVerify that core does not enter debug mode on breakpoint addr\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Enter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1\nExit debug mode (dret instruction)\nVerify that core does not enter debug mode on breakpoint addr\n", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: cg_trigger_match_disabled\nA: uvmt_cv32_tb.u_debug_assert.a_trigger_match_disabled\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug & Trigger", + "Feature": "Trigger module", + "Sub Feature": "Number of triggers", + "Feature Description": "The number of triggers is determined by DBG_NUM_TRIGGERS.\nWhen num triggers is 0, accessing the trigger registers causes illegal instruction exception.\nTriggers never fire.\n\"tselect\" is 0.", + "Verification Goal": "Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that \"tselect\" is 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[40x? Also below.]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that \"tselect\" is 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "The number of triggers is determined by DBG_NUM_TRIGGERS.\nDBG_NUM_TRIGGERS can be any value within 0-4.\n\"tselect\" is WARL (0x0 - (DBG_NUM_TRIGGERS-1)).\n\"tcontrol\" is WARL (0x0).\nAll selectable triggers are functional.\nAll trigger registers are accessible except for \"mcontext\", \"mscontext\", \"hcontext\", and \"scontext\" (those four trap upon access).", + "Verification Goal": "For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher \"tselect\" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "There are a lot of things to check in a single point here. Nothing is wrong with this point as I see it, so there is no need to change, but ideally this point should be split up.", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher \"tselect\" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nMatch Control Type 6", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" match types", + "Feature Description": "The \"load\" and \"store\" bits are supported (so load/store addr matching is supported).\nThe \"execute\" bit is also supported.\nThe only supported match types are \"address match\" for {instr execution, load, store}, all using \"before\" timing so \"mcontrol6.timing\" is always 0.\nData matching is not supported (only addr matching), so \"mcontrol6.select\" is always 0.", + "Verification Goal": "Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. Also check that the tied fields are tied. All of these configurations must be crossed, also against match conditions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. Also check that the tied fields are tied. All of these configurations must be crossed, also against match conditions.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" match conditions", + "Feature Description": "Supported match conditions in \"mcontrol6.match\" are {0 (eq), 2 (geq), 3 (less)}.", + "Verification Goal": "Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the \"match types\" item above.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the \"match types\" item above.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" compare values", + "Feature Description": "\nInstr execute matching uses only one \"compare value\" (the PC itself).\nLoad/Store matching uses compare values depending on the size of the access {A, A+1, etc}.", + "Verification Goal": "Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" enable", + "Feature Description": "Triggers can be en/disabled in M-mode, \"mcontrol6.m\", default is 0.\n40S, triggers can be en/disabled in U-mode, \"mcontrol6.u\", default is 0.\n40X, triggers cannot be enabled in U-mode, \"mcontrol6.u\", WARL (0x0).\nThe trigger action is always to enter D-mode, so \"mcontrol6.action\" is always 1.", + "Verification Goal": "Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" atomics", + "Feature Description": "40X, \"mcontrol6\" trigger behavior has specific descriptions for \"A\" extension.", + "Verification Goal": "40X, this section must be filled out when the time comes for planning atomics verification.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nTrigger Data 1", + "Feature": "Trigger module", + "Sub Feature": "\"tdata1.type\"", + "Feature Description": "The only supported types are \"2 = address match legacy\", \"5 = Exception trigger\", \"6 = Address match\", and \"15 = Disabled\".", + "Verification Goal": "Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is \"15\".", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is \"15\".", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"tdata1.dmode\"", + "Feature Description": "This bit is WARL (0x1), so only D-mode can write tdata registers. And this bit is still WARL (0x1) regardless of \"type\" (2, 5, 6, 15).", + "Verification Goal": "Try to write tdata registers outside of debug mode, check that it traps. Try changing \"tdata1.dmode\" and check that it is WARL (0x1). Cross the above checks with all supported types.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try to write tdata registers outside of debug mode, check that it traps. Try changing \"tdata1.dmode\" and check that it is WARL (0x1). Cross the above checks with all supported types.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nTrigger Info", + "Feature": "Trigger module", + "Sub Feature": "\"tinfo\"", + "Feature Description": "\"tinfo.info\" holds the supported types {2, 5, 6, 15}, and the register is otherwise WARL (0x0).", + "Verification Goal": "When num triggers is 0, check that \"tinfo\" is 0.\nFor any other num triggers, check that \"tinfo.info\" is \"1\" for the three supported types, and that the remaining bits are 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "When num triggers is 0, check that \"tinfo\" is 0.\nFor any other num triggers, check that \"tinfo.info\" is \"1\" for the three supported types, and that the remaining bits are 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nException Trigger", + "Feature": "Trigger module", + "Sub Feature": "\"etrigger\"", + "Feature Description": "A trigger (\"tdata1\") can be configured as an exception trigger (\"etrigger\"). Where \"tdata2\" configures the exceptions to fire upon.", + "Verification Goal": "Configure \"tdata1\" and \"tdata2\" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure \"tdata1\" and \"tdata2\" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "The bits {\"hit\", \"vs\", \"vu\", \"s\"} are not supported (WARL 0).\n\"nmi\" does not exist (mentioned because it briefly did).\n\"m\" is fully supported.\n40S, \"u\" is fully supported.\n40X, \"u\" is not supported (WARL0).\nThe triggers always enter D-mode, so \"etrigger.action\" is WARL 1.", + "Verification Goal": "Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40s User Manual 0.8.0", + "Requirement Location": "Debug Chapter", + "Feature": "debug_pc_o", + "Sub Feature": "", + "Feature Description": "Signal \"debug_pc_o\" is the PC of the last retired instruction The signal is only valid when \"debug_pc_valid_o\" is equal to 1", + "Verification Goal": "Verify that the signal can be matched with related rvfi signals", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Assertion Check", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o\nA: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o_inv", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Debug exception addr", + "Sub Feature": "", + "Feature Description": "If an exception occurs during debug mode, the PC should be set to the dm_exception_addr_i input without changing the status registers", + "Verification Goal": "Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers\nAccording to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Point mentions the exceptions supported by the e40p, need to match 40s/x capabilities and update text", + "Review (Robin)": "\"0.8.0\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug exception addr", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers\nAccording to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_exception\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ecall\nA: uvmt_cv32_tb.u_debug_assert.a_debug_mode_exception", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Core debug registers", + "Sub Feature": "Illegal access", + "Feature Description": "Accessing the core debug registers - DCSR, DPC and DSCRATCH0/1 while NOT in debug mode causes an illegal instruction", + "Verification Goal": "Access all debug registers in M-mode and observe that illegal instruction exception is triggered.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Core debug registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Access all debug registers in M-mode and observe that illegal instruction exception is triggered.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_regs_m_mode\nA: uvmt_cv32_tb.u_debug_assert.a_debug_regs_mmode", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Debug Control and Status", + "Feature": "\"dcsr\" writability", + "Sub Feature": "", + "Feature Description": "All fields of \"dcsr\" (except some) are only writable by the external debugger. Exceptions are {\"v\", \"prv\", \"cause\", \"nmip\"}.", + "Verification Goal": "Keep track of whether an external debug request has happened, check that if there is a change in \"dcsr\" (except some) then there must have been an external debug request.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Trigger module registers", + "Sub Feature": "Access from M-mode", + "Feature Description": "Accessing the trigger module registers - tselect, tdata1/2/3, tinfo, tcontrol are readable from M-mode, but not writeable. (And is not accessible at all from U-mode.)", + "Verification Goal": "Access all trigger module registers in M-mode and observe writes have no effects and reads should reflect register content.\n\nAccess registers from D-mode and observe full R/W access.\n\nAccess from U-mode and observe no access at all.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Should we also check r/w in U-mode?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Access all trigger module registers in M-mode and observe writes have no effects and reads should reflect register content.\n\nAccess registers from D-mode and observe full R/W access.\n\nAccess from U-mode and observe no access at all.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_regs\n", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Trigger Registers", + "Feature": "Trigger module registers", + "Sub Feature": "\"tdata1\", writing zero", + "Feature Description": "\"it is guaranteed that writing 0 to tdata1 disables the trigger, and leaves it in a state where tdata2 and tdata3 can be written with any value that makes sense for any trigger type supported by this trigger.\"\n\nMore generally, \"When a selected trigger is disabled [type 15], tdata2 and tdata3 can be written with any value supported by any of the types this trigger supports\".", + "Verification Goal": "Write 0 to \"tdata1\", ensure that its state becomes disabled (type 15). Write values to \"tdata2\" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Write 0 to \"tdata1\", ensure that its state becomes disabled (type 15). Write values to \"tdata2\" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "\"tdata2\" and \"tdata3\"", + "Feature Description": "\"tdata2\" should always be RW (any), and \"tdata3\" is always WARL (0x0).", + "Verification Goal": "Change the type to 2/5/6/15 and write any data to \"tdata2\", read it back and check that it always gets set. Do the same for \"tdata3\" and check that it always reads back 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "Type 2", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Change the type to 2/5/6/15 and write any data to \"tdata2\", read it back and check that it always gets set. Do the same for \"tdata3\" and check that it always reads back 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "Type 2", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "Other tdata registers", + "Feature Description": "Writing one \"tdata*\" register must not modify other \"tdata*\" registers, and must not modify other triggers than the currently selected.", + "Verification Goal": "Read the state of all triggers, write to tdata1/2/3 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one \"tdata*\" register that was written.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Read the state of all triggers, write to tdata1/2/3 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one \"tdata*\" register that was written.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt2", + "Feature": "Program Buffer", + "Sub Feature": "Interrupts", + "Feature Description": "While in debug mode and executing from the program buffer, all interrupts are masked.", + "Verification Goal": "Enable interrupts (setting mstatus.mie field and mie register).\nBring core into debug mode and start executing from program buffer.\nGenerate interrupts while in debug mode and ensure they are masked.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Enable interrupts (setting mstatus.mie field and mie register).\nBring core into debug mode and start executing from program buffer.\nGenerate interrupts while in debug mode and ensure they are masked.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_in_debug\nA: uvmt_cv32_tb.u_debug_assert.a_irq_in_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt3", + "Feature": "Program Buffer", + "Sub Feature": "Exceptions", + "Feature Description": "While in debug mode and executing from the program buffer, exceptions don\u2019t update any registers but they DO end execution of PB (TBD: goes back to M-mode or restarts in debug(?)) [PZ] this is redundnant with dm_exception_addr_i (on line 10 & 11)", + "Verification Goal": "Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn\u2019t update any registers, and jumps out of debug mode into M-mode", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn\u2019t update any registers, and jumps out of debug mode into M-mode", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt4", + "Feature": "Program Buffer", + "Sub Feature": "Triggers", + "Feature Description": "While in debug mode and executing from the program buffer, no action is taken on any trigger match.", + "Verification Goal": "Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match_disabled (d_match_with_en)", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "dcsr", + "Feature": "Counters", + "Sub Feature": "", + "Feature Description": "Spec:Counters may be stopped, depending on stopcount in dscr", + "Verification Goal": "\"dcsr.stopcount\" is WARL and we must test the counter bevaior for both values of stopcount.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "Is wrong, need update.", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Counters", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "\"dcsr.stopcount\" is WARL and we must test the counter bevaior for both values of stopcount.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_counters_enabled\nA: uvmt_cv32_tb.u_debug_assert.a_minstret_count\nA: uvmt_cv32_tb.u_debug_assert.a_mcycle_count", + "Review (Marton)": "?", + "Review (Robin)": "Any other \"40p\" outdateds here? Marked them all.", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt6", + "Feature": "Program Buffer", + "Sub Feature": "Timers", + "Feature Description": "Timers may be stopped, depending on stoptime in dcsr", + "Verification Goal": "(See \"Counters\" above.)", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt7", + "Feature": "Program Buffer", + "Sub Feature": "WFI instruction", + "Feature Description": "In debug, the WFI instruction acts as a NOP instruction", + "Verification Goal": "Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_in_debug\nA: uvmt_cv32_tb.u_debug_assert.a_wfi_in_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt8", + "Feature": "Program Buffer", + "Sub Feature": "Priv. lvl changes", + "Feature Description": "An ebreak instruction during debug shall result in relaunching the debugger entry code by setting the PC to the halt_addr_i and will not change any CSR in doing this.", + "Verification Goal": "Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_with_ebreakm (.ebreak_in_debug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_with_ebreakm (.ebreak_in_debug)\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_during_debug_mode", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt9", + "Feature": "Program Buffer", + "Sub Feature": "Fence instructions", + "Feature Description": "Completing program buffer execution is considered output for the purpose of the fence instruction.", + "Verification Goal": "TBD - need to understand the fence instruction in cv32e40s. Is \"completing program buffer execution\" the same as executing dret? [PZ] waiting for more clarity from RISCV Foundation debug task group (see https://lists.riscv.org/g/tech-debug/topic/clarification_request/75725318?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,75725318 )\n\nNothing to do. That sentence was retracted here https://github.com/riscv/riscv-debug-spec/pull/601/files . Now it seems they just recommend debug software to do a fence when completing abstract commands.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "What are we doing here?", + "Review (Robin)": "Added N/A disclaimer. Striking it.", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt10", + "Feature": "Program Buffer", + "Sub Feature": "Ctrl. Transfer instr.", + "Feature Description": "All control transfer instructions may act as illegal instructions if destination is within program buffer. If one does, all must.", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt11", + "Feature": "Program Buffer", + "Sub Feature": "Ctrl. Transfer instr.", + "Feature Description": "All control transfer instructions may as illegal instructions if destination is outside the program buffer. If one does, all must.", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt12", + "Feature": "Program Buffer", + "Sub Feature": "Instr. Dependent of PC", + "Feature Description": "Instructions that depend on the PC may act as illegal instructions", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt13", + "Feature": "Program Buffer", + "Sub Feature": "Effective XLEN", + "Feature Description": "Effective XLEN = DXLEN", + "Verification Goal": "CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode\nMike: what exactly would a testcase actually do to check this?\n\u00d8K: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode\nMike: what exactly would a testcase actually do to check this?\n\u00d8K: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.2 Load-Reserved/Store-Conditional", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "N/A for CV32E40s (requires A-extention) : need Arjan/Davide to sign-off on this. [PZ] This is not a test but a warning or assumption that debug entry should not occur between a lr and sc instruction pair. Moreover, CV32E40s does not support A-extension", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.3 Wait for interrupt", + "Feature": "Debug mode", + "Sub Feature": "WFI instruction", + "Feature Description": "If debug_req_i is asserted while waiting for interrupt (core_sleep_o = 1), WFI instruction must complete (core_sleep_o -> 0) and hart enters debug mode.", + "Verification Goal": "Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Update reference document, applies to several following points", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_debug_req\nA: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req_wu\nA: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "By setting step in dcsr[2] before resuming execution, a debugger can cause the hart to execute a single instructin before re-entering debug mode.", + "Verification Goal": "Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the instruction being fetched or executed in a single step casues an exception, debug mode is entered immediately after the PC is changed to the exception handler and registers tval and cause are updated.\n\nNote: CV32E40S does not support tval (this might be supported in future cores)", + "Verification Goal": "Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode.\n\nCheck tval==0", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Update to reflect that we are now checking \"future cores\"", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode.\n\nCheck tval==0", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_illegal)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_exception", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the instruction being fetched or executed in a single step causes a trigger, debug mode is entered immediately after the trigger fired. Cause is set to 2 instead of 4", + "Verification Goal": "Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_trigger_match)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the intruction executed in the single step results in a PC that will cause an exception, the exception will not execute until the next time the hart resumes.", + "Verification Goal": "Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the intruction executed in the single step results in a PC that will cause a trigger event, the trigger event will not take place until the instruction is executed.", + "Verification Goal": "This can be verified in the same steps as marked with (#1).\nMike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "This can be verified in the same steps as marked with (#1).\nMike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_next_pc_will_match)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the single step instruction is WFI, it must be treated as a nop instead of stalling and waiting for interrupt. [PZ] #pz_ref2", + "Verification Goal": "Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_wfi)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_wfi", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.5 Reset", + "Feature": "Debug mode", + "Sub Feature": "Reset", + "Feature Description": "When the hart comes out of reset, it must immediately enter debug mode without executing any instructions if the halt signal or debug_req_i is asserted.", + "Verification Goal": "Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_reset\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_at_reset\nA: uvmt_cv32_tb.u_debug_assert.a_debug_at_reset", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.6 dret instruction", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "Executing dret while NOT in debug mode will cause an illegal instruction exception.", + "Verification Goal": "Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown.\nCan be tested in the same test as for debug entry", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown.\nCan be tested in the same test as for debug entry", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret\nA: uvmt_cv32_tb.u_debug_assert.a_mumode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.6 dret instruction", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "Executing dret while in debug mode will restore PC to the value in dpc and exit debug mode.", + "Verification Goal": "Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. \nCan be tested in the same test as for debug entry.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "remove note, this is covered or 40s (U-Mode) in the next point", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. \nCan be tested in the same test as for debug entry.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret\nA: uvmt_cv32_tb.u_debug_assert.a_dmode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Execution Based", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "40S, \"When dret is executed, [\u2026] normal execution resumes at the privilege set by prv\"", + "Verification Goal": "Be in debug mode, note the value in \"dcsr.prv\", exit debug mode with a \"dret\", check that the mode being executed in is the one indicated by \"dcsr.prv\". (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode, note the value in \"dcsr.prv\", exit debug mode with a \"dret\", check that the mode being executed in is the one indicated by \"dcsr.prv\". (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Resume", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "40S, \"If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.\"", + "Verification Goal": "Be in debug mode, set \"dcsr.prv\" to U-mode, let \"mstatus.MPRV\" be set and clear (different runs), exit debug mode with a \"dret\", check that \"mstatus.MPRV\" ends up cleared. (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode, set \"dcsr.prv\" to U-mode, let \"mstatus.MPRV\" be set and clear (different runs), exit debug mode with a \"dret\", check that \"mstatus.MPRV\" ends up cleared. (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Debug Control and Status", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "\"Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in\"", + "Verification Goal": "40S, enter debug mode from different modes, check that \"dcsr.prv\" represents the previous mode. (Note overlap with user mode vplan.)\n\n40X, check that \"dcsr.prv\" is always M-mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "40S, enter debug mode from different modes, check that \"dcsr.prv\" represents the previous mode. (Note overlap with user mode vplan.)\n\n40X, check that \"dcsr.prv\" is always M-mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Semihosting", + "Sub Feature": "", + "Feature Description": "To enable semihosting, a special instruction sequence is needed as there is only a single EBREAK instruction available.\n\nslli x0, x0, 0x1f # Entry NOP\nebreak # Break to debugger\nsrai x0, x0, 7 # NOP encoding the semihosting call number 7\n\n[PZ] This is a software convention and need not be tested in verification. As long as the above instructions work in general, then no need for dedicated semihosting testing.", + "Verification Goal": "If all points above passes, there should be nothing to verify here. Semihosting will be handled from SW.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger", + "Sub Feature": "Exception handling", + "Feature Description": "If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address\n\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger, single step", + "Sub Feature": "Exception handling", + "Feature Description": "If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. \nSet up single stepping such that the match address will be executed in the next step.\nWhen the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger, single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. \nSet up single stepping such that the match address will be executed in the next step.\nWhen the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address\n\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0\n\nOBI-v1.4", + "Requirement Location": "Core Integration\n\ndbg", + "Feature": "OBI", + "Sub Feature": "", + "Feature Description": "OBI bus accesses shall indicate whether the core is in D-mode or not, signaled via \"instr_dbg_o\" and \"data_dbg_o\".", + "Verification Goal": "Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have \"dbg\" set correspondingly.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "OBI", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have \"dbg\" set correspondingly.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr_inv\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data_inv", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nDebug Control and Status", + "Feature": "NMI", + "Sub Feature": "", + "Feature Description": "The \"dcsr.nmip\" bit is supported.\nWhen a non-maskable interrupt is pending, then this bit must be high.", + "Verification Goal": "Cause an NMI to occur, read \"dcsr.nmip\", check that it is high as expected. Have no NMI pending, read \"dsr.nmip\", check that it is low.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "NMI", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Cause an NMI to occur, read \"dcsr.nmip\", check that it is high as expected. Have no NMI pending, read \"dsr.nmip\", check that it is low.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40X/S user manual\n\nDebug 1.0.0\n\nPrivspec 1.12", + "Requirement Location": "Control and Status Registers\n\nDebug Control and Status\n\nMachine Status Registers", + "Feature": "MPRV", + "Sub Feature": "", + "Feature Description": "\"dcsr.mprven\" is WARL 1.\nSince \"mprven\" is 1, then \"mstatus.MPRV\" always takes effect in D-mode.", + "Verification Goal": "Read \"dcsr.mprven\", check that it is always 1.\n\n40S, be in debug mode, have \"mstatus.MPRV\" disabled, check that all instructions are treated as M-mode. Be in debug mode, have \"mstatus.MPRV\" enabled, have \"mstatus.MPP\" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "MPRV", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Read \"dcsr.mprven\", check that it is always 1.\n\n40S, be in debug mode, have \"mstatus.MPRV\" disabled, check that all instructions are treated as M-mode. Be in debug mode, have \"mstatus.MPRV\" enabled, have \"mstatus.MPP\" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Silabs Internal", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "Haltreq and stepping", + "Feature Description": "External debug requests and single stepping can only cause debug entry on \"instruction boundaries\", so a multi-step instruction cannot be interrupted by this.", + "Verification Goal": "While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "Synchronous entry", + "Feature Description": "Trigger matching can cause synchronous debug entry, and can interrupt \"within\" and instruction.", + "Verification Goal": "Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted \"midway\" and that debug mode is entered correctly.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted \"midway\" and that debug mode is entered correctly.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2\nCV32E40P doc rev 46711ac", + "Requirement Location": "4.8.1 DCSR\n\nControl and Status Registers", + "Feature": "Single step", + "Sub Feature": "Interrupts", + "Feature Description": "While single stepping, interrupts (maskable and non-maskable) may be enabled or disabled using the dcsr.stepie bit. ", + "Verification Goal": "Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (mmode_step_stepie)\nA: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure NMI is asserted while performing a step. Ensure that the NMI is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure NMI is asserted while performing a step. Ensure that the NMI is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.\n", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvmt_cv32_tb.u_debug_assert.cov_step_stepie_nmi\nA: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "Simultaneous Interrupt", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq\n\n\"NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\"\n\n\n", + "Review (Marton)": "What feature is this? Several points in this region lack context, or a merging of left hand cells", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "Simultaneous NMI", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "RISCV compliance", + "Sub Feature": "", + "Feature Description": "All RISCV code should run in debug mode as well as M mode", + "Verification Goal": "[PZ] Run RISCV compliance tests all in debug mode", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Waived", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Corner Cases", + "Feature Description": "", + "Verification Goal": "[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq\n (.irq_dreq_trig_ill/cebreak/ebreak/branch/multicycle)\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] Add coverage to ensure debug_req asserted on every FSM state", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] Have trigger address match an instruction that has an illegal instruction (both in normal and single step mode). Ensure debug is enterred with cause set to trigger and PC is set to exception handler prior to debug entry", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "Not possible with timing=0, core will not execute instruction at match address before entering debug mode.", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "If a debug_req_i is asserted when an illegal instructions is being executed, the address of the trap handler must be stored to dpc instead of the address of the illegal instruction", + "Verification Goal": "Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC debug_test_known_miscompares", + "Review (Marton)": "Lacks verification goal", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_illegal_insn_debug_req", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "Several causes exist for entering debug, the priority is specified in a table in the \"dcsr\" section of the debug spec.\n\nNote: This changed going to v1.0.0", + "Verification Goal": "Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Partly covered in DTC \"debug_test\" and \"debug_test_trigger\", the rest will be covered by corev_rand_debug_ebreak and corev_rand_debug_single_step", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.debug_causes\n (.trig_vs_ebreak, trig_vs_cebreak, trig_vs_dbg_req, trig_vs_step\n ebreak_vs_req, cebreak_vs_req, ebreak_vs_step, cebreak_vs_step, dbg_req_vs_step)", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "3-way Corners", + "Feature Description": "* Haltreq, then single-step ebreak\n* Single-step ebreak, then haltreq\n* Single-step ebreak with trigger\n* Single-step ebreak, then trigger on next instr\n* Haltreq, then ebreak with trigger\n* Haltreq, then ebreak, then trigger on next instr\n* Haltreq during ebreak with trigger\n* Haltreq during ebreak, then tirgger on next instr\n(More 3-way corners could be possible, see \"Generated Corners\" below.)", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "4-way Corners", + "Feature Description": "* Haltreq, then single-step ebreak with trigger\n* Haltreq, then single-step ebreak, then trigger on next instr\n* Single-step ebreak with trigger, then haltreq\n* Single-step ebreak, then haltreq and trigger on next instr\n(More 4-way corners could be possible, see \"Generated Corners\" below.)", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Generated Corners", + "Feature Description": "There are many corners", + "Verification Goal": "Write a covergroup with all events that can cause debug entry {haltreq, step, etc\u2026} and include timing aspects of first/then (\"e.g. haltreq right after step\", etc\u2026). Then, create a cross of all of these, as that should in principle generate all possible corners if written comprehensively. Finally, review if all of these corners are covered by the assertion set.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Dret", + "Feature Description": "https://github.com/openhwgroup/core-v-verif/issues/1476", + "Verification Goal": "Execute \"dret\" in M-mode, followed by a haltreq (as early as possible), so D-mode is entered before the exception handler. Ensure the rest of debug modelling has predictions on all csr and rvfi signals needed for checking this outcome.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "External debug request", + "Sub Feature": "Startup / clock gating", + "Feature Description": "When the reset signal is deasserted, but before the fetch_enable_i signal is active, the internal clock of the core is gated. The cv32e40p would not miss this request, but on the 40s haltreq is no longer sticky and so it should not cause debug entry.", + "Verification Goal": "Assert short (1 cycle) debug_req_i randomly after reset, before the core starts executing. Observe that the core does not enter debug mode but instead starts executing instructions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC debug_test_boot_set", + "Review (Marton)": "Deprecated as debug_req is now non-sticky", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V Debug Support Version 1.0.0-STABLE 86e748abed738f8878707dc31fe2713f41868f2c", + "Requirement Location": "A.2 Execution Based", + "Feature": "Program Buffer", + "Sub Feature": "PMP", + "Feature Description": "\"the PMP must not disallow fetches, loads, or stores in the address range associated with the Debug Module when the hart is in Debug Mode, regardless of how the PMP is configured\"", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "Any verdict on this now?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": 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+ "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + 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a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json new file mode 100644 index 0000000000..4b8759ad3c --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json @@ -0,0 +1,1663 @@ +[ + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mintstatus.mil resets to 0", + "Verification Goal": "CSR value check after reset\n\nDo not implement in initial-block to include formal checking", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mstatus.mie resets to 0\n", + "Verification Goal": "CSR value check after reset\n\nDo not implement in initial-block to include formal checking", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mtvec resets to {mtvec_addr_i[31:7]. 5'b0_0000, 2'b11}", + "Verification Goal": "Assert that mtvec resets to the correct initialization value", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Reset behavior", + "Sub Feature": "Interrupts never enabled out of reset", + "Feature Description": "mstatus.mie resets to 0", + "Verification Goal": "Assert that interrupts are disabled and never taken immediately after deasserting reset", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Privilege Modes", + "Feature Description": "CLIC interrupts only support machine mode", + "Verification Goal": "Assert that clic_irq_priv_i[1:0] is always 2'b11\nAssume on input for formal", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "NMI", + "Feature Description": "NMI address is located at the 15th entry in the machine trap vector table, located at mtvec. In other words, nmi_addr = { mtvec[31:7], 5'b0_1111, 2'b00 }", + "Verification Goal": "Assert that nmi addr = { mtvec[31:7], 5'b0_1111, 2'b00 }", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Interrupts", + "Feature Description": "Support up to a maximum of 1024 CLIC interrupts", + "Verification Goal": "Assert that SMCLIC_ID_WIDTH is inside { 1 .. 10 }", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Interrupts", + "Feature Description": "Interrupt levels inside { 0, 2 .. 255 }", + "Verification Goal": "Correct functionality of interrupts of all valid levels", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Input ports", + "Feature Description": "irq_i[31:0] tied to zero", + "Verification Goal": "Assert that non-clic irq[31:0] signals are tied to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Eventually taken", + "Sub Feature": "Interrupt taken", + "Feature Description": "An interrupt that is both pending and enabled shall be taken, unless if the core is in debug mode or is blocked by external interfaces (rvalid, fence_flush_ack, etc), and the taking happens within a fixed number of cycles", + "Verification Goal": "Check that when conditions are right, then the interrupt gets taken within expected time", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt interface", + "Sub Feature": "Level sensitive", + "Feature Description": "All interrupt lines are level-sensitive", + "Verification Goal": "All assertions and modeling of interrupts for checking assume no edges required to qualify an interrupt", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "Interrupt ack pulse", + "Feature Description": "Interrupt acknowledge is always a pulse", + "Verification Goal": "Assert that irq_ack is always a pulse", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "Interrupt ack valid", + "Feature Description": "Interrupt acknowledge is only asserted when a valid interrupt has been taken by the core", + "Verification Goal": "irq_ack never asserted unless core has taken an interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "NMI", + "Feature Description": "NMI not reported on irq_ack", + "Verification Goal": "Check that after an NMI is triggered, if there is no other interrupt occuring, then there should be no irq_ack", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Interrupt ID is valid", + "Feature Description": "Interrupt valid ID matches the active interrupt during the cycle where interrupt acknowledge is asserted", + "Verification Goal": "Ensure that irq_id is the active interrupt when irq_ack is asserted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Interrupt ID is never reserved", + "Feature Description": "Interrupt valid ID during interrupt acknowledge is never a reserved interrupt [15,14,13,12,10,9,8,6,5,4,2,1,0]", + "Verification Goal": "Assert irq_id is not a reserved valid when irq_ack is asserted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Single interrupt ack per ISR", + "Feature Description": "Interrupt acknowledge only asserted once per interrupt", + "Verification Goal": "irq_ack only asserts once for an interrupt service period", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs internal", + "Feature": "Interrupt interface", + "Sub Feature": "RVFI", + "Feature Description": "Every irq_ack must be followed by a corresponding rvfi_intr", + "Verification Goal": "Check that whenever and irq_ack occurs, then the next rvfi retired instruction must have rvfi interrupt set correctly", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt CSR", + "Sub Feature": "mclicbase", + "Feature Description": "12 least significant bits hardwired to zero", + "Verification Goal": "Assert mclicbase[11:0] = 0 \n\nNote: This register will possibly be removed in the future", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mstatus.mpp", + "Feature Description": "mstatus.mpp accessible through mcause.mpp", + "Verification Goal": "Read/Write mpp to mcause.mpp and read back through mstatus.mpp", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause.mpp", + "Feature Description": "mcause.mpp accessible through mstatus.mpp", + "Verification Goal": "Read/Write mpp to mstatus.mpp and read back through mcause.mpp", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mstatus.mpie", + "Feature Description": "mstatus.mpie accessible through mcause.mpie", + "Verification Goal": "Read/Write mpp to mcause.mpie and read back through mstatus.mpie", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause.mpie", + "Feature Description": "mcause.mpie accessible through mstatus.mpie", + "Verification Goal": "Read/Write mpp to mstatus.mpie and read back through mcause.mpie", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mie", + "Feature Description": "mie not used and hardwired to zero", + "Verification Goal": "Assert that mie always appears as hardwired 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mie", + "Feature Description": "Writes to mie should not trap", + "Verification Goal": "Attempt writes to mie and ensure that 0 is read back", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mip", + "Feature Description": "mip not used and hardwired to zero", + "Verification Goal": "Assert that mip always appears as hardwired 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mip", + "Feature Description": "Writes should not trap", + "Verification Goal": "Attempt writes to mip and ensure that 0 is read back", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvec", + "Feature Description": "Always aligned to 128 bytes", + "Verification Goal": "Assert that mtvec[6:2] always zero", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvec", + "Feature Description": "Always in CLIC mode (I.e. model can not switch between interrupt modes)", + "Verification Goal": "Assert that mtvec.mode is always 2'b11 when CLIC is enabled", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Memory writes to the vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.", + "Verification Goal": "Verify that a fence.i instruction after writes to the vector table guarantees that the new vector table pointer taken matches the latest pointer written to the vector table.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Function ptr reads treated as instruction fetch, adhering to configured PMA settings \n(CV32E40S): PMP settings apply as for any other instruction fetch", + "Verification Goal": "Assert that interrupts accessing the vector table pointers do so through the instruction interface, and that a lack of PMP execute and PMA main-memory settings causes the instruction fetch to fail.\n\nNote, instruction fetch is treated as an implicit read, thus do not require PMP read permissions, but execute permission is required.\n\nBoth the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Always aligned to 2^(max(6, 2+SMCLIC_ID_WIDTH)", + "Verification Goal": "Assert that mtvt [max(6, 2+SMCLIC_ID_WIDTH)-1:0] = 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Determine alignment by software access,\nWrite ones to lower order bits and read back", + "Verification Goal": "Test that correct alignment can be inferred by writing to these fields and read back.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mepc", + "Feature Description": "The CSR\u00a0mepc\u00a0is set to the PC of the interrupted application code or preempted interrupt handler", + "Verification Goal": "Ensure that MEPC in ISR is value of saved PC.\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.interrupt flag always set during ISR regardless of the active interrupt", + "Verification Goal": "mcause[31] is set when an interrupt is taken", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.exccode is set to the active interrupt code", + "Verification Goal": "mcause.exccode reflects the taken interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpil: Previous interrupt level", + "Verification Goal": "mpil reflects the previous privilege level", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpp: Previous privilege mode", + "Verification Goal": "Ensure that mcause.mpp reflects mstatus.mpp previous privilege mode after taking a trap", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpie: Previous interrupt enable", + "Verification Goal": "Ensure that mcause.mpie reflects mstatus.mpie previous interrupt enable value after taking a trap", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 1:\n\"The II is still the ranking interrupt (no change). In this case, as the level of the II will still be higher than pil from the OIC, xil and exccode will be rewritten with the same value that they already had (effectively unchanged), and xnxti will return the table entry for the II.\"\n\n(II: Initital interrupt,\nOIC: Original interrupted context)", + "Verification Goal": "Assert that mnxti returns the table entry for the initial interrupt when the current interrupt is still being signalled to the core as the highest enabled and pending interrupt.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 2:\n\"The II has been superceded by a higher-level non-SHV interrupt. In this case, xil will be set to the new higher interrupt level, exccode will be updated to the new interrupt id, and xnxti will return the vector table entry for the new higher-level interrupt. The OIC is not disturbed, retaining the original epc and the original pil. This case reduces latency to service a more-important interrupt that arrives after the state-save sequence was begun for the less-important II. The II, if still pending-enabled, will be serviced sometime after the higher-level interrupt as described below.\"", + "Verification Goal": "Assert that mnxti returns the table entry for the new higher-level interrupt when the current interrupt is being interrupted by a higher level, non-shv interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 3: \n\"The II has been superceded by a higher-priority non-SHV interrupt at the same level. This operates similarly to the previous case, with exccode updated to the new interrupt id. Because the lower-priority interrupt had not begun to run its service routine, this optimization preserves the property that interrupt handlers at the same interrupt level but different priorities execute atomically with respect to each other (i.e., they do not preempt each other).\"", + "Verification Goal": "Only machine mode interrupts are supported, an interrupt of the same level but higher priority cannot occur\n", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 4:\n\"The II has disappeared and a lower-ranked non-SHV interrupt, which has interrupt level greater than the OIC\u2019s pil is present in CLIC. In this case, the xil of the handler will be reduced to the lower-ranked interrupt\u2019s level, exccode will be updated with the new interrupt id, and xnxti will return a pointer to the appropriate handler in table. In this case, the new lower-ranked interrupt would still have caused the original context to have been interrupted to run the handler, and the disappearing II has simply caused the lower-ranked interrupt\u2019s entry and state-save sequence to begin earlier.\"", + "Verification Goal": "Assert that mnxti returns the table entry for the new lower-level interrupt when the current interrupt is no longer present in the CLIC, and replaced by a new lower-leveled interrupt, with a greater interrupt level than the original interrupted context's pil", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 5:\n\"The II has disappeared and either there is no current interrupt from the CLIC, or the current ranking interrupt is a non-SHV interrupt with level lower than xpil. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. The following trampoline code will then not fetch a vector from the table, and instead just restore the OIC context and mret back to it. This preserves the property that the OIC completes execution before servicing any new interrupt with a lower or equal interrupt level.\"", + "Verification Goal": "Ensure that mnxti returns 0 in case the initial interrupt is no longer signalled, nor replaced by a new interrupt from the CLIC", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 6:\n\"The II has been superceded by a higher-level SHV interrupt. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. Once interrupts are reenabled for the following instruction, the hart will preempt the current handler and execute the vectored interrupt at a higher interrupt level using the function pointer stored in the vector table.\"", + "Verification Goal": "Assert that mnxti will return 0 in case of a higher-leveled SHV interrupt pending", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.9.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mintstatus", + "Feature Description": "R/O CSR, Holds active interrupt level for each supported privilege mode", + "Verification Goal": "Assert that the mil field gets updated with the current interrupt level when an interrupt is taken, and that sil and uil-fields are hard-coded zero.\n\nNote: NMIs explicitly leave \"mintstatus\" unchanged.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "CSR", + "Sub Feature": "CSR access", + "Feature Description": "CSR registers should be accessible as defined in UM", + "Verification Goal": "Add new CLIC-specific registers to CSR access tests and ensure that the registers and their fields can be read/written according to specification\n\nmtvt\nmnxti\nmintstatus\nmintthresh\nmscratchcsw\nmscratchcswl\n\nNote: \"mclicbase\" was removed.\nNote: \"mintstatus\" got moved.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "Hardware vectoring", + "Feature Description": "mcause.minhv: Set at start of hw vectoring", + "Verification Goal": "Assert that mcause.minhv is set when a hw-vectored interrupt is taken", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "Hardware vectoring", + "Feature Description": "mcause.minhv: Cleared at end of hw vectoring", + "Verification Goal": "Assert that mcause.minhv is cleared when pointer fetch of hw-vectored interrupt is taken successfully", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Exception on fetch:\nmepc : set to faulting address (pointer, rather than address for an instruction)\nmcause: exception type", + "Verification Goal": "Write invalid (not pointing to a valid instruction or a region with pmp restricted execute access) pointer to the mtvt table, and trigger this handler. \n", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Prefetcher: no prefetches between pointer fetch and fetch of final vectored target", + "Verification Goal": "Assert that no new instructions get fetched that does not match the final vectored target after a pointer fetch is attempted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Interrupt executes trap handler function pointer located at the address specified in mtvt when shv = 1", + "Verification Goal": "Assert that first pc after a taken, shv interrupt always matches address fetched from mtvt\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Interrupt jumps to common code at mtvec when shv = 0", + "Verification Goal": "Assert that first pc after a taken non-shv interrupt matches ", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt Vector", + "Sub Feature": "PC", + "Feature Description": "non-shv: taken trap handler always has address[6:0] = 0;\nimplied by mtvec alignment restriction", + "Verification Goal": "Assert that first pc after a taken, non-shv interrupt always has bits [6:0] = 0\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupts ignored", + "Feature Description": "Interrupts ignored when \nnew privilege mode (nP) lower than current privilege mode (P)", + "Verification Goal": "Not allowed, assuming clic_irq_priv_i always = 2'b11\nCovered by assertion that asserts that clic_irq_priv_i is always 2'b11 in sim and assumed in formal", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupts ignored", + "Feature Description": "Interrupts ignored when \nnew privilege mode (nP) = current privilege mode(P) and new interrupt level (nL) != 0 and nL < current interrupt level (L)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode\nInside interrupt handler (Nested)\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_irq_lvl > 0 and < current level\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interupts disabled", + "Feature Description": "Interrupts disabled when\nmtatus.mie and clicintie[i] = 0", + "Verification Goal": "mstatus.mie = 0 should disallow any pending and enabled interrupts from being taken as we only have one level where interrupts can be taken (M-mode), so no other higher modes exist\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "No interrupt", + "Feature Description": "No interrupt when \nnew privilege mode (nP) = current privilege mode (P) \nclic.level = 0\n\nP, nP in M, U", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode (Cannot signal U-mode)\nTest in both nested and non-nested cases\n\nclic_irq_i = 1 \nclic_irq_id_i = random 0 .. max index\nclic_irq_lvl = 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "No interrupt", + "Feature Description": "No interrupt when \nnew privilege mode (nP) > current privilege mode (P)\nclic.level = 0\n\nnP = M, P = U, clic.level = 0\n(CV32E40S)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: U-mode\nTest for both nested and non-nested cases\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_irq_lvl = 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Horizontal interrupt taken\n(Nested)", + "Feature Description": "Horizontal interrupt taken when\nmtatus.mie and clicintie[i] = 1\nnew privilege mode (nP) = current privilege mode (P)\nnew privilege level (nL) > current privilege level (L)\n\nOnly applicable for M-mode (P, nP = M) as horizontal user mode traps are not supported (N-extension) in neither CV32E40X nor S", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode (Cannot signal U-mode)\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_lvl > current_lvl\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that an interrupt that should be taken under the given circumstances always get taken\nCheck that system behaves correctly when a pending and enabled interrupt gets taken", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Vertical interrupt taken", + "Feature Description": "Vertical interrupt taken when\nnew privilege mode (nP) > current privilege mode (P)\nnew privilege level (nL) > 0\n\nnP = M, P = U\n\n(CV32E40S)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: U-mode\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_lvl > 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that an interrupt that should be taken under the given circumstances always gets taken\nCheck that the system behaves correctly when a pending and enabled interrupt gets taken", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupt taken", + "Feature Description": "mstatus.mie = 1\nnP = P = M\nnL > L\n\nor\n\nnP > P (i.e. nP = M, P = U)\nnL > 0", + "Verification Goal": "Assert that an interrupt is taken if and only if any of the two conditions are true", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt preemption", + "Sub Feature": "mintthresh", + "Feature Description": "Higher level interrupts than mintthresh.th can preempt execution", + "Verification Goal": "Assert that interrupts with the same privilege mode and higher privilege level than the running ISR can interrupt the currently running ISR", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt preemption", + "Sub Feature": "mintthresh", + "Feature Description": "Lower level interrupts than mintthresh.th cannot preempt execution", + "Verification Goal": "Assert that interrupts with the same privilege mode and lower privilege level than the running ISR cannot interrupt the currently running ISR", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "when \nnP > P\ninterrupt is highest among pending-and-enabled interrupts\ni.level != 0\n\nnP = M, P = U\n\n(CV32E40S)", + "Verification Goal": "clic_irq_i = 1\nclic_irq_lvl > 0\nP = U\nnP = M", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "when\nnP = P\ninterrupt is highest among pending-and-enabled interrupts\ni.level > max(xintstatus.xil, xintthresh.th)\n\n(xintthresh only applies to current privilege mode)\nnP, P = M", + "Verification Goal": "clic_irq_i = 1\nclic_irq_lvl > max(mintstatus.mil, mintthresh.th)\nP, nP = M\n\nTest that only interrupts with a sufficiently high interrupt level are able to preempt execution with both true or temporarily risen interrupt level", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "nP < P\ninterrupt is highest among pending-and-enabled interrupts\ni.level != 0\n\nCan not occur 40S/40X as new privilege mode signalled on the CLIC interface can never be less than current privilege mode", + "Verification Goal": "nP < P cannot occur as we assume clic_irq_lvl = 2'b11\n\nNo test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Ignores", + "Feature Description": "Everything not covered above", + "Verification Goal": "Core does not resume operation unless any of the above resume conditions are true", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt instruction", + "Sub Feature": "Killed instructions have no side-effects", + "Feature Description": "When an instruction is interrupted, it is killed, meaning that it has no side-effects: 1) load/store instructions don't reach the bus, 2) control transfer instructions don't jump, 3) CSRs don't get updated, 4) GPRs don't get updated", + "Verification Goal": "Check that bus, jumps, and registers are unaffected by killed instructions", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "Execution continues at \nPrivilege mode = mcause.mpp\npc = mepc\ninterrupt level = mcause.mpil\nglobal interrupt enable mie = mcause.mpie\n\nmcause.mpil unchanged\nmcause.mpp = least privileged mode\nmcause.mpie = 1", + "Verification Goal": "Correct update of CSR values when core returns from an ISR", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "Execution continues at \nP = mcause.mpp\npc = mepc\nL = mcause.mpil\nie = mcause.mpie\n\nmcause.mpil unchanged\nmcause.mpp = least privileged mode\nmcause.mpie = 1", + "Verification Goal": "Correct update of CSR values when core returns from an ISR\nAdded assertion for formal coverage", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 0.9-draft 4/11/2023", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "\"If the hart is currently running at some privilege mode x, an MRET or SRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.\"", + "Verification Goal": "Use \"mret\" to enter U-mode.\nCheck that \"mintthresh\" is written to zero upon executing the mret.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 0.9-draft 4/11/2023", + "Feature": "Return from debug mode", + "Sub Feature": "dret", + "Feature Description": "\"Likewise, if the RISC-V debug specification is implemented and the hart is currently running at some privilege mode x, a DRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.\"", + "Verification Goal": "Use \"dret\" to enter U-mode.\nCheck that \"mintthresh\" is written to zero upon executing the dret.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i\n\u2022 has a higher privilege mode than the current privilege mode and\n\u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled\ninterrupts and\n\u2022 the interrupt i level is not equal to 0.", + "Verification Goal": "Test that interrupts of higher privilege modes than the current privilege mode can wakeup the core from wfi", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i\n \u2022 has the same privilege mode as the current privilege mode and\n \u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and\n \u2022 the interrupt i level is greater than max(xintstatus.xil, xintthresh.th )", + "Verification Goal": "Test that interrupts of higher privilege level than the current privilege level can wake the core from WFI", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i \n\u2022 has a lower privilege mode than the current privilege mode and \n\u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and \n\u2022 the interrupt i level is not equal to 0.", + "Verification Goal": "nP < P cannot occur as we assume clic_irq_lvl = 2'b11\n\nNo test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "Core only wakes up if any of the conditions mentioned above is true", + "Verification Goal": "Assert that core remains in WFI mode unless correct wakeup conditions occur", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Entry", + "Feature Description": "Execution of WFI causes the core to stop", + "Verification Goal": "In normal execution the core stop within a certain time period after execution.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Clock gating", + "Feature Description": "WFI entry causes the clock to be gated", + "Verification Goal": "The core is not clocked during WFI", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Output signal", + "Feature Description": "core_sleep_o output signal is only asserted during active WFI", + "Verification Goal": "Assert the proper operation of core_sleep_o", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Synchronous exception handling", + "Sub Feature": "Horizontal synchronous exception traps", + "Feature Description": "Serviced at same privilege mode with same interrupt level as instruction that raised exception ", + "Verification Goal": "Assert that interrupt level is not changed when entering the exception handler\n(Can only occur in machine mode)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Synchronous exception handling", + "Sub Feature": "Vertical synchronous exception traps", + "Feature Description": "Serviced at higher privilege mode at interrupt level 0 in the higher privilege mode\n\n(CV32E40S)", + "Verification Goal": "Assert that user mode traps are taken in machine mode with interrupt level 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + WFI", + "Feature Description": "Proper interactions between interrupts and WFI", + "Verification Goal": "Corner case\n\nTest random combinations of streams containing WFI-instructions with random interrupt requests", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Back to back WFI", + "Feature Description": "Correct interactions between interrupts and back-to-back WFI instructions", + "Verification Goal": "Corner case\n\nIn embedded context WFI is used often, ensure that WFI can be re-entered ASAP after servicing a ISR for a previous WFI", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug", + "Feature Description": "Correct interaction between interrupts and debug", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by debug and random interrupt requests.\nGoal is to verify that interrupts are never taken in debug mode, and that interrupt- and debug transitions are handled correctly\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Exceptions", + "Feature Description": "Correct interaction between interrupts and exceptions", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by exceptions and random interrupt requests.\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Bus Error", + "Feature Description": "Correct interaction between interrupts and bus errors", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by random interrupt requests and random bus errors. Aims to verify that interrupts and bus errors are correctly prioritized by the system.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + Bus Error", + "Feature Description": "Correct interaction between interrupts, debug and bus errors\n", + "Verification Goal": "Corner case\nTest random streams of instructions, \n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI", + "Feature Description": "Correct interaction between interrupts, debug and WFI\n", + "Verification Goal": "Test random instruction streams containing WFI, where control flow changes occur due to random debug requests and random interrupts\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI + Bus Error", + "Feature Description": "Correct interaction between interrupts, debug, wfi and bus errors", + "Verification Goal": "Test random instruction streams containing WFI instructions, where control flow changes occur due to random debug requests, random bus errors, random interrupts\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI + Bus Error + Exceptions", + "Feature Description": "Correct interaction between all trap sources", + "Verification Goal": "Trap priority stress test\nTest random streams containing all trap sources to verify correct behavior\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts", + "Feature Description": "Correct interactions between nested interrupts", + "Verification Goal": "Verify potential corner case\n\nImplement nested ISR. Randomly modify mintthresh.th to mask out certain interrupts and randomly trigger new interrupts with higher or lower priority to verify that interrupts with a higher privilege level are allowed to preempt\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts + exceptions", + "Feature Description": "Correct interactions between nested interrupts and exceptions", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts, but random streams include randomly inserted exception-causing instructions\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug", + "Feature Description": "Correct interactions between nested interrupts and debug", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts, but random streams also gets control flow modified by random debug requests.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts + Debug + Bus Error", + "Feature Description": "\nCorrect interactions between nested inteerrupts, debug and bus-errors", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts with debug, but also includes random bus errors\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug + WFI", + "Feature Description": "Correct interactions between nested interrupts, debug and WFI", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts with debug, but the instruction stream should also include WFI instructions.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug + WFI + Bus Error + Exceptions", + "Feature Description": "Correct interactions between nested interrupts and all other trap types", + "Verification Goal": "Verify potential corner case\nTest nested interrupts with randomly traps (all types)\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Load instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Store instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Shift instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit logical instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit compare instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit jump instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit FENCE instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit system instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BEQ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BEQ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BNE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BNE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BLT instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BLT instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BGE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BGE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BLTU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BLTU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BGEU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BGEU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit load instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit store instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit arithmetic instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit shift instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit jump instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit system instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken C.BEQZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken C.BEQZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken C.BNEZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken C.BNEZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 M instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zba instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbb instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbc instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbs instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zicsr instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zifencei instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zc instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zca instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcb instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmb instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmt instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmp instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Illegal instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 A instructions interrupted\n(CV32E40X)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All X interface instructions interrupted\n(CV32E40X)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32F instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 P instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32V instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": " ---- END ----", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json new file mode 100644 index 0000000000..b9a5f7953c --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json @@ -0,0 +1,422 @@ +[ + { + "Requirement Location": "Riscv spec", + "Feature": "StoresVisible", + "Sub Feature": "StoresVisible", + "Feature Description": "After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.", + "Verification Goal": "Do a fencei, but right before the fencei do a store to the instruction following the fencei, then see that the newly stored value is executed instead of the old instruction (e.g. change addi to use a different immediate)", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/\n\nCOV: ???", + "Comment": "TODO must be added to regression lists" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Do a fencei followed by any instruction, but let the environment detect when the fencei is being executed and change the memory holding the next instruction, then see that the old instruction is not executed", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert. (Note was ignored because of the difficulty of writing this as an assert for fv.)" + }, + { + "Requirement Location": "User manual", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqHigh", + "Feature Description": "When executing a fence.i instruction, fencei_flush_req_o shall rise sometime before executing the next instruction", + "Verification Goal": "Check that when executing a fence.i instruction there will be a rising req before has retired", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_rise_before_retire", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitLsu", + "Feature Description": "When executing a fence.i instruction, if there is an ongoing store instruction (not limited to rv32i) that has not completed (data_rvalid_i clocked in as 1), then fencei_flush_req_o shall be low", + "Verification Goal": "Make sure a store instruction is run right before a fence.i, and (possibly using obi stalls) ensure that the fence.i is pending retirement but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o was low until this point where it now goes high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_bus\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitWritebuffer", + "Feature Description": "When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1", + "Verification Goal": "Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_buffer\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitXinterface", + "Feature Description": "When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done", + "Verification Goal": "Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "(Not relevant for the 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitObi", + "Feature Description": "fencei_flush_req_o shall not go high while there are outstanding stores on the obi bus", + "Verification Goal": "Check vs the OBI monitors that there are no outstanding stores at the time fencei_flush_req_o goes high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_outstanding\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_c_req_wait_outstanding_1.cov_req_wait_outstanding_1", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqLow", + "Feature Description": "When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o and fencei_flush_ack_i has been sampled high simultaneously, and then then it shall go low", + "Verification Goal": "Check that when fencei_flush_req_o is high, then it behaves correctly with regards to fencei_flush_ack_i", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_stay_high\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_drop_lo", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "AckChange", + "Feature Description": "fencei_flush_ack_i is allowed to change freely on any clock cycle: It can be permanently high, go high without fence.i and retract, go high at the same cycle as the req, it can delay arbitrarily after req and then go high, etc", + "Verification Goal": "Drive ack to test all permutations of rising/falling before/after/on req, acking without req, retracting an early ack, delaying ack after req, etc.", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reqack_cg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "AckWithold", + "Feature Description": "If req is high, but ack never comes, then the core keeps on stalling and the fence.i is blocked from completing", + "Verification Goal": "Upon a req, try witholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]})", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_stall_until_ack\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_ack_delayed[*].cov_ack_delayed", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "BranchInitiated", + "Feature Description": "After req and ack has been sampled simultaneously high and when req is low again, then the core takes a branch to the instruction after the fence.i instruction", + "Verification Goal": "Check that the branch is taken at the point after req and ack has been simultaneously high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_branch_after_retire\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_branch_after_retire", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ShadowingBranch", + "Feature Description": "If the fence.i ends up not retiring because it was preceeded by a taken branch or a jump, then the fencei_flush_req_o shall not go high", + "Verification Goal": "Take a branch or do a jump to skip a fence.i, and ensure that fencei_flush_req_o doesn't go high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_must_retire\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_retire_without_req\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_no_retire", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "Fetching", + "Sub Feature": "Fetching", + "Feature Description": "Instruction data for the next PC must be fetched after the fence.i instruction has executed (because only then can data-side stores have completed and caches have been updated)", + "Verification Goal": "Check that after a fence.i instruction retires then instr-side obi fetches the next instruction to be executed", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_fetch_after_retire", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "MultiCycle", + "Sub Feature": "MultiCycle", + "Feature Description": "Given zero stalls on neither instr-side and data-side obi nor on fencei_flush_ack_i, then the execution of fence.i takes a fixed number of cycles.", + "Verification Goal": "Check that, given ideal conditions, the cycle count of fence.i is as expected", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_cycle_count_minimum", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "StoresComplete", + "Sub Feature": "StoresComplete", + "Feature Description": "Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted)", + "Verification Goal": "Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "StoresComplete", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "Flush", + "Sub Feature": "Flush", + "Feature Description": "When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed", + "Verification Goal": "Check that a fence.i will cause flushing of the pipeline, prefetcher, write buffer, and data_req_o", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_supress_datareq\n\nA: ???", + "Comment": "TODO missing assert. (Have not checked/covered that the pipeline/writebuffer content is actually purged. Or that any memory change WILL be the next instr word.)" + }, + { + "Requirement Location": "Riscv spec", + "Feature": "UnusedFields", + "Sub Feature": "UnusedFields", + "Feature Description": "imm[11:0], rs1, rd are reserved for future extensions, and implementations shall ignore them", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reserved_cg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json new file mode 100644 index 0000000000..9d66eba2aa --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json @@ -0,0 +1,866 @@ +[ + { + "Requirement Location": "UM 0e447ac", + "Feature": "Regions", + "Sub Feature": "Valid number of regions", + "Feature Description": "There shall be between 0 and 16 PMA regions configured.", + "Verification Goal": "Assert that highest numbered PMA region < 16 (assuming 0-indexed)\n\nCover: Having 0 regions, having maximum num regions, and having something in between.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_valid_num_regions\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_valid_num_regions\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_index\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_index\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_cov_instr_i.cg_inst.cp_numregions", + "Comment": "TODO tests must be added to regression lists.\n\nTODO directed tests has parts to uncomment if RTL is ready.\n\nTODO everything \"atomics\" must be changed to \"integrity\" for 40s." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "Configuration to be tested", + "Feature Description": "0 Regions - Deconfigured", + "Verification Goal": "Test configuration 1, aims to verify the following:\n1. Default parameters for entire memory range", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "No cover, but fascilitates other covers below.\n\nTODO these regions are out of date vs testbench.\n\nTODO must be used in formal regressions too." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "1 Region: \nR[0]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111)\n\nMBCA = M(ain memory)\n B(ufferable)\n C(acheable)\n A(tomic operations allowed)\n\n", + "Verification Goal": "Test configuration 2, aims to verify the following:\n1. System configured with 1 PMA region only\n2. Full address range of maximum size\n3. Upper/Lower bounds for first region set to min/max values", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "1 Region: \nR[0]: 0x0000_0000-0x7FFF_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 3, aims to verify the following:\n1. Correct functionality for 1 defined region\n2. Correct behavior for undefined regions when a region is defined", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "7 Regions:\nR[0]: 0x0000_0000-0x1FFF_FFFF (MBCA = 1111)\nR[1]: 0x2000_0000-0x3FFF_FFFF (MBCA = 1101)\nR[2]: 0x4000_0000-0x5FFF_FFFF (MBCA = 0101)\nR[3]: 0x6000_0000-0x9FFF_FFFF (MBCA = 1001)\nR[4]: 0xA000_0000-0xDFFF_FFFF (MBCA = 0101)\nR[5]: 0xE000_0000-0xE00F_FFFF (MBCA = 0000)\nR[6]: 0xE010_0000-0xFFFF_FFFF (MBCA = 0101)", + "Verification Goal": "Test configuration 4, aims to verify the following:\n1. A standard memory map (Based on ARM Cortex)\n2. A fully defined, contiguous memory map with no undefined regions\n3. Multiple, non-overlapping regions", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nR[0]: 0x4800_0000-0x49FF_FFFF (MBCA = 1011)\nR[1]: 0x4400_0000-0x4BFF_FFFF (MBCA = 0001)\nR[2]: 0x3ACE_0000-0x4ABC_FFFF (MBCA = 0100)\nR[3]: 0x3600_A000-0x4F99_FFFF (MBCA = 1111)\nR[4]: 0x3420_C854-0x5000_ABFF (MBCA = 1101)\nR[5]: 0x3100_FCAB-0x5000_BCCA (MBCA = 1001)\nR[6]: 0x3000_1353-0x5140_FFFF (MBCA = 0000)\nR[7]: 0x2C5A_3200-0x52FF_FFFF (MBCA = 0101)\nR[8]: 0x2A00_0000-0x56FF_FFFF (MBCA = 1111)\nR[9]: 0x2340_000A-0x600F_FFFF (MBCA = 0001)\nR[10]: 0x2000_0000-0x63FF_FFFF (MBCA = 0101)\nR[11]: 0x13AC_AA55-0x7FFF_FFFF (MBCA = 1011)\nR[12]: 0x1000_000F1-0x82FF_FFFF (MBCA = 1101)\nR[13]: 0x0500_0000-0x8459_FFFF (MBCA = 0100)\nR[14]: 0x0200_0000-0xEFFF_FFFF (MBCA = 0000)\nR[15]: 0x0000_A000-0xFFFE_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 5, aims to verify the following:\n1. Region match priority\n2. Maximum number of separate areas in memory (33)\n\nAddress may be modified to better suit implementation and verification enviornment, but the following criteria must be met:\n1. Each defined region must be enclosed by the adjacent region of lower priority\n2. No region boundaries must overlap\n3. There shall be undefined space prior to and aft of largest, highest numbered region\n", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nR[0]: 0x0001_0000-0x001F_FFFF (MBCA = 1001)\nR[1]: 0x0030_0000-0x04FF_FFFF (MBCA = 1111)\nR[2]: 0x1000_0000-0x1001_0000 (MBCA = 0100)\nR[3]: 0x1800_1234-0x18FF_AB21 (MBCA = 0000)\nR[4]: 0x2020_0010-0x2FFF_0000 (MBCA = 0001)\nR[5]: 0x3100_A000-0x32FF_FFFF (MBCA = 1111)\nR[6]: 0x3440_0000-0x3800_FFFF (MBCA = 0100)\nR[7]: 0x4AAA_F000-0x4C00_FFFF (MBCA = 1101)\nR[8]: 0x4D00_5555-0x4FFF_ABCD (MBCA = 1011)\nR[9]: 0x5100_0000-0x52FF_FFFF (MBCA = 0000)\nR[10]: 0x5400_0000-0x5FFF_FFFF (MBCA = 1111)\nR[11]: 0x6300_0000-0x6700_FFFF (MBCA = 0101)\nR[12]: 0xA000_0000-0xAFFF_FFFF (MBCA = 1001)\nR[13]: 0xBC00_0000-0xBCFF_FFFF (MBCA = 1101)\nR[14]: 0xC000_0000-0xDFFF_FFFF (MBCA = 0001)\nR[15]: 0xE700_EF00-0xE9FF_FFFF (MBCA = 0101)", + "Verification Goal": "Test configuration 6, aims to verify designs with the following characteristic:\n1. Non-contiguously defined maximum number of memory regions\n2. Maximum number of separate areas In memory (33)\n3. No overlap, single matching regions\n4. Non-defined areas prior and aft of each defined region\n\nAddress map may be modified to better suit actual implemetations, but the above criteria must be adhered to.", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nNote: Zero length regions are intentional\nR[0]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[1]: 0x5555_5555-0x5555_5555 (MBCA = 0000)\nR[2]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[3]: 0xAAAA_AAAA-0xAAAA_AAAA (MBCA = 0000)\nR[4]: 0xCCCC_CCCC-0xCCCC_CCCC (MBCA = 0000)\nR[5]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[6]: 0xE38E_E38E-0xE38E_E38E (MBCA = 0000)\nR[7]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[8]: 0xFFFF_FFFF-0xFFFF_FFFF (MBCA = 0000)\nR[9]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[10]: 0x9249_2492-0x9249_2492 (MBCA = 0000)\nR[11]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[12]: 0xDB6D_B6DB-0xDB6D_B6DB (MBCA = 0000)\nR[13]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[14]: 0x1249_2492-0x1249_2492 (MBCA = 0000)\nOnly one non-zero region:\nR[15]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 7, aims to verify the following:\n1. Zero length regions does not match any accesses\n2. Upper/Lower bound of outlier (last) region set to min/max of address range\n\nAddress map may be modified to better suit actual implementations, but R[15] must be defined to min/max possible address range. Remaining regions shall have 0 length.\n", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "Coverpoints", + "Feature Description": "Instruction fetch coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing instruction fetch", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "Note: These could also have used RVFI instead.\n\nNote: Not very feasible to match on every single cfg index, because some are overshadowed by overlapping regions and to model this is expensive." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Load instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing load instruction", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Store instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing store instruction", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Atomic instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic operation", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Load alignment error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with load alignment error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Store alignment error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with store alignment error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Atomic load-reserved unallowed error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic load-reserved unallowed error", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Atomic store-conditional unallowed error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic store-conditional unallowed error", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "Risc-V Priv. spec", + "Feature": "PMA Readability", + "Sub Feature": "PMA readable by SW", + "Feature Description": "Design must support SW readback of attributes", + "Verification Goal": "N/A. Can be SW-readable via a C-header, or is otherwise the responsibility of integration- or system-level testing.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Code Execution", + "Sub Feature": "Code Execution only from main memory", + "Feature Description": "Code execution is not allowed from IO region, any attempts to do so should result in an instruction access fault (exception code 1)", + "Verification Goal": "Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nE.g. execute a JMP instruction to an area defined as IO (and/or unconfigured PMA region) and verify that an instruction access fault is triggered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Code Execution", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nE.g. execute a JMP instruction to an area defined as IO (and/or unconfigured PMA region) and verify that an instruction access fault is triggered", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg.cross_pma", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Code Execution", + "Sub Feature": "Instruction fetch violation coverpoints", + "Feature Description": "Instruction group type for failing instruction fetch violations", + "Verification Goal": "Instruction group type cover from ISACOV for each violated PMA instruction fetch", + "Pass/Fail Criteria": "Other", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: TODO", + "Comment": "TODO missing cover. (Problem: Depends on ISACOV updates.)" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Access match", + "Sub Feature": "Non-Overlapping PMA Regions", + "Feature Description": "A match should always be inside its matching region, \nLower_bound[region] <= addr[addr_max:2] < Upper_bound[region]", + "Verification Goal": "Assert that match[region] always implies that the following holds: \nlower[region] & 2'b00 <= addr[31:0] < upper[region] 2'b00", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_bounds\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_bounds", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses: Verify that accesses are matched to their respective memory regions", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "ENV capability, not specific test", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses: Verify that accesses are matched to their respective memory regions", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch*\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_matchregion*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "Overlapping PMA Regions", + "Feature Description": "Any access matching multiple regions should attain the attributes of the lowest numbered matching region", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "Non-Matching Accesses", + "Feature Description": "PMA_NUM_REGIONS==0: \nAccesses not matching attribute regions should be treated as: \nMemory\nNon-Bufferable\nNon-Cacheable\nAtomic operations not allowed", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should pass\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should pass", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_0reg/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should pass\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should pass", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", + "Comment": "TODO is the random stream run without pma regions?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "PMA_NUM_REGIONS>0\nAccesses not matching attribute regions should be treated as: \nIO\nNon-Bufferable\nNon-Cacheable\nAtomic operations not allowed", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should fail\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should fail", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should fail\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should fail", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "OBI transfer flags", + "Sub Feature": "InstructionFetches", + "Feature Description": "Bufferable flag effects - For any instruction fetch marked bufferable, the corresponding OBI transfer instr_memtype[0] signal should be set to match the bufferable flag.", + "Verification Goal": "Ensure that instr_memtype[0] is set to 1 when an instruction fetch attempt is performed with the bufferable flag set to 1. (Which is never, because \"Accesses to regions marked as bufferable (bufferable=1) will result in the OBI mem_type[0] bit being set, except if the access was an instruction fetch [...]\".)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that instr_memtype[0] is set to 0 when an instruction fetch attempt is performed with the bufferable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Cacheable flag effects - For any instruction fetch marked cacheable, the corresponding OBI transfer instr_memtype[1] signal should be set to match the cacheable flag.", + "Verification Goal": "Ensure that instr_memtype[1] is set to 1 when an instruction fetch attempt is performed with the cacheable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk5.a_pma_obi_cacheon\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that instr_memtype[1] is set to 0 when an instruction fetch attempt is performed with the cacheable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_cacheoff\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Instruction fetch attempts to PMA restricted regions should cause instr_req_o to be deasserted.", + "Verification Goal": "Ensure that PMA-violating instruction fetch attempts does not assert the instr_req_o signal by attempting execution of instructions from allowed and restricted areas of memory, checking that instr_req_o remains deasserted when restricted areas are accessed", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_req_prohibited\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "DataFetches", + "Feature Description": "Bufferable flag effects - data_memtype[0] should match the bufferable flag.", + "Verification Goal": "Ensure that data_memtype[0] is set to 1 when a data fetch attempt is performed with the bufferable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk4.a_pma_obi_bufon\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that data_memtype[0] is set to 0 when a data fetch attempt is performed with the bufferable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Cacheable flag effects - data_memtype[1] should match the cacheable flag", + "Verification Goal": "Ensure that data_memtype[1] is set to 1 when an data fetch attempt is performed with the cacheable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk5.a_pma_obi_cacheon\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that data_memtype[1] is set to 0 when an data fetch attempt is performed with the cacheable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_cacheoff\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Data fetch attempts to PMA restricted regions should cause data_req_o to be deasserted.", + "Verification Goal": "Ensure that PMA violating data fetch attempts does not assert the data_req_o signal", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_req_prohibited\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "Non-naturally aligned data accesses shall only occur for Main memory accesses.", + "Feature Description": "Non-naturally aligned load access attempts to I/O shall\n cause a precise load access fault (exception code 5).", + "Verification Goal": "Attempt arbitrary non-naturally aligned load accesses to I/O regions specified by PMA and ensure that these accesses triggers precise load access fault exceptions (code 5). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions. \n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nld from addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nlw from addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nlh from addresses in IO space with and_reduce(addr_lsb[1:0]) = 1\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary non-naturally aligned load accesses to I/O regions specified by PMA and ensure that these accesses triggers precise load access fault exceptions (code 5). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions. \n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nld from addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nlw from addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nlh from addresses in IO space with and_reduce(addr_lsb[1:0]) = 1\n", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*", + "Comment": "TODO missing \"ld/lw/lh\" specific covers." + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "Non-naturally aligned store access attempts to I/O shall\n cause a precise store access fault (exception code 7).", + "Verification Goal": "Attempt arbitrary non-naturally aligned store accesses to I/O regions specified by PMA and ensure that these accesses triggers precise store access fault exceptions (code 7). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nsd to addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nsw to addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nsh to addresses in IO space with and_reduce(addr_lsb[1:0]) = 1", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary non-naturally aligned store accesses to I/O regions specified by PMA and ensure that these accesses triggers precise store access fault exceptions (code 7). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nsd to addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nsw to addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nsh to addresses in IO space with and_reduce(addr_lsb[1:0]) = 1", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*", + "Comment": "TODO missing \"sd/sw/sh\" specific covers." + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "Multi-memory operation instructions", + "Feature Description": "When the first memory access of a non-naturally aligned load operation fails due to PMA checks, the second memory access shall also be supressed. ", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A :uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_failure_denies_subsequents\n\nRTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "If a PMA access fault occurs for any of the memory accesses in a non-naturally aligned load, the register file shall not be updated", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n- Boundary between IO region and memory region s.t. first access will be in memory and second access will be in IO.\n\nIn both cases, the register file should remain unchanged.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n- Boundary between IO region and memory region s.t. first access will be in memory and second access will be in IO.\n\nIn both cases, the register file should remain unchanged.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "When the first memory access of a non-naturally aligned store operation fails due to PMA checks, the second memory access shall also be supressed. ", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Zce Extension", + "Sub Feature": "Push instructions", + "Feature Description": "push, push.e, c.push, c.push.e instructions shall only occur for main memory regions, any such *push* attempts to I/O shall cause a precise load access fault (exception code 5)", + "Verification Goal": "Attempt *push* operations to main memory and IO, verify that all *push* attempts to IO causes a precise store access fault (code 5) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt *push* operations to main memory and IO, verify that all *push* attempts to IO causes a precise store access fault (code 5) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*", + "Comment": "TODO missing random test?\n\nNote: Cover doesn't check that it goes through WB." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "Pop instructions", + "Feature Description": "pop, popret, pop.e, popret.e, c.pop, c.popret, c.pop.e, c.popret.e shall only occur for main memory regions, any such *pop* attempts from I/O shall cause a precise load access fault (exception code 7)", + "Verification Goal": "Attempt *pop* operations to main memory and IO, verify that all *pop* attempts to IO causes a precise loac access fault (code 7) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt *pop* operations to main memory and IO, verify that all *pop* attempts to IO causes a precise loac access fault (code 7) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*", + "Comment": "TODO missing random test?\n\nNote: Cover doesn't check that it goes through WB." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "Table Jump", + "Feature Description": "Both jumps from a Zce table jump should be checked by PMA and handled as instruction fetches. \n\nPMA failure in the first table jump should suppress the second jump - instr_fetch_o should be suppressed and no jump to the restricted address shall be performed", + "Verification Goal": "First jump: Testing a violating first jump (jump to the jump table) requires a custom linker script that deliberatly places the jump table in a non-executable (IO) region. A test must verify that instructions attempting to jump to the jump table location causes an instruction access fault (exception code 1) and that instr_req_o is suppressed\n\nThe second instruction fetch should be suppressed.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Second jump: Test should verify that a PMA access fault on the second jump (jump to the actual instruction address in IO region) should cause an instruction access fault (exception code 1), suppressing instr_req_o. ", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Coverpoint - Table jumps passing PMA checks crossed with region index or default unmapped memory region", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_pmafault_tablejump_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_firstfail_tablejump:_*\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_allow_jvt_*", + "Comment": "TODO missing random test?\n\nNote: This is not maximally comprehensive, but the modelling that would otherwise be required is disproportionately complex." + }, + { + "Requirement Location": "Zce spec. proposal", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "Instruction fetch exceptions occurring when executing an address in the jump table should lead to mepc being set to the C.TBLJ* instruction, and mtval to the address in the jump table entry", + "Verification Goal": "Verify that an instruction fetch exception resulting from a jump table entry leads to mepc being set to the C.TBLJ* instruction and mtval to the address in the jump table entry.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "Risc-V Debug spec.", + "Feature": "Debug mode", + "Sub Feature": "Single step PMA exceptions", + "Feature Description": "Any instruction fetch exception that occurs while single stepping, causes debug mode to be re-entered after PC is changed to the exception handler and the appropriate tval and cause registers are updated", + "Verification Goal": "Verify that instruction fetches to PMA IO regions fails, the appropriate CSRs and PC is updated to the appropriate values and debug mode is reentered. ", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_debug/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "Program buffer PMA exceptions", + "Feature Description": "Exceptions in the program buffer should cause the program buffer code to end and cmderr set to 3 (exception error)", + "Verification Goal": "Verify that program buffer code attempting to fetch instructions from PMA IO region fails, PC is set to dm_exception_addr_i and cmderr is set to 3 (exception error). No other registers should be changed due to this exception.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_debug/", + "Comment": "" + }, + { + "Requirement Location": "40s UM 0.8.0", + "Feature": "DebugRange", + "Sub Feature": "DebugRange", + "Feature Description": "\"CV32E40S overrules the PMA and PMP settings for the Debug Module region when it is in debug mode\"", + "Verification Goal": "Attempt access within/outside the dm region, in both dmode/not, check that the combo within/dmode never gets blocked and that the other combos follow the ordinary rules.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Code Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_dm_region\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_dm_region\n\nA: (The other cases are covered by all other testing.)\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_dmregion_dmode_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Atomic operations", + "Sub Feature": "Atomic operations shall only occur for regions in which Atomic operations are allowed. (Only applies for cores with A-extension)", + "Feature Description": "Load-Reserved attempts to a region where atomic operations are not permitted shall cause a precise load access fault (exception code 5)", + "Verification Goal": "Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Atomic operations", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Atomic operations", + "Sub Feature": "", + "Feature Description": "Store-Conditional or Atomic Memory Operation (AMO) attempts to a region where Atomic operations are not allowed shall cause a precise store/AMO access fault (exception code 7).", + "Verification Goal": "Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Atomic operations", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Fence* instructions", + "Sub Feature": "Fence instructions disregards distinction between memory and IO", + "Feature Description": "Fence instruction shall not be impacted by PMA memory/IO attribute and execute as a conservative fence on all operations ", + "Verification Goal": "Coverpoint - Fence instructions (Fence, fence.i) should not be impacted by PMA.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_waspmafault_wasmain_wasloadstore_fence_*", + "Comment": "TODO missing random test?" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "WriteBuffer", + "Sub Feature": "Bufferable operations", + "Feature Description": "Only bufferable store accesses should use the internal write buffer", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.a_writebuf_bufferable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.gen_noregions_nobuf.a_writebuf_noregions\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------END---------", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json new file mode 100644 index 0000000000..43080652d0 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json @@ -0,0 +1,1718 @@ +[ + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "SmepmpOverrule", + "Feature Description": "The \"smepmp\" spec features can overrule the \"privspec\" (e.g. for locking). Both specs are included here, so be mindful that checking of certain vplan items could be conditional.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "FunctionalCoverage", + "Feature Description": "Functional coverage is encouraged to be creative in capturing a broad set of possible state, and evaluate it towards the checkers, to catch aspects of pmp functionality that this vplan might have overlooked.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "ImplementationChanges", + "Feature Description": "If test implementation reveals new knowledge that contradicts or augments this vplan, then the vplan should be updated.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "TimeAllowance", + "Feature Description": "Some verification goals in this plan has a \"base level\" of checking plus some optional tweaks that might be tried. It is up to the testing implementation how to prioritize and potentially skip the extras, according to what time allows.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "privspec", + "Feature": "General", + "Sub Feature": "Configs", + "Feature Description": "The pmp must be tested in a wide range of configurations. That includes testing on both instruction-side and data-side, and it includes testing overlapping regions, non-overlaping, no regions, differing settings for overlapping regions, M-mode only, U-mode only, both M-mode and U-mode, etc, etc. Use functional coverage with plenty of crosses.", + "Verification Goal": "Run with different configs to test parameters in low/mid/high ranges and in combination with the other parameters, instantiate checking on both instruction-side and data-side, write coverage to see all relevant region overlap combinations and to see an exhaustive combination of block-level input combinations and functional-level states.", + "Pass/Fail Criteria": "Other", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "Smepmp", + "Feature Description": "Given 1) backwards-compatible reset values, and 2) no change in \"mseccfg\", then C) the PMP should be fully compatible with the privspec.", + "Verification Goal": "For all privspec-derived PMP assertions, check that they must hold as long as the two preconditions hold (i.e. must not be excusable/overridable by smepmp features).", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "UmodeAlways", + "Feature Description": "\"PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches in S and U mode, data accesses in S and U mode when the MPRV bit in the mstatus register is clear, and data accesses in any mode when the MPRV bit in mstatus is set and the MPP field in mstatus contains S or U.\"\n\nNote: None of those scenarios should let an access bypass the pmp.", + "Verification Goal": "Set up the system to match each point in the listing, ensure that the pmp's decision matches all modelled expectations.\n\nNote: Also cover when none of the listed preconditions are active and the pmp's decision can disagree with the modelled expectations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "DefaultNone", + "Feature Description": "\"PMP can grant permissions to S and U modes, which by default have none\"", + "Verification Goal": "Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then U-mode has no access permissions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "DefaultFull", + "Feature Description": "\"can revoke permissions from M-mode, which\nby default has full permissions\"", + "Verification Goal": "Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then M-mode has full access permissions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "ResetRegisters", + "Feature Description": "\"Writable PMP registers\u2019 A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers\u2019 A and L fields.\"", + "Verification Goal": "Read the A and L values right after reset, ensure that the default reset values are 0.\n\nNote: Should also be visible on rvfi without specifically using csr instructions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "Warl", + "Feature Description": "\"All PMP CSR fields are WARL and may be hardwired to zero\".\n\nNote: A field shall also not change its value when an attempt is made to write an illegal value to it. (XWR is one field.)", + "Verification Goal": "Try writing any values to the registers and read values out of them, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected and that illegally written fields don't change.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "MmodeOnly", + "Feature Description": "\"PMP CSRs are only accessible to M-mode.\"", + "Verification Goal": "Try to access any of the pmp CSRs from U-mode, ensure that it always gives \"illegal instruction exception\" and that the CSRs are not updated.\n\nNote: M-mode accesses are covered by AlwaysAccessible below.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_csrs_mmode_only\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover (combine with \"Warl\" above)" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "Addr34bit", + "Feature Description": "\"Each PMP address register encodes bits 33\u20132 of a 34-bit physical address for RV32\"", + "Verification Goal": "Ensure that when the pmpaddr MSBs are set, then no NAPOT accesses matches. Cover that all bits have been matched against (\"toggle cross\"). Ensure that there are no attempted accesses to MSBs that the core should not be able to use.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "AddrImplemented", + "Feature Description": "\"Not all physical address bits may be implemented, and so the pmpaddr registers are WARL.\"", + "Verification Goal": "Cover (toggle) that all bits can be both written and set. (UnusedZero below covers the WARL(0x0) case.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "MatchDisabled", + "Feature Description": "\"When A=0, this PMP entry is disabled and matches no addresses\"\nWhen a cfg is set to off but its address(es) (interpreted as napot/tor) is the only rule that matches an attempted access, then it still does not count as a match.", + "Verification Goal": "Have a region's address(es) set up as tor and napot (separate runs), have all other regions not include the target address, have the target region's rule be OFF, make an access within that range, ensure that the outcome is the same as for when an access is outside of all address ranges.\n\nNote: For this and several other items, functional coverage is necessary because the checking doesn't necessarily have the above scenario in its antecedent.\n\nCoverage: Capture the above scenario, minus the checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotMatching", + "Feature Description": "\"NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range [\"yyyy...yy01\" etc]\"\n\nNote: The napot address matching modes match on addresses that are equal to the requested access when masked to the granularity size.", + "Verification Goal": "Configure napot rules of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated sizes.\n\nNote: Includes NAPOT and NA4.\n\nNote: Try also max and min.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4is4byte.a_na4_is_4byte\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_bin_auto[*]\ndut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_disallowed_bin_auto[*]\n\nCOV: ???", + "Comment": "TODO missing coverage" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorMatching", + "Feature Description": "\"If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range. If PMP entry i\u2019s A field is set to TOR, the entry matches any address y such that pmpaddri\u22121 \u2264 y < pmpaddri (irrespective of the value of pmpcfgi\u22121)\"", + "Verification Goal": "Configure tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_ismatch_tor_bin_auto[*]\n\nCOV: ???", + "Comment": "TODO missing coverage" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorZero", + "Feature Description": "\"If PMP entry 0\u2019s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr0.\"", + "Verification Goal": "Configure entry 0 as tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorNomatch", + "Feature Description": "\"If pmpaddri\u22121 \u2265 pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses.\"", + "Verification Goal": "Set up tor regions where the addresses are not in increasing order, try accesses on or within the designated \"reverse\" regions, ensure that they are treated as if there is no match.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "SameGrain", + "Feature Description": "\"In general, the PMP grain [...] must be the same across all PMP regions.\"", + "Verification Goal": "Do the same as for the basic case of GranularityDetermination below, ensure that all read values are the same across all the pmp csrs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "Na4Unselectable", + "Feature Description": "\"When G \u2265 1, the NA4 mode is not selectable.\"", + "Verification Goal": "Have the G parameter set to at least 1, ensure that NA4 never gets selected (even when writing to non-locked cfg).\n\nNote: Formal should easily check this.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_only_g0\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_only_g0\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_not_when_g uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_not_when_g", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotImplied", + "Feature Description": "\"When G \u2265 2 and pmpcfgi.A[1] is set, i.e. the mode is NAPOT\".", + "Verification Goal": "(Covered by Na4Unselectable above)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotOnes", + "Feature Description": "\"When G \u2265 2 and pmpcfgi.A[1] is set, [...] then bits pmpaddri[G-2:0] read as all ones.\"", + "Verification Goal": "Have the G parameter set to at least 2, have A set, read pmpaddri, ensure the LSBs are all ones as specified.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_napot_ones_g2.gen_napot_ones_i[*].a_napot_ones", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "AllZeros", + "Feature Description": "\"When G \u2265 1 and pmpcfgi.A[1] is clear, i.e. the mode is OFF or TOR, then bits pmpaddri[G-1:0] read as all zeros.\"", + "Verification Goal": "Create the listed preconditions, ensure that the read value contains zeroes as specified.\n\nNote: Check both OFF/TOR, and for all configs fields (checking of all configs don't need 100% coverage in simulation).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_all_zeros_g1.gen_all_zeros_i[*].a_all_zeros\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorUnaffected", + "Feature Description": "\"Bits pmpaddri[G-1:0] do not affect the TOR address-matching logic.\"", + "Verification Goal": "Write different values to \"pmpaddri[G-1:0]\", ensure TOR mode matches the same either way.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "StorageUnaffected", + "Feature Description": "\"Although changing pmpcfgi.A[1] affects the value read from pmpaddri, it does not affect the underlying value stored in that register\"\n\"in particular, pmpaddri[G-1] retains its original value when pmpcfgi.A is changed from NAPOT to TOR/OFF then back to NAPOT.\"", + "Verification Goal": "Change in and out of (OFF || TOR) and !(OFF || TOR), ensure that different values can be read without having written anything new to the register.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_storage_unaffected[*].a_storage_unaffected\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "GranularityDetermination", + "Feature Description": "\"Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading back pmpaddr0. If G is the index of the least-significant bit set, the PMP granularity is 2 G+2 bytes.\"", + "Verification Goal": "Write zero to pmpicfg, write ones to pmpaddri, read pmpaddri, ensure that the LSB index matches to granularity parameter.\n\nNote: Formal can maybe check this for all i.\n\nNote: If time allows, can write something else than zero and ensure that the rest follows as expected.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_granularity_determination", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "XlenMatching", + "Feature Description": "\"If the current XLEN is greater than MXLEN, the PMP address registers are zero-extended from MXLEN to XLEN bits for the purposes of address matching.\"", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "UntilReset", + "Feature Description": "\"Locked PMP entries remain locked until the hart is reset.\"", + "Verification Goal": "Lock entry i (for all i, if feasible), ensure that the lock bit is never lifted before reset. (Unless if RLB interferes.)\n\nNote: Sim might do a second reset, formal most likely won't and shouldn't need to.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_until_reset[*].a_until_reset", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "IgnoreWrites", + "Feature Description": "\"If PMP entry i is locked, writes to pmpicfg and pmpaddri are ignored.\"", + "Verification Goal": "Lock entry i (for all i, if feasible), ensure that their value can't change, both when written to and otherwise. (Unless if RLB interferes.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_notrap[*].a_ignore_writes_notrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_nochange[*].a_ignore_writes_nochange\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "IgnoreTor", + "Feature Description": "\"Additionally, if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored.\"", + "Verification Goal": "Lock entry i (\u2026), have A set and the mode be TOR, ensure that pmpaddri-1 can't change, both for explicit writes and otherwise. (Unless RLB.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_stable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_wdata\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "NotIgnore", + "Feature Description": "When neither cfg i is locked, nor is cfg i+1 a locked TOR region, then writes to cfg and addr i are not ignored.", + "Verification Goal": "Have cfg i unlocked, write to cfg and addr csr i, check that it changes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_writes[*].a_addr_nonlocked\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_tor[*].a_addr_nonlocked_tor", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "LockOff", + "Feature Description": "\"Setting the L bit locks the PMP entry even when the A field is set to OFF.\"", + "Verification Goal": "Lock entry i while the mode is OFF, ensure that it gets locked in this case too.\n\nNote: Ensure that checking and coverage handles locking for all possible modes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: (Same checking as for \"IgnoreWrites\" and \"IgnoreTor\" above.)\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "RwxPrivmode", + "Feature Description": "\"In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are enforced on M-mode accesses. When the L bit is set, these permissions are enforced for all privilege modes.\"", + "Verification Goal": "Be in M-mode and U-mode (separate runs), access a region where L is set and where RWX {grant, deny R, deny W, deny X}, ensure that the access is correspondingly granted/denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "MmodeSucceed", + "Feature Description": "\"When the L bit is clear, any M-mode access matching the PMP entry will succeed\"", + "Verification Goal": "Be in M-mode, access a region where L is clear, ensure that access is granted in all cases.\n\n(Note, see \"Smepmp\" above.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "RwxUmode", + "Feature Description": "\"When the L bit is clear [\u2026] the R/W/X permissions apply only to S and U modes.\"", + "Verification Goal": "Be in U-mode, access a region where L is clear, ensure that access is granted/denied based on RWX.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_uorl_onlyif_rwx\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_uorl_onlyif_rwx\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "LowestDetermines", + "Feature Description": "\"PMP entries are statically prioritized. The lowest-numbered PMP entry that matches any byte of an access determines whether that access succeeds or fails.\"\n\nNote: \"any\" byte.", + "Verification Goal": "Access a region that is covered by multiple rules, ensure that the lowest indexed match determines the outcome.\n\nNote: Requires that the rules would disagree on the outcome.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MatchAll", + "Feature Description": "\"The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits.\"", + "Verification Goal": "(Only relevant for 64-bit architectures.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "LrwxDetermines", + "Feature Description": "\"If a PMP entry matches all bytes of an access, then the L, R, W,and X bits determine whether the access succeeds or fails. [...] if the L bit is set or the privilege mode of the access is S or U, then the access succeeds only if the R, W,or X bit corresponding to the access type is set.\"", + "Verification Goal": "Access a pmp region where L and the privmode etc is such that nothing else would deny the access, ensure that each of (or a combination of) RWX can either grant or deny the access.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_lrwx_aftermatch\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_lrwx_aftermatch\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MmodeSucceed2", + "Feature Description": "\"If the L bit is clear and the privilege mode of the access is M, the access succeeds.\"", + "Verification Goal": "(Same as \"MmodeSucceed\" above)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MmodeNomatch", + "Feature Description": "\"If no PMP entry matches an M-mode access, the access succeeds.\"", + "Verification Goal": "Be in M-mode, access a region where no rule matches, ensure that the access is granted (where MMWP is off).\n\n(Note, see \"Smepmp\" above.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "UmodeNomatch", + "Feature Description": "\"If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.\"\n\nNote: \"All PMP CSRs are always implemented\".", + "Verification Goal": "Be in U-mode, do an access that doesn't match any region, ensure that the access fails.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_umode_fails\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_umode_fails\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "UmodeOff", + "Feature Description": "\"If at least one PMP entry is implemented, but all PMP entries\u2019 A fields are set to OFF, then all S-mode and U-mode memory accesses will fail.\"", + "Verification Goal": "Be in U-mode, have all entries OFF, make an access, ensure that the access fails (for all variations of accesses).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "FailException", + "Feature Description": "\"Failed accesses generate an instruction, load, or store access-fault exception.\"", + "Verification Goal": "Cause failed accesses on instructions/loads/stores, ensure that an exception occurs and that it is the right one.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: ::uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MultiAccess", + "Feature Description": "\"Note that a single instruction may generate multiple accesses, which may not be mutually atomic. An access-fault exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects.\"\n\n\"On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an access-fault exception occurs. In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check.\"", + "Verification Goal": "Induce misaligned word instruction-fetch, load, and store, where the lower and upper (separate runs) parts are either accessible or blocked by pmp, ensure that exceptions occur while parts of the access might reach the bus.\n\nAlso check Zc's push/pop and table jump.\n\nNote: It is up to other vplans to check what happens upon the exception. It is up to this PMP vplan to check that the PMP will cause the exceptions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap\n\nA: ???\n\nCOV: ???", + "Comment": "TODO missing assert (on split that errs on first)\n\nTODO missing cover" + }, + { + "Requirement Location": "smepmp", + "Feature": "MsecCfg", + "Sub Feature": "MmodeOnly", + "Feature Description": "\"Machine Security Configuration (mseccfg) is [...] only accessible to Machine mode.\"\n\nNote: Includes \"mseccfgh\".", + "Verification Goal": "Access (read/write) mseccfg (and mseccfgh) from M-mode, access mseccfg from U-mode, ensure that the first always works (WARL) and the second never works (exception).\n\nNote: Cover with MPRV too.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "FieldsWarl", + "Feature Description": "\"All mseccfg fields defined on this proposal are WARL\"", + "Verification Goal": "Try writing any values to the fields (the defined ones, but also other bits) and read values out of the fields, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected.\n\nNote: This relates to the \"stickiness\" of those fields. Regardless of their values and current stickiness, the fields are WARL.\n\nNote: It might be difficult, when trying to write a checker for traps, to filter out all other causes for traps that can occur simultaneously. (Either reduce the scope of checking, or write re-usable helper signals for \"trap causality\" info.)\n\nNote: \"WPRI\" on some bits.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "ReservedZero", + "Feature Description": "\"the remaining bits are reserved for future standard use and should always read zero.\"\n(This spec can't dictate that about other specs, but the user manual agrees on the hardwiring.)", + "Verification Goal": "Read mseccfg, ensure the non-smepmp-field bits are always zero.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "ResetValue", + "Feature Description": "\"The reset value of mseccfg is implementation-specific, otherwise if backwards compatibility is a requirement it should reset to zero on hard reset.\"", + "Verification Goal": "Read the value of mseccfg right after reset, ensure that the default reset value is zero.\n\nNote: Should also be visible on rvfi without specifically using csr instructions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mseccfg_reset_val\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mseccfg_reset_val", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "ModifiableEntries", + "Feature Description": "\"When mseccfg.RLB is 1 locked PMP rules may be removed/modified and locked PMP entries may be edited.\"\n\nNote: Both \"cfg\" and \"addr\" registers, limited to fields within \"cfg\" reg, also TOR affects lower \"addr\" reg.", + "Verification Goal": "Have a locked pmp entry i, set RLB to 1, try modifying any(!) field within {pmpicfg, pmpaddri, pmpaddri-1(tor)}, ensure that values are updated succesfully (while respecting other rules like legal values and reserved bits).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_addr\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_exec\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_lock\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_mode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_read\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_write\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "RemainZero", + "Feature Description": "\"When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset\"\n\nNote: \"any\" entry.", + "Verification Goal": "Have RLB=0 and at least one L=1, ensure that RLB is 0 forever (until reset).\n\nNote: No exception occurs on attempted access, but one should try overwriting the value to stimulate the checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_rlb_never_fall_while_locked\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_rlb_never_fall_while_locked", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "UntilReset", + "Feature Description": "The sticky zero and update-ignores last until reset, and do not hold after reset.", + "Verification Goal": "Ensure that RLB is modifiable after reset. (Unless if reset values are set to activate the RemainZero condition.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_until_reset_notbefore\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "HardwireZero", + "Feature Description": "\"Vendors who don\u2019t need this functionality may hardwire this field to 0.\"", + "Verification Goal": "(40s has not hardwired this to 0, it is RW.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WhiteList", + "Sub Feature": "StickyUntilReset", + "Feature Description": "\"[mseccfg.MMWP] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.\"", + "Verification Goal": "Have MMWP set, ensure that it remains high forever (til reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mmwp_never_fall_until_reset\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mmwp_never_fall_until_reset", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WhiteList", + "Sub Feature": "Denied", + "Feature Description": "\"When set it changes the default PMP policy for M-mode when accessing memory regions that don\u2019t have a matching PMP rule, to denied instead of ignored.\"", + "Verification Goal": "Have MMWP set, be in (effective mode) M-mode, access regions that don't match any rule (including OFF, \"reversed\" TOR, >32bit NAPOT, etc), ensure that the access is denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_mmode_mmwp_fails\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_mmode_mmwp_fails\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "StickyUntilReset", + "Feature Description": "\"[mseccfg.MML] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.\"", + "Verification Goal": "Cover: Trying to clear the bit.\n\nCheck: Have MML set, ensure that it remains high forever (til reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mml_never_fall_until_reset\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mml_never_fall_until_reset\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "ExecIgnored", + "Feature Description": "\"[When mseccfg.MML is set.] Adding an M-mode-only or a locked Shared-Region rule with executable privileges is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged.\"\n\nNote: \"pmpcfg\" refers to a field, so the write to the CSR itself should still update other fields.", + "Verification Goal": "Have MML set, try adding an \"M-mode-only\" rule and a \"locked Shared-Region\" rule with X privileges, ensure that the relevant pmpcfg field is not updated but is left unchanged, ensure also that other fields can still get updated.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "ExecRlb", + "Feature Description": "\"[The above] restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB.\"", + "Verification Goal": "Have RLB and MML set, try adding an \"M-mode-only\" rule and a \"locked Shared-Region\" rule with X privileges, ensure that the relevant pmpcfg field is in fact updated.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rlblifts_lockedexec[*].a_rlblifts_lockedexec", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "MmodeExec", + "Feature Description": "\"Executing code with Machine mode privileges is only possible from memory regions with a matching M-mode-only rule or a locked Shared-Region rule with executable privileges. Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied.\"", + "Verification Goal": "Execute from \"M-mode-only\" and \"locked Shared-Region\" regions, attempt execution without matching and from \"U-mode-only\" regions, ensure corresponding grant or deny.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "RwReserved", + "Feature Description": "\"If mseccfg.MML is not set, the combination of pmpcfg.RW=01 remains reserved for future standard use.\"", + "Verification Goal": "Whitelist the conditions that allow RW=01 (including MML conditions), ensure that it is adhered to.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rwx_mml[*].a_rwx_mml\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rwfuture[*].a_rw_futureuse\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rwfuture[*].a_rw_futureuse", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeEnforce", + "Feature Description": "\"[When mseccfg.MML is set.] An M-mode-only rule is enforced on Machine mode\"", + "Verification Goal": "Be in M-mode, have MML set, access an \"M-mode-only\" region, ensure that the grant/deny is always in accordance to the rule. (E.g. it is not denied execute despite the execute bit being set.)\n\nNote: Exclude cases of interference from e.g. PMA.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeDeny", + "Feature Description": "\"[When mseccfg.MML is set.] An M-mode-only rule is [...] denied in Supervisor or User mode.\"", + "Verification Goal": "Be in U-mode, have MML set, access an \"M-mode-only\" region, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "RemainLocked", + "Feature Description": "\"It also remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset\"\n\nCertain rules under MML are sticky. They cannot be modified again.", + "Verification Goal": "Configure rules for {\"M-mode-only\", \"U-mode-only, \"Shared-Region rule where pmpcfg.L is set\"(both kinds)}, have MML=1 (and RLB=0), ensure that the configs never change again (until reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "RlbUnlocks", + "Feature Description": "\"It also remains locked [...] unless mseccfg.RLB is set.\"", + "Verification Goal": "Have the same setup as in RemainLocked, but let RLB=1, try changing the configs, ensure that they are indeed changed.\n\nNote: \"Assertion check\" includes cover properties.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeEnforce", + "Feature Description": "\"[When mseccfg.MML is set.] An S/U-mode-only rule is enforced on Supervisor and User modes \"", + "Verification Goal": "Be in U-mode, have MML=1, access a \"U-mode-only\" region, ensure that the grant/deny is in accordance with the rule (apart from PMA etc).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cg_data\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cg_instr\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeDeny", + "Feature Description": "\"An S/U-mode-only rule is [...] denied on Machine mode.\"", + "Verification Goal": "Be in M-mode, have MML=1, access a \"U-mode-only\" region, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing coverage. (Just do a cg with crosses of all of these variables.)" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedEnforced", + "Feature Description": "\"A Shared-Region rule is enforced on all modes\"", + "Verification Goal": "Be in M-mode and U-mode (separate runs), access a \"Shared-Region\", ensure that the grant/deny is in accordance with the rule.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedNoexec", + "Feature Description": "\"A Shared-Region rule where pmpcfg.L is not set can be used for sharing data between M-mode and S/U-mode, so is not executable.\"", + "Verification Goal": "Be in M-mode and U-mode, try to execute from \"A Shared-Region rule where pmpcfg.L is not set\", ensure that it does not work (exception).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeReadwrite", + "Feature Description": "\"[Shared-Region rule where pmpcfg.L is not set.] M-mode has read/write access to that region\"", + "Verification Goal": "Be in M-mode, perform reads and writes to such a region, ensure that the intended effects happen and that the accesses do not cause exceptions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeRead", + "Feature Description": "\"[For a Shared-Region rule where pmpcfg.L is not set] S/U-mode has read access if pmpcfg.X is not set, or read/write access if pmpcfg.X is set.\"", + "Verification Goal": "Be in U-mode, perform reads and writes to such a region, ensure that the reads always work and that the writes depend on X.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedNowrite", + "Feature Description": "\"A Shared-Region rule where pmpcfg.L is set can be used for sharing code between M-mode and S/U-mode, so is not writeable.\"\n\nNote: The spec is unclear here, but \"A Shared-Region rule where pmpcfg.L is set\" must refer to \"LRWX=101X\", because \"The encoding pmpcfg.LRWX=1111\" is a separate point. (This holds for the subsequent items below too.)", + "Verification Goal": "Be in M-mode and U-mode, write to such a region, ensure that the writes do not reach the bus and that an exception occurs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "BothExecute", + "Feature Description": "\"Both M-mode and S/U-mode have execute access on the [Shared-Region rule where pmpcfg.L is set]\"", + "Verification Goal": "Be in M-mode and U-mode, attempt to execute from such a region, ensure that the code is executed and that the attempt does not cause an exception.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeRead", + "Feature Description": "\"M-mode also has read access [to Shared-Region rule where pmpcfg.L is set] if pmpcfg.X is set.\"", + "Verification Goal": "Be in M-mode, attempt to read from such a region, ensure that the success depends accordingly on X.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "IgnoreUntilReset", + "Feature Description": "\"The [Shared-Region rule where pmpcfg.L is set] remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.\"", + "Verification Goal": "(Covered by RemainLocked above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "BothReadonly", + "Feature Description": "\"The encoding pmpcfg.LRWX=1111 can be used for sharing data between M-mode and S/U mode, where both modes only have read-only access to the region.\"", + "Verification Goal": "Be in M-mode and U-mode, access such a region, ensure that only the reads work and that the rest (write/execute) excepts.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cover_item_covergroup_cg_internals_instr_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_umode_mml_lrwx\n\nCOV: ???", + "Comment": "TODO technically missing the \"the rest \u2026 excepts\" cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "ReadonlyLocked", + "Feature Description": "\"The [pmpcfg.LRWX=1111] rule remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.\"", + "Verification Goal": "(Covered by RemainLocked above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LegalRwx", + "Sub Feature": "", + "Feature Description": "Depending on the mseccfg control bits and L, some RWX combinations are reserved.\n\nNote: Use the table from the spec.", + "Verification Goal": "Ensure that illegal/reserved mseccfg/L/RWX combinations are unreachable.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Reachable", + "Sub Feature": "", + "Feature Description": "All legal states in the table are reachable. It could theoretically be that platform-specific constraints made certain states unreachable (particularily related to locking), but we should be able to reach all legal and supported combinations of settings.", + "Verification Goal": "Ensure that all legal states are reachable.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "manual", + "Feature": "Parameters", + "Sub Feature": "MinimumGranularity", + "Feature Description": "\"The PMP_GRANULARITY parameter is used to configure the minimum granularity of PMP address matching. The minimum granularity is [2^(PMP_GRANULARITY+2)] bytes, so at least 4 bytes.\"", + "Verification Goal": "Have runs with max granularity, minimum granularity, and something in between. Make sure all checkers/covers are active for each relevant run configuration, so tor/napot/na4 is tested with different granularities. Cover cases where a match would otherwise occur but the granularity made the access not match.\n\nNote: Ensure TorMatching etc above heed this parameter.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "NumRegions", + "Feature Description": "\"The PMP_NUM_REGIONS parameter is used to configure the number of PMP regions, starting from the lowest numbered region.\"\n\nNote: Including 0 regions.", + "Verification Goal": "Have runs with max number, minimum number, and something in between.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "ResetValues", + "Feature Description": "\"The reset value of the PMP CSR registers can be set through the top level parameters PMP_PMPNCFG_RV[], PMP_PMPADDR_RV[] and PMP_MSECCFG_RV.\"", + "Verification Goal": "Have runs with different reset values. Ensure that after reset then the reset values are effectuated.\n\nNote: Try also, reset values with locked configs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "DefaultValues", + "Feature Description": "The reset value defaults should amount to a safe config. (Including no violation of reserved bits.)", + "Verification Goal": "(Covered by all the checks that handles the various legalities.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "AlwaysAccessible", + "Feature Description": "\"All PMP CSRs are always implemented\". \"MRW\". The CSRs are M-mode accessible, and their existence does not depend on PMP_NUM_REGIONS.\n\nNote: \"All\" pmp registers, and all fields within them.", + "Verification Goal": "Be in M-mode, access (reads/writes) all the pmp csrs, ensure that it always works without excepting (because the csrs exist and the mode is appropriate).\n\nNote: Potential overlap with CSR vplan.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "ReservedLegal", + "Feature Description": "Reserved bits/fields have legal values, matching the platform-specified defaults.", + "Verification Goal": "(Overlaps with LegalRwx and RwReservedabove.) Read all fields of all pmp-related csrs, ensure there are no unsupported values anywhere (at all times).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MseccfghZero", + "Feature Description": "\"Hardwired to 0\"", + "Verification Goal": "Read mseccfgh, ensure it is always 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "UnusedZero", + "Feature Description": "\"CSRs (or bitfields of CSRs) related to PMP entries with number PMP_NUM_REGIONS and above are hardwired to zero.\"\n\nNote: Including upper parts of pmpcfgn and also pmpaddr.", + "Verification Goal": "Read pmpcfg and pmpaddr csrs, ensure the values are zero as specified. Cover that the other values can be non-zero.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Hardening", + "Feature Description": "Certain CSRs related to the PMP shall be \"hardened\" as per Xsecure.", + "Verification Goal": "(CSR hardening is the responsibility of the security features vplan, even the pmp-specific part of it.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "WaitUpdate", + "Feature Description": "Updates to pmp configs should NOT have an effect on earlier instructions (nor on the instruction itself).\n\nNote: Potential security hole.", + "Verification Goal": "The pmp grant/deny checking must be compared vs \"rvfi_csr__rdata\".\n(This will detect whether the actual pmp decision differs from what the rvfi csr data would incidate.)\n\nNote: Compare \"pc_rdata\" for execute, and \"mem_\" signals for read/write. (Might need additional decoding of \"rvfi_insn\".)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_musttrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_musttrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Inject pmp csr write instructions in random testing, intermingled with all other kinds of instructions. This should include random interrupts, bus faults, random bus stalls, etc.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "AffectSuccessors", + "Feature Description": "Updates to pmp configs MUST have an effect on later instructions.\n\nNote: Potential security hole.\n\nNote: There was a known rtl bug here before (cv32e40s/issues/168).", + "Verification Goal": "The \"rvfi_csr__wdata\" (masked) for pmp csrs on one instruction, must match the \"_rdata\" value of the next instruction.\n(Combined with checking grant/deny on \"_rdata\", this should ensure that the subsequent instruction has been affected by any pmp csr update.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "(Shares asserts with \"WaitUpdate\" above.)\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_cfg_writes\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_addr_writes", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "(Same random testing as WaitUpdate above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "ImplementationDetails", + "Feature Description": "Details about pipeline/prefetcher/bus flushing etc are not part of this vplan. Only black-box observable functional behavior is checked. (Such requirements exists in specs, but are deliberately not addressed here.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "Performance", + "Feature Description": "Requirements about performance and stalls etc are not covered here (unless review calls for the opposite).", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "WriteBuffer", + "Feature Description": "Changes to the pmp config should not impact the write buffer such that a transaction can get its grant/deny status altered.", + "Verification Goal": "Cover cases of the write buffer being full while the pmp cfg changes. Checking of accidental grants is handled by SuppressReq below. Checking of guaranteed writes is not part of this vplan.\n\nNote: The Write buffer is situated between the pmp and the bus.", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SuppressReq", + "Feature Description": "When an access is denied by the pmp, the effect is that the attempted obi transaction is suppressed and does not reach the bus.\n\nNote: Both \"instr_req_o\" and \"data_req_o\".", + "Verification Goal": "Observe a transaction request coming in to the pmp module, observe the pmp denying the access, ensure that the obi bus is shielded from the transaction request.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_supress_req_data.a_suppress_req_data\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_supress_req_instr.a_suppress_req_instr", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "InternalBuses", + "Feature Description": "(The transaction request feeding into the mpu and its response signaling is not covered by this vplan.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionExecute", + "Feature Description": "\"mcause [...] Instruction access fault [...] Execution attempt with address failing PMP check.\"", + "Verification Goal": "Attempt execution of a region that pmp denies execution of, ensure that an \"instruction access fault\" exception occurs (read mcause and rvfi signals).\n\nNote: Since ISS can check most of this, one could deprioritize this checking if it is not feasible to check within reasonable efforts. (Same for the next 2 items.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionLoad", + "Feature Description": "\"mcause [...] Load access fault [...] Load attempt with address failing PMP check.\"\n\nNote: Holds for load-reserved too.", + "Verification Goal": "Attempt loads (and load-reserveds) of a region that pmp denies reading from, ensure that a \"load access fault\" exception occurs (read mcause and rvfi signals).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionStore", + "Feature Description": "\"mcause [...] Store/AMO access fault [...] Store attempt with address failing PMP check.\"\n\nNote: Holds for store-conditional and amo too.", + "Verification Goal": "Attempt stores (and store-conditionals and amo) to a region that pmp denies writing to, ensure that a \"store/amo access fault\" exception occurs (read mcause and rvfi signals).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "TrapPrecisely", + "Feature Description": "\"All exceptions are precise\".\nMeaning mepc will point to the offending instruction, and exactly previous instructions have their side effects fully visible.\n\nNote: Applies to loads, stores, and executes.", + "Verification Goal": "Observe that the pmp causes an exception, ensure that mepc points to the offending instruction.\n\nNote: Let the Exceptions vplan deal with visibility of side effects for earlier instructions. (Zc push/pop does not follow this, but that is mostly the responsibility of the Zc vplan.)\n\nNote: If satisfactory mepc checking already exist then it is acceptable to just add covers for the pmp scenarios.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "AlertMinor", + "Feature Description": "\"The following issues result in a minor security alert: [...] Instruction access fault [...] Load access fault [...] Store/AMO access fault\"", + "Verification Goal": "(Responsibility of the xsecure vplan. But link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for xsecure vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "AlertNothing", + "Feature Description": "The manual lists which pmp-related events can cause an alert minor, but the pmp should in no other cases be the cause for an alert (major/minor).\n\nNote: Example, \"attempt to reprogram a locked PMP\"", + "Verification Goal": "Observe an alert signal going high while there is no pmp error that should have caused it, ensure that another viable reason for the alert was present.\n\nNote: This is slightly out of scope for this vplan, so if it is not very easy to hook on to existing xsecure (helper-)signals then this can be skipped.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SplitLoadRegfile", + "Feature Description": "Even if parts of a split load can reach the bus, the instruction itself has failed and so the regfile should not get updated.", + "Verification Goal": "(Handled by \"SplitLoadException\" below, because: One only needs to show that an exception is caused, and the exceptions vplan is responsible for checking what that means for the regfile. (But link to coverage here too.))", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "Waiting for exceptions vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SplitLoadException", + "Feature Description": "For split loads, regardless of which of the access that fails, the instruction should still cause an exception.", + "Verification Goal": "Perform a misaligned load that translates to multiple accesses, let any of the accesses be denied by pmp, ensure an exception occurs.\n\nCoverage: See rvfi retire with exception cause from pmp, while the \"low addr\" model checking gave access granted.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "FirstFail", + "Feature Description": "If a split load/store fails on its first transaction it should get an exception immediately, so it should not allow the second transaction reach the bus and mcause shall reflect the failing transactions.", + "Verification Goal": "Attempt such an instruction, ensure that the denied access does not reach the bus, ensure that following accesses also do not reach the bus.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "PushPop", + "Feature Description": "If a push/pop fails on a transaction it should get an exception immediately, so the remaining transactions should not reach the bus and mcause shall reflect the failing transaction.", + "Verification Goal": "(Responsibility of the zc vplan. But link to coverage here too.)\n\nNote: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for zc vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "TableJump", + "Feature Description": "PMP applies to table jumps and Zc instructions in general.", + "Verification Goal": "(Responsibility of the zc vplan. But link to coverage here too.)\n\nNote: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for zc vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ClicVector", + "Feature Description": "Similarly to TableJump above, CLIC vector fetch needs execute permission.", + "Verification Goal": "(Analogous to TableJump above.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for clic vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "Priority", + "Feature Description": "Exceptions priority apply to the PMP as well. Particularily, PMP exception (instruction access fault) gets priority over bus errors (instruction bus fault) if an instruction is the result of two fetches were both of these occurred.\n\nNote: Both could be present in an attempted executed instruction at the same time, because no exception occurs before the point of execution so there is enough time for both to be captured and travel through the pipeline.", + "Verification Goal": "Keep track of words fetched with bus error and with pmp execute denied, check retired instructions for a pc that overlaps two such fetches (cover both orders), ensure that \"instruction access fault\" is the taken exception.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RevokeExecutable", + "Feature Description": "Even if the pma should allow for execution, the pmp can overrule it and deny access.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for execution, let the pmp deny it, attempt execution, ensure that execution is indeed denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RemainNonexecutable", + "Feature Description": "If the pma disallows execution, the pmp cannot change this fact and execution remains disallowed.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma disallow execution, let the pmp allow and deny execution (separate runs), attempt execution, ensure that execution is denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RevokePermissible", + "Feature Description": "Even if the pma allows for data access, the pmp can overrule it and deny access.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for read and write (separate or same runs), let pmp deny read/write, attempt read/write, ensure that the pmp can overrule the pma.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RemainNonpermissible", + "Feature Description": "If the pma disallows data access, the pmp cannot change this fact and data access remains disallowed.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma deny read and write, let pmp allow or deny it, attempt read/write, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "misc", + "Feature": "Misc", + "Sub Feature": "DisallowDebug", + "Feature Description": "The PMP can deny usage of debug mode by setting up regions for dm_halt_addr and dm_exception_addr.", + "Verification Goal": "Set up pmp rules so all D-mode entries are blocked from execution, attempt to enter debug mode, ensure that nohing is executed in debug mode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "Waiting for ongoing spec changes to be resolved" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "40x", + "Feature Description": "The 40x does not have PMP.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Xif", + "Feature Description": "The X-interface can do memory operations, but the 40x does not have PMP and the 40s does not have XIF.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "RvfiReliable", + "Feature Description": "Rvfi is used for checking some pmp functionality, so the link between rvfi and pmp must be checked.", + "Verification Goal": "If feasible to model within reasonable effort, check that 1) the PMPs' privmode inputs and 2) CSRs and 3) wdata/wmask is for csr write instrs, are properly correlated between access attempts and rvfi reportings.\nOtherwise, leave this to general ISS checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\n(Indirectly checked by those asserts)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "RvfiTrap", + "Feature Description": "The \"rvfi_trap\" table has PMP-specific fields.", + "Verification Goal": "Augment the exception checkers above with checking of \"rvfi_trap.cause_type\" to ensure that specifically PMP is reported as the cause.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "UntilReset", + "Feature Description": "Everything that can get locked \"until reset\" must be possible to change after a reset. It should not be possible that these settings lock up so even resets cannot unlock them.\n\nNote: Formal's reset analysis should in principle be able to find every state that is possible to be in after a reset.", + "Verification Goal": "(Covered by ResetValues above. As long as those always take effect out of reset, then a permanent lock up should be either impossible or intentional.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Xsecure", + "Feature Description": "(Will be covered by its own vplan.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Reset", + "Feature Description": "The PMP module is never reset without the whole core being reset. (As this could lift all the locks and stickies and grant privilege escalation.)", + "Verification Goal": "Check that the core's reset is always equal to the pmp module's reset.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "UmodeZeroRegions", + "Feature Description": "If the parameters are set to have 0 pmp regions, then all rules are OFF and U-mode matches nothing and defaults to not have any access.", + "Verification Goal": "Be in U-mode, have PMP_NUM_REGIONS=0, ensure all accesses fail (read/write/execute).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "debug", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "\"All operations are executed with machine mode privilege\".\nIt is mostly the responsibility of other vplans to check D-mode relationship to M-mode and U-mode, but the pmp inputs should be checked against debug mode.\n\nNote: Refer to user-mode vplan and debug vplan if necessary.\n\nNote: It is assumed that once 1) dmode is shown to be interpreted as mmode by pmp, and 2) all mmode features are verified, then C) the mmode features will work in dmode. But one alternative is to duplicate all the mmode-related checking with dmode variants.", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\n(Indirectly checked by those asserts, together with effective priv mode and umode asserts for dmode/mmode.)\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json new file mode 100644 index 0000000000..15c57d7275 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json @@ -0,0 +1,830 @@ +[ + { + "Requirement Location": "privspec", + "Feature": "Misc", + "Sub Feature": "SupportedLevels", + "Feature Description": "\"At any time, a RISC-V hardware thread (hart) is running at some privilege level encoded as a mode\nin one or more CSRs [User, Supervisor, (Reserved), Machine]\"", + "Verification Goal": "Run all supported levels (U-mode, M-mode); ensure no unsupported levels can be run (S-mode, reserved).\n\nCoverage: Attempts to set various modes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_no_unsupported_modes\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_umode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mmode\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "ResetMode", + "Feature Description": "\"M-mode [...] is the first mode entered at reset.\"", + "Verification Goal": "Wait for reset to end, ensure that the core is in M-mode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_initial_mode\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Refetch", + "Feature Description": "Before a mode change, instructions can have been prefetched and exist in the pipeline but the fetching was done in a different mode than what is changed to. This should not allow for privilege escalation so the instructions must be refetched.", + "Verification Goal": "Checking: Handled by \"InstrProt\" below.\n\nCoverage: Instr fetched twice (same pc, different prot).", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_umode_notrap\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_mmode_notrap\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_umode_trap\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_mmode_trap", + "Comment": "" + }, + { + "Requirement Location": "obi", + "Feature": "Misc", + "Sub Feature": "InstrProt", + "Feature Description": "\"prot[2:1]\nUser/Application (2\u2019b00), Supervisor (2\u2019b01), Reserved (2\u2019b10), Machine (2\u2019b11)\nThis matches the privilege levels from [RISC-V-PRIV].\"", + "Verification Goal": "Track prot[2:1] on instruction fetches on obi, observe retirements on rvfi, ensure the privilege mode of the instruction's execution matches what it was fetched as on obi.\n\nCoverage: Explicitly observe U/M both.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_iside_legal\n\nCOV: ???", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "DataProt", + "Feature Description": "\"prot[2:1]\nUser/Application (2\u2019b00), Supervisor (2\u2019b01), Reserved (2\u2019b10), Machine (2\u2019b11)\nThis matches the privilege levels from [RISC-V-PRIV].\"", + "Verification Goal": "Track prot[2:1] on data loads/stores, observe retirements on rvfi, ensure the effective privilege mode of the retirement matches what was used on obi.\n\nCoverage: Explicitly observe U/M both.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_dside_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_equal\n\nCOV: ???", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "DbgProt", + "Feature Description": "Since dmode execs as mmode, and obi has corresponding signals, the relationship should be visible on obi.", + "Verification Goal": "When obi has a transaction with `dbg` high, check that `prot[2:1]` is M-mode on I-side, and \"effective\" mode on D-side.\n\nNote: Consider checking before MPU.\n\nCoverage: Observe U-/M-mode on D-side.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_iside\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_dside\n\nCOV: ???", + "Comment": "" + }, + { + "Requirement Location": "privspec", + "Feature": "CSRs", + "Sub Feature": "IllegalAccess", + "Feature Description": "\"Attempts to access a CSR without appropriate privilege level [\u2026] also raise illegal instruction exceptions\"", + "Verification Goal": "Try all kinds of accesses (R, W, RW, S, C, \u2026) to all M-level CSRs while in U-level; ensure illegal instruction exception happens.\n\n(Hint: Assert RVFI vs csr[9:8])\n\nFunctional coverage can do a full cross of modes vs all CSRs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_illegal_csr_access\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr\n\nDTC: cv32e40s/tests/programs/custom/csr_priv_gen_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "AccessLevel", + "Feature Description": "\"The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR.\"", + "Verification Goal": "Try all kinds of accesses to all implemented M-level and U-level CSRs while in M-mode and U-mode (cross), ensure appropriate access grant/deny.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Warl", + "Feature Description": "U-level CSRs may have WARL fields.", + "Verification Goal": "(There is only JVT, and must be handled by the Zc vplan. Link to cov here still.)", + "Pass/Fail Criteria": "Other", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for Zc vplan linkage" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MisaU", + "Feature Description": "\"The \u201cU\u201d and \u201cS\u201d bits will be set if there is support for user and supervisor modes respectively.\"", + "Verification Goal": "Read misa and see that \"U\" is always on.\n\nCoverage: Ensure actual csr read instruction read misa.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_misa_bits\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MisaN", + "Feature Description": "\"N Tentatively reserved for User-Level Interrupts extension\"", + "Verification Goal": "Read misa and see that \"N\" is always off.\n\nCoverage: Ensure actual csr read instruction read misa.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_misa_bits\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "UserExtensions", + "Feature Description": "\"If both XS and FS are hardwired to zero, then SD is also always zero.\"\n\n\"In systems without additional user extensions requiring new state, the XS field is hardwired to zero.\"\n\n\"If neither the F extension nor S-mode is implemented, then FS is hardwired to zero.\"\n\nNone of those 3 are implemented, so they should all be zero.", + "Verification Goal": "Check that mstatus {XS, FS, SD} are all 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_umode_extensions\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MscratchReliable", + "Feature Description": "\"the OS can rely on holding a value in the mscratch register while the user context\nis running.\"", + "Verification Goal": "Check that mscratch never changes in U-mode.\n\n(CLIC vplan must handle \"mscratchcsw\" and \"mscratchcswl\", but link to coverage of that here too.)\n\nCoverage: See that mscratch is attempted written from umode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mscratch_reliable\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mscratch_changing\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Mcsratchcsw", + "Feature Description": "The clic spec introduces \"conditional swapping\" of mscratch.", + "Verification Goal": "(Relevant user-mode related functionality must be handled by the CLIC vplan. Link to cov here still)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for CLIC vplan linkage." + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MppValues", + "Feature Description": "\"xPP fields are WARL fields that can hold only privilege mode x and any implemented privilege\nmode lower than x\"\n\n\"M-mode software can determine whether a privilege mode is implemented by writing that mode to MPP then reading it back.\"", + "Verification Goal": "Checking: Check that MPP can hold \"M\" and \"U\" and that it can hold nothing else.\n\nCoverage: Write and read instrs with each 2-bit permutation.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mpp_mode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mpp_umode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mpp_mmode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.gen_try_goto_mode[*].cov_try_goto_mode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.gen_try_goto_mode[*].cov_write_mpp", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "SppValues", + "Feature Description": "\"If privilege mode x is not implemented, then xPP must be hardwired to 0.\"", + "Verification Goal": "Check that SPP is always 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_spp_zero", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MedelegMideleg", + "Feature Description": "\"In systems without S-mode, the medeleg and mideleg registers should not exist.\"", + "Verification Goal": "Attempt access to these CSRs.\n\nCoverage: Instrs attempt (R/W) access.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_medeleg_mideleg\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Mcounteren", + "Feature Description": "\"In systems with U-mode, the mcounteren must be implemented\"", + "Verification Goal": "Attempt access to this CSR. (See Counters section below too.)\n\nCoverage: Instrs attempt (R/W) access.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mcounteren_access\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "n-ext", + "Feature": "CSRs", + "Sub Feature": "NExt", + "Feature Description": "N-extension CSRs used to be supported earlier in the legacy of the core's source code.", + "Verification Goal": "Check that the old N-ext CSRs are not accessible (ustatus, uie, utvec, uscratch, uepc, ucause, utval, uip), and traps upon access attempts.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_next_csrs\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "manual", + "Feature": "CSRs", + "Sub Feature": "Jvt", + "Feature Description": "The vector table jump CSR is accessible and effective in U-mode. \"Smstateen\" applies. Both CSR access and instruction execution is affected.", + "Verification Goal": "(Zc vplan should be responsible, but link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_jvt_access\n\nCOV: ???", + "Comment": "Waiting for Zc vplan linkage" + }, + { + "Requirement Location": "privspec", + "Feature": "Traps", + "Sub Feature": "SoftwareInterrupts", + "Feature Description": "U-mode software interrupts are not supported.", + "Verification Goal": "Check that the zero-bits in `mie` and `mip` are always zero, and mcause is never S/U-mode software interrupt.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromie\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromip\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_mcausemode\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "TrapMpp", + "Feature Description": "\"When a trap is taken from privilege mode y into privilege mode x, [\u2026] xPP is set to y.\"", + "Verification Goal": "Checking: Be in mode y, observe exception and interrupt, check MPP is mode y.\n\nCover: Cross U/M with Exc/Int.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_exception\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_general\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_debug\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mpp_excint", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherEnabled", + "Feature Description": "\"Interrupts for higher-privilege modes, y>x ,are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherDisable", + "Feature Description": "\"Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherNone", + "Feature Description": "\"A higher-privilege mode y could disable all of its interrupts before ceding control to a lower-privilege mode\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "LowerLevel", + "Feature Description": "\"Interrupts for lower-privilege modes, w