Imperas model not entering in debug mode with debug_haltreq

[pascalgouedo]

Type

Reference model/RTL mismatch.

Steps to Reproduce

1. git clone -b cv32e40p/dev --single-branch https://github.com/openhwgroup/core-v-verif core-v-verif
2. cd core-v-verif
3. git checkout 7693225
4. git clone -b dev --single-branch https://github.com/openhwgroup/cv32e40p core-v-cores/cv32e40p
5. cd core-v-cores/cv32e40p
6. git checkout bdd52534e28afa4aab4d549f26286355f8b075a8
7. cd ../../cv32e40p/sim/uvmt
8. Environment setup:
   OS: CentOS 7
   Siemens Questa Sim-64 vsim 2023.2_1
   Synopsys Model: imperas_idv/eng.20240530.0
   GNU GCC toolchain: corev-openhw-gcc-centos7-20240530
   setenv PATH <your_path>/core-v-verif/bin:$PATH
9. makeuvmt gen_corev-dv test TEST=corev_rand_pulp_instr_test CHECK_SIM_RESULT=YES CFG=pulp_fpu_2cyclat TEST_CFG_FILE=gen_rand_debug_req,floating_pt_instr_en SIMULATOR=vsim USE_ISS=yes COV=YES RUN_INDEX=894525592 GEN_START_INDEX=894525592 SEED=894525592
10. Logfile and/or wave-dump info (screen shots can be useful)

Info (IDV) Instruction executed prior to mismatch '0x80(_start+0): 0800006f j 100'
Error (IDV) PC mismatch (HartId:0, PC:0x00000100 _start_main+0):
Error (IDV) Mismatch 0>
Error (IDV) . dut:0x1a110800 debug_rom+0
Error (IDV) . ref:0x00000100 _start_main+0
Error (IDV) Insn. bit pattern mismatch (HartId:0, PC:0x00000100 _start_main+0):
Error (IDV) Mismatch 1>
Error (IDV) . dut:7b200073 dret
Error (IDV) . ref:408015b7 lui x11,0x40801
Error (IDV) GPR register value mismatch (HartId:0, PC:0x00000100 _start_main+0):
Error (IDV) Mismatch 2> GPR x11
Error (IDV) . dut:0x00000000 (not updated)
Error (IDV) . ref:0x40801000
Error (IDV) CSR register value mismatch (HartId:0, PC:0x00000100 _start_main+0):
Error (IDV) Mismatch 3> CSR 7b0 (dcsr)
Error (IDV) . dut:0x400000c3 debugver:4 ebreakm:0 stepie:0 stopcount:0 stoptime:0 cause:3(haltreq) mprven:0 nmip:0 step:0 prv:3(M-mode)
Error (IDV) . ref:0x40000003 debugver:4 ebreakm:0 stepie:0 stopcount:0 stoptime:0 cause:0 mprven:0 nmip:0 step:0 prv:3(M-mode) (not updated)
Error (IDV) Mismatch 4> CSR 7b1 (dpc)
Error (IDV) . dut:0x00000100
Error (IDV) . ref:0x00000000 (not updated)
UVM_ERROR @ 336.300 ns : idvPkg.sv(55) reporter [] uvmt_cv32e40p_tb.imperas_dv.trace2api.state_compare @ 336.000 ns: MISMATCH

Analysis

CV32E40Pv2 boots and executes the first jump instruction.
Then there is a debug request so the core goes to debug mode with dcsr.cause = 3.
The model is not going in executing debugger rom code and is expecting dcsr.cause = 0.
debugger code is just a dret so the core immediately goes back to normal running mode.

Analysis from Synopsys

It looks as though the haltreq is getting consumed by some additional processing that is done at time zero; actually on the first instruction retirement.
Analysis on-going on Synopsys R&D side.