DCache组织结构为2路组相联,2x4K,一个cacheline大小为16byte,替代算法用的伪lru算法,组织结构为->data域:256x32的sram8块,TAGV域:256x21的sram两块,LRU:256x1的regfile一块
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out-of-order55/DCache
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2 way|PLRU|2*4k
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