add le patches in split form

patch/kernel/archive/rockchip64-6.3/0001-phy-rockchip-inno-hdmi-use-correct-vco_div_5-macro-o.patch

@@ -0,0 +1,35 @@
+From e5920d1c066177c2cc8c324736f43bfb59b6598d Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 10 Oct 2020 15:32:18 +0000
+Subject: [PATCH 01/46] phy/rockchip: inno-hdmi: use correct vco_div_5 macro on
+ rk3328
+
+inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro
+when configuring vco_div_5 on RK3328.
+
+Fix this by using correct vco_div_5 macro for RK3328.
+
+Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 80acca4e9e14..15339338aae3 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -790,8 +790,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
+ 			 RK3328_PRE_PLL_POWER_DOWN);
+
+ 	/* Configure pre-pll */
+-	inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK,
+-			 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
++	inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
++			 RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
+ 	inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
+
+ 	val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
+-- 
+2.34.1
+

patch/kernel/archive/rockchip64-6.3/0002-phy-rockchip-inno-hdmi-round-fractal-pixclock-in-rk3.patch

@@ -0,0 +1,44 @@
+From 36e6c2d6005714145dd19fb98c38179faed4892c Mon Sep 17 00:00:00 2001
+From: Zheng Yang <zhengyang@rock-chips.com>
+Date: Sat, 10 Oct 2020 15:32:18 +0000
+Subject: [PATCH 02/46] phy/rockchip: inno-hdmi: round fractal pixclock in
+ rk3328 recalc_rate
+
+inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found
+in the pre pll config table when the fractal divider is used.
+This can prevent proper power_on because a tmdsclock for the new rate
+is not found in the pre pll config table.
+
+Fix this by saving and returning a rounded pixel rate that exist
+in the pre pll config table.
+
+Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
+Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 15339338aae3..15a008a1ac7b 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
+ 		do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
+ 	}
+
+-	inno->pixclock = vco;
+-	dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
++	inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
+
+-	return vco;
++	dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
++		__func__, inno->pixclock, vco);
++
++	return inno->pixclock;
+ }
+
+ static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
+-- 
+2.34.1
+

patch/kernel/archive/rockchip64-6.3/0003-phy-rockchip-inno-hdmi-remove-unused-no_c-from-rk332.patch

@@ -0,0 +1,39 @@
+From 5237d5d5b27ad2ddad98bbf0f19df6fbb7b8750d Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 10 Oct 2020 15:32:19 +0000
+Subject: [PATCH 03/46] phy/rockchip: inno-hdmi: remove unused no_c from rk3328
+ recalc_rate
+
+no_c is not used in any calculation, lets remove it.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 15a008a1ac7b..4b936ca19920 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
+ {
+ 	struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
+ 	unsigned long frac;
+-	u8 nd, no_a, no_b, no_c, no_d;
++	u8 nd, no_a, no_b, no_d;
+ 	u64 vco;
+ 	u16 nf;
+
+@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
+ 		no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
+ 		no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
+ 		no_b += 2;
+-		no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
+-		no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
+-		no_c = 1 << no_c;
+ 		no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
+
+ 		do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
+-- 
+2.34.1
+

patch/kernel/archive/rockchip64-6.3/0004-phy-rockchip-inno-hdmi-do-not-power-on-rk3328-post-p.patch

@@ -0,0 +1,49 @@
+From 9d317b7bb03fd88756310d53691f148d77645cc8 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 10 Oct 2020 15:32:19 +0000
+Subject: [PATCH 04/46] phy/rockchip: inno-hdmi: do not power on rk3328 post
+ pll on reg write
+
+inno_write is used to configure 0xaa reg, that also hold the
+POST_PLL_POWER_DOWN bit.
+When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not
+taken into consideration.
+
+Fix this by keeping the power down bit until configuration is complete.
+Also reorder the reg write order for consistency.
+
+Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 4b936ca19920..620961fcfc1d 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
+
+ 	inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
+ 	if (cfg->postdiv == 1) {
+-		inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);
+ 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
+ 			   RK3328_POST_PLL_PRE_DIV(cfg->prediv));
++		inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
++			   RK3328_POST_PLL_POWER_DOWN);
+ 	} else {
+ 		v = (cfg->postdiv / 2) - 1;
+ 		v &= RK3328_POST_PLL_POST_DIV_MASK;
+@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
+ 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
+ 			   RK3328_POST_PLL_PRE_DIV(cfg->prediv));
+ 		inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
+-			   RK3328_POST_PLL_REFCLK_SEL_TMDS);
++			   RK3328_POST_PLL_REFCLK_SEL_TMDS |
++			   RK3328_POST_PLL_POWER_DOWN);
+ 	}
+
+ 	for (v = 0; v < 14; v++)
+-- 
+2.34.1
+

patch/kernel/archive/rockchip64-6.3/0005-phy-rockchip-inno-hdmi-force-set_rate-on-power_on.patch

@@ -0,0 +1,90 @@
+From be0ad42413b10b01f11230d8a1a0dca84c5b3026 Mon Sep 17 00:00:00 2001
+From: Huicong Xu <xhc@rock-chips.com>
+Date: Sat, 10 Oct 2020 15:32:20 +0000
+Subject: [PATCH 05/46] phy/rockchip: inno-hdmi: force set_rate on power_on
+
+Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and
+not in pixel clock rate.
+When the hdmiphy clock is configured with the same pixel clock rate using
+clk_set_rate() the clock framework do not signal the hdmi phy driver
+to set_rate when switching between 8-bit and Deep Color.
+This result in pre/post pll not being re-configured when switching between
+regular 8-bit and Deep Color video formats.
+
+Fix this by calling set_rate in power_on to force pre pll re-configuration.
+
+Signed-off-by: Huicong Xu <xhc@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index 620961fcfc1d..2f01259823ea 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -245,6 +245,7 @@ struct inno_hdmi_phy {
+ 	struct clk_hw hw;
+ 	struct clk *phyclk;
+ 	unsigned long pixclock;
++	unsigned long tmdsclock;
+ };
+
+ struct pre_pll_config {
+@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
+
+ 	dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
+
++	inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
++
+ 	ret = clk_prepare_enable(inno->phyclk);
+ 	if (ret)
+ 		return ret;
+@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy)
+
+ 	clk_disable_unprepare(inno->phyclk);
+
++	inno->tmdsclock = 0;
++
+ 	dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
+
+ 	return 0;
+@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
+ 	dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
+ 		__func__, rate, tmdsclock);
+
++	if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
++		return 0;
++
+ 	cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
+ 	if (IS_ERR(cfg))
+ 		return PTR_ERR(cfg);
+@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
+ 	}
+
+ 	inno->pixclock = rate;
++	inno->tmdsclock = tmdsclock;
+
+ 	return 0;
+ }
+@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
+ 	dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
+ 		__func__, rate, tmdsclock);
+
++	if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
++		return 0;
++
+ 	cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
+ 	if (IS_ERR(cfg))
+ 		return PTR_ERR(cfg);
+@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
+ 	}
+
+ 	inno->pixclock = rate;
++	inno->tmdsclock = tmdsclock;
+
+ 	return 0;
+ }
+-- 
+2.34.1
+

patch/kernel/archive/rockchip64-6.3/0006-drm-drm_fourcc-add-NV20-and-NV30-YUV-formats.patch

@@ -0,0 +1,60 @@
+From c53a1a1f8edea0aaab0f7605f1bd3bde0921993f Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 6 Jul 2020 22:30:13 +0000
+Subject: [PATCH 06/46] drm: drm_fourcc: add NV20 and NV30 YUV formats
+
+DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
+variant of NV15, a 10-bit 2-plane YUV format that has no padding between
+components. Instead, luminance and chrominance samples are grouped into 4s
+so that each group is packed into an integer number of bytes:
+
+YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
+
+The '20' and '30' suffix refers to the optimum effective bits per pixel
+which is achieved when the total number of luminance samples is a multiple
+of 4.
+
+V2: Added NV30 format
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Sandy Huang <hjc@rock-chips.com>
+---
+ drivers/gpu/drm/drm_fourcc.c  | 8 ++++++++
+ include/uapi/drm/drm_fourcc.h | 2 ++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
+index 0f17dfa8702b..193cf8ed7912 100644
+--- a/drivers/gpu/drm/drm_fourcc.c
++++ b/drivers/gpu/drm/drm_fourcc.c
+@@ -299,6 +299,14 @@ const struct drm_format_info *__drm_format_info(u32 format)
+ 		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
+ 		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
+ 		  .vsub = 2, .is_yuv = true },
++		{ .format = DRM_FORMAT_NV20,		.depth = 0,
++		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
++		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
++		  .vsub = 1, .is_yuv = true },
++		{ .format = DRM_FORMAT_NV30,		.depth = 0,
++		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
++		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
++		  .vsub = 1, .is_yuv = true },
+ 		{ .format = DRM_FORMAT_Q410,		.depth = 0,
+ 		  .num_planes = 3, .char_per_block = { 2, 2, 2 },
+ 		  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 1,
+diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
+index de703c6be969..13f8e4250382 100644
+--- a/include/uapi/drm/drm_fourcc.h
++++ b/include/uapi/drm/drm_fourcc.h
+@@ -323,6 +323,8 @@ extern "C" {
+  * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
+  */
+ #define DRM_FORMAT_NV15		fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
++#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
++#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
+
+ /*
+  * 2 plane YCbCr MSB aligned
+-- 
+2.34.1
+