diff --git a/.gitignore b/.gitignore index a6e3eaaf992..f60eba4d2cd 100644 --- a/.gitignore +++ b/.gitignore @@ -24,6 +24,8 @@ payloads/external/U-Boot/u-boot/ payloads/external/Memtest86Plus/memtest86plus/ payloads/external/iPXE/ipxe/ payloads/external/sortbootorder/sortbootorder +payloads/external/linux/linux/ +payloads/external/u-root/uroot/ util/crossgcc/acpica-unix-*/ util/crossgcc/binutils-*/ util/crossgcc/build-*BINUTILS/ diff --git a/.gitmodules b/.gitmodules index 84cbf40ee3a..de4b4f52a5b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -42,3 +42,7 @@ url = https://review.coreboot.org/amd_blobs.git update = none ignore = dirty +[submodule "payloads/external/landing-zone"] + path = payloads/external/landing-zone + url = https://github.com/TrenchBoot/landing-zone.git + diff --git a/configs/config.pcengines_apu2.tb b/configs/config.pcengines_apu2.tb new file mode 100644 index 00000000000..2e7b0355f7f --- /dev/null +++ b/configs/config.pcengines_apu2.tb @@ -0,0 +1,14 @@ +CONFIG_LOCALVERSION="v4.10.0.2" +CONFIG_VENDOR_PCENGINES=y +CONFIG_FMDFILE="$(top)/src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" +CONFIG_VBOOT=y +CONFIG_BOARD_PCENGINES_APU2=y +CONFIG_NO_GFX_INIT=y +CONFIG_VBOOT_MEASURED_BOOT=y +CONFIG_USER_TPM2=y +CONFIG_PAYLOAD_GRUB2=y +CONFIG_GRUB2_REVISION=y +CONFIG_GRUB2_INCLUDE_RUNTIME_CONFIG_FILE=y +CONFIG_GRUB2_TRENCHBOOT_DRTM=y +CONFIG_GRUB2_INCLUDE_UROOT=y +CONFIG_GRUB2_REVISION_ID="origin/trenchboot_support_2.04" diff --git a/configs/config.pcengines_apu2_tb_ipxe b/configs/config.pcengines_apu2_tb_ipxe new file mode 100644 index 00000000000..6115be052d0 --- /dev/null +++ b/configs/config.pcengines_apu2_tb_ipxe @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="v4.11.0.1" +CONFIG_VENDOR_PCENGINES=y +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" +CONFIG_BOARD_PCENGINES_APU2=y +CONFIG_PXE_ROM_ID="8086,157b" +CONFIG_NO_GFX_INIT=y +CONFIG_USER_TPM2=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +CONFIG_SEABIOS_REVISION=y +CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3" +CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_LZ=y +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_PXE_CUSTOM_BUILD_ID="12345678" +CONFIG_PXE_ADD_SCRIPT=y +CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe" +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y +CONFIG_MEMTEST_REVISION=y +CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753" diff --git a/grub.cfg b/grub.cfg new file mode 100644 index 00000000000..29977a56f14 --- /dev/null +++ b/grub.cfg @@ -0,0 +1,10 @@ +set debug=linux +serial --speed=115200 --word=8 --parity=no --stop=1 +terminal_input --append serial +terminal_output --append serial + +linux (cbfsdisk)/bzImage console=ttyS0,115200 earlyprintk=serial,ttyS0,115200 +initrd (cbfsdisk)/initrd +slaunch skinit +slaunch_module (cbfsdisk)/lz_header +boot diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index 8e88614f75e..5bd5c020f41 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -38,6 +38,8 @@ payloads/external/tianocore \ payloads/external/GRUB2 \ payloads/external/LinuxBoot \ payloads/external/Yabits \ +payloads/external/linux \ +payloads/external/u-root \ payloads/coreinfo/build/coreinfo.elf coreinfo: $(MAKE) -C payloads/coreinfo defaultbuild diff --git a/payloads/external/GRUB2/Kconfig b/payloads/external/GRUB2/Kconfig index 552f06a5238..77c2a55863d 100644 --- a/payloads/external/GRUB2/Kconfig +++ b/payloads/external/GRUB2/Kconfig @@ -28,12 +28,14 @@ endchoice config GRUB2_REVISION_ID string "Insert a commit's SHA-1 or a branch name" depends on GRUB2_REVISION + default "origin/move_header" if GRUB2_TRENCHBOOT_DRTM default "origin/master" help The commit's SHA-1 or branch name of the revision to use. config GRUB2_EXTRA_MODULES string "Extra modules to include in GRUB image" + default "slaunch" if GRUB2_TRENCHBOOT_DRTM help Space-separated list of additional modules to include. Few common ones: @@ -71,4 +73,18 @@ config GRUB2_RUNTIME_CONFIG_FILE help The path of the GRUB2 runtime configuration file to be added to CBFS. +config GRUB2_TRENCHBOOT_DRTM + bool "Add TrenchBoot DRTM support" + depends on PAYLOAD_GRUB2 + default n + help + Enable Trenchboot DRTM extensions in GRUB2 and build LandingZone binary that will be included in CBFS. + +config GRUB2_INCLUDE_UROOT + bool "Include u-root binaries" + depends on GRUB2_TRENCHBOOT_DRTM + default no + help + Include Linux kernel with u-root initrd. + endif diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index f13c12892aa..db7b5a1bebf 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -5,7 +5,7 @@ NAME-$(CONFIG_GRUB2_MASTER)=HEAD NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID) NAME-$(CONFIG_GRUB2_STABLE)=2.04 -project_git_repo=https://git.savannah.gnu.org/git/grub.git/ +project_git_repo=https://github.com/3mdeb/grub.git project_dir=grub2 unexport HOSTCC CC LD OBJCOPY STRIP @@ -13,23 +13,33 @@ MAKEOVERRIDES := all: grub2 -checkout: - echo " GIT GRUB2 $(NAME-y)" - test -d $(project_dir) || git clone $(project_git_repo) $(project_dir) - git -C $(project_dir) fetch -ifeq ("$(shell test -d $(project_dir) && \ - (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain))",) - git -C $(project_dir) checkout -f $(TAG-y) -else - echo "WARNING: index/tree not clean, skipping update / force checkout." - echo " Checkout manually with `git -C $(project_dir) checkout -f`." +clone: + echo " Cloning GRUB2 from Git" + git clone $(project_git_repo) $(project_dir) + +fetch: clone +ifeq ($(TAG-y),) + echo "Error: The specified tag is invalid" +ifeq ($(CONFIG_GRUB2_REVISION),y) + echo "Error: There is no revision specified for GRUB2" + false +endif + false endif + cd grub2; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ] || \ + [ "$(TAG-y)" = "origin/master" ]; then \ + echo " Fetching new commits from the GRUB2 git repo"; \ + git fetch; fi + +checkout: fetch + echo " Checking out GRUB2 revision $(TAG-y)" + cd grub2; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) grub2/build/config.h: $(CONFIG_DEP) | checkout echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./bootstrap ; ./autogen.sh + cd grub2 && ./bootstrap && ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 1f0af021fe2..3dda8acadfd 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -223,8 +223,40 @@ grub2: $(obj)/config.h CONFIG_GRUB2_REVISION_ID=$(CONFIG_GRUB2_REVISION_ID) \ CONFIG_GRUB2_EXTRA_MODULES=$(CONFIG_GRUB2_EXTRA_MODULES) +lzheader: + $(MAKE) -C payloads/external/landing-zone \ + CC="$(HOSTCC)" + +linux: + $(MAKE) -C payloads/external/linux + +uroot: + $(MAKE) -C payloads/external/u-root + payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 +ifneq ($(CONFIG_GRUB2_TRENCHBOOT_DRTM),) +payloads/external/landing-zone/lz_header.bin: lzheader +cbfs-files-y += lz_header +lz_header-file := payloads/external/landing-zone/lz_header.bin +lz_header-type := raw +endif + +ifneq ($(CONFIG_GRUB2_INCLUDE_UROOT),) +payloads/external/linux/linux/bzImage: linux +payloads/external/u-root/uroot/initramfs.cpio.lzma: uroot + +cbfs-files-y += bzImage +bzImage-file := payloads/external/linux/linux/bzImage +bzImage-type := raw +bzImage-compression := none + +cbfs-files-y += initrd +initrd-file := payloads/external/u-root/uroot/initramfs.cpio.lzma +initrd-type := raw +initrd-compression := none +endif + # U-Boot payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) @@ -321,6 +353,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT) PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \ CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \ CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \ + CONFIG_IPXE_LZ=$(CONFIG_IPXE_LZ) \ CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \ IPXE_UART=$(IPXE_UART) \ CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \ diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index 807aa48fa92..beaf2ad696e 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -54,6 +54,11 @@ config IPXE_MASTER help Newest iPXE version. +config IPXE_LZ + bool "landing_zone" + help + iPXE with support for TrenchBoot's Landing Zone. + endchoice config PXE_ROM_FILE diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 8a6cda5275c..374ea91d8fc 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -19,10 +19,15 @@ STABLE_COMMIT_ID=ebf2eaf515e46abd43bc798e7e4ba77bfe529218 TAG-$(CONFIG_IPXE_MASTER)=origin/master TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID) +TAG-$(CONFIG_IPXE_LZ)=origin/landing_zone project_name=iPXE project_dir=ipxe +ifeq ($(CONFIG_IPXE_LZ),y) +project_git_repo=https://github.com/3mdeb/ipxe.git +else project_git_repo=https://git.ipxe.org/ipxe.git +endif unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG diff --git a/payloads/external/landing-zone b/payloads/external/landing-zone new file mode 160000 index 00000000000..3312de3ba7e --- /dev/null +++ b/payloads/external/landing-zone @@ -0,0 +1 @@ +Subproject commit 3312de3ba7e6379fdbb5c6d0b9dbc5dcf321a4e7 diff --git a/payloads/external/linux/Makefile b/payloads/external/linux/Makefile new file mode 100644 index 00000000000..7a7b68c0afc --- /dev/null +++ b/payloads/external/linux/Makefile @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +project_name=Linux +project_dir=$(CURDIR)/linux +project_git_repo=https://github.com/3mdeb/linux-stable.git +project_git_branch=linux-sl-5.1-sha2-amd + +unexport $(COREBOOT_EXPORTS) + +all: build + +$(project_dir): + echo " Cloning $(project_name) from Git" + git clone $(project_git_repo) $(project_dir) --depth=1 -b $(project_git_branch) + +build: $(project_dir) + echo " MAKE $(project_name)" + cp $(CURDIR)/linux_defconfig-5.1 $(project_dir)/.config + $(MAKE) -C $(project_dir) olddefconfig V=1 + $(MAKE) -C $(project_dir) bzImage V=1 + cp $(project_dir)/arch/x86/boot/bzImage $(project_dir)/bzImage + +clean: + test -d $(project_dir) && rm $(project_dir)/bzImage || exit 0 + test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0 + +distclean: + rm -rf $(project_dir) + +print-repo-info: + echo "$(project_git_repo) $(project_dir)" + +.PHONY: all build clean distclean print-repo-info diff --git a/payloads/external/linux/linux_defconfig b/payloads/external/linux/linux_defconfig new file mode 100644 index 00000000000..95737d5a46f --- /dev/null +++ b/payloads/external/linux/linux_defconfig @@ -0,0 +1,125 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZMA=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_PERF=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_MULTIUSER is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_FHANDLE is not set +# CONFIG_POSIX_TIMERS is not set +# CONFIG_BUG is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_BASE_FULL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_MEMBARRIER is not set +# CONFIG_KALLSYMS is not set +# CONFIG_RSEQ is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_ZONE_DMA is not set +CONFIG_SMP=y +# CONFIG_RETPOLINE is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +# CONFIG_SCHED_OMIT_FRAME_POINTER is not set +# CONFIG_DMI is not set +# CONFIG_X86_MCE is not set +# CONFIG_MICROCODE is not set +CONFIG_X86_MSR=y +CONFIG_X86_CPUID=y +# CONFIG_MTRR is not set +# CONFIG_ARCH_RANDOM is not set +# CONFIG_X86_SMAP is not set +# CONFIG_X86_INTEL_UMIP is not set +CONFIG_SECURE_LAUNCH_STUB=y +# CONFIG_SECCOMP is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +# CONFIG_RELOCATABLE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk=serial,ttyS0,115200" +# CONFIG_MODIFY_LDT_SYSCALL is not set +# CONFIG_SUSPEND is not set +CONFIG_ISA_BUS=y +# CONFIG_VIRTUALIZATION is not set +# CONFIG_STACKPROTECTOR is not set +# CONFIG_COREDUMP is not set +# CONFIG_COMPACTION is not set +CONFIG_DEVTMPFS=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS=y +CONFIG_TCG_CRB=y +CONFIG_I2C=y +CONFIG_SPI=y +# CONFIG_HWMON is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PCI=y +CONFIG_MMC_SDHCI_ACPI=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_EXT4_FS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_VFAT_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_XZ_DEC=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_DOUBLEFAULT is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_X86_DEBUG_FPU is not set +CONFIG_UNWINDER_GUESS=y diff --git a/payloads/external/linux/linux_defconfig-5.1 b/payloads/external/linux/linux_defconfig-5.1 new file mode 100644 index 00000000000..f7ba8a0f489 --- /dev/null +++ b/payloads/external/linux/linux_defconfig-5.1 @@ -0,0 +1,134 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZMA=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_MULTIUSER is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_FHANDLE is not set +# CONFIG_POSIX_TIMERS is not set +# CONFIG_BUG is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_BASE_FULL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_MEMBARRIER is not set +# CONFIG_KALLSYMS is not set +# CONFIG_RSEQ is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_ZONE_DMA is not set +CONFIG_SMP=y +# CONFIG_RETPOLINE is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +# CONFIG_SCHED_OMIT_FRAME_POINTER is not set +# CONFIG_DMI is not set +# CONFIG_X86_MCE is not set +# CONFIG_MICROCODE is not set +CONFIG_X86_MSR=y +CONFIG_X86_CPUID=y +# CONFIG_MTRR is not set +# CONFIG_ARCH_RANDOM is not set +# CONFIG_X86_SMAP is not set +# CONFIG_X86_INTEL_UMIP is not set +CONFIG_SECURE_LAUNCH=y +# CONFIG_SECCOMP is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +# CONFIG_RELOCATABLE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk=serial,ttyS0,115200" +# CONFIG_MODIFY_LDT_SYSCALL is not set +# CONFIG_SUSPEND is not set +CONFIG_ISA_BUS=y +# CONFIG_VIRTUALIZATION is not set +# CONFIG_STACKPROTECTOR is not set +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_COREDUMP is not set +# CONFIG_COMPACTION is not set +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +CONFIG_DEVTMPFS=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS=y +CONFIG_TCG_CRB=y +CONFIG_I2C=y +CONFIG_SPI=y +# CONFIG_HWMON is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_EXT4_FS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_VFAT_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_CRYPTO_SHA1_SSSE3=y +# CONFIG_CRYPTO_HW is not set +CONFIG_XZ_DEC=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_DOUBLEFAULT is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_X86_DEBUG_FPU is not set +CONFIG_UNWINDER_GUESS=y diff --git a/payloads/external/sortbootorder/Makefile b/payloads/external/sortbootorder/Makefile index dd922d7020e..3e3a443cbcf 100644 --- a/payloads/external/sortbootorder/Makefile +++ b/payloads/external/sortbootorder/Makefile @@ -28,24 +28,24 @@ ifeq ($(SORTBOOTORDER_REVISION),y) endif false endif - cd sortbootorder; git show $(TAG-y) >/dev/null 2>&1 ; \ + cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \ if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \ echo " Fetching new commits from the sortbootorder repo"; \ git fetch; fi checkout: fetch echo " Checking out sortbootorder revision $(TAG-y)" - cd sortbootorder; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) build: checkout echo " MAKE sortbootorder" - $(MAKE) -C sortbootorder VERSION=$(TAG-y) APU1=$(TARGET_APU1) + $(MAKE) -C $(project_dir) VERSION=$(TAG-y) APU1=$(TARGET_APU1) clean: - test -d sortbootorder && $(MAKE) -C sortbootorder clean || exit 0 + test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0 distclean: - rm -rf sortbootorder + rm -rf $(project_dir) print-repo-info: echo "$(project_git_repo) $(project_dir)" diff --git a/payloads/external/u-root/0001-examples-uinit-uinit.go-automate-Xen-launch.patch b/payloads/external/u-root/0001-examples-uinit-uinit.go-automate-Xen-launch.patch new file mode 100644 index 00000000000..f36828df528 --- /dev/null +++ b/payloads/external/u-root/0001-examples-uinit-uinit.go-automate-Xen-launch.patch @@ -0,0 +1,34 @@ +From 668ebbc3fcf525c42a09cbcc1797f05f144adea1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Sat, 28 Sep 2019 17:09:30 +0200 +Subject: [PATCH] examples/uinit/uinit.go: automate Xen launch +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Michał Żygowski +--- + examples/uinit/uinit.go | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/examples/uinit/uinit.go b/examples/uinit/uinit.go +index b0075daf..6bafa4d6 100644 +--- a/examples/uinit/uinit.go ++++ b/examples/uinit/uinit.go +@@ -14,10 +14,9 @@ import ( + + var ( + commands = []string{ +- "/bbin/date", +- "/bbin/dhclient -ipv6=false", +- "/bbin/ip a", +- "/bbin/elvish", ++ "/bbin/mount -t ext4 /dev/sda1 /var", ++ "/bbin/kexec -l -c \"dom0_mem=512M loglvl=all guest_loglvl=all com1=115200,8n1 console=com1 no-real-mode\" --module \"/var/bzImage console=hvc0 earlyprintk=xen nomodeset root=/dev/sda2\" /var/xen.gz", ++ "/bbin/kexec -e", + "/bbin/shutdown halt", + } + ) +-- +2.20.1 + diff --git a/payloads/external/u-root/Makefile b/payloads/external/u-root/Makefile new file mode 100644 index 00000000000..d596ecdbdc3 --- /dev/null +++ b/payloads/external/u-root/Makefile @@ -0,0 +1,50 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +project_name=uroot +project_dir=$(CURDIR)/uroot +project_git_repo=github.com/u-root/u-root + +export GOPATH:=$(CURDIR)/uroot +export PATH:=/usr/local/go/bin:$(GOPATH)/bin:$(PATH) + +all: build + +$(project_dir): + echo " Cloning $(project_name) with Go" + mkdir $(project_dir) + go get $(project_git_repo) + go get github.com/3mdeb/uinit + +build: $(project_dir) + cd $(project_dir)/src/$(project_git_repo) ; \ + u-root -defaultsh="" -format=cpio -o $(project_dir)/initramfs.cpio -build=bb \ + $(project_git_repo)/cmds/core/init \ + $(project_git_repo)/cmds/core/kexec \ + $(project_git_repo)/cmds/core/mount \ + github.com/3mdeb/uinit + cd $(project_dir) + lzma -f -k $(project_dir)/initramfs.cpio + +clean: + test -d $(project_dir) && rm $(project_dir)/initramfs.cpio* || exit 0 + +distclean: + rm -rf $(project_dir) + +print-repo-info: + echo "$(project_git_repo) $(project_dir)" + +.PHONY: all build clean distclean print-repo-info diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 68475c157e4..1caa841b9ad 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -274,9 +274,6 @@ typedef struct acpi_vfct { acpi_vfct_image_hdr_t image_hdr; } __packed acpi_vfct_t; -typedef struct acpi_ivrs_info { -} __packed acpi_ivrs_info_t; - /* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 10h */ typedef struct acpi_ivrs_ivhd { uint8_t type; @@ -284,15 +281,44 @@ typedef struct acpi_ivrs_ivhd { uint16_t length; uint16_t device_id; uint16_t capability_offset; - uint32_t iommu_base_low; - uint32_t iommu_base_high; + uint32_t iommu_base_lo; + uint32_t iommu_base_hi; uint16_t pci_segment_group; uint16_t iommu_info; uint32_t iommu_feature_info; uint8_t entry[0]; } __packed acpi_ivrs_ivhd_t; -/* IVRS (I/O Virtualization Reporting Structure) Type 10h */ +/* IVHD Type 11h IOMMU Attributes */ + +typedef struct ivhd11_iommu_attr { + uint32_t reserved1 : 13; + uint32_t perf_counters : 4; + uint32_t perf_counter_banks : 6; + uint32_t msi_num_ppr : 5; + uint32_t reserved2 : 4; +} __packed ivhd11_iommu_attr_t; + +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 11h */ +typedef struct acpi_ivrs_ivhd_11 { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_lo; + uint32_t iommu_base_hi; + uint16_t pci_segment_group; + uint16_t iommu_info; + struct ivhd11_iommu_attr iommu_attributes; + uint32_t efr_reg_image_lo; + uint32_t efr_reg_image_hi; + uint32_t reserved[2]; + uint8_t entry[0]; +} __packed acpi_ivrs_ivhd11_t; + + +/* IVRS (I/O Virtualization Reporting Structure) */ typedef struct acpi_ivrs { acpi_header_t header; uint32_t iv_info; @@ -300,6 +326,60 @@ typedef struct acpi_ivrs { struct acpi_ivrs_ivhd ivhd; } __packed acpi_ivrs_t; +/* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ +typedef struct ivrs_ivhd_generic { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; +} __packed ivrs_ivhd_generic_t; + +enum ivhd_generic_type { + IVHD_GENERIC_RESERVED = 0, + IVHD_GENERIC_ALL = 1, + IVHD_GENERIC_SELECT = 2, + IVHD_GENERIC_START_OF_RANGE = 3, + IVHD_GENERIC_END_OF_RANGE =4 +}; + +/* IVHD (I/O Virtualization Hardware Definition Block) 8-byte entries */ +typedef struct ivrs_ivhd_alias { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint8_t reserved1; + uint16_t source_dev_id; + uint8_t reserved2; +} __packed ivrs_ivhd_alias_t; + +typedef struct ivrs_ivhd_extended { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint32_t extended_dte_setting; +} __packed ivrs_ivhd_extended_t; + +typedef struct ivrs_ivhd_special { + uint8_t type; + uint16_t reserved; + uint8_t dte_setting; + uint8_t handle; + uint16_t source_dev_id; + uint8_t variety; +} __packed ivrs_ivhd_special_t; + +enum ivhd_extended_type { + IVHD_ALIAS_SELECT = 0x42, + IVHD_ALIAST_START_OF_RANGE = 0x43, + IVHD_EXTENDED_SELECT = 0x46, + IVHD_EXTENDED_START_OF_RANGE = 0x47, + IVHD_SPECIAL_DEVICE = 0x48 +}; + +enum ivhd_special_device_variety { + IVHD_VARIETY_IOAPIC = 0x01, + IVHD_VARIETY_HPET = 0x02 +}; + enum dev_scope_type { SCOPE_PCI_ENDPOINT = 1, SCOPE_PCI_SUB = 2, diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index a35ef83d2c0..0c8e9c35098 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -896,11 +896,16 @@ static void lpc_tpm_fill_ssdt(struct device *dev) acpigen_write_scope(path); acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0C31"); - - acpigen_write_name("_CID"); - acpigen_emit_eisaid("PNP0C31"); + if (CONFIG(TPM2)) { + acpigen_write_name_string("_HID", "MSFT0101"); + acpigen_write_name_string("_CID", "MSFT0101"); + } else { + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0C31"); + + acpigen_write_name("_CID"); + acpigen_emit_eisaid("PNP0C31"); + } acpi_device_write_uid(dev); diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 6390c31d01e..7aedf8c1028 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #include static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -35,6 +37,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; @@ -159,3 +162,70 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_SUCCESS; } + +/* PCIE slot reset control */ +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + PCIe_SLOT_RESET_INFO *ResetInfo; + uint32_t GpioData; + uint8_t GpioValue; + + ResetInfo = ConfigPtr; + Status = AGESA_UNSUPPORTED; + + switch (ResetInfo->ResetId) + { + /* + * ResetID 1 = PCIE_RST# affects all PCIe slots on all boards except + * apu2. It uses no GPIO + */ + case 1: Status = AGESA_SUCCESS; break; + case 51: /* GPIO51 resets mPCIe1 slot on apu2 */ + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + GpioData = gpio1_read32(0x8); + printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xa); + GpioValue &= ~BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + GpioData = gpio1_read32(0x8); + printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xa); + GpioValue |= BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + } + break; + case 55: /* GPIO51 resets mPCIe2 slot on apu2 */ + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + GpioData = gpio1_read32(0xc); + printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xe); + GpioValue &= ~BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + GpioData = gpio1_read32(0xc); + printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n", + __func__, ResetInfo->ResetId, GpioData); + GpioValue = gpio1_read8(0xe); + GpioValue |= BIT6; + gpio1_write8(0xa, GpioValue); + Status = AGESA_SUCCESS; + break; + } + break; + } + + return Status; +} diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index b3bdc3b8225..2f51f8e783f 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -35,6 +35,10 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH_WINBOND select MAINBOARD_HAS_LPC_TPM select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 67e6f42426c..196ff4b5876 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -20,6 +20,16 @@ #include #include +#define PCIE_NIC_RESET_ID 1 + +#if CONFIG(BOARD_PCENGINES_APU2) +#define PCIE_GFX_RESET_ID 55 +#define PCIE_PORT3_RESET_ID 51 +#else +#define PCIE_GFX_RESET_ID PCIE_NIC_RESET_ID +#define PCIE_PORT3_RESET_ID PCIE_NIC_RESET_ID +#endif + static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -28,7 +38,8 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x01, 0) + AspmL0sL1, PCIE_PORT3_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -38,7 +49,8 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x02, 0) + AspmL0sL1, PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -48,7 +60,8 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x03, 0) + AspmL0sL1, PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -58,7 +71,8 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x04, 0) + AspmL0sL1, PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -68,7 +82,8 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x05, 0) + AspmL0sL1, PCIE_GFX_RESET_ID, + ClkPmSupportEnabled) } }; diff --git a/src/mainboard/pcengines/apu2/board.fmd b/src/mainboard/pcengines/apu2/board.fmd new file mode 100644 index 00000000000..dd4b842be57 --- /dev/null +++ b/src/mainboard/pcengines/apu2/board.fmd @@ -0,0 +1,18 @@ +FLASH 8M { + SI_BIOS@0x0 0x800000 { + MISC_RW@0x0 0xa0000 { + RW_UNUSED@0x0 0x20000 + PSPDIR@0x20000 0x80000 + } + WP_RO@0xa0000 0x760000{ + RO_VPD@0x0 0x4000 + RO_SECTION@0x4000 0x75c000{ + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x66c000 + } + } + } +} diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def index 26686bea9ce..14462c94462 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -26,5 +26,5 @@ mpcie2_clk0 com2_en0 boosten1 sd3mode0 -iommu0 +iommu1 watchdog0000 diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 3aa9fbdddae..89359af718f 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -19,6 +19,7 @@ #include #include #include +#include static void *smp_write_config_table(void *v) { @@ -53,6 +54,11 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24); + ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF); + + smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 8bffdf33ec4..0ea2e3b399c 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -52,6 +52,15 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Release GPIO32/33 for other uses. */ pm_write8(0xea, 1); + + /* + * Assert resets on the PCIe slots, since AGESA calls deassert callout + * only. Only apu2 uses GPIOs to reset PCIe slots. + */ + if (CONFIG(BOARD_PCENGINES_APU2)) { + gpio1_write8(0xa, gpio1_read8(0xa) & ~(1 << 6)); + gpio1_write8(0xe, gpio1_read8(0xe) & ~(1 << 6)); + } } static void early_lpc_init(void) diff --git a/src/mainboard/pcengines/apu2/variants/apu2/bootorder b/src/mainboard/pcengines/apu2/variants/apu2/bootorder index eb6247f75e3..6524719cde0 100644 Binary files a/src/mainboard/pcengines/apu2/variants/apu2/bootorder and b/src/mainboard/pcengines/apu2/variants/apu2/bootorder differ diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder index eb6247f75e3..6524719cde0 100644 Binary files a/src/mainboard/pcengines/apu2/variants/apu3/bootorder and b/src/mainboard/pcengines/apu2/variants/apu3/bootorder differ diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder index eb6247f75e3..6524719cde0 100644 Binary files a/src/mainboard/pcengines/apu2/variants/apu4/bootorder and b/src/mainboard/pcengines/apu2/variants/apu4/bootorder differ diff --git a/src/mainboard/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/variants/apu5/bootorder index d6bcf164e62..43f21242006 100644 Binary files a/src/mainboard/pcengines/apu2/variants/apu5/bootorder and b/src/mainboard/pcengines/apu2/variants/apu5/bootorder differ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index fbc420d91b8..6e68831058f 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -18,7 +18,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -35,6 +37,8 @@ #include #include #include +#include + #include "mainboard/pcengines/apu2/bios_knobs.h" #define MAX_NODE_NUMS MAX_NODES @@ -292,6 +296,7 @@ static void read_resources(struct device *dev) { u32 nodeid; struct bus *link; + struct resource *res; nodeid = amdfam16_nodeid(dev); for (link = dev->link_list; link; link = link->next) { @@ -306,6 +311,12 @@ static void read_resources(struct device *dev) * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + /* NB IOAPIC2 resource */ + res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res->base = IO_APIC2_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) @@ -412,6 +423,7 @@ static void set_resources(struct device *dev) static void northbridge_init(struct device *dev) { + setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) @@ -432,59 +444,148 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) +{ + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + unsigned long offset = ((current + 0x7) & (~ 0x7)) - current; + ivrs_ivhd_special_t *ivhd_ioapic = + (ivrs_ivhd_special_t *)(current + offset); + + ivhd_ioapic->type = IVHD_SPECIAL_DEVICE; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = 0xd7; /* Allow all interrupts */ + ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_ioapic->variety = IVHD_VARIETY_IOAPIC; + current += sizeof(ivrs_ivhd_special_t) + offset; + + ivhd_ioapic = (ivrs_ivhd_special_t *)current; + + ivhd_ioapic->type = IVHD_SPECIAL_DEVICE; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = 0x00; + ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ + /* + * GNB IOAPIC on Root Complex. + * This device ID is requested by IOMMU drivers on most systems + * although it is not described in any documentation. + */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); + ivhd_ioapic->variety = IVHD_VARIETY_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_describe_hpet(acpi_ivrs_t *ivrs, + unsigned long current, u16 *length) +{ + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + unsigned long offset = ((current + 0x7) & (~ 0x7)) - current; + ivrs_ivhd_special_t *ivhd_hpet = + (ivrs_ivhd_special_t *)(current + offset); + + ivhd_hpet->type = IVHD_SPECIAL_DEVICE; + ivhd_hpet->reserved = 0x0000; + ivhd_hpet->dte_setting = 0x00; + ivhd_hpet->handle = 0x00; + ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_hpet->variety = IVHD_VARIETY_HPET; + current += sizeof(ivrs_ivhd_special_t) + offset; + *length += sizeof(ivrs_ivhd_special_t) + offset; + + return current; +} + +static unsigned long ivhd_generic_range(unsigned long current, u16 start_devid, + u16 end_devid, u8 setting, u16 *length) +{ + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + unsigned long offset = ((current + 0x3) & (~ 0x3)) - current; + ivrs_ivhd_generic_t *ivhd_range = + (ivrs_ivhd_generic_t *)(current + offset); + + /* create the start range IVHD entry */ + ivhd_range->type = IVHD_GENERIC_START_OF_RANGE; + ivhd_range->dev_id = start_devid; + ivhd_range->dte_setting = setting; + current += sizeof(ivrs_ivhd_generic_t) + offset; + *length += sizeof(ivrs_ivhd_generic_t) + offset; + + /* create the end range IVHD entry */ + ivhd_range = (ivrs_ivhd_generic_t *)current; + ivhd_range->type = IVHD_GENERIC_END_OF_RANGE; + ivhd_range->dev_id = end_devid; + ivhd_range->dte_setting = setting; + current += sizeof (ivrs_ivhd_generic_t); + *length += sizeof(ivrs_ivhd_generic_t); + + return current; +} + static void add_ivhd_dev_entry(struct device *parent, struct device *dev, unsigned long *current, uint16_t *length, uint8_t type, uint8_t data) { - uint8_t *p; - p = (uint8_t *) *current; - - if (type == 0x2) { - /* Entry type */ - p[0] = type; - /* Device */ - p[1] = dev->path.pci.devfn; - /* Bus */ - p[2] = dev->bus->secondary; - /* Data */ - p[3] = data; - /* [4:7] Padding */ - p[4] = 0x0; - p[5] = 0x0; - p[6] = 0x0; - p[7] = 0x0; - *length += 8; - *current += 8; - } else if (type == 0x42) { - /* Entry type */ - p[0] = type; - /* Device */ - p[1] = dev->path.pci.devfn; - /* Bus */ - p[2] = dev->bus->secondary; - /* Data */ - p[3] = 0x0; - /* Reserved */ - p[4] = 0x0; - /* Device */ - p[5] = parent->path.pci.devfn; - /* Bus */ - p[6] = parent->bus->secondary; - /* Reserved */ - p[7] = 0x0; - *length += 8; - *current += 8; + unsigned long offset; + + if (type == IVHD_GENERIC_SELECT) { + /* 4-byte IVHD structure, align it to the 4-byte boundary. */ + offset = ((*current + 0x3) & (~ 0x3)) - *current; + ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)(*current + offset); + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + + *current += sizeof(ivrs_ivhd_generic_t) + offset; + *length += sizeof(ivrs_ivhd_generic_t) + offset; + } else if (type == IVHD_ALIAS_SELECT) { + /* 8-byte IVHD structure, align it to the 8-byte boundary. */ + offset = ((*current + 0x7) & (~ 0x7)) - *current; + ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)(*current + offset); + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + ivhd_entry->reserved1 = 0; + ivhd_entry->reserved2 = 0; + ivhd_entry->source_dev_id = parent->path.pci.devfn | (parent->bus->secondary << 8); + + *current += sizeof(ivrs_ivhd_alias_t) + offset; + *length += sizeof(ivrs_ivhd_alias_t) + offset; } } -static void add_ivrs_device_entries(struct device *parent, struct device *dev, +static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, + unsigned long *current, uint16_t *length) +{ + unsigned int header_type, is_pcie; + + header_type = dev->hdr_type & 0x7f; + is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + if (((header_type == PCI_HEADER_TYPE_NORMAL) || + (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { + add_ivhd_dev_entry(parent, dev, current, length, + IVHD_GENERIC_SELECT, 0x0); + } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { + /* Device is legacy PCI or PCI-X */ + add_ivhd_dev_entry(parent, dev, current, length, IVHD_ALIAS_SELECT, 0x0); + } +} + +static void add_ivhd_device_entries(struct device *parent, struct device *dev, unsigned int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length) { struct device *sibling; struct bus *link; - unsigned int header_type; - unsigned int is_pcie; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } if (dev->path.type == DEVICE_PATH_PCI) { @@ -493,30 +594,8 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, *root_level = depth; if ((*root_level != -1) && (dev->enabled)) { - if (depth == *root_level) { - if (dev->path.pci.devfn == (0x14 << 3)) { - /* SMBUS controller */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x97); - } else if (dev->path.pci.devfn != 0x2 && - dev->path.pci.devfn < (0x2 << 3)) { - /* FCH control device */ - } else { - /* Other devices */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); - } - } else { - header_type = dev->hdr_type & 0x7f; - is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (((header_type == PCI_HEADER_TYPE_NORMAL) || - (header_type == PCI_HEADER_TYPE_BRIDGE)) - && is_pcie) { - /* Device or Bridge is PCIe */ - add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0); - } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && - !is_pcie) { - add_ivhd_dev_entry(parent, dev, current, length, 0x42, 0x0); - /* Device is legacy PCI or PCI-X */ - } + if (depth != *root_level) { + ivrs_add_device_or_bridge(parent, dev, current, length); } } } @@ -524,121 +603,143 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, for (link = dev->link_list; link; link = link->next) for (sibling = link->children; sibling; sibling = sibling->sibling) - add_ivrs_device_entries(dev, sibling, depth + 1, depth, + add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); -} -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) -{ - uint8_t *p; - - uint32_t apicid_sb800; - uint32_t apicid_northbridge; - - apicid_sb800 = CONFIG_MAX_CPUS; - apicid_northbridge = CONFIG_MAX_CPUS + 1; - - /* Describe NB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0x0; /* Data */ - p[4] = apicid_northbridge; /* IOAPIC ID */ - p[5] = 0x0; /* Device 0 Function 0 */ - p[6] = 0x0; /* Northbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - /* Describe SB IOAPIC */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = apicid_sb800; /* IOAPIC ID */ - p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ - p[6] = 0x0; /* Southbridge bus */ - p[7] = 0x1; /* Variety */ - current += 8; - - return current; + free(root_level); } +#define IOMMU_MMIO32(x) *((volatile uint32_t *)(x)) +#define AMD_IOMMU_EFR_SUPPORT BIT(27) + static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) { - uint8_t *p; acpi_ivrs_t *ivrs_agesa; + acpi_ivrs_ivhd11_t *ivhd_11; + unsigned long current_backup; struct device *nb_dev = pcidev_on_root(0x0, 0); if (!nb_dev) { - printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); return (unsigned long)ivrs; } + struct device *iommu_dev = pcidev_on_root(0, 2); + + if (!iommu_dev) { + printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); + + return (unsigned long)ivrs; + } - /* obtain IOMMU base address */ ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); if (ivrs_agesa != NULL) { - ivrs->iv_info = 0x0; - /* Maximum supported virtual address size */ - ivrs->iv_info |= (0x40 << 15); - /* Maximum supported physical address size */ - ivrs->iv_info |= (0x30 << 8); - /* Guest virtual address width */ - ivrs->iv_info |= (0x2 << 5); - + ivrs->iv_info = ivrs_agesa->iv_info; ivrs->ivhd.type = 0x10; - ivrs->ivhd.flags = 0x0e; - /* Enable ATS support */ - ivrs->ivhd.flags |= 0x10; + ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); /* BDF :00.2 */ - ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); - /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); + /* PCI Capability block 0x40 (type 0xf, "Secure device") */ ivrs->ivhd.capability_offset = 0x40; - ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; - ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; - ivrs->ivhd.pci_segment_group = 0x0; - ivrs->ivhd.iommu_info = 0x0; - ivrs->ivhd.iommu_info |= (0x13 << 8); - /* use only performance counters related bits: - * PNCounters[16:13] and - * PNBanks[22:17], - * otherwise 0 */ + ivrs->ivhd.iommu_base_lo = ivrs_agesa->ivhd.iommu_base_lo; + ivrs->ivhd.iommu_base_hi = ivrs_agesa->ivhd.iommu_base_hi; + ivrs->ivhd.pci_segment_group = 0x0000; + ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; ivrs->ivhd.iommu_feature_info = - ivrs_agesa->ivhd.iommu_feature_info & 0x7fe000; + ivrs_agesa->ivhd.iommu_feature_info; + /* Enable EFR */ + if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) + & AMD_IOMMU_EFR_SUPPORT) + ivrs->iv_info |= 1; } else { printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); return (unsigned long)ivrs; } - /* Describe HPET */ - p = (uint8_t *)current; - p[0] = 0x48; /* Entry type */ - p[1] = 0; /* Device */ - p[2] = 0; /* Bus */ - p[3] = 0xd7; /* Data */ - p[4] = 0x0; /* HPET number */ - p[5] = 0x14 << 3; /* HPET device */ - p[6] = nb_dev->bus->secondary; /* HPET bus */ - p[7] = 0x2; /* Variety */ - ivrs->ivhd.length += 8; - current += 8; + /* + * Add all possible PCI devices on bus 0 that can generate transactions + * processed by IOMMU. Start with device 00:01.0 since IOMMU does not + * translate transactions generated by itself. + */ + current = ivhd_generic_range(current, PCI_DEVFN(1, 0), + PCI_DEVFN(0x1f, 7), 0, + &ivrs->ivhd.length); /* Describe PCI devices */ - int8_t root_level = -1; - add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, ¤t, + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); + /* Describe HPET */ + current = ivhd_describe_hpet(ivrs, current, &ivrs->ivhd.length); + + current_backup = current; + /* Describe IOAPICs */ - unsigned long prev_current = current; current = acpi_fill_ivrs_ioapic(ivrs, current); - ivrs->ivhd.length += (current - prev_current); + + /* Add IOAPIC entries size to currently assembled IVHD */ + ivrs->ivhd.length += (current - current_backup); + + /* If EFR is not supported, IVHD type 11h is reserved */ + if (!(ivrs->iv_info & 1)) + return current; + + /* + * In order ot utilize all features, firmware should expose type 11h + * IVHD which supersedes the type 10h. + */ + memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); + ivhd_11 = (acpi_ivrs_ivhd11_t *)current; + + /* Enable EFR */ + ivhd_11->type = 0x11; + /* For type 11h bits 6 and 7 are reserved */ + ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; + ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); + /* BDF :00.2 */ + ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + /* PCI Capability block 0x40 (type 0xf, "Secure device") */ + ivhd_11->capability_offset = 0x40; + ivhd_11->iommu_base_lo = ivrs_agesa->ivhd.iommu_base_lo; + ivhd_11->iommu_base_hi = ivrs_agesa->ivhd.iommu_base_hi; + ivhd_11->pci_segment_group = 0x0000; + ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; + ivhd_11->iommu_attributes.perf_counters = + (IOMMU_MMIO32(ivhd_11->iommu_base_lo + 0x4000) >> 7) & 0xf; + ivhd_11->iommu_attributes.perf_counter_banks = + (IOMMU_MMIO32(ivhd_11->iommu_base_lo + 0x4000) >> 12) & 0x3f; + ivhd_11->iommu_attributes.msi_num_ppr = + (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; + + if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) + & AMD_IOMMU_EFR_SUPPORT) { + ivhd_11->efr_reg_image_lo = + IOMMU_MMIO32(ivrs_agesa->ivhd.iommu_base_lo + 0x30); + ivhd_11->efr_reg_image_hi = + IOMMU_MMIO32(ivrs_agesa->ivhd.iommu_base_lo + 0x34); + } + + current += sizeof(acpi_ivrs_ivhd11_t); + + /* Now repeat all the device entries from type 10h */ + current = ivhd_generic_range(current, PCI_DEVFN(1, 0), + PCI_DEVFN(0x1f, 7), 0, + &ivhd_11->length); + + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, + &ivhd_11->length); + + current = ivhd_describe_hpet(ivrs, current, &ivhd_11->length); + + current_backup = current; + + current = acpi_fill_ivrs_ioapic(ivrs, current); + + ivhd_11->length += (current - current_backup); return current; } @@ -684,7 +785,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, if (check_iommu()) { current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = (acpi_ivrs_t *) current; + ivrs = (acpi_ivrs_t *)current; acpi_create_ivrs(ivrs, acpi_fill_ivrs); current += ivrs->header.length; acpi_add_table(rsdp, ivrs); @@ -947,7 +1048,7 @@ static void domain_set_resources(struct device *dev) } - //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08llx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index 5cb77fc0fab..5c738e9083a 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -20,6 +20,7 @@ #include #include #include +#include void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { @@ -64,7 +65,7 @@ void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ Mid->GnbMidConfiguration.iGpuVgaMode = 0; - Mid->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; + Mid->GnbMidConfiguration.GnbIoapicAddress = IO_APIC2_ADDR; } void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h index 3e78155afd2..5b914afc308 100644 --- a/src/northbridge/amd/pi/nb_common.h +++ b/src/northbridge/amd/pi/nb_common.h @@ -15,5 +15,7 @@ #define __AMD_NB_COMMON_H__ #define DEV_CDB 0x18 +#define IO_APIC2_ADDR 0xfec20000 + #endif diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 1d17a176576..7d5b21b5710 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -333,7 +333,8 @@ void verstage_main(void) "Initializing measured boot mode failed!"); } - if (get_recovery_mode_switch()) { + /* Boot to Recovery Mode if no RW slot present */ + if (!CONFIG(VBOOT_SLOTS_RW_A) || get_recovery_mode_switch()) { ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) ctx->flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE;