From f8d56bd8009aa210fc7d5b83097cda2740873e71 Mon Sep 17 00:00:00 2001 From: hasheddan Date: Sat, 8 Apr 2023 18:23:25 -0400 Subject: [PATCH 001/209] Fix typo in serial protocol docs Fixes misspelling of `triggered` in serial protocol docs. Signed-off-by: hasheddan --- docs/en/advanced-topics/serial-protocol.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/en/advanced-topics/serial-protocol.rst b/docs/en/advanced-topics/serial-protocol.rst index 03d930baa..83a7e3a6b 100644 --- a/docs/en/advanced-topics/serial-protocol.rst +++ b/docs/en/advanced-topics/serial-protocol.rst @@ -60,7 +60,7 @@ Each received command will result in a response SLIP packet sent from the ESP ch +========+=============+==============================================================================================================+ | 0 | Direction | Always ``0x01`` for responses | +--------+-------------+--------------------------------------------------------------------------------------------------------------+ -| 1 | Command | Same value as Command identifier in the request packet that trigged the response | +| 1 | Command | Same value as Command identifier in the request packet that triggered the response | +--------+-------------+--------------------------------------------------------------------------------------------------------------+ | 2-3 | Size | Size of data field. At least the length of the `Status Bytes`_ (2 or 4 bytes, see below). | +--------+-------------+--------------------------------------------------------------------------------------------------------------+ From 806af0e4f61d08efd3d47009535079a6d5803f90 Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Wed, 12 Apr 2023 14:16:33 +0200 Subject: [PATCH 002/209] Support more recent reedsolo packages - https://github.com/tomerfiliba-org/reedsolomon/releases/tag/v1.6.1 - this seems to be related to licenses only. - https://github.com/tomerfiliba-org/reedsolomon/releases/tag/v1.7.0 - this is related to installation. Closes https://github.com/espressif/esptool/issues/872 --- setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.py b/setup.py index 04c484fd5..25f0b5e80 100644 --- a/setup.py +++ b/setup.py @@ -125,7 +125,7 @@ def find_version(*file_paths): "cryptography>=2.1.4,<40.0.0", "ecdsa>=0.16.0", "pyserial>=3.0", - "reedsolo>=1.5.3,<=1.6.0", + "reedsolo>=1.5.3,<1.8", ], packages=find_packages(), include_package_data=True, From 637c0dbb841ef13db5b037258ee1756174bac8a5 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 14 Apr 2023 15:21:32 +0200 Subject: [PATCH 003/209] build(arm): add pip extra url for github action build --- .github/workflows/build_esptool.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index 6bd1ced26..9390404df 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -32,6 +32,7 @@ jobs: env: DISTPATH: esptool-${{ matrix.TARGET }} STUBS_DIR: /esptool/targets/stub_flasher/ + PIP_EXTRA_INDEX_URL: "https://dl.espressif.com/pypi" steps: - name: Checkout repository uses: actions/checkout@master From 6779495f84edf59046f91f933ec4ca9a816df25c Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 17 Apr 2023 12:45:59 +0200 Subject: [PATCH 004/209] ci: Fix libffi symlinks for cryptography>=40 --- .gitlab-ci.yml | 4 ++-- setup.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b631db632..32bb72e08 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -209,6 +209,8 @@ check_stub_build: PYTEST_ADDOPTS: "-sv --junitxml=test/report.xml --color=yes" before_script: - pip install -e .[dev] --prefer-binary + # libffi (needed for espsecure) version keeps changing in python docker images. Add a symlink to the installed version on Raspberry Pi + - if [ $(uname -m) = "armv7l" ]; then ln -sfn /usr/lib/arm-linux-gnueabihf/libffi.so.7.1.0 /usr/lib/arm-linux-gnueabihf/libffi.so.6; fi artifacts: reports: junit: test/report.xml @@ -233,8 +235,6 @@ target_esp32: tags: - esptool_esp32_target script: - # libffi (needed for espsecure) version keeps changing in python docker images, add a symlink to the installed version - - ln -sfn /usr/lib/arm-linux-gnueabihf/libffi.so.7.1.0 /usr/lib/arm-linux-gnueabihf/libffi.so.6 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32 --chip esp32 --baud 115200 # ESP32S2 diff --git a/setup.py b/setup.py index 25f0b5e80..f23d64bc2 100644 --- a/setup.py +++ b/setup.py @@ -122,7 +122,7 @@ def find_version(*file_paths): }, install_requires=[ "bitstring>=3.1.6", - "cryptography>=2.1.4,<40.0.0", + "cryptography>=2.1.4", "ecdsa>=0.16.0", "pyserial>=3.0", "reedsolo>=1.5.3,<1.8", From 37e75de390abd93012ddc8ab883ad3db9024e084 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Mon, 3 Apr 2023 21:41:43 +0800 Subject: [PATCH 005/209] espefuse: Prevent burning XTS_AES and ECDSA keys into BLOCK9 (BLOCK_KEY5) eFuse module has a hardware bug. It is related to ESP32-C3, C6, S3, H2 chips: - BLOCK9 (BLOCK_KEY5) can not be used by XTS_AES keys. For H2 chips, the BLOCK9 (BLOCK_KEY5) can not be used by ECDSA keys. S2 does not have such a hardware bug. --- espefuse/efuse/esp32c3/fields.py | 8 ++++ espefuse/efuse/esp32c6/fields.py | 8 ++++ espefuse/efuse/esp32h2/fields.py | 8 ++++ espefuse/efuse/esp32h2beta1/fields.py | 8 ++++ espefuse/efuse/esp32s3/fields.py | 8 ++++ espefuse/efuse/esp32s3beta2/fields.py | 8 ++++ test/test_espefuse.py | 62 ++++++++++++++++++++++++--- 7 files changed, 104 insertions(+), 6 deletions(-) diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index 48ab06249..bf3db04ce 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -459,6 +459,14 @@ def get(self, from_read=True): return p[0] return "FORBIDDEN_STATE" + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + def save(self, new_value): raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index 14a878199..dfbb64ebb 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -459,6 +459,14 @@ def get(self, from_read=True): return p[0] return "FORBIDDEN_STATE" + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + def save(self, new_value): raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index 696eedd57..d9db46230 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -461,6 +461,14 @@ def get(self, from_read=True): return p[0] return "FORBIDDEN_STATE" + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + def save(self, new_value): raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value in ["XTS_AES_128_KEY", "ECDSA_KEY"]: + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index 587bf3263..66663ca85 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -447,6 +447,14 @@ def get(self, from_read=True): return p[0] return "FORBIDDEN_STATE" + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + def save(self, new_value): raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index a96f0cc07..85ad28e7b 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -471,6 +471,14 @@ def get(self, from_read=True): return p[0] return "FORBIDDEN_STATE" + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + def save(self, new_value): raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 952e72927..9e0d129b7 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -471,6 +471,14 @@ def get(self, from_read=True): return p[0] return "FORBIDDEN_STATE" + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + def save(self, new_value): raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 7f0ea9297..2bd3fbc3d 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -980,20 +980,19 @@ def test_burn_key_512bit_non_consecutive_blocks(self): f"burn_key \ BLOCK_KEY2 {IMAGES_DIR}/256bit XTS_AES_128_KEY" ) - self.espefuse_py( - f"burn_key \ - BLOCK_KEY3 {IMAGES_DIR}/256bit USER --no-read-protect --no-write-protect" - ) self.espefuse_py( f"burn_key \ BLOCK_KEY4 {IMAGES_DIR}/256bit SECURE_BOOT_DIGEST0" ) - self.espefuse_py( f"burn_key \ BLOCK_KEY1 {IMAGES_DIR}/256bit_1_256bit_2_combined \ XTS_AES_256_KEY --no-read-protect --no-write-protect" ) + self.espefuse_py( + f"burn_key \ + BLOCK_KEY5 {IMAGES_DIR}/256bit USER --no-read-protect --no-write-protect" + ) # Second half of key should burn to first available key block (BLOCK_KEY5) output = self.espefuse_py("summary -d") @@ -1009,7 +1008,7 @@ def test_burn_key_512bit_non_consecutive_blocks(self): "b0b1b2b3 acadaeaf a8a9aaab a4a5a6a7 11a1a2a3" ) in output assert ( - "[9 ] read_regs: bcbd22bf b8b9babb b4b5b6b7 " + "[7 ] read_regs: bcbd22bf b8b9babb b4b5b6b7 " "b0b1b2b3 acadaeaf a8a9aaab a4a5a6a7 22a1a2a3" ) in output @@ -1901,3 +1900,54 @@ def test_not_burn_cmds(self): adc_info \ check_error" ) + + +@pytest.mark.skipif( + arg_chip not in ["esp32c3", "esp32c6", "esp32h2", "esp32s3"], + reason="These chips have a hardware bug that limits the use of the KEY5", +) +class TestKeyPurposes(EfuseTestCase): + def test_burn_xts_aes_key_purpose(self): + self.espefuse_py( + "burn_efuse KEY_PURPOSE_5 XTS_AES_128_KEY", + check_msg="A fatal error occurred: " + "KEY_PURPOSE_5 can not have XTS_AES_128_KEY " + "key due to a hardware bug (please see TRM for more details)", + ret_code=2, + ) + + @pytest.mark.skipif( + arg_chip != "esp32h2", reason="esp32h2 can not have ECDSA key in KEY5" + ) + def test_burn_ecdsa_key_purpose(self): + self.espefuse_py( + "burn_efuse KEY_PURPOSE_5 ECDSA_KEY", + check_msg="A fatal error occurred: " + "KEY_PURPOSE_5 can not have ECDSA_KEY " + "key due to a hardware bug (please see TRM for more details)", + ret_code=2, + ) + + def test_burn_xts_aes_key(self): + self.espefuse_py( + f"burn_key \ + BLOCK_KEY5 {IMAGES_DIR}/256bit XTS_AES_128_KEY", + check_msg="A fatal error occurred: " + "KEY_PURPOSE_5 can not have XTS_AES_128_KEY " + "key due to a hardware bug (please see TRM for more details)", + ret_code=2, + ) + + @pytest.mark.skipif( + arg_chip != "esp32h2", reason="esp32h2 can not have ECDSA key in KEY5" + ) + def test_burn_ecdsa_key(self): + self.espefuse_py( + f"burn_key \ + BLOCK_KEY5 {S_IMAGES_DIR}/ecdsa192_secure_boot_signing_key_v2.pem \ + ECDSA_KEY", + check_msg="A fatal error occurred: " + "KEY_PURPOSE_5 can not have ECDSA_KEY " + "key due to a hardware bug (please see TRM for more details)", + ret_code=2, + ) From 660cd29679b568f244c73b445c16ad2049d3f3c5 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 19 Apr 2023 18:17:54 -0700 Subject: [PATCH 006/209] image_info: Display disabled WP pin as disabled The image formats know about the special value 0xee used to disable WP. Display this with image_info. E.g.: ESP32-C3 extended image header ============================== WP pin: 0xee (disabled) --- esptool/cmds.py | 5 ++++- test/test_image_info.py | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index fc3825c84..a1dc81fc5 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -737,7 +737,10 @@ def get_key_from_value(dict, val): title = "{} extended image header".format(args.chip.upper()) print(title) print("=" * len(title)) - print("WP pin: {:#02x}".format(image.wp_pin)) + print( + f"WP pin: {image.wp_pin:#02x}", + *["(disabled)"] if image.wp_pin == image.WP_PIN_DISABLED else [], + ) print( "Flash pins drive settings: " "clk_drv: {:#02x}, q_drv: {:#02x}, d_drv: {:#02x}, " diff --git a/test/test_image_info.py b/test/test_image_info.py index 2dd783d93..a1980e425 100755 --- a/test/test_image_info.py +++ b/test/test_image_info.py @@ -86,7 +86,7 @@ def test_v2_esp32c3(self): assert "Flash mode: DIO" in out, "Wrong flash mode" # Extended header - assert "WP pin: 0xee" in out, "Wrong WP pin" + assert "WP pin: 0xee (disabled)" in out, "Wrong WP pin" assert "Chip ID: 5" in out, "Wrong chip ID" assert ( "clk_drv: 0x0, q_drv: 0x0, d_drv: 0x0, " From a7a35765030ae9117f98ec67ccc488705dfd8bd3 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 19 Apr 2023 18:20:46 -0700 Subject: [PATCH 007/209] image_info: Print chip ID's name if known Example: Flash pins drive settings: clk_drv: 0x0, q_drv: 0x0, d_drv: 0x0, cs0_drv: 0x0, hd_drv: 0x0, wp_drv: 0x0 Chip ID: 5 (ESP32-C3) Minimal chip revision: v0.0, (legacy min_rev = 0) Maximal chip revision: v655.35 An unknown ID will be printed as: Chip ID: 42 (Unknown ID) --- esptool/cmds.py | 10 +++++++++- test/test_image_info.py | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index a1dc81fc5..6bc28f608 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -753,7 +753,15 @@ def get_key_from_value(dict, val): image.wp_drv, ) ) - print("Chip ID: {}".format(image.chip_id)) + try: + chip = next( + chip + for chip in CHIP_DEFS.values() + if getattr(chip, "IMAGE_CHIP_ID", None) == image.chip_id + ) + print(f"Chip ID: {image.chip_id} ({chip.CHIP_NAME})") + except StopIteration: + print(f"Chip ID: {image.chip_id} (Unknown ID)") print( "Minimal chip revision: " f"v{image.min_rev_full // 100}.{image.min_rev_full % 100}, " diff --git a/test/test_image_info.py b/test/test_image_info.py index a1980e425..d7820f0c0 100755 --- a/test/test_image_info.py +++ b/test/test_image_info.py @@ -87,7 +87,7 @@ def test_v2_esp32c3(self): # Extended header assert "WP pin: 0xee (disabled)" in out, "Wrong WP pin" - assert "Chip ID: 5" in out, "Wrong chip ID" + assert "Chip ID: 5 (ESP32-C3)" in out, "Wrong chip ID" assert ( "clk_drv: 0x0, q_drv: 0x0, d_drv: 0x0, " "cs0_drv: 0x0, hd_drv: 0x0, wp_drv: 0x0" in out From aad3b8750fb10e9ee859f828d85faa0db6c235ec Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 20 Mar 2023 15:07:09 +0100 Subject: [PATCH 008/209] tests: Make the testsuite Windows compatible --- .gitlab-ci.yml | 36 ++++++++++ test/.covconf | 6 ++ test/conftest.py | 5 ++ test/test_espefuse.py | 3 +- test/test_espsecure.py | 46 +++++++++++-- test/test_esptool.py | 150 ++++++++++++++++++++++++++++------------- 6 files changed, 193 insertions(+), 53 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 32bb72e08..fb947bce1 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -343,6 +343,41 @@ target_esp32h2_jtag_serial: script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32H2_JTAG_SERIAL --preload-port /dev/serial_ports/ESP32H2_PRELOAD --chip esp32h2 --baud 115200 +.windows_test: + stage: test + variables: + PYTEST_ADDOPTS: "-sv --junitxml=test/report.xml --color=yes" + PYTHONPATH: "$PYTHONPATH:${CI_PROJECT_DIR}/test" + COVERAGE_PROCESS_START: "${CI_PROJECT_DIR}/test/.covconf" + before_script: + - pip install -e .[dev] --prefer-binary + artifacts: + reports: + junit: test/report.xml + when: always + paths: + - test/*.out + - "**/.coverage*" + - ".coverage*" + expire_in: 1 week + tags: + - windows-target + +host_tests_windows: + extends: .windows_test + script: + - python -m coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py + - python -m coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espsecure.py + - python -m coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_imagegen.py + - python -m coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_image_info.py + - python -m coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_modules.py + - python -m coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_merge_bin.py + +target_tests_windows: + extends: .windows_test + script: + - python -m coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port COM4 --chip esp32 --baud 115200 -m quick_test + combine_reports: stage: report image: python:3.7-bullseye @@ -362,6 +397,7 @@ combine_reports: coverage: '/(?i)total.*? (100(?:\.0+)?\%|[1-9]?\d(?:\.\d+)?\%)$/' variables: LC_ALL: C.UTF-8 + COVERAGE_RCFILE: "${CI_PROJECT_DIR}/test/.covconf" before_script: - pip install -e .[dev] --prefer-binary script: diff --git a/test/.covconf b/test/.covconf index 07eaf71da..a36bbba25 100644 --- a/test/.covconf +++ b/test/.covconf @@ -1,2 +1,8 @@ [run] parallel = true + +[paths] +source = + ./ + ./ + C:\GitLab-Runner\builds\*\*\espressif\esptool\ \ No newline at end of file diff --git a/test/conftest.py b/test/conftest.py index 93cdfe202..b87fe5624 100644 --- a/test/conftest.py +++ b/test/conftest.py @@ -47,6 +47,11 @@ def pytest_configure(config): "(don't require a real chip connected).", ) + config.addinivalue_line( + "markers", + "quick_test: mark esptool tests checking basic functionality.", + ) + def need_to_install_package_err(): pytest.exit( diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 2bd3fbc3d..1a66268b4 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -67,7 +67,7 @@ class EfuseTestCase: def setup_method(self): if reset_port is None: - self.efuse_file = tempfile.NamedTemporaryFile() + self.efuse_file = tempfile.NamedTemporaryFile(delete=False) self.base_cmd = ( f"{sys.executable} -m espefuse --chip {arg_chip} " f"--virt --path-efuse-file {self.efuse_file.name} -d" @@ -82,6 +82,7 @@ def setup_method(self): def teardown_method(self): if reset_port is None: self.efuse_file.close() + os.unlink(self.efuse_file.name) def reset_efuses(self): # reset and zero efuses diff --git a/test/test_espsecure.py b/test/test_espsecure.py index 82d2823a9..90045ff40 100755 --- a/test/test_espsecure.py +++ b/test/test_espsecure.py @@ -182,7 +182,9 @@ def test_sign_v1_with_pre_calculated_signature(self): # Sign using pre-calculated signature + Verify signing_pubkey = "ecdsa_secure_boot_signing_pubkey.pem" pre_calculated_signature = "pre_calculated_bootloader_signature.bin" - with tempfile.NamedTemporaryFile() as output_file: + + try: + output_file = tempfile.NamedTemporaryFile(delete=False) args = self.SignArgs( "1", None, @@ -200,6 +202,9 @@ def test_sign_v1_with_pre_calculated_signature(self): "1", False, None, self._open(signing_pubkey), output_file ) espsecure.verify_signature(args) + finally: + output_file.close() + os.unlink(output_file.name) def test_sign_v2_data(self): signing_keys = [ @@ -208,7 +213,8 @@ def test_sign_v2_data(self): "ecdsa_secure_boot_signing_key.pem", ] for key in signing_keys: - with tempfile.NamedTemporaryFile() as output_file: + try: + output_file = tempfile.NamedTemporaryFile(delete=False) args = self.SignArgs( "2", [self._open(key)], @@ -224,10 +230,14 @@ def test_sign_v2_data(self): args = self.VerifyArgs("2", False, None, self._open(key), output_file) espsecure.verify_signature(args) + finally: + output_file.close() + os.unlink(output_file.name) def test_sign_v2_multiple_keys(self): # 3 keys + Verify with 3rd key - with tempfile.NamedTemporaryFile() as output_file: + try: + output_file = tempfile.NamedTemporaryFile(delete=False) args = self.SignArgs( "2", [ @@ -273,11 +283,15 @@ def test_sign_v2_multiple_keys(self): output_file, ) espsecure.verify_signature(args) + finally: + output_file.close() + os.unlink(output_file.name) def test_sign_v2_append_signatures(self): # Append signatures + Verify with an appended key # (bootloader_signed_v2.bin already signed with rsa_secure_boot_signing_key.pem) - with tempfile.NamedTemporaryFile() as output_file: + try: + output_file = tempfile.NamedTemporaryFile(delete=False) args = self.SignArgs( "2", [ @@ -322,10 +336,15 @@ def test_sign_v2_append_signatures(self): output_file, ) espsecure.verify_signature(args) + finally: + output_file.close() + os.unlink(output_file.name) def test_sign_v2_append_signatures_multiple_steps(self): # similar to previous test, but sign in two invocations - with tempfile.NamedTemporaryFile() as output_file1, tempfile.NamedTemporaryFile() as output_file2: # noqa E501 + try: + output_file1 = tempfile.NamedTemporaryFile(delete=False) + output_file2 = tempfile.NamedTemporaryFile(delete=False) args = self.SignArgs( "2", [self._open("rsa_secure_boot_signing_key2.pem")], @@ -380,6 +399,11 @@ def test_sign_v2_append_signatures_multiple_steps(self): output_file2, ) espsecure.verify_signature(args) + finally: + output_file1.close() + os.unlink(output_file1.name) + output_file2.close() + os.unlink(output_file2.name) def test_sign_v2_with_pre_calculated_signature(self): # Sign using pre-calculated signature + Verify @@ -394,7 +418,8 @@ def test_sign_v2_with_pre_calculated_signature(self): "pre_calculated_bootloader_signature_ecdsa256.bin", ] for pub_key, signature in zip(signing_keys, pre_calculated_signatures): - with tempfile.NamedTemporaryFile() as output_file: + try: + output_file = tempfile.NamedTemporaryFile(delete=False) args = self.SignArgs( "2", None, @@ -412,6 +437,9 @@ def test_sign_v2_with_pre_calculated_signature(self): "2", False, None, self._open(pub_key), output_file ) espsecure.verify_signature(args) + finally: + output_file.close() + os.unlink(output_file.name) def test_sign_v2_with_multiple_pre_calculated_signatures(self): # Sign using multiple pre-calculated signatures + Verify @@ -425,7 +453,8 @@ def test_sign_v2_with_multiple_pre_calculated_signatures(self): "pre_calculated_bootloader_signature_rsa.bin", "pre_calculated_bootloader_signature_rsa.bin", ] - with tempfile.NamedTemporaryFile() as output_file: + try: + output_file = tempfile.NamedTemporaryFile(delete=False) args = self.SignArgs( "2", None, @@ -443,6 +472,9 @@ def test_sign_v2_with_multiple_pre_calculated_signatures(self): "2", False, None, self._open(signing_pubkeys[0]), output_file ) espsecure.verify_signature(args) + finally: + output_file.close() + os.unlink(output_file.name) def test_verify_signature_signing_key(self): # correct key v1 diff --git a/test/test_esptool.py b/test/test_esptool.py index 9350073df..897a33718 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -230,17 +230,21 @@ def teardown_class(self): def readback(self, offset, length): """Read contents of flash back, return to caller.""" - with tempfile.NamedTemporaryFile() as tf: # need a file we can read into + dump_file = tempfile.NamedTemporaryFile(delete=False) # a file we can read into + try: self.run_esptool( - f"--before default_reset read_flash {offset} {length} {tf.name}" + f"--before default_reset read_flash {offset} {length} {dump_file.name}" ) - with open(tf.name, "rb") as f: + with open(dump_file.name, "rb") as f: rb = f.read() - assert length == len( - rb - ), f"read_flash length {length} offset {offset:#x} yielded {len(rb)} bytes!" - return rb + assert length == len( + rb + ), f"read_flash length {length} offset {offset:#x} yielded {len(rb)} bytes!" + return rb + finally: + dump_file.close() + os.unlink(dump_file.name) def verify_readback(self, offset, length, compare_to, is_bootloader=False): rb = self.readback(offset, length) @@ -266,11 +270,14 @@ def verify_readback(self, offset, length, compare_to, is_bootloader=False): @pytest.mark.skipif(arg_chip != "esp32", reason="ESP32 only") class TestFlashEncryption(EsptoolTestCase): def valid_key_present(self): - esp = esptool.ESP32ROM(arg_port) - esp.connect() - efuses, _ = espefuse.get_efuses(esp=esp) - blk1_rd_en = efuses["BLOCK1"].is_readable() - return not blk1_rd_en + try: + esp = esptool.ESP32ROM(arg_port) + esp.connect() + efuses, _ = espefuse.get_efuses(esp=esp) + blk1_rd_en = efuses["BLOCK1"].is_readable() + return not blk1_rd_en + finally: + esp._port.close() def test_blank_efuse_encrypt_write_abort(self): """ @@ -366,10 +373,12 @@ def test_blank_efuse_encrypt_write_continue2(self): class TestFlashing(EsptoolTestCase): + @pytest.mark.quick_test def test_short_flash(self): self.run_esptool("write_flash 0x0 images/one_kb.bin") self.verify_readback(0, 1024, "images/one_kb.bin") + @pytest.mark.quick_test def test_highspeed_flash(self): self.run_esptool("write_flash 0x0 images/fifty_kb.bin", baud=921600) self.verify_readback(0, 50 * 1024, "images/fifty_kb.bin") @@ -423,6 +432,7 @@ def test_correct_offset(self): ct = f.read() assert last_sector == ct + @pytest.mark.quick_test def test_no_compression_flash(self): self.run_esptool( "write_flash -u 0x0 images/sector.bin 0x1000 images/fifty_kb.bin" @@ -430,6 +440,7 @@ def test_no_compression_flash(self): self.verify_readback(0, 4096, "images/sector.bin") self.verify_readback(4096, 50 * 1024, "images/fifty_kb.bin") + @pytest.mark.quick_test @pytest.mark.skipif(arg_chip == "esp8266", reason="Added in ESP32") def test_compressed_nostub_flash(self): self.run_esptool( @@ -465,6 +476,7 @@ def test_length_not_aligned_4bytes(self): def test_length_not_aligned_4bytes_no_compression(self): self.run_esptool("write_flash -u 0x0 images/not_4_byte_aligned.bin") + @pytest.mark.quick_test @pytest.mark.host_test def test_write_overlap(self): output = self.run_esptool_error( @@ -472,6 +484,7 @@ def test_write_overlap(self): ) assert "Detected overlap at address: 0x1000 " in output + @pytest.mark.quick_test @pytest.mark.host_test def test_repeated_address(self): output = self.run_esptool_error( @@ -479,6 +492,7 @@ def test_repeated_address(self): ) assert "Detected overlap at address: 0x0 " in output + @pytest.mark.quick_test @pytest.mark.host_test def test_write_sector_overlap(self): # These two 1KB files don't overlap, @@ -495,19 +509,30 @@ def test_write_no_overlap(self): assert "Detected overlap at address" not in output def test_compressible_file(self): - with tempfile.NamedTemporaryFile() as f: + try: + input_file = tempfile.NamedTemporaryFile(delete=False) file_size = 1024 * 1024 - f.write(b"\x00" * file_size) - self.run_esptool(f"write_flash 0x10000 {f.name}") + input_file.write(b"\x00" * file_size) + input_file.close() + self.run_esptool(f"write_flash 0x10000 {input_file.name}") + finally: + os.unlink(input_file.name) def test_compressible_non_trivial_file(self): - with tempfile.NamedTemporaryFile() as f: + try: + input_file = tempfile.NamedTemporaryFile(delete=False) file_size = 1000 * 1000 same_bytes = 8000 for _ in range(file_size // same_bytes): - f.write(struct.pack("B", random.randrange(0, 1 << 8)) * same_bytes) - self.run_esptool(f"write_flash 0x10000 {f.name}") + input_file.write( + struct.pack("B", random.randrange(0, 1 << 8)) * same_bytes + ) + input_file.close() + self.run_esptool(f"write_flash 0x10000 {input_file.name}") + finally: + os.unlink(input_file.name) + @pytest.mark.quick_test def test_zero_length(self): # Zero length files are skipped with a warning output = self.run_esptool( @@ -516,6 +541,7 @@ def test_zero_length(self): self.verify_readback(0x10000, 1024, "images/one_kb.bin") assert "zerolength.bin is empty" in output + @pytest.mark.quick_test def test_single_byte(self): self.run_esptool("write_flash 0x0 images/onebyte.bin") self.verify_readback(0x0, 1, "images/onebyte.bin") @@ -575,6 +601,7 @@ def test_flash_with_min_max_rev(self): ) assert "Use --force to flash anyway." in output + @pytest.mark.quick_test def test_erase_before_write(self): output = self.run_esptool("write_flash --erase-all 0x0 images/one_kb.bin") assert "Chip erase completed successfully" in output @@ -616,6 +643,7 @@ def test_large_no_compression(self): self.run_esptool("write_flash -u -fs 4MB 0x280000 images/one_mb.bin") self.verify_readback(0x280000, 0x100000, "images/one_mb.bin") + @pytest.mark.quick_test @pytest.mark.host_test def test_invalid_size_arg(self): self.run_esptool_error("write_flash -fs 10MB 0x6000 images/one_kb.bin") @@ -654,23 +682,29 @@ def test_flash_size_keep(self): class TestFlashDetection(EsptoolTestCase): + @pytest.mark.quick_test def test_flash_id(self): """Test manufacturer and device response of flash detection.""" res = self.run_esptool("flash_id") assert "Manufacturer:" in res assert "Device:" in res + @pytest.mark.quick_test def test_flash_id_expand_args(self): """ Test manufacturer and device response of flash detection with expandable arg """ - with tempfile.NamedTemporaryFile() as tf: - tf.write(b"flash_id\n") - tf.seek(0) - res = self.run_esptool(f"@{tf.name}") + try: + arg_file = tempfile.NamedTemporaryFile(delete=False) + arg_file.write(b"flash_id\n") + arg_file.close() + res = self.run_esptool(f"@{arg_file.name}") assert "Manufacturer:" in res assert "Device:" in res + finally: + os.unlink(arg_file.name) + @pytest.mark.quick_test def test_flash_id_trace(self): """Test trace functionality on flash detection, running without stub""" res = self.run_esptool("--trace flash_id") @@ -690,6 +724,9 @@ def test_flash_id_trace(self): assert "Device:" in res +@pytest.mark.skipif( + os.name == "nt", reason="Temporarily disabled on windows" +) # TODO: ESPTOOL-673 class TestStubReuse(EsptoolTestCase): def test_stub_reuse_with_synchronization(self): """Keep the flasher stub running and reuse it the next time.""" @@ -720,6 +757,7 @@ def test_stub_reuse_without_synchronization(self): class TestErase(EsptoolTestCase): + @pytest.mark.quick_test def test_chip_erase(self): self.run_esptool("write_flash 0x10000 images/one_kb.bin") self.verify_readback(0x10000, 0x400, "images/one_kb.bin") @@ -762,6 +800,7 @@ def test_overlap(self): class TestVerifyCommand(EsptoolTestCase): + @pytest.mark.quick_test def test_verify_success(self): self.run_esptool("write_flash 0x5000 images/one_kb.bin") self.run_esptool("verify_flash 0x5000 images/one_kb.bin") @@ -780,6 +819,7 @@ def test_verify_unaligned_length(self): class TestReadIdentityValues(EsptoolTestCase): + @pytest.mark.quick_test def test_read_mac(self): output = self.run_esptool("read_mac") mac = re.search(r"[0-9a-f:]{17}", output) @@ -799,6 +839,7 @@ def test_read_chip_id(self): class TestMemoryOperations(EsptoolTestCase): + @pytest.mark.quick_test def test_memory_dump(self): output = self.run_esptool("dump_mem 0x50000000 128 memout.bin") assert "Read 128 bytes" in output @@ -851,6 +892,7 @@ def test_keep_does_not_change_settings(self): arg_chip not in ["esp8266", "esp32", "esp32c3"], reason="Don't run for every chip, so other bootloader images are not needed", ) + @pytest.mark.quick_test def test_detect_size_changes_size(self): self.run_esptool( f"write_flash -fs detect {self.flash_offset:#x} {self.BL_IMAGE}" @@ -900,6 +942,7 @@ def test_explicit_set_size_freq_mode(self): class TestLoadRAM(EsptoolTestCase): # flashing an application not supporting USB-CDC will make # /dev/ttyACM0 disappear and USB-CDC tests will not work anymore + @pytest.mark.quick_test def test_load_ram(self): """Verify load_ram command @@ -907,15 +950,17 @@ def test_load_ram(self): "Hello world!\n" to the serial port. """ self.run_esptool(f"load_ram images/ram_helloworld/helloworld-{arg_chip}.bin") - p = serial.serial_for_url(arg_port, arg_baud) - p.timeout = 5 - output = p.read(100) - print(f"Output: {output}") - assert ( - b"Hello world!" in output # xtensa - or b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04' in output # RISC-V - ) - p.close() + try: + p = serial.serial_for_url(arg_port, arg_baud) + p.timeout = 5 + output = p.read(100) + print(f"Output: {output}") + assert ( + b"Hello world!" in output # xtensa + or b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04' in output # C3 + ) + finally: + p.close() class TestDeepSleepFlash(EsptoolTestCase): @@ -945,6 +990,7 @@ class TestBootloaderHeaderRewriteCases(EsptoolTestCase): arg_chip not in ["esp8266", "esp32", "esp32c3"], reason="Don't run on every chip, so other bootloader images are not needed", ) + @pytest.mark.quick_test def test_flash_header_rewrite(self): bl_offset = 0x1000 if arg_chip in ("esp32", "esp32s2") else 0 bl_image = f"images/bootloader_{arg_chip}.bin" @@ -981,6 +1027,7 @@ def _check_output(self, output): assert f"Detecting chip type... {expected_chip_name}" in output assert f"Chip is {expected_chip_name}" in output + @pytest.mark.quick_test def test_auto_detect(self): output = self.run_esptool("chip_id", chip="auto") self._check_output(output) @@ -988,6 +1035,7 @@ def test_auto_detect(self): @pytest.mark.flaky(reruns=5) @pytest.mark.skipif(arg_preload_port is not False, reason="USB-to-UART bridge only") +@pytest.mark.skipif(os.name == "nt", reason="Linux/MacOS only") class TestVirtualPort(TestAutoDetect): def test_auto_detect_virtual_port(self): with ESPRFC2217Server() as server: @@ -1009,6 +1057,7 @@ def test_highspeed_flash_virtual_port(self): self.verify_readback(0, 50 * 1024, "images/fifty_kb.bin") +@pytest.mark.quick_test class TestReadWriteMemory(EsptoolTestCase): def _test_read_write(self, esp): # find the start of one of these named memory regions @@ -1039,19 +1088,26 @@ def _test_read_write(self, esp): assert esp.read_reg(test_addr) == 0x555 finally: esp.write_reg(test_addr, val) # write the original value, non-destructive + esp._port.close() def test_read_write_memory_rom(self): - esp = esptool.get_default_connected_device( - [arg_port], arg_port, 10, 115200, arg_chip - ) - self._test_read_write(esp) + try: + esp = esptool.get_default_connected_device( + [arg_port], arg_port, 10, 115200, arg_chip + ) + self._test_read_write(esp) + finally: + esp._port.close() def test_read_write_memory_stub(self): - esp = esptool.get_default_connected_device( - [arg_port], arg_port, 10, 115200, arg_chip - ) - esp = esp.run_stub() - self._test_read_write(esp) + try: + esp = esptool.get_default_connected_device( + [arg_port], arg_port, 10, 115200, arg_chip + ) + esp = esp.run_stub() + self._test_read_write(esp) + finally: + esp._port.close() @pytest.mark.skipif( arg_chip != "esp32", reason="Could be unsupported by different flash" @@ -1067,11 +1123,14 @@ def test_read_write_flash_status(self): assert f"After flash status: {match.group(1)}" in res def test_read_chip_description(self): - esp = esptool.get_default_connected_device( - [arg_port], arg_port, 10, 115200, arg_chip - ) - chip = esp.get_chip_description() - assert "unknown" not in chip.lower() + try: + esp = esptool.get_default_connected_device( + [arg_port], arg_port, 10, 115200, arg_chip + ) + chip = esp.get_chip_description() + assert "unknown" not in chip.lower() + finally: + esp._port.close() @pytest.mark.skipif( @@ -1111,6 +1170,7 @@ def test_make_image(self): @pytest.mark.skipif(arg_chip != "esp32", reason="Don't need to test multiple times") +@pytest.mark.quick_test class TestConfigFile(EsptoolTestCase): class ConfigFile: """ From b1e355bb8367f3bbc52e347c787e0112a5c241cf Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Mon, 1 May 2023 23:07:12 +0800 Subject: [PATCH 009/209] espefuse: Adds external esp instance Closes https://github.com/espressif/esptool/issues/873 --- espefuse/__init__.py | 44 ++++++++++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/espefuse/__init__.py b/espefuse/__init__.py index 681a9ba25..d36d42262 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -132,7 +132,7 @@ def split_on_groups(all_args): return groups, used_cmds -def main(custom_commandline=None): +def main(custom_commandline=None, esp=None): """ Main function for espefuse @@ -140,7 +140,13 @@ def main(custom_commandline=None): (that uses sys.argv), can be a list of custom arguments as strings. Arguments and their values need to be added as individual items to the list e.g. "--port /dev/ttyUSB1" thus becomes ['--port', '/dev/ttyUSB1']. + + esp - Optional override of the connected device previously + returned by esptool.get_default_connected_device() """ + + external_esp = esp is not None + init_parser = argparse.ArgumentParser( description="espefuse.py v%s - [ESP32xx] efuse get/set tool" % esptool.__version__, @@ -211,22 +217,24 @@ def main(custom_commandline=None): print("espefuse.py v{}".format(esptool.__version__)) - try: - esp = get_esp( - common_args.port, - common_args.baud, - common_args.before, - common_args.chip, - just_print_help, - common_args.virt, - common_args.debug, - common_args.path_efuse_file, - ) - except esptool.FatalError as e: - raise esptool.FatalError( - f"{e}\nPlease make sure that you have specified " - "the right port with the --port argument" - ) # TODO: Require the --port argument in the next major release, ESPTOOL-490 + if not external_esp: + try: + esp = get_esp( + common_args.port, + common_args.baud, + common_args.before, + common_args.chip, + just_print_help, + common_args.virt, + common_args.debug, + common_args.path_efuse_file, + ) + except esptool.FatalError as e: + raise esptool.FatalError( + f"{e}\nPlease make sure that you have specified " + "the right port with the --port argument" + ) + # TODO: Require the --port argument in the next major release, ESPTOOL-490 efuses, efuse_operations = get_efuses( esp, just_print_help, debug_mode, common_args.do_not_confirm @@ -276,7 +284,7 @@ def main(custom_commandline=None): if not efuses.burn_all(check_batch_mode=True): raise esptool.FatalError("BURN was not done") finally: - if not common_args.virt and esp._port: + if not external_esp and not common_args.virt and esp._port: esp._port.close() From 0b3524f33861fb18cc49a88d4bf5ba416bc61a5c Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Wed, 26 Apr 2023 01:41:19 +0800 Subject: [PATCH 010/209] espefuse: Improve efuse error viewing --- espefuse/efuse/base_fields.py | 19 ++++++++ espefuse/efuse/base_operations.py | 65 ++++++++++++++++++--------- espefuse/efuse/esp32/fields.py | 3 -- espefuse/efuse/esp32c2/fields.py | 26 +---------- espefuse/efuse/esp32c3/fields.py | 26 +---------- espefuse/efuse/esp32c6/fields.py | 26 +---------- espefuse/efuse/esp32h2/fields.py | 26 +---------- espefuse/efuse/esp32h2beta1/fields.py | 26 +---------- espefuse/efuse/esp32s2/fields.py | 26 +---------- espefuse/efuse/esp32s3/fields.py | 26 +---------- espefuse/efuse/esp32s3beta2/fields.py | 26 +---------- 11 files changed, 79 insertions(+), 216 deletions(-) diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index 87224c6d9..45dbc547e 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -551,6 +551,10 @@ def print_error_msg(self, error_msg): else: raise esptool.FatalError(error_msg) + def get_block_errors(self, block_num): + """Returns (error count, failure boolean flag)""" + return self.blocks[block_num].num_errors, self.blocks[block_num].fail + class EfuseFieldBase(EfuseProtectBase): def __init__(self, parent, param): @@ -734,3 +738,18 @@ def burn(self, new_value): # Burn a efuse. Added for compatibility reason. self.save(new_value) self.parent.burn_all() + + def get_info(self): + output = f"{self.name} (BLOCK{self.block})" + if self.block == 0: + if self.fail: + output += "[error]" + else: + errs, fail = self.parent.get_block_errors(self.block) + if errs != 0 or fail: + output += "[error]" + if self.efuse_class == "keyblock": + name = self.parent.blocks[self.block].key_purpose_name + if name is not None: + output += f"\n Purpose: {self.parent[name].get()}\n " + return output diff --git a/espefuse/efuse/base_operations.py b/espefuse/efuse/base_operations.py index d062448e4..959ae19f8 100644 --- a/espefuse/efuse/base_operations.py +++ b/espefuse/efuse/base_operations.py @@ -668,26 +668,49 @@ def burn_bit(esp, efuses, args): print("Successful") -def check_error(esp, efuses, args): +def get_error_summary(efuses): error_in_blocks = efuses.get_coding_scheme_warnings() - if args.recovery: - if error_in_blocks: - confirmed = False - for block in reversed(efuses.blocks): - if block.fail or block.num_errors > 0: - if not block.get_bitstring().all(False): - block.save(block.get_bitstring().bytes[::-1]) - if not confirmed: - confirmed = True - efuses.confirm( - "Recovery of block coding errors", args.do_not_confirm - ) - block.burn() - # Reset the recovery flag to run check_error() without it, - # just to check the new state of eFuse blocks. - args.recovery = False - check_error(esp, efuses, args) - else: - if error_in_blocks: - raise esptool.FatalError("Error(s) were detected in eFuses") + if not error_in_blocks: + return False + writable = True + for blk in efuses.blocks: + if blk.fail or blk.num_errors: + if blk.id == 0: + for field in efuses: + if field.block == blk.id and (field.fail or field.num_errors): + wr = "writable" if field.is_writeable() else "not writable" + writable &= wr == "writable" + name = field.name + val = field.get() + print(f"BLOCK{field.block:<2}: {name:<40} = {val:<8} ({wr})") + else: + wr = "writable" if blk.is_writeable() else "not writable" + writable &= wr == "writable" + name = f"{blk.name} [ERRORS:{blk.num_errors} FAIL:{int(blk.fail)}]" + val = str(blk.get_bitstring()) + print(f"BLOCK{blk.id:<2}: {name:<40} = {val:<8} ({wr})") + if not writable and error_in_blocks: + print("Not all errors can be fixed because some fields are write-protected!") + return True + + +def check_error(esp, efuses, args): + error_in_blocks = get_error_summary(efuses) + if args.recovery and error_in_blocks: + confirmed = False + for block in reversed(efuses.blocks): + if block.fail or block.num_errors > 0: + if not block.get_bitstring().all(False): + block.save(block.get_bitstring().bytes[::-1]) + if not confirmed: + confirmed = True + efuses.confirm( + "Recovery of block coding errors", args.do_not_confirm + ) + block.burn() + if confirmed: + efuses.update_efuses() + error_in_blocks = get_error_summary(efuses) + if error_in_blocks: + raise esptool.FatalError("Error(s) were detected in eFuses") print("No errors detected") diff --git a/espefuse/efuse/esp32/fields.py b/espefuse/efuse/esp32/fields.py index ceb160c19..3f764944a 100644 --- a/espefuse/efuse/esp32/fields.py +++ b/espefuse/efuse/esp32/fields.py @@ -286,9 +286,6 @@ def from_tuple(parent, efuse_tuple, type_class): "pkg": EfusePkg, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - return "%s (BLOCK%d):" % (self.name, self.block) - class EfuseMacField(EfuseField): """ diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index f05ee082d..7e58b0a64 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -147,10 +147,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -260,12 +256,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR_REG + offs * 4) for offs in range(1) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -304,21 +297,6 @@ def from_tuple(parent, efuse_tuple, type_class): "adc_tp": EfuseAdcPointCalibration, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseTempSensor(EfuseField): def get(self, from_read=True): diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index bf3db04ce..61008779b 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -158,10 +158,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -262,12 +258,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -311,21 +304,6 @@ def from_tuple(parent, efuse_tuple, type_class): "wafer": EfuseWafer, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseWafer(EfuseField): def get(self, from_read=True): diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index dfbb64ebb..0cab98432 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -158,10 +158,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -262,12 +258,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -311,21 +304,6 @@ def from_tuple(parent, efuse_tuple, type_class): "wafer": EfuseWafer, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseWafer(EfuseField): def get(self, from_read=True): diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index d9db46230..be1488014 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -158,10 +158,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -263,12 +259,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -312,21 +305,6 @@ def from_tuple(parent, efuse_tuple, type_class): "wafer": EfuseWafer, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseWafer(EfuseField): def get(self, from_read=True): diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index 66663ca85..bd2a0bb38 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -152,10 +152,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -258,12 +254,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -302,21 +295,6 @@ def from_tuple(parent, efuse_tuple, type_class): "adc_tp": EfuseAdcPointCalibration, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseTempSensor(EfuseField): def get(self, from_read=True): diff --git a/espefuse/efuse/esp32s2/fields.py b/espefuse/efuse/esp32s2/fields.py index 4bc7af9a7..0fb82c6c5 100644 --- a/espefuse/efuse/esp32s2/fields.py +++ b/espefuse/efuse/esp32s2/fields.py @@ -158,10 +158,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -310,12 +306,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -365,21 +358,6 @@ def from_tuple(parent, efuse_tuple, type_class): "wafer": EfuseWafer, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseWafer(EfuseField): def get(self, from_read=True): diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index 85ad28e7b..36eafdf86 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -158,10 +158,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -264,12 +260,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -319,21 +312,6 @@ def from_tuple(parent, efuse_tuple, type_class): "wafer": EfuseWafer, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseWafer(EfuseField): def get(self, from_read=True): diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 9e0d129b7..0555094bb 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -158,10 +158,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -264,12 +260,9 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: @@ -319,21 +312,6 @@ def from_tuple(parent, efuse_tuple, type_class): "wafer": EfuseWafer, }.get(type_class, EfuseField)(parent, efuse_tuple) - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output - class EfuseWafer(EfuseField): def get(self, from_read=True): From f318f82ec4abcbbc98736aab44dc5cb06f7a897d Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Wed, 26 Apr 2023 01:43:54 +0800 Subject: [PATCH 011/209] espefuse: Explicit setting of efuse time settings EFUSE_PWR_ON_NUM in C3 has default value = 0x2880, now = 0x3000 --- espefuse/efuse/esp32c2/fields.py | 7 +++++++ espefuse/efuse/esp32c2/mem_definition.py | 12 ++++++++++++ espefuse/efuse/esp32c3/fields.py | 7 +++++++ espefuse/efuse/esp32c3/mem_definition.py | 12 ++++++++++++ espefuse/efuse/esp32c6/fields.py | 7 +++++++ espefuse/efuse/esp32c6/mem_definition.py | 12 ++++++++++++ espefuse/efuse/esp32h2/fields.py | 7 +++++++ espefuse/efuse/esp32h2/mem_definition.py | 12 ++++++++++++ espefuse/efuse/esp32h2beta1/fields.py | 7 +++++++ espefuse/efuse/esp32h2beta1/mem_definition.py | 12 ++++++++++++ espefuse/efuse/esp32s3/fields.py | 7 +++++++ espefuse/efuse/esp32s3/mem_definition.py | 12 ++++++++++++ espefuse/efuse/esp32s3beta2/fields.py | 7 +++++++ espefuse/efuse/esp32s3beta2/mem_definition.py | 12 ++++++++++++ 14 files changed, 133 insertions(+) diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index 7e58b0a64..92561e0a6 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -234,6 +234,13 @@ def set_efuse_timing(self): "The eFuse supports only xtal=26M and 40M (xtal was %d)" % xtal_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) diff --git a/espefuse/efuse/esp32c2/mem_definition.py b/espefuse/efuse/esp32c2/mem_definition.py index 0127ddc7a..5b8c7d4df 100644 --- a/espefuse/efuse/esp32c2/mem_definition.py +++ b/espefuse/efuse/esp32c2/mem_definition.py @@ -44,6 +44,18 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_TPGM_INACTIVE_S = 8 EFUSE_TPGM_INACTIVE_M = 0xFF << EFUSE_TPGM_INACTIVE_S + EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x114 + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x108 + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index 61008779b..efe0b0458 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -245,6 +245,13 @@ def set_efuse_timing(self): "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) diff --git a/espefuse/efuse/esp32c3/mem_definition.py b/espefuse/efuse/esp32c3/mem_definition.py index a0405a13b..9384e0dab 100644 --- a/espefuse/efuse/esp32c3/mem_definition.py +++ b/espefuse/efuse/esp32c3/mem_definition.py @@ -73,6 +73,18 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_PWR_OFF_NUM_S = 0 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index 0cab98432..be75a2cbe 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -245,6 +245,13 @@ def set_efuse_timing(self): "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) diff --git a/espefuse/efuse/esp32c6/mem_definition.py b/espefuse/efuse/esp32c6/mem_definition.py index 890653888..47045232e 100644 --- a/espefuse/efuse/esp32c6/mem_definition.py +++ b/espefuse/efuse/esp32c6/mem_definition.py @@ -73,6 +73,18 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_PWR_OFF_NUM_S = 0 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index be1488014..b177228ed 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -246,6 +246,13 @@ def set_efuse_timing(self): "The eFuse supports only xtal=32M (xtal was %d)" % apb_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) diff --git a/espefuse/efuse/esp32h2/mem_definition.py b/espefuse/efuse/esp32h2/mem_definition.py index a49ce9a0d..ed89ca8d4 100644 --- a/espefuse/efuse/esp32h2/mem_definition.py +++ b/espefuse/efuse/esp32h2/mem_definition.py @@ -73,6 +73,18 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_PWR_OFF_NUM_S = 0 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index bd2a0bb38..14ba4e939 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -239,6 +239,13 @@ def set_efuse_timing(self): "The eFuse supports only xtal=32M (xtal was %d)" % apb_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) diff --git a/espefuse/efuse/esp32h2beta1/mem_definition.py b/espefuse/efuse/esp32h2beta1/mem_definition.py index 58aff675f..a9e8bc49e 100644 --- a/espefuse/efuse/esp32h2beta1/mem_definition.py +++ b/espefuse/efuse/esp32h2beta1/mem_definition.py @@ -57,6 +57,18 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_PWR_OFF_NUM_S = 0 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index 36eafdf86..941becb07 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -245,6 +245,13 @@ def set_efuse_timing(self): "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) diff --git a/espefuse/efuse/esp32s3/mem_definition.py b/espefuse/efuse/esp32s3/mem_definition.py index b4e19a76c..b99d97be7 100644 --- a/espefuse/efuse/esp32s3/mem_definition.py +++ b/espefuse/efuse/esp32s3/mem_definition.py @@ -58,6 +58,18 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_PWR_OFF_NUM_S = 0 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 0555094bb..ef202aaef 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -245,6 +245,13 @@ def set_efuse_timing(self): "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) diff --git a/espefuse/efuse/esp32s3beta2/mem_definition.py b/espefuse/efuse/esp32s3beta2/mem_definition.py index a551fce89..a5788d1bf 100644 --- a/espefuse/efuse/esp32s3beta2/mem_definition.py +++ b/espefuse/efuse/esp32s3beta2/mem_definition.py @@ -58,6 +58,18 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_PWR_OFF_NUM_S = 0 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): From 5f2d20d1e30933484785335a628fa6a23b93c714 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 25 Apr 2023 16:00:33 +0200 Subject: [PATCH 012/209] docs(Boot log): Add all esp targets to cover boot troubleshooting Closes https://github.com/espressif/esptool/issues/732 --- .../advanced-topics/boot-mode-selection.rst | 99 +++++++++++++------ 1 file changed, 67 insertions(+), 32 deletions(-) diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index d8d99a7b6..fda23f016 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -2,6 +2,8 @@ {IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO2", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46", esp32c3="GPIO8"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0", esp8266="0", esp32="1000", esp32s2="1000", esp32s3="0", esp32c3="0"} + .. _boot-mode: Boot Mode Selection @@ -217,7 +219,7 @@ Depending on the kind of hardware you have, it may also be possible to manually The rest of boot messages are used internally by Espressif. -.. only:: esp32 +.. only:: not esp8266 Boot Log -------- @@ -225,38 +227,50 @@ Depending on the kind of hardware you have, it may also be possible to manually Boot Mode Message ^^^^^^^^^^^^^^^^^ - After reset, the second line printed by the ESP32 ROM (at 115200bps) is a reset & boot mode message: + After reset, the second line printed by the {IDF_TARGET_NAME} ROM (at 115200bps) is a reset & boot mode message: :: ets Jun 8 2016 00:22:57 rst:0x1 (POWERON_RESET),boot:0x3 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2)) - ``rst:0xNN (REASON)`` is an enumerated value (and description) of the reason for the reset. `A mapping between the hex value and each reason can be found in the ESP-IDF source `__. - The value can be read in ESP32 code via the `get_reset_reason() ROM function `__. - ``boot:0xNN (DESCRIPTION)`` is the hex value of the strapping pins, as represented in the `GPIO_STRAP register `__. + ``rst:0xNN (REASON)`` is an enumerated value (and description) of the reason for the reset. A mapping between the hex value and each reason can be found in the `ESP-IDF source under RESET_REASON enum `__. + The value can be read in {IDF_TARGET_NAME} code via the `get_reset_reason() ROM function `__. + + ``boot:0xNN (DESCRIPTION)`` is the hex value of the strapping pins, as represented in the `GPIO_STRAP register `__. + The individual bit values are as follows: + + .. only:: esp32 + + - ``0x01`` - GPIO5 + - ``0x02`` - MTDO (GPIO15) + - ``0x04`` - GPIO4 + - ``0x08`` - GPIO2 + - ``0x10`` - GPIO0 + - ``0x20`` - MTDI (GPIO12) + + .. only:: not esp32 - - ``0x01`` - GPIO5 - - ``0x02`` - MTDO (GPIO15) - - ``0x04`` - GPIO4 - - ``0x08`` - GPIO2 - - ``0x10`` - GPIO0 - - ``0x20`` - MTDI (GPIO12) + - ``0x04`` - {IDF_TARGET_STRAP_BOOT_2_GPIO} + - ``0x08`` - {IDF_TARGET_STRAP_BOOT_GPIO} If the pin was high on reset, the bit value will be set. If it was low on reset, the bit will be cleared. A number of boot mode strings can be shown depending on which bits are set: - - ``DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2)`` - ESP32 is in download flashing mode (suitable for esptool) + - ``DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2)`` or ``DOWNLOAD(USB/UART0)`` - {IDF_TARGET_NAME} is in download flashing mode (suitable for esptool) - ``SPI_FAST_FLASH_BOOT`` - This is the normal SPI flash boot mode. - - Other modes (including ``HSPI_FLASH_BOOT``, ``SPI_FLASH_BOOT``, ``SDIO_REI_FEO_V1_BOOT``, ``ATE_BOOT``) may be shown here. This indicates an unsupported boot mode has been selected. - Consult the strapping pins shown above (in most cases, one of these modes is selected if GPIO2 has been pulled high when GPIO0 is low). + - Other modes (including ``SPI_FLASH_BOOT``, ``SDIO_REI_FEO_V1_BOOT``, ``ATE_BOOT``) may be shown here. This indicates an unsupported boot mode has been selected. + Consult the strapping pins shown above (in most cases, one of these modes is selected if {IDF_TARGET_STRAP_BOOT_2_GPIO} has been pulled high when {IDF_TARGET_STRAP_BOOT_GPIO} is low). - .. note:: + .. only:: esp32 + + .. note:: + + ``GPIO_STRAP`` register includes GPIO 4 but this pin is not used by any supported boot mode and be set either high or low for all supported boot modes. - ``GPIO_STRAP`` register includes GPIO 4 but this pin is not used by any supported boot mode and be set either high or low for all supported boot modes. Later Boot Messages ^^^^^^^^^^^^^^^^^^^ @@ -269,34 +283,55 @@ Depending on the kind of hardware you have, it may also be possible to manually :: - flash read err, 1000 + flash read err, {IDF_TARGET_BOOTLOADER_OFFSET} - This fatal error indicates that the bootloader tried to read the software bootloader header at address 0x1000 but failed to read valid data. Possible reasons for this include: + This fatal error indicates that the bootloader tried to read the software bootloader header at address 0x{IDF_TARGET_BOOTLOADER_OFFSET} but failed to read valid data. Possible reasons for this include: - - There isn't actually a bootloader at offset 0x1000 (maybe the bootloader was flashed to the wrong offset by mistake, or the flash has been erased and no bootloader has been flashed yet.) + - There isn't actually a bootloader at offset 0x{IDF_TARGET_BOOTLOADER_OFFSET} (maybe the bootloader was flashed to the wrong offset by mistake, or the flash has been erased and no bootloader has been flashed yet.) - Physical problem with the connection to the flash chip, or flash chip power. - - Boot mode accidentally set to ``HSPI_FLASH_BOOT``, which uses different SPI flash pins. Check GPIO2 (see above). - - VDDSDIO has been enabled at 1.8V (due to MTDI/GPIO12, see above), but this flash chip requires 3.3V so it's browning out. - Flash encryption is enabled but the bootloader is plaintext. Alternatively, flash encryption is disabled but the bootloader is encrypted ciphertext. + .. only:: esp32 + + - Boot mode accidentally set to ``HSPI_FLASH_BOOT``, which uses different SPI flash pins. Check {IDF_TARGET_STRAP_BOOT_2_GPIO} (see above). + - VDDSDIO has been enabled at 1.8V (due to MTDI/GPIO12, see above), but this flash chip requires 3.3V so it's browning out. + + Software Bootloader Header Info """"""""""""""""""""""""""""""" - :: + .. only:: esp32 + + :: + + configsip: 0, SPIWP:0x00 + clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 + mode:DIO, clock div:1 + + + .. only:: not esp32 + + :: + + SPIWP:0xee + mode:DIO, clock div:1 + + + This is normal boot output based on a combination of efuse values and information read from the bootloader header at flash offset 0x{IDF_TARGET_BOOTLOADER_OFFSET}: + + .. only:: esp32 + + - ``configsip: N`` indicates SPI flash config: + + - 0 for default SPI flash + - 1 if booting from the HSPI bus (due to EFUSE configuration) + - Any other value indicates that SPI flash pins have been remapped via efuse (the value is the value read from efuse, consult :ref:`espefuse docs ` to get an easier to read representation of these pin mappings). - configsip: 0, SPIWP:0x00 - clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 - mode:DIO, clock div:1 + - ``clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00`` Custom GPIO drive strength values for SPI flash pins. These are read from the bootloader header in flash. Not currently supported. - This is normal boot output based on a combination of efuse values and information read from the bootloader header at flash offset 0x1000: - - ``configsip: N`` indicates SPI flash config: - - 0 for default SPI flash - - 1 if booting from the HSPI bus (due to EFUSE configuration) - - Any other value indicates that SPI flash pins have been remapped via efuse (the value is the value read from efuse, consult :ref:`espefuse docs ` to get an easier to read representation of these pin mappings). - ``SPIWP:0xNN`` indicates a custom ``WP`` pin value, which is stored in the bootloader header. This pin value is only used if SPI flash pins have been remapped via efuse (as shown in the ``configsip`` value). All custom pin values but WP are encoded in the configsip byte loaded from efuse, and WP is supplied in the bootloader header. - - ``clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00`` Custom GPIO drive strength values for SPI flash pins. These are read from the bootloader header in flash. Not currently supported. - ``mode: AAA, clock div: N``. SPI flash access mode. Read from the bootloader header, correspond to the ``--flash_mode`` and ``--flash_freq`` arguments supplied to ``esptool.py write_flash`` or ``esptool.py elf2image``. - ``mode`` can be DIO, DOUT, QIO, or QOUT. *QIO and QOUT are not supported here*, to boot in a Quad I/O mode the ROM bootloader should load the software bootloader in a Dual I/O mode and then the ESP-IDF software bootloader enables Quad I/O based on the detected flash chip mode. - ``clock div: N`` is the SPI flash clock frequency divider. This is an integer clock divider value from an 80MHz APB clock, based on the supplied ``--flash_freq`` argument (ie 80MHz=1, 40MHz=2, etc). @@ -316,7 +351,7 @@ Depending on the kind of hardware you have, it may also be possible to manually These entries are printed as the ROM bootloader loads each segment in the software bootloader image. The load address and length of each segment is printed. - You can compare these values to the software bootloader image by running ``esptool.py --chip esp32 image_info /path/to/bootloader.bin`` to dump image info including a summary of each segment. Corresponding details will also be found in the bootloader ELF file headers. + You can compare these values to the software bootloader image by running ``esptool.py --chip {IDF_TARGET_PATH_NAME} image_info /path/to/bootloader.bin`` to dump image info including a summary of each segment. Corresponding details will also be found in the bootloader ELF file headers. If there is a problem with the SPI flash chip addressing mode, the values printed by the bootloader here may be corrupted. From 18e2cf6eaf01956cd398d1941d2b1daa44676819 Mon Sep 17 00:00:00 2001 From: Dean Gardiner Date: Tue, 9 May 2023 00:39:22 +1200 Subject: [PATCH 013/209] fix: USB-JTAG-Serial PID detection error --- esptool/loader.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/esptool/loader.py b/esptool/loader.py index eb6402369..ba8b7f5bd 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -494,12 +494,14 @@ def _get_pid(self): if active_port.startswith("/dev/") and os.path.islink(active_port): active_port = os.path.realpath(active_port) + active_ports = [active_port] + # The "cu" (call-up) device has to be used for outgoing communication on MacOS if sys.platform == "darwin" and "tty" in active_port: - active_port = [active_port, active_port.replace("tty", "cu")] + active_ports.append(active_port.replace("tty", "cu")) ports = list_ports.comports() for p in ports: - if p.device in active_port: + if p.device in active_ports: return p.pid print( "\nFailed to get PID of a device on {}, " From b188bdd1ddf9b43a8fdeed70051106777604182a Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 28 Apr 2023 21:36:58 +0800 Subject: [PATCH 014/209] esptool: Move bootdesc on the top of the ram segment --- docs/en/esptool/basic-commands.rst | 4 +++- esptool/__init__.py | 2 +- esptool/bin_image.py | 10 ++++++++++ esptool/cmds.py | 27 ++++++++++++++++++++++++++ esptool/util.py | 10 ++++++++++ test/images/bootloader_esp32_v5_2.bin | Bin 0 -> 26768 bytes test/test_image_info.py | 10 ++++++++++ 7 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 test/images/bootloader_esp32_v5_2.bin diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index 967f06b65..373803047 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -220,7 +220,9 @@ This information corresponds to the headers described in :ref:`image-format`. .. only:: not esp8266 - If a valid `ESP-IDF application header `__ is detected in the image, specific fields describing the application are also displayed. + If the given binary file is an application and a valid `ESP-IDF application header `__ is detected in the image, specific fields describing the application are also displayed. + + If the given binary file is a bootloader and a valid `ESP-IDF bootloader header `__ is detected in the image, specific fields describing the bootloader are also displayed. .. _merge-bin: diff --git a/esptool/__init__.py b/esptool/__init__.py index e2cebff88..b0579884e 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -354,7 +354,7 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): subparsers.add_parser("run", help="Run application code in flash") parser_image_info = subparsers.add_parser( - "image_info", help="Dump headers from an application image" + "image_info", help="Dump headers from a binary file (bootloader or application)" ) parser_image_info.add_argument("filename", help="Image file to parse") parser_image_info.add_argument( diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 5d203a51c..24a08e456 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -640,6 +640,16 @@ def save(self, filename): flash_segments.insert(0, segment) break + # For the bootloader image + # move ".dram0.bootdesc" segment to the top of the ram segment + # So bootdesc will be at the very top of the binary at 0x20 offset + # (in the first segment). + for segment in ram_segments: + if segment.name == ".dram0.bootdesc": + ram_segments.remove(segment) + ram_segments.insert(0, segment) + break + # check for multiple ELF sections that are mapped in the same # flash mapping region. This is usually a sign of a broken linker script, # but if you have a legitimate use case then let us know diff --git a/esptool/cmds.py b/esptool/cmds.py index 6bc28f608..ed9cdb3a3 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -34,6 +34,7 @@ from .util import ( div_roundup, flash_size_bytes, + get_file_size, hexify, pad_to, print_overwrite, @@ -788,11 +789,16 @@ def get_key_from_value(dict, val): ) format_str = "{:7} {:#07x} {:#010x} {:#010x} {}" app_desc = None + bootloader_desc = None for idx, seg in enumerate(image.segments, start=1): segs = seg.get_memory_type(image) seg_name = ", ".join(segs) if "DROM" in segs: # The DROM segment starts with the esp_app_desc_t struct app_desc = seg.data[:256] + elif "DRAM" in segs: + # The DRAM segment starts with the esp_bootloader_desc_t struct + if len(seg.data) >= 80: + bootloader_desc = seg.data[:80] print( format_str.format(idx, len(seg.data), seg.addr, seg.file_offs, seg_name) ) @@ -850,6 +856,27 @@ def get_key_from_value(dict, val): print(f'ESP-IDF: {idf_ver.decode("utf-8")}') print(f"Secure version: {secure_version}") + elif bootloader_desc: + BOOTLOADER_DESC_STRUCT_FMT = "F1PDSa4Y+$ksOaU-&$nn&XbeB3F z#STNw*i@2lG-N-xirl{CZqQ`!ng?jIlWrbwV-Xm= zeVin^2cNNsdB#wZpSxv@Dhb14j9|uVQ1Z>OwE~Av>|GHUY-!>DFP&Mh7N)kJM(RPLXc4fqMacP;&BVGfLu zUufuf4M3gAFU&0(Q=l||E9g1uP$^?9Dq>0tz&0`Jg8ah#g0cb_x=hv9e06!^r=F7NZBD7T)AA!adA^K?Wsr(+=O=bVBP!EiogEpqpiIprQr2m2kUaMi;Ca zV;d81Yt-m?WMB>{LUVMpo|_c!+TgKVjhh5Yf03(Puy%PFNWSz=!}Vsps41S#U}lc7 z+n~aNiV0SRF>KB@7;;J(fhv=omtQ<4_pYo9mKP1~@`O21$dLVXDX1nWEQqIQlOgA> z1(OQ1i%Loi*~W1t?}~oM#(*N{XETLm1zCoY+l}*h^}JPF=v5{UdI|K%Xefcv1U4S@ z8|S4h5yE6G=&hR-Luqk_FktQ^;f15^b^8{xn1%Wc*<~B_Mwm2lUSvuP;2z-DUE3wl z#_81E3CP!ISGikX|5E7A-5pDgS0)7wEx? zdHTpum=nqTiYYaMK1C7_J(QG?_)vCHK{0eL%&`xRG5)1x#l_$-J(ORVy`e0}FgB~q zn7?6G9s#tXMrlP6MPTzc=!;8*A>p3ou$t_r@0cUZQa6iu(34Vi%ZV%yCdL_kPELuT zw3I2)7p^xDn3MrELWRO7=Ki<%FD=P_=w|U_nDd+>Luui3@JREGIKFS`<}DmIF>DS2?!cW`8q*(cJ0R$q z$H{f;({0n!Z7Sln&ZABgv7<~___xsm`5~zWyMA}u}3!- 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z_-T=H*P(d$2~$20Ink9UArw+qSnT`wyX3D5Zx^nIiAb3%H~uSwuRxA=fz5(T-3Rcw zZ-rPySD2og9Tp=WSiFSxuQpelbkXs2s3~+849rgur@fU_eDA!$JDcF1AsuoV&OR^t z5vTmv5zGaw_dKBkL+fL9TqswZ90{Qkf5bI1*W|P{IcZ2Qy!rQ6wI znW8=HXNa^1&LCAJ+N~>2?uwJGKuq_WCmdtf2jRt(iXS}twbRz+JaeuQB!kZncUnwl z3*2Aj{^c}XZfA{HiaP_fb(40u594o9Z)2EDVUIWR?@pR}ftw#0uIN7FXoF9~IS2gw z-Qj*{4xcYMx+e}TkTu$**8k^deARFU?sN-#P8X>TxHf$fsl&VM?1CM!@PC{x)b$ z9_p}MYLgY8@`D8H7lQ&0OSJsa8L|xCJy7gkL|#BHry607d4ma7cF!S}M(3vf1UEf> zRdbLi@TKZ;ESITz9SdZq)(9C_;YP0vUV5mW8d6j{ZPiZZ?MCKc1w1M>AwkUvKg+%k zEDtgfG1FrfMNF9hj0esrY4efiT^@NN|*u;~M``Wl}+ z>9loY~caNQ8`4U+PSPxVBYebh!$H~ z8{t6ZG+yxa#!j((H;Gj^V_2A}O~QXULPxbL$@wf3Er-)=m|BCT?+UhdIN+^NQ1=Ip zCf3q8S@k7`uTJj%6neY7r&&qPh}OKi%hGIg@2`OGK0$aePnk|nHl3Jk3ZJ}wv)XjT z3vSqL_d0kGOf(F0Qv-A66r2My%_sa|f~kR1rEmsy`z((Sxa*hK)Ofvv>*A*6@MFfG z`URHP;32s9+pG6N>?9@~!yonX_LBk4ZwD|D0kn?}QAxsmjeB9UQ>3|^tbzClPe;46;J8*eU=vovcm4UR{QsT& kwDgtP!{XA0haYMFx^1&|=2PV#w0!bkK^GtN^RgfM{~v_PbpQYW literal 0 HcmV?d00001 diff --git a/test/test_image_info.py b/test/test_image_info.py index d7820f0c0..0727081ce 100755 --- a/test/test_image_info.py +++ b/test/test_image_info.py @@ -179,3 +179,13 @@ def test_application_info(self): assert "Application information" not in out out = self.run_image_info("auto", ESP8266_BIN, "2") assert "Application information" not in out + + def test_bootloader_info(self): + # This bootloader binary is built from "hello_world" project + # with default settings, IDF version is v5.2. + out = self.run_image_info("esp32", "bootloader_esp32_v5_2.bin", "2") + assert "File size: 26768 (bytes)" in out + assert "Bootloader information" in out + assert "Bootloader version: 1" in out + assert "ESP-IDF: v5.2-dev-254-g1950b15" in out + assert "Compile time: Apr 25 2023 00:13:32" in out From e1863815fc0fcc08c7f697c1233222c64d0e7404 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 7 Oct 2022 20:28:54 +0800 Subject: [PATCH 015/209] espefuse: Move some vars under init method to speedup tool after adding yaml support --- espefuse/efuse/esp32/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32/fields.py | 11 +++++------ espefuse/efuse/esp32c2/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32c2/fields.py | 11 +++++------ espefuse/efuse/esp32c3/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32c3/fields.py | 11 +++++------ espefuse/efuse/esp32c6/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32c6/fields.py | 11 +++++------ .../efuse/esp32h2beta1/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32h2beta1/fields.py | 11 +++++------ espefuse/efuse/esp32s2/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32s2/fields.py | 11 +++++------ espefuse/efuse/esp32s3/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32s3/fields.py | 11 +++++------ .../efuse/esp32s3beta2/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32s3beta2/fields.py | 11 +++++------ 16 files changed, 64 insertions(+), 72 deletions(-) diff --git a/espefuse/efuse/esp32/emulate_efuse_controller.py b/espefuse/efuse/esp32/emulate_efuse_controller.py index 35923cfb1..da7cd44d6 100644 --- a/espefuse/efuse/esp32/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) """ esptool method start >> """ diff --git a/espefuse/efuse/esp32/fields.py b/espefuse/efuse/esp32/fields.py index 3f764944a..85296b49d 100644 --- a/espefuse/efuse/esp32/fields.py +++ b/espefuse/efuse/esp32/fields.py @@ -65,16 +65,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm diff --git a/espefuse/efuse/esp32c2/emulate_efuse_controller.py b/espefuse/efuse/esp32c2/emulate_efuse_controller.py index 1a15f8496..d7323ca90 100644 --- a/espefuse/efuse/esp32c2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c2/emulate_efuse_controller.py @@ -18,11 +18,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-C2" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index 92561e0a6..65e1f606a 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm diff --git a/espefuse/efuse/esp32c3/emulate_efuse_controller.py b/espefuse/efuse/esp32c3/emulate_efuse_controller.py index 71381a23d..6d39762ec 100644 --- a/espefuse/efuse/esp32c3/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c3/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-C3" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index efe0b0458..c77ee9b88 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm diff --git a/espefuse/efuse/esp32c6/emulate_efuse_controller.py b/espefuse/efuse/esp32c6/emulate_efuse_controller.py index e22bb7578..bd7d4e4fd 100644 --- a/espefuse/efuse/esp32c6/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c6/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-C6" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index be75a2cbe..913fa284c 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm diff --git a/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py b/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py index 1f98087d3..937371339 100644 --- a/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-H2(beta1)" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index 14ba4e939..d9e669e7d 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm diff --git a/espefuse/efuse/esp32s2/emulate_efuse_controller.py b/espefuse/efuse/esp32s2/emulate_efuse_controller.py index 749fd424f..e926f3e71 100644 --- a/espefuse/efuse/esp32s2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s2/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-S2" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32s2/fields.py b/espefuse/efuse/esp32s2/fields.py index 0fb82c6c5..d6af81d07 100644 --- a/espefuse/efuse/esp32s2/fields.py +++ b/espefuse/efuse/esp32s2/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm diff --git a/espefuse/efuse/esp32s3/emulate_efuse_controller.py b/espefuse/efuse/esp32s3/emulate_efuse_controller.py index 69e8bafac..1d7569c7e 100644 --- a/espefuse/efuse/esp32s3/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s3/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-S3" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index 941becb07..d4b57b13f 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm diff --git a/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py b/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py index 48f9305a4..ae917b45f 100644 --- a/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-S3(beta2)" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index ef202aaef..98bbe5606 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm From 4c419042e60e737aa67396dcfb007e0bb829352b Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Fri, 7 Oct 2022 02:45:25 +0800 Subject: [PATCH 016/209] espefuse: Adds yaml efuse description files for all chip - esptool: Updates eFuses wafer major&minor versions - esptool(esp32c6): Adds package versions - espefuse(esp32c6): Replace PKG_VERSION BLK_VERSION_MINOR BLK_VERSION_MAJOR - espefuse(esp32c6): Adds adc calib efuses - espefuse: Adds yaml files for Build with PyInstaller --- .github/workflows/build_esptool.yml | 3 +- MANIFEST.in | 1 + docs/en/espefuse/inc/summary_ESP32-C2.rst | 92 +++--- docs/en/espefuse/inc/summary_ESP32-C3.rst | 228 +++++++------- docs/en/espefuse/inc/summary_ESP32-C6.rst | 155 ++++++++++ docs/en/espefuse/inc/summary_ESP32-H2.rst | 155 ++++++++++ docs/en/espefuse/inc/summary_ESP32-S2.rst | 252 ++++++++------- docs/en/espefuse/inc/summary_ESP32-S3.rst | 246 ++++++++------- docs/en/espefuse/inc/summary_ESP32.rst | 122 +++++--- espefuse/efuse/base_fields.py | 12 +- espefuse/efuse/base_operations.py | 21 +- .../efuse/emulate_efuse_controller_base.py | 9 +- espefuse/efuse/esp32/fields.py | 76 ++--- espefuse/efuse/esp32/mem_definition.py | 188 +++++------ .../efuse/esp32c2/emulate_efuse_controller.py | 3 +- espefuse/efuse/esp32c2/fields.py | 60 ++-- espefuse/efuse/esp32c2/mem_definition.py | 185 +++++------ espefuse/efuse/esp32c3/fields.py | 44 +-- espefuse/efuse/esp32c3/mem_definition.py | 288 +++++++---------- espefuse/efuse/esp32c6/fields.py | 72 ++--- espefuse/efuse/esp32c6/mem_definition.py | 287 ++++++----------- espefuse/efuse/esp32c6/operations.py | 52 ++-- .../efuse/esp32h2/emulate_efuse_controller.py | 6 +- espefuse/efuse/esp32h2/fields.py | 87 +++--- espefuse/efuse/esp32h2/mem_definition.py | 278 +++++------------ espefuse/efuse/esp32h2/operations.py | 8 +- espefuse/efuse/esp32h2beta1/fields.py | 57 ++-- espefuse/efuse/esp32h2beta1/mem_definition.py | 242 +++++---------- espefuse/efuse/esp32h2beta1/operations.py | 4 +- espefuse/efuse/esp32s2/fields.py | 49 ++- espefuse/efuse/esp32s2/mem_definition.py | 292 ++++++------------ espefuse/efuse/esp32s3/fields.py | 49 ++- espefuse/efuse/esp32s3/mem_definition.py | 284 ++++++----------- espefuse/efuse/esp32s3beta2/fields.py | 49 ++- espefuse/efuse/esp32s3beta2/mem_definition.py | 279 ++++++----------- espefuse/efuse/mem_definition_base.py | 132 +++++++- espefuse/efuse_defs/esp32.yaml | 64 ++++ espefuse/efuse_defs/esp32c2.yaml | 53 ++++ espefuse/efuse_defs/esp32c3.yaml | 110 +++++++ espefuse/efuse_defs/esp32c6.yaml | 106 +++++++ espefuse/efuse_defs/esp32h2.yaml | 90 ++++++ espefuse/efuse_defs/esp32s2.yaml | 119 +++++++ espefuse/efuse_defs/esp32s3.yaml | 129 ++++++++ esptool/targets/esp32c6.py | 5 +- esptool/targets/esp32c6beta.py | 3 +- esptool/targets/esp32h2.py | 13 +- esptool/targets/esp32h2beta1.py | 15 +- setup.py | 1 + test/test_espefuse.py | 44 +-- 49 files changed, 2741 insertions(+), 2378 deletions(-) create mode 100644 docs/en/espefuse/inc/summary_ESP32-C6.rst create mode 100644 docs/en/espefuse/inc/summary_ESP32-H2.rst create mode 100644 espefuse/efuse_defs/esp32.yaml create mode 100644 espefuse/efuse_defs/esp32c2.yaml create mode 100644 espefuse/efuse_defs/esp32c3.yaml create mode 100644 espefuse/efuse_defs/esp32c6.yaml create mode 100644 espefuse/efuse_defs/esp32h2.yaml create mode 100644 espefuse/efuse_defs/esp32s2.yaml create mode 100644 espefuse/efuse_defs/esp32s3.yaml diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index 9390404df..f5fcbe664 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -32,6 +32,7 @@ jobs: env: DISTPATH: esptool-${{ matrix.TARGET }} STUBS_DIR: /esptool/targets/stub_flasher/ + EFUSE_DIR: /espefuse/efuse_defs/ PIP_EXTRA_INDEX_URL: "https://dl.espressif.com/pypi" steps: - name: Checkout repository @@ -50,7 +51,7 @@ jobs: - name: Build with PyInstaller run: | pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico --add-data=".${{ env.STUBS_DIR }}*.json${{ matrix.SEPARATOR }}${{ env.STUBS_DIR }}" esptool.py - pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico espefuse.py + pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico --add-data=".${{ env.EFUSE_DIR }}*.yaml${{ matrix.SEPARATOR }}${{ env.EFUSE_DIR }}" espefuse.py pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico espsecure.py pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico esp_rfc2217_server.py - name: Sign binaries diff --git a/MANIFEST.in b/MANIFEST.in index 0f6d078f6..42ef8ccff 100644 --- a/MANIFEST.in +++ b/MANIFEST.in @@ -1,6 +1,7 @@ include README.md include LICENSE include esptool/targets/stub_flasher/*.json +include espefuse/efuse_defs/*.yaml # sdist includes test/test*.py by default, but esptool.py tests # are so far only intended to run from the git repo itself prune test diff --git a/docs/en/espefuse/inc/summary_ESP32-C2.rst b/docs/en/espefuse/inc/summary_ESP32-C2.rst index 47c4efc6e..0c29a2556 100644 --- a/docs/en/espefuse/inc/summary_ESP32-C2.rst +++ b/docs/en/espefuse/inc/summary_ESP32-C2.rst @@ -8,72 +8,60 @@ === Run "summary" command === EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- - Adc_Calib fuses: - ADC_CALIBRATION_0 (BLOCK2) = 0 R/W (0b0000000000000000000000) - ADC_CALIBRATION_1 (BLOCK2) = 0 R/W (0x00000000) - ADC_CALIBRATION_2 (BLOCK2) = 0 R/W (0x00000000) - Config fuses: - UART_PRINT_CONTROL (BLOCK0) Set UART boot message output mode = Force print R/W (0b00) - FORCE_SEND_RESUME (BLOCK0) Force ROM code to send a resume cmd during SPI boo = False R/W (0b0) - t - DIS_DIRECT_BOOT (BLOCK0) Disable direct_boot mode = False R/W (0b0) - - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00) - RD_DIS (BLOCK0) Disables software reading from BLOCK3 = 0 R/W (0b00) + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00) + RD_DIS (BLOCK0) Disable reading from BlOCK3 = 0 R/W (0b00) + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + DIS_DIRECT_BOOT (BLOCK0) This bit set means disable direct_boot mode = False R/W (0b0) - Flash Config fuses: - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms + Flash fuses: + FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) + mmand during SPI boot + FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) + nit of ms. If the value is less than 15; the waiti + ng time is the configurable value. Otherwise; the + waiting time is twice the configurable value Identity fuses: - SECURE_VERSION (BLOCK0) Secure version (anti-rollback feature) = 0 R/W (0x0) - CUSTOM_MAC_USED (BLOCK0) Enable CUSTOM_MAC programming = False R/W (0b0) - CUSTOM_MAC (BLOCK1) Custom MAC addr - = 00:00:00:00:00:00 (OK) R/W - MAC (BLOCK2) Factory MAC Address - = 94:b5:55:80:00:d0 (OK) R/W - WAFER_VERSION (BLOCK2) WAFER version = (revision 0) R/W (0b000) - PKG_VERSION (BLOCK2) Package version = ESP32-C2 R/W (0b000) - BLK_VERSION_MINOR (BLOCK2) Version of BLOCK2 = No calibration R/W (0b000) + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MINOR (BLOCK2) WAFER_VERSION_MINOR = 0 R/W (0x0) + WAFER_VERSION_MAJOR (BLOCK2) WAFER_VERSION_MAJOR = 1 R/W (0b01) + PKG_VERSION (BLOCK2) EFUSE_PKG_VERSION = 1 R/W (0b001) + BLK_VERSION_MINOR (BLOCK2) Minor version of BLOCK2 = No calib R/W (0b000) + BLK_VERSION_MAJOR (BLOCK2) Major version of BLOCK2 = 0 R/W (0b00) - Jtag Config fuses: - DIS_PAD_JTAG (BLOCK0) Permanently disable JTAG access via padsUSB JTAG i = False R/W (0b0) - s controlled separately + Jtag fuses: + DIS_PAD_JTAG (BLOCK0) Set this bit to disable pad jtag = False R/W (0b0) - Ldo fuses: - LDO_VOL_BIAS_CONFIG_LOW (BLOCK2) = 0 R/W (0b000) - LDO_VOL_BIAS_CONFIG_HIGH (BLOCK2) = 0 R/W (0b000000000000000000000000000) - - Pvt fuses: - PVT_LOW (BLOCK2) = 0 R/W (0b00000) - PVT_HIGH (BLOCK2) = 0 R/W (0b0000000000) - - Rf fuses: - RF_REF_I_BIAS_CONFIG (BLOCK2) = 0 R/W (0b000) + Mac fuses: + CUSTOM_MAC_USED (BLOCK0) True if MAC_CUSTOM is burned = False R/W (0b0) + CUSTOM_MAC (BLOCK1) Custom MAC address + = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK2) MAC address + = 10:97:bd:f0:e5:28 (OK) R/W Security fuses: - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables iCache in download mode = False R/W (0b0) - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption in Download boot modes = False R/W (0b0) - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,dis - abled otherwise + DIS_DOWNLOAD_ICACHE (BLOCK0) The bit be set to disable icache in download mode = False R/W (0b0) + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) The bit be set to disable manual encryption = False R/W (0b0) + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise XTS_KEY_LENGTH_256 (BLOCK0) Flash encryption key length = 128 bits key R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - SECURE_BOOT_EN (BLOCK0) Configures secure boot = Flase R/W (0b0) + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) + :0] = 0; 1; 2; 4; 5; 6; 7) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) + SECURE_BOOT_EN (BLOCK0) The bit be set to enable secure boot = False R/W (0b0) + SECURE_VERSION (BLOCK0) Secure version for anti-rollback = 0 R/W (0x0) BLOCK_KEY0 (BLOCK3) BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryp - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W tion BLOCK_KEY0_LOW_128 (BLOCK3) BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Encryption BLOCK_KEY0_HI_128 (BLOCK3) BLOCK_KEY0 - higher 128-bits. 128-bits key of Secu = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - re Boot. + re Boot - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) RTC WDT timeout threshold = 0 R/W (0b00) + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle diff --git a/docs/en/espefuse/inc/summary_ESP32-C3.rst b/docs/en/espefuse/inc/summary_ESP32-C3.rst index c5ef0b91a..b1a19ea79 100644 --- a/docs/en/espefuse/inc/summary_ESP32-C3.rst +++ b/docs/en/espefuse/inc/summary_ESP32-C3.rst @@ -4,133 +4,151 @@ Connecting.... Detecting chip type... ESP32-C3 - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- + Calibration fuses: + K_RTC_LDO (BLOCK1) BLOCK1 K_RTC_LDO = -36 R/W (0b1001001) + K_DIG_LDO (BLOCK1) BLOCK1 K_DIG_LDO = -64 R/W (0b1010000) + V_RTC_DBIAS20 (BLOCK1) BLOCK1 voltage of rtc dbias20 = -40 R/W (0x8a) + V_DIG_DBIAS20 (BLOCK1) BLOCK1 voltage of digital dbias20 = -76 R/W (0x93) + DIG_DBIAS_HVT (BLOCK1) BLOCK1 digital dbias when hvt = -28 R/W (0b10111) + THRES_HVT (BLOCK1) BLOCK1 pvt threshold when hvt = 2000 R/W (0b0111110100) + TEMP_CALIB (BLOCK2) Temperature calibration data = -7.2 R/W (0b101001000) + OCODE (BLOCK2) ADC OCode = 78 R/W (0x4e) + ADC1_INIT_CODE_ATTEN0 (BLOCK2) ADC1 init code at atten0 = 1560 R/W (0b0110000110) + ADC1_INIT_CODE_ATTEN1 (BLOCK2) ADC1 init code at atten1 = -108 R/W (0b1000011011) + ADC1_INIT_CODE_ATTEN2 (BLOCK2) ADC1 init code at atten2 = -232 R/W (0b1000111010) + ADC1_INIT_CODE_ATTEN3 (BLOCK2) ADC1 init code at atten3 = -696 R/W (0b1010101110) + ADC1_CAL_VOL_ATTEN0 (BLOCK2) ADC1 calibration voltage at atten0 = -212 R/W (0b1000110101) + ADC1_CAL_VOL_ATTEN1 (BLOCK2) ADC1 calibration voltage at atten1 = 52 R/W (0b0000001101) + ADC1_CAL_VOL_ATTEN2 (BLOCK2) ADC1 calibration voltage at atten2 = -152 R/W (0b1000100110) + ADC1_CAL_VOL_ATTEN3 (BLOCK2) ADC1 calibration voltage at atten3 = -284 R/W (0b1001000111) + Config fuses: - DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) - DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) - DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) - VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0) - BTLC_GPIO_ENABLE (BLOCK0) Enable btlc gpio = 0 R/W (0b00) - POWERGLITCH_EN (BLOCK0) Set this bit to enable power glitch function = False R/W (0b0) - POWER_GLITCH_DSENSE (BLOCK0) Sample delay configuration of power glitch = 0 R/W (0b00) - DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0) - DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) - UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) - FORCE_SEND_RESUME (BLOCK0) Force ROM code to send a resume command during SPI = False R/W (0b0) - bootduring SPI boot - BLOCK_USR_DATA (BLOCK3) User data + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) + DIS_TWAI (BLOCK0) Set this bit to disable CAN function = False R/W (0b0) + DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + ERR_RST_ENABLE (BLOCK0) Use BLOCK0 to check error record registers = with check R/W (0b1) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) - RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) - - Flash Config fuses: - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - FLASH_ECC_MODE (BLOCK0) Set this bit to set flsah ecc mode. - = flash ecc 16to18 byte mode R/W (0b0) - FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) - FLASH_PAGE_SIZE (BLOCK0) Flash page size = 0 R/W (0b00) - FLASH_ECC_EN (BLOCK0) Enable ECC for flash boot = False R/W (0b0) + Flash fuses: + FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) + nit of ms. If the value is less than 15; the waiti + ng time is the configurable value; Otherwise; the + waiting time is twice the configurable value + FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) + mmand during SPI boot Identity fuses: - SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) - MAC (BLOCK1) Factory MAC Address - = 7c:df:a1:40:40:08: (OK) R/W - WAFER_VERSION (BLOCK1) WAFER version = (revision 0) R/W (0b000) - PKG_VERSION (BLOCK1) Package version = ESP32-C3 R/W (0x0) - BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLK_VERSION_MAJOR (BLOCK2) Version of BLOCK2 = No calibration R/W (0b000) - CUSTOM_MAC (BLOCK3) Custom MAC Address - = 00:00:00:00:00:00 (OK) R/W + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 3 R/W (0b011) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 2 R/W (0b010) + WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) + WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 25 60 04 96 c3 fd 41 6f be ed 2c 51 1d e3 7e 21 R/W + BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = With calibration R/W (0b01) + WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 3 R/W (0x3) + << 3 + WAFER_VERSION_MINOR_LO (read only) + + Jtag fuses: + SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) + d number 1 means disable ). JTAG can be enabled in + HMAC module + DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) + is disabled permanently - Jtag Config fuses: - JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) - ag and pad_to_jtag through strapping gpio10 when b - oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa - l to 0. - SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = 0 R/W (0b000) - AG can be activated temporarily by HMAC peripheral - DIS_PAD_JTAG (BLOCK0) Permanently disable JTAG access via pads. USB JTAG = False R/W (0b0) - is controlled separately. + Mac fuses: + MAC (BLOCK1) MAC address + = 58:cf:79:0f:96:8c (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC address + = 00:00:00:00:00:00 (OK) R/W Security fuses: - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,di - sabled otherwise - SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) - KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) - KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) - KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) - KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) - KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) - KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) - SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) - SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - BLOCK_KEY0 (BLOCK4)(0 errors): + DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) + oot_mode[3:0] is 0; 1; 2; 3; 6; 7) + DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) + hip into download mode + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) + ownload boot modes + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) + SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) + boot + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) + :0] = 0; 1; 2; 3; 6; 7) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) + SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) + ure) + BLOCK_KEY0 (BLOCK4) Purpose: USER - Encryption key0 or user data + Key0 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY1 (BLOCK5)(0 errors): + BLOCK_KEY1 (BLOCK5) Purpose: USER - Encryption key1 or user data + Key1 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY2 (BLOCK6)(0 errors): + BLOCK_KEY2 (BLOCK6) Purpose: USER - Encryption key2 or user data + Key2 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY3 (BLOCK7)(0 errors): + BLOCK_KEY3 (BLOCK7) Purpose: USER - Encryption key3 or user data + Key3 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY4 (BLOCK8)(0 errors): + BLOCK_KEY4 (BLOCK8) Purpose: USER - Encryption key4 or user data + Key4 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY5 (BLOCK9)(0 errors): + BLOCK_KEY5 (BLOCK9) Purpose: USER - Encryption key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10)(0 errors): System data (part 2) + Key5 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Spi_Pad_Config fuses: - SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) + Spi Pad fuses: + SPI_PAD_CONFIG_CLK (BLOCK1) SPI PAD CLK = 0 R/W (0b000000) + SPI_PAD_CONFIG_Q (BLOCK1) SPI PAD Q(D1) = 0 R/W (0b000000) + SPI_PAD_CONFIG_D (BLOCK1) SPI PAD D(D0) = 0 R/W (0b000000) + SPI_PAD_CONFIG_CS (BLOCK1) SPI PAD CS = 0 R/W (0b000000) + SPI_PAD_CONFIG_HD (BLOCK1) SPI PAD HD(D3) = 0 R/W (0b000000) + SPI_PAD_CONFIG_WP (BLOCK1) SPI PAD WP(D2) = 0 R/W (0b000000) + SPI_PAD_CONFIG_DQS (BLOCK1) SPI PAD DQS = 0 R/W (0b000000) + SPI_PAD_CONFIG_D4 (BLOCK1) SPI PAD D4 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D5 (BLOCK1) SPI PAD D5 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D6 (BLOCK1) SPI PAD D6 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D7 (BLOCK1) SPI PAD D7 = 0 R/W (0b000000) - Usb Config fuses: - DIS_USB_JTAG (BLOCK0) Disables USB JTAG. JTAG access via pads is control = False R/W (0b0) - led separately - DIS_USB_DEVICE (BLOCK0) Disables USB DEVICE = False R/W (0b0) - DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) - USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disables download through USB-Serial-JTAG = False R/W (0b0) + Usb fuses: + DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) + jtag in module of usb device + DIS_USB_SERIAL_JTAG (BLOCK0) USB-Serial-JTAG = Enable R/W (0b0) + USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disable UART download mode through USB-Serial-JTAG = False R/W (0b0) - Vdd_Spi Config fuses: - PIN_POWER_SELECTION (BLOCK0) GPIO33-GPIO37 power supply selection in ROM code = VDD3P3_CPU R/W (0b0) + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Set this bit to vdd spi pin function as gpio = False R/W (0b0) - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = False R/W (0b0) + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle diff --git a/docs/en/espefuse/inc/summary_ESP32-C6.rst b/docs/en/espefuse/inc/summary_ESP32-C6.rst new file mode 100644 index 000000000..39411b778 --- /dev/null +++ b/docs/en/espefuse/inc/summary_ESP32-C6.rst @@ -0,0 +1,155 @@ +.. code-block:: none + + > espefuse.py -p PORT summary + + Connecting.... + Detecting chip type... ESP32-C6 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + SWAP_UART_SDIO_EN (BLOCK0) Represents whether pad of uart and sdio is swapped = False R/W (0b0) + or not. 1: swapped. 0: not swapped + DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0) + 1: disabled. 0: enabled + DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is the programmed value. Otherwise; the + waiting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot. 1: forced. 0:not for + ced + FLASH_CAP (BLOCK1) = 0 R/W (0b000) + FLASH_TEMP (BLOCK1) = 0 R/W (0b00) + FLASH_VENDOR (BLOCK1) = 0 R/W (0b000) + + Identity fuses: + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MINOR (BLOCK1) = 0 R/W (0x0) + WAFER_VERSION_MAJOR (BLOCK1) = 0 R/W (0b00) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio15 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled. 1: enabled. 0: + disabled + SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) + dd number: disabled. Even number: enabled + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently). 1: disabled. 0: enabled + + Mac fuses: + MAC (BLOCK1) MAC address + = 60:55:f9:f6:03:24 (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W + + Security fuses: + DIS_DOWNLOAD_ICACHE (BLOCK0) Represents whether icache is disabled or enabled i = False R/W (0b0) + n Download mode. 1: disabled. 0: enabled + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled. 1: disab + led. 0: enabled + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) + e_download is disabled or enabled. 1: disabled. 0: + enabled + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode). 1: disabl + ed. 0: enabled + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) + nabled. 0: disabled + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led. 1: enabled. 0: disabled + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled. 1: enabled. 0: disabled + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled. 1: enabled. 0: disabled + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) + or enabled when Secure Boot is enabled. 1: disabl + ed. 0: enabled + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled. 1: disabled. 0: enable + d + DIS_USB_SERIAL_JTAG (BLOCK0) Represents whether USB-Serial-JTAG is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) + . 1: exchanged. 0: not exchanged + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) + isabled or enabled. 1: disabled. 0: enabled + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled. 1: disabled. 0: ena + bled + + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) + io. 1: functioned. 0: not functioned + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) + is selected at startup. 1: selected. 0: not select + ed diff --git a/docs/en/espefuse/inc/summary_ESP32-H2.rst b/docs/en/espefuse/inc/summary_ESP32-H2.rst new file mode 100644 index 000000000..920ace3f3 --- /dev/null +++ b/docs/en/espefuse/inc/summary_ESP32-H2.rst @@ -0,0 +1,155 @@ +.. code-block:: none + + > espefuse.py -p PORT summary + + Connecting.... + Detecting chip type... ESP32-H2 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0) + 1: disabled. 0: enabled + POWERGLITCH_EN (BLOCK0) Represents whether power glitch function is enable = False R/W (0b0) + d. 1: enabled. 0: disabled + DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + HYS_EN_PAD0 (BLOCK0) Set bits to enable hysteresis function of PAD0~5 = 0 R/W (0b000000) + HYS_EN_PAD1 (BLOCK0) Set bits to enable hysteresis function of PAD6~27 = 0 R/W (0b0000000000000000000000) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is the programmed value. Otherwise; the + waiting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot. 1: forced. 0:not for + ced + FLASH_CAP (BLOCK1) = 0 R/W (0b000) + FLASH_TEMP (BLOCK1) = 0 R/W (0b00) + FLASH_VENDOR (BLOCK1) = 0 R/W (0b000) + + Identity fuses: + WAFER_VERSION_MINOR (BLOCK1) = 0 R/W (0b000) + WAFER_VERSION_MAJOR (BLOCK1) = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) + DISABLE_BLK_VERSION_MAJOR (BLOCK2) Disables check of blk version major = False R/W (0b0) + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio25 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 + SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) + dd number: disabled. Even number: enabled + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently). 1: disabled. 0: enabled + + Mac fuses: + MAC (BLOCK1) MAC address + = 60:55:f9:f7:2c:05:ff:fe (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = ff:fe (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00:ff:fe (OK) R/W + + Security fuses: + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled. 1: disab + led. 0: enabled + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) + e_download is disabled or enabled. 1: disabled. 0: + enabled + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode). 1: disabl + ed. 0: enabled + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + ECDSA_FORCE_USE_HARDWARE_K (BLOCK0) Represents whether hardware random number k is for = False R/W (0b0) + ced used in ESDCA. 1: force used. 0: not force use + d + CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) + nabled. 0: disabled + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led. 1: enabled. 0: disabled + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled. 1: enabled. 0: disabled + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled. 1: enabled. 0: disabled + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) + or enabled when Secure Boot is enabled. 1: disabl + ed. 0: enabled + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled. 1: disabled. 0: enable + d + USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) + . 1: exchanged. 0: not exchanged + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Set this bit to disable USB-Serial-JTAG print duri = False R/W (0b0) + ng rom boot + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled. 1: disabled. 0: ena + bled + + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) + io. 1: functioned. 0: not functioned + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) + is selected at startup. 1: selected. 0: not select + ed diff --git a/docs/en/espefuse/inc/summary_ESP32-S2.rst b/docs/en/espefuse/inc/summary_ESP32-S2.rst index cfc61535f..85617bfa4 100644 --- a/docs/en/espefuse/inc/summary_ESP32-S2.rst +++ b/docs/en/espefuse/inc/summary_ESP32-S2.rst @@ -4,149 +4,169 @@ Connecting.... Detecting chip type... ESP32-S2 - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- Calibration fuses: - TEMP_SENSOR_CAL (BLOCK2) Temperature calibration = -9.200000000000001 R/W (0b101011100) - ADC1_MODE0_D2 (BLOCK2) ADC1 calibration 1 = -28 R/W (0x87) - ADC1_MODE1_D2 (BLOCK2) ADC1 calibration 2 = -28 R/W (0x87) - ADC1_MODE2_D2 (BLOCK2) ADC1 calibration 3 = -28 R/W (0x87) - ADC1_MODE3_D2 (BLOCK2) ADC1 calibration 4 = -24 R/W (0x86) - ADC2_MODE0_D2 (BLOCK2) ADC2 calibration 5 = 12 R/W (0x03) - ADC2_MODE1_D2 (BLOCK2) ADC2 calibration 6 = 8 R/W (0x02) - ADC2_MODE2_D2 (BLOCK2) ADC2 calibration 7 = 12 R/W (0x03) - ADC2_MODE3_D2 (BLOCK2) ADC2 calibration 8 = 16 R/W (0x04) - ADC1_MODE0_D1 (BLOCK2) ADC1 calibration 9 = -20 R/W (0b100101) - ADC1_MODE1_D1 (BLOCK2) ADC1 calibration 10 = -12 R/W (0b100011) - ADC1_MODE2_D1 (BLOCK2) ADC1 calibration 11 = -12 R/W (0b100011) - ADC1_MODE3_D1 (BLOCK2) ADC1 calibration 12 = -4 R/W (0b100001) - ADC2_MODE0_D1 (BLOCK2) ADC2 calibration 13 = -12 R/W (0b100011) - ADC2_MODE1_D1 (BLOCK2) ADC2 calibration 14 = -8 R/W (0b100010) - ADC2_MODE2_D1 (BLOCK2) ADC2 calibration 15 = -8 R/W (0b100010) - ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001) + ADC_CALIB (BLOCK2) 4 bit of ADC calibration = 0 R/W (0x0) + TEMP_CALIB (BLOCK2) Temperature calibration data = 3.2 R/W (0b000100000) + RTCCALIB_V1IDX_A10H (BLOCK2) = 55 R/W (0x37) + RTCCALIB_V1IDX_A11H (BLOCK2) = 51 R/W (0x33) + RTCCALIB_V1IDX_A12H (BLOCK2) = 52 R/W (0x34) + RTCCALIB_V1IDX_A13H (BLOCK2) = 53 R/W (0x35) + RTCCALIB_V1IDX_A20H (BLOCK2) = 56 R/W (0x38) + RTCCALIB_V1IDX_A21H (BLOCK2) = 55 R/W (0x37) + RTCCALIB_V1IDX_A22H (BLOCK2) = 55 R/W (0x37) + RTCCALIB_V1IDX_A23H (BLOCK2) = 59 R/W (0x3b) + RTCCALIB_V1IDX_A10L (BLOCK2) = 25 R/W (0b011001) + RTCCALIB_V1IDX_A11L (BLOCK2) = 17 R/W (0b010001) + RTCCALIB_V1IDX_A12L (BLOCK2) = 14 R/W (0b001110) + RTCCALIB_V1IDX_A13L (BLOCK2) = 7 R/W (0b000111) + RTCCALIB_V1IDX_A20L (BLOCK2) = 19 R/W (0b010011) + RTCCALIB_V1IDX_A21L (BLOCK2) = 14 R/W (0b001110) + RTCCALIB_V1IDX_A22L (BLOCK2) = 10 R/W (0b001010) + RTCCALIB_V1IDX_A23L (BLOCK2) = 6 R/W (0b000110) Config fuses: - DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0) - DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) - DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0) - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) - DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) - DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) - DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) - DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0) - ace - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - DIS_LEGACY_SPI_BOOT (BLOCK0) Disables Legacy SPI boot mode = False R/W (0b0) - UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) - DIS_USB_DOWNLOAD_MODE (BLOCK0) Disables use of USB in UART download boot mode = False R/W (0b0) - UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) - FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) - FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0) - d during SPI boot - BLOCK_USR_DATA (BLOCK3) User data + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) + DIS_DCACHE (BLOCK0) Set this bit to disable Dcache = False R/W (0b0) + DIS_TWAI (BLOCK0) Set this bit to disable the TWAI Controller functi = False R/W (0b0) + on + DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0) + ace + DIS_LEGACY_SPI_BOOT (BLOCK0) Set this bit to disable Legacy SPI boot mode = False R/W (0b0) + UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot message = UART0 R/W (0b0) + s + UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) + PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) + en SPI flash is initialized + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) - RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) + Flash fuses: + FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up; = 0 R/W (0x0) + in unit of (ms/2). When the value is 15; delay is + 7.5 ms + FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) + FORCE_SEND_RESUME (BLOCK0) If set; forces ROM code to send an SPI flash resum = False R/W (0b0) + e command during SPI boot + FLASH_VERSION (BLOCK1) Flash version = 1 R/W (0x1) Identity fuses: - BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00) - SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) - MAC (BLOCK1) Factory MAC Address - = 7c:df:a1:00:3a:6e: (OK) R/W - WAFER_VERSION (BLOCK1) WAFER version = A R/W (0b000) - PKG_VERSION (BLOCK1) Package version - = ESP32-S2, QFN 7x7 56 pins R/W (0x0) - BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID - = 7d 33 b8 bb 0b 13 b3 c8 71 37 0e e8 7c ab d5 92 R/W - BLK_VERSION_MINOR (BLOCK2) Version of BLOCK2 = With calibration R/W (0b001) - CUSTOM_MAC (BLOCK3) Custom MAC Address + BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) + WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR = 0 R/W (0b00) + PSRAM_VERSION (BLOCK1) PSRAM version = 0 R/W (0x0) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0x0) + WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = d9 8f 05 d0 86 77 53 db 80 6c ee 40 df 5d ef b0 R/W + BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2 = ADC calib V1 R/W (0b001) + WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) + << 3 + WAFER_VERSION_MINOR_LO (read only) + + Jtag fuses: + SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled; JT = False R/W (0b0) + AG can be activated temporarily by HMAC peripheral + HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) + + Mac fuses: + MAC (BLOCK1) MAC address + = 7c:df:a1:00:48:34 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC = 00:00:00:00:00:00 (OK) R/W Security fuses: - SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = False R/W (0b0) - AG can be activated temporarily by HMAC peripheral - HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,di - sabled otherwise - SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) - KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) - KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) - KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) - KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) - KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) - KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) - SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) - SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - BLOCK_KEY0 (BLOCK4)(0 errors): + DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) + DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) + DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) + hip into download mode + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) + des + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disabled otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Purpose of KEY0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Purpose of KEY1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Purpose of KEY2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Purpose of KEY3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Purpose of KEY4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Purpose of KEY5 = USER R/W (0x0) + SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable aggressive secure boot key = False R/W (0b0) + revocation mode + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable all download boot modes = False R/W (0b0) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode ( = False R/W (0b0) + read/write flash only) + SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) + ure) + BLOCK_KEY0 (BLOCK4) Purpose: USER - Encryption key0 or user data + Key0 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY1 (BLOCK5)(0 errors): + BLOCK_KEY1 (BLOCK5) Purpose: USER - Encryption key1 or user data + Key1 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY2 (BLOCK6)(0 errors): + BLOCK_KEY2 (BLOCK6) Purpose: USER - Encryption key2 or user data + Key2 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY3 (BLOCK7)(0 errors): + BLOCK_KEY3 (BLOCK7) Purpose: USER - Encryption key3 or user data + Key3 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY4 (BLOCK8)(0 errors): + BLOCK_KEY4 (BLOCK8) Purpose: USER - Encryption key4 or user data + Key4 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY5 (BLOCK9)(0 errors): + BLOCK_KEY5 (BLOCK9) Purpose: USER - Encryption key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data (part 2) + Key5 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Spi_Pad_Config fuses: - SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) + Spi Pad fuses: + SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) + SPI_PAD_CONFIG_Q (BLOCK1) SPI_PAD_configure Q(D1) = 0 R/W (0b000000) + SPI_PAD_CONFIG_D (BLOCK1) SPI_PAD_configure D(D0) = 0 R/W (0b000000) + SPI_PAD_CONFIG_CS (BLOCK1) SPI_PAD_configure CS = 0 R/W (0b000000) + SPI_PAD_CONFIG_HD (BLOCK1) SPI_PAD_configure HD(D3) = 0 R/W (0b000000) + SPI_PAD_CONFIG_WP (BLOCK1) SPI_PAD_configure WP(D2) = 0 R/W (0b000000) + SPI_PAD_CONFIG_DQS (BLOCK1) SPI_PAD_configure DQS = 0 R/W (0b000000) + SPI_PAD_CONFIG_D4 (BLOCK1) SPI_PAD_configure D4 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D5 (BLOCK1) SPI_PAD_configure D5 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D6 (BLOCK1) SPI_PAD_configure D6 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D7 (BLOCK1) SPI_PAD_configure D7 = 0 R/W (0b000000) - Usb Config fuses: - DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) - USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) - EXT_PHY_ENABLE (BLOCK0) Enables external USB PHY = False R/W (0b0) - USB_FORCE_NOPERSIST (BLOCK0) Forces to set USB BVALID to 1 = False R/W (0b0) + Usb fuses: + DIS_USB (BLOCK0) Set this bit to disable USB OTG function = False R/W (0b0) + USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) + USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external USB PHY = False R/W (0b0) + USB_FORCE_NOPERSIST (BLOCK0) If set; forces USB BVALID to 1 = False R/W (0b0) + DIS_USB_DOWNLOAD_MODE (BLOCK0) Set this bit to disable use of USB OTG in UART dow = False R/W (0b0) + nload boot mode - Vdd_Spi Config fuses: - VDD_SPI_FORCE (BLOCK0) Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = False R/W (0b0) - ure VDD_SPI LDO - VDD_SPI_XPD (BLOCK0) The VDD_SPI regulator is powered on = False R/W (0b0) - VDD_SPI_TIEH (BLOCK0) The VDD_SPI power supply voltage at reset = Connect to 1.8V LDO R/W (0b0) - PIN_POWER_SELECTION (BLOCK0) Sets default power supply for GPIO33..37, set when = VDD3P3_CPU R/W (0b0) - SPI flash is initialized + Vdd fuses: + VDD_SPI_XPD (BLOCK0) If VDD_SPI_FORCE is 1; this value determines if th = False R/W (0b0) + e VDD_SPI regulator is powered on + VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage + = VDD_SPI connects to 1.8 V LDO R/W (0b0) + VDD_SPI_FORCE (BLOCK0) Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TI = False R/W (0b0) + EH to configure VDD_SPI LDO - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = 0 R/W (0b00) + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). diff --git a/docs/en/espefuse/inc/summary_ESP32-S3.rst b/docs/en/espefuse/inc/summary_ESP32-S3.rst index 603f64239..25c64ac27 100644 --- a/docs/en/espefuse/inc/summary_ESP32-S3.rst +++ b/docs/en/espefuse/inc/summary_ESP32-S3.rst @@ -4,148 +4,160 @@ Connecting.... Detecting chip type... ESP32-S3 - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) - ---------------------------------------------------------------------------------------- - Calibration fuses: - TEMP_SENSOR_CAL (BLOCK2) Temperature calibration = -9.200000000000001 R/W (0b101011100) - ADC1_MODE0_D2 (BLOCK2) ADC1 calibration 1 = -28 R/W (0x87) - ADC1_MODE1_D2 (BLOCK2) ADC1 calibration 2 = -28 R/W (0x87) - ADC1_MODE2_D2 (BLOCK2) ADC1 calibration 3 = -28 R/W (0x87) - ADC1_MODE3_D2 (BLOCK2) ADC1 calibration 4 = -24 R/W (0x86) - ADC2_MODE0_D2 (BLOCK2) ADC2 calibration 5 = 12 R/W (0x03) - ADC2_MODE1_D2 (BLOCK2) ADC2 calibration 6 = 8 R/W (0x02) - ADC2_MODE2_D2 (BLOCK2) ADC2 calibration 7 = 12 R/W (0x03) - ADC2_MODE3_D2 (BLOCK2) ADC2 calibration 8 = 16 R/W (0x04) - ADC1_MODE0_D1 (BLOCK2) ADC1 calibration 9 = -20 R/W (0b100101) - ADC1_MODE1_D1 (BLOCK2) ADC1 calibration 10 = -12 R/W (0b100011) - ADC1_MODE2_D1 (BLOCK2) ADC1 calibration 11 = -12 R/W (0b100011) - ADC1_MODE3_D1 (BLOCK2) ADC1 calibration 12 = -4 R/W (0b100001) - ADC2_MODE0_D1 (BLOCK2) ADC2 calibration 13 = -12 R/W (0b100011) - ADC2_MODE1_D1 (BLOCK2) ADC2 calibration 14 = -8 R/W (0b100010) - ADC2_MODE2_D1 (BLOCK2) ADC2 calibration 15 = -8 R/W (0b100010) - ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001) + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- Config fuses: - DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) - DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0) - DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) - DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) - DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) - DIS_CAN (BLOCK0) Disables the TWAI Controller hardware = False R/W (0b0) - DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0) - ace - FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up, = 0 R/W (0x0) - unit is (ms/2). When the value is 15, delay is 7. - 5 ms - DIS_DIRECT_BOOT (BLOCK0) Disables direct boot mode = False R/W (0b0) - DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Selects the default UART for printing boot msg = UART0 R/W (0b0) - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Disables download through USB-Serial-JTAG = False R/W (0b0) - UART_PRINT_CONTROL (BLOCK0) Sets the default UART boot message output mode = Enabled R/W (0b00) - FLASH_TYPE (BLOCK0) Selects SPI flash type = 4 data lines R/W (0b0) - FORCE_SEND_RESUME (BLOCK0) Forces ROM code to send an SPI flash resume comman = False R/W (0b0) - d during SPI boot - BLOCK_USR_DATA (BLOCK3) User data + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) + DIS_DCACHE (BLOCK0) Set this bit to disable Dcache = False R/W (0b0) + DIS_TWAI (BLOCK0) Set this bit to disable CAN function = False R/W (0b0) + DIS_APP_CPU (BLOCK0) Disable app cpu = False R/W (0b0) + DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) + UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) + PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) + en SPI flash is initialized + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Efuse fuses: - WR_DIS (BLOCK0) Disables programming of individual eFuses = 0 R/W (0x00000000) - RD_DIS (BLOCK0) Disables software reading from BLOCK4-10 = 0 R/W (0b0000000) + Flash fuses: + FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) + nit of ms. If the value is less than 15; the waiti + ng time is the configurable value. Otherwise; the + waiting time is twice the configurable value + FLASH_ECC_MODE (BLOCK0) Flash ECC mode in ROM = 16to18 byte R/W (0b0) + FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) + FLASH_PAGE_SIZE (BLOCK0) Set Flash page size = 0 R/W (0b00) + FLASH_ECC_EN (BLOCK0) Set 1 to enable ECC for flash boot = False R/W (0b0) + FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) + mmand during SPI boot Identity fuses: - BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00) - SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) - MAC (BLOCK1) Factory MAC Address - = 7c:df:a1:00:3a:6e: (OK) R/W - WAFER_VERSION (BLOCK1) WAFER version = A R/W (0b000) - PKG_VERSION (BLOCK1) Package version - = ESP32-S3, QFN 7x7 56 pins R/W (0x0) - BLOCK1_VERSION (BLOCK1) BLOCK1 efuse version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2)(0 errors): Optional unique 128-bit ID - = 7d 33 b8 bb 0b 13 b3 c8 71 37 0e e8 7c ab d5 92 R/W - BLK_VERSION_MAJOR (BLOCK2) Version of BLOCK2 = With calibration R/W (0b001) - CUSTOM_MAC (BLOCK3) Custom MAC Address + DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) + WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 0 R/W (0b000) + WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) + WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = No calib R/W (0b00) + WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) + << 3 + WAFER_VERSION_MINOR_LO (read only) + + Jtag fuses: + SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) + d number 1 means disable ). JTAG can be enabled in + HMAC module + DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) + is disabled permanently + STRAP_JTAG_SEL (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio10 when b + oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa + l to 0 + + Mac fuses: + MAC (BLOCK1) MAC address + = 7c:df:a1:e0:00:58 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC = 00:00:00:00:00:00 (OK) R/W Security fuses: - SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled, JT = False R/W (0b000) - AG can be activated temporarily by HMAC peripheral - HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) - DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des - SPI_BOOT_CRYPT_CNT (BLOCK0) Enables encryption and decryption, when an SPI boo = Disable R/W (0b000) - t mode is set. Enabled when 1 or 3 bits are set,di - sabled otherwise - SECURE_BOOT_KEY_REVOKE0 (BLOCK0) If set, revokes use of secure boot key digest 0 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE1 (BLOCK0) If set, revokes use of secure boot key digest 1 = False R/W (0b0) - SECURE_BOOT_KEY_REVOKE2 (BLOCK0) If set, revokes use of secure boot key digest 2 = False R/W (0b0) - KEY_PURPOSE_0 (BLOCK0) KEY0 purpose = USER R/W (0x0) - KEY_PURPOSE_1 (BLOCK0) KEY1 purpose = USER R/W (0x0) - KEY_PURPOSE_2 (BLOCK0) KEY2 purpose = USER R/W (0x0) - KEY_PURPOSE_3 (BLOCK0) KEY3 purpose = USER R/W (0x0) - KEY_PURPOSE_4 (BLOCK0) KEY4 purpose = USER R/W (0x0) - KEY_PURPOSE_5 (BLOCK0) KEY5 purpose = USER R/W (0x0) - SECURE_BOOT_EN (BLOCK0) Enables secure boot = False R/W (0b0) - SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Enables aggressive secure boot key revocation mode = False R/W (0b0) - DIS_DOWNLOAD_MODE (BLOCK0) Disables all Download boot modes = False R/W (0b0) - ENABLE_SECURITY_DOWNLOAD (BLOCK0) Enables secure UART download mode (read/write flas = False R/W (0b0) - h only) - BLOCK_KEY0 (BLOCK4)(0 errors): + DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) + oot_mode[3:0] is 0; 1; 2; 3; 6; 7) + DIS_DOWNLOAD_DCACHE (BLOCK0) Set this bit to disable Dcache in download mode ( = False R/W (0b0) + boot_mode[3:0] is 0; 1; 2; 3; 6; 7) + DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) + hip into download mode + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) + ownload boot modes + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disabled otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) + SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) + boot + DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) + :0] = 0; 1; 2; 3; 6; 7) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) + SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) + ure) + BLOCK_KEY0 (BLOCK4) Purpose: USER - Encryption key0 or user data + Key0 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY1 (BLOCK5)(0 errors): + BLOCK_KEY1 (BLOCK5) Purpose: USER - Encryption key1 or user data + Key1 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY2 (BLOCK6)(0 errors): + BLOCK_KEY2 (BLOCK6) Purpose: USER - Encryption key2 or user data + Key2 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY3 (BLOCK7)(0 errors): + BLOCK_KEY3 (BLOCK7) Purpose: USER - Encryption key3 or user data + Key3 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY4 (BLOCK8)(0 errors): + BLOCK_KEY4 (BLOCK8) Purpose: USER - Encryption key4 or user data + Key4 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_KEY5 (BLOCK9)(0 errors): + BLOCK_KEY5 (BLOCK9) Purpose: USER - Encryption key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data (part 2) + Key5 or user data = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Spi_Pad_Config fuses: - SPI_PAD_CONFIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_WP (BLOCK1) SPI WP (D2) pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_DQS (BLOCK1) SPI DQS pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D4 (BLOCK1) SPI D4 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D5 (BLOCK1) SPI D5 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D6 (BLOCK1) SPI D6 pad = 0 R/W (0b000000) - SPI_PAD_CONFIG_D7 (BLOCK1) SPI D7 pad = 0 R/W (0b000000) + Spi Pad fuses: + SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) + SPI_PAD_CONFIG_Q (BLOCK1) SPI_PAD_configure Q(D1) = 0 R/W (0b000000) + SPI_PAD_CONFIG_D (BLOCK1) SPI_PAD_configure D(D0) = 0 R/W (0b000000) + SPI_PAD_CONFIG_CS (BLOCK1) SPI_PAD_configure CS = 0 R/W (0b000000) + SPI_PAD_CONFIG_HD (BLOCK1) SPI_PAD_configure HD(D3) = 0 R/W (0b000000) + SPI_PAD_CONFIG_WP (BLOCK1) SPI_PAD_configure WP(D2) = 0 R/W (0b000000) + SPI_PAD_CONFIG_DQS (BLOCK1) SPI_PAD_configure DQS = 0 R/W (0b000000) + SPI_PAD_CONFIG_D4 (BLOCK1) SPI_PAD_configure D4 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D5 (BLOCK1) SPI_PAD_configure D5 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D6 (BLOCK1) SPI_PAD_configure D6 = 0 R/W (0b000000) + SPI_PAD_CONFIG_D7 (BLOCK1) SPI_PAD_configure D7 = 0 R/W (0b000000) - Usb Config fuses: - DIS_USB (BLOCK0) Disables the USB OTG hardware = False R/W (0b0) - USB_EXCHG_PINS (BLOCK0) Exchanges USB D+ and D- pins = False R/W (0b0) - EXT_PHY_ENABLE (BLOCK0) Enables external USB PHY = False R/W (0b0) - USB_FORCE_NOPERSIST (BLOCK0) Forces to set USB BVALID to 1 = False R/W (0b0) + Usb fuses: + DIS_USB_OTG (BLOCK0) Set this bit to disable USB function = False R/W (0b0) + USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) + USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external PHY = False R/W (0b0) + DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) + jtag in module of usb device + DIS_USB_SERIAL_JTAG (BLOCK0) Set this bit to disable usb device = False R/W (0b0) + USB_PHY_SEL (BLOCK0) This bit is used to switch internal PHY and extern + = internal PHY is assigned to USB Device while external PHY is assigned to USB OTG R/W (0b0) + al PHY for USB OTG and USB Device + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable UART download mode through = False R/W (0b0) + USB + DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download through USB-OTG = False R/W (0b0) - Vdd_Spi Config fuses: - VDD_SPI_FORCE (BLOCK0) Force using VDD_SPI_XPD and VDD_SPI_TIEH to config = False R/W (0b0) - ure VDD_SPI LDO - VDD_SPI_XPD (BLOCK0) The VDD_SPI regulator is powered on = False R/W (0b0) - VDD_SPI_TIEH (BLOCK0) The VDD_SPI power supply voltage at reset = Connect to 1.8V LDO R/W (0b0) - PIN_POWER_SELECTION (BLOCK0) Sets default power supply for GPIO33..37, set when = VDD3P3_CPU R/W (0b0) - SPI flash is initialized + Vdd fuses: + VDD_SPI_XPD (BLOCK0) SPI regulator power up signal = False R/W (0b0) + VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage + = VDD_SPI connects to 1.8 V LDO R/W (0b0) + VDD_SPI_FORCE (BLOCK0) Set this bit and force to use the configuration of = False R/W (0b0) + eFuse to configure VDD_SPI - Wdt Config fuses: - WDT_DELAY_SEL (BLOCK0) Selects RTC WDT timeout threshold at startup = 0 R/W (0b00) + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) + ock cycle Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). diff --git a/docs/en/espefuse/inc/summary_ESP32.rst b/docs/en/espefuse/inc/summary_ESP32.rst index 575cdb91a..59f303815 100644 --- a/docs/en/espefuse/inc/summary_ESP32.rst +++ b/docs/en/espefuse/inc/summary_ESP32.rst @@ -4,61 +4,87 @@ Connecting........__ Detecting chip type... ESP32 - EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- Calibration fuses: - BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = True R/W (0b1) - ADC_VREF (BLOCK0): Voltage reference calibration = 1114 R/W (0b00010) - ADC1_TP_LOW (BLOCK3): ADC1 150mV reading = 346 R/W (0b0010001) - ADC1_TP_HIGH (BLOCK3): ADC1 850mV reading = 3285 R/W (0b000000101) - ADC2_TP_LOW (BLOCK3): ADC2 150mV reading = 449 R/W (0b0000111) - ADC2_TP_HIGH (BLOCK3): ADC2 850mV reading = 3362 R/W (0b111110101) + ADC_VREF (BLOCK0): True ADC reference voltage = 1121 R/W (0b00011) Config fuses: - XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0) - XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0) - XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0) - CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 53 R/W (0x35) - SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000) - SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000) - SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000) - SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000) - SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000) - DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0) + WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000) + RD_DIS (BLOCK0): Disable reading from BlOCK1-3 = 0 R/W (0x0) + DISABLE_APP_CPU (BLOCK0): Disables APP CPU = False R/W (0b0) + DISABLE_BT (BLOCK0): Disables Bluetooth = False R/W (0b0) + DIS_CACHE (BLOCK0): Disables cache = False R/W (0b0) + CHIP_CPU_FREQ_LOW (BLOCK0): If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the = False R/W (0b0) + ESP32's max CPU frequency is rated for 160MHz. 24 + 0MHz otherwise + CHIP_CPU_FREQ_RATED (BLOCK0): If set; the ESP32's maximum CPU frequency has been = True R/W (0b1) + rated + BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0) + CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 51 R/W (0x33) + VOL_LEVEL_HP_INV (BLOCK0): This field stores the voltage level for CPU to run = 0 R/W (0b00) + at 240 MHz; or for flash/PSRAM to run at 80 MHz.0 + x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: leve + l 4. (RO) + CODING_SCHEME (BLOCK0): Efuse variable block length scheme + = NONE (BLK1-3 len=256 bits) R/W (0b00) + CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1) + DISABLE_SDIO_HOST (BLOCK0): = False R/W (0b0) + DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0) - Efuse fuses: - WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000) - RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0) - CODING_SCHEME (BLOCK0): Efuse variable block length scheme - = 3/4 (BLK1-3 len=192 bits) R/W (0b01) - KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0) + Flash fuses: + FLASH_CRYPT_CNT (BLOCK0): Flash encryption is enabled if this field has an o = 0 R/W (0b0000000) + dd number of bits set + FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0) Identity fuses: - MAC (BLOCK0): Factory MAC Address - = 84:0d:8e:18:8e:44 (CRC 0xad OK) R/W - MAC_CRC (BLOCK0): CRC8 for factory MAC address = 173 R/W (0xad) - CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1) - CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0) - CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10) - CHIP_PACKAGE (BLOCK0): Chip package identifier = 0 R/W (0b000) - MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00) + CHIP_PACKAGE_4BIT (BLOCK0): Chip package identifier #4bit = False R/W (0b0) + CHIP_PACKAGE (BLOCK0): Chip package identifier = 1 R/W (0b001) + CHIP_VER_REV1 (BLOCK0): bit is set to 1 for rev1 silicon = True R/W (0b1) + CHIP_VER_REV2 (BLOCK0): = True R/W (0b1) + WAFER_VERSION_MINOR (BLOCK0): = 0 R/W (0b00) + WAFER_VERSION_MAJOR (BLOCK0): calc WAFER VERSION MAJOR from CHIP_VER_REV1 and CH = 3 R/W (0b011) + IP_VER_REV2 and apb_ctl_date (read only) + PKG_VERSION (BLOCK0): calc Chip package = CHIP_PACKAGE_4BIT << 3 + CHIP_ = 1 R/W (0x1) + PACKAGE (read only) + + Jtag fuses: + JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0) + + Mac fuses: + MAC (BLOCK0): MAC address + = 94:b9:7e:5a:6e:58 (CRC 0xe2 OK) R/W + MAC_CRC (BLOCK0): CRC8 for MAC address = 226 R/W (0xe2) + MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00) Security fuses: - FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000) - UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0) - FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0) - CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1) - ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0) - ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0) - JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0) - DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0) - DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0) - DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0) - BLOCK1 (BLOCK1): Flash encryption key - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK2 (BLOCK2): Secure boot key - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK3 (BLOCK3): Variable Block 3 - = 00 00 00 00 00 00 00 00 00 00 00 00 91 02 87 fa 00 00 00 00 00 00 00 00 R/W + UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode. Valid for ESP32 V3 and = False R/W (0b0) + newer; only + ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0) + ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0) + DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0) + DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0) + KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0) + SECURE_VERSION (BLOCK3): Secure version for anti-rollback = 0 R/W (0x00000000) + BLOCK1 (BLOCK1): Flash encryption key + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK2 (BLOCK2): Security boot key + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK3 (BLOCK3): Variable Block 3 + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Spi Pad fuses: + SPI_PAD_CONFIG_HD (BLOCK0): read for SPI_pad_config_hd = 0 R/W (0b00000) + SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000) + SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000) + SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000) + SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000) + + Vdd fuses: + XPD_SDIO_REG (BLOCK0): read for XPD_SDIO_REG = False R/W (0b0) + XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0) + XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0) - Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V). + Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V) diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index 45dbc547e..fe244efc3 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -5,7 +5,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later import binascii -import re import sys from bitstring import BitArray, BitStream, CreationError @@ -570,16 +569,11 @@ def __init__(self, parent, param): self.efuse_type = param.type self.description = param.description self.dict_value = param.dictionary + self.bit_len = param.bit_len + self.alt_names = param.alt_names self.fail = False self.num_errors = 0 - if self.efuse_type.startswith("bool"): - field_len = 1 - else: - field_len = int(re.search(r"\d+", self.efuse_type).group()) - if self.efuse_type.startswith("bytes"): - field_len *= 8 - self.bitarray = BitStream(field_len) - self.bit_len = field_len + self.bitarray = BitStream(self.bit_len) self.bitarray.set(0) self.update(self.parent.blocks[self.block].bitarray) diff --git a/espefuse/efuse/base_operations.py b/espefuse/efuse/base_operations.py index 959ae19f8..5e3475e49 100644 --- a/espefuse/efuse/base_operations.py +++ b/espefuse/efuse/base_operations.py @@ -71,7 +71,8 @@ def check_efuse_name(efuse_name, efuse_list): metavar="[EFUSE_NAME VALUE] [{} VALUE".format( " VALUE] [".join([e.name for e in efuses.efuses]) ), - efuse_choices=[e.name for e in efuses.efuses], + efuse_choices=[e.name for e in efuses.efuses] + + [name for e in efuses.efuses for name in e.alt_names if name != ""], efuses=efuses, ) @@ -83,7 +84,14 @@ def check_efuse_name(efuse_name, efuse_list): "efuse_name", help="Name of efuse register to burn", nargs="+", - choices=[e.name for e in efuses.efuses if e.read_disable_bit is not None], + choices=[e.name for e in efuses.efuses if e.read_disable_bit is not None] + + [ + name + for e in efuses.efuses + if e.read_disable_bit is not None + for name in e.alt_names + if name != "" + ], ) write_protect_efuse = subparsers.add_parser( @@ -94,7 +102,14 @@ def check_efuse_name(efuse_name, efuse_list): "efuse_name", help="Name of efuse register to burn", nargs="+", - choices=[e.name for e in efuses.efuses if e.write_disable_bit is not None], + choices=[e.name for e in efuses.efuses if e.write_disable_bit is not None] + + [ + name + for e in efuses.efuses + if e.write_disable_bit is not None + for name in e.alt_names + if name != "" + ], ) burn_block_data = subparsers.add_parser( diff --git a/espefuse/efuse/emulate_efuse_controller_base.py b/espefuse/efuse/emulate_efuse_controller_base.py index d1c200f0f..232bfaad8 100644 --- a/espefuse/efuse/emulate_efuse_controller_base.py +++ b/espefuse/efuse/emulate_efuse_controller_base.py @@ -109,8 +109,7 @@ def clean_blocks_wr_regs(self): self.write_reg(wr_addr, 0) def read_field(self, name, bitstring=True): - for e in self.Fields.EFUSES: - field = self.Fields.get(e) + for field in self.Fields.EFUSES: if field.name == name: self.read_block(field.block) block = self.read_block(field.block) @@ -166,8 +165,7 @@ def check_wr_protection_area(self, num_blk, wr_data): ): mask_wr_data.set(1) else: - for e in self.Fields.EFUSES: - field = self.Fields.get(e) + for field in self.Fields.EFUSES: if blk.id == field.block and field.block == num_blk: if field.write_disable_bit is not None and write_disable_bit & ( 1 << field.write_disable_bit @@ -193,8 +191,7 @@ def check_rd_protection_area(self): ): block.set(0) else: - for e in self.Fields.EFUSES: - field = self.Fields.get(e) + for field in self.Fields.EFUSES: if ( blk.id == field.block and field.read_disable_bit is not None diff --git a/espefuse/efuse/esp32/fields.py b/espefuse/efuse/esp32/fields.py index 85296b49d..7ca5fc356 100644 --- a/espefuse/efuse/esp32/fields.py +++ b/espefuse/efuse/esp32/fields.py @@ -88,44 +88,26 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS_256 + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS_256 ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CUSTOM_MAC + EfuseField.convert(self, efuse) for efuse in self.Fields.CUSTOM_MAC ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.ADC_CALIBRATION + EfuseField.convert(self, efuse) for efuse in self.Fields.ADC_CALIBRATION ] else: if self.coding_scheme == self.REGS.CODING_SCHEME_NONE: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS_256 ] elif self.coding_scheme == self.REGS.CODING_SCHEME_34: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS_192 ] else: @@ -134,54 +116,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ) if self["MAC_VERSION"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CUSTOM_MAC + EfuseField.convert(self, efuse) for efuse in self.Fields.CUSTOM_MAC ] if self["BLK3_PART_RESERVE"].get(): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.ADC_CALIBRATION ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.CUSTOM_MAC: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CUSTOM_MAC + EfuseField.convert(self, efuse) for efuse in self.Fields.CUSTOM_MAC ] new_fields = True for efuse in self.Fields.ADC_CALIBRATION: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.ADC_CALIBRATION ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -262,8 +233,7 @@ def get_coding_scheme_warnings(self, silent=False): def summary(self): if self["XPD_SDIO_FORCE"].get() == 0: - output = "Flash voltage (VDD_SDIO) determined by GPIO12 on reset " - "(High for 1.8V, Low/NC for 3.3V)." + output = "Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V)" elif self["XPD_SDIO_REG"].get() == 0: output = "Flash voltage (VDD_SDIO) internal regulator disabled by efuse." elif self["XPD_SDIO_TIEH"].get() == 0: @@ -275,7 +245,7 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "spipin": EfuseSpiPinField, @@ -283,7 +253,7 @@ def from_tuple(parent, efuse_tuple, type_class): "adc_tp": EfuseAdcPointCalibration, "wafer": EfuseWafer, "pkg": EfusePkg, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseMacField(EfuseField): @@ -398,7 +368,9 @@ def print_field(e, new_value): class EfuseWafer(EfuseField): def get(self, from_read=True): rev_bit0 = self.parent["CHIP_VER_REV1"].get(from_read) + assert self.parent["CHIP_VER_REV1"].bit_len == 1 rev_bit1 = self.parent["CHIP_VER_REV2"].get(from_read) + assert self.parent["CHIP_VER_REV2"].bit_len == 1 apb_ctl_date = self.parent.read_reg(self.parent.REGS.APB_CTL_DATE_ADDR) rev_bit2 = ( apb_ctl_date >> self.parent.REGS.APB_CTL_DATE_S diff --git a/espefuse/efuse/esp32/mem_definition.py b/espefuse/efuse/esp32/mem_definition.py index 0e09030c5..7d29a010a 100644 --- a/espefuse/efuse/esp32/mem_definition.py +++ b/espefuse/efuse/esp32/mem_definition.py @@ -4,7 +4,17 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +import copy +import os + +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) class EfuseDefineRegisters(EfuseRegistersBase): @@ -56,11 +66,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_RD_CHIP_VER_REV2 = 1 << 20 -# fmt: off class EfuseDefineBlocks(EfuseBlocksBase): - __base_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_regs + 0x000, __base_regs + 0x01C, None, None, 7, None), @@ -68,6 +77,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK2", ["secure_boot_v1", "secure_boot_v2"], 2, __base_regs + 0x058, __base_regs + 0x0B8, 8, 1, 8, None), ("BLOCK3", [], 3, __base_regs + 0x078, __base_regs + 0x0D8, 9, 2, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -79,87 +89,91 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # Lists of efuse fields - EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('WR_DIS', "efuse", 0, 0, 0, "uint:16", 1, None, None, "Efuse write disable mask", None), - ('RD_DIS', "efuse", 0, 0, 16, "uint:4", 0, None, None, "Efuse read disable mask", None), - ('CODING_SCHEME', "efuse", 0, 6, 0, "uint:2", 10, 3, None, "Efuse variable block length scheme", - {0: "NONE (BLK1-3 len=256 bits)", - 1: "3/4 (BLK1-3 len=192 bits)", - 2: "REPEAT (BLK1-3 len=128 bits) not supported", - 3: "NONE (BLK1-3 len=256 bits)"}), - ('KEY_STATUS', "efuse", 0, 6, 10, "bool", 10, 3, None, "Usage of efuse block 3 (reserved)", None), - ('MAC', "identity", 0, 1, 0, "bytes:6", 3, None, "mac", "Factory MAC Address", None), - ('MAC_CRC', "identity", 0, 2, 16, "uint:8", 3, None, None, "CRC8 for factory MAC address", None), - ('CHIP_VER_REV1', "identity", 0, 3, 15, "bool", 3, None, None, "Silicon Revision 1", None), - ('CHIP_VER_REV2', "identity", 0, 5, 20, "bool", 6, None, None, "Silicon Revision 2", None), - ("WAFER_VERSION_MINOR", "identity", 0, 5, 24, "uint:2", 6, None, None, "WAFER VERSION MINOR", None), - ('CHIP_PACKAGE', "identity", 0, 3, 9, "uint:3", 3, None, None, "Chip package identifier", None), - ('CHIP_PACKAGE_4BIT', "identity", 0, 3, 2, "uint:1", 3, None, None, "Chip package identifier #4bit", None), - ('XPD_SDIO_FORCE', "config", 0, 4, 16, "bool", 5, None, None, "Ignore MTDI pin (GPIO12) for VDD_SDIO on reset", None), - ('XPD_SDIO_REG', "config", 0, 4, 14, "bool", 5, None, None, "If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset", None), - ('XPD_SDIO_TIEH', "config", 0, 4, 15, "bool", 5, None, None, "If XPD_SDIO_FORCE & XPD_SDIO_REG", - {1: "3.3V", - 0: "1.8V"}), - ('CLK8M_FREQ', "config", 0, 4, 0, "uint:8", None, None, None, "8MHz clock freq override", None), - ('SPI_PAD_CONFIG_CLK', "config", 0, 5, 0, "uint:5", 6, None, "spipin", "Override SD_CLK pad (GPIO6/SPICLK)", None), - ('SPI_PAD_CONFIG_Q', "config", 0, 5, 5, "uint:5", 6, None, "spipin", "Override SD_DATA_0 pad (GPIO7/SPIQ)", None), - ('SPI_PAD_CONFIG_D', "config", 0, 5, 10, "uint:5", 6, None, "spipin", "Override SD_DATA_1 pad (GPIO8/SPID)", None), - ('SPI_PAD_CONFIG_HD', "config", 0, 3, 4, "uint:5", 6, None, "spipin", "Override SD_DATA_2 pad (GPIO9/SPIHD)", None), - ('SPI_PAD_CONFIG_CS0', "config", 0, 5, 15, "uint:5", 6, None, "spipin", "Override SD_CMD pad (GPIO11/SPICS0)", None), - ('DISABLE_SDIO_HOST', "config", 0, 6, 3, "bool", None, None, None, "Disable SDIO host", None), - ('FLASH_CRYPT_CNT', "security", 0, 0, 20, "uint:7", 2, None, "bitcount", "Flash encryption mode counter", None), - ('UART_DOWNLOAD_DIS', "security", 0, 0, 27, "bool", 2, None, None, "Disable UART download mode (ESP32 rev3 only)", None), - ('FLASH_CRYPT_CONFIG', "security", 0, 5, 28, "uint:4", 10, 3, None, "Flash encryption config (key tweak bits)", None), - ('CONSOLE_DEBUG_DISABLE', "security", 0, 6, 2, "bool", 15, None, None, "Disable ROM BASIC interpreter fallback", None), - ('ABS_DONE_0', "security", 0, 6, 4, "bool", 12, None, None, "Secure boot V1 is enabled for bootloader image", None), - ('ABS_DONE_1', "security", 0, 6, 5, "bool", 13, None, None, "Secure boot V2 is enabled for bootloader image", None), - ('JTAG_DISABLE', "security", 0, 6, 6, "bool", 14, None, None, "Disable JTAG", None), - ('DISABLE_DL_ENCRYPT', "security", 0, 6, 7, "bool", 15, None, None, "Disable flash encryption in UART bootloader", None), - ('DISABLE_DL_DECRYPT', "security", 0, 6, 8, "bool", 15, None, None, "Disable flash decryption in UART bootloader", None), - ('DISABLE_DL_CACHE', "security", 0, 6, 9, "bool", 15, None, None, "Disable flash cache in UART bootloader", None), - ('BLK3_PART_RESERVE', "calibration", 0, 3, 14, "bool", 10, 3, None, "BLOCK3 partially served for ADC calibration data", None), - ('ADC_VREF', "calibration", 0, 4, 8, "uint:5", 0, None, "vref", "Voltage reference calibration", None), - ('MAC_VERSION', "identity", 3, 5, 24, "uint:8", 9, 2, None, "Version of the MAC field", - {1: "Custom MAC in BLOCK3"}), - ] - - # if MAC_VERSION is set "1", these efuse fields are in BLOCK3: - CUSTOM_MAC = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('CUSTOM_MAC', "identity", 3, 0, 8, "bytes:6", 9, 2, "mac", "Custom MAC", None), - ('CUSTOM_MAC_CRC', "identity", 3, 0, 0, "uint:8", 9, 2, None, "CRC of custom MAC", None), - ] - - # The len of fields depends on coding scheme: for CODING_SCHEME_NONE - KEYBLOCKS_256 = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK1', "security", 1, 0, 0, "bytes:32", 7, 0, "keyblock", "Flash encryption key", None), - ('BLOCK2', "security", 2, 0, 0, "bytes:32", 8, 1, "keyblock", "Secure boot key", None), - ('BLOCK3', "security", 3, 0, 0, "bytes:32", 9, 2, "keyblock", "Variable Block 3", None), - ] - - # The len of fields depends on coding scheme: for CODING_SCHEME_34 - KEYBLOCKS_192 = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK1', "security", 1, 0, 0, "bytes:24", 7, 0, "keyblock", "Flash encryption key", None), - ('BLOCK2', "security", 2, 0, 0, "bytes:24", 8, 1, "keyblock", "Secure boot key", None), - ('BLOCK3', "security", 3, 0, 0, "bytes:24", 9, 2, "keyblock", "Variable Block 3", None), - ] - - # if BLK3_PART_RESERVE is set, these efuse fields are in BLOCK3: - ADC_CALIBRATION = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('ADC1_TP_LOW', "calibration", 3, 3, 0, "uint:7", 9, 2, "adc_tp", "ADC1 150mV reading", None), - ('ADC1_TP_HIGH', "calibration", 3, 3, 7, "uint:9", 9, 2, "adc_tp", "ADC1 850mV reading", None), - ('ADC2_TP_LOW', "calibration", 3, 3, 16, "uint:7", 9, 2, "adc_tp", "ADC2 150mV reading", None), - ('ADC2_TP_HIGH', "calibration", 3, 3, 23, "uint:9", 9, 2, "adc_tp", "ADC2 850mV reading", None), - ] - - CALC = [ - ("WAFER_VERSION_MAJOR", "identity", 0, None, None, "uint:3", None, None, "wafer", "calc WAFER VERSION MAJOR from CHIP_VER_REV1 and CHIP_VER_REV2 and apb_ctl_date (read only)", None), - ('PKG_VERSION', "identity", 0, None, None, "uint:4", None, None, "pkg", "calc Chip package = CHIP_PACKAGE_4BIT << 3 + CHIP_PACKAGE (read only)", None), - ] -# fmt: on + def __init__(self) -> None: + self.EFUSES = [] + # if MAC_VERSION is set "1", these efuse fields are in BLOCK3: + self.CUSTOM_MAC = [] + # The len of fields depends on coding scheme: for CODING_SCHEME_NONE + self.KEYBLOCKS_256 = [] + # The len of fields depends on coding scheme: for CODING_SCHEME_34 + self.KEYBLOCKS_192 = [] + # if BLK3_PART_RESERVE is set, these efuse fields are in BLOCK3: + self.ADC_CALIBRATION = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name == "BLOCK1" or efuse.name == "BLOCK2": + self.KEYBLOCKS_256.append(efuse) + BLOCK = copy.deepcopy(efuse) + BLOCK.type = "bytes:24" + BLOCK.bit_len = 24 * 8 + self.KEYBLOCKS_192.append(BLOCK) + self.ALL_EFUSES[i] = None + + elif efuse.name == "MAC_VERSION": + # A field from BLOCK3, It is used as a template + BLOCK3 = copy.deepcopy(efuse) + BLOCK3.name = "BLOCK3" + BLOCK3.block = 3 + BLOCK3.word = 0 + BLOCK3.pos = 0 + BLOCK3.bit_len = 32 * 8 + BLOCK3.type = "bytes:32" + BLOCK3.category = "security" + BLOCK3.class_type = "keyblock" + BLOCK3.description = "Variable Block 3" + self.KEYBLOCKS_256.append(BLOCK3) + + BLOCK3 = copy.deepcopy(BLOCK3) + BLOCK3.type = "bytes:24" + BLOCK3.bit_len = 24 * 8 + self.KEYBLOCKS_192.append(BLOCK3) + + elif efuse.category == "calibration" and efuse.block == 3: + self.ADC_CALIBRATION.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.name in ["CUSTOM_MAC_CRC", "CUSTOM_MAC"]: + self.CUSTOM_MAC.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "spi pad": + efuse.class_type = "spipin" + + f = Field() + f.name = "WAFER_VERSION_MAJOR" + f.block = 0 + f.bit_len = 3 + f.type = f"uint:{f.bit_len}" + f.category = "identity" + f.class_type = "wafer" + f.description = "calc WAFER VERSION MAJOR from CHIP_VER_REV1 and CHIP_VER_REV2 and apb_ctl_date (read only)" + self.CALC.append(f) + + f = Field() + f.name = "PKG_VERSION" + f.block = 0 + f.bit_len = 4 + f.type = f"uint:{f.bit_len}" + f.category = "identity" + f.class_type = "pkg" + f.description = ( + "calc Chip package = CHIP_PACKAGE_4BIT << 3 + CHIP_PACKAGE (read only)" + ) + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32c2/emulate_efuse_controller.py b/espefuse/efuse/esp32c2/emulate_efuse_controller.py index d7323ca90..f08a170c4 100644 --- a/espefuse/efuse/esp32c2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c2/emulate_efuse_controller.py @@ -124,8 +124,7 @@ def get_read_disable_mask(blk): else: block.set(0) else: - for e in self.Fields.EFUSES: - field = self.Fields.get(e) + for field in self.Fields.EFUSES: if ( blk.id == field.block and field.read_disable_bit is not None diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index 65e1f606a..d2a6e1b6c 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -84,53 +84,40 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: if self["BLK_VERSION_MINOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -295,13 +282,13 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseTempSensor(EfuseField): @@ -377,22 +364,13 @@ def print_field(e, new_value): class EfuseKeyPurposeField(EfuseField): KEY_PURPOSES = [ - ("USER", 0, None), # User purposes (software-only use) - ( - "XTS_AES_128_KEY", - 1, - None, - ), # (whole 256bits) XTS_AES_128_KEY (flash/PSRAM encryption) - ( - "XTS_AES_128_KEY_DERIVED_FROM_128_EFUSE_BITS", - 2, - None, - ), # (lo 128bits) XTS_AES_128_KEY (flash/PSRAM encryption) - ( - "SECURE_BOOT_DIGEST", - 3, - "DIGEST", - ), # (hi 128bits)SECURE_BOOT_DIGEST (Secure Boot key digest) + # fmt: off + ("USER", 0, None), # User purposes (software-only use) + ("XTS_AES_128_KEY", 1, None), # (whole 256bits) flash/PSRAM encryption + ("XTS_AES_128_KEY_DERIVED_FROM_128_EFUSE_BITS", 2, None), # (lo 128bits) flash/PSRAM encryption + ("SECURE_BOOT_DIGEST", 3, "DIGEST"), + # (hi 128bits) Secure Boot key digest + # fmt: on ] KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] diff --git a/espefuse/efuse/esp32c2/mem_definition.py b/espefuse/efuse/esp32c2/mem_definition.py index 5b8c7d4df..7adb0111f 100644 --- a/espefuse/efuse/esp32c2/mem_definition.py +++ b/espefuse/efuse/esp32c2/mem_definition.py @@ -4,36 +4,43 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +import copy +import os +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, +) -# fmt: off -class EfuseDefineRegisters(EfuseRegistersBase): - EFUSE_MEM_SIZE = (0x01FC + 4) +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x60008800 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_PGM_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x88 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x8C - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x90 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x94 + DR_REG_EFUSE_BASE = 0x60008800 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_PGM_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x88 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x8C + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x90 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x94 EFUSE_RD_REPEAT_ERR_REG = DR_REG_EFUSE_BASE + 0x80 - EFUSE_RD_RS_ERR_REG = DR_REG_EFUSE_BASE + 0x84 - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 + EFUSE_RD_RS_ERR_REG = DR_REG_EFUSE_BASE + 0x84 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 BLOCK_ERRORS = [ # error_reg, err_num_mask, err_num_offs, fail_bit - (EFUSE_RD_REPEAT_ERR_REG, None, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR_REG, 0x7, 0, 3), # BLOCK1 - (EFUSE_RD_RS_ERR_REG, 0x7, 4, 7), # BLOCK2 - (EFUSE_RD_RS_ERR_REG, 0x7, 8, 11), # BLOCK3 + (EFUSE_RD_REPEAT_ERR_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR_REG, 0x7, 0, 3), # BLOCK1 + (EFUSE_RD_RS_ERR_REG, 0x7, 4, 7), # BLOCK2 + (EFUSE_RD_RS_ERR_REG, 0x7, 8, 11), # BLOCK3 ] EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x118 @@ -58,10 +65,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", ["BLOCK0"], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 2, None), @@ -69,6 +76,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK2", ["BLOCK2"], 2, __base_rd_regs + 0x040, __base_wr_regs, 6, None, 8, None), ("BLOCK_KEY0", ["BLOCK3"], 3, __base_rd_regs + 0x060, __base_wr_regs, 7, [0, 1], 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -82,87 +90,58 @@ def get_burn_block_data_names(self): return list_of_names def get_blocks_for_keys(self): - return ['BLOCK_KEY0'] + return ["BLOCK_KEY0"] class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:8", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:2", 0, None, None, "Disables software reading from BLOCK3", None), - ("WDT_DELAY_SEL", "WDT config", 0, 1, 2, "uint:2", 1, None, None, "RTC WDT timeout threshold", None), - ("DIS_PAD_JTAG", "jtag config", 0, 1, 4, "bool", 1, None, None, "Permanently disable JTAG access via pads" - "USB JTAG is controlled separately", None), - ("DIS_DOWNLOAD_ICACHE", "security", 0, 1, 5, "bool", 1, None, None, "Disables iCache in download mode", None), - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 6, "bool", 2, None, None, "Disables flash encryption in Download boot modes", - None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 1, 7, "uint:3", 2, None, None, "Enables encryption and decryption, when an SPI boot" - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("XTS_KEY_LENGTH_256", "security", 0, 1, 10, "bool", 2, None, None, "Flash encryption key length", - {0: "128 bits key", - 1: "256 bits key"}), - ("UART_PRINT_CONTROL", "config", 0, 1, 11, "uint:2", 3, None, None, "Set UART boot message output mode", - {0: "Force print", - 1: "Low-level print controlled by GPIO 8", - 3: "High-level print controlled by GPIO 8", - 7: "Print force disabled"}), - ("FORCE_SEND_RESUME", "config", 0, 1, 13, "bool", 3, None, None, "Force ROM code to send a resume cmd during SPI boot", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 1, 14, "bool", 3, None, None, "Disables all Download boot modes", None), - ("DIS_DIRECT_BOOT", "config", 0, 1, 15, "bool", 3, None, None, "Disable direct_boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 1, 16, "bool", 3, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("FLASH_TPUW", "flash config", 0, 1, 17, "uint:4", 3, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("SECURE_BOOT_EN", "security", 0, 1, 21, "bool", 2, None, None, "Configures secure boot", None), - ("SECURE_VERSION", "identity", 0, 1, 22, "uint:4", 4, None, "bitcount", "Secure version (anti-rollback feature)", None), - ("CUSTOM_MAC_USED", "identity", 0, 1, 26, "bool", 4, None, None, "Enable CUSTOM_MAC programming", None), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 1, 27, "bool", 4, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 1, 28, "bool", 4, None, None, "Disables check of blk version major", None), - - # - # Parameters in BLOCK1 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("CUSTOM_MAC", "identity", 1, 0, 0, "bytes:6", 5, None, 'mac', "Custom MAC addr", None), - - # - # Parameters in BLOCK2 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 2, 0, 0, "bytes:6", 6, None, 'mac', "Factory MAC Address", None), - ("WAFER_VERSION_MINOR", "identity", 2, 1, 16, "uint:4", 6, None, None, "Minor WAFER version", None), - ("WAFER_VERSION_MAJOR", "identity", 2, 1, 20, "uint:2", 6, None, None, "Major WAFER version", None), - ("PKG_VERSION", "identity", 2, 1, 22, "uint:3", 6, None, None, "Package version", None), - ("BLK_VERSION_MINOR", "identity", 2, 1, 25, "uint:3", 6, None, None, "Minor version of BLOCK2", - {0: "No calibration", 1: "With calibration"}), - - ("BLK_VERSION_MAJOR", "identity", 2, 1, 28, "uint:2", 6, None, None, "Major version of BLOCK2", None), - ("LDO_VOL_BIAS_CONFIG_HIGH", "ldo", 2, 2, 0, "uint:27", 6, None, None, "", None), - ("PVT_LOW", "pvt", 2, 2, 27, "uint:5", 6, None, None, "", None), - ("PVT_HIGH", "pvt", 2, 3, 0, "uint:10", 6, None, None, "", None), - ("ADC_CALIBRATION_0", "adc_calib", 2, 3, 10, "uint:22", 6, None, None, "", None), - ("ADC_CALIBRATION_1", "adc_calib", 2, 4, 0, "uint:32", 6, None, None, "", None), - ("ADC_CALIBRATION_2", "adc_calib", 2, 5, 0, "uint:32", 6, None, None, "", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_KEY0', "security", 3, 0, 0, "bytes:32", 7, [0, 1], "keyblock", "BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption", None), - ('BLOCK_KEY0_LOW_128', "security", 3, 0, 0, "bytes:16", 7, 0, "keyblock", "BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash Encryption", None), - ('BLOCK_KEY0_HI_128', "security", 3, 4, 0, "bytes:16", 7, 1, "keyblock", "BLOCK_KEY0 - higher 128-bits. 128-bits key of Secure Boot.", None), - ] - - # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in ["BLOCK_KEY0"]: + self.KEYBLOCKS.append(efuse) + BLOCK_KEY0_LOW_128 = copy.deepcopy(efuse) + BLOCK_KEY0_LOW_128.name = "BLOCK_KEY0_LOW_128" + BLOCK_KEY0_LOW_128.type = "bytes:16" + BLOCK_KEY0_LOW_128.bit_len = 16 * 8 + BLOCK_KEY0_LOW_128.description = ( + "BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash Encryption" + ) + BLOCK_KEY0_LOW_128.read_disable_bit = efuse.read_disable_bit[0] + self.KEYBLOCKS.append(BLOCK_KEY0_LOW_128) + BLOCK_KEY0_HI_128 = copy.deepcopy(efuse) + BLOCK_KEY0_HI_128.name = "BLOCK_KEY0_HI_128" + BLOCK_KEY0_HI_128.word = 4 + BLOCK_KEY0_HI_128.type = "bytes:16" + BLOCK_KEY0_HI_128.bit_len = 16 * 8 + BLOCK_KEY0_HI_128.description = ( + "BLOCK_KEY0 - higher 128-bits. 128-bits key of Secure Boot" + ) + BLOCK_KEY0_HI_128.read_disable_bit = efuse.read_disable_bit[1] + self.KEYBLOCKS.append(BLOCK_KEY0_HI_128) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index c77ee9b88..5f68c2ae4 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -84,59 +84,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: if self["BLK_VERSION_MAJOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -301,20 +285,22 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, "wafer": EfuseWafer, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseWafer(EfuseField): def get(self, from_read=True): hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 return (hi_bits << 3) + lo_bits def save(self, new_value): diff --git a/espefuse/efuse/esp32c3/mem_definition.py b/espefuse/efuse/esp32c3/mem_definition.py index 9384e0dab..610d64e17 100644 --- a/espefuse/efuse/esp32c3/mem_definition.py +++ b/espefuse/efuse/esp32c3/mem_definition.py @@ -4,24 +4,31 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +import os +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) -# fmt: off -class EfuseDefineRegisters(EfuseRegistersBase): - EFUSE_MEM_SIZE = (0x01FC + 4) +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x60008800 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 - EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 - EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + DR_REG_EFUSE_BASE = 0x60008800 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 @@ -32,41 +39,41 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 # this chip has a design error so fail_bit is shifted by one block but err_num is in the correct place BLOCK_FAIL_BIT = [ # error_reg, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 7), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 11), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 15), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 19), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 23), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 27), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 31), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR1_REG, 3), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 7), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, None), # BLOCK_SYS_DATA2 + (EFUSE_RD_REPEAT_ERR0_REG, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 7), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 11), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 15), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 19), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 23), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 27), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 31), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR1_REG, 3), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 7), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, None), # BLOCK_SYS_DATA2 ] BLOCK_NUM_ERRORS = [ # error_reg, err_num_mask, err_num_offs - (EFUSE_RD_REPEAT_ERR0_REG, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4), # BLOCK_SYS_DATA2 + (EFUSE_RD_REPEAT_ERR0_REG, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4), # BLOCK_SYS_DATA2 ] # EFUSE_WR_TIM_CONF2_REG @@ -87,10 +94,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), @@ -105,6 +112,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -119,141 +127,63 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Table 51: Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), - ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), - ("DIS_USB_JTAG", "usb config", 0, 1, 9, "bool", 2, None, None, "Disables USB JTAG. " - "JTAG access via pads is controlled separately", None), - ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), - ("DIS_USB_DEVICE", "usb config", 0, 1, 11, "bool", 2, None, None, "Disables USB DEVICE", None), - ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), - ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), - ("SOFT_DIS_JTAG", "jtag config", 0, 1, 16, "uint:3", 2, None, None, "Software disables JTAG. When software disabled, " - "JTAG can be activated temporarily by HMAC peripheral", - None), - ("DIS_PAD_JTAG", "jtag config", 0, 1, 19, "bool", 2, None, None, "Permanently disable JTAG access via pads. " - "USB JTAG is controlled separately.", None), - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 20, "bool", 2, None, None, "Disables flash encryption when in download boot modes", - None), - ("USB_EXCHG_PINS", "usb config", 0, 1, 25, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), - ("VDD_SPI_AS_GPIO", "config", 0, 1, 26, "bool", 30, None, None, "Set this bit to vdd spi pin function as gpio", None), - ("BTLC_GPIO_ENABLE", "config", 0, 1, 27, "uint:2", 30, None, None, "Enable btlc gpio", None), - ("POWERGLITCH_EN", "config", 0, 1, 29, "bool", 30, None, None, "Set this bit to enable power glitch function", None), - ("POWER_GLITCH_DSENSE", "config", 0, 1, 30, "uint:2", 30, None, None, "Sample delay configuration of power glitch", None), - ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "bool", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "If set, revokes use of secure boot key digest 0", None), - ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "If set, revokes use of secure boot key digest 1", None), - ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "If set, revokes use of secure boot key digest 2", None), - ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), - ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), - ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), - ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), - ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), - ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), - ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), - ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", - None), - ("FLASH_TPUW", "flash config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), - ("DIS_DIRECT_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables direct boot mode", None), - ("DIS_USB_SERIAL_JTAG_ROM_PRINT", "config", 0, 4, 2, "bool", 18, None, None, "Disables USB-Serial-JTAG ROM printing", None), - ("DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE", "usb config", 0, 4, 4, "bool", 18, None, None, "Disables USB-Serial-JTAG download feature in " - "UART download boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", - {0: "Enabled", - 1: "Enable when GPIO8 is low at reset", - 2: "Enable when GPIO8 is high at reset", - 3: "Disabled"}), - ("FORCE_SEND_RESUME", "config", 0, 4, 13, "bool", 18, None, None, "Force ROM code to send a resume command during SPI boot" - "during SPI boot", None), - ("SECURE_VERSION", "identity", 0, 4, 14, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", - None), - ("ERR_RST_ENABLE", "config", 0, 4, 31, "bool", 19, None, None, "Use BLOCK0 to check error record registers", - {0: "without check", - 1: "with check"}), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), - # - # Table 53: Parameters in BLOCK1-10 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), - ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), - ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), - ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), - ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), - ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), - ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), - ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), - ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), - ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), - ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), - ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), - - ("WAFER_VERSION_MINOR_LO", "identity", 1, 3, 18, "uint:3", 20, None, None, "WAFER_VERSION_MINOR least significant bits", None), - ("PKG_VERSION", "identity", 1, 3, 21, "uint:3", 20, None, None, "Package version", None), - ("BLK_VERSION_MINOR", "identity", 1, 3, 24, "uint:3", 20, None, None, "BLOCK version minor", None), - ("WAFER_VERSION_MINOR_HI", "identity", 1, 5, 23, "uint:1", 20, None, None, "WAFER_VERSION_MINOR most significant bits", None), - ("WAFER_VERSION_MAJOR", "identity", 1, 5, 24, "uint:2", 20, None, None, "WAFER_VERSION_MAJOR", None), - - ("OPTIONAL_UNIQUE_ID", "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), - ("BLK_VERSION_MAJOR", "identity", 2, 4, 0, "uint:2", 21, None, None, "BLOCK version major", - {0: "No calibration", - 1: "With calibration"}), - ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), - ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), - ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), - ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), - ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), - ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), - ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), - ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, "keyblock", "System data (part 2)", None), - ] - - # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "Temperature calibration", None), - ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "ADC1 calibration 1", None), - ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "ADC1 calibration 2", None), - ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "ADC1 calibration 3", None), - ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "ADC1 calibration 4", None), - ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "ADC2 calibration 5", None), - ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "ADC2 calibration 6", None), - ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "ADC2 calibration 7", None), - ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "ADC2 calibration 8", None), - ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "ADC1 calibration 9", None), - ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "ADC1 calibration 10", None), - ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "ADC1 calibration 11", None), - ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "ADC1 calibration 12", None), - ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "ADC2 calibration 13", None), - ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "ADC2 calibration 14", None), - ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "ADC2 calibration 15", None), - ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "ADC2 calibration 16", None), - ] - - CALC = [ - ("WAFER_VERSION_MINOR", "identity", 0, None, None, "uint:4", None, None, "wafer", "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)", None), - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + # It is not functional, a bug in the hardware + elif efuse.name == "JTAG_SEL_ENABLE": + self.ALL_EFUSES[i] = None + + f = Field() + f.name = "WAFER_VERSION_MINOR" + f.block = 0 + f.bit_len = 4 + f.type = f"uint:{f.bit_len}" + f.category = "identity" + f.class_type = "wafer" + f.description = "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)" + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index 913fa284c..2d09c9fd3 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -84,59 +84,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLK_VERSION_MAJOR"].get() == 1: + if self["BLK_VERSION_MINOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -257,6 +241,8 @@ def set_efuse_timing(self): def get_coding_scheme_warnings(self, silent=False): """Check if the coding scheme has detected any errors.""" + old_addr_reg = 0 + reg_value = 0 ret_fail = False for block in self.blocks: if block.id == 0: @@ -270,20 +256,16 @@ def get_coding_scheme_warnings(self, silent=False): block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: - addr_reg_f, fail_bit = self.REGS.BLOCK_FAIL_BIT[block.id] - if fail_bit is None: - block.fail = False - else: - block.fail = self.read_reg(addr_reg_f) & (1 << fail_bit) != 0 - - addr_reg_n, num_mask, num_offs = self.REGS.BLOCK_NUM_ERRORS[block.id] - if num_mask is None or num_offs is None: - block.num_errors = 0 - else: - block.num_errors = ( - self.read_reg(addr_reg_n) >> num_offs - ) & num_mask - + addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[ + block.id + ] + if err_num_mask is None or err_num_offs is None or fail_bit is None: + continue + if addr_reg != old_addr_reg: + old_addr_reg = addr_reg + reg_value = self.read_reg(addr_reg) + block.fail = reg_value & (1 << fail_bit) != 0 + block.num_errors = (reg_value >> err_num_offs) & err_num_mask ret_fail |= block.fail if not silent and (block.fail or block.num_errors): print( @@ -301,20 +283,22 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, "wafer": EfuseWafer, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseWafer(EfuseField): def get(self, from_read=True): hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 return (hi_bits << 3) + lo_bits def save(self, new_value): diff --git a/espefuse/efuse/esp32c6/mem_definition.py b/espefuse/efuse/esp32c6/mem_definition.py index 47045232e..60e4b6cde 100644 --- a/espefuse/efuse/esp32c6/mem_definition.py +++ b/espefuse/efuse/esp32c6/mem_definition.py @@ -4,24 +4,30 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +import os +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, +) -# fmt: off -class EfuseDefineRegisters(EfuseRegistersBase): - EFUSE_MEM_SIZE = (0x01FC + 4) +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x600B0800 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 - EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 - EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + DR_REG_EFUSE_BASE = 0x600B0800 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 @@ -32,41 +38,25 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 - - # this chip has a design error so fail_bit is shifted by one block but err_num is in the correct place - BLOCK_FAIL_BIT = [ - # error_reg, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 7), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 11), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 15), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 19), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 23), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 27), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 31), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR1_REG, 3), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 7), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, None), # BLOCK_SYS_DATA2 - ] - - BLOCK_NUM_ERRORS = [ - # error_reg, err_num_mask, err_num_offs - (EFUSE_RD_REPEAT_ERR0_REG, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4), # BLOCK_SYS_DATA2 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 + + BLOCK_ERRORS = [ + # error_reg, err_num_mask, err_num_offs, fail_bit + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 ] # EFUSE_WR_TIM_CONF2_REG @@ -87,10 +77,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), @@ -105,6 +95,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -119,155 +110,49 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Table 51: Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), - ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), - ("DIS_USB_JTAG", "usb config", 0, 1, 9, "bool", 2, None, None, "Disables USB JTAG. " - "JTAG access via pads is controlled separately", None), - ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), - ("DIS_USB_DEVICE", "usb config", 0, 1, 11, "bool", 2, None, None, "Disables USB DEVICE", None), - ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), - ("DIS_USB", "usb config", 0, 1, 13, "bool", 2, None, None, "Disables the USB OTG hardware", None), - ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), - ("JTAG_SEL_ENABLE", "jtag config", 0, 1, 15, "bool", 2, None, None, "Set this bit to enable selection between " - "usb_to_jtag and pad_to_jtag through strapping " - "gpio10 when both reg_dis_usb_jtag and " - "reg_dis_pad_jtag are equal to 0.", None), - ("SOFT_DIS_JTAG", "jtag config", 0, 1, 16, "uint:3", 2, None, None, "Software disables JTAG. When software disabled, " - "JTAG can be activated temporarily by HMAC peripheral", - None), - ("DIS_PAD_JTAG", "jtag config", 0, 1, 19, "bool", 2, None, None, "Permanently disable JTAG access via pads. " - "USB JTAG is controlled separately.", None), - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 20, "bool", 2, None, None, "Disables flash encryption when in download boot modes", - None), - ("USB_EXCHG_PINS", "usb config", 0, 1, 25, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), - ("VDD_SPI_AS_GPIO", "config", 0, 1, 26, "bool", 30, None, None, "Set this bit to vdd spi pin function as gpio", None), - ("BTLC_GPIO_ENABLE", "config", 0, 1, 27, "uint:2", 30, None, None, "Enable btlc gpio", None), - ("POWERGLITCH_EN", "config", 0, 1, 29, "bool", 30, None, None, "Set this bit to enable power glitch function", None), - ("POWER_GLITCH_DSENSE", "config", 0, 1, 30, "uint:2", 30, None, None, "Sample delay configuration of power glitch", None), - ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "bool", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "If set, revokes use of secure boot key digest 0", None), - ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "If set, revokes use of secure boot key digest 1", None), - ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "If set, revokes use of secure boot key digest 2", None), - ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), - ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), - ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), - ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), - ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), - ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), - ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), - ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", - None), - ("FLASH_TPUW", "flash config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), - ("DIS_DIRECT_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables direct boot mode", None), - ("UART_PRINT_CHANNEL", "config", 0, 4, 2, "bool", 18, None, None, "Selects the default UART for printing boot msg", - {0: "UART0", - 1: "UART1"}), - ("FLASH_ECC_MODE", "flash config", 0, 4, 3, "bool", 18, None, None, "Set this bit to set flsah ecc mode.", - {0: "flash ecc 16to18 byte mode", - 1: "flash ecc 16to17 byte mode"}), - ("DIS_USB_DOWNLOAD_MODE", "usb config", 0, 4, 4, "bool", 18, None, None, "Disables use of USB in UART download boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", - {0: "Enabled", - 1: "Enable when GPIO8 is low at reset", - 2: "Enable when GPIO8 is high at reset", - 3: "Disabled"}), - ("PIN_POWER_SELECTION", "VDD_SPI config", 0, 4, 8, "bool", 18, None, None, "GPIO33-GPIO37 power supply selection in ROM code", - {0: "VDD3P3_CPU", - 1: "VDD_SPI"}), - ("FLASH_TYPE", "flash config", 0, 4, 9, "bool", 18, None, None, "Selects SPI flash type", - {0: "4 data lines", - 1: "8 data lines"}), - ("FLASH_PAGE_SIZE", "flash config", 0, 4, 10, "uint:2", 18, None, None, "Flash page size", None), - ("FLASH_ECC_EN", "flash config", 0, 4, 12, "bool", 18, None, None, "Enable ECC for flash boot", None), - ("FORCE_SEND_RESUME", "config", 0, 4, 13, "bool", 18, None, None, "Force ROM code to send a resume command during SPI boot" - "during SPI boot", None), - ("SECURE_VERSION", "identity", 0, 4, 14, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", - None), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), - # - # Table 53: Parameters in BLOCK1-10 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), - ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), - ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), - ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), - ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), - ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), - ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), - ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), - ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), - ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), - ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), - ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), - - ("WAFER_VERSION_MINOR_LO", "identity", 1, 3, 18, "uint:3", 20, None, None, "WAFER_VERSION_MINOR least significant bits", None), - ("PKG_VERSION", "identity", 1, 3, 21, "uint:3", 20, None, None, "Package version", None), - ("BLK_VERSION_MINOR", "identity", 1, 3, 24, "uint:3", 20, None, None, "BLOCK version minor", None), - ("WAFER_VERSION_MINOR_HI", "identity", 1, 5, 23, "uint:1", 20, None, None, "WAFER_VERSION_MINOR most significant bits", None), - ("WAFER_VERSION_MAJOR", "identity", 1, 5, 24, "uint:2", 20, None, None, "WAFER_VERSION_MAJOR", None), - - ("OPTIONAL_UNIQUE_ID", "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), - ("BLK_VERSION_MAJOR", "identity", 2, 4, 0, "uint:2", 21, None, None, "BLOCK version major", - {0: "No calibration", - 1: "With calibration"}), - ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), - ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), - ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), - ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), - ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), - ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), - ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), - ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, "keyblock", "System data (part 2)", None), - ] - - # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "Temperature calibration", None), - ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "ADC1 calibration 1", None), - ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "ADC1 calibration 2", None), - ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "ADC1 calibration 3", None), - ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "ADC1 calibration 4", None), - ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "ADC2 calibration 5", None), - ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "ADC2 calibration 6", None), - ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "ADC2 calibration 7", None), - ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "ADC2 calibration 8", None), - ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "ADC1 calibration 9", None), - ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "ADC1 calibration 10", None), - ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "ADC1 calibration 11", None), - ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "ADC1 calibration 12", None), - ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "ADC2 calibration 13", None), - ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "ADC2 calibration 14", None), - ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "ADC2 calibration 15", None), - ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "ADC2 calibration 16", None), - ] - - CALC = [ - ("WAFER_VERSION_MINOR", "identity", 0, None, None, "uint:4", None, None, "wafer", "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)", None), - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32c6/operations.py b/espefuse/efuse/esp32c6/operations.py index 6cdbba21b..f37991cca 100644 --- a/espefuse/efuse/esp32c6/operations.py +++ b/espefuse/efuse/esp32c6/operations.py @@ -167,7 +167,8 @@ def add_commands(subparsers, efuses): p.add_argument( "mac", help="Custom MAC Address to burn given in hexadecimal format with bytes " - "separated by colons (e.g. AA:CD:EF:01:02:03).", + "separated by colons (e.g. AA:CD:EF:01:02:03). " + "Final CUSTOM_MAC = CUSTOM_MAC[48] + MAC_EXT[16]", type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), ) add_force_write_always(p) @@ -194,38 +195,29 @@ def set_flash_voltage(esp, efuses, args): def adc_info(esp, efuses, args): print("") # fmt: off - if efuses["BLK_VERSION_MAJOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) + if efuses["BLK_VERSION_MINOR"].get() == 1: + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) print("") - print("ADC1 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC1_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC1_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC1_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC1_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC1_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC1_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC1_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC1_MODE3_D2"].get())) - - print("") - print("ADC2 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC2_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC2_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC2_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC2_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC2_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC2_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) + print("ADC1 Calibration data stored in efuse BLOCK2:") + print(f"OCODE: {efuses['OCODE'].get()}") + print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") + print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") + print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") + print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") + print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") + print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") + print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") + print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") + print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") + print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") + print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") + print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") + print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") + print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") + print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") else: - print("BLK_VERSION_MAJOR = {}".format(efuses["BLK_VERSION_MAJOR"].get_meaning())) + print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) # fmt: on diff --git a/espefuse/efuse/esp32h2/emulate_efuse_controller.py b/espefuse/efuse/esp32h2/emulate_efuse_controller.py index c4c839da6..438061e6e 100644 --- a/espefuse/efuse/esp32h2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32h2/emulate_efuse_controller.py @@ -16,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-H2" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index b177228ed..5be835253 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -54,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm @@ -85,59 +84,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: if self["BLK_VERSION_MAJOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -259,6 +242,8 @@ def set_efuse_timing(self): def get_coding_scheme_warnings(self, silent=False): """Check if the coding scheme has detected any errors.""" + old_addr_reg = 0 + reg_value = 0 ret_fail = False for block in self.blocks: if block.id == 0: @@ -272,20 +257,16 @@ def get_coding_scheme_warnings(self, silent=False): block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: - addr_reg_f, fail_bit = self.REGS.BLOCK_FAIL_BIT[block.id] - if fail_bit is None: - block.fail = False - else: - block.fail = self.read_reg(addr_reg_f) & (1 << fail_bit) != 0 - - addr_reg_n, num_mask, num_offs = self.REGS.BLOCK_NUM_ERRORS[block.id] - if num_mask is None or num_offs is None: - block.num_errors = 0 - else: - block.num_errors = ( - self.read_reg(addr_reg_n) >> num_offs - ) & num_mask - + addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[ + block.id + ] + if err_num_mask is None or err_num_offs is None or fail_bit is None: + continue + if addr_reg != old_addr_reg: + old_addr_reg = addr_reg + reg_value = self.read_reg(addr_reg) + block.fail = reg_value & (1 << fail_bit) != 0 + block.num_errors = (reg_value >> err_num_offs) & err_num_mask ret_fail |= block.fail if not silent and (block.fail or block.num_errors): print( @@ -303,20 +284,22 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, "wafer": EfuseWafer, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseWafer(EfuseField): def get(self, from_read=True): hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 return (hi_bits << 3) + lo_bits def save(self, new_value): @@ -373,7 +356,11 @@ def check(self): def get(self, from_read=True): if self.name == "CUSTOM_MAC": - mac = self.get_raw(from_read)[::-1] + mac = self.get_raw(from_read)[::-1] + self.parent["MAC_EXT"].get_raw( + from_read + ) + elif self.name == "MAC": + mac = self.get_raw(from_read) + self.parent["MAC_EXT"].get_raw(from_read) else: mac = self.get_raw(from_read) return "%s %s" % (util.hexify(mac, ":"), self.check()) diff --git a/espefuse/efuse/esp32h2/mem_definition.py b/espefuse/efuse/esp32h2/mem_definition.py index ed89ca8d4..d548794f6 100644 --- a/espefuse/efuse/esp32h2/mem_definition.py +++ b/espefuse/efuse/esp32h2/mem_definition.py @@ -4,24 +4,26 @@ # # SPDX-License-Identifier: GPL-2.0-or-later +import os + +import yaml + from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase -# fmt: off class EfuseDefineRegisters(EfuseRegistersBase): - - EFUSE_MEM_SIZE = (0x01FC + 4) + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x600B0800 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 - EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 - EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + DR_REG_EFUSE_BASE = 0x600B0800 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 @@ -32,41 +34,25 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 - - # this chip has a design error so fail_bit is shifted by one block but err_num is in the correct place - BLOCK_FAIL_BIT = [ - # error_reg, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 7), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 11), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 15), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 19), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 23), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 27), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 31), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR1_REG, 3), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 7), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, None), # BLOCK_SYS_DATA2 - ] - - BLOCK_NUM_ERRORS = [ - # error_reg, err_num_mask, err_num_offs - (EFUSE_RD_REPEAT_ERR0_REG, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4), # BLOCK_SYS_DATA2 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 + + BLOCK_ERRORS = [ + # error_reg, err_num_mask, err_num_offs, fail_bit + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 ] # EFUSE_WR_TIM_CONF2_REG @@ -87,10 +73,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), @@ -105,6 +91,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -119,152 +106,49 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Table 51: Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), - ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), - ("DIS_USB_JTAG", "usb config", 0, 1, 9, "bool", 2, None, None, "Disables USB JTAG. " - "JTAG access via pads is controlled separately", None), - ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), - ("DIS_USB_DEVICE", "usb config", 0, 1, 11, "bool", 2, None, None, "Disables USB DEVICE", None), - ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), - ("DIS_USB", "usb config", 0, 1, 13, "bool", 2, None, None, "Disables the USB OTG hardware", None), - ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), - ("JTAG_SEL_ENABLE", "jtag config", 0, 1, 15, "bool", 2, None, None, "Set this bit to enable selection between " - "usb_to_jtag and pad_to_jtag through strapping " - "gpio10 when both reg_dis_usb_jtag and " - "reg_dis_pad_jtag are equal to 0.", None), - ("SOFT_DIS_JTAG", "jtag config", 0, 1, 16, "uint:3", 2, None, None, "Software disables JTAG. When software disabled, " - "JTAG can be activated temporarily by HMAC peripheral", - None), - ("DIS_PAD_JTAG", "jtag config", 0, 1, 19, "bool", 2, None, None, "Permanently disable JTAG access via pads. " - "USB JTAG is controlled separately.", None), - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 20, "bool", 2, None, None, "Disables flash encryption when in download boot modes", - None), - ("USB_EXCHG_PINS", "usb config", 0, 1, 25, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), - ("VDD_SPI_AS_GPIO", "config", 0, 1, 26, "bool", 30, None, None, "Set this bit to vdd spi pin function as gpio", None), - ("BTLC_GPIO_ENABLE", "config", 0, 1, 27, "uint:2", 30, None, None, "Enable btlc gpio", None), - ("POWERGLITCH_EN", "config", 0, 1, 29, "bool", 30, None, None, "Set this bit to enable power glitch function", None), - ("POWER_GLITCH_DSENSE", "config", 0, 1, 30, "uint:2", 30, None, None, "Sample delay configuration of power glitch", None), - ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "bool", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "If set, revokes use of secure boot key digest 0", None), - ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "If set, revokes use of secure boot key digest 1", None), - ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "If set, revokes use of secure boot key digest 2", None), - ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), - ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), - ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), - ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), - ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), - ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), - ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), - ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", - None), - ("FLASH_TPUW", "flash config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), - ("DIS_DIRECT_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables direct boot mode", None), - ("UART_PRINT_CHANNEL", "config", 0, 4, 2, "bool", 18, None, None, "Selects the default UART for printing boot msg", - {0: "UART0", - 1: "UART1"}), - ("FLASH_ECC_MODE", "flash config", 0, 4, 3, "bool", 18, None, None, "Set this bit to set flsah ecc mode.", - {0: "flash ecc 16to18 byte mode", - 1: "flash ecc 16to17 byte mode"}), - ("DIS_USB_DOWNLOAD_MODE", "usb config", 0, 4, 4, "bool", 18, None, None, "Disables use of USB in UART download boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", - {0: "Enabled", - 1: "Enable when GPIO8 is low at reset", - 2: "Enable when GPIO8 is high at reset", - 3: "Disabled"}), - ("PIN_POWER_SELECTION", "VDD_SPI config", 0, 4, 8, "bool", 18, None, None, "GPIO33-GPIO37 power supply selection in ROM code", - {0: "VDD3P3_CPU", - 1: "VDD_SPI"}), - ("FLASH_PAGE_SIZE", "flash config", 0, 4, 10, "uint:2", 18, None, None, "Flash page size", None), - ("FLASH_ECC_EN", "flash config", 0, 4, 12, "bool", 18, None, None, "Enable ECC for flash boot", None), - ("FORCE_SEND_RESUME", "config", 0, 4, 13, "bool", 18, None, None, "Force ROM code to send a resume command during SPI boot" - "during SPI boot", None), - ("SECURE_VERSION", "identity", 0, 4, 14, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", - None), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), - # - # Table 53: Parameters in BLOCK1-10 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), - ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), - ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), - ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), - ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), - ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), - ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), - ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), - ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), - ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), - ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), - ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), - - ("WAFER_VERSION_MINOR_LO", "identity", 1, 3, 18, "uint:3", 20, None, None, "WAFER_VERSION_MINOR least significant bits", None), - ("PKG_VERSION", "identity", 1, 3, 21, "uint:3", 20, None, None, "Package version", None), - ("BLK_VERSION_MINOR", "identity", 1, 3, 24, "uint:3", 20, None, None, "BLOCK version minor", None), - ("WAFER_VERSION_MINOR_HI", "identity", 1, 5, 23, "uint:1", 20, None, None, "WAFER_VERSION_MINOR most significant bits", None), - ("WAFER_VERSION_MAJOR", "identity", 1, 5, 24, "uint:2", 20, None, None, "WAFER_VERSION_MAJOR", None), - - ("OPTIONAL_UNIQUE_ID", "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), - ("BLK_VERSION_MAJOR", "identity", 2, 4, 0, "uint:2", 21, None, None, "BLOCK version major", - {0: "No calibration", - 1: "With calibration"}), - ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), - ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), - ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), - ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), - ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), - ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), - ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), - ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, "keyblock", "System data (part 2)", None), - ] - - # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "Temperature calibration", None), - ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "ADC1 calibration 1", None), - ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "ADC1 calibration 2", None), - ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "ADC1 calibration 3", None), - ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "ADC1 calibration 4", None), - ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "ADC2 calibration 5", None), - ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "ADC2 calibration 6", None), - ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "ADC2 calibration 7", None), - ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "ADC2 calibration 8", None), - ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "ADC1 calibration 9", None), - ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "ADC1 calibration 10", None), - ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "ADC1 calibration 11", None), - ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "ADC1 calibration 12", None), - ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "ADC2 calibration 13", None), - ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "ADC2 calibration 14", None), - ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "ADC2 calibration 15", None), - ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "ADC2 calibration 16", None), - ] - - CALC = [ - ("WAFER_VERSION_MINOR", "identity", 0, None, None, "uint:4", None, None, "wafer", "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)", None), - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32h2/operations.py b/espefuse/efuse/esp32h2/operations.py index 300cc2f71..3ce3c896e 100644 --- a/espefuse/efuse/esp32h2/operations.py +++ b/espefuse/efuse/esp32h2/operations.py @@ -155,9 +155,8 @@ def add_commands(subparsers, efuses): p = subparsers.add_parser( "set_flash_voltage", help="Permanently set the internal flash voltage regulator " - "to either 1.8V, 3.3V or OFF. " - "This means GPIO45 can be high or low at reset without " - "changing the flash voltage.", + "to either 1.8V, 3.3V or OFF. This means GPIO45 can be high or low " + "at reset without changing the flash voltage.", ) p.add_argument("voltage", help="Voltage selection", choices=["1.8V", "3.3V", "OFF"]) @@ -167,7 +166,8 @@ def add_commands(subparsers, efuses): p.add_argument( "mac", help="Custom MAC Address to burn given in hexadecimal format with bytes " - "separated by colons (e.g. AA:CD:EF:01:02:03).", + "separated by colons (e.g. AA:CD:EF:01:02:03). " + "Final CUSTOM_MAC = CUSTOM_MAC[48] + MAC_EXT[16]", type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), ) add_force_write_always(p) diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index d9e669e7d..ec2e8a217 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -84,53 +84,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLOCK2_VERSION"].get() == 1: + if self["BLK_VERSION_MAJOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] + self.efuses += [ + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC + ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -293,13 +283,26 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, - }.get(type_class, EfuseField)(parent, efuse_tuple) + "wafer": EfuseWafer, + }.get(efuse.class_type, EfuseField)(parent, efuse) + + +class EfuseWafer(EfuseField): + def get(self, from_read=True): + hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 + lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 + return (hi_bits << 3) + lo_bits + + def save(self, new_value): + raise esptool.FatalError("Burning %s is not supported" % self.name) class EfuseTempSensor(EfuseField): @@ -384,8 +387,6 @@ class EfuseKeyPurposeField(EfuseField): KEY_PURPOSES = [ ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) ("RESERVED", 1, None, None, "no_need_rd_protect"), # Reserved - ("XTS_AES_256_KEY_1", 2, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_1 (flash/PSRAM encryption) - ("XTS_AES_256_KEY_2", 3, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_2 (flash/PSRAM encryption) ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) ("HMAC_DOWN_ALL", 5, None, None, "need_rd_protect"), # HMAC Downstream mode ("HMAC_DOWN_JTAG", 6, None, None, "need_rd_protect"), # JTAG soft enable key (uses HMAC Downstream mode) diff --git a/espefuse/efuse/esp32h2beta1/mem_definition.py b/espefuse/efuse/esp32h2beta1/mem_definition.py index a9e8bc49e..ee2f00697 100644 --- a/espefuse/efuse/esp32h2beta1/mem_definition.py +++ b/espefuse/efuse/esp32h2beta1/mem_definition.py @@ -4,24 +4,26 @@ # # SPDX-License-Identifier: GPL-2.0-or-later +import os + +import yaml + from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase -# fmt: off class EfuseDefineRegisters(EfuseRegistersBase): - - EFUSE_MEM_SIZE = (0x01FC + 4) + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x6001A000 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 - EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 - EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + DR_REG_EFUSE_BASE = 0x6001A000 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 @@ -32,25 +34,25 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 BLOCK_ERRORS = [ # error_reg, err_num_mask, err_num_offs, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 ] # EFUSE_WR_TIM_CONF2_REG @@ -71,10 +73,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), @@ -89,6 +91,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -103,137 +106,50 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Table 51: Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), - ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), - ("DIS_USB_JTAG", "usb config", 0, 1, 9, "bool", 2, None, None, "Disables USB JTAG. " - "JTAG access via pads is controlled separately", None), - ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), - ("DIS_USB_DEVICE", "usb config", 0, 1, 11, "bool", 2, None, None, "Disables USB DEVICE", None), - ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), - ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), - ("JTAG_SEL_ENABLE", "jtag config", 0, 1, 15, "bool", 2, None, None, "Set this bit to enable selection between " - "usb_to_jtag and pad_to_jtag through strapping " - "gpio10 when both reg_dis_usb_jtag and " - "reg_dis_pad_jtag are equal to 0.", None), - ("SOFT_DIS_JTAG", "jtag config", 0, 1, 16, "uint:3", 2, None, None, "Software disables JTAG. When software disabled, " - "JTAG can be activated temporarily by HMAC peripheral", - None), - ("DIS_PAD_JTAG", "jtag config", 0, 1, 19, "bool", 2, None, None, "Permanently disable JTAG access via pads. " - "USB JTAG is controlled separately.", None), - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 20, "bool", 2, None, None, "Disables flash encryption when in download boot modes", - None), - ("USB_EXCHG_PINS", "usb config", 0, 1, 25, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), - ("VDD_SPI_AS_GPIO", "config", 0, 1, 26, "bool", 30, None, None, "Set this bit to vdd spi pin function as gpio", None), - ("BTLC_GPIO_ENABLE", "config", 0, 1, 27, "uint:2", 30, None, None, "Enable btlc gpio", None), - ("POWERGLITCH_EN", "config", 0, 1, 29, "bool", 30, None, None, "Set this bit to enable power glitch function", None), - ("POWER_GLITCH_DSENSE", "config", 0, 1, 30, "uint:2", 30, None, None, "Sample delay configuration of power glitch", None), - ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "bool", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "If set, revokes use of secure boot key digest 0", None), - ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "If set, revokes use of secure boot key digest 1", None), - ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "If set, revokes use of secure boot key digest 2", None), - ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), - ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), - ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), - ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), - ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), - ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), - ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), - ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", - None), - ("FLASH_TPUW", "flash config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), - ("DIS_DIRECT_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables direct boot mode", None), - ("DIS_USB_SERIAL_JTAG_ROM_PRINT", "config", 0, 4, 2, "bool", 18, None, None, "Disables USB-Serial-JTAG ROM printing", None), - ("DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE", "usb config", 0, 4, 4, "bool", 18, None, None, "Disables USB-Serial-JTAG download feature in " - "UART download boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", - {0: "Enabled", - 1: "Enable when GPIO8 is low at reset", - 2: "Enable when GPIO8 is high at reset", - 3: "Disabled"}), - ("FORCE_SEND_RESUME", "config", 0, 4, 13, "bool", 18, None, None, "Force ROM code to send a resume command during SPI boot" - "during SPI boot", None), - ("SECURE_VERSION", "identity", 0, 4, 14, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", - None), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), - # - # Table 53: Parameters in BLOCK1-10 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), - ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), - ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), - ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), - ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), - ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), - ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), - ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), - ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), - ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), - ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), - ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), - ("WAFER_VERSION", "identity", 1, 3, 18, "uint:3", 20, None, None, "WAFER version", - {0: "(revision 0)", 1: "(revision 1)"}), - ("PKG_VERSION", "identity", 1, 3, 21, "uint:4", 20, None, None, "Package version", - {0: "ESP32-H2(beta1)"}), - ("BLOCK1_VERSION", "identity", 1, 3, 24, "uint:3", 20, None, None, "BLOCK1 efuse version", None), - ("MAC_EXT", "identity", 1, 3, 27, "bytes:2", 20, None, "mac", "MAC extension", None), - ("OPTIONAL_UNIQUE_ID", "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), - ("BLOCK2_VERSION", "identity", 2, 4, 4, "uint:3", 21, None, None, "Version of BLOCK2", - {0: "No calibration", - 1: "With calibration"}), - ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), - ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), - ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), - ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), - ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), - ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), - ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), - ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, "keyblock", "System data (part 2)", None), - ] - - # if BLOCK2_VERSION is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "Temperature calibration", None), - ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "ADC1 calibration 1", None), - ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "ADC1 calibration 2", None), - ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "ADC1 calibration 3", None), - ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "ADC1 calibration 4", None), - ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "ADC2 calibration 5", None), - ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "ADC2 calibration 6", None), - ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "ADC2 calibration 7", None), - ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "ADC2 calibration 8", None), - ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "ADC1 calibration 9", None), - ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "ADC1 calibration 10", None), - ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "ADC1 calibration 11", None), - ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "ADC1 calibration 12", None), - ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "ADC2 calibration 13", None), - ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "ADC2 calibration 14", None), - ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "ADC2 calibration 15", None), - ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "ADC2 calibration 16", None), - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + efuse_file = efuse_file.replace("esp32h2beta1", "esp32h2") + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32h2beta1/operations.py b/espefuse/efuse/esp32h2beta1/operations.py index 58c7bb9c4..35cbb94c3 100644 --- a/espefuse/efuse/esp32h2beta1/operations.py +++ b/espefuse/efuse/esp32h2beta1/operations.py @@ -194,7 +194,7 @@ def set_flash_voltage(esp, efuses, args): def adc_info(esp, efuses, args): print("") # fmt: off - if efuses["BLOCK2_VERSION"].get() == 1: + if efuses["BLK_VERSION_MAJOR"].get() == 1: print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) print("") @@ -225,7 +225,7 @@ def adc_info(esp, efuses, args): print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) else: - print("BLOCK2_VERSION = {}".format(efuses["BLOCK2_VERSION"].get_meaning())) + print("BLK_VERSION_MAJOR = {}".format(efuses["BLK_VERSION_MAJOR"].get_meaning())) # fmt: on diff --git a/espefuse/efuse/esp32s2/fields.py b/espefuse/efuse/esp32s2/fields.py index d6af81d07..f38107367 100644 --- a/espefuse/efuse/esp32s2/fields.py +++ b/espefuse/efuse/esp32s2/fields.py @@ -84,59 +84,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: if self["BLK_VERSION_MINOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -334,9 +318,10 @@ def get_coding_scheme_warnings(self, silent=False): def summary(self): if self["VDD_SPI_FORCE"].get() == 0: output = "Flash voltage (VDD_SPI) determined by GPIO45 on reset " - "(GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO\n" + output += "(GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO\n" output += "GPIO45=Low or NC: VDD_SPI pin is powered directly from " - "VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V)." + output += "VDD3P3_RTC_IO via resistor Rspi. " + output += "Typically this voltage is 3.3 V)." elif self["VDD_SPI_XPD"].get() == 0: output = "Flash voltage (VDD_SPI) internal regulator disabled by efuse." elif self["VDD_SPI_TIEH"].get() == 0: @@ -348,20 +333,22 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, "wafer": EfuseWafer, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseWafer(EfuseField): def get(self, from_read=True): hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 return (hi_bits << 3) + lo_bits def save(self, new_value): diff --git a/espefuse/efuse/esp32s2/mem_definition.py b/espefuse/efuse/esp32s2/mem_definition.py index 94642ad3c..b83ea9139 100644 --- a/espefuse/efuse/esp32s2/mem_definition.py +++ b/espefuse/efuse/esp32s2/mem_definition.py @@ -4,24 +4,31 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +import os +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) -# fmt: off -class EfuseDefineRegisters(EfuseRegistersBase): - EFUSE_MEM_SIZE = (0x01FC + 4) +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x3f41A000 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1c8 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1cc - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1d0 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1d4 - EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x194 - EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x198 + DR_REG_EFUSE_BASE = 0x3F41A000 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x194 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x198 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 @@ -32,28 +39,28 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F4 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F8 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 BLOCK_ERRORS = [ # error_reg, err_num_mask, err_num_offs, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 ] - EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1e8 + EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 EFUSE_DAC_CLK_DIV_S = 0 EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S @@ -89,7 +96,7 @@ class EfuseDefineRegisters(EfuseRegistersBase): # Taken from TRM chapter "eFuse Controller": eFuse-Programming Timing 80: (0x2, 0x320, 0x2, 0x4), 40: (0x1, 0x190, 0x1, 0x2), - 20: (0x1, 0xC8, 0x1, 0x1), + 20: (0x1, 0xC8, 0x1, 0x1), } VDDQ_TIMING_PARAMETERS = { @@ -110,10 +117,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), @@ -128,6 +135,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -142,167 +150,59 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Table 51: Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), - ("DIS_RTC_RAM_BOOT", "config", 0, 1, 7, "bool", 1, None, None, "Disables boot from RTC RAM", None), - ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), - ("DIS_DCACHE", "config", 0, 1, 9, "bool", 2, None, None, "Disables DCache", None), - ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), - ("DIS_DOWNLOAD_DCACHE", "config", 0, 1, 11, "bool", 2, None, None, "Disables Dcache when SoC is in Download mode", None), - ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), - ("DIS_USB", "usb config", 0, 1, 13, "bool", 2, None, None, "Disables the USB OTG hardware", None), - ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), - ("DIS_BOOT_REMAP", "config", 0, 1, 15, "bool", 2, None, None, "Disables capability to Remap RAM to ROM address space", - None), - ("SOFT_DIS_JTAG", "security", 0, 1, 17, "bool", 2, None, None, "Software disables JTAG. When software disabled, " - "JTAG can be activated temporarily by HMAC peripheral", - None), - ("HARD_DIS_JTAG", "security", 0, 1, 18, "bool", 2, None, None, "Hardware disables JTAG permanently", None), - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 19, "bool", 2, None, None, "Disables flash encryption when in download boot modes", - None), - ("USB_EXCHG_PINS", "usb config", 0, 1, 24, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), - ("EXT_PHY_ENABLE", "usb config", 0, 1, 25, "bool", 30, None, None, "Enables external USB PHY", None), - ("USB_FORCE_NOPERSIST", "usb config", 0, 1, 26, "bool", 30, None, None, "Forces to set USB BVALID to 1", None), - ("BLOCK0_VERSION", "identity", 0, 1, 27, "uint:2", 30, None, None, "BLOCK0 efuse version", None), - ("VDD_SPI_FORCE", "VDD_SPI config", 0, 2, 6, "bool", 3, None, None, "Force using VDD_SPI_XPD and VDD_SPI_TIEH " - "to configure VDD_SPI LDO", None), - ("VDD_SPI_XPD", "VDD_SPI config", 0, 2, 4, "bool", 3, None, None, "The VDD_SPI regulator is powered on", None), - ("VDD_SPI_TIEH", "VDD_SPI config", 0, 2, 5, "bool", 3, None, None, "The VDD_SPI power supply voltage at reset", - {0: "Connect to 1.8V LDO", - 1: "Connect to VDD3P3_RTC_IO"}), - ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "uint:2", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "If set, revokes use of secure boot key digest 0", None), - ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "If set, revokes use of secure boot key digest 1", None), - ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "If set, revokes use of secure boot key digest 2", None), - ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), - ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), - ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), - ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), - ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), - ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), - ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), - ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", - None), - ("FLASH_TPUW", "config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), - ("DIS_LEGACY_SPI_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables Legacy SPI boot mode", None), - ("UART_PRINT_CHANNEL", "config", 0, 4, 2, "bool", 18, None, None, "Selects the default UART for printing boot msg", - - {0: "UART0", - 1: "UART1"}), - ("DIS_USB_DOWNLOAD_MODE", "config", 0, 4, 4, "bool", 18, None, None, "Disables use of USB in UART download boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", - - {0: "Enabled", - 1: "Enable when GPIO 46 is low at reset", - 2: "Enable when GPIO 46 is high at rest", - 3: "Disabled"}), - ("PIN_POWER_SELECTION", "VDD_SPI config", 0, 4, 8, "bool", 18, None, None, "Sets default power supply for GPIO33..37, " - "set when SPI flash is initialized", - - {0: "VDD3P3_CPU", - 1: "VDD_SPI"}), - ("FLASH_TYPE", "config", 0, 4, 9, "bool", 18, None, None, "Selects SPI flash type", - - {0: "4 data lines", - 1: "8 data lines"}), - ("FORCE_SEND_RESUME", "config", 0, 4, 10, "bool", 18, None, None, "Forces ROM code to send an SPI flash resume command " - "during SPI boot", None), - ("SECURE_VERSION", "identity", 0, 4, 11, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", - None), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), - # - # Table 53: Parameters in BLOCK1-10 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), - ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), - ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), - ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), - ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), - ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), - ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), - ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), - ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), - ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), - ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), - ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), - - ("WAFER_VERSION_MAJOR", "identity", 1, 3, 18, "uint:2", 20, None, None, "WAFER_VERSION_MAJOR", None), - ("WAFER_VERSION_MINOR_HI", "identity", 1, 3, 20, "uint:1", 20, None, None, "WAFER_VERSION_MINOR most significant bits", None), - ("FLASH_VERSION", "identity", 1, 3, 21, "uint:4", 20, None, None, "Flash version", - {0: "No Embedded Flash", - 1: "Embedded Flash 2MB", - 2: "Embedded Flash 4MB"}), - ("BLK_VERSION_MAJOR", "identity", 1, 3, 25, "uint:2", 20, None, None, "BLOCK version major", None), - ("PSRAM_VERSION", "identity", 1, 3, 28, "uint:4", 20, None, None, "PSRAM version", - {0: "No Embedded PSRAM", - 1: "Embedded PSRAM 2MB", - 2: "Embedded PSRAM 4MB"}), - ("PKG_VERSION", "identity", 1, 4, 0, "uint:4", 20, None, None, "Package version", None), - ("WAFER_VERSION_MINOR_LO", "identity", 1, 4, 4, "uint:3", 20, None, None, "WAFER_VERSION_MINOR least significant bits", None), - - ('OPTIONAL_UNIQUE_ID', "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), - ("BLK_VERSION_MINOR", "identity", 2, 4, 4, "uint:3", 21, None, None, "BLOCK version minor", - {0: "No calibration", - 1: "With ADC calibration V1", - 2: "With ADC calibration V2"}), - ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), - ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), - ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), - ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), - ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), - ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), - ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), - ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, None, "System data (part 2)", None), - ] - - # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "Temperature calibration", None), - ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "ADC1 calibration 1", None), - ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "ADC1 calibration 2", None), - ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "ADC1 calibration 3", None), - ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "ADC1 calibration 4", None), - ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "ADC2 calibration 5", None), - ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "ADC2 calibration 6", None), - ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "ADC2 calibration 7", None), - ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "ADC2 calibration 8", None), - ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "ADC1 calibration 9", None), - ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "ADC1 calibration 10", None), - ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "ADC1 calibration 11", None), - ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "ADC1 calibration 12", None), - ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "ADC2 calibration 13", None), - ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "ADC2 calibration 14", None), - ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "ADC2 calibration 15", None), - ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "ADC2 calibration 16", None), - ] - - CALC = [ - ("WAFER_VERSION_MINOR", "identity", 0, None, None, "uint:4", None, None, "wafer", "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)", None), - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + f = Field() + f.name = "WAFER_VERSION_MINOR" + f.block = 0 + f.bit_len = 4 + f.type = f"uint:{f.bit_len}" + f.category = "identity" + f.class_type = "wafer" + f.description = "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)" + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index d4b57b13f..6949184a3 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -84,59 +84,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: if self["BLK_VERSION_MAJOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -295,9 +279,10 @@ def get_coding_scheme_warnings(self, silent=False): def summary(self): if self["VDD_SPI_FORCE"].get() == 0: output = "Flash voltage (VDD_SPI) determined by GPIO45 on reset " - "(GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO\n" + output += "(GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO\n" output += "GPIO45=Low or NC: VDD_SPI pin is powered directly from " - "VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V)." + output += "VDD3P3_RTC_IO via resistor Rspi. " + output += "Typically this voltage is 3.3 V)." elif self["VDD_SPI_XPD"].get() == 0: output = "Flash voltage (VDD_SPI) internal regulator disabled by efuse." elif self["VDD_SPI_TIEH"].get() == 0: @@ -309,20 +294,22 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, "wafer": EfuseWafer, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseWafer(EfuseField): def get(self, from_read=True): hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 return (hi_bits << 3) + lo_bits def save(self, new_value): diff --git a/espefuse/efuse/esp32s3/mem_definition.py b/espefuse/efuse/esp32s3/mem_definition.py index b99d97be7..54c88712c 100644 --- a/espefuse/efuse/esp32s3/mem_definition.py +++ b/espefuse/efuse/esp32s3/mem_definition.py @@ -4,25 +4,32 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +import os +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) -# fmt: off -class EfuseDefineRegisters(EfuseRegistersBase): +class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_ADDR_MASK = 0x00000FFF - EFUSE_MEM_SIZE = (0x01FC + 4) + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x60007000 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 - EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 - EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + DR_REG_EFUSE_BASE = 0x60007000 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 @@ -33,25 +40,25 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F4 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F8 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 BLOCK_ERRORS = [ # error_reg, err_num_mask, err_num_offs, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 ] # EFUSE_WR_TIM_CONF2_REG @@ -72,10 +79,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), @@ -90,6 +97,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -104,163 +112,59 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Table 51: Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), - ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), - ("DIS_DCACHE", "config", 0, 1, 9, "bool", 2, None, None, "Disables DCache", None), - ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), - ("DIS_DOWNLOAD_DCACHE", "config", 0, 1, 11, "bool", 2, None, None, "Disables Dcache when SoC is in Download mode", None), - ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), - ("DIS_USB", "usb config", 0, 1, 13, "bool", 2, None, None, "Disables the USB OTG hardware", None), - ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), - ("DIS_APP_CPU", "config", 0, 1, 15, "bool", 2, None, None, "Disables APP CPU", None), - ("SOFT_DIS_JTAG", "security", 0, 1, 16, "uint:3", 31, None, None, "Software disables JTAG by programming " - "odd number of 1 bit(s). " - "JTAG can be re-enabled via HMAC peripheral", - None), - ("HARD_DIS_JTAG", "security", 0, 1, 19, "bool", 2, None, None, "Hardware disables JTAG permanently", None), - - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 20, "bool", 2, None, None, "Disables flash encryption when in download boot modes", - None), - ("USB_EXCHG_PINS", "usb config", 0, 1, 25, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), - ("EXT_PHY_ENABLE", "usb config", 0, 1, 26, "bool", 30, None, None, "Enables external USB PHY", None), - ("BTLC_GPIO_ENABLE", "usb config", 0, 1, 27, "uint:2", 30, None, None, "Enables BTLC GPIO", None), - ("VDD_SPI_XPD", "VDD_SPI config", 0, 2, 4, "bool", 3, None, None, "The VDD_SPI regulator is powered on", None), - ("VDD_SPI_TIEH", "VDD_SPI config", 0, 2, 5, "bool", 3, None, None, "The VDD_SPI power supply voltage at reset", - {0: "Connect to 1.8V LDO", - 1: "Connect to VDD_RTC_IO"}), - ("VDD_SPI_FORCE", "VDD_SPI config", 0, 2, 6, "bool", 3, None, None, "Force using VDD_SPI_XPD and VDD_SPI_TIEH " - "to configure VDD_SPI LDO", None), - ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "uint:2", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "Revokes use of secure boot key digest 0", None), - ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "Revokes use of secure boot key digest 1", None), - ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "Revokes use of secure boot key digest 2", None), - ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), - ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), - ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), - ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), - ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), - ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), - ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), - ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", - None), - ("DIS_USB_JTAG", "usb config", 0, 3, 22, "bool", 2, None, None, "Disable usb_serial_jtag-to-jtag function", None), - ("DIS_USB_SERIAL_JTAG", "usb config", 0, 3, 23, "bool", 2, None, None, "Disable usb_serial_jtag module", None), - ("STRAP_JTAG_SEL", "security", 0, 3, 24, "bool", 2, None, None, "Enable selection between usb_to_jtag" - "or pad_to_jtag through GPIO3", None), - ("USB_PHY_SEL", "usb config", 0, 3, 25, "bool", 2, None, None, "Select internal/external PHY for USB OTG" - "and usb_serial_jtag", None), - ("FLASH_TPUW", "config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), - ("DIS_DIRECT_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables direct boot mode", None), - ("DIS_USB_SERIAL_JTAG_ROM_PRINT", "config", 0, 4, 2, "bool", 18, None, None, "Disables USB-Serial-JTAG ROM printing", None), - ("FLASH_ECC_MODE", "config", 0, 4, 3, "bool", 18, None, None, "Configures the ECC mode for SPI flash", - {0: "16-byte to 18-byte mode", - 1: "16-byte to 17-byte mode"}), - ("DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE", "config", 0, 4, 4, "bool", 18, None, None, "Disables USB-Serial-JTAG download feature in " - "UART download boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", - {0: "Enabled", - 1: "Enable when GPIO 46 is low at reset", - 2: "Enable when GPIO 46 is high at rest", - 3: "Disabled"}), - ("PIN_POWER_SELECTION", "VDD_SPI config", 0, 4, 8, "bool", 18, None, None, "Sets default power supply for GPIO33..37", - {0: "VDD3P3_CPU", - 1: "VDD_SPI"}), - ("FLASH_TYPE", "config", 0, 4, 9, "bool", 18, None, None, "Selects SPI flash type", - {0: "4 data lines", - 1: "8 data lines"}), - ("FLASH_PAGE_SIZE", "config", 0, 4, 10, "uint:2", 18, None, None, "Sets the size of flash page", None), - ("FLASH_ECC_EN", "config", 0, 4, 12, "bool", 18, None, None, "Enables ECC in Flash boot mode", None), - ("FORCE_SEND_RESUME", "config", 0, 4, 13, "bool", 18, None, None, "Forces ROM code to send an SPI flash resume command " - "during SPI boot", None), - ("SECURE_VERSION", "identity", 0, 4, 14, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", - None), - ("DIS_USB_OTG_DOWNLOAD_MODE", "config", 0, 4, 31, "bool", 19, None, None, "Disables USB-OTG download feature in " - "UART download boot mode", None), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), - # - # Table 53: Parameters in BLOCK1-10 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), - ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), - ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), - ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), - ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), - ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), - ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), - ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), - ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), - ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), - ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), - ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), - - ("WAFER_VERSION_MINOR_LO", "identity", 1, 3, 18, "uint:3", 20, None, None, "WAFER_VERSION_MINOR least significant bits", None), - ("PKG_VERSION", "identity", 1, 3, 21, "uint:3", 20, None, None, "Package version", None), - ("BLK_VERSION_MINOR", "identity", 1, 3, 24, "uint:3", 20, None, None, "BLOCK version minor", None), - ("WAFER_VERSION_MINOR_HI", "identity", 1, 5, 23, "uint:1", 20, None, None, "WAFER_VERSION_MINOR most significant bits", None), - ("WAFER_VERSION_MAJOR", "identity", 1, 5, 24, "uint:2", 20, None, None, "WAFER_VERSION_MAJOR", None), - - ("OPTIONAL_UNIQUE_ID", "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), - ("BLK_VERSION_MAJOR", "identity", 2, 4, 0, "uint:2", 21, None, None, "BLOCK version major", - {0: "No calibration", - 1: "With calibration"}), - ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), - ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), - ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), - ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), - ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), - ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), - ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), - ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, None, "System data (part 2)", None), - ] - - # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "??? Temperature calibration", None), - ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 1", None), - ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 2", None), - ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 3", None), - ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 4", None), - ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 5", None), - ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 6", None), - ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 7", None), - ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 8", None), - ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 9", None), - ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 10", None), - ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 11", None), - ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 12", None), - ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 13", None), - ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 14", None), - ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 15", None), - ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 16", None), - ] - - CALC = [ - ("WAFER_VERSION_MINOR", "identity", 0, None, None, "uint:4", None, None, "wafer", "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)", None), - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + f = Field() + f.name = "WAFER_VERSION_MINOR" + f.block = 0 + f.bit_len = 4 + f.type = f"uint:{f.bit_len}" + f.category = "identity" + f.class_type = "wafer" + f.description = "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)" + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 98bbe5606..017a0beae 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -84,59 +84,43 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: if self["BLK_VERSION_MAJOR"].get() == 1: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -295,9 +279,10 @@ def get_coding_scheme_warnings(self, silent=False): def summary(self): if self["VDD_SPI_FORCE"].get() == 0: output = "Flash voltage (VDD_SPI) determined by GPIO45 on reset " - "(GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO\n" + output += "(GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO\n" output += "GPIO45=Low or NC: VDD_SPI pin is powered directly from " - "VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V)." + output += "VDD3P3_RTC_IO via resistor Rspi. " + output += "Typically this voltage is 3.3 V)." elif self["VDD_SPI_XPD"].get() == 0: output = "Flash voltage (VDD_SPI) internal regulator disabled by efuse." elif self["VDD_SPI_TIEH"].get() == 0: @@ -309,20 +294,22 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, "wafer": EfuseWafer, - }.get(type_class, EfuseField)(parent, efuse_tuple) + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseWafer(EfuseField): def get(self, from_read=True): hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 return (hi_bits << 3) + lo_bits def save(self, new_value): diff --git a/espefuse/efuse/esp32s3beta2/mem_definition.py b/espefuse/efuse/esp32s3beta2/mem_definition.py index a5788d1bf..eabf76781 100644 --- a/espefuse/efuse/esp32s3beta2/mem_definition.py +++ b/espefuse/efuse/esp32s3beta2/mem_definition.py @@ -4,25 +4,32 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +import os +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) -# fmt: off -class EfuseDefineRegisters(EfuseRegistersBase): +class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_ADDR_MASK = 0x00000FFF - EFUSE_MEM_SIZE = (0x01FC + 4) + EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x6001A000 - EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE - EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 - EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 - EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC - EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 - EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 - EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 - EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + DR_REG_EFUSE_BASE = 0x6001A000 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 @@ -33,25 +40,25 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F4 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F8 EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC - EFUSE_WRITE_OP_CODE = 0x5A5A - EFUSE_READ_OP_CODE = 0x5AA5 - EFUSE_PGM_CMD_MASK = 0x3 - EFUSE_PGM_CMD = 0x2 - EFUSE_READ_CMD = 0x1 + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 BLOCK_ERRORS = [ # error_reg, err_num_mask, err_num_offs, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 ] # EFUSE_WR_TIM_CONF2_REG @@ -72,10 +79,10 @@ class EfuseDefineRegisters(EfuseRegistersBase): class EfuseDefineBlocks(EfuseBlocksBase): - __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG # List of efuse blocks + # fmt: off BLOCKS = [ # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), @@ -90,6 +97,7 @@ class EfuseDefineBlocks(EfuseBlocksBase): ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), ] + # fmt: on def get_burn_block_data_names(self): list_of_names = [] @@ -104,157 +112,60 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - - # List of efuse fields from TRM the chapter eFuse Controller. - EFUSES = [ - # - # Table 51: Parameters in BLOCK0 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("WR_DIS", "efuse", 0, 0, 0, "uint:32", None, None, None, "Disables programming of individual eFuses", None), - ("RD_DIS", "efuse", 0, 1, 0, "uint:7", 0, None, None, "Disables software reading from BLOCK4-10", None), - ("DIS_ICACHE", "config", 0, 1, 8, "bool", 2, None, None, "Disables ICache", None), - ("DIS_DCACHE", "config", 0, 1, 9, "bool", 2, None, None, "Disables DCache", None), - ("DIS_DOWNLOAD_ICACHE", "config", 0, 1, 10, "bool", 2, None, None, "Disables Icache when SoC is in Download mode", None), - ("DIS_DOWNLOAD_DCACHE", "config", 0, 1, 11, "bool", 2, None, None, "Disables Dcache when SoC is in Download mode", None), - ("DIS_FORCE_DOWNLOAD", "config", 0, 1, 12, "bool", 2, None, None, "Disables forcing chip into Download mode", None), - ("DIS_USB", "usb config", 0, 1, 13, "bool", 2, None, None, "Disables the USB OTG hardware", None), - ("DIS_CAN", "config", 0, 1, 14, "bool", 2, None, None, "Disables the TWAI Controller hardware", None), - ("DIS_APP_CPU", "config", 0, 1, 15, "bool", 2, None, None, "Disables APP CPU", None), - ("SOFT_DIS_JTAG", "security", 0, 1, 16, "uint:3", 31, None, None, "Software disables JTAG by programming " - "odd number of 1 bit(s). " - "JTAG can be re-enabled via HMAC peripheral", - None), - ("HARD_DIS_JTAG", "security", 0, 1, 19, "bool", 2, None, None, "Hardware disables JTAG permanently", None), - - ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 20, "bool", 2, None, None, "Disables flash encryption when in download boot modes", - None), - ("USB_EXCHG_PINS", "usb config", 0, 1, 25, "bool", 30, None, None, "Exchanges USB D+ and D- pins", None), - ("EXT_PHY_ENABLE", "usb config", 0, 1, 26, "bool", 30, None, None, "Enables external USB PHY", None), - ("BTLC_GPIO_ENABLE", "usb config", 0, 1, 27, "uint:2", 30, None, None, "Enables BTLC GPIO", None), - ("VDD_SPI_XPD", "VDD_SPI config", 0, 2, 4, "bool", 3, None, None, "The VDD_SPI regulator is powered on", None), - ("VDD_SPI_TIEH", "VDD_SPI config", 0, 2, 5, "bool", 3, None, None, "The VDD_SPI power supply voltage at reset", - {0: "Connect to 1.8V LDO", - 1: "Connect to VDD_RTC_IO"}), - ("VDD_SPI_FORCE", "VDD_SPI config", 0, 2, 6, "bool", 3, None, None, "Force using VDD_SPI_XPD and VDD_SPI_TIEH " - "to configure VDD_SPI LDO", None), - ("WDT_DELAY_SEL", "WDT config", 0, 2, 16, "uint:2", 3, None, None, "Selects RTC WDT timeout threshold at startup", None), - ("SPI_BOOT_CRYPT_CNT", "security", 0, 2, 18, "uint:3", 4, None, "bitcount", "Enables encryption and decryption, when an SPI boot " - "mode is set. Enabled when 1 or 3 bits are set," - "disabled otherwise", - {0: "Disable", - 1: "Enable", - 3: "Disable", - 7: "Enable"}), - ("SECURE_BOOT_KEY_REVOKE0", "security", 0, 2, 21, "bool", 5, None, None, "Revokes use of secure boot key digest 0", None), - ("SECURE_BOOT_KEY_REVOKE1", "security", 0, 2, 22, "bool", 6, None, None, "Revokes use of secure boot key digest 1", None), - ("SECURE_BOOT_KEY_REVOKE2", "security", 0, 2, 23, "bool", 7, None, None, "Revokes use of secure boot key digest 2", None), - ("KEY_PURPOSE_0", "security", 0, 2, 24, "uint:4", 8, None, "keypurpose", "KEY0 purpose", None), - ("KEY_PURPOSE_1", "security", 0, 2, 28, "uint:4", 9, None, "keypurpose", "KEY1 purpose", None), - ("KEY_PURPOSE_2", "security", 0, 3, 0, "uint:4", 10, None, "keypurpose", "KEY2 purpose", None), - ("KEY_PURPOSE_3", "security", 0, 3, 4, "uint:4", 11, None, "keypurpose", "KEY3 purpose", None), - ("KEY_PURPOSE_4", "security", 0, 3, 8, "uint:4", 12, None, "keypurpose", "KEY4 purpose", None), - ("KEY_PURPOSE_5", "security", 0, 3, 12, "uint:4", 13, None, "keypurpose", "KEY5 purpose", None), - ("SECURE_BOOT_EN", "security", 0, 3, 20, "bool", 15, None, None, "Enables secure boot", None), - ("SECURE_BOOT_AGGRESSIVE_REVOKE", "security", 0, 3, 21, "bool", 16, None, None, "Enables aggressive secure boot key revocation mode", - None), - ("FLASH_TPUW", "config", 0, 3, 28, "uint:4", 18, None, None, "Configures flash startup delay after SoC power-up, " - "unit is (ms/2). When the value is 15, delay is 7.5 ms", - None), - ("DIS_DOWNLOAD_MODE", "security", 0, 4, 0, "bool", 18, None, None, "Disables all Download boot modes", None), - ("DIS_DIRECT_BOOT", "config", 0, 4, 1, "bool", 18, None, None, "Disables direct boot mode", None), - ("DIS_USB_SERIAL_JTAG_ROM_PRINT", "config", 0, 4, 2, "bool", 18, None, None, "Disables USB-Serial-JTAG ROM printing", None), - ("FLASH_ECC_MODE", "config", 0, 4, 3, "bool", 18, None, None, "Configures the ECC mode for SPI flash", - {0: "16-byte to 18-byte mode", - 1: "16-byte to 17-byte mode"}), - ("DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE", "config", 0, 4, 4, "bool", 18, None, None, "Disables USB-Serial-JTAG download feature in " - "UART download boot mode", None), - ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 4, 5, "bool", 18, None, None, "Enables secure UART download mode " - "(read/write flash only)", None), - ("UART_PRINT_CONTROL", "config", 0, 4, 6, "uint:2", 18, None, None, "Sets the default UART boot message output mode", - {0: "Enabled", - 1: "Enable when GPIO 46 is low at reset", - 2: "Enable when GPIO 46 is high at rest", - 3: "Disabled"}), - ("PIN_POWER_SELECTION", "VDD_SPI config", 0, 4, 8, "bool", 18, None, None, "Sets default power supply for GPIO33..37", - {0: "VDD3P3_CPU", - 1: "VDD_SPI"}), - ("FLASH_TYPE", "config", 0, 4, 9, "bool", 18, None, None, "Selects SPI flash type", - {0: "4 data lines", - 1: "8 data lines"}), - ("FLASH_PAGE_SIZE", "config", 0, 4, 10, "uint:2", 18, None, None, "Sets the size of flash page", None), - ("FLASH_ECC_EN", "config", 0, 4, 12, "bool", 18, None, None, "Enables ECC in Flash boot mode", None), - ("FORCE_SEND_RESUME", "config", 0, 4, 13, "bool", 18, None, None, "Forces ROM code to send an SPI flash resume command " - "during SPI boot", None), - ("SECURE_VERSION", "identity", 0, 4, 14, "uint:16", 18, None, "bitcount", "Secure version (used by ESP-IDF anti-rollback feature)", - None), - ("DIS_USB_OTG_DOWNLOAD_MODE", "config", 0, 4, 31, "bool", 19, None, None, "Disables USB-OTG download feature in " - "UART download boot mode", None), - ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 5, 0, "bool", 19, None, None, "Disables check of wafer version major", None), - ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 5, 1, "bool", 19, None, None, "Disables check of blk version major", None), - # - # Table 53: Parameters in BLOCK1-10 - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ("MAC", "identity", 1, 0, 0, "bytes:6", 20, None, "mac", "Factory MAC Address", None), - ("SPI_PAD_CONFIG_CLK", "spi_pad_config", 1, 1, 16, "uint:6", 20, None, None, "SPI CLK pad", None), - ("SPI_PAD_CONFIG_Q", "spi_pad_config", 1, 1, 22, "uint:6", 20, None, None, "SPI Q (D1) pad", None), - ("SPI_PAD_CONFIG_D", "spi_pad_config", 1, 1, 28, "uint:6", 20, None, None, "SPI D (D0) pad", None), - ("SPI_PAD_CONFIG_CS", "spi_pad_config", 1, 2, 2, "uint:6", 20, None, None, "SPI CS pad", None), - ("SPI_PAD_CONFIG_HD", "spi_pad_config", 1, 2, 8, "uint:6", 20, None, None, "SPI HD (D3) pad", None), - ("SPI_PAD_CONFIG_WP", "spi_pad_config", 1, 2, 14, "uint:6", 20, None, None, "SPI WP (D2) pad", None), - ("SPI_PAD_CONFIG_DQS", "spi_pad_config", 1, 2, 20, "uint:6", 20, None, None, "SPI DQS pad", None), - ("SPI_PAD_CONFIG_D4", "spi_pad_config", 1, 2, 26, "uint:6", 20, None, None, "SPI D4 pad", None), - ("SPI_PAD_CONFIG_D5", "spi_pad_config", 1, 3, 0, "uint:6", 20, None, None, "SPI D5 pad", None), - ("SPI_PAD_CONFIG_D6", "spi_pad_config", 1, 3, 6, "uint:6", 20, None, None, "SPI D6 pad", None), - ("SPI_PAD_CONFIG_D7", "spi_pad_config", 1, 3, 12, "uint:6", 20, None, None, "SPI D7 pad", None), - - ("WAFER_VERSION_MINOR_LO", "identity", 1, 3, 18, "uint:3", 20, None, None, "WAFER_VERSION_MINOR least significant bits", None), - ("PKG_VERSION", "identity", 1, 3, 21, "uint:3", 20, None, None, "Package version", None), - ("BLK_VERSION_MINOR", "identity", 1, 3, 24, "uint:3", 20, None, None, "BLOCK version minor", None), - ("WAFER_VERSION_MINOR_HI", "identity", 1, 5, 23, "uint:1", 20, None, None, "WAFER_VERSION_MINOR most significant bits", None), - ("WAFER_VERSION_MAJOR", "identity", 1, 5, 24, "uint:2", 20, None, None, "WAFER_VERSION_MAJOR", None), - - ("OPTIONAL_UNIQUE_ID", "identity", 2, 0, 0, "bytes:16", 21, None, "keyblock", "Optional unique 128-bit ID", None), - ("BLK_VERSION_MAJOR", "identity", 2, 4, 0, "uint:2", 21, None, None, "BLOCK version major", - {0: "No calibration", - 1: "With calibration"}), - ("CUSTOM_MAC", "identity", 3, 6, 8, "bytes:6", 22, None, "mac", "Custom MAC Address", None), - ] - - KEYBLOCKS = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('BLOCK_USR_DATA', "config", 3, 0, 0, "bytes:32", 22, None, None, "User data", None), - ('BLOCK_KEY0', "security", 4, 0, 0, "bytes:32", 23, 0, "keyblock", "Encryption key0 or user data", None), - ('BLOCK_KEY1', "security", 5, 0, 0, "bytes:32", 24, 1, "keyblock", "Encryption key1 or user data", None), - ('BLOCK_KEY2', "security", 6, 0, 0, "bytes:32", 25, 2, "keyblock", "Encryption key2 or user data", None), - ('BLOCK_KEY3', "security", 7, 0, 0, "bytes:32", 26, 3, "keyblock", "Encryption key3 or user data", None), - ('BLOCK_KEY4', "security", 8, 0, 0, "bytes:32", 27, 4, "keyblock", "Encryption key4 or user data", None), - ('BLOCK_KEY5', "security", 9, 0, 0, "bytes:32", 28, 5, "keyblock", "Encryption key5 or user data", None), - ('BLOCK_SYS_DATA2', "security", 10, 0, 0, "bytes:32", 29, 6, None, "System data (part 2)", None), - ] - - # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 - BLOCK2_CALIBRATION_EFUSES = [ - # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary - ('TEMP_SENSOR_CAL', "calibration", 2, 4, 7, "uint:9", 21, None, "t_sensor", "??? Temperature calibration", None), - ('ADC1_MODE0_D2', "calibration", 2, 4, 16, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 1", None), - ('ADC1_MODE1_D2', "calibration", 2, 4, 24, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 2", None), - ('ADC1_MODE2_D2', "calibration", 2, 5, 0, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 3", None), - ('ADC1_MODE3_D2', "calibration", 2, 5, 8, "uint:8", 21, None, "adc_tp", "??? ADC1 calibration 4", None), - ('ADC2_MODE0_D2', "calibration", 2, 5, 16, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 5", None), - ('ADC2_MODE1_D2', "calibration", 2, 5, 24, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 6", None), - ('ADC2_MODE2_D2', "calibration", 2, 6, 0, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 7", None), - ('ADC2_MODE3_D2', "calibration", 2, 6, 8, "uint:8", 21, None, "adc_tp", "??? ADC2 calibration 8", None), - ('ADC1_MODE0_D1', "calibration", 2, 6, 16, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 9", None), - ('ADC1_MODE1_D1', "calibration", 2, 6, 22, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 10", None), - ('ADC1_MODE2_D1', "calibration", 2, 6, 28, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 11", None), - ('ADC1_MODE3_D1', "calibration", 2, 7, 2, "uint:6", 21, None, "adc_tp", "??? ADC1 calibration 12", None), - ('ADC2_MODE0_D1', "calibration", 2, 7, 8, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 13", None), - ('ADC2_MODE1_D1', "calibration", 2, 7, 14, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 14", None), - ('ADC2_MODE2_D1', "calibration", 2, 7, 20, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 15", None), - ('ADC2_MODE3_D1', "calibration", 2, 7, 26, "uint:6", 21, None, "adc_tp", "??? ADC2 calibration 16", None), - ] - - CALC = [ - ("WAFER_VERSION_MINOR", "identity", 0, None, None, "uint:4", None, None, "wafer", "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)", None), - ] -# fmt: on + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + efuse_file = efuse_file.replace("esp32s3beta2", "esp32s3") + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + f = Field() + f.name = "WAFER_VERSION_MINOR" + f.block = 0 + f.bit_len = 4 + f.type = f"uint:{f.bit_len}" + f.category = "identity" + f.class_type = "wafer" + f.description = "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)" + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/mem_definition_base.py b/espefuse/efuse/mem_definition_base.py index 1d1f4ebf6..21ae698b3 100644 --- a/espefuse/efuse/mem_definition_base.py +++ b/espefuse/efuse/mem_definition_base.py @@ -43,13 +43,129 @@ def get_blocks_for_keys(self): return list_of_names +class Field: + name = "" + block = 0 + word = None + pos = None + bit_len = 0 + alt_names = [] + type = "" + write_disable_bit = None + read_disable_bit = None + category = "config" + class_type = "" + description = "" + dictionary = None + + class EfuseFieldsBase(object): - NamedtupleField = namedtuple( - "Efuse", - "name category block word pos type write_disable_bit " - "read_disable_bit class_type description dictionary", - ) + def __init__(self, e_desc) -> None: + self.ALL_EFUSES = [] - @staticmethod - def get(tuple_field): - return EfuseFieldsBase.NamedtupleField._make(tuple_field) + def set_category_and_class_type(efuse, name): + def includes(name, names): + return any([word in name for word in names]) + + if name.startswith("SPI_PAD_CONFIG"): + efuse.category = "spi pad" + + elif "USB" in name: + efuse.category = "usb" + + elif "WDT" in name: + efuse.category = "wdt" + + elif "JTAG" in name: + efuse.category = "jtag" + + elif includes(name, ["FLASH", "FORCE_SEND_RESUME"]): + efuse.category = "flash" + + elif includes(name, ["VDD_SPI_", "XPD"]): + efuse.category = "vdd" + + elif "MAC" in name: + efuse.category = "MAC" + if name in ["MAC", "CUSTOM_MAC", "MAC_EXT"]: + efuse.class_type = "mac" + + elif includes( + name, + [ + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK1", + "BLOCK2", + ], + ): + efuse.category = "security" + efuse.class_type = "keyblock" + + elif includes( + name, + [ + "KEY", + "SECURE", + "DOWNLOAD", + "SPI_BOOT_CRYPT_CNT", + "KEY_PURPOSE", + "SECURE_VERSION", + "DPA", + "ECDSA", + "FLASH_CRYPT_CNT", + "ENCRYPT", + "DECRYPT", + "ABS_DONE", + ], + ): + efuse.category = "security" + if name.startswith("KEY_PURPOSE"): + efuse.class_type = "keypurpose" + elif includes( + name, ["FLASH_CRYPT_CNT", "SPI_BOOT_CRYPT_CNT", "SECURE_VERSION"] + ): + efuse.class_type = "bitcount" + + elif includes(name, ["VERSION", "WAFER", "_ID", "PKG", "PACKAGE", "REV"]): + efuse.category = "identity" + if name == "OPTIONAL_UNIQUE_ID": + efuse.class_type = "keyblock" + + elif includes(name, ["ADC", "LDO", "DBIAS", "_HVT", "CALIB", "OCODE"]): + efuse.category = "calibration" + if name == "ADC_VREF": + efuse.class_type = "vref" + return + if includes(name, ["ADC", "LDO", "DBIAS", "_HVT"]): + efuse.class_type = "adc_tp" + elif name == "TEMP_CALIB": + efuse.class_type = "t_sensor" + + for e_name in e_desc["EFUSES"]: + data_dict = e_desc["EFUSES"][e_name] + if data_dict["show"] == "y": + d = Field() + d.name = e_name + d.block = data_dict["blk"] + d.word = data_dict["word"] + d.pos = data_dict["pos"] + d.bit_len = data_dict["len"] + d.type = data_dict["type"] + d.write_disable_bit = data_dict["wr_dis"] + d.read_disable_bit = ( + [int(x) for x in data_dict["rd_dis"].split(" ")] + if isinstance(data_dict["rd_dis"], str) + else data_dict["rd_dis"] + ) + d.description = data_dict["desc"] + d.alt_names = data_dict["alt"].split(" ") if data_dict["alt"] else [] + d.dictionary = ( + eval(data_dict["dict"]) if data_dict["dict"] != "" else None + ) + set_category_and_class_type(d, e_name) + self.ALL_EFUSES.append(d) diff --git a/espefuse/efuse_defs/esp32.yaml b/espefuse/efuse_defs/esp32.yaml new file mode 100644 index 000000000..cfae99038 --- /dev/null +++ b/espefuse/efuse_defs/esp32.yaml @@ -0,0 +1,64 @@ +VER_NO: 369d2d860d34e777c0f7d545a7dfc3c4 +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 16, start : 0, type : 'uint:16', wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: Efuse write disable mask, rloc: 'EFUSE_BLK0_RDATA0_REG[15:0]', bloc: 'B0,B1'} + RD_DIS : {show: y, blk : 0, word: 0, pos: 16, len : 4, start : 16, type : 'uint:4', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK1-3, rloc: 'EFUSE_BLK0_RDATA0_REG[19:16]', bloc: 'B2[3:0]'} + FLASH_CRYPT_CNT : {show: y, blk : 0, word: 0, pos: 20, len : 7, start : 20, type : 'uint:7', wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Flash encryption is enabled if this field has an odd number of bits set, rloc: 'EFUSE_BLK0_RDATA0_REG[26:20]', bloc: 'B2[7:4],B3[2:0]'} + UART_DOWNLOAD_DIS : {show: y, blk : 0, word: 0, pos: 27, len : 1, start : 27, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Disable UART download mode. Valid for ESP32 V3 and newer; only, rloc: 'EFUSE_BLK0_RDATA0_REG[27]', bloc: 'B3[3]'} + RESERVED_0_28 : {show: n, blk : 0, word: 0, pos: 28, len : 4, start : 28, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_BLK0_RDATA0_REG[31:28]', bloc: 'B3[7:4]'} + MAC : {show: y, blk : 0, word: 1, pos : 0, len : 48, start : 32, type : 'bytes:6', wr_dis : 3, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_BLK0_RDATA1_REG, bloc: 'B4,B5,B6,B7,B8,B9'} + MAC_CRC : {show: y, blk : 0, word: 2, pos: 16, len : 8, start : 80, type : 'uint:8', wr_dis : 3, rd_dis: null, alt : MAC_FACTORY_CRC, dict : '', desc: CRC8 for MAC address, rloc: 'EFUSE_BLK0_RDATA2_REG[23:16]', bloc: B10} + RESERVE_0_88 : {show: n, blk : 0, word: 2, pos: 24, len : 8, start : 88, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA2_REG[31:24]', bloc: B11} + DISABLE_APP_CPU : {show: y, blk : 0, word: 3, pos : 0, len : 1, start : 96, type : bool, wr_dis : 3, rd_dis: null, alt : CHIP_VER_DIS_APP_CPU, dict : '', desc: Disables APP CPU, rloc: 'EFUSE_BLK0_RDATA3_REG[0]', bloc: 'B12[0]'} + DISABLE_BT : {show: y, blk : 0, word: 3, pos : 1, len : 1, start : 97, type : bool, wr_dis : 3, rd_dis: null, alt : CHIP_VER_DIS_BT, dict : '', desc: Disables Bluetooth, rloc: 'EFUSE_BLK0_RDATA3_REG[1]', bloc: 'B12[1]'} + CHIP_PACKAGE_4BIT : {show: y, blk : 0, word: 3, pos : 2, len : 1, start : 98, type : bool, wr_dis: null, rd_dis: null, alt : CHIP_VER_PKG_4BIT, dict : '', desc: 'Chip package identifier #4bit', rloc: 'EFUSE_BLK0_RDATA3_REG[2]', bloc: 'B12[2]'} + DIS_CACHE : {show: y, blk : 0, word: 3, pos : 3, len : 1, start : 99, type : bool, wr_dis : 3, rd_dis: null, alt : CHIP_VER_DIS_CACHE, dict : '', desc: Disables cache, rloc: 'EFUSE_BLK0_RDATA3_REG[3]', bloc: 'B12[3]'} + SPI_PAD_CONFIG_HD : {show: y, blk : 0, word: 3, pos : 4, len : 5, start: 100, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: read for SPI_pad_config_hd, rloc: 'EFUSE_BLK0_RDATA3_REG[8:4]', bloc: 'B12[7:4],B13[0]'} + CHIP_PACKAGE : {show: y, blk : 0, word: 3, pos : 9, len : 3, start: 105, type : 'uint:3', wr_dis: null, rd_dis: null, alt : CHIP_VER_PKG, dict : '', desc: Chip package identifier, rloc: 'EFUSE_BLK0_RDATA3_REG[11:9]', bloc: 'B13[3:1]'} + CHIP_CPU_FREQ_LOW : {show: y, blk : 0, word: 3, pos: 12, len : 1, start: 108, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise, rloc: 'EFUSE_BLK0_RDATA3_REG[12]', bloc: 'B13[4]'} + CHIP_CPU_FREQ_RATED : {show: y, blk : 0, word: 3, pos: 13, len : 1, start: 109, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: If set; the ESP32's maximum CPU frequency has been rated, rloc: 'EFUSE_BLK0_RDATA3_REG[13]', bloc: 'B13[5]'} + BLK3_PART_RESERVE : {show: y, blk : 0, word: 3, pos: 14, len : 1, start: 110, type : bool, wr_dis : 10, rd_dis : 3, alt : '', dict : '', desc: BLOCK3 partially served for ADC calibration data, rloc: 'EFUSE_BLK0_RDATA3_REG[14]', bloc: 'B13[6]'} + CHIP_VER_REV1 : {show: y, blk : 0, word: 3, pos: 15, len : 1, start: 111, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: bit is set to 1 for rev1 silicon, rloc: 'EFUSE_BLK0_RDATA3_REG[15]', bloc: 'B13[7]'} + RESERVE_0_112 : {show: n, blk : 0, word: 3, pos: 16, len : 16, start: 112, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA3_REG[31:16]', bloc: 'B14,B15'} + CLK8M_FREQ : {show: y, blk : 0, word: 4, pos : 0, len : 8, start: 128, type : 'uint:8', wr_dis : 4, rd_dis: null, alt : CK8M_FREQ, dict : '', desc: 8MHz clock freq override, rloc: 'EFUSE_BLK0_RDATA4_REG[7:0]', bloc: B16} + ADC_VREF : {show: y, blk : 0, word: 4, pos : 8, len : 5, start: 136, type : 'uint:5', wr_dis : 4, rd_dis: null, alt : '', dict : '', desc: True ADC reference voltage, rloc: 'EFUSE_BLK0_RDATA4_REG[12:8]', bloc: 'B17[4:0]'} + RESERVE_0_141 : {show: n, blk : 0, word: 4, pos: 13, len : 1, start: 141, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA4_REG[13]', bloc: 'B17[5]'} + XPD_SDIO_REG : {show: y, blk : 0, word: 4, pos: 14, len : 1, start: 142, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: read for XPD_SDIO_REG, rloc: 'EFUSE_BLK0_RDATA4_REG[14]', bloc: 'B17[6]'} + XPD_SDIO_TIEH : {show: y, blk : 0, word: 4, pos: 15, len : 1, start: 143, type : bool, wr_dis : 5, rd_dis: null, alt : SDIO_TIEH, dict: '{1: "3.3V", 0: "1.8V"}', desc: If XPD_SDIO_FORCE & XPD_SDIO_REG, rloc: 'EFUSE_BLK0_RDATA4_REG[15]', bloc: 'B17[7]'} + XPD_SDIO_FORCE : {show: y, blk : 0, word: 4, pos: 16, len : 1, start: 144, type : bool, wr_dis : 5, rd_dis: null, alt : SDIO_FORCE, dict : '', desc: Ignore MTDI pin (GPIO12) for VDD_SDIO on reset, rloc: 'EFUSE_BLK0_RDATA4_REG[16]', bloc: 'B18[0]'} + RESERVE_0_145 : {show: n, blk : 0, word: 4, pos: 17, len : 15, start: 145, type : 'uint:15', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA4_REG[31:17]', bloc: 'B18[7:1],B19'} + SPI_PAD_CONFIG_CLK : {show: y, blk : 0, word: 5, pos : 0, len : 5, start: 160, type : 'uint:5', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Override SD_CLK pad (GPIO6/SPICLK), rloc: 'EFUSE_BLK0_RDATA5_REG[4:0]', bloc: 'B20[4:0]'} + SPI_PAD_CONFIG_Q : {show: y, blk : 0, word: 5, pos : 5, len : 5, start: 165, type : 'uint:5', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Override SD_DATA_0 pad (GPIO7/SPIQ), rloc: 'EFUSE_BLK0_RDATA5_REG[9:5]', bloc: 'B20[7:5],B21[1:0]'} + SPI_PAD_CONFIG_D : {show: y, blk : 0, word: 5, pos: 10, len : 5, start: 170, type : 'uint:5', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Override SD_DATA_1 pad (GPIO8/SPID), rloc: 'EFUSE_BLK0_RDATA5_REG[14:10]', bloc: 'B21[6:2]'} + SPI_PAD_CONFIG_CS0 : {show: y, blk : 0, word: 5, pos: 15, len : 5, start: 175, type : 'uint:5', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Override SD_CMD pad (GPIO11/SPICS0), rloc: 'EFUSE_BLK0_RDATA5_REG[19:15]', bloc: 'B21[7],B22[3:0]'} + CHIP_VER_REV2 : {show: y, blk : 0, word: 5, pos: 20, len : 1, start: 180, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_BLK0_RDATA5_REG[20]', bloc: 'B22[4]'} + RESERVE_0_181 : {show: n, blk : 0, word: 5, pos: 21, len : 1, start: 181, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA5_REG[21]', bloc: 'B22[5]'} + VOL_LEVEL_HP_INV : {show: y, blk : 0, word: 5, pos: 22, len : 2, start: 182, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)', rloc: 'EFUSE_BLK0_RDATA5_REG[23:22]', bloc: 'B22[7:6]'} + WAFER_VERSION_MINOR : {show: y, blk : 0, word: 5, pos: 24, len : 2, start: 184, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_BLK0_RDATA5_REG[25:24]', bloc: 'B23[1:0]'} + RESERVE_0_186 : {show: n, blk : 0, word: 5, pos: 26, len : 2, start: 186, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA5_REG[27:26]', bloc: 'B23[3:2]'} + FLASH_CRYPT_CONFIG : {show: y, blk : 0, word: 5, pos: 28, len : 4, start: 188, type : 'uint:4', wr_dis : 10, rd_dis : 3, alt : ENCRYPT_CONFIG, dict : '', desc: Flash encryption config (key tweak bits), rloc: 'EFUSE_BLK0_RDATA5_REG[31:28]', bloc: 'B23[7:4]'} + CODING_SCHEME : {show: y, blk : 0, word: 6, pos : 0, len : 2, start: 192, type : 'uint:2', wr_dis : 10, rd_dis : 3, alt : '', dict: '{0: "NONE (BLK1-3 len=256 bits)", 1: "3/4 (BLK1-3 len=192 bits)", 2: "REPEAT (BLK1-3 len=128 bits) not supported", 3: "NONE (BLK1-3 len=256 bits)"}', desc: Efuse variable block length scheme, rloc: 'EFUSE_BLK0_RDATA6_REG[1:0]', bloc: 'B24[1:0]'} + CONSOLE_DEBUG_DISABLE: {show: y, blk : 0, word: 6, pos : 2, len : 1, start: 194, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: Disable ROM BASIC interpreter fallback, rloc: 'EFUSE_BLK0_RDATA6_REG[2]', bloc: 'B24[2]'} + DISABLE_SDIO_HOST : {show: y, blk : 0, word: 6, pos : 3, len : 1, start: 195, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_BLK0_RDATA6_REG[3]', bloc: 'B24[3]'} + ABS_DONE_0 : {show: y, blk : 0, word: 6, pos : 4, len : 1, start: 196, type : bool, wr_dis : 12, rd_dis: null, alt : '', dict : '', desc: Secure boot V1 is enabled for bootloader image, rloc: 'EFUSE_BLK0_RDATA6_REG[4]', bloc: 'B24[4]'} + ABS_DONE_1 : {show: y, blk : 0, word: 6, pos : 5, len : 1, start: 197, type : bool, wr_dis : 13, rd_dis: null, alt : '', dict : '', desc: Secure boot V2 is enabled for bootloader image, rloc: 'EFUSE_BLK0_RDATA6_REG[5]', bloc: 'B24[5]'} + JTAG_DISABLE : {show: y, blk : 0, word: 6, pos : 6, len : 1, start: 198, type : bool, wr_dis : 14, rd_dis: null, alt : DISABLE_JTAG, dict : '', desc: Disable JTAG, rloc: 'EFUSE_BLK0_RDATA6_REG[6]', bloc: 'B24[6]'} + DISABLE_DL_ENCRYPT : {show: y, blk : 0, word: 6, pos : 7, len : 1, start: 199, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: Disable flash encryption in UART bootloader, rloc: 'EFUSE_BLK0_RDATA6_REG[7]', bloc: 'B24[7]'} + DISABLE_DL_DECRYPT : {show: y, blk : 0, word: 6, pos : 8, len : 1, start: 200, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: Disable flash decryption in UART bootloader, rloc: 'EFUSE_BLK0_RDATA6_REG[8]', bloc: 'B25[0]'} + DISABLE_DL_CACHE : {show: y, blk : 0, word: 6, pos : 9, len : 1, start: 201, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: Disable flash cache in UART bootloader, rloc: 'EFUSE_BLK0_RDATA6_REG[9]', bloc: 'B25[1]'} + KEY_STATUS : {show: y, blk : 0, word: 6, pos: 10, len : 1, start: 202, type : bool, wr_dis : 10, rd_dis : 3, alt : '', dict : '', desc: Usage of efuse block 3 (reserved), rloc: 'EFUSE_BLK0_RDATA6_REG[10]', bloc: 'B25[2]'} + RESERVE_0_203 : {show: n, blk : 0, word: 6, pos: 11, len : 21, start: 203, type : 'uint:21', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_BLK0_RDATA6_REG[31:11]', bloc: 'B25[7:3],B26,B27'} + BLOCK1 : {show: y, blk : 1, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 7, rd_dis : 0, alt : ENCRYPT_FLASH_KEY, dict : '', desc: Flash encryption key, rloc: EFUSE_BLK1_RDATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK2 : {show: y, blk : 2, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 8, rd_dis : 1, alt : SECURE_BOOT_KEY, dict : '', desc: Security boot key, rloc: EFUSE_BLK2_RDATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + CUSTOM_MAC_CRC : {show: y, blk : 3, word: 0, pos : 0, len : 8, start : 0, type : 'uint:8', wr_dis : 9, rd_dis : 2, alt : MAC_CUSTOM_CRC, dict : '', desc: CRC8 for custom MAC address, rloc: 'EFUSE_BLK3_RDATA0_REG[7:0]', bloc: B0} + CUSTOM_MAC : {show: y, blk : 3, word: 0, pos : 8, len : 48, start : 8, type : 'bytes:6', wr_dis : 9, rd_dis : 2, alt : MAC_CUSTOM, dict : '', desc: Custom MAC address, rloc: 'EFUSE_BLK3_RDATA0_REG[31:8]', bloc: 'B1,B2,B3,B4,B5,B6'} + RESERVED_3_56 : {show: n, blk : 3, word: 1, pos: 24, len : 8, start : 56, type : 'uint:8', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_BLK3_RDATA1_REG[31:24]', bloc: B7} + BLK3_RESERVED_2 : {show: n, blk : 3, word: 2, pos : 0, len : 32, start : 64, type : 'uint:32', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: read for BLOCK3, rloc: EFUSE_BLK3_RDATA2_REG, bloc: 'B8,B9,B10,B11'} + ADC1_TP_LOW : {show: y, blk : 3, word: 3, pos : 0, len : 7, start : 96, type : 'uint:7', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[6:0]', bloc: 'B12[6:0]'} + ADC1_TP_HIGH : {show: y, blk : 3, word: 3, pos : 7, len : 9, start: 103, type : 'uint:9', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[15:7]', bloc: 'B12[7],B13'} + ADC2_TP_LOW : {show: y, blk : 3, word: 3, pos: 16, len : 7, start: 112, type : 'uint:7', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[22:16]', bloc: 'B14[6:0]'} + ADC2_TP_HIGH : {show: y, blk : 3, word: 3, pos: 23, len : 9, start: 119, type : 'uint:9', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE, rloc: 'EFUSE_BLK3_RDATA3_REG[31:23]', bloc: 'B14[7],B15'} + SECURE_VERSION : {show: y, blk : 3, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: Secure version for anti-rollback, rloc: EFUSE_BLK3_RDATA4_REG, bloc: 'B16,B17,B18,B19'} + RESERVED_3_160 : {show: n, blk : 3, word: 5, pos : 0, len : 24, start: 160, type : 'uint:24', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_BLK3_RDATA5_REG[23:0]', bloc: 'B20,B21,B22'} + MAC_VERSION : {show: y, blk : 3, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis : 9, rd_dis : 2, alt : MAC_CUSTOM_VER, dict: '{1: "Custom MAC in BLOCK3"}', desc: Version of the MAC field, rloc: 'EFUSE_BLK3_RDATA5_REG[31:24]', bloc: B23} + BLK3_RESERVED_6 : {show: n, blk : 3, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: read for BLOCK3, rloc: EFUSE_BLK3_RDATA6_REG, bloc: 'B24,B25,B26,B27'} + BLK3_RESERVED_7 : {show: n, blk : 3, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 9, rd_dis : 2, alt : '', dict : '', desc: read for BLOCK3, rloc: EFUSE_BLK3_RDATA7_REG, bloc: 'B28,B29,B30,B31'} diff --git a/espefuse/efuse_defs/esp32c2.yaml b/espefuse/efuse_defs/esp32c2.yaml new file mode 100644 index 000000000..e89e354fc --- /dev/null +++ b/espefuse/efuse_defs/esp32c2.yaml @@ -0,0 +1,53 @@ +VER_NO: 897499b0349a608b895d467abbcf006b +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 8, start : 0, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: 'EFUSE_RD_WR_DIS_REG[7:0]', bloc: B0} + RESERVED_0_8 : {show: n, blk : 0, word: 0, pos : 8, len : 24, start : 8, type : 'uint:24', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_WR_DIS_REG[31:8]', bloc: 'B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 2, start : 32, type : 'uint:2', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK3, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[1:0]', bloc: 'B1[1:0]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 1, pos : 2, len : 2, start : 34, type : 'uint:2', wr_dis : 1, rd_dis: null, alt : '', dict: '{0: "40000", 1: "80000", 2: "160000", 3: "320000"}', desc: RTC watchdog timeout threshold; in unit of slow clock cycle, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[3:2]', bloc: 'B1[3:2]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos : 4, len : 1, start : 36, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable pad jtag, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[4]', bloc: 'B1[4]'} + DIS_DOWNLOAD_ICACHE : {show: y, blk : 0, word: 1, pos : 5, len : 1, start : 37, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: The bit be set to disable icache in download mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[5]', bloc: 'B1[5]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT: {show: y, blk : 0, word: 1, pos : 6, len : 1, start : 38, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: The bit be set to disable manual encryption, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6]', bloc: 'B1[6]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 1, pos : 7, len : 3, start : 39, type : 'uint:3', wr_dis : 2, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9:7]', bloc: 'B1[7],B2[1:0]'} + XTS_KEY_LENGTH_256 : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict: '{0: "128 bits key", 1: "256 bits key"}', desc: Flash encryption key length, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B2[2]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 1, pos: 11, len : 2, start : 43, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12:11]', bloc: 'B2[4:3]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Set this bit to force ROM code to send a resume command during SPI boot, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B2[5]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7)', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B2[6]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: This bit set means disable direct_boot mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B2[7]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 16, len : 1, start : 48, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable secure UART download mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[16]', bloc: 'B3[0]'} + FLASH_TPUW : {show: y, blk : 0, word: 1, pos: 17, len : 4, start : 49, type : 'uint:4', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20:17]', bloc: 'B3[4:1]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 1, pos: 21, len : 1, start : 53, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: The bit be set to enable secure boot, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[21]', bloc: 'B3[5]'} + SECURE_VERSION : {show: y, blk : 0, word: 1, pos: 22, len : 4, start : 54, type : 'uint:4', wr_dis : 4, rd_dis: null, alt : '', dict : '', desc: Secure version for anti-rollback, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25:22]', bloc: 'B3[7:6],B4[1:0]'} + CUSTOM_MAC_USED : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 4, rd_dis: null, alt : ENABLE_CUSTOM_MAC, dict : '', desc: True if MAC_CUSTOM is burned, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B4[2]'} + DISABLE_WAFER_VERSION_MAJOR: {show: y, blk : 0, word: 1, pos: 27, len : 1, start : 59, type : bool, wr_dis : 4, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[27]', bloc: 'B4[3]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 0, word: 1, pos: 28, len : 1, start : 60, type : bool, wr_dis : 4, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28]', bloc: 'B4[4]'} + RESERVED_0_61 : {show: n, blk : 0, word: 1, pos: 29, len : 3, start : 61, type : 'uint:3', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:29]', bloc: 'B4[7:5]'} + CUSTOM_MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 5, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC address, rloc: EFUSE_RD_BLK1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + RESERVED_1_48 : {show: n, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'uint:16', wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_BLK1_DATA1_REG[31:16]', bloc: 'B6,B7'} + SYSTEM_DATA2 : {show: n, blk : 1, word: 2, pos : 0, len : 24, start : 64, type : 'uint:24', wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: 'Stores the bits [64:87] of system data', rloc: 'EFUSE_RD_BLK1_DATA2_REG[23:0]', bloc: 'B8,B9,B10'} + MAC : {show: y, blk : 2, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 6, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_BLK2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + WAFER_VERSION_MINOR : {show: y, blk : 2, word: 1, pos: 16, len : 4, start : 48, type : 'uint:4', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR, rloc: 'EFUSE_RD_BLK2_DATA1_REG[19:16]', bloc: 'B6[3:0]'} + WAFER_VERSION_MAJOR : {show: y, blk : 2, word: 1, pos: 20, len : 2, start : 52, type : 'uint:2', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MAJOR, rloc: 'EFUSE_RD_BLK2_DATA1_REG[21:20]', bloc: 'B6[5:4]'} + PKG_VERSION : {show: y, blk : 2, word: 1, pos: 22, len : 3, start : 54, type : 'uint:3', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: EFUSE_PKG_VERSION, rloc: 'EFUSE_RD_BLK2_DATA1_REG[24:22]', bloc: 'B6[7:6],B7[0]'} + BLK_VERSION_MINOR : {show: y, blk : 2, word: 1, pos: 25, len : 3, start : 57, type : 'uint:3', wr_dis : 6, rd_dis: null, alt : '', dict: '{0: "No calib", 1: "With calib"}', desc: Minor version of BLOCK2, rloc: 'EFUSE_RD_BLK2_DATA1_REG[27:25]', bloc: 'B7[3:1]'} + BLK_VERSION_MAJOR : {show: y, blk : 2, word: 1, pos: 28, len : 2, start : 60, type : 'uint:2', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Major version of BLOCK2, rloc: 'EFUSE_RD_BLK2_DATA1_REG[29:28]', bloc: 'B7[5:4]'} + OCODE : {show: y, blk : 2, word: 1, pos: 30, len : 7, start : 62, type : 'uint:7', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: OCode, rloc: 'EFUSE_RD_BLK2_DATA1_REG[31:30]', bloc: 'B7[7:6],B8[4:0]'} + TEMP_CALIB : {show: y, blk : 2, word: 2, pos : 5, len : 9, start : 69, type : 'uint:9', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_BLK2_DATA2_REG[13:5]', bloc: 'B8[7:5],B9[5:0]'} + ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 2, pos: 14, len : 8, start : 78, type : 'uint:8', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_BLK2_DATA2_REG[21:14]', bloc: 'B9[7:6],B10[5:0]'} + ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 2, pos: 22, len : 5, start : 86, type : 'uint:5', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_BLK2_DATA2_REG[26:22]', bloc: 'B10[7:6],B11[2:0]'} + ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 2, pos: 27, len : 8, start : 91, type : 'uint:8', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_BLK2_DATA2_REG[31:27]', bloc: 'B11[7:3],B12[2:0]'} + ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 3, pos : 3, len : 6, start : 99, type : 'uint:6', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_BLK2_DATA3_REG[8:3]', bloc: 'B12[7:3],B13[0]'} + DIG_DBIAS_HVT : {show: y, blk : 2, word: 3, pos : 9, len : 5, start: 105, type : 'uint:5', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 digital dbias when hvt, rloc: 'EFUSE_RD_BLK2_DATA3_REG[13:9]', bloc: 'B13[5:1]'} + DIG_LDO_SLP_DBIAS2 : {show: y, blk : 2, word: 3, pos: 14, len : 7, start: 110, type : 'uint:7', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_DBG0_DBIAS2, rloc: 'EFUSE_RD_BLK2_DATA3_REG[20:14]', bloc: 'B13[7:6],B14[4:0]'} + DIG_LDO_SLP_DBIAS26 : {show: y, blk : 2, word: 3, pos: 21, len : 8, start: 117, type : 'uint:8', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_DBG0_DBIAS26, rloc: 'EFUSE_RD_BLK2_DATA3_REG[28:21]', bloc: 'B14[7:5],B15[4:0]'} + DIG_LDO_ACT_DBIAS26 : {show: y, blk : 2, word: 3, pos: 29, len : 6, start: 125, type : 'uint:6', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_ACT_DBIAS26, rloc: 'EFUSE_RD_BLK2_DATA3_REG[31:29]', bloc: 'B15[7:5],B16[2:0]'} + DIG_LDO_ACT_STEPD10 : {show: y, blk : 2, word: 4, pos : 3, len : 4, start: 131, type : 'uint:4', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_ACT_STEPD10, rloc: 'EFUSE_RD_BLK2_DATA4_REG[6:3]', bloc: 'B16[6:3]'} + RTC_LDO_SLP_DBIAS13 : {show: y, blk : 2, word: 4, pos : 7, len : 7, start: 135, type : 'uint:7', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_SLP_DBIAS13, rloc: 'EFUSE_RD_BLK2_DATA4_REG[13:7]', bloc: 'B16[7],B17[5:0]'} + RTC_LDO_SLP_DBIAS29 : {show: y, blk : 2, word: 4, pos: 14, len : 9, start: 142, type : 'uint:9', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_SLP_DBIAS29, rloc: 'EFUSE_RD_BLK2_DATA4_REG[22:14]', bloc: 'B17[7:6],B18[6:0]'} + RTC_LDO_SLP_DBIAS31 : {show: y, blk : 2, word: 4, pos: 23, len : 6, start: 151, type : 'uint:6', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_SLP_DBIAS31, rloc: 'EFUSE_RD_BLK2_DATA4_REG[28:23]', bloc: 'B18[7],B19[4:0]'} + RTC_LDO_ACT_DBIAS31 : {show: y, blk : 2, word: 4, pos: 29, len : 6, start: 157, type : 'uint:6', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_ACT_DBIAS31, rloc: 'EFUSE_RD_BLK2_DATA4_REG[31:29]', bloc: 'B19[7:5],B20[2:0]'} + RTC_LDO_ACT_DBIAS13 : {show: y, blk : 2, word: 5, pos : 3, len : 8, start: 163, type : 'uint:8', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: BLOCK2 DIG_LDO_ACT_DBIAS13, rloc: 'EFUSE_RD_BLK2_DATA5_REG[10:3]', bloc: 'B20[7:3],B21[2:0]'} + RESERVED_2_171 : {show: n, blk : 2, word: 5, pos: 11, len : 21, start: 171, type : 'uint:21', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_BLK2_DATA5_REG[31:11]', bloc: 'B21[7:3],B22,B23'} + ADC_CALIBRATION_3 : {show: y, blk : 2, word: 6, pos : 0, len : 11, start: 192, type : 'uint:11', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: 'Store the bit [86:96] of ADC calibration data', rloc: 'EFUSE_RD_BLK2_DATA6_REG[10:0]', bloc: 'B24,B25[2:0]'} + BLK2_RESERVED_DATA_0 : {show: n, blk : 2, word: 6, pos: 11, len : 21, start: 203, type : 'uint:21', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: 'Store the bit [0:20] of block2 reserved data', rloc: 'EFUSE_RD_BLK2_DATA6_REG[31:11]', bloc: 'B25[7:3],B26,B27'} + BLK2_RESERVED_DATA_1 : {show: n, blk : 2, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: 'Store the bit [21:52] of block2 reserved data', rloc: EFUSE_RD_BLK2_DATA7_REG, bloc: 'B28,B29,B30,B31'} + BLOCK_KEY0 : {show: y, blk : 3, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 7, rd_dis : 0 1, alt : KEY0, dict : '', desc: BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption, rloc: EFUSE_RD_BLK3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espefuse/efuse_defs/esp32c3.yaml b/espefuse/efuse_defs/esp32c3.yaml new file mode 100644 index 000000000..57872999a --- /dev/null +++ b/espefuse/efuse_defs/esp32c3.yaml @@ -0,0 +1,110 @@ +VER_NO: a85f874ae2b6538ca48b7c3db4a79531 +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + DIS_RTC_RAM_BOOT : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable boot from RTC RAM, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable Icache, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable function of usb switch to jtag in module of usb device, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + DIS_DOWNLOAD_ICACHE : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_USB_DEVICE, dict: '{0: "Enable", 1: "Disable"}', desc: USB-Serial-JTAG, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable the function that forces chip into download mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + RPT4_RESERVED6 : {show: n, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: Set this bit to disable CAN function, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable flash encryption when in download boot modes, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Controls single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV; stored in eFuse, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Controls single-end input threshold vrefl; 0.8 V to 1.04 V with step of 80 mV; stored in eFuse, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Set this bit to exchange USB D+ and D- pins, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Set this bit to vdd spi pin function as gpio, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + BTLC_GPIO_ENABLE : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Enable btlc gpio, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} + POWERGLITCH_EN : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable power glitch function, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} + POWER_GLITCH_DSENSE : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Sample delay configuration of power glitch, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} + RPT4_RESERVED2 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict: '{0: "40000", 1: "80000", 2: "160000", 3: "320000"}', desc: RTC watchdog timeout threshold; in unit of slow clock cycle, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + RPT4_RESERVED3 : {show: n, blk : 0, word: 3, pos: 16, len : 4, start: 112, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19:16]', bloc: 'B14[3:0]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable secure boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable revoking aggressive secure boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RPT4_RESERVED0 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value; Otherwise; the waiting time is twice the configurable value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_LEGACY_SPI_BOOT, dict : '', desc: Disable direct boot mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : UART_PRINT_CHANNEL, dict: '{0: "Enable", 1: "Disable"}', desc: USB printing, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + FLASH_ECC_MODE : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "ROM would Enable Flash ECC 16to18 byte mode", 1: "ROM would use 16to17 byte mode"}', desc: ECC mode in ROM, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_DOWNLOAD_MODE, dict : '', desc: Disable UART download mode through USB-Serial-JTAG, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable secure UART download mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + PIN_POWER_SELECTION : {show: n, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "VDD3P3_CPU", 1: "VDD_SPI"}', desc: GPIO33-GPIO37 power supply selection in ROM code, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + FLASH_TYPE : {show: n, blk : 0, word: 4, pos : 9, len : 1, start: 137, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "4 data lines", 1: "8 data lines"}', desc: Maximum lines of SPI flash, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[9]', bloc: 'B17[1]'} + FLASH_PAGE_SIZE : {show: n, blk : 0, word: 4, pos: 10, len : 2, start: 138, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set Flash page size, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[11:10]', bloc: 'B17[3:2]'} + FLASH_ECC_EN : {show: n, blk : 0, word: 4, pos: 12, len : 1, start: 140, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set 1 to enable ECC for flash boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[12]', bloc: 'B17[4]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos: 13, len : 1, start: 141, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to force ROM code to send a resume command during SPI boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[13]', bloc: 'B17[5]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos: 14, len : 16, start: 142, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Secure version (used by ESP-IDF anti-rollback feature), rloc: 'EFUSE_RD_REPEAT_DATA3_REG[29:14]', bloc: 'B17[7:6],B18,B19[5:0]'} + RESERVED_0_158 : {show: n, blk : 0, word: 4, pos: 30, len : 1, start: 158, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[30]', bloc: 'B19[6]'} + ERR_RST_ENABLE : {show: y, blk : 0, word: 4, pos: 31, len : 1, start: 159, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict: '{0: "without check", 1: "with check"}', desc: Use BLOCK0 to check error record registers, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31]', bloc: 'B19[7]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 0, len : 1, start: 160, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[0]', bloc: 'B20[0]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 1, len : 1, start: 161, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1]', bloc: 'B20[1]'} + RESERVED_0_162 : {show: n, blk : 0, word: 5, pos : 2, len : 22, start: 162, type : 'uint:22', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:2]', bloc: 'B20[7:2],B21,B22'} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + SPI_PAD_CONFIG_CLK : {show: y, blk : 1, word: 1, pos: 16, len : 6, start : 48, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD CLK, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[21:16]', bloc: 'B6[5:0]'} + SPI_PAD_CONFIG_Q : {show: y, blk : 1, word: 1, pos: 22, len : 6, start : 54, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD Q(D1), rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[27:22]', bloc: 'B6[7:6],B7[3:0]'} + SPI_PAD_CONFIG_D : {show: y, blk : 1, word: 1, pos: 28, len : 6, start : 60, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD D(D0), rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:28]', bloc: 'B7[7:4],B8[1:0]'} + SPI_PAD_CONFIG_CS : {show: y, blk : 1, word: 2, pos : 2, len : 6, start : 66, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD CS, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[7:2]', bloc: 'B8[7:2]'} + SPI_PAD_CONFIG_HD : {show: y, blk : 1, word: 2, pos : 8, len : 6, start : 72, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD HD(D3), rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[13:8]', bloc: 'B9[5:0]'} + SPI_PAD_CONFIG_WP : {show: y, blk : 1, word: 2, pos: 14, len : 6, start : 78, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD WP(D2), rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[19:14]', bloc: 'B9[7:6],B10[3:0]'} + SPI_PAD_CONFIG_DQS : {show: y, blk : 1, word: 2, pos: 20, len : 6, start : 84, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD DQS, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[25:20]', bloc: 'B10[7:4],B11[1:0]'} + SPI_PAD_CONFIG_D4 : {show: y, blk : 1, word: 2, pos: 26, len : 6, start : 90, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD D4, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:26]', bloc: 'B11[7:2]'} + SPI_PAD_CONFIG_D5 : {show: y, blk : 1, word: 3, pos : 0, len : 6, start : 96, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD D5, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[5:0]', bloc: 'B12[5:0]'} + SPI_PAD_CONFIG_D6 : {show: y, blk : 1, word: 3, pos : 6, len : 6, start: 102, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD D6, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[11:6]', bloc: 'B12[7:6],B13[3:0]'} + SPI_PAD_CONFIG_D7 : {show: y, blk : 1, word: 3, pos: 12, len : 6, start: 108, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI PAD D7, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:12]', bloc: 'B13[7:4],B14[1:0]'} + WAFER_VERSION_MINOR_LO : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR least significant bits, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} + PKG_VERSION : {show: y, blk : 1, word: 3, pos: 21, len : 3, start: 117, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:21]', bloc: 'B14[7:5]'} + BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + RESERVED_1_123 : {show: n, blk : 1, word: 3, pos: 27, len : 5, start: 123, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:27]', bloc: 'B15[7:3]'} + RESERVED_1_128 : {show: n, blk : 1, word: 4, pos : 0, len : 7, start: 128, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[6:0]', bloc: 'B16[6:0]'} + K_RTC_LDO : {show: y, blk : 1, word: 4, pos : 7, len : 7, start: 135, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_RTC_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[13:7]', bloc: 'B16[7],B17[5:0]'} + K_DIG_LDO : {show: y, blk : 1, word: 4, pos: 14, len : 7, start: 142, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_DIG_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[20:14]', bloc: 'B17[7:6],B18[4:0]'} + V_RTC_DBIAS20 : {show: y, blk : 1, word: 4, pos: 21, len : 8, start: 149, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of rtc dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[28:21]', bloc: 'B18[7:5],B19[4:0]'} + V_DIG_DBIAS20 : {show: y, blk : 1, word: 4, pos: 29, len : 8, start: 157, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of digital dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:29]', bloc: 'B19[7:5],B20[4:0]'} + DIG_DBIAS_HVT : {show: y, blk : 1, word: 5, pos : 5, len : 5, start: 165, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 digital dbias when hvt, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[9:5]', bloc: 'B20[7:5],B21[1:0]'} + THRES_HVT : {show: y, blk : 1, word: 5, pos: 10, len : 10, start: 170, type : 'uint:10', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 pvt threshold when hvt, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[19:10]', bloc: 'B21[7:2],B22[3:0]'} + RESERVED_1_180 : {show: n, blk : 1, word: 5, pos: 20, len : 3, start: 180, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[22:20]', bloc: 'B22[6:4]'} + WAFER_VERSION_MINOR_HI : {show: y, blk : 1, word: 5, pos: 23, len : 1, start: 183, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR most significant bit, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[23]', bloc: 'B22[7]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 5, pos: 24, len : 2, start: 184, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MAJOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[25:24]', bloc: 'B23[1:0]'} + RESERVED_1_186 : {show: n, blk : 1, word: 5, pos: 26, len : 6, start: 186, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[31:26]', bloc: 'B23[7:2]'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 0, len : 2, start: 128, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict: '{0: "No calibration", 1: "With calibration"}', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[1:0]', bloc: 'B16[1:0]'} + RESERVED_2_130 : {show: n, blk : 2, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[2]', bloc: 'B16[2]'} + TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 3, len : 9, start: 131, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[11:3]', bloc: 'B16[7:3],B17[3:0]'} + OCODE : {show: y, blk : 2, word: 4, pos: 12, len : 8, start: 140, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[19:12]', bloc: 'B17[7:4],B18[3:0]'} + ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 20, len : 10, start: 148, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[29:20]', bloc: 'B18[7:4],B19[5:0]'} + ADC1_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 30, len : 10, start: 158, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:30]', bloc: 'B19[7:6],B20'} + ADC1_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 8, len : 10, start: 168, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[17:8]', bloc: 'B21,B22[1:0]'} + ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 5, pos: 18, len : 10, start: 178, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[27:18]', bloc: 'B22[7:2],B23[3:0]'} + ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 5, pos: 28, len : 10, start: 188, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:28]', bloc: 'B23[7:4],B24[5:0]'} + ADC1_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 6, pos : 6, len : 10, start: 198, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[15:6]', bloc: 'B24[7:6],B25'} + ADC1_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 6, pos: 16, len : 10, start: 208, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[25:16]', bloc: 'B26,B27[1:0]'} + ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 6, pos: 26, len : 10, start: 218, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:26]', bloc: 'B27[7:2],B28[3:0]'} + RESERVED_2_228 : {show: n, blk : 2, word: 7, pos : 4, len : 28, start: 228, type : 'uint:28', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:4]', bloc: 'B28[7:4],B29,B30,B31'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC address, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espefuse/efuse_defs/esp32c6.yaml b/espefuse/efuse_defs/esp32c6.yaml new file mode 100644 index 000000000..aee94306f --- /dev/null +++ b/espefuse/efuse_defs/esp32c6.yaml @@ -0,0 +1,106 @@ +VER_NO: 709e8ea096e8a03a10006d40d5451a49 +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + SWAP_UART_SDIO_EN : {show: y, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + DIS_DOWNLOAD_ICACHE : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} + RPT4_RESERVED0_1 : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} + RPT4_RESERVED0_0 : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} + RPT4_RESERVED1_0 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : DPA_SEC_LEVEL, dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} + CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} + RPT4_RESERVED2_1 : {show: n, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RPT4_RESERVED2_0 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + RPT4_RESERVED3_5 : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + RPT4_RESERVED3_4 : {show: n, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + RPT4_RESERVED3_3 : {show: n, blk : 0, word: 4, pos : 9, len : 1, start: 137, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[9]', bloc: 'B17[1]'} + RPT4_RESERVED3_2 : {show: n, blk : 0, word: 4, pos: 10, len : 2, start: 138, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[11:10]', bloc: 'B17[3:2]'} + RPT4_RESERVED3_1 : {show: n, blk : 0, word: 4, pos: 12, len : 1, start: 140, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[12]', bloc: 'B17[4]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos: 13, len : 1, start: 141, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[13]', bloc: 'B17[5]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos: 14, len : 16, start: 142, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[29:14]', bloc: 'B17[7:6],B18,B19[5:0]'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 30, len : 1, start: 158, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[30]', bloc: 'B19[6]'} + RPT4_RESERVED3_0 : {show: n, blk : 0, word: 4, pos: 31, len : 1, start: 159, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31]', bloc: 'B19[7]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 0, len : 1, start: 160, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[0]', bloc: 'B20[0]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 1, len : 1, start: 161, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1]', bloc: 'B20[1]'} + RESERVED_0_162 : {show: n, blk : 0, word: 5, pos : 2, len : 22, start: 162, type : 'uint:22', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:2]', bloc: 'B20[7:2],B21,B22'} + RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:16]', bloc: 'B6,B7'} + MAC_SPI_RESERVED : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} + SPI_PAD_CONF_1 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + SPI_PAD_CONF_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 4, start: 114, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[21:18]', bloc: 'B14[5:2]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 22, len : 2, start: 118, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:22]', bloc: 'B14[7:6]'} + PKG_VERSION : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'} + BLK_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'} + FLASH_CAP : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} + FLASH_TEMP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'} + FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 5, len : 3, start: 133, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[7:5]', bloc: 'B16[7:5]'} + RESERVED_1_136 : {show: n, blk : 1, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:8]', bloc: 'B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SPI_SYS_5_REG, bloc: 'B20,B21,B22,B23'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 0, len : 9, start: 128, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[8:0]', bloc: 'B16,B17[0]'} + OCODE : {show: y, blk : 2, word: 4, pos : 9, len : 8, start: 137, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[16:9]', bloc: 'B17[7:1],B18[0]'} + ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 17, len : 10, start: 145, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[26:17]', bloc: 'B18[7:1],B19[2:0]'} + ADC1_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 27, len : 10, start: 155, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:27]', bloc: 'B19[7:3],B20[4:0]'} + ADC1_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 5, len : 10, start: 165, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[14:5]', bloc: 'B20[7:5],B21[6:0]'} + ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 5, pos: 15, len : 10, start: 175, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[24:15]', bloc: 'B21[7],B22,B23[0]'} + ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 5, pos: 25, len : 10, start: 185, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:25]', bloc: 'B23[7:1],B24[2:0]'} + ADC1_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 6, pos : 3, len : 10, start: 195, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[12:3]', bloc: 'B24[7:3],B25[4:0]'} + ADC1_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 6, pos: 13, len : 10, start: 205, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[22:13]', bloc: 'B25[7:5],B26[6:0]'} + ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 6, pos: 23, len : 10, start: 215, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:23]', bloc: 'B26[7],B27,B28[0]'} + ADC1_INIT_CODE_ATTEN0_CH0 : {show: y, blk : 2, word: 7, pos : 1, len : 4, start: 225, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch0, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[4:1]', bloc: 'B28[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH1 : {show: y, blk : 2, word: 7, pos : 5, len : 4, start: 229, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch1, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[8:5]', bloc: 'B28[7:5],B29[0]'} + ADC1_INIT_CODE_ATTEN0_CH2 : {show: y, blk : 2, word: 7, pos : 9, len : 4, start: 233, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[12:9]', bloc: 'B29[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH3 : {show: y, blk : 2, word: 7, pos: 13, len : 4, start: 237, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:13]', bloc: 'B29[7:5],B30[0]'} + ADC1_INIT_CODE_ATTEN0_CH4 : {show: y, blk : 2, word: 7, pos: 17, len : 4, start: 241, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch4, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[20:17]', bloc: 'B30[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH5 : {show: y, blk : 2, word: 7, pos: 21, len : 4, start: 245, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch5, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[24:21]', bloc: 'B30[7:5],B31[0]'} + ADC1_INIT_CODE_ATTEN0_CH6 : {show: y, blk : 2, word: 7, pos: 25, len : 4, start: 249, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch6, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[28:25]', bloc: 'B31[4:1]'} + RESERVED_2_253 : {show: n, blk : 2, word: 7, pos: 29, len : 3, start: 253, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:29]', bloc: 'B31[7:5]'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espefuse/efuse_defs/esp32h2.yaml b/espefuse/efuse_defs/esp32h2.yaml new file mode 100644 index 000000000..eabcd1f55 --- /dev/null +++ b/espefuse/efuse_defs/esp32h2.yaml @@ -0,0 +1,90 @@ +VER_NO: 304372753f7bc2d7665354c487c05b4e +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + RPT4_RESERVED0_4 : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + POWERGLITCH_EN : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether power glitch function is enabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: n, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} + RPT4_RESERVED0_1 : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} + RPT4_RESERVED0_0 : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} + RPT4_RESERVED1_1 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} + ECDSA_FORCE_USE_HARDWARE_K : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} + CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RPT4_RESERVED2_0 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: Set this bit to disable USB-Serial-JTAG print during rom boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + RPT4_RESERVED3_5 : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos : 9, len : 16, start: 137, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[24:9]', bloc: 'B17[7:1],B18,B19[0]'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 25, len : 1, start: 153, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'} + HYS_EN_PAD0 : {show: y, blk : 0, word: 4, pos: 26, len : 6, start: 154, type : 'uint:6', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Set bits to enable hysteresis function of PAD0~5, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:26]', bloc: 'B19[7:2]'} + HYS_EN_PAD1 : {show: y, blk : 0, word: 5, pos : 0, len : 22, start: 160, type : 'uint:22', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Set bits to enable hysteresis function of PAD6~27, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[21:0]', bloc: 'B20,B21,B22[5:0]'} + RPT4_RESERVED4_1 : {show: n, blk : 0, word: 5, pos: 22, len : 2, start: 182, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:22]', bloc: 'B22[7:6]'} + RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'} + MAC_RESERVED_1 : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} + MAC_RESERVED_0 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 21, len : 2, start: 117, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[22:21]', bloc: 'B14[6:5]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 23, len : 1, start: 119, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_MAC_SYS_3_REG[23]', bloc: 'B14[7]'} + FLASH_CAP : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[28:27]', bloc: 'B15[4:3]'} + FLASH_VENDOR : {show: y, blk : 1, word: 3, pos: 29, len : 3, start: 125, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:29]', bloc: 'B15[7:5]'} + PKG_VERSION : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} + RESERVED_1_131 : {show: n, blk : 1, word: 4, pos : 3, len : 29, start: 131, type : 'uint:29', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_4_REG[31:3]', bloc: 'B16[7:3],B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_5_REG, bloc: 'B20,B21,B22,B23'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + RESERVED_2_128 : {show: n, blk : 2, word: 4, pos : 0, len : 2, start: 128, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[1:0]', bloc: 'B16[1:0]'} + BLK_VERSION_MINOR : {show: y, blk : 2, word: 4, pos : 2, len : 3, start: 130, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[4:2]', bloc: 'B16[4:2]'} + BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 5, len : 2, start: 133, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[6:5]', bloc: 'B16[6:5]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 7, len : 1, start: 135, type : bool, wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[7]', bloc: 'B16[7]'} + RESERVED_2_136 : {show: n, blk : 2, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:8]', bloc: 'B17,B18,B19'} + SYS_DATA_PART1_5 : {show: n, blk : 2, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the fifth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA5_REG, bloc: 'B20,B21,B22,B23'} + SYS_DATA_PART1_6 : {show: n, blk : 2, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the sixth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA6_REG, bloc: 'B24,B25,B26,B27'} + SYS_DATA_PART1_7 : {show: n, blk : 2, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the seventh 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA7_REG, bloc: 'B28,B29,B30,B31'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espefuse/efuse_defs/esp32s2.yaml b/espefuse/efuse_defs/esp32s2.yaml new file mode 100644 index 000000000..45b5900e4 --- /dev/null +++ b/espefuse/efuse_defs/esp32s2.yaml @@ -0,0 +1,119 @@ +VER_NO: 888a61f6f500d9c7ee0aa32016b0bee7 +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + DIS_RTC_RAM_BOOT : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable Icache, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_DCACHE : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable Dcache, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + DIS_DOWNLOAD_ICACHE : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Disables Icache when SoC is in Download mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_DOWNLOAD_DCACHE : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Disables Dcache when SoC is in Download mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable the function that forces chip into download mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + DIS_USB : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable USB OTG function, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: Set this bit to disable the TWAI Controller function, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + DIS_BOOT_REMAP : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Disables capability to Remap RAM to ROM address space, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + RPT4_RESERVED5 : {show: n, blk : 0, word: 1, pos: 16, len : 1, start : 48, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA0_REG[16]', bloc: 'B6[0]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 17, len : 1, start : 49, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[17]', bloc: 'B6[1]'} + HARD_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 18, len : 1, start : 50, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Hardware disables JTAG permanently, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18]', bloc: 'B6[2]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Disables flash encryption when in download boot modes, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 20, len : 2, start : 52, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Controls single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV; stored in eFuse, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[21:20]', bloc: 'B6[5:4]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 22, len : 2, start : 54, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Controls single-end input threshold vrefl; 0.8 V to 1.04 V with step of 80 mV; stored in eFuse, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[23:22]', bloc: 'B6[7:6]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 24, len : 1, start : 56, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Set this bit to exchange USB D+ and D- pins, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24]', bloc: 'B7[0]'} + USB_EXT_PHY_ENABLE : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : EXT_PHY_ENABLE, dict : '', desc: Set this bit to enable external USB PHY, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + USB_FORCE_NOPERSIST : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: If set; forces USB BVALID to 1, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + BLOCK0_VERSION : {show: y, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: BLOCK0 efuse version, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} + VDD_SPI_MODECURLIM : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator switches current limit mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} + VDD_SPI_DREFH : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator high voltage reference, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} + VDD_SPI_DREFM : {show: n, blk : 0, word: 2, pos : 0, len : 2, start : 64, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator medium voltage reference, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[1:0]', bloc: 'B8[1:0]'} + VDD_SPI_DREFL : {show: n, blk : 0, word: 2, pos : 2, len : 2, start : 66, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator low voltage reference, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[3:2]', bloc: 'B8[3:2]'} + VDD_SPI_XPD : {show: y, blk : 0, word: 2, pos : 4, len : 1, start : 68, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[4]', bloc: 'B8[4]'} + VDD_SPI_TIEH : {show: y, blk : 0, word: 2, pos : 5, len : 1, start : 69, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict: '{0: "VDD_SPI connects to 1.8 V LDO", 1: "VDD_SPI connects to VDD3P3_RTC_IO"}', desc: If VDD_SPI_FORCE is 1; determines VDD_SPI voltage, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[5]', bloc: 'B8[5]'} + VDD_SPI_FORCE : {show: y, blk : 0, word: 2, pos : 6, len : 1, start : 70, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[6]', bloc: 'B8[6]'} + VDD_SPI_EN_INIT : {show: n, blk : 0, word: 2, pos : 7, len : 1, start : 71, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Set SPI regulator to 0 to configure init[1:0]=0', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[7]', bloc: 'B8[7]'} + VDD_SPI_ENCURLIM : {show: n, blk : 0, word: 2, pos : 8, len : 1, start : 72, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set SPI regulator to 1 to enable output current limit, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[8]', bloc: 'B9[0]'} + VDD_SPI_DCURLIM : {show: n, blk : 0, word: 2, pos : 9, len : 3, start : 73, type : 'uint:3', wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Tunes the current limit threshold of SPI regulator when tieh=0; about 800 mA/(8+d), rloc: 'EFUSE_RD_REPEAT_DATA1_REG[11:9]', bloc: 'B9[3:1]'} + VDD_SPI_INIT : {show: n, blk : 0, word: 2, pos: 12, len : 2, start : 76, type : 'uint:2', wr_dis : 2, rd_dis: null, alt : '', dict: '{0: "no resistance", 1: "6K", 2: "4K", 3: "2K"}', desc: Adds resistor from LDO output to ground, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[13:12]', bloc: 'B9[5:4]'} + VDD_SPI_DCAP : {show: n, blk : 0, word: 2, pos: 14, len : 2, start : 78, type : 'uint:2', wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Prevents SPI regulator from overshoot, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:14]', bloc: 'B9[7:6]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict: '{0: "40000", 1: "80000", 2: "160000", 3: "320000"}', desc: RTC watchdog timeout threshold; in unit of slow clock cycle, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disabled otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Purpose of KEY0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Purpose of KEY1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Purpose of KEY2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Purpose of KEY3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Purpose of KEY4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Purpose of KEY5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + KEY_PURPOSE_6 : {show: n, blk : 0, word: 3, pos: 16, len : 4, start: 112, type : 'uint:4', wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: Purpose of KEY6, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19:16]', bloc: 'B14[3:0]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable secure boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE: {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable aggressive secure boot key revocation mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RPT4_RESERVED1 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable all download boot modes, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_LEGACY_SPI_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable Legacy SPI boot mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + UART_PRINT_CHANNEL : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "UART0", 1: "UART1"}', desc: Selects the default UART for printing boot messages, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + RPT4_RESERVED3 : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable use of USB OTG in UART download boot mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable secure UART download mode (read/write flash only), rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO46 is low at reset", 2: "Enable when GPIO46 is high at reset", 3: "Disable"}', desc: Set the default UART boot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + PIN_POWER_SELECTION : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "VDD3P3_CPU", 1: "VDD_SPI"}', desc: Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + FLASH_TYPE : {show: y, blk : 0, word: 4, pos : 9, len : 1, start: 137, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "4 data lines", 1: "8 data lines"}', desc: SPI flash type, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[9]', bloc: 'B17[1]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos: 10, len : 1, start: 138, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: If set; forces ROM code to send an SPI flash resume command during SPI boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[10]', bloc: 'B17[2]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos: 11, len : 16, start: 139, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Secure version (used by ESP-IDF anti-rollback feature), rloc: 'EFUSE_RD_REPEAT_DATA3_REG[26:11]', bloc: 'B17[7:3],B18,B19[2:0]'} + RPT4_RESERVED2 : {show: n, blk : 0, word: 4, pos: 27, len : 5, start: 155, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:27]', bloc: 'B19[7:3]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 0, len : 1, start: 160, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[0]', bloc: 'B20[0]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 1, len : 1, start: 161, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1]', bloc: 'B20[1]'} + RESERVED_0_162 : {show: n, blk : 0, word: 5, pos : 2, len : 22, start: 162, type : 'uint:22', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:2]', bloc: 'B20[7:2],B21,B22'} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + SPI_PAD_CONFIG_CLK : {show: y, blk : 1, word: 1, pos: 16, len : 6, start : 48, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure CLK, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[21:16]', bloc: 'B6[5:0]'} + SPI_PAD_CONFIG_Q : {show: y, blk : 1, word: 1, pos: 22, len : 6, start : 54, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure Q(D1), rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[27:22]', bloc: 'B6[7:6],B7[3:0]'} + SPI_PAD_CONFIG_D : {show: y, blk : 1, word: 1, pos: 28, len : 6, start : 60, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D(D0), rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:28]', bloc: 'B7[7:4],B8[1:0]'} + SPI_PAD_CONFIG_CS : {show: y, blk : 1, word: 2, pos : 2, len : 6, start : 66, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure CS, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[7:2]', bloc: 'B8[7:2]'} + SPI_PAD_CONFIG_HD : {show: y, blk : 1, word: 2, pos : 8, len : 6, start : 72, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure HD(D3), rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[13:8]', bloc: 'B9[5:0]'} + SPI_PAD_CONFIG_WP : {show: y, blk : 1, word: 2, pos: 14, len : 6, start : 78, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure WP(D2), rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[19:14]', bloc: 'B9[7:6],B10[3:0]'} + SPI_PAD_CONFIG_DQS : {show: y, blk : 1, word: 2, pos: 20, len : 6, start : 84, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure DQS, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[25:20]', bloc: 'B10[7:4],B11[1:0]'} + SPI_PAD_CONFIG_D4 : {show: y, blk : 1, word: 2, pos: 26, len : 6, start : 90, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D4, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:26]', bloc: 'B11[7:2]'} + SPI_PAD_CONFIG_D5 : {show: y, blk : 1, word: 3, pos : 0, len : 6, start : 96, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D5, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[5:0]', bloc: 'B12[5:0]'} + SPI_PAD_CONFIG_D6 : {show: y, blk : 1, word: 3, pos : 6, len : 6, start: 102, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D6, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[11:6]', bloc: 'B12[7:6],B13[3:0]'} + SPI_PAD_CONFIG_D7 : {show: y, blk : 1, word: 3, pos: 12, len : 6, start: 108, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D7, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:12]', bloc: 'B13[7:4],B14[1:0]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 18, len : 2, start: 114, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MAJOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[19:18]', bloc: 'B14[3:2]'} + WAFER_VERSION_MINOR_HI : {show: y, blk : 1, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR most significant bit, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[20]', bloc: 'B14[4]'} + FLASH_VERSION : {show: y, blk : 1, word: 3, pos: 21, len : 4, start: 117, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Flash version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[24:21]', bloc: 'B14[7:5],B15[0]'} + BLK_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 25, len : 2, start: 121, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:25]', bloc: 'B15[2:1]'} + RESERVED_1_123 : {show: n, blk : 1, word: 3, pos: 27, len : 1, start: 123, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[27]', bloc: 'B15[3]'} + PSRAM_VERSION : {show: y, blk : 1, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PSRAM version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:28]', bloc: 'B15[7:4]'} + PKG_VERSION : {show: y, blk : 1, word: 4, pos : 0, len : 4, start: 128, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[3:0]', bloc: 'B16[3:0]'} + WAFER_VERSION_MINOR_LO : {show: y, blk : 1, word: 4, pos : 4, len : 3, start: 132, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR least significant bits, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[6:4]', bloc: 'B16[6:4]'} + RESERVED_1_135 : {show: n, blk : 1, word: 4, pos : 7, len : 25, start: 135, type : 'uint:25', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:7]', bloc: 'B16[7],B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second part of the zeroth part of system data, rloc: EFUSE_RD_MAC_SPI_SYS_5_REG, bloc: 'B20,B21,B22,B23'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + ADC_CALIB : {show: y, blk : 2, word: 4, pos : 0, len : 4, start: 128, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: 4 bit of ADC calibration, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[3:0]', bloc: 'B16[3:0]'} + BLK_VERSION_MINOR : {show: y, blk : 2, word: 4, pos : 4, len : 3, start: 132, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict: '{0: "No calib", 1: "ADC calib V1", 2: "ADC calib V2"}', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[6:4]', bloc: 'B16[6:4]'} + TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 7, len : 9, start: 135, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[15:7]', bloc: 'B16[7],B17'} + RTCCALIB_V1IDX_A10H : {show: y, blk : 2, word: 4, pos: 16, len : 8, start: 144, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[23:16]', bloc: B18} + RTCCALIB_V1IDX_A11H : {show: y, blk : 2, word: 4, pos: 24, len : 8, start: 152, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:24]', bloc: B19} + RTCCALIB_V1IDX_A12H : {show: y, blk : 2, word: 5, pos : 0, len : 8, start: 160, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[7:0]', bloc: B20} + RTCCALIB_V1IDX_A13H : {show: y, blk : 2, word: 5, pos : 8, len : 8, start: 168, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[15:8]', bloc: B21} + RTCCALIB_V1IDX_A20H : {show: y, blk : 2, word: 5, pos: 16, len : 8, start: 176, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[23:16]', bloc: B22} + RTCCALIB_V1IDX_A21H : {show: y, blk : 2, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:24]', bloc: B23} + RTCCALIB_V1IDX_A22H : {show: y, blk : 2, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[7:0]', bloc: B24} + RTCCALIB_V1IDX_A23H : {show: y, blk : 2, word: 6, pos : 8, len : 8, start: 200, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[15:8]', bloc: B25} + RTCCALIB_V1IDX_A10L : {show: y, blk : 2, word: 6, pos: 16, len : 6, start: 208, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[21:16]', bloc: 'B26[5:0]'} + RTCCALIB_V1IDX_A11L : {show: y, blk : 2, word: 6, pos: 22, len : 6, start: 214, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[27:22]', bloc: 'B26[7:6],B27[3:0]'} + RTCCALIB_V1IDX_A12L : {show: y, blk : 2, word: 6, pos: 28, len : 6, start: 220, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:28]', bloc: 'B27[7:4],B28[1:0]'} + RTCCALIB_V1IDX_A13L : {show: y, blk : 2, word: 7, pos : 2, len : 6, start: 226, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[7:2]', bloc: 'B28[7:2]'} + RTCCALIB_V1IDX_A20L : {show: y, blk : 2, word: 7, pos : 8, len : 6, start: 232, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[13:8]', bloc: 'B29[5:0]'} + RTCCALIB_V1IDX_A21L : {show: y, blk : 2, word: 7, pos: 14, len : 6, start: 238, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[19:14]', bloc: 'B29[7:6],B30[3:0]'} + RTCCALIB_V1IDX_A22L : {show: y, blk : 2, word: 7, pos: 20, len : 6, start: 244, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[25:20]', bloc: 'B30[7:4],B31[1:0]'} + RTCCALIB_V1IDX_A23L : {show: y, blk : 2, word: 7, pos: 26, len : 6, start: 250, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:26]', bloc: 'B31[7:2]'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espefuse/efuse_defs/esp32s3.yaml b/espefuse/efuse_defs/esp32s3.yaml new file mode 100644 index 000000000..6f8b0913c --- /dev/null +++ b/espefuse/efuse_defs/esp32s3.yaml @@ -0,0 +1,129 @@ +VER_NO: 6925129eca795b8b087d31be539740ec +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + DIS_RTC_RAM_BOOT : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable boot from RTC RAM, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable Icache, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_DCACHE : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable Dcache, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + DIS_DOWNLOAD_ICACHE : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_DOWNLOAD_DCACHE : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7)', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable the function that forces chip into download mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + DIS_USB_OTG : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_USB, dict : '', desc: Set this bit to disable USB function, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: Set this bit to disable CAN function, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + DIS_APP_CPU : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Disable app cpu, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : HARD_DIS_JTAG, dict : '', desc: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable flash encryption when in download boot modes, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Controls single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV; stored in eFuse, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Controls single-end input threshold vrefl; 0.8 V to 1.04 V with step of 80 mV; stored in eFuse, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Set this bit to exchange USB D+ and D- pins, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + USB_EXT_PHY_ENABLE : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : EXT_PHY_ENABLE, dict : '', desc: Set this bit to enable external PHY, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + BTLC_GPIO_ENABLE : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Bluetooth GPIO signal output security level control, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} + VDD_SPI_MODECURLIM : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator switches current limit mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} + VDD_SPI_DREFH : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator high voltage reference, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} + VDD_SPI_DREFM : {show: n, blk : 0, word: 2, pos : 0, len : 2, start : 64, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator medium voltage reference, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[1:0]', bloc: 'B8[1:0]'} + VDD_SPI_DREFL : {show: n, blk : 0, word: 2, pos : 2, len : 2, start : 66, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator low voltage reference, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[3:2]', bloc: 'B8[3:2]'} + VDD_SPI_XPD : {show: y, blk : 0, word: 2, pos : 4, len : 1, start : 68, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: SPI regulator power up signal, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[4]', bloc: 'B8[4]'} + VDD_SPI_TIEH : {show: y, blk : 0, word: 2, pos : 5, len : 1, start : 69, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict: '{0: "VDD_SPI connects to 1.8 V LDO", 1: "VDD_SPI connects to VDD3P3_RTC_IO"}', desc: If VDD_SPI_FORCE is 1; determines VDD_SPI voltage, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[5]', bloc: 'B8[5]'} + VDD_SPI_FORCE : {show: y, blk : 0, word: 2, pos : 6, len : 1, start : 70, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Set this bit and force to use the configuration of eFuse to configure VDD_SPI, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[6]', bloc: 'B8[6]'} + VDD_SPI_EN_INIT : {show: n, blk : 0, word: 2, pos : 7, len : 1, start : 71, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Set SPI regulator to 0 to configure init[1:0]=0', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[7]', bloc: 'B8[7]'} + VDD_SPI_ENCURLIM : {show: n, blk : 0, word: 2, pos : 8, len : 1, start : 72, type : bool, wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Set SPI regulator to 1 to enable output current limit, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[8]', bloc: 'B9[0]'} + VDD_SPI_DCURLIM : {show: n, blk : 0, word: 2, pos : 9, len : 3, start : 73, type : 'uint:3', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Tunes the current limit threshold of SPI regulator when tieh=0; about 800 mA/(8+d), rloc: 'EFUSE_RD_REPEAT_DATA1_REG[11:9]', bloc: 'B9[3:1]'} + VDD_SPI_INIT : {show: n, blk : 0, word: 2, pos: 12, len : 2, start : 76, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict: '{0: "no resistance", 1: "6K", 2: "4K", 3: "2K"}', desc: Adds resistor from LDO output to ground, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[13:12]', bloc: 'B9[5:4]'} + VDD_SPI_DCAP : {show: n, blk : 0, word: 2, pos: 14, len : 2, start : 78, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: Prevents SPI regulator from overshoot, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:14]', bloc: 'B9[7:6]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict: '{0: "40000", 1: "80000", 2: "160000", 3: "320000"}', desc: RTC watchdog timeout threshold; in unit of slow clock cycle, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disabled otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + RPT4_RESERVED0 : {show: n, blk : 0, word: 3, pos: 16, len : 4, start: 112, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved (used for four backups method), rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19:16]', bloc: 'B14[3:0]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable secure boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable revoking aggressive secure boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 3, pos: 22, len : 1, start: 118, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable function of usb switch to jtag in module of usb device, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[22]', bloc: 'B14[6]'} + DIS_USB_SERIAL_JTAG : {show: y, blk : 0, word: 3, pos: 23, len : 1, start: 119, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_USB_DEVICE, dict : '', desc: Set this bit to disable usb device, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23]', bloc: 'B14[7]'} + STRAP_JTAG_SEL : {show: y, blk : 0, word: 3, pos: 24, len : 1, start: 120, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[24]', bloc: 'B15[0]'} + USB_PHY_SEL : {show: y, blk : 0, word: 3, pos: 25, len : 1, start: 121, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict: '{0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG", 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}', desc: This bit is used to switch internal PHY and external PHY for USB OTG and USB Device, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[25]', bloc: 'B15[1]'} + POWER_GLITCH_DSENSE : {show: n, blk : 0, word: 3, pos: 26, len : 2, start: 122, type : 'uint:2', wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: Sample delay configuration of power glitch, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:26]', bloc: 'B15[3:2]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_LEGACY_SPI_BOOT, dict : '', desc: Disable direct boot mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : UART_PRINT_CHANNEL, dict: '{0: "Enable", 1: "Disable"}', desc: USB printing, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + FLASH_ECC_MODE : {show: y, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "16to18 byte", 1: "16to17 byte"}', desc: Flash ECC mode in ROM, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_DOWNLOAD_MODE, dict : '', desc: Set this bit to disable UART download mode through USB, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable secure UART download mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO46 is low at reset", 2: "Enable when GPIO46 is high at reset", 3: "Disable"}', desc: Set the default UART boot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + PIN_POWER_SELECTION : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "VDD3P3_CPU", 1: "VDD_SPI"}', desc: Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + FLASH_TYPE : {show: y, blk : 0, word: 4, pos : 9, len : 1, start: 137, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "4 data lines", 1: "8 data lines"}', desc: SPI flash type, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[9]', bloc: 'B17[1]'} + FLASH_PAGE_SIZE : {show: y, blk : 0, word: 4, pos: 10, len : 2, start: 138, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set Flash page size, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[11:10]', bloc: 'B17[3:2]'} + FLASH_ECC_EN : {show: y, blk : 0, word: 4, pos: 12, len : 1, start: 140, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set 1 to enable ECC for flash boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[12]', bloc: 'B17[4]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos: 13, len : 1, start: 141, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Set this bit to force ROM code to send a resume command during SPI boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[13]', bloc: 'B17[5]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos: 14, len : 16, start: 142, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Secure version (used by ESP-IDF anti-rollback feature), rloc: 'EFUSE_RD_REPEAT_DATA3_REG[29:14]', bloc: 'B17[7:6],B18,B19[5:0]'} + POWERGLITCH_EN : {show: n, blk : 0, word: 4, pos: 30, len : 1, start: 158, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable power glitch function, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[30]', bloc: 'B19[6]'} + DIS_USB_OTG_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos: 31, len : 1, start: 159, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable download through USB-OTG, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31]', bloc: 'B19[7]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 0, len : 1, start: 160, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[0]', bloc: 'B20[0]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 1, len : 1, start: 161, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1]', bloc: 'B20[1]'} + RESERVED_0_162 : {show: n, blk : 0, word: 5, pos : 2, len : 22, start: 162, type : 'uint:22', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:2]', bloc: 'B20[7:2],B21,B22'} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + SPI_PAD_CONFIG_CLK : {show: y, blk : 1, word: 1, pos: 16, len : 6, start : 48, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure CLK, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[21:16]', bloc: 'B6[5:0]'} + SPI_PAD_CONFIG_Q : {show: y, blk : 1, word: 1, pos: 22, len : 6, start : 54, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure Q(D1), rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[27:22]', bloc: 'B6[7:6],B7[3:0]'} + SPI_PAD_CONFIG_D : {show: y, blk : 1, word: 1, pos: 28, len : 6, start : 60, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D(D0), rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:28]', bloc: 'B7[7:4],B8[1:0]'} + SPI_PAD_CONFIG_CS : {show: y, blk : 1, word: 2, pos : 2, len : 6, start : 66, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure CS, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[7:2]', bloc: 'B8[7:2]'} + SPI_PAD_CONFIG_HD : {show: y, blk : 1, word: 2, pos : 8, len : 6, start : 72, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure HD(D3), rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[13:8]', bloc: 'B9[5:0]'} + SPI_PAD_CONFIG_WP : {show: y, blk : 1, word: 2, pos: 14, len : 6, start : 78, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure WP(D2), rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[19:14]', bloc: 'B9[7:6],B10[3:0]'} + SPI_PAD_CONFIG_DQS : {show: y, blk : 1, word: 2, pos: 20, len : 6, start : 84, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure DQS, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[25:20]', bloc: 'B10[7:4],B11[1:0]'} + SPI_PAD_CONFIG_D4 : {show: y, blk : 1, word: 2, pos: 26, len : 6, start : 90, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D4, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:26]', bloc: 'B11[7:2]'} + SPI_PAD_CONFIG_D5 : {show: y, blk : 1, word: 3, pos : 0, len : 6, start : 96, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D5, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[5:0]', bloc: 'B12[5:0]'} + SPI_PAD_CONFIG_D6 : {show: y, blk : 1, word: 3, pos : 6, len : 6, start: 102, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D6, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[11:6]', bloc: 'B12[7:6],B13[3:0]'} + SPI_PAD_CONFIG_D7 : {show: y, blk : 1, word: 3, pos: 12, len : 6, start: 108, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: SPI_PAD_configure D7, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:12]', bloc: 'B13[7:4],B14[1:0]'} + WAFER_VERSION_MINOR_LO : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR least significant bits, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} + PKG_VERSION : {show: y, blk : 1, word: 3, pos: 21, len : 3, start: 117, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:21]', bloc: 'B14[7:5]'} + BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + RESERVED_1_123 : {show: n, blk : 1, word: 3, pos: 27, len : 5, start: 123, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:27]', bloc: 'B15[7:3]'} + RESERVED_1_128 : {show: n, blk : 1, word: 4, pos : 0, len : 13, start: 128, type : 'uint:13', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[12:0]', bloc: 'B16,B17[4:0]'} + K_RTC_LDO : {show: y, blk : 1, word: 4, pos: 13, len : 7, start: 141, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_RTC_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[19:13]', bloc: 'B17[7:5],B18[3:0]'} + K_DIG_LDO : {show: y, blk : 1, word: 4, pos: 20, len : 7, start: 148, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_DIG_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[26:20]', bloc: 'B18[7:4],B19[2:0]'} + V_RTC_DBIAS20 : {show: y, blk : 1, word: 4, pos: 27, len : 8, start: 155, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of rtc dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:27]', bloc: 'B19[7:3],B20[2:0]'} + V_DIG_DBIAS20 : {show: y, blk : 1, word: 5, pos : 3, len : 8, start: 163, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of digital dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[10:3]', bloc: 'B20[7:3],B21[2:0]'} + DIG_DBIAS_HVT : {show: y, blk : 1, word: 5, pos: 11, len : 5, start: 171, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 digital dbias when hvt, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[15:11]', bloc: 'B21[7:3]'} + RESERVED_1_176 : {show: n, blk : 1, word: 5, pos: 16, len : 7, start: 176, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[22:16]', bloc: 'B22[6:0]'} + WAFER_VERSION_MINOR_HI : {show: y, blk : 1, word: 5, pos: 23, len : 1, start: 183, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR most significant bit, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[23]', bloc: 'B22[7]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 5, pos: 24, len : 2, start: 184, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MAJOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[25:24]', bloc: 'B23[1:0]'} + ADC2_CAL_VOL_ATTEN3 : {show: y, blk : 1, word: 5, pos: 26, len : 6, start: 186, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: ADC2 calibration voltage at atten3, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[31:26]', bloc: 'B23[7:2]'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 0, len : 2, start: 128, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict: '{0: "No calib", 1: "ADC calib V1"}', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[1:0]', bloc: 'B16[1:0]'} + RESERVED_2_130 : {show: n, blk : 2, word: 4, pos : 2, len : 2, start: 130, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[3:2]', bloc: 'B16[3:2]'} + TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 4, len : 9, start: 132, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[12:4]', bloc: 'B16[7:4],B17[4:0]'} + OCODE : {show: y, blk : 2, word: 4, pos: 13, len : 8, start: 141, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[20:13]', bloc: 'B17[7:5],B18[4:0]'} + ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 21, len : 8, start: 149, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[28:21]', bloc: 'B18[7:5],B19[4:0]'} + ADC1_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 29, len : 6, start: 157, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:29]', bloc: 'B19[7:5],B20[2:0]'} + ADC1_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 3, len : 6, start: 163, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[8:3]', bloc: 'B20[7:3],B21[0]'} + ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 5, pos : 9, len : 6, start: 169, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[14:9]', bloc: 'B21[6:1]'} + ADC2_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 5, pos: 15, len : 8, start: 175, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC2 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[22:15]', bloc: 'B21[7],B22[6:0]'} + ADC2_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 5, pos: 23, len : 6, start: 183, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC2 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[28:23]', bloc: 'B22[7],B23[4:0]'} + ADC2_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos: 29, len : 6, start: 189, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC2 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:29]', bloc: 'B23[7:5],B24[2:0]'} + ADC2_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 6, pos : 3, len : 6, start: 195, type : 'uint:6', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC2 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[8:3]', bloc: 'B24[7:3],B25[0]'} + ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 6, pos : 9, len : 8, start: 201, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[16:9]', bloc: 'B25[7:1],B26[0]'} + ADC1_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 6, pos: 17, len : 8, start: 209, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[24:17]', bloc: 'B26[7:1],B27[0]'} + ADC1_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 6, pos: 25, len : 8, start: 217, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:25]', bloc: 'B27[7:1],B28[0]'} + ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 7, pos : 1, len : 8, start: 225, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[8:1]', bloc: 'B28[7:1],B29[0]'} + ADC2_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 7, pos : 9, len : 8, start: 233, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC2 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:9]', bloc: 'B29[7:1],B30[0]'} + ADC2_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 7, pos: 17, len : 7, start: 241, type : 'uint:7', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC2 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[23:17]', bloc: 'B30[7:1]'} + ADC2_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 7, pos: 24, len : 7, start: 248, type : 'uint:7', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC2 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[30:24]', bloc: 'B31[6:0]'} + RESERVED_2_255 : {show: n, blk : 2, word: 7, pos: 31, len : 1, start: 255, type : bool, wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31]', bloc: 'B31[7]'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index 6f03bc91b..9b0658f7b 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -98,7 +98,7 @@ class ESP32C6ROM(ESP32C3ROM): def get_pkg_version(self): num_word = 3 - return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 29) & 0x07 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x07 def get_minor_chip_version(self): num_word = 3 @@ -110,7 +110,8 @@ def get_major_chip_version(self): def get_chip_description(self): chip_name = { - 0: "ESP32-C6", + 0: "ESP32-C6 (QFN40)", + 1: "ESP32-C6FH4 (QFN32)", }.get(self.get_pkg_version(), "unknown ESP32-C6") major_rev = self.get_major_chip_version() minor_rev = self.get_minor_chip_version() diff --git a/esptool/targets/esp32c6beta.py b/esptool/targets/esp32c6beta.py index 4c4b6bebd..b6e100bb4 100644 --- a/esptool/targets/esp32c6beta.py +++ b/esptool/targets/esp32c6beta.py @@ -16,7 +16,8 @@ class ESP32C6BETAROM(ESP32C3ROM): def get_chip_description(self): chip_name = { - 0: "ESP32-C6", + 0: "ESP32-C6 (QFN40)", + 1: "ESP32-C6FH4 (QFN32)", }.get(self.get_pkg_version(), "unknown ESP32-C6") major_rev = self.get_major_chip_version() minor_rev = self.get_minor_chip_version() diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py index a37617e1d..67a49e54b 100644 --- a/esptool/targets/esp32h2.py +++ b/esptool/targets/esp32h2.py @@ -21,11 +21,16 @@ class ESP32H2ROM(ESP32C6ROM): } def get_pkg_version(self): + num_word = 4 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07 + + def get_minor_chip_version(self): + num_word = 3 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 18) & 0x07 + + def get_major_chip_version(self): num_word = 3 - block1_addr = self.EFUSE_BASE + 0x044 - word3 = self.read_reg(block1_addr + (4 * num_word)) - pkg_version = (word3 >> 21) & 0x0F - return pkg_version + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x03 def get_chip_description(self): chip_name = { diff --git a/esptool/targets/esp32h2beta1.py b/esptool/targets/esp32h2beta1.py index 66b6df902..2720f1586 100644 --- a/esptool/targets/esp32h2beta1.py +++ b/esptool/targets/esp32h2beta1.py @@ -76,19 +76,16 @@ class ESP32H2BETA1ROM(ESP32C3ROM): } def get_pkg_version(self): - num_word = 3 - return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x0F + num_word = 4 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07 def get_minor_chip_version(self): - hi_num_word = 5 - hi = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * hi_num_word)) >> 23) & 0x01 - low_num_word = 3 - low = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * low_num_word)) >> 18) & 0x07 - return (hi << 3) + low + num_word = 3 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 18) & 0x07 def get_major_chip_version(self): - num_word = 5 - return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x03 + num_word = 3 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x03 def get_chip_description(self): chip_name = { diff --git a/setup.py b/setup.py index f23d64bc2..13272e0f1 100644 --- a/setup.py +++ b/setup.py @@ -126,6 +126,7 @@ def find_version(*file_paths): "ecdsa>=0.16.0", "pyserial>=3.0", "reedsolo>=1.5.3,<1.8", + "PyYAML>=5.1", ], packages=find_packages(), include_package_data=True, diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 1a66268b4..6a13934f4 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -184,7 +184,7 @@ def test_get_custom_mac(self): self.espefuse_py("get_custom_mac -h") if arg_chip == "esp32": right_msg = "Custom MAC Address is not set in the device." - elif arg_chip == "esp32h2beta1": + elif arg_chip in ["esp32h2", "esp32h2beta1"]: right_msg = "Custom MAC Address: 00:00:00:00:00:00:00:00 (OK)" else: right_msg = "Custom MAC Address: 00:00:00:00:00:00 (OK)" @@ -346,7 +346,7 @@ def test_write_protect_efuse(self): XTS_KEY_LENGTH_256 UART_PRINT_CONTROL""" efuse_lists2 = "RD_DIS DIS_DOWNLOAD_ICACHE" else: - efuse_lists = """RD_DIS DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD + efuse_lists = """RD_DIS DIS_ICACHE DIS_FORCE_DOWNLOAD DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT USB_EXCHG_PINS WDT_DELAY_SEL SPI_BOOT_CRYPT_CNT SECURE_BOOT_KEY_REVOKE0 SECURE_BOOT_KEY_REVOKE1 @@ -354,14 +354,18 @@ def test_write_protect_efuse(self): KEY_PURPOSE_2 KEY_PURPOSE_3 KEY_PURPOSE_4 KEY_PURPOSE_5 SECURE_BOOT_EN SECURE_BOOT_AGGRESSIVE_REVOKE FLASH_TPUW DIS_DOWNLOAD_MODE - ENABLE_SECURITY_DOWNLOAD - UART_PRINT_CONTROL MAC SPI_PAD_CONFIG_CLK SPI_PAD_CONFIG_Q - SPI_PAD_CONFIG_D SPI_PAD_CONFIG_CS SPI_PAD_CONFIG_HD - SPI_PAD_CONFIG_WP SPI_PAD_CONFIG_DQS SPI_PAD_CONFIG_D4 - SPI_PAD_CONFIG_D5 SPI_PAD_CONFIG_D6 SPI_PAD_CONFIG_D7 - OPTIONAL_UNIQUE_ID + ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL + MAC OPTIONAL_UNIQUE_ID BLOCK_USR_DATA BLOCK_KEY0 BLOCK_KEY1 BLOCK_KEY2 BLOCK_KEY3 BLOCK_KEY4 BLOCK_KEY5""" + if arg_chip not in ["esp32h2", "esp32h2beta1"] and arg_chip not in [ + "esp32c6" + ]: + efuse_lists += """ DIS_DOWNLOAD_ICACHE + SPI_PAD_CONFIG_CLK SPI_PAD_CONFIG_Q + SPI_PAD_CONFIG_D SPI_PAD_CONFIG_CS SPI_PAD_CONFIG_HD + SPI_PAD_CONFIG_WP SPI_PAD_CONFIG_DQS SPI_PAD_CONFIG_D4 + SPI_PAD_CONFIG_D5 SPI_PAD_CONFIG_D6 SPI_PAD_CONFIG_D7""" efuse_lists2 = "RD_DIS DIS_ICACHE" self.espefuse_py(f"write_protect_efuse {efuse_lists}") output = self.espefuse_py(f"write_protect_efuse {efuse_lists2}") @@ -391,7 +395,7 @@ def test_burn_custom_mac(self): else: mac_custom = ( "aa:cd:ef:11:22:33:00:00" - if arg_chip == "esp32h2beta1" + if arg_chip in ["esp32h2", "esp32h2beta1"] else "aa:cd:ef:11:22:33" ) self.espefuse_py(cmd, check_msg=f"Custom MAC Address: {mac_custom} (OK)") @@ -641,7 +645,7 @@ def test_burn_mac_custom_efuse(self): ret_code=2, ) self.espefuse_py("burn_efuse CUSTOM_MAC AA:CD:EF:01:02:03") - if arg_chip in ["esp32h2beta2", "esp32h2beta1"]: + if arg_chip in ["esp32h2", "esp32h2beta1"]: self.espefuse_py( "get_custom_mac", check_msg=f"aa:cd:ef:01:02:03:00:00 {crc_msg}" ) @@ -688,14 +692,13 @@ def test_burn_efuse(self): efuse_from_blk2 = "BLK_VERSION_MAJOR" if arg_chip == "esp32s2": efuse_from_blk2 = "BLK_VERSION_MINOR" - if arg_chip == "esp32h2beta1": - efuse_from_blk2 = "BLOCK2_VERSION" - self.espefuse_py( - f"burn_efuse {efuse_from_blk2} 1", - check_msg="Burn into BLOCK_SYS_DATA is forbidden " - "(RS coding scheme does not allow this).", - ret_code=2, - ) + if arg_chip != "esp32c6": + self.espefuse_py( + f"burn_efuse {efuse_from_blk2} 1", + check_msg="Burn into BLOCK_SYS_DATA is forbidden " + "(RS coding scheme does not allow this).", + ret_code=2, + ) blk1 = "BLOCK_KEY1" blk2 = "BLOCK_KEY2" output = self.espefuse_py( @@ -880,7 +883,10 @@ def test_burn_key_with_6_keys(self): BLOCK_KEY0 {IMAGES_DIR}/256bit XTS_AES_256_KEY_1 \ BLOCK_KEY1 {IMAGES_DIR}/256bit_1 XTS_AES_256_KEY_2 \ BLOCK_KEY2 {IMAGES_DIR}/256bit_2 XTS_AES_128_KEY" - if arg_chip in ["esp32c3", "esp32c6", "esp32h2"]: + if arg_chip in ["esp32c3", "esp32c6"] or arg_chip in [ + "esp32h2", + "esp32h2beta1", + ]: cmd = cmd.replace("XTS_AES_256_KEY_1", "XTS_AES_128_KEY") cmd = cmd.replace("XTS_AES_256_KEY_2", "XTS_AES_128_KEY") self.espefuse_py(cmd + " --no-read-protect --no-write-protect") From 1c728c2678b0b14f68e1ccb4b13915b4be5ff70e Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 18 May 2023 20:03:19 +0800 Subject: [PATCH 017/209] efuse(H2): Adds RF Calibration Information --- espefuse/efuse_defs/esp32h2.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/espefuse/efuse_defs/esp32h2.yaml b/espefuse/efuse_defs/esp32h2.yaml index eabcd1f55..895751a8a 100644 --- a/espefuse/efuse_defs/esp32h2.yaml +++ b/espefuse/efuse_defs/esp32h2.yaml @@ -1,4 +1,4 @@ -VER_NO: 304372753f7bc2d7665354c487c05b4e +VER_NO: 4df10f83de85f2d830b7c466aabb28e7 EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} @@ -56,8 +56,10 @@ EFUSES: RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'} - MAC_RESERVED_1 : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} - MAC_RESERVED_0 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + RXIQ_VERSION : {show: y, blk : 1, word: 2, pos : 0, len : 3, start : 64, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[2:0]', bloc: 'B8[2:0]'} + RXIQ_0 : {show: y, blk : 1, word: 2, pos : 3, len : 7, start : 67, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 0, rloc: 'EFUSE_RD_MAC_SYS_2_REG[9:3]', bloc: 'B8[7:3],B9[1:0]'} + RXIQ_1 : {show: y, blk : 1, word: 2, pos: 10, len : 7, start : 74, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 1, rloc: 'EFUSE_RD_MAC_SYS_2_REG[16:10]', bloc: 'B9[7:2],B10[0]'} + RESERVED_1_81 : {show: n, blk : 1, word: 2, pos: 17, len : 15, start : 81, type : 'uint:15', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:17]', bloc: 'B10[7:1],B11'} MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 21, len : 2, start: 117, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[22:21]', bloc: 'B14[6:5]'} @@ -70,7 +72,7 @@ EFUSES: SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_5_REG, bloc: 'B20,B21,B22,B23'} OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} RESERVED_2_128 : {show: n, blk : 2, word: 4, pos : 0, len : 2, start: 128, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[1:0]', bloc: 'B16[1:0]'} - BLK_VERSION_MINOR : {show: y, blk : 2, word: 4, pos : 2, len : 3, start: 130, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[4:2]', bloc: 'B16[4:2]'} + BLK_VERSION_MINOR : {show: y, blk : 2, word: 4, pos : 2, len : 3, start: 130, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: 'BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1', rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[4:2]', bloc: 'B16[4:2]'} BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 5, len : 2, start: 133, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[6:5]', bloc: 'B16[6:5]'} DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 7, len : 1, start: 135, type : bool, wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[7]', bloc: 'B16[7]'} RESERVED_2_136 : {show: n, blk : 2, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:8]', bloc: 'B17,B18,B19'} From 7377fdbe1367b298faf02d638c0877ac6f7c0a28 Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Mon, 15 May 2023 13:28:50 +0200 Subject: [PATCH 018/209] espsecure: Improve error message for incorrect PEM format Closes https://github.com/espressif/esptool/issues/881 --- espsecure/__init__.py | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/espsecure/__init__.py b/espsecure/__init__.py index 2f0e73f9c..6e85af5d2 100755 --- a/espsecure/__init__.py +++ b/espsecure/__init__.py @@ -202,7 +202,13 @@ def generate_signing_key(args): def load_ecdsa_signing_key(keyfile): """Load ECDSA signing key""" - sk = ecdsa.SigningKey.from_pem(keyfile.read()) + try: + sk = ecdsa.SigningKey.from_pem(keyfile.read()) + except ValueError: + raise esptool.FatalError( + "Incorrect ECDSA private key specified. " + "Please check algorithm and/or format." + ) if sk.curve not in [ecdsa.NIST192p, ecdsa.NIST256p]: raise esptool.FatalError("Supports NIST192p and NIST256p keys only") return sk @@ -221,7 +227,13 @@ def _load_ecdsa_signing_key(keyfile): def _load_ecdsa_verifying_key(keyfile): """Load ECDSA verifying key for Secure Boot V1 only""" - vk = ecdsa.VerifyingKey.from_pem(keyfile.read()) + try: + vk = ecdsa.VerifyingKey.from_pem(keyfile.read()) + except ValueError: + raise esptool.FatalError( + "Incorrect ECDSA public key specified. " + "Please check algorithm and/or format." + ) if vk.curve != ecdsa.NIST256p: raise esptool.FatalError( "Signing key uses incorrect curve. ESP32 Secure Boot only supports " @@ -1645,7 +1657,8 @@ def main(custom_commandline=None): p = subparsers.add_parser( "digest_private_key", help="Generate an SHA-256 digest of the private signing key. " - "This can be used as a reproducible secure bootloader or flash encryption key.", + "This can be used as a reproducible secure bootloader (only secure boot v1) " + "or flash encryption key.", ) p.add_argument( "--keyfile", From 0849c38fa61a05337472946606c9ef713e5daf50 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 11 May 2023 13:58:47 +0200 Subject: [PATCH 019/209] bugfix(usb_jtag_serial): Autofeed super watchdog (SWD) to avoid resets during flashing --- esptool/targets/esp32c3.py | 25 +++++++++++++++---- esptool/targets/esp32c6.py | 5 ++++ esptool/targets/esp32h2.py | 9 +++++++ esptool/targets/esp32s3.py | 25 +++++++++++++++---- .../stub_flasher/stub_flasher_32c3.json | 4 +-- .../stub_flasher/stub_flasher_32c6.json | 4 +-- .../stub_flasher/stub_flasher_32h2.json | 4 +-- .../stub_flasher/stub_flasher_32s3.json | 6 ++--- .../stub_flasher/stub_flasher_32s3beta2.json | 6 ++--- flasher_stub/include/soc_support.h | 18 ++++++++++++- flasher_stub/stub_flasher.c | 8 ++++-- 11 files changed, 89 insertions(+), 25 deletions(-) diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index 3db0dea74..3b3c30153 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -75,10 +75,15 @@ class ESP32C3ROM(ESP32ROM): UARTDEV_BUF_NO = 0x3FCDF07C # Variable in ROM .bss which indicates the port in use UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3 # The above var when USB-JTAG/Serial is used - RTC_CNTL_WDT_WKEY = 0x50D83AA1 RTCCNTL_BASE_REG = 0x60008000 + RTC_CNTL_SWD_CONF_REG = RTCCNTL_BASE_REG + 0x00AC + RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 31 + RTC_CNTL_SWD_WPROTECT_REG = RTCCNTL_BASE_REG + 0x00B0 + RTC_CNTL_SWD_WKEY = 0x8F1D312A + RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090 RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00A8 + RTC_CNTL_WDT_WKEY = 0x50D83AA1 MEMORY_MAP = [ [0x00000000, 0x00010000, "PADDING"], @@ -175,17 +180,27 @@ def uses_usb_jtag_serial(self): return False # Can't detect USB-JTAG/Serial in secure download mode return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_JTAG_SERIAL - def disable_rtc_watchdog(self): - # When USB-JTAG/Serial is used, the RTC watchdog is not reset - # and can then reset the board during flashing. Disable it. + def disable_watchdogs(self): + # When USB-JTAG/Serial is used, the RTC WDT and SWD watchdog are not reset + # and can then reset the board during flashing. Disable or autofeed them. if self.uses_usb_jtag_serial(): + # Disable RTC WDT self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY) self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0) self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0) + # Automatically feed SWD + self.write_reg(self.RTC_CNTL_SWD_WPROTECT_REG, self.RTC_CNTL_SWD_WKEY) + self.write_reg( + self.RTC_CNTL_SWD_CONF_REG, + self.read_reg(self.RTC_CNTL_SWD_CONF_REG) + | self.RTC_CNTL_SWD_AUTO_FEED_EN, + ) + self.write_reg(self.RTC_CNTL_SWD_WPROTECT_REG, 0) + def _post_connect(self): if not self.sync_stub_detected: # Don't run if stub is reused - self.disable_rtc_watchdog() + self.disable_watchdogs() class ESP32C3StubLoader(ESP32C3ROM): diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index 9b0658f7b..e90c33466 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -76,6 +76,11 @@ class ESP32C6ROM(ESP32C3ROM): RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0 # LP_WDT_RWDT_CONFIG0_REG RTC_CNTL_WDTWPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0018 # LP_WDT_RWDT_WPROTECT_REG + RTC_CNTL_SWD_CONF_REG = DR_REG_LP_WDT_BASE + 0x001C # LP_WDT_SWD_CONFIG_REG + RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18 + RTC_CNTL_SWD_WPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0020 # LP_WDT_SWD_WPROTECT_REG + RTC_CNTL_SWD_WKEY = 0x50D83AA1 # LP_WDT_SWD_WKEY, same as WDT key in this case + FLASH_FREQUENCY = { "80m": 0x0, # workaround for wrong mspi HS div value in ROM "40m": 0x0, diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py index 67a49e54b..73fe60c33 100644 --- a/esptool/targets/esp32h2.py +++ b/esptool/targets/esp32h2.py @@ -13,6 +13,15 @@ class ESP32H2ROM(ESP32C6ROM): # Magic value for ESP32H2 CHIP_DETECT_MAGIC_VALUE = [0xD7B73E80] + DR_REG_LP_WDT_BASE = 0x600B1C00 + RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0 # LP_WDT_RWDT_CONFIG0_REG + RTC_CNTL_WDTWPROTECT_REG = DR_REG_LP_WDT_BASE + 0x001C # LP_WDT_RWDT_WPROTECT_REG + + RTC_CNTL_SWD_CONF_REG = DR_REG_LP_WDT_BASE + 0x0020 # LP_WDT_SWD_CONFIG_REG + RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18 + RTC_CNTL_SWD_WPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0024 # LP_WDT_SWD_WPROTECT_REG + RTC_CNTL_SWD_WKEY = 0x50D83AA1 # LP_WDT_SWD_WKEY, same as WDT key in this case + FLASH_FREQUENCY = { "48m": 0xF, "24m": 0x0, diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 660537b51..3f923fd7b 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -83,10 +83,15 @@ class ESP32S3ROM(ESP32ROM): UARTDEV_BUF_NO_USB_OTG = 3 # The above var when USB-OTG is used UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4 # The above var when USB-JTAG/Serial is used - RTC_CNTL_WDT_WKEY = 0x50D83AA1 RTCCNTL_BASE_REG = 0x60008000 + RTC_CNTL_SWD_CONF_REG = RTCCNTL_BASE_REG + 0x00B4 + RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 31 + RTC_CNTL_SWD_WPROTECT_REG = RTCCNTL_BASE_REG + 0x00B8 + RTC_CNTL_SWD_WKEY = 0x8F1D312A + RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090 RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00B0 + RTC_CNTL_WDT_WKEY = 0x50D83AA1 USB_RAM_BLOCK = 0x800 # Max block size USB-OTG is used @@ -238,19 +243,29 @@ def uses_usb_jtag_serial(self): return False # can't detect USB-JTAG/Serial in secure download mode return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_JTAG_SERIAL - def disable_rtc_watchdog(self): - # When USB-JTAG/Serial is used, the RTC watchdog is not reset - # and can then reset the board during flashing. Disable it. + def disable_watchdogs(self): + # When USB-JTAG/Serial is used, the RTC WDT and SWD watchdog are not reset + # and can then reset the board during flashing. Disable them. if self.uses_usb_jtag_serial(): + # Disable RTC WDT self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY) self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0) self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0) + # Automatically feed SWD + self.write_reg(self.RTC_CNTL_SWD_WPROTECT_REG, self.RTC_CNTL_SWD_WKEY) + self.write_reg( + self.RTC_CNTL_SWD_CONF_REG, + self.read_reg(self.RTC_CNTL_SWD_CONF_REG) + | self.RTC_CNTL_SWD_AUTO_FEED_EN, + ) + self.write_reg(self.RTC_CNTL_SWD_WPROTECT_REG, 0) + def _post_connect(self): if self.uses_usb_otg(): self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK if not self.sync_stub_detected: # Don't run if stub is reused - self.disable_rtc_watchdog() + self.disable_watchdogs() def _check_if_can_reset(self): """ diff --git a/esptool/targets/stub_flasher/stub_flasher_32c3.json b/esptool/targets/stub_flasher/stub_flasher_32c3.json index 8426a637a..3bac88b2d 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32c3.json +++ b/esptool/targets/stub_flasher/stub_flasher_32c3.json @@ -1,7 +1,7 @@ { "entry": 1077413532, - "text": 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RTC_CNTL_RTC_WDTWPROTECT_REG +#define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00B4) +#define RTC_CNTL_SWD_WPROTECT_REG (RTCCNTL_BASE_REG + 0x00B8) +#define RTC_CNTL_SWD_WKEY 0x8F1D312A +#define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 31) #endif #ifdef ESP32C3 #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0090) #define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00A8) +#define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00AC) +#define RTC_CNTL_SWD_WPROTECT_REG (RTCCNTL_BASE_REG + 0x00B0) +#define RTC_CNTL_SWD_WKEY 0x8F1D312A +#define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 31) #endif #ifdef ESP32C6 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG +#define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_SWD_CONFIG_REG +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0020) // LP_WDT_SWD_WPROTECT_REG +#define RTC_CNTL_SWD_WKEY 0x50D83AA1 +#define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 18) #endif #ifdef ESP32H2 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_RWDT_WPROTECT_REG +#define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x0020) // LP_WDT_SWD_CONFIG_REG +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0024) // LP_WDT_SWD_WPROTECT_REG +#define RTC_CNTL_SWD_WKEY 0x50D83AA1 +#define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 18) #endif #define RTC_CNTL_WDT_WKEY 0x50D83AA1 diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c index 69edd7cda..bcbbd55eb 100644 --- a/flasher_stub/stub_flasher.c +++ b/flasher_stub/stub_flasher.c @@ -108,13 +108,17 @@ static void reset_cpu_freq() #endif // USE_MAX_CPU_FREQ #if WITH_USB_JTAG_SERIAL -static void disable_rtc_watchdog() +static void disable_watchdogs() { if (stub_uses_usb_jtag_serial()) { WRITE_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY); // Disable write protection WRITE_REG(RTC_CNTL_WDTCONFIG0_REG, 0x0); // Disable RTC watchdog WRITE_REG(RTC_CNTL_WDTWPROTECT_REG, 0x0); // Re-enable write protection + + WRITE_REG(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY); // Disable write protection + REG_SET_MASK(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); // Autofeed super watchdog + WRITE_REG(RTC_CNTL_SWD_WPROTECT_REG, 0x0); // Re-enable write protection } } #endif // WITH_USB_JTAG_SERIAL @@ -450,7 +454,7 @@ void stub_main() #endif // USE_MAX_CPU_FREQ #if WITH_USB_JTAG_SERIAL - disable_rtc_watchdog(); + disable_watchdogs(); #endif // WITH_USB_JTAG_SERIAL /* zero bss */ From b2df4a191c3ff2230d6b8f9d1ec1ee56519313ad Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Mon, 22 May 2023 15:40:05 +0800 Subject: [PATCH 020/209] esptool: Read 64-bit MAC address on C6 and H2 --- esptool/targets/esp32c6.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index e90c33466..a2d736c51 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -136,8 +136,12 @@ def override_vddsdio(self, new_voltage): def read_mac(self): mac0 = self.read_reg(self.MAC_EFUSE_REG) - mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC - bitstring = struct.pack(">II", mac1, mac0)[2:] + mac_reg1 = self.read_reg(self.MAC_EFUSE_REG + 4) + mac1 = mac_reg1 & 0xFFFF + mac_ext = (mac_reg1 >> 16) & 0xFFFF + bitstring = struct.pack(">HIH", mac1, mac0, mac_ext) + # MAC: 60:55:f9:f7:2c:a2:ff:fe + # | mac1| mac0 | mac_ext| return tuple(bitstring) def get_flash_crypt_config(self): From 40cd69e8f23f4b5e0c9a5e460b4e2771c27d1207 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 22 May 2023 11:22:27 +0200 Subject: [PATCH 021/209] bugfix: Adjust wrapper scripts to not import themselves --- espefuse.py | 9 ++++++--- espsecure.py | 9 ++++++--- esptool.py | 9 ++++++--- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/espefuse.py b/espefuse.py index 9b8633a22..2222d4e55 100755 --- a/espefuse.py +++ b/espefuse.py @@ -18,9 +18,12 @@ # Linux/macOS: remove current script directory to avoid importing this file # as a module; we want to import the installed espefuse module instead with contextlib.suppress(ValueError): - if sys.path[0].endswith("/bin"): - sys.path.pop(0) - sys.path.remove(os.path.dirname(sys.executable)) + executable_dir = os.path.dirname(sys.executable) + sys.path = [ + path + for path in sys.path + if not path.endswith(("/bin", "/sbin")) and path != executable_dir + ] # Linux/macOS: delete imported module entry to force Python to load # the module from scratch; this enables importing espefuse module in diff --git a/espsecure.py b/espsecure.py index c58eabf15..29b8e48e8 100755 --- a/espsecure.py +++ b/espsecure.py @@ -18,9 +18,12 @@ # Linux/macOS: remove current script directory to avoid importing this file # as a module; we want to import the installed espsecure module instead with contextlib.suppress(ValueError): - if sys.path[0].endswith("/bin"): - sys.path.pop(0) - sys.path.remove(os.path.dirname(sys.executable)) + executable_dir = os.path.dirname(sys.executable) + sys.path = [ + path + for path in sys.path + if not path.endswith(("/bin", "/sbin")) and path != executable_dir + ] # Linux/macOS: delete imported module entry to force Python to load # the module from scratch; this enables importing espsecure module in diff --git a/esptool.py b/esptool.py index 60e5bd339..ee3fdc90f 100755 --- a/esptool.py +++ b/esptool.py @@ -18,9 +18,12 @@ # Linux/macOS: remove current script directory to avoid importing this file # as a module; we want to import the installed esptool module instead with contextlib.suppress(ValueError): - if sys.path[0].endswith("/bin"): - sys.path.pop(0) - sys.path.remove(os.path.dirname(sys.executable)) + executable_dir = os.path.dirname(sys.executable) + sys.path = [ + path + for path in sys.path + if not path.endswith(("/bin", "/sbin")) and path != executable_dir + ] # Linux/macOS: delete imported module entry to force Python to load # the module from scratch; this enables importing esptool module in From 333fa4e693a787d57ef42886a93a8a3bc8a112e9 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 22 May 2023 15:14:38 +0200 Subject: [PATCH 022/209] bugfix(espsecure): Print a clear error message if incompatible OpenSSL backend is used Closes https://github.com/espressif/esptool/issues/878 --- espsecure/__init__.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/espsecure/__init__.py b/espsecure/__init__.py index 6e85af5d2..d978a862c 100755 --- a/espsecure/__init__.py +++ b/espsecure/__init__.py @@ -1812,6 +1812,16 @@ def _main(): except esptool.FatalError as e: print("\nA fatal error occurred: %s" % e) sys.exit(2) + except ValueError as e: + try: + if [arg for arg in e.args if "Could not deserialize key data." in arg]: + print( + "Note: This error originates from the cryptography module. " + "It is likely not a problem with espsecure, " + "please make sure you are using a compatible OpenSSL backend." + ) + finally: + raise if __name__ == "__main__": From 7812df26073458fb7afb49e7ffc2dabac65d5d91 Mon Sep 17 00:00:00 2001 From: Massimiliano Montagni Date: Thu, 25 May 2023 11:16:11 +0200 Subject: [PATCH 023/209] fix: inconsistent usage of dirs separator --- esptool/loader.py | 4 ++-- flasher_stub/wrap_stub.py | 4 ++-- test/test_espefuse.py | 6 +++--- test/test_image_info.py | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/esptool/loader.py b/esptool/loader.py index ba8b7f5bd..834b26636 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -97,13 +97,13 @@ # Number of times to try writing a data block WRITE_BLOCK_ATTEMPTS = cfg.getint("write_block_attempts", 3) -STUBS_DIR = os.path.join(os.path.dirname(__file__), "./targets/stub_flasher/") +STUBS_DIR = os.path.join(os.path.dirname(__file__), "targets", "stub_flasher") def get_stub_json_path(chip_name): chip_name = strip_chip_name(chip_name) chip_name = chip_name.replace("esp", "") - return STUBS_DIR + "stub_flasher_" + chip_name + ".json" + return os.path.join(STUBS_DIR, f"stub_flasher_{chip_name}.json") def timeout_per_mb(seconds_per_mb, size_bytes): diff --git a/flasher_stub/wrap_stub.py b/flasher_stub/wrap_stub.py index fe063618b..504d9f883 100755 --- a/flasher_stub/wrap_stub.py +++ b/flasher_stub/wrap_stub.py @@ -17,7 +17,7 @@ import esptool # noqa: E402 THIS_DIR = os.path.dirname(__file__) -BUILD_DIR = os.path.join(THIS_DIR, "./build/") +BUILD_DIR = os.path.join(THIS_DIR, "build") def wrap_stub(elf_file): @@ -66,7 +66,7 @@ def default(self, obj): return json.JSONEncoder.default(self, obj) for filename, stub_data in stubs_dict.items(): - with open(BUILD_DIR + filename, "w") as outfile: + with open(os.path.join(BUILD_DIR, filename), "w") as outfile: json.dump(stub_data, outfile, cls=BytesEncoder, indent=4) diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 6a13934f4..68cbc34ee 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -36,9 +36,9 @@ from conftest import arg_chip, arg_port, arg_reset_port, need_to_install_package_err TEST_DIR = os.path.abspath(os.path.dirname(__file__)) -IMAGES_DIR = os.path.join(TEST_DIR, "images/efuse/") -S_IMAGES_DIR = os.path.join(TEST_DIR, "secure_images/") -EFUSE_S_DIR = os.path.join(TEST_DIR, "efuse_scripts/") +IMAGES_DIR = os.path.join(TEST_DIR, "images", "efuse") +S_IMAGES_DIR = os.path.join(TEST_DIR, "secure_images") +EFUSE_S_DIR = os.path.join(TEST_DIR, "efuse_scripts") import pytest diff --git a/test/test_image_info.py b/test/test_image_info.py index 0727081ce..d9edef602 100755 --- a/test/test_image_info.py +++ b/test/test_image_info.py @@ -12,7 +12,7 @@ except ImportError: need_to_install_package_err() -IMAGES_DIR = os.path.join(os.path.abspath(os.path.dirname(__file__)), "images/") +IMAGES_DIR = os.path.join(os.path.abspath(os.path.dirname(__file__)), "images") ESP8266_BIN = "not_4_byte_aligned.bin" @@ -40,7 +40,7 @@ def run_image_info(self, chip, file, version=None): ] if version is not None: cmd += ["--version", str(version)] - cmd += ["".join([IMAGES_DIR, file])] + cmd += ["".join([IMAGES_DIR, os.sep, file])] print("\nExecuting {}".format(" ".join(cmd))) try: From 024cda385ab18b041a84b7545177b4c57a648f53 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 16 May 2023 15:19:25 +0200 Subject: [PATCH 024/209] feat(esptool): add option to dump whole flash based on detected size Closes https://github.com/espressif/esptool/issues/461 --- docs/en/esptool/basic-commands.rst | 8 ++++++++ esptool/__init__.py | 32 +++++++++++++++++++++++++++--- test/test_esptool.py | 4 ++++ 3 files changed, 41 insertions(+), 3 deletions(-) diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index 373803047..f05cc4f03 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -105,6 +105,14 @@ The read_flash command allows reading back the contents of flash. The arguments esptool.py -p PORT -b 460800 read_flash 0 0x200000 flash_contents.bin + +It is also possible to autodetect flash size by using ``ALL`` as size. The above example with autodetection would look like this: + +:: + + esptool.py -p PORT -b 460800 read_flash 0 ALL flash_contents.bin + + .. note:: If ``write_flash`` updated the boot image's :ref:`flash mode and flash size ` during flashing then these bytes may be different when read back. diff --git a/esptool/__init__.py b/esptool/__init__.py index b0579884e..782d37804 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -39,6 +39,7 @@ import traceback from esptool.cmds import ( + DETECTED_FLASH_SIZES, chip_id, detect_chip, detect_flash_size, @@ -526,7 +527,9 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): add_spi_connection_arg(parser_read_flash) parser_read_flash.add_argument("address", help="Start address", type=arg_auto_int) parser_read_flash.add_argument( - "size", help="Size of region to dump", type=arg_auto_int + "size", + help="Size of region to dump. Use `ALL` to read to the end of flash.", + type=arg_auto_size, ) parser_read_flash.add_argument("filename", help="Name of binary dump") parser_read_flash.add_argument( @@ -570,8 +573,9 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): ) parser_erase_region.add_argument( "size", - help="Size of region to erase (must be multiple of 4096)", - type=arg_auto_int, + help="Size of region to erase (must be multiple of 4096). " + "Use `ALL` to erase to the end of flash.", + type=arg_auto_size, ) parser_merge_bin = subparsers.add_parser( @@ -827,6 +831,23 @@ def flash_xmc_startup(): "than 16MB, in case of failure use --no-stub." ) + if getattr(args, "size", "") == "all": + if esp.secure_download_mode: + raise FatalError( + "Detecting flash size is not supported in secure download mode. " + "Set an exact size value." + ) + # detect flash size + flash_id = esp.flash_id() + size_id = flash_id >> 16 + size_str = DETECTED_FLASH_SIZES.get(size_id) + if size_str is None: + raise FatalError( + "Detecting flash size failed. Set an exact size value." + ) + print(f"Detected flash size: {size_str}") + args.size = flash_size_bytes(size_str) + if esp.IS_STUB and hasattr(args, "address") and hasattr(args, "size"): if args.address + args.size > 0x1000000: print( @@ -871,6 +892,11 @@ def arg_auto_int(x): return int(x, 0) +def arg_auto_size(x): + x = x.lower() + return x if x == "all" else arg_auto_int(x) + + def get_port_list(): if list_ports is None: raise FatalError( diff --git a/test/test_esptool.py b/test/test_esptool.py index 897a33718..0d5c108ba 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -776,6 +776,10 @@ def test_region_erase(self): empty = self.readback(0x10000, 0x1000) assert empty == b"\xFF" * 0x1000 + def test_region_erase_all(self): + res = self.run_esptool("erase_region 0x0 ALL") + assert re.search(r"Detected flash size: \d+[KM]B", res) is not None + def test_large_region_erase(self): # verifies that erasing a large region doesn't time out self.run_esptool("erase_region 0x0 0x100000") From 2b6d5e3e11f3af53c82f983f75891bbf1a3536ba Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 29 May 2023 11:17:52 +0200 Subject: [PATCH 025/209] Update version to v4.6 --- esptool/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 782d37804..4271047c9 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.6-dev" +__version__ = "4.6" import argparse import inspect From f7a7f92d28e79de6b2903566c03ce91a14069d6e Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 29 May 2023 11:18:32 +0200 Subject: [PATCH 026/209] Update version to v4.7-dev --- esptool/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 4271047c9..ae5d7816c 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.6" +__version__ = "4.7-dev" import argparse import inspect From 4ffc399914763fdfd65b8f943f500a3163e73809 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 1 Jun 2023 12:33:23 +0200 Subject: [PATCH 027/209] fix(ESP32-S3): Correct RTC WDT registers to fix resets during flashing --- esptool/targets/esp32s3.py | 2 +- esptool/targets/stub_flasher/stub_flasher_32s3.json | 2 +- esptool/targets/stub_flasher/stub_flasher_32s3beta2.json | 2 +- flasher_stub/include/soc_support.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 3f923fd7b..ef611dc8b 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -89,7 +89,7 @@ class ESP32S3ROM(ESP32ROM): RTC_CNTL_SWD_WPROTECT_REG = RTCCNTL_BASE_REG + 0x00B8 RTC_CNTL_SWD_WKEY = 0x8F1D312A - RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090 + RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0098 RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00B0 RTC_CNTL_WDT_WKEY = 0x50D83AA1 diff --git a/esptool/targets/stub_flasher/stub_flasher_32s3.json b/esptool/targets/stub_flasher/stub_flasher_32s3.json index d9963d0a6..ec58b93e7 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32s3.json +++ b/esptool/targets/stub_flasher/stub_flasher_32s3.json @@ -1,6 +1,6 @@ { "entry": 1077381696, - "text": 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"text_start": 1077379072, "data": "ZCvKP7aLN0BDjDdAC5E3QM6MN0BjjDdAzow3QC2NN0D6jTdAbY43QBWON0BBizdAkI03QOyNN0BQjTdAkI43QHqNN0CQjjdAMYw3QI6MN0DOjDdALY03QEmMN0CCizdAUI83QM+QN0BgijdA8ZA3QGCKN0BgijdAYIo3QGCKN0BgijdAYIo3QGCKN0BgijdA6o43QGCKN0DmjzdAz5A3QA==", "data_start": 1070279668 diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index f1fe7fac2..ace371337 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -324,7 +324,7 @@ #ifdef ESP32S3 #define RTC_CNTL_OPTION1_REG (RTCCNTL_BASE_REG + 0x012C) -#define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0090) // RTC_CNTL_RTC_WDTCONFIG0_REG +#define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0098) // RTC_CNTL_RTC_WDTCONFIG0_REG #define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00B0) // RTC_CNTL_RTC_WDTWPROTECT_REG #define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00B4) #define RTC_CNTL_SWD_WPROTECT_REG (RTCCNTL_BASE_REG + 0x00B8) From ccc1648b9370c2b1b18971138cc8ab66c46faa10 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 1 Jun 2023 12:38:58 +0200 Subject: [PATCH 028/209] Update version to v4.6.1 --- esptool/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index ae5d7816c..2f2589a3a 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.7-dev" +__version__ = "4.6.1" import argparse import inspect From 7e6fe297ea1a104d5394282a9a7c2efc310ccff8 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 1 Jun 2023 12:39:27 +0200 Subject: [PATCH 029/209] Update version to v4.7-dev --- esptool/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 2f2589a3a..ae5d7816c 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.6.1" +__version__ = "4.7-dev" import argparse import inspect From a1a51358136b34a1046e9a30c633836cb8a5517d Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 24 May 2023 12:45:50 +0200 Subject: [PATCH 030/209] docs: add explanation for flash_id example to avoid confusion --- docs/en/esptool/remote-serial-ports.rst | 2 +- docs/en/index.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/en/esptool/remote-serial-ports.rst b/docs/en/esptool/remote-serial-ports.rst index f0f75ce3b..5863516f0 100644 --- a/docs/en/esptool/remote-serial-ports.rst +++ b/docs/en/esptool/remote-serial-ports.rst @@ -1,7 +1,7 @@ Remote Serial Ports =================== -It is possible to connect to any networked remote serial port that supports `RFC2217 `__ (Telnet) protocol. To do this, specify the serial port to esptool as ``rfc2217://:``. For example: +It is possible to connect to any networked remote serial port that supports `RFC2217 `__ (Telnet) protocol. To do this, specify the serial port to esptool as ``rfc2217://:``. For example, to read information about your chip's SPI flash, run: :: diff --git a/docs/en/index.rst b/docs/en/index.rst index b1c49be3c..a367fab53 100644 --- a/docs/en/index.rst +++ b/docs/en/index.rst @@ -29,7 +29,7 @@ Getting started is easy: 2) Connect an Espressif chip to your computer. -3) Run ``esptool.py`` commands: +3) Run ``esptool.py`` commands. For example, to read information about your chip's SPI flash, run: :: From f8e5c0c15af960c39afbe7a16c5a5639963c53ed Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Thu, 25 May 2023 13:35:30 +0200 Subject: [PATCH 031/209] docs(boot-log): fix list formatting --- .../advanced-topics/boot-mode-selection.rst | 42 +++++++++---------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index fda23f016..2ff0ac30e 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -287,14 +287,14 @@ Depending on the kind of hardware you have, it may also be possible to manually This fatal error indicates that the bootloader tried to read the software bootloader header at address 0x{IDF_TARGET_BOOTLOADER_OFFSET} but failed to read valid data. Possible reasons for this include: - - There isn't actually a bootloader at offset 0x{IDF_TARGET_BOOTLOADER_OFFSET} (maybe the bootloader was flashed to the wrong offset by mistake, or the flash has been erased and no bootloader has been flashed yet.) - - Physical problem with the connection to the flash chip, or flash chip power. - - Flash encryption is enabled but the bootloader is plaintext. Alternatively, flash encryption is disabled but the bootloader is encrypted ciphertext. + .. list:: - .. only:: esp32 + - There isn't actually a bootloader at offset 0x{IDF_TARGET_BOOTLOADER_OFFSET} (maybe the bootloader was flashed to the wrong offset by mistake, or the flash has been erased and no bootloader has been flashed yet.) + - Physical problem with the connection to the flash chip, or flash chip power. + - Flash encryption is enabled but the bootloader is plaintext. Alternatively, flash encryption is disabled but the bootloader is encrypted ciphertext. - - Boot mode accidentally set to ``HSPI_FLASH_BOOT``, which uses different SPI flash pins. Check {IDF_TARGET_STRAP_BOOT_2_GPIO} (see above). - - VDDSDIO has been enabled at 1.8V (due to MTDI/GPIO12, see above), but this flash chip requires 3.3V so it's browning out. + :esp32: - Boot mode accidentally set to ``HSPI_FLASH_BOOT``, which uses different SPI flash pins. Check {IDF_TARGET_STRAP_BOOT_2_GPIO} (see above). + :esp32: - VDDSDIO has been enabled at 1.8V (due to MTDI/GPIO12, see above), but this flash chip requires 3.3V so it's browning out. Software Bootloader Header Info @@ -317,26 +317,24 @@ Depending on the kind of hardware you have, it may also be possible to manually mode:DIO, clock div:1 - This is normal boot output based on a combination of efuse values and information read from the bootloader header at flash offset 0x{IDF_TARGET_BOOTLOADER_OFFSET}: - - .. only:: esp32 - - - ``configsip: N`` indicates SPI flash config: + This is normal boot output based on a combination of eFuse values and information read from the bootloader header at flash offset 0x{IDF_TARGET_BOOTLOADER_OFFSET}: - - 0 for default SPI flash - - 1 if booting from the HSPI bus (due to EFUSE configuration) - - Any other value indicates that SPI flash pins have been remapped via efuse (the value is the value read from efuse, consult :ref:`espefuse docs ` to get an easier to read representation of these pin mappings). + .. list:: - - ``clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00`` Custom GPIO drive strength values for SPI flash pins. These are read from the bootloader header in flash. Not currently supported. + :esp32: - ``configsip: N`` indicates SPI flash config: + :esp32: - 0 for default SPI flash + :esp32: - 1 if booting from the HSPI bus (due to eFuse configuration) + :esp32: - Any other value indicates that SPI flash pins have been remapped via eFuse (the value is the value read from eFuse, consult :ref:`espefuse docs ` to get an easier to read representation of these pin mappings). - - ``SPIWP:0xNN`` indicates a custom ``WP`` pin value, which is stored in the bootloader header. This pin value is only used if SPI flash pins have been remapped via efuse (as shown in the ``configsip`` value). - All custom pin values but WP are encoded in the configsip byte loaded from efuse, and WP is supplied in the bootloader header. - - ``mode: AAA, clock div: N``. SPI flash access mode. Read from the bootloader header, correspond to the ``--flash_mode`` and ``--flash_freq`` arguments supplied to ``esptool.py write_flash`` or ``esptool.py elf2image``. - - ``mode`` can be DIO, DOUT, QIO, or QOUT. *QIO and QOUT are not supported here*, to boot in a Quad I/O mode the ROM bootloader should load the software bootloader in a Dual I/O mode and then the ESP-IDF software bootloader enables Quad I/O based on the detected flash chip mode. - - ``clock div: N`` is the SPI flash clock frequency divider. This is an integer clock divider value from an 80MHz APB clock, based on the supplied ``--flash_freq`` argument (ie 80MHz=1, 40MHz=2, etc). - The ROM bootloader actually loads the software bootloader at a lower frequency than the flash_freq value. The initial APB clock frequency is equal to the crystal frequency, so with a 40MHz crystal the SPI clock used to load the software bootloader will be half the configured value (40MHz/2=20MHz). - When the software bootloader starts it sets the APB clock to 80MHz causing the SPI clock frequency to match the value set when flashing. + - ``SPIWP:0xNN`` indicates a custom ``WP`` pin value, which is stored in the bootloader header. This pin value is only used if SPI flash pins have been remapped via eFuse (as shown in the ``configsip`` value). + All custom pin values but WP are encoded in the configsip byte loaded from eFuse, and WP is supplied in the bootloader header. + :esp32: - ``clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00`` Custom GPIO drive strength values for SPI flash pins. These are read from the bootloader header in flash. Not currently supported. + - ``mode: AAA, clock div: N``. SPI flash access mode. Read from the bootloader header, correspond to the ``--flash_mode`` and ``--flash_freq`` arguments supplied to ``esptool.py write_flash`` or ``esptool.py elf2image``. + - ``mode`` can be DIO, DOUT, QIO, or QOUT. *QIO and QOUT are not supported here*, to boot in a Quad I/O mode the ROM bootloader should load the software bootloader in a Dual I/O mode and then the ESP-IDF software bootloader enables Quad I/O based on the detected flash chip mode. + - ``clock div: N`` is the SPI flash clock frequency divider. This is an integer clock divider value from an 80MHz APB clock, based on the supplied ``--flash_freq`` argument (ie 80MHz=1, 40MHz=2, etc). + The ROM bootloader actually loads the software bootloader at a lower frequency than the flash_freq value. The initial APB clock frequency is equal to the crystal frequency, so with a 40MHz crystal the SPI clock used to load the software bootloader will be half the configured value (40MHz/2=20MHz). + When the software bootloader starts it sets the APB clock to 80MHz causing the SPI clock frequency to match the value set when flashing. Software Bootloader Load Segments """"""""""""""""""""""""""""""""" From 11216a74d3524d2b11cf86368790b2cb5d10e805 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Thu, 25 May 2023 15:32:49 +0200 Subject: [PATCH 032/209] docs: add c2, c6 and h2 as build targets --- .gitlab-ci.yml | 2 +- docs/_static/esptool_versions.js | 3 + docs/conf_common.py | 20 ++++- .../advanced-topics/boot-mode-selection.rst | 8 +- .../advanced-topics/firmware-image-format.rst | 89 ++++++++++++++----- docs/en/esptool/advanced-commands.rst | 2 +- docs/en/esptool/advanced-options.rst | 2 +- docs/en/esptool/flash-modes.rst | 17 ++-- docs/en/troubleshooting.rst | 2 +- docs/requirements.txt | 2 +- 10 files changed, 111 insertions(+), 36 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index fb947bce1..faaaad309 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -427,7 +427,7 @@ build_docs: script: - cd docs - pip install -r requirements.txt --prefer-binary - - build-docs -l en -t {esp8266,esp32,esp32s2,esp32c3,esp32s3} + - build-docs -l en -t {esp8266,esp32,esp32s2,esp32c3,esp32s3,esp32c2,esp32c6,esp32h2} .deploy_docs_template: stage: deploy_docs diff --git a/docs/_static/esptool_versions.js b/docs/_static/esptool_versions.js index 6bc1a1887..b5e0fab54 100644 --- a/docs/_static/esptool_versions.js +++ b/docs/_static/esptool_versions.js @@ -9,5 +9,8 @@ var DOCUMENTATION_VERSIONS = { { text: "ESP32-S2", value: "esp32s2" }, { text: "ESP32-S3", value: "esp32s3" }, { text: "ESP32-C3", value: "esp32c3" }, + { text: "ESP32-C2", value: "esp32c2" }, + { text: "ESP32-C6", value: "esp32c6" }, + { text: "ESP32-H2", value: "esp32h2" }, ] }; diff --git a/docs/conf_common.py b/docs/conf_common.py index afd4cdd55..3d82118d5 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -1,7 +1,16 @@ from esp_docs.conf_docs import * # noqa: F403,F401 languages = ["en"] -idf_targets = ["esp8266", "esp32", "esp32s2", "esp32s3", "esp32c3"] +idf_targets = [ + "esp8266", + "esp32", + "esp32s2", + "esp32s3", + "esp32c3", + "esp32c2", + "esp32c6", + "esp32h2", +] # link roles config github_repo = "espressif/esptool" @@ -28,12 +37,21 @@ ESP32S3_DOCS = ESP32S2_DOCS +ESP32C2_DOCS = ESP32S3_DOCS + +ESP32C6_DOCS = ESP32C2_DOCS + +ESP32H2_DOCS = ESP32C6_DOCS + conditional_include_dict = { "esp8266": ESP8266_DOCS, "esp32": ESP32_DOCS, "esp32s2": ESP32S2_DOCS, "esp32c3": ESP32C3_DOCS, "esp32s3": ESP32S3_DOCS, + "esp32c2": ESP32C2_DOCS, + "esp32c6": ESP32C6_DOCS, + "esp32h2": ESP32H2_DOCS, } # Extra options required by sphinx_idf_theme diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index 2ff0ac30e..875025397 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -1,8 +1,8 @@ -{IDF_TARGET_STRAP_BOOT_GPIO:default="GPIO0", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0", esp32c3="GPIO9"} +{IDF_TARGET_STRAP_BOOT_GPIO:default="GPIO9", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0"} -{IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO2", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46", esp32c3="GPIO8"} +{IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO8", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46"} -{IDF_TARGET_BOOTLOADER_OFFSET:default="0", esp8266="0", esp32="1000", esp32s2="1000", esp32s3="0", esp32c3="0"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0",esp32="1000", esp32s2="1000"} .. _boot-mode: @@ -84,7 +84,7 @@ This guide explains how to select the boot mode correctly and describes the boot {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be either left unconnected/floating, or driven Low, in order to enter the serial bootloader. - .. only:: esp32c3 + .. only:: esp32c3 or esp32c2 or esp32h2 or esp32c6 {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be driven High, in order to enter the serial bootloader reliably. The strapping combination of {IDF_TARGET_STRAP_BOOT_2_GPIO} = 0 and {IDF_TARGET_STRAP_BOOT_GPIO} = 0 is invalid and will trigger unexpected behavior. diff --git a/docs/en/advanced-topics/firmware-image-format.rst b/docs/en/advanced-topics/firmware-image-format.rst index 529df3d5f..48cb90669 100644 --- a/docs/en/advanced-topics/firmware-image-format.rst +++ b/docs/en/advanced-topics/firmware-image-format.rst @@ -1,3 +1,12 @@ +{IDF_TARGET_FLASH_FREQ_F:default="80", esp32c2="60", esp32h2="48"} + +{IDF_TARGET_FLASH_FREQ_0:default="40", esp32c2="30", esp32h2="24"} + +{IDF_TARGET_FLASH_FREQ_1:default="26", esp32c2="20", esp32h2="16"} + +{IDF_TARGET_FLASH_FREQ_2:default="20", esp32c2="15", esp32h2="12"} + + .. _image-format: Firmware Image Format @@ -37,29 +46,67 @@ The image header is 8 bytes long: | 4-7 | Entry point address | +--------+--------------------------------------------------------------------------------------------------+ -.. only:: not esp8266 - - +--------+--------------------------------------------------------------------------------------------------+ - | Byte | Description | - +========+==================================================================================================+ - | 0 | Magic number (always ``0xE9``) | - +--------+--------------------------------------------------------------------------------------------------+ - | 1 | Number of segments | - +--------+--------------------------------------------------------------------------------------------------+ - | 2 | SPI Flash Mode (``0`` = QIO, ``1`` = QOUT, ``2`` = DIO, ``3`` = DOUT) | - +--------+--------------------------------------------------------------------------------------------------+ - | 3 | High four bits - Flash size (``0`` = 1MB, ``1`` = 2MB, ``2`` = 4MB, ``3`` = 8MB, ``4`` = 16MB) | - | | | - | | Low four bits - Flash frequency (``0`` = 40MHz, ``1`` = 26MHz, ``2`` = 20MHz, ``0xf`` = 80MHz) | - +--------+--------------------------------------------------------------------------------------------------+ - | 4-7 | Entry point address | - +--------+--------------------------------------------------------------------------------------------------+ - -.. only:: esp32c2 or esp32h2 - .. fail_when_new_target_added:: +.. only:: esp32s2 or esp32s3 + + +--------+------------------------------------------------------------------------------------------------+ + | Byte | Description | + +========+================================================================================================+ + | 0 | Magic number (always ``0xE9``) | + +--------+------------------------------------------------------------------------------------------------+ + | 1 | Number of segments | + +--------+------------------------------------------------------------------------------------------------+ + | 2 | SPI Flash Mode (``0`` = QIO, ``1`` = QOUT, ``2`` = DIO, ``3`` = DOUT) | + +--------+------------------------------------------------------------------------------------------------+ + | 3 | High four bits - Flash size (``0`` = 1MB, ``1`` = 2MB, ``2`` = 4MB, ``3`` = 8MB, ``4`` = 16MB, | + | | ``5`` = 32MB, ``6`` = 64MB, ``7`` = 128MB") | + | | | + | | Low four bits - Flash frequency (``0`` = {IDF_TARGET_FLASH_FREQ_0}MHz, ``1`` = {IDF_TARGET_FLASH_FREQ_1}MHz, ``2`` = {IDF_TARGET_FLASH_FREQ_2}MHz, ``0xf`` = {IDF_TARGET_FLASH_FREQ_F}MHz) | + +--------+------------------------------------------------------------------------------------------------+ + | 4-7 | Entry point address | + +--------+------------------------------------------------------------------------------------------------+ + + +.. only:: esp32c6 + + +--------+------------------------------------------------------------------------------------------------+ + | Byte | Description | + +========+================================================================================================+ + | 0 | Magic number (always ``0xE9``) | + +--------+------------------------------------------------------------------------------------------------+ + | 1 | Number of segments | + +--------+------------------------------------------------------------------------------------------------+ + | 2 | SPI Flash Mode (``0`` = QIO, ``1`` = QOUT, ``2`` = DIO, ``3`` = DOUT) | + +--------+------------------------------------------------------------------------------------------------+ + | 3 | High four bits - Flash size (``0`` = 1MB, ``1`` = 2MB, ``2`` = 4MB, ``3`` = 8MB, ``4`` = 16MB) | + | | | + | | Low four bits - Flash frequency (``0`` = 80MHz, ``0`` = 40MHz, ``2`` = 20MHz) | + +--------+------------------------------------------------------------------------------------------------+ + | 4-7 | Entry point address | + +--------+------------------------------------------------------------------------------------------------+ + + .. note:: + Flash frequency with value ``0`` can mean either 80MHz or 40MHz based on MSPI clock source mode. + + +.. only:: not (esp8266 or esp32c6 or esp32s3 or esp32s2) + + +--------+------------------------------------------------------------------------------------------------+ + | Byte | Description | + +========+================================================================================================+ + | 0 | Magic number (always ``0xE9``) | + +--------+------------------------------------------------------------------------------------------------+ + | 1 | Number of segments | + +--------+------------------------------------------------------------------------------------------------+ + | 2 | SPI Flash Mode (``0`` = QIO, ``1`` = QOUT, ``2`` = DIO, ``3`` = DOUT) | + +--------+------------------------------------------------------------------------------------------------+ + | 3 | High four bits - Flash size (``0`` = 1MB, ``1`` = 2MB, ``2`` = 4MB, ``3`` = 8MB, ``4`` = 16MB) | + | | | + | | Low four bits - Flash frequency (``0`` = {IDF_TARGET_FLASH_FREQ_0}MHz, ``1`` = {IDF_TARGET_FLASH_FREQ_1}MHz, ``2`` = {IDF_TARGET_FLASH_FREQ_2}MHz, ``0xf`` = {IDF_TARGET_FLASH_FREQ_F}MHz) | + +--------+------------------------------------------------------------------------------------------------+ + | 4-7 | Entry point address | + +--------+------------------------------------------------------------------------------------------------+ - TODO: Update flash frequency lists to be esp32c2 or esp32h2 specific ``esptool.py`` overrides the 2nd and 3rd (start from 0) bytes according to the SPI flash info provided through command line option, but only if there is no SHA256 digest appended after the image. Therefore, if you would like to change SPI flash info during flashing, i.e. with the ``esptool.py write_flash`` command, then generate images without SHA256 digests. This can be achieved by running ``esptool.py elf2image`` with the ``--dont-append-digest`` argument. diff --git a/docs/en/esptool/advanced-commands.rst b/docs/en/esptool/advanced-commands.rst index a5dd1562e..5143963a5 100644 --- a/docs/en/esptool/advanced-commands.rst +++ b/docs/en/esptool/advanced-commands.rst @@ -1,4 +1,4 @@ -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp8266="0x0", esp32="0x1000", esp32s2="0x1000", esp32s3="0x0", esp32c3="0x0"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} .. _advanced-commands: diff --git a/docs/en/esptool/advanced-options.rst b/docs/en/esptool/advanced-options.rst index 8d8b8e483..793853c44 100644 --- a/docs/en/esptool/advanced-options.rst +++ b/docs/en/esptool/advanced-options.rst @@ -22,7 +22,7 @@ The ``--before`` argument allows you to specify whether the chip needs resetting * ``--before default_reset`` is the default, which uses DTR & RTS serial control lines (see :ref:`entering-the-bootloader`) to try to reset the chip into bootloader mode. * ``--before no_reset`` will skip DTR/RTS control signal assignments and just start sending a serial synchronisation command to the chip. This is useful if your chip doesn't have DTR/RTS, or for some serial interfaces (like Arduino board onboard serial) which behave differently when DTR/RTS are toggled. * ``--before no_reset_no_sync`` will skip DTR/RTS control signal assignments and skip also the serial synchronization command. This is useful if your chip is already running the :ref:`stub bootloader ` and you want to avoid resetting the chip and uploading the stub again. - :esp32c3 or esp32s3: * ``--before usb_reset`` will use custom reset sequence for USB-JTAG-Serial (used for example for ESP chips connected through the USB-JTAG-Serial peripheral). Usually, this option doesn't have to be used directly. Esptool should be able to detect connection through USB-JTAG-Serial. + :esp32c3 or esp32s3 or esp32c6 or esp32h2: * ``--before usb_reset`` will use custom reset sequence for USB-JTAG-Serial (used for example for ESP chips connected through the USB-JTAG-Serial peripheral). Usually, this option doesn't have to be used directly. Esptool should be able to detect connection through USB-JTAG-Serial. Reset After Operation ^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/esptool/flash-modes.rst b/docs/en/esptool/flash-modes.rst index 675673d8f..37d3033b7 100644 --- a/docs/en/esptool/flash-modes.rst +++ b/docs/en/esptool/flash-modes.rst @@ -1,4 +1,11 @@ -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp8266="0x0", esp32="0x1000", esp32s2="0x1000", esp32s3="0x0", esp32c3="0x0"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} + +{IDF_TARGET_FLASH_FREQ_F:default="80", esp32c2="60", esp32h2="48"} + +{IDF_TARGET_FLASH_FREQ_0:default="40", esp32c2="30", esp32h2="24"} + +{IDF_TARGET_FLASH_FREQ:default="``40m``, ``26m``, ``20m``, ``80m``", esp32c2="``30m``, ``20m``, ``15m``, ``60m``", esp32h2="``24m``, ``16m``, ``12m``, ``48m``", esp32c6="``40m``, ``20m``, ``80m``"} + .. _flash-modes: @@ -36,9 +43,9 @@ For a full explanation of these modes, see the :ref:`SPI Flash Modes page Date: Mon, 5 Jun 2023 13:33:31 +0200 Subject: [PATCH 033/209] fix(compressed upload): Accept short data blocks with only Adler-32 bytes --- esptool/targets/stub_flasher/stub_flasher_32.json | 4 ++-- .../targets/stub_flasher/stub_flasher_32c2.json | 4 ++-- .../targets/stub_flasher/stub_flasher_32c3.json | 4 ++-- .../targets/stub_flasher/stub_flasher_32c6.json | 4 ++-- .../stub_flasher/stub_flasher_32c6beta.json | 4 ++-- .../targets/stub_flasher/stub_flasher_32h2.json | 4 ++-- .../stub_flasher/stub_flasher_32h2beta1.json | 4 ++-- .../stub_flasher/stub_flasher_32h2beta2.json | 4 ++-- .../targets/stub_flasher/stub_flasher_32s2.json | 4 ++-- .../targets/stub_flasher/stub_flasher_32s3.json | 4 ++-- .../stub_flasher/stub_flasher_32s3beta2.json | 4 ++-- .../targets/stub_flasher/stub_flasher_8266.json | 4 ++-- flasher_stub/stub_write_flash.c | 14 +++++++++----- 13 files changed, 33 insertions(+), 29 deletions(-) diff --git a/esptool/targets/stub_flasher/stub_flasher_32.json b/esptool/targets/stub_flasher/stub_flasher_32.json index 3e87d813c..23a283fa9 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32.json +++ b/esptool/targets/stub_flasher/stub_flasher_32.json @@ -1,7 +1,7 @@ { "entry": 1074521560, - "text": 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Gvf+CIS0mKALGmQBGggAM4seyAsYwAJIhJdApwKYiAoYlACGj/OAwlEF9/CojQCKQIhIMADIRMCAxlvIAMCkxFjIFJzwCRiQAhhIAAAyjx7NEkZj8fPgAA0DgYJFgYAQgKDAqJpoiQCKQIpIMG3PWggYrYz0HZ7zdhgYAoiEnfMOgYQQMEmAjg20CHAPGdv4AANIhJF0LYiElZ73eIg0AGz0AHEAAIqEg7iCLzAzi3QPHMgLG2v8GCAAiDQEyzAgAE0AAMqEiDQDSzQIAHEAAIqEgIyAg7iDCzBAhdfzgMJRhT/wqI2AikDISDAAzETAgMZaiADA5MSAghEYJAAAAgWz8DKR89xs0AARA4ECRQEAEICcwKiSKImAikCKSDE0DliL+AANA4OCRMMzAImEoDPMnIxUhOvxyISj6MiFe/Bv/KiNyQgAGNAAAgiEoZrga3H8cCZJhKAYBANIhJF0LHBMhL/x89jliBkH+MVP8KiMiwvAiAgAiYSYnPB0GDgCiISd8w6BhBAwSYCODbQIcI8Y1/gAA0iEkXQtiISVnvd4b3QstIgIAciEmABxAACKhi8wg7iB3POGCISYxQPySISgMFgAYQABmoZozC2Yyw/DgJhBiAwAACEDg4JEqZiE5/IDMwCovDANmuQwxDPz6QzE1/Do0MgMATQZSYTRiYTWyYTYBSfzAAABiITVSITRq/7IhNoYAAAAMD3EB/EInEWInEmpkZ78Chnj/95YHhgIA0iEkXQscU0bJ/wDxIfwhIvw9D1JhNGJhNbJhNnJhMwE1/MAAAHIhMyEL/DInEUInEjo/ATD8wAAAsiE2YiE1UiE0Mer7KMMLIinD8ej7eM/WN7iGPgFiISUM4tA2wKZDDkG2+1A0wKYjAkZNAMYyAseyAoYuAKYjAkYlAEHc++AglEAikCISvAAyETAgMZYSATApMRZSBSc8AsYkAAYTAAAAAAyjx7NEfPiSpLAAA0DgYJFgYAQgKDAqJpoiQCKQIpIMG3PWggYrYz0HZ7zdhgYAciEnfMNwYQQMEmAjg20CHHPG1P0AANIhJF0LgiElh73eIg0AGz0AHEAAIqEg7iCLzAzi3QPHMgKG2/8GCAAAACINAYs8ABNAADKhIg0AK90AHEAAIqEgIyAg7iDCzBBBr/vgIJRAIpAiErwAIhEg8DGWjwAgKTHw8ITGCAAMo3z3YqSwGyMAA0DgMJEwMATw9zD682r/QP+Q8p8MPQKWL/4AAkDg4JEgzMAioP/3ogLGQACGAgAAHIMG0wDSISRdCyFp+ye17/JFAG0PG1VG6wAM4scyGTINASINAIAzESAjIAAcQAAioSDuICvdwswQMYr74CCUqiIwIpAiEgwAIhEgMDEgKTHWEwIMpBskAARA4ECRQEAEMDkwOjRBf/uKM0AzkDKTDE0ClvP9/QMAAkDg4JEgzMB3g3xioA7HNhpCDQEiDQCARBEgJCAAHEAAIqEg7iDSzQLCzBBBcPvgIJSqIkAikEISDABEEUAgMUBJMdYSAgymG0YABkDgYJFgYAQgKTAqJmFl+4oiYCKQIpIMbQSW8v0yRQAABEDg4JFAzMB3AggbVf0CRgIAAAAiRQErVQZz//BghGb2AoazACKu/ypmIYH74GYRaiIoAiJhJiF/+3IhJmpi+AYWhwV3PBzGDQCCISd8w4BhBAwSYCODbQIck4Zb/QDSISRdC5IhJZe93xvdCy0iAgCiISYAHEAAIqGLzCDuIKc84WIhJgwSABZAACKhCyLgIhBgzMAABkDg4JEq/wzix7IChjAAciEl0CfApiICxiUAQTP74CCUQCKQItIPIhIMADIRMCAxlgIBMCkxFkIFJzwChiQAxhIAAAAMo8ezRJFW+3z4AANA4GCRYGAEICgwKiaaIkAikCKSDBtz1oIGK2M9B2e83YYGAIIhJ3zDgGEEDBJgI4NtAhyjxiv9AADSISRdC5IhJZe93iINABs9ABxAACKhIO4gi8wM4t0DxzICBtv/BggAAAAiDQGLPAATQAAyoSINACvdABxAACKhICMgIO4gwswQYQb74CCUYCKQItIPMhIMADMRMCAxloIAMDkxICCExggAgSv7DKR89xs0AARA4ECRQEAEICcwKiSKImAikCKSDE0DliL+AANA4OCRMMzAMSH74CIRKjM4AzJhJjEf+6IhJiojKAIiYSgWCganPB5GDgByISd8w3BhBAwSYCODbQIcs8b3/AAAANIhJF0LgiElh73dG90LLSICAJIhJgAcQAAioYvMIO4glzzhoiEmDBIAGkAAIqFiISgLIuAiECpmAApA4OCRoMzAYmEocen6giEocHXAkiEsMeb6gCfAkCIQOiJyYSk9BSe1AT0CQZ36+jNtDze0bQYSACHH+ixTOWLGbQA8UyHE+n0NOWIMJgZsAF0L0iEkRgAA/QYhkvonteGiISliIShyISxgKsAx0PpwIhAqIyICABuqIkUAomEpG1ULb1Yf/QYMAAAyAgBixv0yRQAyAgEyRQEyAgI7IjJFAjtV9jbjFgYBMgIAMkUAZiYFIgIBIkUBalX9BqKgsHz5gqSwcqEABr3+IaP6KLIH4gIGl/zAICQnPCBGDwCCISd8w4BhBAwSYCODbQIsAwas/AAAXQvSISRGAAD9BpIhJZe92RvdCy0iAgAAHEAAIqGLzCDuIMAgJCc84cAgJAACQODgkXyCIMwQfQ1GAQAAC3fCzPiiISR3ugL2jPEht/oxt/pNDFJhNHJhM7JhNgWVAAsisiE2ciEzUiE0IO4QDA8WLAaGDAAAAIIhJ3zDgGEEDBJgI4NtAiyTBg8AciEkXQuSISWXt+AbdwsnIgIAABxAACKhIO4gi8y2jOTgMHTCzPjg6EEGCgCiISd8w6BhBAwSYCODbQIsoyFm+jliRg8AciEkXQtiISVnt9syBwAbd0Fg+hv/KKSAIhEwIiAppPZPCEbe/wByISRdCyFa+iwjOWIMBoYBAHIhJF0LfPYmFhVLJsxyhgMAAAt3wsz4giEkd7gC9ozxgU/6IX/6MX/6yXhNDFJhNGJhNXJhM4JhMrJhNoWGAIIhMpIhKKIhJgsimeiSISng4hCiaBByITOiISRSITSyITZiITX5+OJoFJJoFaDXwLDFwP0GllYOMWz6+NgtDMV+APDg9E0C8PD1fQwMeGIhNbIhNkYlAAAAkgIAogIC6umSAgHqmZru+v7iAgOampr/mp7iAgSa/5qe4gIFmv+anuICBpr/mp7iAgea/5ru6v+LIjqSRznAQCNBsCKwsJBgRgIAADICABsiOu7q/yo5vQJHM+8xTvotDkJhMWJhNXJhM4JhMrJhNgV2ADFI+u0CLQ+FdQBCITFyITOyITZAd8CCITJBQfpiITX9AoyHLQuwOMDG5v8AAAD/ESEI+urv6dL9BtxW+KLw7sB87+D3g0YCAAAAAAwM3Qzyr/0xNPpSISooI2IhJNAiwNBVwNpm0RD6KSM4DXEP+lJhKspTWQ1wNcAMAgwV8CWDYmEkICB0VoIAQtOAQCWDFpIAwQX6LQzFKQDJDYIhKtHs+Yz4KD0WsgDwLzHwIsDWIgDGhPvWjwAioMcpXQY6AABWTw4oPcwSRlH6IqDIhgAAIqDJKV3GTfooLYwSBkz6Ie75ARv6wAAAAR76wAAAhkf6yD3MHMZF+iKj6AEV+sAAAMAMAAZC+gDiYSIMfEaU+gEV+sAAAAwcDAMGCAAAyC34PfAsICAgtMwSxpv6Ri77Mi0DIi0CRTMAMqAADBwgw4PGKft4fWhtWF1ITTg9KC0MDAH7+cAAAO0CDBLgwpOGJfsAAAH1+cAAAAwMBh/7ACHI+UhdOC1JAiHG+TkCBvr/QcT5DAI4BMKgyDDCgykEQcD5PQwMHCkEMMKDBhP7xzICxvP9xvr9KD0WIvLGF/oCIUOSoRDCIULSIUHiIUDyIT+aEQ3wAAAIAABgHAAAYAAAAGAQAABgIfz/EsHw6QHAIADoAgkxySHZESH4/8AgAMgCwMB0nOzRmvlGBAAAADH0/8AgACgDOA0gIHTAAwALzGYM6ob0/yHv/wgxwCAA6QLIIdgR6AESwRAN8AAAAPgCAGAQAgBgAAIAYAAAAAgh/P/AIAA4AjAwJFZD/yH5/0H6/8AgADkCMff/wCAASQPAIABIA1Z0/8AgACgCDBMgIAQwIjAN8AAAgAAAAABA////AAQCAGASwfDJIcFw+QkxKEzZERaCCEX6/xYiCChMDPMMDSejDCgsMCIQDBMg04PQ0HQQESBF+P8WYv8h3v8x7v/AIAA5AsAgADIiAFZj/zHX/8AgACgDICAkVkL/KCwx5f9AQhEhZfnQMoMh5P8gJBBB5P/AIAApBCHP/8AgADkCwCAAOAJWc/8MEhwD0COT3QIoTNAiwClMKCza0tksCDHIIdgREsEQDfAAAABMSgBAEsHgyWHBRfn5Mfg86UEJcdlR7QL3swH9AxYfBNgc2t/Q3EEGAQAAAIXy/yhMphIEKCwnrfJF7f8Wkv8oHE0PPQ4B7v/AAAAgIHSMMiKgxClcKBxIPPoi8ETAKRxJPAhxyGHYUehB+DESwSAN8AAAAP8PAABRKvkSwfAJMQwUQkUAMExBSSVB+v85FSk1MDC0SiIqIyAsQSlFDAIiZQUBXPnAAAAIMTKgxSAjkxLBEA3wAAAAMDsAQBLB8AkxMqDAN5IRIqDbAfv/wAAAIqDcRgQAAAAAMqDbN5IIAfb/wAAAIqDdAfT/wAAACDESwRAN8AAAABLB8Mkh2REJMc0COtJGAgAAIgwAwswBxfr/15zzAiEDwiEC2BESwRAN8AAAWBAAAHAQAAAYmABAHEsAQDSYAEAAmQBAkfv/EsHgyWHpQfkxCXHZUZARwO0CItEQzQMB9f/AAADx+viGCgDdDMe/Ad0PTQ09AS0OAfD/wAAAICB0/EJNDT0BItEQAez/wAAA0O6A0MzAVhz9IeX/MtEQECKAAef/wAAAIeH/HAMaIgX1/y0MBgEAAAAioGOR3f+aEQhxyGHYUehB+DESwSAN8AASwfAioMAJMQG6/8AAAAgxEsEQDfAAAABsEAAAaBAAAHQQAAB4EAAAfBAAAIAQAACQEAAAmA8AQIw7AEASweCR/P/5Mf0CIcb/yWHZUQlx6UGQEcAaIjkCMfL/LAIaM0kDQfD/0tEQGkTCoABSZADCbRoB8P/AAABh6v8hwPgaZmgGZ7ICxkkALQ0Btv/AAAAhs/8x5f8qQRozSQNGPgAAAGGv/zHf/xpmaAYaM+gDwCbA57ICIOIgYd3/PQEaZlkGTQ7wLyABqP/AAAAx2P8gIHQaM1gDjLIMBEJtFu0ExhIAAAAAQdH/6v8aRFkEBfH/PQ4tAYXj/0Xw/00OPQHQLSABmv/AAABhyf/qzBpmWAYhk/8aIigCJ7y8McL/UCzAGjM4AzeyAkbd/0bq/0KgAEJNbCG5/xAigAG//8AAAFYC/2G5/yINbBBmgDgGRQcA9+IR9k4OQbH/GkTqNCJDABvuxvH/Mq/+N5LBJk4pIXv/0D0gECKAAX7/wAAABej/IXb/HAMaIkXa/0Xn/ywCAav4wAAAhgUAYXH/Ui0aGmZoBme1yFc8AgbZ/8bv/wCRoP+aEQhxyGHYUehB+DESwSAN8F0CQqDAKANHlQ7MMgwShgYADAIpA3ziDfAmEgUmIhHGCwBCoNstBUeVKQwiKQMGCAAioNwnlQgMEikDLQQN8ABCoN188keVCwwSKQMioNsN8AB88g3wAAC2IzBtAlD2QEDzQEe1KVBEwAAUQAAzoQwCNzYEMGbAGyLwIhEwMUELRFbE/jc2ARsiDfAAjJMN8Dc2DAwSDfAAAAAAAERJVjAMAg3wtiMoUPJAQPNAR7UXUETAABRAADOhNzICMCLAMDFBQsT/VgT/NzICMCLADfDMUwAAAERJVjAMAg3wAAAAABRA5sQJIDOBACKhDfAAAAAyoQwCDfAA", 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6ciKksCp3IYb8IHeQklcMQiEsG5kbREJhLHIhLpcXAsa9/4IhLSYoAsaYAEaBAAzix7ICxi8AkiEl0CnApiICBiUAIZv84DCUQXX8KiNAIpAiEgwAMhEwIDGW8gAwKTEWEgUnPAJGIwAGEgAADKPHs0KRkPx8+AADQOBgkWBgBCAoMCommiJAIpAikgwbc9ZCBitjPQdnvN0GBgCiISd8w6BhBAwSYCODbQIcA8Z1/tIhJF0LYiElZ73gIg0AGz0AHEAAIqEg7iCLzAzi3QPHMgJG2/+GBwAiDQGLPAATQAAyoSINACvdABxAACKhICMgIO4gwswQIW784DCUYUj8KiNgIpAyEgwAMxEwIDGWogAwOTEgIIRGCQAAAIFl/AykfPcbNAAEQOBAkUBABCAnMCokiiJgIpAikgxNA5Yi/gADQODgkTDMwCJhKAzzJyMVITP8ciEo+jIhV/wb/yojckIABjQAAIIhKGa4Gtx/HAmSYSgGAQDSISRdCxwTISj8fPY5YgZB/jFM/CojIsLwIgIAImEmJzwdBg4AoiEnfMOgYQQMEmAjg20CHCPGNf4AANIhJF0LYiElZ73eG90LLSICAHIhJgAcQAAioYvMIO4gdzzhgiEmMTn8kiEoDBYAGEAAZqGaMwtmMsPw4CYQYgMAAAhA4OCRKmYhMvyAzMAqLwwDZrkMMQX8+kMxLvw6NDIDAE0GUmE0YmE1smE2AUH8wAAAYiE1UiE0av+yITaGAAAADA9x+vtCJxFiJxJqZGe/AoZ5//eWB4YCANIhJF0LHFNGyf8A8Rr8IRv8PQ9SYTRiYTWyYTZyYTMBLfzAAAByITMhBPwyJxFCJxI6PwEo/MAAALIhNmIhNVIhNDHj+yjDCyIpw/Hh+3jP1me4hj4BYiElDOLQNsCmQw9Br/tQNMCmIwJGTQDGMQIAx7ICRi4ApiMCBiUAQdX74CCUQCKQIhK8ADIRMCAxlgIBMCkxFkIFJzwChiQAxhIAAAAMo8ezRHz4kqSwAANA4GCRYGAEICgwKiaaIkAikCKSDBtz1oIGK2M9B2e83YYGAHIhJ3zDcGEEDBJgI4NtAhxzxtT9AADSISRdC4IhJYe93iINABs9ABxAACKhIO4gi8wM4t0DxzICxtv/BggAAAAiDQGLPAATQAAyoSINACvdABxAACKhICMgIO4gwswQQaj74CCUQCKQIhK8ACIRIPAxlo8AICkx8PCExggADKN892KksBsjAANA4DCRMDAE8Pcw+vNq/0D/kPKfDD0Cli/+AAJA4OCRIMzAIqD/96ICxkAAhgIAAByDBtMA0iEkXQshYvsnte/yRQBtDxtVRusADOLHMhkyDQEiDQCAMxEgIyAAHEAAIqEg7iAr3cLMEDGD++AglKoiMCKQIhIMACIRIDAxICkx1hMCDKQbJAAEQOBAkUBABDA5MDo0QXj7ijNAM5AykwxNApbz/f0DAAJA4OCRIMzAd4N8YqAOxzYaQg0BIg0AgEQRICQgABxAACKhIO4g0s0CwswQQWn74CCUqiJAIpBCEgwARBFAIDFASTHWEgIMphtGAAZA4GCRYGAEICkwKiZhXvuKImAikCKSDG0ElvL9MkUAAARA4OCRQMzAdwIIG1X9AkYCAAAAIkUBK1UGc//wYIRm9gKGswAirv8qZiF6++BmEWoiKAIiYSYhePtyISZqYvgGFpcFdzwdBg4AAACCISd8w4BhBAwSYCODbQIckwZb/dIhJF0LkiEll73gG90LLSICAKIhJgAcQAAioYvMIO4gpzzhYiEmDBIAFkAAIqELIuAiEGDMwAAGQODgkSr/DOLHsgJGMAByISXQJ8CmIgKGJQBBLPvgIJRAIpAi0g8iEgwAMhEwIDGW8gAwKTEWMgUnPAJGJACGEgAADKPHs0SRT/t8+AADQOBgkWBgBCAoMCommiJAIpAikgwbc9aCBitjPQdnvN2GBgCCISd8w4BhBAwSYCODbQIco8Yr/QAA0iEkXQuSISWXvd4iDQAbPQAcQAAioSDuIIvMDOLdA8cyAkbb/wYIAAAAIg0BizwAE0AAMqEiDQAr3QAcQAAioSAjICDuIMLMEGH/+uAglGAikCLSDzISDAAzETAgMZaCADA5MSAghMYIAIEk+wykfPcbNAAEQOBAkUBABCAnMCokiiJgIpAikgxNA5Yi/gADQODgkTDMwDEa++AiESozOAMyYSYxGPuiISYqIygCImEoFgoGpzweRg4AciEnfMNwYQQMEmAjg20CHLPG9/wAAADSISRdC4IhJYe93RvdCy0iAgCSISYAHEAAIqGLzCDuIJc84aIhJgwSABpAACKhYiEoCyLgIhAqZgAKQODgkaDMwGJhKHHi+oIhKHB1wJIhKzHf+oAnwJAiEDoicmEqPQUntQE9AkGW+vozbQ83tG0GEgAhwPosUzliBm4APFMhvfp9DTliDCZGbABdC9IhJEYAAP0GIYv6J7XhoiEqYiEociErYCrAMcn6cCIQKiMiAgAbqiJFAKJhKhtVC29WH/0GDAAAMgIAYsb9MkUAMgIBMkUBMgICOyIyRQI7VfY24xYGATICADJFAGYmBSICASJFAWpV/QaioLB8+YKksHKhAAa9/iGc+iiyB+IChpb8wCAkJzwgRg8AgiEnfMOAYQQMEmAjg20CLAMGrPwAAF0L0iEkRgAA/QaSISWXvdkb3QstIgIAABxAACKhi8wg7iDAICQnPOHAICQAAkDg4JF8giDMEH0NRgEAAAt3wsz4oiEkd7oC9ozxIbD6MbD6TQxSYTRyYTOyYTZFlAALIrIhNnIhM1IhNCDuEAwPFkwGhgwAAACCISd8w4BhBAwSYCODbQIskwYPAHIhJF0LkiEll7fgG3cLJyICAAAcQAAioSDuIIvMtozk4DB0wsz44OhBhgoAoiEnfMOgYQQMEmAjg20CLKMhX/o5YoYPAAAAciEkXQtiISVnt9kyBwAbd0FZ+hv/KKSAIhEwIiAppPZPB8bd/3IhJF0LIVL6LCM5YgwGhgEAciEkXQt89iYWFEsmzGJGAwALd8LM+IIhJHe4AvaM8YFI+iF4+jF4+sl4TQxSYTRiYTVyYTOCYTKyYTbFhQCCITKSISiiISYLIpnokiEq4OIQomgQciEzoiEkUiE0siE2YiE1+fjiaBSSaBWg18CwxcD9BpZWDjFl+vjYLQwFfgDw4PRNAvDw9X0MDHhiITWyITZGJQAAAJICAKICAurpkgIB6pma7vr+4gIDmpqa/5qe4gIEmv+anuICBZr/mp7iAgaa/5qe4gIHmv+a7ur/iyI6kkc5wEAjQbAisLCQYEYCAAAyAgAbIjru6v8qOb0CRzPvMUf6LQ5CYTFiYTVyYTOCYTKyYTZFdQAxQfrtAi0PxXQAQiExciEzsiE2QHfAgiEyQTr6YiE1/QKMhy0LsDjAxub/AAAA/xEhAfrq7+nS/QbcVvii8O7AfO/g94NGAgAAAAAMDN0M8q/9MS36UiEpKCNiISTQIsDQVcDaZtEJ+ikjOA1xCPpSYSnKU1kNcDXADAIMFfAlg2JhJCAgdFaCAELTgEAlgxaSAMH++S0MBSkAyQ2CISmcKJHl+Sg5FrIA8C8x8CLA1iIAxoP7MqDHId/5li8BjB9GS/oh3PkyIgPME4ZI+jKgyDlShkb6KC2MEsZE+iHo+QEU+sAAAAEW+sAAAEZA+sg9zByGPvoio+gBDvrAAADADADGOvriYSIMfEaN+gEO+sAAAAwcDAMGCAAAyC34PfAsICAgtMwSxpT6Rif7Mi0DIi0CxTIAMqAADBwgw4PGIvt4fWhtWF1ITTg9KC0MDAH0+cAAAO0CDBLgwpOGHvsAAAHu+cAAAAwMBhj7ACHC+UhdOC1JAiHA+TkCBvr/Qb75DAI4BMKgyDDCgykEQbr5PQwMHCkEMMKDBgz7xzICxvT9xvv9AiFDkqEQwiFC0iFB4iFA8iE/mhEN8AAACAAAYBwAAGAAAABgEAAAYCH8/xLB8OkBwCAA6AIJMckh2REh+P/AIADIAsDAdJzs0Zb5RgQAAAAx9P/AIAAoAzgNICB0wAMAC8xmDOqG9P8h7/8IMcAgAOkCyCHYEegBEsEQDfAAAAD4AgBgEAIAYAACAGAAAAAIIfz/wCAAOAIwMCRWQ/8h+f9B+v/AIAA5AjH3/8AgAEkDwCAASANWdP/AIAAoAgwTICAEMCIwDfAAAIAAAAAAQP///wAEAgBgEsHwySHBbPkJMShM2REWgghF+v8WIggoTAzzDA0nowwoLDAiEAwTINOD0NB0EBEgRfj/FmL/Id7/Me7/wCAAOQLAIAAyIgBWY/8x1//AIAAoAyAgJFZC/ygsMeX/QEIRIWH50DKDIeT/ICQQQeT/wCAAKQQhz//AIAA5AsAgADgCVnP/DBIcA9Ajk90CKEzQIsApTCgs2tLZLAgxyCHYERLBEA3wAAAATEoAQBLB4MlhwUH5+TH4POlBCXHZUe0C97MB/QMWHwTYHNrf0NxBBgEAAACF8v8oTKYSBCgsJ63yRe3/FpL/KBxNDz0OAe7/wAAAICB0jDIioMQpXCgcSDz6IvBEwCkcSTwIcchh2FHoQfgxEsEgDfAAAAD/DwAAUSb5EsHwCTEMFEJFADBMQUklQfr/ORUpNTAwtEoiKiMgLEEpRQwCImUFAVf5wAAACDEyoMUgI5MSwRAN8AAAADA7AEASwfAJMTKgwDeSESKg2wH7/8AAACKg3EYEAAAAADKg2zeSCAH2/8AAACKg3QH0/8AAAAgxEsEQDfAAAAASwfDJIdkRCTHNAjrSRgIAACIMAMLMAcX6/9ec8wIhA8IhAtgREsEQDfAAAFgQAABwEAAAGJgAQBxLAEA0mABAAJkAQJH7/xLB4Mlh6UH5MQlx2VGQEcDtAiLREM0DAfX/wAAA8fb4hgoA3QzHvwHdD00NPQEtDgHw/8AAACAgdPxCTQ09ASLREAHs/8AAANDugNDMwFYc/SHl/zLREBA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"data_start": 1073720488 } \ No newline at end of file diff --git a/flasher_stub/stub_write_flash.c b/flasher_stub/stub_write_flash.c index b166976d8..e94d0b56c 100644 --- a/flasher_stub/stub_write_flash.c +++ b/flasher_stub/stub_write_flash.c @@ -273,7 +273,7 @@ static void start_next_erase(void) esp_rom_opiflash_wren(); esp_rom_opiflash_exec_cmd(1, SPI_FLASH_SLOWRD_MODE, - CMD_LARGE_BLOCK_ERASE, 8, + CMD_LARGE_BLOCK_ERASE, 8, fs.next_erase_sector * FLASH_SECTOR_SIZE, 24, 0, NULL, 0, @@ -291,7 +291,7 @@ static void start_next_erase(void) esp_rom_opiflash_wren(); esp_rom_opiflash_exec_cmd(1, SPI_FLASH_SLOWRD_MODE, - CMD_SECTOR_ERASE, 8, + CMD_SECTOR_ERASE, 8, fs.next_erase_sector * FLASH_SECTOR_SIZE, 24, 0, NULL, 0, @@ -423,6 +423,13 @@ void handle_flash_encrypt_data(void *data_buf, uint32_t length) { #endif // !ESP8266 void handle_flash_deflated_data(void *data_buf, uint32_t length) { + /* if all data has been uploaded and another block comes, + accept it only if it is part of a 4-byte Adler-32 checksum */ + if (fs.remaining == 0 && length > 4) { + fs.last_error = ESP_TOO_MUCH_DATA; + return; + } + static uint8_t out_buf[32768]; static uint8_t *next_out = out_buf; int status = TINFL_STATUS_NEEDS_MORE_INPUT; @@ -464,9 +471,6 @@ void handle_flash_deflated_data(void *data_buf, uint32_t length) { if (status == TINFL_STATUS_DONE && fs.remaining > 0) { fs.last_error = ESP_NOT_ENOUGH_DATA; } - if (status != TINFL_STATUS_DONE && fs.remaining == 0) { - fs.last_error = ESP_TOO_MUCH_DATA; - } } esp_command_error handle_flash_end(void) From f517a1982ba2556fdd3b90d7f475203c862c2af4 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 6 Jun 2023 16:04:05 +0200 Subject: [PATCH 034/209] fix(CH9102F): Suggest to install new serial drivers if writing to RAM fails --- esptool/__init__.py | 11 ++++++++++- esptool/loader.py | 9 +++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index ae5d7816c..3c99b9784 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -713,7 +713,16 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): ) args.no_stub = True else: - esp = esp.run_stub() + try: + esp = esp.run_stub() + except Exception: + # The CH9102 bridge (PID: 0x55D4) can have issues on MacOS + if sys.platform == "darwin" and esp._get_pid() == 0x55D4: + print( + "\nNote: If issues persist, " + "try installing the WCH USB-to-Serial MacOS driver." + ) + raise if args.override_vddsdio: esp.override_vddsdio(args.override_vddsdio) diff --git a/esptool/loader.py b/esptool/loader.py index 834b26636..88f1b77d4 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -295,6 +295,7 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): "flash_id": None, "chip_id": None, "uart_no": None, + "usb_pid": None, } if isinstance(port, str): @@ -475,6 +476,9 @@ def sync(self): self.sync_stub_detected &= val == 0 def _get_pid(self): + if self.cache["usb_pid"] is not None: + return self.cache["usb_pid"] + if list_ports is None: print( "\nListing all serial ports is currently not available. " @@ -502,10 +506,11 @@ def _get_pid(self): ports = list_ports.comports() for p in ports: if p.device in active_ports: + self.cache["usb_pid"] = p.pid return p.pid print( - "\nFailed to get PID of a device on {}, " - "using standard reset sequence.".format(active_port) + f"\nFailed to get PID of a device on {active_port}, " + "using standard reset sequence." ) def _connect_attempt(self, reset_strategy, mode="default_reset"): From d8ce9446a33be25cef6f201e6d712e1d4b32352b Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Wed, 7 Jun 2023 14:54:31 +0800 Subject: [PATCH 035/209] esptool & espefuse: Fix byte order in MAC (for C6 and H2) MAC: 60:55:f9:ff:fe:f7:2c:a2 (EUI64, used for IEEE802154) BASE MAC: 60:55:f9:f7:2c:a2 (used for BT) MAC_EXT: ff:fe --- docs/en/espefuse/inc/summary_ESP32-H2.rst | 4 +-- espefuse/efuse/base_fields.py | 9 ++++-- espefuse/efuse/esp32c6/fields.py | 33 ++++++++++++++------- espefuse/efuse/esp32c6/mem_definition.py | 11 +++++++ espefuse/efuse/esp32c6/operations.py | 3 +- espefuse/efuse/esp32h2/fields.py | 35 +++++++++++++--------- espefuse/efuse/esp32h2/mem_definition.py | 17 ++++++++++- espefuse/efuse/esp32h2/operations.py | 3 +- espefuse/efuse/esp32h2beta1/fields.py | 36 ++++++++++++++--------- espefuse/efuse/esp32h2beta1/operations.py | 3 +- esptool/cmds.py | 10 +++++-- esptool/targets/esp32.py | 4 ++- esptool/targets/esp32c3.py | 5 +++- esptool/targets/esp32c6.py | 23 ++++++++++----- esptool/targets/esp32h2.py | 2 +- esptool/targets/esp32h2beta1.py | 5 +++- esptool/targets/esp32s2.py | 5 +++- esptool/targets/esp32s3.py | 5 +++- esptool/targets/esp8266.py | 4 ++- test/test_espefuse.py | 21 +++---------- 20 files changed, 153 insertions(+), 85 deletions(-) diff --git a/docs/en/espefuse/inc/summary_ESP32-H2.rst b/docs/en/espefuse/inc/summary_ESP32-H2.rst index 920ace3f3..0032586bd 100644 --- a/docs/en/espefuse/inc/summary_ESP32-H2.rst +++ b/docs/en/espefuse/inc/summary_ESP32-H2.rst @@ -62,10 +62,10 @@ Mac fuses: MAC (BLOCK1) MAC address - = 60:55:f9:f7:2c:05:ff:fe (OK) R/W + = 60:55:f9:f7:2c:05 (OK) R/W MAC_EXT (BLOCK1) Stores the extended bits of MAC address = ff:fe (OK) R/W CUSTOM_MAC (BLOCK3) Custom MAC - = 00:00:00:00:00:00:ff:fe (OK) R/W + = 00:00:00:00:00:00 (OK) R/W Security fuses: DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index fe244efc3..ab12f0312 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -577,6 +577,9 @@ def __init__(self, parent, param): self.bitarray.set(0) self.update(self.parent.blocks[self.block].bitarray) + def is_field_calculated(self): + return self.word is None or self.pos is None + def check_format(self, new_value_str): if new_value_str is None: return new_value_str @@ -669,8 +672,10 @@ def save(self, new_value): self.save_to_block(bitarray_field) def update(self, bit_array_block): - if self.word is None or self.pos is None: - self.bitarray.overwrite(self.convert_to_bitstring(self.get()), pos=0) + if self.is_field_calculated(): + self.bitarray.overwrite( + self.convert_to_bitstring(self.check_format(self.get())), pos=0 + ) return field_len = self.bitarray.len bit_array_block.pos = bit_array_block.length - ( diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index 2d09c9fd3..3f67ec06d 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -326,23 +326,27 @@ def check_format(self, new_value_str): raise esptool.FatalError( "Required MAC Address in AA:CD:EF:01:02:03 format!" ) - if new_value_str.count(":") != 5: + num_bytes = 8 if self.name == "MAC_EUI64" else 6 + if new_value_str.count(":") != num_bytes - 1: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal format " + f"MAC Address needs to be a {num_bytes}-byte hexadecimal format " "separated by colons (:)!" ) - hexad = new_value_str.replace(":", "") - if len(hexad) != 12: + hexad = new_value_str.replace(":", "").split(" ", 1)[0] + hexad = hexad.split(" ", 1)[0] if self.is_field_calculated() else hexad + if len(hexad) != num_bytes * 2: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal number " - "(12 hexadecimal characters)!" + f"MAC Address needs to be a {num_bytes}-byte hexadecimal number " + f"({num_bytes * 2} hexadecimal characters)!" ) # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', bindata = binascii.unhexlify(hexad) - # unicast address check according to - # https://tools.ietf.org/html/rfc7042#section-2.1 - if esptool.util.byte(bindata, 0) & 0x01: - raise esptool.FatalError("Custom MAC must be a unicast MAC!") + + if not self.is_field_calculated(): + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") return bindata def check(self): @@ -356,6 +360,13 @@ def check(self): def get(self, from_read=True): if self.name == "CUSTOM_MAC": mac = self.get_raw(from_read)[::-1] + elif self.name == "MAC": + mac = self.get_raw(from_read) + elif self.name == "MAC_EUI64": + mac = self.parent["MAC"].get_bitstring(from_read).copy() + mac_ext = self.parent["MAC_EXT"].get_bitstring(from_read) + mac.insert(mac_ext, 24) + mac = mac.bytes else: mac = self.get_raw(from_read) return "%s %s" % (util.hexify(mac, ":"), self.check()) @@ -375,7 +386,7 @@ def print_field(e, new_value): else: # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, # as it's written in the factory. - raise esptool.FatalError("Writing Factory MAC address is not supported") + raise esptool.FatalError(f"Burning {self.name} is not supported") # fmt: off diff --git a/espefuse/efuse/esp32c6/mem_definition.py b/espefuse/efuse/esp32c6/mem_definition.py index 60e4b6cde..25e4caf01 100644 --- a/espefuse/efuse/esp32c6/mem_definition.py +++ b/espefuse/efuse/esp32c6/mem_definition.py @@ -12,6 +12,7 @@ EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase, + Field, ) @@ -151,6 +152,16 @@ def __init__(self) -> None: self.BLOCK2_CALIBRATION_EFUSES.append(efuse) self.ALL_EFUSES[i] = None + f = Field() + f.name = "MAC_EUI64" + f.block = 1 + f.bit_len = 64 + f.type = f"bytes:{f.bit_len // 8}" + f.category = "MAC" + f.class_type = "mac" + f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" + self.CALC.append(f) + for efuse in self.ALL_EFUSES: if efuse is not None: self.EFUSES.append(efuse) diff --git a/espefuse/efuse/esp32c6/operations.py b/espefuse/efuse/esp32c6/operations.py index f37991cca..f8e450fa0 100644 --- a/espefuse/efuse/esp32c6/operations.py +++ b/espefuse/efuse/esp32c6/operations.py @@ -167,8 +167,7 @@ def add_commands(subparsers, efuses): p.add_argument( "mac", help="Custom MAC Address to burn given in hexadecimal format with bytes " - "separated by colons (e.g. AA:CD:EF:01:02:03). " - "Final CUSTOM_MAC = CUSTOM_MAC[48] + MAC_EXT[16]", + "separated by colons (e.g. AA:CD:EF:01:02:03).", type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), ) add_force_write_always(p) diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index 5be835253..7f7d4cee4 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -327,23 +327,27 @@ def check_format(self, new_value_str): raise esptool.FatalError( "Required MAC Address in AA:CD:EF:01:02:03 format!" ) - if new_value_str.count(":") != 5: + num_bytes = 8 if self.name == "MAC_EUI64" else 6 + if new_value_str.count(":") != num_bytes - 1: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal format " + f"MAC Address needs to be a {num_bytes}-byte hexadecimal format " "separated by colons (:)!" ) hexad = new_value_str.replace(":", "") - if len(hexad) != 12: + hexad = hexad.split(" ", 1)[0] if self.is_field_calculated() else hexad + if len(hexad) != num_bytes * 2: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal number " - "(12 hexadecimal characters)!" + f"MAC Address needs to be a {num_bytes}-byte hexadecimal number " + f"({num_bytes * 2} hexadecimal characters)!" ) # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', bindata = binascii.unhexlify(hexad) - # unicast address check according to - # https://tools.ietf.org/html/rfc7042#section-2.1 - if esptool.util.byte(bindata, 0) & 0x01: - raise esptool.FatalError("Custom MAC must be a unicast MAC!") + + if not self.is_field_calculated(): + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") return bindata def check(self): @@ -356,11 +360,14 @@ def check(self): def get(self, from_read=True): if self.name == "CUSTOM_MAC": - mac = self.get_raw(from_read)[::-1] + self.parent["MAC_EXT"].get_raw( - from_read - ) + mac = self.get_raw(from_read)[::-1] elif self.name == "MAC": - mac = self.get_raw(from_read) + self.parent["MAC_EXT"].get_raw(from_read) + mac = self.get_raw(from_read) + elif self.name == "MAC_EUI64": + mac = self.parent["MAC"].get_bitstring(from_read).copy() + mac_ext = self.parent["MAC_EXT"].get_bitstring(from_read) + mac.insert(mac_ext, 24) + mac = mac.bytes else: mac = self.get_raw(from_read) return "%s %s" % (util.hexify(mac, ":"), self.check()) @@ -380,7 +387,7 @@ def print_field(e, new_value): else: # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, # as it's written in the factory. - raise esptool.FatalError("Writing Factory MAC address is not supported") + raise esptool.FatalError(f"Burning {self.name} is not supported") # fmt: off diff --git a/espefuse/efuse/esp32h2/mem_definition.py b/espefuse/efuse/esp32h2/mem_definition.py index d548794f6..edf07f112 100644 --- a/espefuse/efuse/esp32h2/mem_definition.py +++ b/espefuse/efuse/esp32h2/mem_definition.py @@ -8,7 +8,12 @@ import yaml -from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) class EfuseDefineRegisters(EfuseRegistersBase): @@ -147,6 +152,16 @@ def __init__(self) -> None: self.BLOCK2_CALIBRATION_EFUSES.append(efuse) self.ALL_EFUSES[i] = None + f = Field() + f.name = "MAC_EUI64" + f.block = 1 + f.bit_len = 64 + f.type = f"bytes:{f.bit_len // 8}" + f.category = "MAC" + f.class_type = "mac" + f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" + self.CALC.append(f) + for efuse in self.ALL_EFUSES: if efuse is not None: self.EFUSES.append(efuse) diff --git a/espefuse/efuse/esp32h2/operations.py b/espefuse/efuse/esp32h2/operations.py index 3ce3c896e..20a76da96 100644 --- a/espefuse/efuse/esp32h2/operations.py +++ b/espefuse/efuse/esp32h2/operations.py @@ -166,8 +166,7 @@ def add_commands(subparsers, efuses): p.add_argument( "mac", help="Custom MAC Address to burn given in hexadecimal format with bytes " - "separated by colons (e.g. AA:CD:EF:01:02:03). " - "Final CUSTOM_MAC = CUSTOM_MAC[48] + MAC_EXT[16]", + "separated by colons (e.g. AA:CD:EF:01:02:03).", type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), ) add_force_write_always(p) diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index ec2e8a217..bef76f4e2 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -326,23 +326,27 @@ def check_format(self, new_value_str): raise esptool.FatalError( "Required MAC Address in AA:CD:EF:01:02:03 format!" ) - if new_value_str.count(":") != 5: + num_bytes = 8 if self.name == "MAC_EUI64" else 6 + if new_value_str.count(":") != num_bytes - 1: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal format " + f"MAC Address needs to be a {num_bytes}-byte hexadecimal format " "separated by colons (:)!" ) - hexad = new_value_str.replace(":", "") - if len(hexad) != 12: + hexad = new_value_str.replace(":", "").split(" ", 1)[0] + hexad = hexad.split(" ", 1)[0] if self.is_field_calculated() else hexad + if len(hexad) != num_bytes * 2: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal number " - "(12 hexadecimal characters)!" + f"MAC Address needs to be a {num_bytes}-byte hexadecimal number " + f"({num_bytes * 2} hexadecimal characters)!" ) # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', bindata = binascii.unhexlify(hexad) - # unicast address check according to - # https://tools.ietf.org/html/rfc7042#section-2.1 - if esptool.util.byte(bindata, 0) & 0x01: - raise esptool.FatalError("Custom MAC must be a unicast MAC!") + + if not self.is_field_calculated(): + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") return bindata def check(self): @@ -355,11 +359,14 @@ def check(self): def get(self, from_read=True): if self.name == "CUSTOM_MAC": - mac = self.get_raw(from_read)[::-1] + self.parent["MAC_EXT"].get_raw( - from_read - ) + mac = self.get_raw(from_read)[::-1] elif self.name == "MAC": - mac = self.get_raw(from_read) + self.parent["MAC_EXT"].get_raw(from_read) + mac = self.get_raw(from_read) + elif self.name == "MAC_EUI64": + mac = self.parent["MAC"].get_bitstring(from_read).copy() + mac_ext = self.parent["MAC_EXT"].get_bitstring(from_read) + mac.insert(mac_ext, 24) + mac = mac.bytes else: mac = self.get_raw(from_read) return "%s %s" % (util.hexify(mac, ":"), self.check()) @@ -379,6 +386,7 @@ def print_field(e, new_value): else: # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, # as it's written in the factory. + raise esptool.FatalError(f"Burning {self.name} is not supported") raise esptool.FatalError("Writing Factory MAC address is not supported") diff --git a/espefuse/efuse/esp32h2beta1/operations.py b/espefuse/efuse/esp32h2beta1/operations.py index 35cbb94c3..9f602544a 100644 --- a/espefuse/efuse/esp32h2beta1/operations.py +++ b/espefuse/efuse/esp32h2beta1/operations.py @@ -166,8 +166,7 @@ def add_commands(subparsers, efuses): p.add_argument( "mac", help="Custom MAC Address to burn given in hexadecimal format with bytes " - "separated by colons (e.g. AA:CD:EF:01:02:03). " - "Final CUSTOM_MAC = CUSTOM_MAC[48] + MAC_EXT[16]", + "separated by colons (e.g. AA:CD:EF:01:02:03).", type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), ) add_force_write_always(p) diff --git a/esptool/cmds.py b/esptool/cmds.py index ed9cdb3a3..02442f9de 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -1029,12 +1029,16 @@ def elf2image(args): def read_mac(esp, args): - mac = esp.read_mac() - def print_mac(label, mac): print("%s: %s" % (label, ":".join(map(lambda x: "%02x" % x, mac)))) - print_mac("MAC", mac) + eui64 = esp.read_mac("EUI64") + if eui64: + print_mac("MAC", eui64) + print_mac("BASE MAC", esp.read_mac("BASE_MAC")) + print_mac("MAC_EXT", esp.read_mac("MAC_EXT")) + else: + print_mac("MAC", esp.read_mac("BASE_MAC")) def chip_id(esp, args): diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index b805ed453..45aac2e95 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -283,8 +283,10 @@ def read_efuse(self, n): def chip_id(self): raise NotSupportedError(self, "chip_id") - def read_mac(self): + def read_mac(self, mac_type="BASE_MAC"): """Read MAC from EFUSE region""" + if mac_type != "BASE_MAC": + return None words = [self.read_efuse(2), self.read_efuse(1)] bitstring = struct.pack(">II", *words) bitstring = bitstring[2:8] # trim the 2 byte CRC diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index 3b3c30153..f7d6540d3 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -134,7 +134,10 @@ def override_vddsdio(self, new_voltage): "VDD_SDIO overrides are not supported for ESP32-C3" ) - def read_mac(self): + def read_mac(self, mac_type="BASE_MAC"): + """Read MAC from EFUSE region""" + if mac_type != "BASE_MAC": + return None mac0 = self.read_reg(self.MAC_EFUSE_REG) mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC bitstring = struct.pack(">II", mac1, mac0)[2:] diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index a2d736c51..fd39c6e09 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -134,15 +134,22 @@ def override_vddsdio(self, new_voltage): "VDD_SDIO overrides are not supported for ESP32-C6" ) - def read_mac(self): + def read_mac(self, mac_type="BASE_MAC"): + """Read MAC from EFUSE region""" mac0 = self.read_reg(self.MAC_EFUSE_REG) - mac_reg1 = self.read_reg(self.MAC_EFUSE_REG + 4) - mac1 = mac_reg1 & 0xFFFF - mac_ext = (mac_reg1 >> 16) & 0xFFFF - bitstring = struct.pack(">HIH", mac1, mac0, mac_ext) - # MAC: 60:55:f9:f7:2c:a2:ff:fe - # | mac1| mac0 | mac_ext| - return tuple(bitstring) + mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC + base_mac = struct.pack(">II", mac1, mac0)[2:] + ext_mac = struct.pack(">H", (mac1 >> 16) & 0xFFFF) + eui64 = base_mac[0:3] + ext_mac + base_mac[3:6] + # BASE MAC: 60:55:f9:f7:2c:a2 + # EUI64 MAC: 60:55:f9:ff:fe:f7:2c:a2 + # EXT_MAC: ff:fe + macs = { + "BASE_MAC": tuple(base_mac), + "EUI64": tuple(eui64), + "MAC_EXT": tuple(ext_mac), + } + return macs.get(mac_type, None) def get_flash_crypt_config(self): return None # doesn't exist on ESP32-C6 diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py index 73fe60c33..88a0bba18 100644 --- a/esptool/targets/esp32h2.py +++ b/esptool/targets/esp32h2.py @@ -50,7 +50,7 @@ def get_chip_description(self): return f"{chip_name} (revision v{major_rev}.{minor_rev})" def get_chip_features(self): - return ["BLE"] + return ["BLE", "IEEE802.15.4"] def get_crystal_freq(self): # ESP32H2 XTAL is fixed to 32MHz diff --git a/esptool/targets/esp32h2beta1.py b/esptool/targets/esp32h2beta1.py index 2720f1586..49e38e44a 100644 --- a/esptool/targets/esp32h2beta1.py +++ b/esptool/targets/esp32h2beta1.py @@ -106,7 +106,10 @@ def override_vddsdio(self, new_voltage): "VDD_SDIO overrides are not supported for ESP32-H2" ) - def read_mac(self): + def read_mac(self, mac_type="BASE_MAC"): + """Read MAC from EFUSE region""" + if mac_type != "BASE_MAC": + return None mac0 = self.read_reg(self.MAC_EFUSE_REG) mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC bitstring = struct.pack(">II", mac1, mac0)[2:] diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py index bffd55331..92b611812 100644 --- a/esptool/targets/esp32s2.py +++ b/esptool/targets/esp32s2.py @@ -182,7 +182,10 @@ def override_vddsdio(self, new_voltage): "VDD_SDIO overrides are not supported for ESP32-S2" ) - def read_mac(self): + def read_mac(self, mac_type="BASE_MAC"): + """Read MAC from EFUSE region""" + if mac_type != "BASE_MAC": + return None mac0 = self.read_reg(self.MAC_EFUSE_REG) mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC bitstring = struct.pack(">II", mac1, mac0)[2:] diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index ef611dc8b..8a29add2d 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -213,7 +213,10 @@ def override_vddsdio(self, new_voltage): "VDD_SDIO overrides are not supported for ESP32-S3" ) - def read_mac(self): + def read_mac(self, mac_type="BASE_MAC"): + """Read MAC from EFUSE region""" + if mac_type != "BASE_MAC": + return None mac0 = self.read_reg(self.MAC_EFUSE_REG) mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC bitstring = struct.pack(">II", mac1, mac0)[2:] diff --git a/esptool/targets/esp8266.py b/esptool/targets/esp8266.py index f9966634d..9027eb86e 100644 --- a/esptool/targets/esp8266.py +++ b/esptool/targets/esp8266.py @@ -131,8 +131,10 @@ def chip_id(self): id1 = self.read_reg(self.ESP_OTP_MAC1) return (id0 >> 24) | ((id1 & 0xFFFFFF) << 8) - def read_mac(self): + def read_mac(self, mac_type="BASE_MAC"): """Read MAC from OTP ROM""" + if mac_type != "BASE_MAC": + return None mac0 = self.read_reg(self.ESP_OTP_MAC0) mac1 = self.read_reg(self.ESP_OTP_MAC1) mac3 = self.read_reg(self.ESP_OTP_MAC3) diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 68cbc34ee..6f8176323 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -184,8 +184,6 @@ def test_get_custom_mac(self): self.espefuse_py("get_custom_mac -h") if arg_chip == "esp32": right_msg = "Custom MAC Address is not set in the device." - elif arg_chip in ["esp32h2", "esp32h2beta1"]: - right_msg = "Custom MAC Address: 00:00:00:00:00:00:00:00 (OK)" else: right_msg = "Custom MAC Address: 00:00:00:00:00:00 (OK)" self.espefuse_py("get_custom_mac", check_msg=right_msg) @@ -386,19 +384,13 @@ class TestBurnCustomMacCommands(EfuseTestCase): def test_burn_custom_mac(self): self.espefuse_py("burn_custom_mac -h") cmd = "burn_custom_mac AA:CD:EF:11:22:33" + mac = "aa:cd:ef:11:22:33" if arg_chip == "esp32": self.espefuse_py( - cmd, - check_msg="Custom MAC Address version 1: " - "aa:cd:ef:11:22:33 (CRC 0x63 OK)", + cmd, check_msg=f"Custom MAC Address version 1: {mac} (CRC 0x63 OK)" ) else: - mac_custom = ( - "aa:cd:ef:11:22:33:00:00" - if arg_chip in ["esp32h2", "esp32h2beta1"] - else "aa:cd:ef:11:22:33" - ) - self.espefuse_py(cmd, check_msg=f"Custom MAC Address: {mac_custom} (OK)") + self.espefuse_py(cmd, check_msg=f"Custom MAC Address: {mac} (OK)") def test_burn_custom_mac2(self): self.espefuse_py( @@ -645,12 +637,7 @@ def test_burn_mac_custom_efuse(self): ret_code=2, ) self.espefuse_py("burn_efuse CUSTOM_MAC AA:CD:EF:01:02:03") - if arg_chip in ["esp32h2", "esp32h2beta1"]: - self.espefuse_py( - "get_custom_mac", check_msg=f"aa:cd:ef:01:02:03:00:00 {crc_msg}" - ) - else: - self.espefuse_py("get_custom_mac", check_msg=f"aa:cd:ef:01:02:03 {crc_msg}") + self.espefuse_py("get_custom_mac", check_msg=f"aa:cd:ef:01:02:03 {crc_msg}") def test_burn_efuse(self): self.espefuse_py("burn_efuse -h") From c63057777139023a4f99ebb026cf4cea0514c524 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 12 Jun 2023 14:16:14 +0200 Subject: [PATCH 036/209] Update version to v4.6.2 --- esptool/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 3c99b9784..ec7cb1782 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.7-dev" +__version__ = "4.6.2" import argparse import inspect From b03a219316c71a602eca4cb35d14496ad653b0e6 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 12 Jun 2023 14:16:54 +0200 Subject: [PATCH 037/209] Update version to v4.7 --- esptool/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index ec7cb1782..3c99b9784 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.6.2" +__version__ = "4.7-dev" import argparse import inspect From b9de209d8150df33c9762b5e07026ac4f257453d Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 28 Jun 2023 11:35:10 +0200 Subject: [PATCH 038/209] change: Add conventional precommit linter --- .pre-commit-config.yaml | 6 ++++++ CONTRIBUTING.rst | 11 ++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index edf3b57c9..5b15d12fd 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -7,3 +7,9 @@ repos: rev: 22.3.0 hooks: - id: black + - repo: https://github.com/espressif/conventional-precommit-linter + rev: v1.1.0 + hooks: + - id: conventional-precommit-linter + stages: [commit-msg] +default_install_hook_types: [pre-commit, commit-msg] diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index a46742c63..6b9d5536e 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -78,15 +78,20 @@ Pre-commit checks `pre-commit `_ is a framework for managing pre-commit hooks. These hooks help to identify simple issues before committing code for review. -To use the tool, first install ``pre-commit`` and then the git hooks: +To use the tool, first install ``pre-commit``. Then enable the ``pre-commit`` and ``commit-msg`` git hooks: :: $ python -m pip install pre-commit - $ pre-commit install + $ pre-commit install -t pre-commit -t commit-msg On the first commit ``pre-commit`` will install the hooks, subsequent checks will be significantly faster. If an error is found an appropriate error message will be displayed. If the error was with ``black`` then the tool will fix them for you automatically. Review the changes and re-stage for commit if you are happy with them. +Conventional Commits +"""""""""""""""""""" + +``esptool.py`` complies with the `Conventional Commits standard `_. Every commit message is checked with `Conventional Precommit Linter `_, ensuring it adheres to the standard. + Flake8 """""" @@ -97,7 +102,7 @@ Black All files should be formatted using the `Black `_ auto-formatter. -``Black`` and ``flake8`` tools will be automatically run by ``pre-commit`` if that is configured. To check your code manually before submitting, run ``python -m flake8`` and ``black .`` (the tools are installed as part of the development requirements shown at the beginning of this document). +``Black``, ``flake8``, and ``Conventional Precommit Linter`` tools will be automatically run by ``pre-commit`` if that is configured. To check your code manually before submitting, run ``python -m flake8`` and ``black .`` (the tools are installed as part of the development requirements shown at the beginning of this document). When you submit a Pull Request, the GitHub Actions automated build system will run automated checks using these tools. From 486e02f8206cf6f40dee5520f9da85923f86b644 Mon Sep 17 00:00:00 2001 From: Tomas Sebestik Date: Fri, 30 Jun 2023 09:08:55 +0200 Subject: [PATCH 039/209] ci(pre-commit): Update version of `conventional-precommit-linter` --- .pre-commit-config.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 5b15d12fd..a005434de 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -8,7 +8,7 @@ repos: hooks: - id: black - repo: https://github.com/espressif/conventional-precommit-linter - rev: v1.1.0 + rev: v1.2.0 hooks: - id: conventional-precommit-linter stages: [commit-msg] From 5cbcc6c95072d777ebf187a5bc8180d7db82355d Mon Sep 17 00:00:00 2001 From: Aditya Patwardhan Date: Fri, 23 Jun 2023 08:56:32 +0530 Subject: [PATCH 040/209] feat(get_security_info): Improved the output format and added more details --- esptool/cmds.py | 90 +++++++++++++++++++++++++++++++++++++++++--- test/test_esptool.py | 10 +++-- 2 files changed, 91 insertions(+), 9 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 02442f9de..156a27fb4 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -1180,15 +1180,95 @@ def write_flash_status(esp, args): print(("After flash status: " + fmt) % esp.read_status(args.bytes)) +# The following mapping was taken from the ROM code +# This mapping is same across all targets in the ROM +SECURITY_INFO_FLAG_MAP = { + "SECURE_BOOT_EN": (1 << 0), + "SECURE_BOOT_AGGRESSIVE_REVOKE": (1 << 1), + "SECURE_DOWNLOAD_ENABLE": (1 << 2), + "SECURE_BOOT_KEY_REVOKE0": (1 << 3), + "SECURE_BOOT_KEY_REVOKE1": (1 << 4), + "SECURE_BOOT_KEY_REVOKE2": (1 << 5), + "SOFT_DIS_JTAG": (1 << 6), + "HARD_DIS_JTAG": (1 << 7), + "DIS_USB": (1 << 8), + "DIS_DOWNLOAD_DCACHE": (1 << 9), + "DIS_DOWNLOAD_ICACHE": (1 << 10), +} + + +# Get the status of respective security flag +def get_security_flag_status(flag_name, flags_value): + try: + return (flags_value & SECURITY_INFO_FLAG_MAP[flag_name]) != 0 + except KeyError: + raise ValueError(f"Invalid flag name: {flag_name}") + + def get_security_info(esp, args): si = esp.get_security_info() - # TODO: better display + print() + title = "Security Information:" + print(title) + print("=" * len(title)) print("Flags: {:#010x} ({})".format(si["flags"], bin(si["flags"]))) - print("Flash_Crypt_Cnt: {:#x}".format(si["flash_crypt_cnt"])) - print("Key_Purposes: {}".format(si["key_purposes"])) + print("Key Purposes: {}".format(si["key_purposes"])) if si["chip_id"] is not None and si["api_version"] is not None: - print("Chip_ID: {}".format(si["chip_id"])) - print("Api_Version: {}".format(si["api_version"])) + print("Chip ID: {}".format(si["chip_id"])) + print("API Version: {}".format(si["api_version"])) + + flags = si["flags"] + + if get_security_flag_status("SECURE_BOOT_EN", flags): + print("Secure Boot: Enabled") + if get_security_flag_status("SECURE_BOOT_AGGRESSIVE_REVOKE", flags): + print("Secure Boot Aggressive key revocation: Enabled") + + revoked_keys = [] + for i, key in enumerate( + [ + "SECURE_BOOT_KEY_REVOKE0", + "SECURE_BOOT_KEY_REVOKE1", + "SECURE_BOOT_KEY_REVOKE2", + ] + ): + if get_security_flag_status(key, flags): + revoked_keys.append(i) + + if len(revoked_keys) > 0: + print("Secure Boot Key Revocation Status:\n") + for i in revoked_keys: + print(f"\tSecure Boot Key{i} is Revoked\n") + + else: + print("Secure Boot: Disabled") + + flash_crypt_cnt = bin(si["flash_crypt_cnt"]) + if (flash_crypt_cnt.count("1") % 2) != 0: + print("Flash Encryption: Enabled") + else: + print("Flash Encryption: Disabled") + + CRYPT_CNT_STRING = "SPI Boot Crypt Count (SPI_BOOT_CRYPT_CNT)" + if esp.CHIP_NAME == "esp32": + CRYPT_CNT_STRING = "Flash Crypt Count (FLASH_CRYPT_CNT)" + + print(f"{CRYPT_CNT_STRING}: {si['flash_crypt_cnt']:#x}") + + if get_security_flag_status("DIS_DOWNLOAD_DCACHE", flags): + print("Dcache in UART download mode: Disabled") + + if get_security_flag_status("DIS_DOWNLOAD_ICACHE", flags): + print("Icache in UART download mode: Disabled") + + hard_dis_jtag = get_security_flag_status("HARD_DIS_JTAG", flags) + soft_dis_jtag = get_security_flag_status("SOFT_DIS_JTAG", flags) + if hard_dis_jtag: + print("JTAG: Permenantly Disabled") + elif soft_dis_jtag: + print("JTAG: Software Access Disabled") + if get_security_flag_status("DIS_USB", flags): + print("USB Access: Disabled") def merge_bin(args): diff --git a/test/test_esptool.py b/test/test_esptool.py index 0d5c108ba..d29fdb6e5 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -616,14 +616,16 @@ class TestSecurityInfo(EsptoolTestCase): def test_show_security_info(self): res = self.run_esptool("get_security_info") assert "Flags" in res - assert "Flash_Crypt_Cnt" in res - assert "Key_Purposes" in res + assert "Crypt Count" in res + assert "Key Purposes" in res if arg_chip != "esp32s2": esp = esptool.get_default_connected_device( [arg_port], arg_port, 10, 115200, arg_chip ) - assert f"Chip_ID: {esp.IMAGE_CHIP_ID}" in res - assert "Api_Version" in res + assert f"Chip ID: {esp.IMAGE_CHIP_ID}" in res + assert "API Version" in res + assert "Secure Boot" in res + assert "Flash Encryption" in res class TestFlashSizes(EsptoolTestCase): From 99076bc9837656aff543ae025840b78864ca6e6c Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 17 Jul 2023 16:55:08 +0200 Subject: [PATCH 041/209] fix(esp32-c2): Enable flashing in secure download mode Closes https://github.com/espressif/esptool/issues/895 --- esptool/cmds.py | 2 +- esptool/targets/esp32c2.py | 2 +- esptool/util.py | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 156a27fb4..9f27b3835 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -466,7 +466,7 @@ def write_flash(esp, args): flash_end = flash_size_bytes( detect_flash_size(esp) if args.flash_size == "keep" else args.flash_size ) - if flash_end is not None: # Secure download mode + if flash_end is not None: # Not in secure download mode for address, argfile in args.addr_filename: argfile.seek(0, os.SEEK_END) if address + argfile.tell() > flash_end: diff --git a/esptool/targets/esp32c2.py b/esptool/targets/esp32c2.py index f70d4a826..f28ee24f4 100644 --- a/esptool/targets/esp32c2.py +++ b/esptool/targets/esp32c2.py @@ -110,7 +110,7 @@ def change_baud(self, baud): def _post_connect(self): # ESP32C2 ECO0 is no longer supported by the flasher stub - if self.get_chip_revision() == 0: + if not self.secure_download_mode and self.get_chip_revision() == 0: self.stub_is_disabled = True self.IS_STUB = False diff --git a/esptool/util.py b/esptool/util.py index e390e1045..91e4ee16b 100644 --- a/esptool/util.py +++ b/esptool/util.py @@ -34,6 +34,8 @@ def flash_size_bytes(size): """Given a flash size of the type passed in args.flash_size (ie 512KB or 1MB) then return the size in bytes. """ + if size is None: + return None if "MB" in size: return int(size[: size.index("MB")]) * 1024 * 1024 elif "KB" in size: From 7971aa97ce58ddb6223cd4596bc931a65254607e Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 18 Jul 2023 16:02:28 +0200 Subject: [PATCH 042/209] ci: Add DangerJS checks to GL and GH --- .github/pull_request_template.md | 19 ++++++++++++------- .github/workflows/dangerjs.yml | 19 +++++++++++++++++++ .gitlab-ci.yml | 13 +++++++++++++ 3 files changed, 44 insertions(+), 7 deletions(-) create mode 100644 .github/workflows/dangerjs.yml diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index 7685f2935..34be8e5f4 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -1,15 +1,20 @@ -(Please delete any lines which don't apply) - -# Description of change + # This change fixes the following bug(s): + # I have tested this change with the following hardware & software combinations: + -(Operating system(s), development board name(s), ESP8266 and/or ESP32.) +# I have run the esptool.py automated integration tests with this change and the above hardware: + diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml new file mode 100644 index 000000000..5a1c9fc19 --- /dev/null +++ b/.github/workflows/dangerjs.yml @@ -0,0 +1,19 @@ +name: DangerJS Check +on: + pull_request: + types: [opened, edited, reopened, synchronize] + +permissions: + pull-requests: write + statuses: write + +jobs: + pull-request-style-linter: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + + - name: DangerJS pull request linter + uses: espressif/github-actions/danger_pr_review@master + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index faaaad309..f020d75c7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,20 @@ # Gitlab CI config # # Note: When updating, please also update test_esptool.yml GH Actions workflow file +include: + - project: 'espressif/shared-ci-dangerjs' + ref: master + file: 'danger.yaml' + +workflow: + rules: + - if: '$CI_PIPELINE_SOURCE == "merge_request_event"' + - if: '$CI_COMMIT_BRANCH && $CI_OPEN_MERGE_REQUESTS && $CI_PIPELINE_SOURCE == "push"' + when: never + - if: '$CI_COMMIT_BRANCH' + stages: + - danger - test - report - build_docs From 694b9362373414a126fa487dba40de5e30dbd2e6 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 6 Jul 2023 14:47:08 +0800 Subject: [PATCH 043/209] feat(esptool): Add PICO package for ESP32S3 and flash/psram efuses --- espefuse/efuse_defs/esp32s3.yaml | 11 ++++++-- esptool/targets/esp32s3.py | 47 ++++++++++++++++++++++++++++++-- esptool/targets/esp32s3beta2.py | 5 ---- 3 files changed, 53 insertions(+), 10 deletions(-) diff --git a/espefuse/efuse_defs/esp32s3.yaml b/espefuse/efuse_defs/esp32s3.yaml index 6f8b0913c..4d4c69511 100644 --- a/espefuse/efuse_defs/esp32s3.yaml +++ b/espefuse/efuse_defs/esp32s3.yaml @@ -1,4 +1,4 @@ -VER_NO: 6925129eca795b8b087d31be539740ec +VER_NO: f75f74727101326a187188a23f4a6c70 EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} @@ -84,8 +84,13 @@ EFUSES: WAFER_VERSION_MINOR_LO : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR least significant bits, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} PKG_VERSION : {show: y, blk : 1, word: 3, pos: 21, len : 3, start: 117, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:21]', bloc: 'B14[7:5]'} BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} - RESERVED_1_123 : {show: n, blk : 1, word: 3, pos: 27, len : 5, start: 123, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:27]', bloc: 'B15[7:3]'} - RESERVED_1_128 : {show: n, blk : 1, word: 4, pos : 0, len : 13, start: 128, type : 'uint:13', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[12:0]', bloc: 'B16,B17[4:0]'} + FLASH_CAP : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "8M", 2: "4M"}', desc: Flash capacity, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'} + FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "105C", 2: "85C"}', desc: Flash temperature, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'} + FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "XMC", 2: "GD", 3: "FM", 4: "TT", 5: "BY"}', desc: Flash vendor, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} + PSRAM_CAP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "8M", 2: "2M"}', desc: PSRAM capacity, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'} + PSRAM_TEMP : {show: y, blk : 1, word: 4, pos : 5, len : 2, start: 133, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "105C", 2: "85C"}', desc: PSRAM temperature, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[6:5]', bloc: 'B16[6:5]'} + PSRAM_VENDOR : {show: y, blk : 1, word: 4, pos : 7, len : 2, start: 135, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "AP_3v3", 2: "AP_1v8"}', desc: PSRAM vendor, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[8:7]', bloc: 'B16[7],B17[0]'} + RESERVED_1_137 : {show: n, blk : 1, word: 4, pos : 9, len : 4, start: 137, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[12:9]', bloc: 'B17[4:1]'} K_RTC_LDO : {show: y, blk : 1, word: 4, pos: 13, len : 7, start: 141, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_RTC_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[19:13]', bloc: 'B17[7:5],B18[3:0]'} K_DIG_LDO : {show: y, blk : 1, word: 4, pos: 20, len : 7, start: 148, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_DIG_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[26:20]', bloc: 'B18[7:4],B19[2:0]'} V_RTC_DBIAS20 : {show: y, blk : 1, word: 4, pos: 27, len : 8, start: 155, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of rtc dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:27]', bloc: 'B19[7:3],B20[2:0]'} diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 8a29add2d..72aa88fb1 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -165,10 +165,53 @@ def get_raw_major_chip_version(self): def get_chip_description(self): major_rev = self.get_major_chip_version() minor_rev = self.get_minor_chip_version() - return f"{self.CHIP_NAME} (revision v{major_rev}.{minor_rev})" + pkg_version = self.get_pkg_version() + + chip_name = { + 0: "ESP32-S3 (QFN56)", + 1: "ESP32-S3-PICO-1 (LGA56)", + }.get(pkg_version, "unknown ESP32-S3") + + return f"{chip_name} (revision v{major_rev}.{minor_rev})" + + def get_flash_cap(self): + num_word = 3 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 27) & 0x07 + + def get_flash_vendor(self): + num_word = 4 + vendor_id = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07 + return {1: "XMC", 2: "GD", 3: "FM", 4: "TT", 5: "BY"}.get(vendor_id, "") + + def get_psram_cap(self): + num_word = 4 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 3) & 0x03 + + def get_psram_vendor(self): + num_word = 4 + vendor_id = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 7) & 0x03 + return {1: "AP_3v3", 2: "AP_1v8"}.get(vendor_id, "") def get_chip_features(self): - return ["WiFi", "BLE"] + features = ["WiFi", "BLE"] + + flash = { + 0: None, + 1: "Embedded Flash 8MB", + 2: "Embedded Flash 4MB", + }.get(self.get_flash_cap(), "Unknown Embedded Flash") + if flash is not None: + features += [flash + f" ({self.get_flash_vendor()})"] + + psram = { + 0: None, + 1: "Embedded PSRAM 8MB", + 2: "Embedded PSRAM 2MB", + }.get(self.get_psram_cap(), "Unknown Embedded PSRAM") + if psram is not None: + features += [psram + f" ({self.get_psram_vendor()})"] + + return features def get_crystal_freq(self): # ESP32S3 XTAL is fixed to 40MHz diff --git a/esptool/targets/esp32s3beta2.py b/esptool/targets/esp32s3beta2.py index b7958bd53..f91bb3cb2 100644 --- a/esptool/targets/esp32s3beta2.py +++ b/esptool/targets/esp32s3beta2.py @@ -14,11 +14,6 @@ class ESP32S3BETA2ROM(ESP32S3ROM): EFUSE_BASE = 0x6001A000 # BLOCK0 read base address - def get_chip_description(self): - major_rev = self.get_major_chip_version() - minor_rev = self.get_minor_chip_version() - return f"{self.CHIP_NAME} (revision v{major_rev}.{minor_rev})" - class ESP32S3BETA2StubLoader(ESP32S3BETA2ROM): """Access class for ESP32S3 stub loader, runs on top of ROM. From 3f86e1e950f050bf04877a346ad0ae36c22796f1 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Wed, 19 Jul 2023 19:49:32 +0800 Subject: [PATCH 044/209] feat(esptool): Add tests for get_chip_features --- esptool/targets/esp32s2.py | 12 +++++++++--- test/test_esptool.py | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py index 92b611812..2f321afd5 100644 --- a/esptool/targets/esp32s2.py +++ b/esptool/targets/esp32s2.py @@ -120,10 +120,16 @@ def get_flash_version(self): num_word = 3 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x0F + def get_flash_cap(self): + return self.get_flash_version() + def get_psram_version(self): num_word = 3 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 28) & 0x0F + def get_psram_cap(self): + return self.get_psram_version() + def get_block2_version(self): # BLK_VERSION_MINOR num_word = 4 @@ -137,7 +143,7 @@ def get_chip_description(self): 102: "ESP32-S2FNR2", 100: "ESP32-S2R2", }.get( - self.get_flash_version() + self.get_psram_version() * 100, + self.get_flash_cap() + self.get_psram_cap() * 100, "unknown ESP32-S2", ) major_rev = self.get_major_chip_version() @@ -154,14 +160,14 @@ def get_chip_features(self): 0: "No Embedded Flash", 1: "Embedded Flash 2MB", 2: "Embedded Flash 4MB", - }.get(self.get_flash_version(), "Unknown Embedded Flash") + }.get(self.get_flash_cap(), "Unknown Embedded Flash") features += [flash_version] psram_version = { 0: "No Embedded PSRAM", 1: "Embedded PSRAM 2MB", 2: "Embedded PSRAM 4MB", - }.get(self.get_psram_version(), "Unknown Embedded PSRAM") + }.get(self.get_psram_cap(), "Unknown Embedded PSRAM") features += [psram_version] block2_version = { diff --git a/test/test_esptool.py b/test/test_esptool.py index d29fdb6e5..d6bb8e531 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -24,6 +24,7 @@ import time from socket import AF_INET, SOCK_STREAM, socket from time import sleep +from unittest.mock import MagicMock # Link command line options --port, --chip, --baud, --with-trace, and --preload-port from conftest import ( @@ -1138,6 +1139,23 @@ def test_read_chip_description(self): finally: esp._port.close() + def test_read_get_chip_features(self): + try: + esp = esptool.get_default_connected_device( + [arg_port], arg_port, 10, 115200, arg_chip + ) + + if hasattr(esp, "get_flash_cap") and esp.get_flash_cap() == 0: + esp.get_flash_cap = MagicMock(return_value=1) + if hasattr(esp, "get_psram_cap") and esp.get_psram_cap() == 0: + esp.get_psram_cap = MagicMock(return_value=1) + + features = ", ".join(esp.get_chip_features()) + assert "Unknown Embedded Flash" not in features + assert "Unknown Embedded PSRAM" not in features + finally: + esp._port.close() + @pytest.mark.skipif( arg_chip != "esp8266", reason="Make image option is supported only on ESP8266" From 1a1ea3717e21fd45698ebcb79b77ecde373f8dc1 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Mon, 10 Jul 2023 22:24:00 +0800 Subject: [PATCH 045/209] feat(esptool): Add new packages for ESP32C3 and flash efuses --- espefuse/efuse_defs/esp32c3.yaml | 8 +++++--- esptool/targets/esp32c3.py | 27 +++++++++++++++++++++++++-- 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/espefuse/efuse_defs/esp32c3.yaml b/espefuse/efuse_defs/esp32c3.yaml index 57872999a..035f30c5b 100644 --- a/espefuse/efuse_defs/esp32c3.yaml +++ b/espefuse/efuse_defs/esp32c3.yaml @@ -1,4 +1,4 @@ -VER_NO: a85f874ae2b6538ca48b7c3db4a79531 +VER_NO: 4622cf9245401eca0eb1df8122449a6d EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} @@ -71,8 +71,10 @@ EFUSES: WAFER_VERSION_MINOR_LO : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR least significant bits, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} PKG_VERSION : {show: y, blk : 1, word: 3, pos: 21, len : 3, start: 117, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:21]', bloc: 'B14[7:5]'} BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} - RESERVED_1_123 : {show: n, blk : 1, word: 3, pos: 27, len : 5, start: 123, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:27]', bloc: 'B15[7:3]'} - RESERVED_1_128 : {show: n, blk : 1, word: 4, pos : 0, len : 7, start: 128, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[6:0]', bloc: 'B16[6:0]'} + FLASH_CAP : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "4M", 2: "2M", 3: "1M", 4: "8M"}', desc: Flash capacity, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'} + FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "105C", 2: "85C"}', desc: Flash temperature, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'} + FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "XMC", 2: "GD", 3: "FM", 4: "TT", 5: "ZBIT"}', desc: Flash vendor, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} + RESERVED_1_131 : {show: n, blk : 1, word: 4, pos : 3, len : 4, start: 131, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[6:3]', bloc: 'B16[6:3]'} K_RTC_LDO : {show: y, blk : 1, word: 4, pos : 7, len : 7, start: 135, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_RTC_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[13:7]', bloc: 'B16[7],B17[5:0]'} K_DIG_LDO : {show: y, blk : 1, word: 4, pos: 14, len : 7, start: 142, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 K_DIG_LDO, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[20:14]', bloc: 'B17[7:6],B18[4:0]'} V_RTC_DBIAS20 : {show: y, blk : 1, word: 4, pos: 21, len : 8, start: 149, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of rtc dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[28:21]', bloc: 'B18[7:5],B19[4:0]'} diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index f7d6540d3..bff0d5447 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -114,16 +114,39 @@ def get_major_chip_version(self): num_word = 5 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x03 + def get_flash_cap(self): + num_word = 3 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 27) & 0x07 + + def get_flash_vendor(self): + num_word = 4 + vendor_id = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07 + return {1: "XMC", 2: "GD", 3: "FM", 4: "TT", 5: "ZBIT"}.get(vendor_id, "") + def get_chip_description(self): chip_name = { - 0: "ESP32-C3", + 0: "ESP32-C3 (QFN32)", + 1: "ESP8685 (QFN28)", + 2: "ESP32-C3 AZ (QFN32)", + 3: "ESP8686 (QFN24)", }.get(self.get_pkg_version(), "unknown ESP32-C3") major_rev = self.get_major_chip_version() minor_rev = self.get_minor_chip_version() return f"{chip_name} (revision v{major_rev}.{minor_rev})" def get_chip_features(self): - return ["WiFi", "BLE"] + features = ["WiFi", "BLE"] + + flash = { + 0: None, + 1: "Embedded Flash 4MB", + 2: "Embedded Flash 2MB", + 3: "Embedded Flash 1MB", + 4: "Embedded Flash 8MB", + }.get(self.get_flash_cap(), "Unknown Embedded Flash") + if flash is not None: + features += [flash + f" ({self.get_flash_vendor()})"] + return features def get_crystal_freq(self): # ESP32C3 XTAL is fixed to 40MHz From 2d1c8688012c08a4f930ffc0a15b4c3dc6b07489 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 24 Jul 2023 14:08:58 +0200 Subject: [PATCH 046/209] fix(expand file args): Correctly print the expanded command --- esptool/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 3c99b9784..0e8569497 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -934,7 +934,7 @@ def expand_file_arguments(argv): else: new_args.append(arg) if expanded: - print("esptool %s" % (" ".join(new_args[1:]))) + print(f"esptool.py {' '.join(new_args)}") return new_args return argv From 7fc22ca4536aae411c885e793882793d3dbd20ff Mon Sep 17 00:00:00 2001 From: Richard Retanubun Date: Wed, 12 Jul 2023 13:46:50 -0400 Subject: [PATCH 047/209] feat(espsecure): Allow prompting for HSM PIN in read_hsm_config If hsm_config does not contain "credentials" the user will be prompted for the HSM PIN. This avoids the need to have HSM PINs typed in config files which is not a good security practice. ADJUNCT: Updated documentation to reflect new usage Closes https://github.com/espressif/esptool/pull/900 --- docs/en/espsecure/index.rst | 3 +++ espsecure/esp_hsm_sign/__init__.py | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/docs/en/espsecure/index.rst b/docs/en/espsecure/index.rst index c4b26766c..c03b3478e 100644 --- a/docs/en/espsecure/index.rst +++ b/docs/en/espsecure/index.rst @@ -50,6 +50,9 @@ HSM config file An HSM config file is required with the fields (``pkcs11_lib``, ``credentials``, ``slot``, ``label``, ``label_pubkey``) populated corresponding to the HSM used. +To access an HSM token of a selected slot, you will also need to pass in the token User PIN and thus you will be prompted to type in the User PIN. +Alternatively, you could also add a ``credentials`` field in the HSM config file to store the (plaintext) User PIN to automate the signing workflow. + Below is a sample HSM config file (``hsm_config.ini``) for using `SoftHSMv2 `_ as an external HSM: :: # hsm_config.ini diff --git a/espsecure/esp_hsm_sign/__init__.py b/espsecure/esp_hsm_sign/__init__.py index baf88241a..d255116ad 100644 --- a/espsecure/esp_hsm_sign/__init__.py +++ b/espsecure/esp_hsm_sign/__init__.py @@ -6,6 +6,7 @@ import configparser import os import sys +from getpass import getpass try: import pkcs11 @@ -31,11 +32,17 @@ def read_hsm_config(configfile): if not config.has_section(section): raise configparser.NoSectionError(section) - section_options = ["pkcs11_lib", "credentials", "slot", "label"] + section_options = ["pkcs11_lib", "slot", "label"] for option in section_options: if not config.has_option(section, option): raise configparser.NoOptionError(option, section) + # If the config file does not contain the "credentials" option, + # prompt the user for the HSM PIN + if not config.has_option(section, "credentials"): + hsm_pin = getpass("Please enter the PIN of your HSM:\n") + config.set(section, "credentials", hsm_pin) + return config[section] From 6dd85474dfbb22d7ace7e664a89744073d4cf3dd Mon Sep 17 00:00:00 2001 From: Tomas Sebestik Date: Tue, 25 Jul 2023 08:46:13 +0200 Subject: [PATCH 048/209] fix(dangerGH): Update token permissions - allow Danger to add comments to PR --- .github/workflows/dangerjs.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml index 5a1c9fc19..ea1c08b8d 100644 --- a/.github/workflows/dangerjs.yml +++ b/.github/workflows/dangerjs.yml @@ -5,7 +5,7 @@ on: permissions: pull-requests: write - statuses: write + contents: write jobs: pull-request-style-linter: From a99ccfa54ff573b4592ca5024568d906dbac4789 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 26 Jul 2023 16:57:59 +0800 Subject: [PATCH 049/209] fix(elf2image): fix text/rodata mapping overlap issue on uni-idrom bus chips --- esptool/bin_image.py | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 24a08e456..08a7ddbf3 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -248,6 +248,20 @@ def save_segment(self, f, segment, checksum=None): if checksum is not None: return ESPLoader.checksum(segment_data, checksum) + def save_flash_segment(self, f, segment, checksum=None): + """ + Save the next segment to the image file, return next checksum value if provided + """ + if self.ROM_LOADER.CHIP_NAME == "ESP32": + # Work around a bug in ESP-IDF 2nd stage bootloader, that it didn't map the + # last MMU page, if an IROM/DROM segment was < 0x24 bytes + # over the page boundary. + segment_end_pos = f.tell() + len(segment.data) + self.SEG_HEADER_LEN + segment_len_remainder = segment_end_pos % self.IROM_ALIGN + if segment_len_remainder < 0x24: + segment.data += b"\x00" * (0x24 - segment_len_remainder) + return self.save_segment(f, segment, checksum) + def read_checksum(self, f): """Return ESPLoader checksum from end of just-read image""" # Skip the padding. The checksum is stored in the last byte so that the @@ -771,19 +785,6 @@ def get_alignment_data_needed(segment): with open(filename, "wb") as real_file: real_file.write(f.getvalue()) - def save_flash_segment(self, f, segment, checksum=None): - """ - Save the next segment to the image file, return next checksum value if provided - """ - segment_end_pos = f.tell() + len(segment.data) + self.SEG_HEADER_LEN - segment_len_remainder = segment_end_pos % self.IROM_ALIGN - if segment_len_remainder < 0x24: - # Work around a bug in ESP-IDF 2nd stage bootloader, that it didn't map the - # last MMU page, if an IROM/DROM segment was < 0x24 bytes - # over the page boundary. - segment.data += b"\x00" * (0x24 - segment_len_remainder) - return self.save_segment(f, segment, checksum) - def load_extended_header(self, load_file): def split_byte(n): return (n & 0x0F, (n >> 4) & 0x0F) From 5ad6e7505c4ec683a6a0021e684ac925add6b67d Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Tue, 25 Jul 2023 21:10:59 +0800 Subject: [PATCH 050/209] fix: assert in esp32 exclusive workaround --- esptool/targets/esp32.py | 1 + 1 file changed, 1 insertion(+) diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index 45aac2e95..0ccceabff 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -361,6 +361,7 @@ def get_rom_cal_crystal_freq(self): return rom_calculated_freq def change_baud(self, baud): + assert self.CHIP_NAME == "ESP32", "This workaround should only apply to ESP32" # It's a workaround to avoid esp32 CK_8M frequency drift. rom_calculated_freq = self.get_rom_cal_crystal_freq() valid_freq = 40000000 if rom_calculated_freq > 33000000 else 26000000 From beb07968d121317c31fa1e3c9b61d90b35ae398d Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 26 Jul 2023 15:34:39 +0200 Subject: [PATCH 051/209] docs: Add other resources page --- docs/en/contributing.rst | 2 ++ docs/en/index.rst | 1 + docs/en/resources.rst | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 docs/en/resources.rst diff --git a/docs/en/contributing.rst b/docs/en/contributing.rst index ac7b6bcf3..c7fcb94cf 100644 --- a/docs/en/contributing.rst +++ b/docs/en/contributing.rst @@ -1 +1,3 @@ +.. _contribute: + .. include:: ../../CONTRIBUTING.rst diff --git a/docs/en/index.rst b/docs/en/index.rst index a367fab53..201b71bf1 100644 --- a/docs/en/index.rst +++ b/docs/en/index.rst @@ -51,4 +51,5 @@ More Information Troubleshooting Contribute Versions + Resources About diff --git a/docs/en/resources.rst b/docs/en/resources.rst new file mode 100644 index 000000000..13add7041 --- /dev/null +++ b/docs/en/resources.rst @@ -0,0 +1,40 @@ +.. _resources: + +Resources +========= + + +Useful Links +------------- + +* The `esp32.com forum `_ is a place to ask questions and find community resources. + +* Check the `Issues `_ section on GitHub if you find a bug or have a feature request. Please check existing `issues `_ before opening a new one. + +* Several `books `_ have been written about the ESP8266 or ESP32 series of SoCs and they are listed on `Espressif `__ web site. + +* If you're interested in contributing to esptool.py, please check the :ref:`contribute` page. + +* For additional {IDF_TARGET_NAME} product related information, please refer to the `documentation `_ section of `Espressif `__ web site. + +Webinars and Trainings +---------------------- + +Mastering the Basics of Espressif Chips: An In-Depth Look at Chip Flashing +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The content of this webinar is designed for developers, engineers and hobbyists interested in getting a better understanding of how to use esptool.py or other tools for the development with the ESP8266 or ESP32 series of SoCs. + +It offers an in-depth look at the inner mechanisms of esptool.py, including the :ref:`boot-mode` process. + +.. image:: https://img.youtube.com/vi/zh-Y_s4X6zs/maxresdefault.jpg + :alt: Mastering the Basics of Espressif Chips: An In-Depth Look at Chip Flashing + :target: https://www.youtube.com/watch?v=zh-Y_s4X6zs + +DevCon22: esptool.py: Espressif's Swiss Army Knife +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +This talk aims to show how simple, yet powerful, esptool.py is, and how to use it to tame your ESP. + +.. image:: https://img.youtube.com/vi/GjWGKzu3XTk/maxresdefault.jpg + :alt: DevCon22: esptool.py: Espressif's Swiss Army Knife + :target: https://www.youtube.com/watch?v=GjWGKzu3XTk From 8bb82aee995e4f83b126381a623ba8c0d0f00a1a Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 27 Jul 2023 14:31:13 +0200 Subject: [PATCH 052/209] fix(autodetection): Remove the ESP32-S2 ROM class from get_security_info autodetection --- esptool/cmds.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 9f27b3835..77cfbee14 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -96,7 +96,7 @@ def detect_chip( print("Detecting chip type...", end="") chip_id = detect_port.get_chip_id() for cls in [ - n for n in ROM_LIST if n.CHIP_NAME not in ("ESP8266", "ESP32", "ESP32S2") + n for n in ROM_LIST if n.CHIP_NAME not in ("ESP8266", "ESP32", "ESP32-S2") ]: # cmd not supported on ESP8266 and ESP32 + ESP32-S2 doesn't return chip_id if chip_id == cls.IMAGE_CHIP_ID: From b1f819f66b0df962abc1962e233f0504f47a7b96 Mon Sep 17 00:00:00 2001 From: Tomas Sebestik Date: Tue, 1 Aug 2023 14:47:47 +0200 Subject: [PATCH 053/209] change(pre-commit): Bump version conventional-precommit-linter to 1.2.1 --- .pre-commit-config.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index a005434de..fa6705f9a 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -8,7 +8,7 @@ repos: hooks: - id: black - repo: https://github.com/espressif/conventional-precommit-linter - rev: v1.2.0 + rev: v1.2.1 hooks: - id: conventional-precommit-linter stages: [commit-msg] From ab1c19a517e371b3f31cbb361ae3b8dce9000717 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 27 Jul 2023 10:54:14 +0800 Subject: [PATCH 054/209] feat(esptool): added target to esp32p4 --- .gitlab-ci.yml | 2 + espefuse/__init__.py | 2 + espefuse/efuse/esp32p4/__init__.py | 3 + .../efuse/esp32p4/emulate_efuse_controller.py | 94 ++++ espefuse/efuse/esp32p4/fields.py | 457 ++++++++++++++++++ espefuse/efuse/esp32p4/mem_definition.py | 162 +++++++ espefuse/efuse/esp32p4/operations.py | 381 +++++++++++++++ espefuse/efuse_defs/esp32p4.yaml | 92 ++++ espsecure/__init__.py | 4 +- esptool/bin_image.py | 11 + esptool/targets/__init__.py | 2 + esptool/targets/esp32p4.py | 184 +++++++ flasher_stub/compare_stubs.py | 2 +- test/test_espefuse.py | 11 +- 14 files changed, 1401 insertions(+), 6 deletions(-) create mode 100644 espefuse/efuse/esp32p4/__init__.py create mode 100644 espefuse/efuse/esp32p4/emulate_efuse_controller.py create mode 100644 espefuse/efuse/esp32p4/fields.py create mode 100644 espefuse/efuse/esp32p4/mem_definition.py create mode 100644 espefuse/efuse/esp32p4/operations.py create mode 100644 espefuse/efuse_defs/esp32p4.yaml create mode 100644 esptool/targets/esp32p4.py diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f020d75c7..43da07e89 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -84,6 +84,8 @@ host_tests: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2beta1 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c6 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2 + # TODO: ESP32P4 + # - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32p4 # some .coverage files in sub-directories are not collected on some runners, move them first - find . -mindepth 2 -type f -name ".coverage*" -print -exec mv --backup=numbered {} . \; diff --git a/espefuse/__init__.py b/espefuse/__init__.py index d36d42262..777d53f41 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -14,6 +14,7 @@ import espefuse.efuse.esp32c6 as esp32c6_efuse import espefuse.efuse.esp32h2 as esp32h2_efuse import espefuse.efuse.esp32h2beta1 as esp32h2beta1_efuse +import espefuse.efuse.esp32p4 as esp32p4_efuse import espefuse.efuse.esp32s2 as esp32s2_efuse import espefuse.efuse.esp32s3 as esp32s3_efuse import espefuse.efuse.esp32s3beta2 as esp32s3beta2_efuse @@ -49,6 +50,7 @@ "esp32c3": DefChip("ESP32-C3", esp32c3_efuse, esptool.targets.ESP32C3ROM), "esp32c6": DefChip("ESP32-C6", esp32c6_efuse, esptool.targets.ESP32C6ROM), "esp32h2": DefChip("ESP32-H2", esp32h2_efuse, esptool.targets.ESP32H2ROM), + "esp32p4": DefChip("ESP32-P4", esp32p4_efuse, esptool.targets.ESP32P4ROM), "esp32h2beta1": DefChip( "ESP32-H2(beta1)", esp32h2beta1_efuse, esptool.targets.ESP32H2BETA1ROM ), diff --git a/espefuse/efuse/esp32p4/__init__.py b/espefuse/efuse/esp32p4/__init__.py new file mode 100644 index 000000000..a3b55a802 --- /dev/null +++ b/espefuse/efuse/esp32p4/__init__.py @@ -0,0 +1,3 @@ +from . import operations +from .emulate_efuse_controller import EmulateEfuseController +from .fields import EspEfuses diff --git a/espefuse/efuse/esp32p4/emulate_efuse_controller.py b/espefuse/efuse/esp32p4/emulate_efuse_controller.py new file mode 100644 index 000000000..fa9217fc4 --- /dev/null +++ b/espefuse/efuse/esp32p4/emulate_efuse_controller.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python +# +# This file describes eFuses controller for ESP32-P4 chip +# +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from ..emulate_efuse_controller_base import EmulateEfuseControllerBase, FatalError + + +class EmulateEfuseController(EmulateEfuseControllerBase): + """The class for virtual efuse operation. Using for HOST_TEST.""" + + CHIP_NAME = "ESP32-P4" + mem = None + debug = False + Blocks = EfuseDefineBlocks + Fields = EfuseDefineFields + REGS = EfuseDefineRegisters + + def __init__(self, efuse_file=None, debug=False): + super(EmulateEfuseController, self).__init__(efuse_file, debug) + self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + + """ esptool method start >>""" + + def get_major_chip_version(self): + return 0 + + def get_minor_chip_version(self): + return 0 + + def get_crystal_freq(self): + return 40 # MHz (common for all chips) + + def get_security_info(self): + return { + "flags": 0, + "flash_crypt_cnt": 0, + "key_purposes": 0, + "chip_id": 0, + "api_version": 0, + } + + """ << esptool method end """ + + def handle_writing_event(self, addr, value): + if addr == self.REGS.EFUSE_CMD_REG: + if value & self.REGS.EFUSE_PGM_CMD: + self.copy_blocks_wr_regs_to_rd_regs(updated_block=(value >> 2) & 0xF) + self.clean_blocks_wr_regs() + self.check_rd_protection_area() + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + elif value == self.REGS.EFUSE_READ_CMD: + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.save_to_file() + + def get_bitlen_of_block(self, blk, wr=False): + if blk.id == 0: + if wr: + return 32 * 8 + else: + return 32 * blk.len + else: + if wr: + rs_coding = 32 * 3 + return 32 * 8 + rs_coding + else: + return 32 * blk.len + + def handle_coding_scheme(self, blk, data): + if blk.id != 0: + # CODING_SCHEME RS applied only for all blocks except BLK0. + coded_bytes = 12 + data.pos = coded_bytes * 8 + plain_data = data.readlist("32*uint:8")[::-1] + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(coded_bytes) + # 32 byte of data + 12 bytes RS + calc_encoded_data = list(rs.encode([x for x in plain_data])) + data.pos = 0 + if calc_encoded_data != data.readlist("44*uint:8")[::-1]: + raise FatalError("Error in coding scheme data") + data = data[coded_bytes * 8 :] + if blk.len < 8: + data = data[(8 - blk.len) * 32 :] + return data diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py new file mode 100644 index 000000000..d74b98277 --- /dev/null +++ b/espefuse/efuse/esp32p4/fields.py @@ -0,0 +1,457 @@ +#!/usr/bin/env python +# +# This file describes eFuses for ESP32-P4 chip +# +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import binascii +import struct +import time + +from bitstring import BitArray + +import esptool + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from .. import base_fields +from .. import util + + +class EfuseBlock(base_fields.EfuseBlockBase): + def len_of_burn_unit(self): + # The writing register window is 8 registers for any blocks. + # len in bytes + return 8 * 4 + + def __init__(self, parent, param, skip_read=False): + parent.read_coding_scheme() + super(EfuseBlock, self).__init__(parent, param, skip_read=skip_read) + + def apply_coding_scheme(self): + data = self.get_raw(from_read=False)[::-1] + if len(data) < self.len_of_burn_unit(): + add_empty_bytes = self.len_of_burn_unit() - len(data) + data = data + (b"\x00" * add_empty_bytes) + if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS: + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(12) + # 32 byte of data + 12 bytes RS + encoded_data = rs.encode([x for x in data]) + words = struct.unpack("<" + "I" * 11, encoded_data) + # returns 11 words (8 words of data + 3 words of RS coding) + else: + # takes 32 bytes + words = struct.unpack("<" + ("I" * (len(data) // 4)), data) + # returns 8 words + return words + + +class EspEfuses(base_fields.EspEfusesBase): + """ + Wrapper object to manage the efuse fields in a connected ESP bootloader + """ + + Blocks = EfuseDefineBlocks() + Fields = EfuseDefineFields() + REGS = EfuseDefineRegisters + BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() + BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() + + debug = False + do_not_confirm = False + + def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self._esp = esp + self.debug = debug + self.do_not_confirm = do_not_confirm + if esp.CHIP_NAME != "ESP32-P4": + raise esptool.FatalError( + "Expected the 'esp' param for ESP32-P4 chip but got for '%s'." + % (esp.CHIP_NAME) + ) + if not skip_connect: + flags = self._esp.get_security_info()["flags"] + GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE = 1 << 2 + if flags & GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE: + raise esptool.FatalError( + "Secure Download Mode is enabled. The tool can not read eFuses." + ) + self.blocks = [ + EfuseBlock(self, self.Blocks.get(block), skip_read=skip_connect) + for block in self.Blocks.BLOCKS + ] + if not skip_connect: + self.get_coding_scheme_warnings() + self.efuses = [ + EfuseField.from_tuple( + self, self.Fields.get(efuse), self.Fields.get(efuse).class_type + ) + for efuse in self.Fields.EFUSES + ] + self.efuses += [ + EfuseField.from_tuple( + self, self.Fields.get(efuse), self.Fields.get(efuse).class_type + ) + for efuse in self.Fields.KEYBLOCKS + ] + if skip_connect: + self.efuses += [ + EfuseField.from_tuple( + self, self.Fields.get(efuse), self.Fields.get(efuse).class_type + ) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + else: + if self["BLK_VERSION_MAJOR"].get() == 1: + self.efuses += [ + EfuseField.from_tuple( + self, self.Fields.get(efuse), self.Fields.get(efuse).class_type + ) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + self.efuses += [ + EfuseField.from_tuple( + self, self.Fields.get(efuse), self.Fields.get(efuse).class_type + ) + for efuse in self.Fields.CALC + ] + + def __getitem__(self, efuse_name): + """Return the efuse field with the given name""" + for e in self.efuses: + if efuse_name == e.name: + return e + new_fields = False + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: + e = self.Fields.get(efuse) + if e.name == efuse_name: + self.efuses += [ + EfuseField.from_tuple( + self, self.Fields.get(efuse), self.Fields.get(efuse).class_type + ) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + new_fields = True + if new_fields: + for e in self.efuses: + if efuse_name == e.name: + return e + raise KeyError + + def read_coding_scheme(self): + self.coding_scheme = self.REGS.CODING_SCHEME_RS + + def print_status_regs(self): + print("") + self.blocks[0].print_block(self.blocks[0].err_bitarray, "err__regs", debug=True) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG) + ) + ) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG) + ) + ) + + def get_block_errors(self, block_num): + """Returns (error count, failure boolean flag)""" + return self.blocks[block_num].num_errors, self.blocks[block_num].fail + + def efuse_controller_setup(self): + self.set_efuse_timing() + self.clear_pgm_registers() + self.wait_efuse_idle() + + def write_efuses(self, block): + self.efuse_program(block) + return self.get_coding_scheme_warnings(silent=True) + + def clear_pgm_registers(self): + self.wait_efuse_idle() + for r in range( + self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4 + ): + self.write_reg(r, 0) + + def wait_efuse_idle(self): + deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT + while time.time() < deadline: + # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: + if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: + return + raise esptool.FatalError( + "Timed out waiting for Efuse controller command to complete" + ) + + def efuse_program(self, block): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE) + self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2)) + self.wait_efuse_idle() + self.clear_pgm_registers() + self.efuse_read() + + def efuse_read(self): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE) + # need to add a delay after triggering EFUSE_READ_CMD, as ROM loader checks some + # efuse registers after each command is completed + # if ENABLE_SECURITY_DOWNLOAD or DIS_DOWNLOAD_MODE is enabled by the current cmd, then we need to try to reconnect to the chip. + try: + self.write_reg( + self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_READ_CMD, delay_after_us=1000 + ) + self.wait_efuse_idle() + except esptool.FatalError: + secure_download_mode_before = self._esp.secure_download_mode + + try: + self._esp = self.reconnect_chip(self._esp) + except esptool.FatalError: + print("Can not re-connect to the chip") + if not self["DIS_DOWNLOAD_MODE"].get() and self[ + "DIS_DOWNLOAD_MODE" + ].get(from_read=False): + print( + "This is the correct behavior as we are actually burning " + "DIS_DOWNLOAD_MODE which disables the connection to the chip" + ) + print("DIS_DOWNLOAD_MODE is enabled") + print("Successful") + exit(0) # finish without errors + raise + + print("Established a connection with the chip") + if self._esp.secure_download_mode and not secure_download_mode_before: + print("Secure download mode is enabled") + if not self["ENABLE_SECURITY_DOWNLOAD"].get() and self[ + "ENABLE_SECURITY_DOWNLOAD" + ].get(from_read=False): + print( + "espefuse tool can not continue to work in Secure download mode" + ) + print("ENABLE_SECURITY_DOWNLOAD is enabled") + print("Successful") + exit(0) # finish without errors + raise + + def set_efuse_timing(self): + """Set timing registers for burning efuses""" + # Configure clock + apb_freq = self.get_crystal_freq() + if apb_freq != 40: + raise esptool.FatalError( + "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq + ) + + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 + ) + + def get_coding_scheme_warnings(self, silent=False): + """Check if the coding scheme has detected any errors.""" + ret_fail = False + for block in self.blocks: + if block.id == 0: + words = [ + self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) + for offs in range(5) + ] + data = BitArray() + for word in reversed(words): + data.append("uint:32=%d" % word) + # pos=32 because EFUSE_WR_DIS goes first it is 32bit long + # and not under error control + block.err_bitarray.overwrite(data, pos=32) + block.num_errors = block.err_bitarray.count(True) + block.fail = block.num_errors != 0 + else: + addr_reg_f, fail_bit = self.REGS.BLOCK_FAIL_BIT[block.id] + if fail_bit is None: + block.fail = False + else: + block.fail = self.read_reg(addr_reg_f) & (1 << fail_bit) != 0 + + addr_reg_n, num_mask, num_offs = self.REGS.BLOCK_NUM_ERRORS[block.id] + if num_mask is None or num_offs is None: + block.num_errors = 0 + else: + block.num_errors = ( + self.read_reg(addr_reg_n) >> num_offs + ) & num_mask + + ret_fail |= block.fail + if not silent and (block.fail or block.num_errors): + print( + "Error(s) in BLOCK%d [ERRORS:%d FAIL:%d]" + % (block.id, block.num_errors, block.fail) + ) + if (self.debug or ret_fail) and not silent: + self.print_status_regs() + return ret_fail + + def summary(self): + # TODO add support set_flash_voltage - "Flash voltage (VDD_SPI)" + return "" + + +class EfuseField(base_fields.EfuseFieldBase): + @staticmethod + def from_tuple(parent, efuse_tuple, type_class): + return { + "mac": EfuseMacField, + "keypurpose": EfuseKeyPurposeField, + "t_sensor": EfuseTempSensor, + "adc_tp": EfuseAdcPointCalibration, + }.get(type_class, EfuseField)(parent, efuse_tuple) + + def get_info(self): + output = "%s (BLOCK%d)" % (self.name, self.block) + errs, fail = self.parent.get_block_errors(self.block) + if errs != 0 or fail: + output += ( + "[FAIL:%d]" % (fail) + if self.block == 0 + else "[ERRS:%d FAIL:%d]" % (errs, fail) + ) + if self.efuse_class == "keyblock": + name = self.parent.blocks[self.block].key_purpose_name + if name is not None: + output += "\n Purpose: %s\n " % (self.parent[name].get()) + return output + + +class EfuseTempSensor(EfuseField): + def get(self, from_read=True): + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * 0.1 + + +class EfuseAdcPointCalibration(EfuseField): + def get(self, from_read=True): + STEP_SIZE = 4 + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * STEP_SIZE + + +class EfuseMacField(EfuseField): + def check_format(self, new_value_str): + if new_value_str is None: + raise esptool.FatalError( + "Required MAC Address in AA:CD:EF:01:02:03 format!" + ) + if new_value_str.count(":") != 5: + raise esptool.FatalError( + "MAC Address needs to be a 6-byte hexadecimal format " + "separated by colons (:)!" + ) + hexad = new_value_str.replace(":", "") + if len(hexad) != 12: + raise esptool.FatalError( + "MAC Address needs to be a 6-byte hexadecimal number " + "(12 hexadecimal characters)!" + ) + # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', + bindata = binascii.unhexlify(hexad) + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") + return bindata + + def check(self): + errs, fail = self.parent.get_block_errors(self.block) + if errs != 0 or fail: + output = "Block%d has ERRORS:%d FAIL:%d" % (self.block, errs, fail) + else: + output = "OK" + return "(" + output + ")" + + def get(self, from_read=True): + if self.name == "CUSTOM_MAC": + mac = self.get_raw(from_read)[::-1] + else: + mac = self.get_raw(from_read) + return "%s %s" % (util.hexify(mac, ":"), self.check()) + + def save(self, new_value): + def print_field(e, new_value): + print( + " - '{}' ({}) {} -> {}".format( + e.name, e.description, e.get_bitstring(), new_value + ) + ) + + if self.name == "CUSTOM_MAC": + bitarray_mac = self.convert_to_bitstring(new_value) + print_field(self, bitarray_mac) + super(EfuseMacField, self).save(new_value) + else: + # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, + # as it's written in the factory. + raise esptool.FatalError("Writing Factory MAC address is not supported") + + +# fmt: off +class EfuseKeyPurposeField(EfuseField): + KEY_PURPOSES = [ + ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) + ("RESERVED", 1, None, None, "no_need_rd_protect"), # Reserved + ("XTS_AES_256_KEY_1", 2, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_1 (flash/PSRAM encryption) + ("XTS_AES_256_KEY_2", 3, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_2 (flash/PSRAM encryption) + ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) + ("HMAC_DOWN_ALL", 5, None, None, "need_rd_protect"), # HMAC Downstream mode + ("HMAC_DOWN_JTAG", 6, None, None, "need_rd_protect"), # JTAG soft enable key (uses HMAC Downstream mode) + ("HMAC_DOWN_DIGITAL_SIGNATURE", 7, None, None, "need_rd_protect"), # Digital Signature peripheral key (uses HMAC Downstream mode) + ("HMAC_UP", 8, None, None, "need_rd_protect"), # HMAC Upstream mode + ("SECURE_BOOT_DIGEST0", 9, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST0 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST1", 10, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST1 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST2", 11, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST2 (Secure Boot key digest) + ] +# fmt: on + KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] + DIGEST_KEY_PURPOSES = [name[0] for name in KEY_PURPOSES if name[2] == "DIGEST"] + + def check_format(self, new_value_str): + # str convert to int: "XTS_AES_128_KEY" - > str(4) + # if int: 4 -> str(4) + raw_val = new_value_str + for purpose_name in self.KEY_PURPOSES: + if purpose_name[0] == new_value_str: + raw_val = str(purpose_name[1]) + break + if raw_val.isdigit(): + if int(raw_val) not in [p[1] for p in self.KEY_PURPOSES if p[1] > 0]: + raise esptool.FatalError("'%s' can not be set (value out of range)" % raw_val) + else: + raise esptool.FatalError("'%s' unknown name" % raw_val) + return raw_val + + def need_reverse(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[3] == "Reverse" + + def need_rd_protect(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[4] == "need_rd_protect" + + def get(self, from_read=True): + for p in self.KEY_PURPOSES: + if p[1] == self.get_raw(from_read): + return p[0] + return "FORBIDDEN_STATE" + + def save(self, new_value): + raw_val = int(self.check_format(str(new_value))) + return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32p4/mem_definition.py b/espefuse/efuse/esp32p4/mem_definition.py new file mode 100644 index 000000000..eae160fe0 --- /dev/null +++ b/espefuse/efuse/esp32p4/mem_definition.py @@ -0,0 +1,162 @@ +# This file describes eFuses fields and registers for ESP32-P4 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os + +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, +) + + +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 + + # EFUSE registers & command/conf values + DR_REG_EFUSE_BASE = 0x5012D000 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C + EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 + EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 + EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 + EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C + EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 + EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC + EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 + EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 + EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 + + # this chip has a design error so fail_bit is shifted by one block but err_num is in the correct place + BLOCK_FAIL_BIT = [ + # error_reg, fail_bit + (EFUSE_RD_REPEAT_ERR0_REG, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 7), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 11), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 15), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 19), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 23), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 27), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 31), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR1_REG, 3), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 7), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, None), # BLOCK_SYS_DATA2 + ] + + BLOCK_NUM_ERRORS = [ + # error_reg, err_num_mask, err_num_offs + (EFUSE_RD_REPEAT_ERR0_REG, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4), # BLOCK_SYS_DATA2 + ] + + # EFUSE_WR_TIM_CONF2_REG + EFUSE_PWR_OFF_NUM_S = 0 + EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + + +class EfuseDefineBlocks(EfuseBlocksBase): + __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE + __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG + # List of efuse blocks + # fmt: off + BLOCKS = [ + # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose + ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), + ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), + ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), + ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), + ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), + ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), + ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), + ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), + ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), + ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), + ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), + ] + # fmt: on + + def get_burn_block_data_names(self): + list_of_names = [] + for block in self.BLOCKS: + blk = self.get(block) + if blk.name: + list_of_names.append(blk.name) + if blk.alias: + for alias in blk.alias: + list_of_names.append(alias) + return list_of_names + + +class EfuseDefineFields(EfuseFieldsBase): + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32p4/operations.py b/espefuse/efuse/esp32p4/operations.py new file mode 100644 index 000000000..271584ffc --- /dev/null +++ b/espefuse/efuse/esp32p4/operations.py @@ -0,0 +1,381 @@ +#!/usr/bin/env python +# +# This file includes the operations with eFuses for ESP32-P4 chip +# +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import argparse +import os # noqa: F401. It is used in IDF scripts +import traceback + +import espsecure + +import esptool + +from . import fields +from .. import util +from ..base_operations import ( + add_common_commands, + add_force_write_always, + burn_bit, + burn_block_data, + burn_efuse, + check_error, + dump, + read_protect_efuse, + summary, + write_protect_efuse, +) + + +def protect_options(p): + p.add_argument( + "--no-write-protect", + help="Disable write-protecting of the key. The key remains writable. " + "(The keys use the RS coding scheme that does not support " + "post-write data changes. Forced write can damage RS encoding bits.) " + "The write-protecting of keypurposes does not depend on the option, " + "it will be set anyway.", + action="store_true", + ) + p.add_argument( + "--no-read-protect", + help="Disable read-protecting of the key. The key remains readable software." + "The key with keypurpose[USER, RESERVED and *_DIGEST] " + "will remain readable anyway. For the rest keypurposes the read-protection " + "will be defined the option (Read-protect by default).", + action="store_true", + ) + + +def add_commands(subparsers, efuses): + add_common_commands(subparsers, efuses) + burn_key = subparsers.add_parser( + "burn_key", help="Burn the key block with the specified name" + ) + protect_options(burn_key) + add_force_write_always(burn_key) + burn_key.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data", + action="append", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + + burn_key_digest = subparsers.add_parser( + "burn_key_digest", + help="Parse a RSA public key and burn the digest to key efuse block", + ) + protect_options(burn_key_digest) + add_force_write_always(burn_key_digest) + burn_key_digest.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + action="append", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key_digest.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + + p = subparsers.add_parser( + "set_flash_voltage", + help="Permanently set the internal flash voltage regulator " + "to either 1.8V, 3.3V or OFF. " + "This means GPIO45 can be high or low at reset without " + "changing the flash voltage.", + ) + p.add_argument("voltage", help="Voltage selection", choices=["1.8V", "3.3V", "OFF"]) + + p = subparsers.add_parser( + "burn_custom_mac", help="Burn a 48-bit Custom MAC Address to EFUSE BLOCK3." + ) + p.add_argument( + "mac", + help="Custom MAC Address to burn given in hexadecimal format with bytes " + "separated by colons (e.g. AA:CD:EF:01:02:03).", + type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), + ) + add_force_write_always(p) + + p = subparsers.add_parser("get_custom_mac", help="Prints the Custom MAC Address.") + + +def burn_custom_mac(esp, efuses, args): + efuses["CUSTOM_MAC"].save(args.mac) + if not efuses.burn_all(check_batch_mode=True): + return + get_custom_mac(esp, efuses, args) + print("Successful") + + +def get_custom_mac(esp, efuses, args): + print("Custom MAC Address: {}".format(efuses["CUSTOM_MAC"].get())) + + +def set_flash_voltage(esp, efuses, args): + raise esptool.FatalError("set_flash_voltage is not supported!") + + +def adc_info(esp, efuses, args): + print("not supported yet") + + +def burn_key(esp, efuses, args, digest=None): + if digest is None: + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + else: + datafile_list = digest[0 : len([name for name in digest if name is not None]) :] + efuses.force_write_always = args.force_write_always + block_name_list = args.block[ + 0 : len([name for name in args.block if name is not None]) : + ] + keypurpose_list = args.keypurpose[ + 0 : len([name for name in args.keypurpose if name is not None]) : + ] + + util.check_duplicate_name_in_list(block_name_list) + if len(block_name_list) != len(datafile_list) or len(block_name_list) != len( + keypurpose_list + ): + raise esptool.FatalError( + "The number of blocks (%d), datafile (%d) and keypurpose (%d) " + "should be the same." + % (len(block_name_list), len(datafile_list), len(keypurpose_list)) + ) + + print("Burn keys to blocks:") + for block_name, datafile, keypurpose in zip( + block_name_list, datafile_list, keypurpose_list + ): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + + block_num = efuses.get_index_block_by_name(block_name) + block = efuses.blocks[block_num] + + if digest is None: + data = datafile.read() + else: + data = datafile + + print(" - %s" % (efuse.name), end=" ") + revers_msg = None + if efuses[block.key_purpose_name].need_reverse(keypurpose): + revers_msg = "\tReversing byte order for AES-XTS hardware peripheral" + data = data[::-1] + print("-> [%s]" % (util.hexify(data, " "))) + if revers_msg: + print(revers_msg) + if len(data) != num_bytes: + raise esptool.FatalError( + "Incorrect key file size %d. Key file must be %d bytes (%d bits) " + "of raw binary key data." % (len(data), num_bytes, num_bytes * 8) + ) + + if efuses[block.key_purpose_name].need_rd_protect(keypurpose): + read_protect = False if args.no_read_protect else True + else: + read_protect = False + write_protect = not args.no_write_protect + + # using efuse instead of a block gives the advantage of checking it as the whole field. + efuse.save(data) + + disable_wr_protect_key_purpose = False + if efuses[block.key_purpose_name].get() != keypurpose: + if efuses[block.key_purpose_name].is_writeable(): + print( + "\t'%s': '%s' -> '%s'." + % ( + block.key_purpose_name, + efuses[block.key_purpose_name].get(), + keypurpose, + ) + ) + efuses[block.key_purpose_name].save(keypurpose) + disable_wr_protect_key_purpose = True + else: + raise esptool.FatalError( + "It is not possible to change '%s' to '%s' " + "because write protection bit is set." + % (block.key_purpose_name, keypurpose) + ) + else: + print("\t'%s' is already '%s'." % (block.key_purpose_name, keypurpose)) + if efuses[block.key_purpose_name].is_writeable(): + disable_wr_protect_key_purpose = True + + if disable_wr_protect_key_purpose: + print("\tDisabling write to '%s'." % block.key_purpose_name) + efuses[block.key_purpose_name].disable_write() + + if read_protect: + print("\tDisabling read to key block") + efuse.disable_read() + + if write_protect: + print("\tDisabling write to key block") + efuse.disable_write() + print("") + + if not write_protect: + print("Keys will remain writeable (due to --no-write-protect)") + if args.no_read_protect: + print("Keys will remain readable (due to --no-read-protect)") + + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") + + +def burn_key_digest(esp, efuses, args): + digest_list = [] + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + block_list = args.block[ + 0 : len([block for block in args.block if block is not None]) : + ] + for block_name, datafile in zip(block_list, datafile_list): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + digest = espsecure._digest_sbv2_public_key(datafile) + if len(digest) != num_bytes: + raise esptool.FatalError( + "Incorrect digest size %d. Digest must be %d bytes (%d bits) " + "of raw binary key data." % (len(digest), num_bytes, num_bytes * 8) + ) + digest_list.append(digest) + burn_key(esp, efuses, args, digest=digest_list) + + +def espefuse(esp, efuses, args, command): + parser = argparse.ArgumentParser() + subparsers = parser.add_subparsers(dest="operation") + add_commands(subparsers, efuses) + try: + cmd_line_args = parser.parse_args(command.split()) + except SystemExit: + traceback.print_stack() + raise esptool.FatalError('"{}" - incorrect command'.format(command)) + if cmd_line_args.operation == "execute_scripts": + configfiles = cmd_line_args.configfiles + index = cmd_line_args.index + # copy arguments from args to cmd_line_args + vars(cmd_line_args).update(vars(args)) + if cmd_line_args.operation == "execute_scripts": + cmd_line_args.configfiles = configfiles + cmd_line_args.index = index + if cmd_line_args.operation is None: + parser.print_help() + parser.exit(1) + operation_func = globals()[cmd_line_args.operation] + # each 'operation' is a module-level function of the same name + operation_func(esp, efuses, cmd_line_args) + + +def execute_scripts(esp, efuses, args): + efuses.batch_mode_cnt += 1 + del args.operation + scripts = args.scripts + del args.scripts + + for file in scripts: + with open(file.name, "r") as file: + exec(compile(file.read(), file.name, "exec")) + + if args.debug: + for block in efuses.blocks: + data = block.get_bitstring(from_read=False) + block.print_block(data, "regs_for_burn", args.debug) + + efuses.batch_mode_cnt -= 1 + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") diff --git a/espefuse/efuse_defs/esp32p4.yaml b/espefuse/efuse_defs/esp32p4.yaml new file mode 100644 index 000000000..895751a8a --- /dev/null +++ b/espefuse/efuse_defs/esp32p4.yaml @@ -0,0 +1,92 @@ +VER_NO: 4df10f83de85f2d830b7c466aabb28e7 +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + RPT4_RESERVED0_4 : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + POWERGLITCH_EN : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether power glitch function is enabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: n, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} + RPT4_RESERVED0_1 : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} + RPT4_RESERVED0_0 : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} + RPT4_RESERVED1_1 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} + ECDSA_FORCE_USE_HARDWARE_K : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} + CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RPT4_RESERVED2_0 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: Set this bit to disable USB-Serial-JTAG print during rom boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + RPT4_RESERVED3_5 : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos : 9, len : 16, start: 137, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[24:9]', bloc: 'B17[7:1],B18,B19[0]'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 25, len : 1, start: 153, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'} + HYS_EN_PAD0 : {show: y, blk : 0, word: 4, pos: 26, len : 6, start: 154, type : 'uint:6', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Set bits to enable hysteresis function of PAD0~5, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:26]', bloc: 'B19[7:2]'} + HYS_EN_PAD1 : {show: y, blk : 0, word: 5, pos : 0, len : 22, start: 160, type : 'uint:22', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Set bits to enable hysteresis function of PAD6~27, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[21:0]', bloc: 'B20,B21,B22[5:0]'} + RPT4_RESERVED4_1 : {show: n, blk : 0, word: 5, pos: 22, len : 2, start: 182, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:22]', bloc: 'B22[7:6]'} + RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'} + RXIQ_VERSION : {show: y, blk : 1, word: 2, pos : 0, len : 3, start : 64, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[2:0]', bloc: 'B8[2:0]'} + RXIQ_0 : {show: y, blk : 1, word: 2, pos : 3, len : 7, start : 67, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 0, rloc: 'EFUSE_RD_MAC_SYS_2_REG[9:3]', bloc: 'B8[7:3],B9[1:0]'} + RXIQ_1 : {show: y, blk : 1, word: 2, pos: 10, len : 7, start : 74, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 1, rloc: 'EFUSE_RD_MAC_SYS_2_REG[16:10]', bloc: 'B9[7:2],B10[0]'} + RESERVED_1_81 : {show: n, blk : 1, word: 2, pos: 17, len : 15, start : 81, type : 'uint:15', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:17]', bloc: 'B10[7:1],B11'} + MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 21, len : 2, start: 117, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[22:21]', bloc: 'B14[6:5]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 23, len : 1, start: 119, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_MAC_SYS_3_REG[23]', bloc: 'B14[7]'} + FLASH_CAP : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[28:27]', bloc: 'B15[4:3]'} + FLASH_VENDOR : {show: y, blk : 1, word: 3, pos: 29, len : 3, start: 125, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:29]', bloc: 'B15[7:5]'} + PKG_VERSION : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} + RESERVED_1_131 : {show: n, blk : 1, word: 4, pos : 3, len : 29, start: 131, type : 'uint:29', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_4_REG[31:3]', bloc: 'B16[7:3],B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_5_REG, bloc: 'B20,B21,B22,B23'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + RESERVED_2_128 : {show: n, blk : 2, word: 4, pos : 0, len : 2, start: 128, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[1:0]', bloc: 'B16[1:0]'} + BLK_VERSION_MINOR : {show: y, blk : 2, word: 4, pos : 2, len : 3, start: 130, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: 'BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1', rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[4:2]', bloc: 'B16[4:2]'} + BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 5, len : 2, start: 133, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[6:5]', bloc: 'B16[6:5]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 7, len : 1, start: 135, type : bool, wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[7]', bloc: 'B16[7]'} + RESERVED_2_136 : {show: n, blk : 2, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:8]', bloc: 'B17,B18,B19'} + SYS_DATA_PART1_5 : {show: n, blk : 2, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the fifth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA5_REG, bloc: 'B20,B21,B22,B23'} + SYS_DATA_PART1_6 : {show: n, blk : 2, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the sixth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA6_REG, bloc: 'B24,B25,B26,B27'} + SYS_DATA_PART1_7 : {show: n, blk : 2, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the seventh 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA7_REG, bloc: 'B28,B29,B30,B31'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espsecure/__init__.py b/espsecure/__init__.py index d978a862c..3e5ef2039 100755 --- a/espsecure/__init__.py +++ b/espsecure/__init__.py @@ -1712,7 +1712,7 @@ def main(custom_commandline=None): "--aes_xts", "-x", help="Decrypt data using AES-XTS as used on " - "ESP32-S2, ESP32-C2, ESP32-C3 and ESP32-C6", + "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6 and ESP32-P4", action="store_true", ) p.add_argument( @@ -1752,7 +1752,7 @@ def main(custom_commandline=None): "--aes_xts", "-x", help="Encrypt data using AES-XTS as used on " - "ESP32-S2, ESP32-C2, ESP32-C3 and ESP32-C6", + "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6 and ESP32-P4", action="store_true", ) p.add_argument( diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 08a7ddbf3..c6ed200b7 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -20,6 +20,7 @@ ESP32H2BETA1ROM, ESP32H2BETA2ROM, ESP32H2ROM, + ESP32P4ROM, ESP32ROM, ESP32S2ROM, ESP32S3BETA2ROM, @@ -61,6 +62,7 @@ def select_image_class(f, chip): "esp32c2": ESP32C2FirmwareImage, "esp32c6": ESP32C6FirmwareImage, "esp32h2": ESP32H2FirmwareImage, + "esp32p4": ESP32P4FirmwareImage, }[chip](f) else: # Otherwise, ESP8266 so look at magic to determine the image type magic = ord(f.read(1)) @@ -1056,6 +1058,15 @@ def set_mmu_page_size(self, size): ESP32C6ROM.BOOTLOADER_IMAGE = ESP32C6FirmwareImage +class ESP32P4FirmwareImage(ESP32FirmwareImage): + """ESP32P4 Firmware Image almost exactly the same as ESP32FirmwareImage""" + + ROM_LOADER = ESP32P4ROM + + +ESP32P4ROM.BOOTLOADER_IMAGE = ESP32P4FirmwareImage + + class ESP32H2FirmwareImage(ESP32C6FirmwareImage): """ESP32H2 Firmware Image almost exactly the same as ESP32FirmwareImage""" diff --git a/esptool/targets/__init__.py b/esptool/targets/__init__.py index 9d76ca543..dd1ba485d 100644 --- a/esptool/targets/__init__.py +++ b/esptool/targets/__init__.py @@ -6,6 +6,7 @@ from .esp32h2 import ESP32H2ROM from .esp32h2beta1 import ESP32H2BETA1ROM from .esp32h2beta2 import ESP32H2BETA2ROM +from .esp32p4 import ESP32P4ROM from .esp32s2 import ESP32S2ROM from .esp32s3 import ESP32S3ROM from .esp32s3beta2 import ESP32S3BETA2ROM @@ -25,6 +26,7 @@ "esp32c2": ESP32C2ROM, "esp32c6": ESP32C6ROM, "esp32h2": ESP32H2ROM, + "esp32p4": ESP32P4ROM, } CHIP_LIST = list(CHIP_DEFS.keys()) diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py new file mode 100644 index 000000000..74e6ff089 --- /dev/null +++ b/esptool/targets/esp32p4.py @@ -0,0 +1,184 @@ +# SPDX-FileCopyrightText: 2023 Fredrik Ahlberg, Angus Gratton, +# Espressif Systems (Shanghai) CO LTD, other contributors as noted. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import struct + +from .esp32 import ESP32ROM +from ..loader import ESPLoader +from ..util import FatalError, NotImplementedInROMError + + +class ESP32P4ROM(ESP32ROM): + CHIP_NAME = "ESP32-P4" + IMAGE_CHIP_ID = 18 + + FPGA_SLOW_BOOT = False + + IROM_MAP_START = 0x40000000 + IROM_MAP_END = 0x44000000 + DROM_MAP_START = 0x40000000 + DROM_MAP_END = 0x44000000 + + BOOTLOADER_FLASH_OFFSET = 0x0 + + CHIP_DETECT_MAGIC_VALUE = [0x0] + + UART_DATE_REG_ADDR = 0x500CA000 + 0x8C + + EFUSE_BASE = 0x5012D000 + EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044 + MAC_EFUSE_REG = EFUSE_BASE + 0x044 + + SPI_REG_BASE = 0x5008C000 + + EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030 # BLOCK0 read base address + + EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY0_SHIFT = 24 + EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY1_SHIFT = 28 + EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38 + EFUSE_PURPOSE_KEY2_SHIFT = 0 + EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38 + EFUSE_PURPOSE_KEY3_SHIFT = 4 + EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38 + EFUSE_PURPOSE_KEY4_SHIFT = 8 + EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38 + EFUSE_PURPOSE_KEY5_SHIFT = 12 + + EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE + EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20 + + EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034 + EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18 + + EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038 + EFUSE_SECURE_BOOT_EN_MASK = 1 << 20 + + PURPOSE_VAL_XTS_AES256_KEY_1 = 2 + PURPOSE_VAL_XTS_AES256_KEY_2 = 3 + PURPOSE_VAL_XTS_AES128_KEY = 4 + + SUPPORTS_ENCRYPTED_FLASH = True + + FLASH_ENCRYPTED_WRITE_ALIGN = 16 + + MEMORY_MAP = [ + [0x00000000, 0x00010000, "PADDING"], + [0x40000000, 0x44000000, "DROM"], + [0x4FF00000, 0x4FFA0000, "DRAM"], + [0x4FF00000, 0x4FFA0000, "BYTE_ACCESSIBLE"], + [0x4FC00000, 0x4FC20000, "DROM_MASK"], + [0x4FC00000, 0x4FC20000, "IROM_MASK"], + [0x40000000, 0x44000000, "IROM"], + [0x4FF00000, 0x4FFA0000, "IRAM"], + [0x50108000, 0x50110000, "RTC_IRAM"], + [0x50108000, 0x50110000, "RTC_DRAM"], + [0x600FE000, 0x60100000, "MEM_INTERNAL2"], + ] + + def get_pkg_version(self): + # ESP32P4 TODO + return 0 + + def get_minor_chip_version(self): + # ESP32P4 TODO + return 0 + + def get_major_chip_version(self): + # ESP32P4 TODO + return 0 + + def get_chip_description(self): + chip_name = { + 0: "ESP32-P4", + }.get(self.get_pkg_version(), "unknown ESP32-P4") + major_rev = self.get_major_chip_version() + minor_rev = self.get_minor_chip_version() + return f"{chip_name} (revision v{major_rev}.{minor_rev})" + + def get_chip_features(self): + return ["High-Performance MCU"] + + def get_crystal_freq(self): + # ESP32P4 XTAL is fixed to 40MHz + return 40 + + def override_vddsdio(self, new_voltage): + raise NotImplementedInROMError( + "VDD_SDIO overrides are not supported for ESP32-P4" + ) + + def read_mac(self, mac_type="BASE_MAC"): + """Read MAC from EFUSE region""" + if mac_type != "BASE_MAC": + return None + mac0 = self.read_reg(self.MAC_EFUSE_REG) + mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC + bitstring = struct.pack(">II", mac1, mac0)[2:] + return tuple(bitstring) + + def get_flash_crypt_config(self): + return None # doesn't exist on ESP32-P4 + + def get_secure_boot_enabled(self): + return ( + self.read_reg(self.EFUSE_SECURE_BOOT_EN_REG) + & self.EFUSE_SECURE_BOOT_EN_MASK + ) + + def get_key_block_purpose(self, key_block): + if key_block < 0 or key_block > 5: + raise FatalError("Valid key block numbers must be in range 0-5") + + reg, shift = [ + (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT), + (self.EFUSE_PURPOSE_KEY1_REG, self.EFUSE_PURPOSE_KEY1_SHIFT), + (self.EFUSE_PURPOSE_KEY2_REG, self.EFUSE_PURPOSE_KEY2_SHIFT), + (self.EFUSE_PURPOSE_KEY3_REG, self.EFUSE_PURPOSE_KEY3_SHIFT), + (self.EFUSE_PURPOSE_KEY4_REG, self.EFUSE_PURPOSE_KEY4_SHIFT), + (self.EFUSE_PURPOSE_KEY5_REG, self.EFUSE_PURPOSE_KEY5_SHIFT), + ][key_block] + return (self.read_reg(reg) >> shift) & 0xF + + def is_flash_encryption_key_valid(self): + # Need to see either an AES-128 key or two AES-256 keys + purposes = [self.get_key_block_purpose(b) for b in range(6)] + + if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes): + return True + + return any(p == self.PURPOSE_VAL_XTS_AES256_KEY_1 for p in purposes) and any( + p == self.PURPOSE_VAL_XTS_AES256_KEY_2 for p in purposes + ) + + def change_baud(self, baud): + ESPLoader.change_baud(self, baud) + + def _post_connect(self): + # ESP32-P4 doesn't have stub flasher support yet + self.stub_is_disabled = True + self.IS_STUB = False + + +class ESP32P4StubLoader(ESP32P4ROM): + """Access class for ESP32P4 stub loader, runs on top of ROM. + + (Basically the same as ESP32StubLoader, but different base class. + Can possibly be made into a mixin.) + """ + + FLASH_WRITE_SIZE = 0x4000 # matches MAX_WRITE_BLOCK in stub_loader.c + STATUS_BYTES_LENGTH = 2 # same as ESP8266, different to ESP32 ROM + IS_STUB = True + + def __init__(self, rom_loader): + self.secure_download_mode = rom_loader.secure_download_mode + self._port = rom_loader._port + self._trace_enabled = rom_loader._trace_enabled + self.flush_input() # resets _slip_reader + + +ESP32P4ROM.STUB_CLASS = ESP32P4StubLoader diff --git a/flasher_stub/compare_stubs.py b/flasher_stub/compare_stubs.py index 6c8bb7f11..a7b68d01f 100755 --- a/flasher_stub/compare_stubs.py +++ b/flasher_stub/compare_stubs.py @@ -66,7 +66,7 @@ def diff(path_to_new, path_to_old): if __name__ == "__main__": same = True - for chip in esptool.CHIP_LIST: + for chip in [n for n in esptool.CHIP_LIST if n != "esp32p4"]: print("Comparing {} stub: ".format(chip), end="") chip = chip.replace("esp", "") diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 6f8176323..770a82576 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -1,7 +1,7 @@ # HOST_TEST for espefuse.py using the pytest framework # # Supports esp32, esp32s2, esp32s3beta2, esp32s3, -# esp32c3, esp32h2beta1, esp32c2, esp32c6 +# esp32c3, esp32h2beta1, esp32c2, esp32c6, esp32p4 # # How to use: # @@ -431,7 +431,7 @@ def test_burn_custom_mac_with_34_coding_scheme(self): @pytest.mark.skipif( - arg_chip in ["esp32c2", "esp32h2beta1", "esp32c3", "esp32c6", "esp32h2"], + arg_chip in ["esp32c2", "esp32h2beta1", "esp32c3", "esp32c6", "esp32h2", "esp32p4"], reason=f"TODO: add support set_flash_voltage for {arg_chip}", ) class TestSetFlashVoltageCommands(EfuseTestCase): @@ -862,6 +862,7 @@ def test_burn_key_one_key_block_with_fe_and_sb_keys(self): "esp32h2beta1", "esp32c6", "esp32h2", + "esp32p4", ], reason="Only chips with 6 keys", ) @@ -870,7 +871,7 @@ def test_burn_key_with_6_keys(self): BLOCK_KEY0 {IMAGES_DIR}/256bit XTS_AES_256_KEY_1 \ BLOCK_KEY1 {IMAGES_DIR}/256bit_1 XTS_AES_256_KEY_2 \ BLOCK_KEY2 {IMAGES_DIR}/256bit_2 XTS_AES_128_KEY" - if arg_chip in ["esp32c3", "esp32c6"] or arg_chip in [ + if arg_chip in ["esp32c3", "esp32c6", "esp32p4"] or arg_chip in [ "esp32h2", "esp32h2beta1", ]: @@ -1164,6 +1165,7 @@ def test_burn_block_data_with_1_key_block(self): "esp32h2beta1", "esp32c6", "esp32h2", + "esp32p4", ], reason="Only chip with 6 keys", ) @@ -1301,6 +1303,7 @@ def test_burn_block_data_with_offset_1_key_block(self): "esp32h2beta1", "esp32c6", "esp32h2", + "esp32p4", ], reason="Only chips with 6 keys", ) @@ -1496,6 +1499,7 @@ def test_burn_key_from_digest2(self): "esp32h2beta1", "esp32c6", "esp32h2", + "esp32p4", ], reason="Supports 6 key blocks", ) @@ -1607,6 +1611,7 @@ def test_burn_bit_for_chips_with_1_key_block(self): "esp32h2beta1", "esp32c6", "esp32h2", + "esp32p4", ], reason="Only chip with 6 keys", ) From 6c2efddef3f50be6992077d56e5c2e88cf63f7d5 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 27 Jul 2023 23:05:40 +0800 Subject: [PATCH 055/209] feat(espefuse): Add support for esp32p4 chip --- .gitlab-ci.yml | 3 +- docs/en/espefuse/inc/summary_ESP32-P4.rst | 176 ++++++++++++++++++ .../efuse/esp32p4/emulate_efuse_controller.py | 10 +- espefuse/efuse/esp32p4/fields.py | 158 +++++++--------- espefuse/efuse/esp32p4/mem_definition.py | 65 ++++--- espefuse/efuse/esp32p4/operations.py | 23 ++- espefuse/efuse_defs/esp32p4.yaml | 135 +++++++------- test/test_espefuse.py | 24 ++- 8 files changed, 386 insertions(+), 208 deletions(-) create mode 100644 docs/en/espefuse/inc/summary_ESP32-P4.rst diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 43da07e89..4fca1f1ee 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -84,8 +84,7 @@ host_tests: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2beta1 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c6 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2 - # TODO: ESP32P4 - # - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32p4 + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32p4 # some .coverage files in sub-directories are not collected on some runners, move them first - find . -mindepth 2 -type f -name ".coverage*" -print -exec mv --backup=numbered {} . \; diff --git a/docs/en/espefuse/inc/summary_ESP32-P4.rst b/docs/en/espefuse/inc/summary_ESP32-P4.rst new file mode 100644 index 000000000..74421869c --- /dev/null +++ b/docs/en/espefuse/inc/summary_ESP32-P4.rst @@ -0,0 +1,176 @@ +.. code-block:: none + + > espefuse.py -p PORT summary + + Connecting.... + Detecting chip type... ESP32-P4 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + POWERGLITCH_EN (BLOCK0) Represents whether power glitch function is enable = False R/W (0b0) + d. 1: enabled. 0: disabled + DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + KM_HUK_GEN_STATE_LOW (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000000) + mode. Odd of 1 is invalid; even of 1 is valid + KM_HUK_GEN_STATE_HIGH (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000) + mode. Odd of 1 is invalid; even of 1 is valid + KM_RND_SWITCH_CYCLE (BLOCK0) Set bits to control key manager random number swit = 0 R/W (0b00) + ch cycle. 0: control by register. 1: 8 km clk cycl + es. 2: 16 km cycles. 3: 32 km cycles + KM_DEPLOY_ONLY_ONCE (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0) + can only be deployed once. 1 is true; 0 is false. + Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + UART_PRINT_CONTROL (BLOCK0) Represents the type of UART printing. 00: force en = 0 R/W (0b00) + able printing. 01: enable printing when GPIO8 is r + eset at low level. 10: enable printing when GPIO8 + is reset at high level. 11: force disable printing + HYS_EN_PAD (BLOCK0) Represents whether the hysteresis function of corr = False R/W (0b0) + esponding PAD is enabled. 1: enabled. 0:disabled + DCDC_VSET (BLOCK0) Set the dcdc voltage default = 0 R/W (0b00000) + PXA0_TIEH_SEL_0 (BLOCK0) TBD = 0 R/W (0b00) + PXA0_TIEH_SEL_1 (BLOCK0) TBD = 0 R/W (0b00) + PXA0_TIEH_SEL_2 (BLOCK0) TBD = 0 R/W (0b00) + PXA0_TIEH_SEL_3 (BLOCK0) TBD = 0 R/W (0b00) + KM_DISABLE_DEPLOY_MODE (BLOCK0) TBD = 0 R/W (0x0) + HP_PWR_SRC_SEL (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + DCDC_VSET_EN (BLOCK0) Select dcdc vset use efuse_dcdc_vset = False R/W (0b0) + DIS_SWD (BLOCK0) Set this bit to disable super-watchdog = False R/W (0b0) + BLOCK_SYS_DATA1 (BLOCK2) System data part 1 + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TYPE (BLOCK0) The type of interfaced flash. 0: four data lines; = False R/W (0b0) + 1: eight data lines + FLASH_PAGE_SIZE (BLOCK0) Set flash page size = 0 R/W (0b00) + FLASH_ECC_EN (BLOCK0) Set this bit to enable ecc for flash boot = False R/W (0b0) + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is the programmed value. Otherwise; the + waiting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot. 1: forced. 0:not for + ced + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio15 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled. 1: enabled. 0: + disabled + SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) + dd number: disabled. Even number: enabled + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently). 1: disabled. 0: enabled + + Mac fuses: + MAC (BLOCK1) MAC address + = 00:00:00:00:00:00 (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W + MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M + = 00:00:00:00:00:00:00:00 (OK) R/W + AC_EXT[1]:MAC[3]:MAC[4]:MAC[5] + + Security fuses: + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled. 1: disab + led. 0: enabled + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Set this bit to disable accessing MSPI flash/MSPI = False R/W (0b0) + ram by SYS AXI matrix during boot_mode_download + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode). 1: disabl + ed. 0: enabled + FORCE_USE_KEY_MANAGER_KEY (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0) + must come from key manager.. 1 is true; 0 is false + . Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + FORCE_DISABLE_SW_INIT_KEY (BLOCK0) Set this bit to disable software written init key; = False R/W (0b0) + and force use efuse_init_key + XTS_KEY_LENGTH_256 (BLOCK0) Set this bit to configure flash encryption use xts = False R/W (0b0) + -128 key; else use xts-256 key + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + ECDSA_ENABLE_SOFT_K (BLOCK0) Represents whether hardware random number k is for = False R/W (0b0) + ced used in ESDCA. 1: force used. 0: not force use + d + CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) + nabled. 0: disabled + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led. 1: enabled. 0: disabled + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled. 1: enabled. 0: disabled + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + LOCK_KM_KEY (BLOCK0) TBD = False R/W (0b0) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled. 1: enabled. 0: disabled + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) + or enabled when Secure Boot is enabled. 1: disabl + ed. 0: enabled + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + USB_DEVICE_EXCHG_PINS (BLOCK0) Enable usb device exchange pins of D+ and D- = False R/W (0b0) + USB_OTG11_EXCHG_PINS (BLOCK0) Enable usb otg11 exchange pins of D+ and D- = False R/W (0b0) + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled. 1: disabled. 0: enable + d + USB_PHY_SEL (BLOCK0) TBD = False R/W (0b0) + DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download via USB-OTG = False R/W (0b0) + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) + isabled or enabled. 1: disabled. 0: enabled + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled. 1: disabled. 0: ena + bled + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) + is selected at startup. 1: selected. 0: not select + ed + DIS_WDT (BLOCK0) Set this bit to disable watch dog = False R/W (0b0) + \ No newline at end of file diff --git a/espefuse/efuse/esp32p4/emulate_efuse_controller.py b/espefuse/efuse/esp32p4/emulate_efuse_controller.py index fa9217fc4..a96439fdd 100644 --- a/espefuse/efuse/esp32p4/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32p4/emulate_efuse_controller.py @@ -1,8 +1,6 @@ -#!/usr/bin/env python -# # This file describes eFuses controller for ESP32-P4 chip # -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later @@ -18,11 +16,11 @@ class EmulateEfuseController(EmulateEfuseControllerBase): CHIP_NAME = "ESP32-P4" mem = None debug = False - Blocks = EfuseDefineBlocks - Fields = EfuseDefineFields - REGS = EfuseDefineRegisters def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py index d74b98277..44c813060 100644 --- a/espefuse/efuse/esp32p4/fields.py +++ b/espefuse/efuse/esp32p4/fields.py @@ -1,8 +1,6 @@ -#!/usr/bin/env python -# # This file describes eFuses for ESP32-P4 chip # -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later @@ -56,16 +54,15 @@ class EspEfuses(base_fields.EspEfusesBase): Wrapper object to manage the efuse fields in a connected ESP bootloader """ - Blocks = EfuseDefineBlocks() - Fields = EfuseDefineFields() - REGS = EfuseDefineRegisters - BURN_BLOCK_DATA_NAMES = Blocks.get_burn_block_data_names() - BLOCKS_FOR_KEYS = Blocks.get_blocks_for_keys() - debug = False do_not_confirm = False def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() self._esp = esp self.debug = debug self.do_not_confirm = do_not_confirm @@ -87,59 +84,44 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): ] if not skip_connect: self.get_coding_scheme_warnings() - self.efuses = [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.EFUSES - ] + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.KEYBLOCKS + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS ] if skip_connect: self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLK_VERSION_MAJOR"].get() == 1: - self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES - ] + # TODO add processing of self.Fields.BLOCK2_CALIBRATION_EFUSES + # if self["BLK_VERSION_MINOR"].get() == 1: + # self.efuses += [ + # EfuseField.convert(self, efuse) + # for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + # ] self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) - for efuse in self.Fields.CALC + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] def __getitem__(self, efuse_name): """Return the efuse field with the given name""" for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e new_fields = False for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: - e = self.Fields.get(efuse) - if e.name == efuse_name: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): self.efuses += [ - EfuseField.from_tuple( - self, self.Fields.get(efuse), self.Fields.get(efuse).class_type - ) + EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] new_fields = True if new_fields: for e in self.efuses: - if efuse_name == e.name: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): return e raise KeyError @@ -160,10 +142,6 @@ def print_status_regs(self): ) ) - def get_block_errors(self, block_num): - """Returns (error count, failure boolean flag)""" - return self.blocks[block_num].num_errors, self.blocks[block_num].fail - def efuse_controller_setup(self): self.set_efuse_timing() self.clear_pgm_registers() @@ -251,12 +229,21 @@ def set_efuse_timing(self): "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq ) + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) self.update_reg( self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 ) def get_coding_scheme_warnings(self, silent=False): """Check if the coding scheme has detected any errors.""" + old_addr_reg = 0 + reg_value = 0 ret_fail = False for block in self.blocks: if block.id == 0: @@ -264,29 +251,22 @@ def get_coding_scheme_warnings(self, silent=False): self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) for offs in range(5) ] - data = BitArray() + block.err_bitarray.pos = 0 for word in reversed(words): - data.append("uint:32=%d" % word) - # pos=32 because EFUSE_WR_DIS goes first it is 32bit long - # and not under error control - block.err_bitarray.overwrite(data, pos=32) + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) block.num_errors = block.err_bitarray.count(True) block.fail = block.num_errors != 0 else: - addr_reg_f, fail_bit = self.REGS.BLOCK_FAIL_BIT[block.id] - if fail_bit is None: - block.fail = False - else: - block.fail = self.read_reg(addr_reg_f) & (1 << fail_bit) != 0 - - addr_reg_n, num_mask, num_offs = self.REGS.BLOCK_NUM_ERRORS[block.id] - if num_mask is None or num_offs is None: - block.num_errors = 0 - else: - block.num_errors = ( - self.read_reg(addr_reg_n) >> num_offs - ) & num_mask - + addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[ + block.id + ] + if err_num_mask is None or err_num_offs is None or fail_bit is None: + continue + if addr_reg != old_addr_reg: + old_addr_reg = addr_reg + reg_value = self.read_reg(addr_reg) + block.fail = reg_value & (1 << fail_bit) != 0 + block.num_errors = (reg_value >> err_num_offs) & err_num_mask ret_fail |= block.fail if not silent and (block.fail or block.num_errors): print( @@ -304,28 +284,13 @@ def summary(self): class EfuseField(base_fields.EfuseFieldBase): @staticmethod - def from_tuple(parent, efuse_tuple, type_class): + def convert(parent, efuse): return { "mac": EfuseMacField, "keypurpose": EfuseKeyPurposeField, "t_sensor": EfuseTempSensor, "adc_tp": EfuseAdcPointCalibration, - }.get(type_class, EfuseField)(parent, efuse_tuple) - - def get_info(self): - output = "%s (BLOCK%d)" % (self.name, self.block) - errs, fail = self.parent.get_block_errors(self.block) - if errs != 0 or fail: - output += ( - "[FAIL:%d]" % (fail) - if self.block == 0 - else "[ERRS:%d FAIL:%d]" % (errs, fail) - ) - if self.efuse_class == "keyblock": - name = self.parent.blocks[self.block].key_purpose_name - if name is not None: - output += "\n Purpose: %s\n " % (self.parent[name].get()) - return output + }.get(efuse.class_type, EfuseField)(parent, efuse) class EfuseTempSensor(EfuseField): @@ -349,23 +314,27 @@ def check_format(self, new_value_str): raise esptool.FatalError( "Required MAC Address in AA:CD:EF:01:02:03 format!" ) - if new_value_str.count(":") != 5: + num_bytes = 8 if self.name == "MAC_EUI64" else 6 + if new_value_str.count(":") != num_bytes - 1: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal format " + f"MAC Address needs to be a {num_bytes}-byte hexadecimal format " "separated by colons (:)!" ) - hexad = new_value_str.replace(":", "") - if len(hexad) != 12: + hexad = new_value_str.replace(":", "").split(" ", 1)[0] + hexad = hexad.split(" ", 1)[0] if self.is_field_calculated() else hexad + if len(hexad) != num_bytes * 2: raise esptool.FatalError( - "MAC Address needs to be a 6-byte hexadecimal number " - "(12 hexadecimal characters)!" + f"MAC Address needs to be a {num_bytes}-byte hexadecimal number " + f"({num_bytes * 2} hexadecimal characters)!" ) # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', bindata = binascii.unhexlify(hexad) - # unicast address check according to - # https://tools.ietf.org/html/rfc7042#section-2.1 - if esptool.util.byte(bindata, 0) & 0x01: - raise esptool.FatalError("Custom MAC must be a unicast MAC!") + + if not self.is_field_calculated(): + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") return bindata def check(self): @@ -379,6 +348,13 @@ def check(self): def get(self, from_read=True): if self.name == "CUSTOM_MAC": mac = self.get_raw(from_read)[::-1] + elif self.name == "MAC": + mac = self.get_raw(from_read) + elif self.name == "MAC_EUI64": + mac = self.parent["MAC"].get_bitstring(from_read).copy() + mac_ext = self.parent["MAC_EXT"].get_bitstring(from_read) + mac.insert(mac_ext, 24) + mac = mac.bytes else: mac = self.get_raw(from_read) return "%s %s" % (util.hexify(mac, ":"), self.check()) @@ -398,7 +374,7 @@ def print_field(e, new_value): else: # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, # as it's written in the factory. - raise esptool.FatalError("Writing Factory MAC address is not supported") + raise esptool.FatalError(f"Burning {self.name} is not supported") # fmt: off diff --git a/espefuse/efuse/esp32p4/mem_definition.py b/espefuse/efuse/esp32p4/mem_definition.py index eae160fe0..1d56f8d86 100644 --- a/espefuse/efuse/esp32p4/mem_definition.py +++ b/espefuse/efuse/esp32p4/mem_definition.py @@ -12,6 +12,7 @@ EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase, + Field, ) @@ -44,41 +45,37 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_PGM_CMD = 0x2 EFUSE_READ_CMD = 0x1 - # this chip has a design error so fail_bit is shifted by one block but err_num is in the correct place - BLOCK_FAIL_BIT = [ - # error_reg, fail_bit - (EFUSE_RD_REPEAT_ERR0_REG, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 7), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 11), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 15), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 19), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 23), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 27), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 31), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR1_REG, 3), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 7), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, None), # BLOCK_SYS_DATA2 - ] - - BLOCK_NUM_ERRORS = [ - # error_reg, err_num_mask, err_num_offs - (EFUSE_RD_REPEAT_ERR0_REG, None, None), # BLOCK0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 0), # MAC_SPI_8M_0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 4), # BLOCK_SYS_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 8), # BLOCK_USR_DATA - (EFUSE_RD_RS_ERR0_REG, 0x7, 12), # BLOCK_KEY0 - (EFUSE_RD_RS_ERR0_REG, 0x7, 16), # BLOCK_KEY1 - (EFUSE_RD_RS_ERR0_REG, 0x7, 20), # BLOCK_KEY2 - (EFUSE_RD_RS_ERR0_REG, 0x7, 24), # BLOCK_KEY3 - (EFUSE_RD_RS_ERR0_REG, 0x7, 28), # BLOCK_KEY4 - (EFUSE_RD_RS_ERR1_REG, 0x7, 0), # BLOCK_KEY5 - (EFUSE_RD_RS_ERR1_REG, 0x7, 4), # BLOCK_SYS_DATA2 + BLOCK_ERRORS = [ + # error_reg, err_num_mask, err_num_offs, fail_bit + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 ] # EFUSE_WR_TIM_CONF2_REG EFUSE_PWR_OFF_NUM_S = 0 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + class EfuseDefineBlocks(EfuseBlocksBase): __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE @@ -155,6 +152,16 @@ def __init__(self) -> None: self.BLOCK2_CALIBRATION_EFUSES.append(efuse) self.ALL_EFUSES[i] = None + f = Field() + f.name = "MAC_EUI64" + f.block = 1 + f.bit_len = 64 + f.type = f"bytes:{f.bit_len // 8}" + f.category = "MAC" + f.class_type = "mac" + f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" + self.CALC.append(f) + for efuse in self.ALL_EFUSES: if efuse is not None: self.EFUSES.append(efuse) diff --git a/espefuse/efuse/esp32p4/operations.py b/espefuse/efuse/esp32p4/operations.py index 271584ffc..87f5f9c8f 100644 --- a/espefuse/efuse/esp32p4/operations.py +++ b/espefuse/efuse/esp32p4/operations.py @@ -1,8 +1,6 @@ -#!/usr/bin/env python -# # This file includes the operations with eFuses for ESP32-P4 chip # -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later @@ -19,6 +17,7 @@ from ..base_operations import ( add_common_commands, add_force_write_always, + add_show_sensitive_info_option, burn_bit, burn_block_data, burn_efuse, @@ -57,6 +56,7 @@ def add_commands(subparsers, efuses): ) protect_options(burn_key) add_force_write_always(burn_key) + add_show_sensitive_info_option(burn_key) burn_key.add_argument( "block", help="Key block to burn", @@ -107,6 +107,7 @@ def add_commands(subparsers, efuses): ) protect_options(burn_key_digest) add_force_write_always(burn_key_digest) + add_show_sensitive_info_option(burn_key_digest) burn_key_digest.add_argument( "block", help="Key block to burn", @@ -175,15 +176,11 @@ def add_commands(subparsers, efuses): def burn_custom_mac(esp, efuses, args): - efuses["CUSTOM_MAC"].save(args.mac) - if not efuses.burn_all(check_batch_mode=True): - return - get_custom_mac(esp, efuses, args) - print("Successful") + print("Not supported yet") def get_custom_mac(esp, efuses, args): - print("Custom MAC Address: {}".format(efuses["CUSTOM_MAC"].get())) + print("Not supported yet") def set_flash_voltage(esp, efuses, args): @@ -244,7 +241,13 @@ def burn_key(esp, efuses, args, digest=None): if efuses[block.key_purpose_name].need_reverse(keypurpose): revers_msg = "\tReversing byte order for AES-XTS hardware peripheral" data = data[::-1] - print("-> [%s]" % (util.hexify(data, " "))) + print( + "-> [{}]".format( + util.hexify(data, " ") + if args.show_sensitive_info + else " ".join(["??"] * len(data)) + ) + ) if revers_msg: print(revers_msg) if len(data) != num_bytes: diff --git a/espefuse/efuse_defs/esp32p4.yaml b/espefuse/efuse_defs/esp32p4.yaml index 895751a8a..fe10b2eda 100644 --- a/espefuse/efuse_defs/esp32p4.yaml +++ b/espefuse/efuse_defs/esp32p4.yaml @@ -1,28 +1,31 @@ -VER_NO: 4df10f83de85f2d830b7c466aabb28e7 +VER_NO: 95ae7b662df04208c40c69564ea06a28 EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} - RPT4_RESERVED0_4 : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} - DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} - DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} - POWERGLITCH_EN : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether power glitch function is enabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} - DIS_USB_SERIAL_JTAG : {show: n, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} - DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} - SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} - DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} - JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} - SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} - DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} - DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} - USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} - USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} - USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} - VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} - RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} - RPT4_RESERVED0_1 : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} - RPT4_RESERVED0_0 : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} - RPT4_RESERVED1_1 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'} - WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + USB_DEVICE_EXCHG_PINS : {show: y, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Enable usb device exchange pins of D+ and D-, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + USB_OTG11_EXCHG_PINS : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Enable usb otg11 exchange pins of D+ and D-, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + POWERGLITCH_EN : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether power glitch function is enabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: n, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DEVICE_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: USB intphy of usb device signle-end input high threshold; 1.76V to 2V. Step by 80mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_OTG11_DREFH : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: USB intphy of usb otg11 signle-end input high threshold; 1.76V to 2V. Step by 80mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_PHY_SEL : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + KM_HUK_GEN_STATE_LOW : {show: y, blk : 0, word: 1, pos: 26, len : 6, start : 58, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:26]', bloc: 'B7[7:2]'} + KM_HUK_GEN_STATE_HIGH : {show: y, blk : 0, word: 2, pos : 0, len : 3, start : 64, type : 'uint:3', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[2:0]', bloc: 'B8[2:0]'} + KM_RND_SWITCH_CYCLE : {show: y, blk : 0, word: 2, pos : 3, len : 2, start : 67, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[4:3]', bloc: 'B8[4:3]'} + KM_DEPLOY_ONLY_ONCE : {show: y, blk : 0, word: 2, pos : 5, len : 4, start : 69, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[8:5]', bloc: 'B8[7:5],B9[0]'} + FORCE_USE_KEY_MANAGER_KEY : {show: y, blk : 0, word: 2, pos : 9, len : 4, start : 73, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[12:9]', bloc: 'B9[4:1]'} + FORCE_DISABLE_SW_INIT_KEY : {show: y, blk : 0, word: 2, pos: 13, len : 1, start : 77, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable software written init key; and force use efuse_init_key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[13]', bloc: 'B9[5]'} + XTS_KEY_LENGTH_256 : {show: y, blk : 0, word: 2, pos: 14, len : 1, start : 78, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to configure flash encryption use xts-128 key; else use xts-256 key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[14]', bloc: 'B9[6]'} + RESERVE_0_79 : {show: n, blk : 0, word: 2, pos: 15, len : 1, start : 79, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15]', bloc: 'B9[7]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} @@ -33,56 +36,52 @@ EFUSES: KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} - SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} - ECDSA_FORCE_USE_HARDWARE_K : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} - CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} - SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} - SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} - RPT4_RESERVED2_0 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} - FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} - DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} - DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} - DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: Set this bit to disable USB-Serial-JTAG print during rom boot, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} - RPT4_RESERVED3_5 : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} - ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} - UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} - FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} - SECURE_VERSION : {show: y, blk : 0, word: 4, pos : 9, len : 16, start: 137, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[24:9]', bloc: 'B17[7:1],B18,B19[0]'} - SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 25, len : 1, start: 153, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'} - HYS_EN_PAD0 : {show: y, blk : 0, word: 4, pos: 26, len : 6, start: 154, type : 'uint:6', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Set bits to enable hysteresis function of PAD0~5, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:26]', bloc: 'B19[7:2]'} - HYS_EN_PAD1 : {show: y, blk : 0, word: 5, pos : 0, len : 22, start: 160, type : 'uint:22', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Set bits to enable hysteresis function of PAD6~27, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[21:0]', bloc: 'B20,B21,B22[5:0]'} - RPT4_RESERVED4_1 : {show: n, blk : 0, word: 5, pos: 22, len : 2, start: 182, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:22]', bloc: 'B22[7:6]'} - RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} + ECDSA_ENABLE_SOFT_K : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} + CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RESERVE_0_118 : {show: n, blk : 0, word: 3, pos: 22, len : 1, start: 118, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[22]', bloc: 'B14[6]'} + FLASH_TYPE : {show: y, blk : 0, word: 3, pos: 23, len : 1, start: 119, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'The type of interfaced flash. 0: four data lines; 1: eight data lines', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23]', bloc: 'B14[7]'} + FLASH_PAGE_SIZE : {show: y, blk : 0, word: 3, pos: 24, len : 2, start: 120, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set flash page size, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[25:24]', bloc: 'B15[1:0]'} + FLASH_ECC_EN : {show: y, blk : 0, word: 3, pos: 26, len : 1, start: 122, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to enable ecc for flash boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26]', bloc: 'B15[2]'} + DIS_USB_OTG_DOWNLOAD_MODE : {show: y, blk : 0, word: 3, pos: 27, len : 1, start: 123, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable download via USB-OTG, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27]', bloc: 'B15[3]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + LOCK_KM_KEY : {show: y, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos : 9, len : 16, start: 137, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[24:9]', bloc: 'B17[7:1],B18,B19[0]'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 25, len : 1, start: 153, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'} + HYS_EN_PAD : {show: y, blk : 0, word: 4, pos: 26, len : 1, start: 154, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[26]', bloc: 'B19[2]'} + DCDC_VSET : {show: y, blk : 0, word: 4, pos: 27, len : 5, start: 155, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set the dcdc voltage default, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:27]', bloc: 'B19[7:3]'} + PXA0_TIEH_SEL_0 : {show: y, blk : 0, word: 5, pos : 0, len : 2, start: 160, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_0, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1:0]', bloc: 'B20[1:0]'} + PXA0_TIEH_SEL_1 : {show: y, blk : 0, word: 5, pos : 2, len : 2, start: 162, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_1, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[3:2]', bloc: 'B20[3:2]'} + PXA0_TIEH_SEL_2 : {show: y, blk : 0, word: 5, pos : 4, len : 2, start: 164, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_2, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[5:4]', bloc: 'B20[5:4]'} + PXA0_TIEH_SEL_3 : {show: y, blk : 0, word: 5, pos : 6, len : 2, start: 166, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_3, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[7:6]', bloc: 'B20[7:6]'} + KM_DISABLE_DEPLOY_MODE : {show: y, blk : 0, word: 5, pos : 8, len : 4, start: 168, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[11:8]', bloc: 'B21[3:0]'} + USB_DEVICE_DREFL : {show: n, blk : 0, word: 5, pos: 12, len : 2, start: 172, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb device single-end input low threhold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13:12]', bloc: 'B21[5:4]'} + USB_OTG11_DREFL : {show: n, blk : 0, word: 5, pos: 14, len : 2, start: 174, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb otg11 single-end input low threhold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[15:14]', bloc: 'B21[7:6]'} + RESERVE_0_176 : {show: n, blk : 0, word: 5, pos: 16, len : 2, start: 176, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[17:16]', bloc: 'B22[1:0]'} + HP_PWR_SRC_SEL : {show: y, blk : 0, word: 5, pos: 18, len : 1, start: 178, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'HP system power source select. 0:LDO. 1: DCDC', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[18]', bloc: 'B22[2]'} + DCDC_VSET_EN : {show: y, blk : 0, word: 5, pos: 19, len : 1, start: 179, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Select dcdc vset use efuse_dcdc_vset, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[19]', bloc: 'B22[3]'} + DIS_WDT : {show: y, blk : 0, word: 5, pos: 20, len : 1, start: 180, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable watch dog, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[20]', bloc: 'B22[4]'} + DIS_SWD : {show: y, blk : 0, word: 5, pos: 21, len : 1, start: 181, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable super-watchdog, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[21]', bloc: 'B22[5]'} + RESERVE_0_182 : {show: n, blk : 0, word: 5, pos: 22, len : 10, start: 182, type : 'uint:10', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:22]', bloc: 'B22[7:6],B23'} MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'} - RXIQ_VERSION : {show: y, blk : 1, word: 2, pos : 0, len : 3, start : 64, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[2:0]', bloc: 'B8[2:0]'} - RXIQ_0 : {show: y, blk : 1, word: 2, pos : 3, len : 7, start : 67, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 0, rloc: 'EFUSE_RD_MAC_SYS_2_REG[9:3]', bloc: 'B8[7:3],B9[1:0]'} - RXIQ_1 : {show: y, blk : 1, word: 2, pos: 10, len : 7, start : 74, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 1, rloc: 'EFUSE_RD_MAC_SYS_2_REG[16:10]', bloc: 'B9[7:2],B10[0]'} - RESERVED_1_81 : {show: n, blk : 1, word: 2, pos: 17, len : 15, start : 81, type : 'uint:15', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:17]', bloc: 'B10[7:1],B11'} + MAC_RESERVED_1 : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} + MAC_RESERVED_0 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} - WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} - WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 21, len : 2, start: 117, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[22:21]', bloc: 'B14[6:5]'} - DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 23, len : 1, start: 119, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_MAC_SYS_3_REG[23]', bloc: 'B14[7]'} - FLASH_CAP : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} - FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[28:27]', bloc: 'B15[4:3]'} - FLASH_VENDOR : {show: y, blk : 1, word: 3, pos: 29, len : 3, start: 125, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:29]', bloc: 'B15[7:5]'} - PKG_VERSION : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} - RESERVED_1_131 : {show: n, blk : 1, word: 4, pos : 3, len : 29, start: 131, type : 'uint:29', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_4_REG[31:3]', bloc: 'B16[7:3],B17,B18,B19'} + SYS_DATA_PART0_0 : {show: n, blk : 1, word: 3, pos: 18, len : 14, start: 114, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first 14 bits of the zeroth part of system data, rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:18]', bloc: 'B14[7:2],B15'} + SYS_DATA_PART0_1 : {show: n, blk : 1, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_4_REG, bloc: 'B16,B17,B18,B19'} SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_5_REG, bloc: 'B20,B21,B22,B23'} - OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} - RESERVED_2_128 : {show: n, blk : 2, word: 4, pos : 0, len : 2, start: 128, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[1:0]', bloc: 'B16[1:0]'} - BLK_VERSION_MINOR : {show: y, blk : 2, word: 4, pos : 2, len : 3, start: 130, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: 'BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1', rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[4:2]', bloc: 'B16[4:2]'} - BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 5, len : 2, start: 133, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[6:5]', bloc: 'B16[6:5]'} - DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 7, len : 1, start: 135, type : bool, wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[7]', bloc: 'B16[7]'} - RESERVED_2_136 : {show: n, blk : 2, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:8]', bloc: 'B17,B18,B19'} - SYS_DATA_PART1_5 : {show: n, blk : 2, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the fifth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA5_REG, bloc: 'B20,B21,B22,B23'} - SYS_DATA_PART1_6 : {show: n, blk : 2, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the sixth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA6_REG, bloc: 'B24,B25,B26,B27'} - SYS_DATA_PART1_7 : {show: n, blk : 2, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the seventh 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA7_REG, bloc: 'B28,B29,B30,B31'} - BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} - RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} - CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} - RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_SYS_DATA1 : {show: y, blk : 2, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 21, rd_dis: null, alt : SYS_DATA_PART1, dict : '', desc: System data part 1, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 770a82576..3d83e86a3 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -180,6 +180,9 @@ def test_summary(self): def test_summary_json(self): self.espefuse_py("summary --format json") + @pytest.mark.skipif( + arg_chip == "esp32p4", reason="No Custom MAC Address defined yet" + ) def test_get_custom_mac(self): self.espefuse_py("get_custom_mac -h") if arg_chip == "esp32": @@ -343,6 +346,10 @@ def test_write_protect_efuse(self): efuse_lists = """RD_DIS DIS_DOWNLOAD_ICACHE XTS_KEY_LENGTH_256 UART_PRINT_CONTROL""" efuse_lists2 = "RD_DIS DIS_DOWNLOAD_ICACHE" + elif arg_chip == "esp32p4": + efuse_lists = """RD_DIS KEY_PURPOSE_0 SECURE_BOOT_KEY_REVOKE0 + SPI_BOOT_CRYPT_CNT""" + efuse_lists2 = "RD_DIS KEY_PURPOSE_0 KEY_PURPOSE_2" else: efuse_lists = """RD_DIS DIS_ICACHE DIS_FORCE_DOWNLOAD DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT @@ -380,6 +387,7 @@ def test_write_protect_efuse2(self): ) +@pytest.mark.skipif(arg_chip == "esp32p4", reason="No Custom MAC Address defined yet") class TestBurnCustomMacCommands(EfuseTestCase): def test_burn_custom_mac(self): self.espefuse_py("burn_custom_mac -h") @@ -617,6 +625,9 @@ def test_set_spi_flash_pin_efuses(self): assert "(Override SD_CMD pad (GPIO11/SPICS0)) 0b00000 -> 0b11111" in output assert "BURN BLOCK0 - OK (all write block bits are set)" in output + @pytest.mark.skipif( + arg_chip == "esp32p4", reason="No Custom MAC Address defined yet" + ) def test_burn_mac_custom_efuse(self): crc_msg = "(OK)" self.espefuse_py("burn_efuse -h") @@ -639,6 +650,9 @@ def test_burn_mac_custom_efuse(self): self.espefuse_py("burn_efuse CUSTOM_MAC AA:CD:EF:01:02:03") self.espefuse_py("get_custom_mac", check_msg=f"aa:cd:ef:01:02:03 {crc_msg}") + @pytest.mark.skipif( + arg_chip == "esp32p4", reason="No such eFuses, will be defined later" + ) def test_burn_efuse(self): self.espefuse_py("burn_efuse -h") if arg_chip == "esp32": @@ -1742,14 +1756,20 @@ def teardown_class(self): # Restore the stored working directory os.chdir(self.stored_dir) - @pytest.mark.skipif(arg_chip == "esp32c2", reason="TODO: Add tests for esp32c2") + @pytest.mark.skipif( + arg_chip in ["esp32c2", "esp32p4"], + reason="These chips do not have eFuses used in this test", + ) def test_execute_scripts_with_check_that_only_one_burn(self): self.espefuse_py("execute_scripts -h") name = arg_chip if arg_chip in ["esp32", "esp32c2"] else "esp32xx" os.chdir(os.path.join(TEST_DIR, "efuse_scripts", name)) self.espefuse_py("execute_scripts execute_efuse_script2.py") - @pytest.mark.skipif(arg_chip == "esp32c2", reason="TODO: Add tests for esp32c2") + @pytest.mark.skipif( + arg_chip in ["esp32c2", "esp32p4"], + reason="These chips do not have eFuses used in this test", + ) def test_execute_scripts_with_check(self): self.espefuse_py("execute_scripts -h") name = arg_chip if arg_chip in ["esp32", "esp32c2"] else "esp32xx" From e81992715bb865bade9e662f5edfa36d0cb32cb4 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 8 Aug 2023 13:44:46 +0200 Subject: [PATCH 056/209] fix: Fix redirection of STDOUT Closes https://github.com/espressif/esptool/issues/904 --- esptool/util.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/util.py b/esptool/util.py index 91e4ee16b..ecd41c0d9 100644 --- a/esptool/util.py +++ b/esptool/util.py @@ -68,7 +68,7 @@ def print_overwrite(message, last_line=False): If output is not a TTY (for example redirected a pipe), no overwriting happens and this function is the same as print(). """ - if sys.stdout.isatty(): + if hasattr(sys.stdout, "isatty") and sys.stdout.isatty(): print("\r%s" % message, end="\n" if last_line else "") else: print(message) From 96dd81aeedd87455d91494903294dd62d203778a Mon Sep 17 00:00:00 2001 From: Tomas Sebestik Date: Tue, 22 Aug 2023 14:30:36 +0200 Subject: [PATCH 057/209] fix(danger-github): Fir Danger GitHub token permission --- .github/workflows/dangerjs.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml index ea1c08b8d..5a1c9fc19 100644 --- a/.github/workflows/dangerjs.yml +++ b/.github/workflows/dangerjs.yml @@ -5,7 +5,7 @@ on: permissions: pull-requests: write - contents: write + statuses: write jobs: pull-request-style-linter: From 10fbb4b6c70c1ae0018e2ed74a261e6364af6a3c Mon Sep 17 00:00:00 2001 From: Tomas Sebestik Date: Wed, 23 Aug 2023 13:01:38 +0200 Subject: [PATCH 058/209] ci(danger-github): Fix github-action-bot permissions for posting Danger output --- .github/workflows/dangerjs.yml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml index 5a1c9fc19..ab9f002a6 100644 --- a/.github/workflows/dangerjs.yml +++ b/.github/workflows/dangerjs.yml @@ -1,18 +1,21 @@ name: DangerJS Check on: - pull_request: + pull_request_target: types: [opened, edited, reopened, synchronize] permissions: pull-requests: write - statuses: write + contents: write jobs: pull-request-style-linter: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v3 - + - name: Check out PR head + uses: actions/checkout@v3 + with: + ref: ${{ github.event.pull_request.head.sha }} + - name: DangerJS pull request linter uses: espressif/github-actions/danger_pr_review@master env: From 2714ebe08324514ea8efd6854ea7f3379bfcf3fa Mon Sep 17 00:00:00 2001 From: Tomas Sebestik Date: Wed, 23 Aug 2023 13:49:48 +0200 Subject: [PATCH 059/209] ci: Shared danger to local stage (remove possible double CI pipelines) --- .gitlab-ci.yml | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4fca1f1ee..a7c8fb35c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,10 +1,13 @@ # Gitlab CI config # # Note: When updating, please also update test_esptool.yml GH Actions workflow file -include: - - project: 'espressif/shared-ci-dangerjs' - ref: master - file: 'danger.yaml' +stages: + - pre-check + - test + - report + - build_docs + - deploy_docs + - deploy_development_package workflow: rules: @@ -13,13 +16,12 @@ workflow: when: never - if: '$CI_COMMIT_BRANCH' -stages: - - danger - - test - - report - - build_docs - - deploy_docs - - deploy_development_package +include: + - project: espressif/shared-ci-dangerjs + ref: master + file: danger.yaml +run-danger-mr-linter: + stage: pre-check # cache the pip download directory in all jobs variables: From b0a3968aac274b23ea6dbf130fe418f65a88e475 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 25 Aug 2023 13:14:02 +0200 Subject: [PATCH 060/209] ci: add 'flake8-import-order' as a dependecy to flake8 --- .pre-commit-config.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index fa6705f9a..f2fdbc737 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -3,6 +3,7 @@ repos: rev: 4.0.1 hooks: - id: flake8 + additional_dependencies: [flake8-import-order] - repo: https://github.com/psf/black rev: 22.3.0 hooks: @@ -12,4 +13,5 @@ repos: hooks: - id: conventional-precommit-linter stages: [commit-msg] +default_stages: [commit] default_install_hook_types: [pre-commit, commit-msg] From 7b547c9e07db78ba58b60192c32e11f5266306e9 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 12 Sep 2023 13:37:08 +0200 Subject: [PATCH 061/209] fix(bin_image): Check only ELF sections when searching for .flash.appdesc Closes https://github.com/espressif/esptool/issues/917 --- esptool/bin_image.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index c6ed200b7..fc3872b13 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -648,10 +648,10 @@ def save(self, filename): if not self.is_flash_addr(s.addr) ] - # Patch to support 761 union bus memmap // TODO: ESPTOOL-512 + # Patch to support ESP32-C6 union bus memmap # move ".flash.appdesc" segment to the top of the flash segment for segment in flash_segments: - if segment.name == ".flash.appdesc": + if isinstance(segment, ELFSection) and segment.name == ".flash.appdesc": flash_segments.remove(segment) flash_segments.insert(0, segment) break From d1d9cfc92b9dcaa9b9da1baa278eab0c749ce523 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Wed, 23 Aug 2023 17:57:26 +0800 Subject: [PATCH 062/209] feat(efuse): ESP32P4 adds ecdsa_key support --- espefuse/efuse/esp32p4/fields.py | 7 ++++++- espefuse/efuse/esp32p4/operations.py | 15 +++++++++++---- test/test_espefuse.py | 13 ++++++++++--- 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py index 44c813060..e0270d5a4 100644 --- a/espefuse/efuse/esp32p4/fields.py +++ b/espefuse/efuse/esp32p4/fields.py @@ -381,7 +381,7 @@ def print_field(e, new_value): class EfuseKeyPurposeField(EfuseField): KEY_PURPOSES = [ ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) - ("RESERVED", 1, None, None, "no_need_rd_protect"), # Reserved + ("ECDSA_KEY", 1, None, "Reverse", "need_rd_protect"), # ECDSA key ("XTS_AES_256_KEY_1", 2, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_1 (flash/PSRAM encryption) ("XTS_AES_256_KEY_2", 3, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_2 (flash/PSRAM encryption) ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) @@ -428,6 +428,11 @@ def get(self, from_read=True): return p[0] return "FORBIDDEN_STATE" + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + def save(self, new_value): raw_val = int(self.check_format(str(new_value))) return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32p4/operations.py b/espefuse/efuse/esp32p4/operations.py index 87f5f9c8f..093a04802 100644 --- a/espefuse/efuse/esp32p4/operations.py +++ b/espefuse/efuse/esp32p4/operations.py @@ -65,7 +65,7 @@ def add_commands(subparsers, efuses): ) burn_key.add_argument( "keyfile", - help="File containing 256 bits of binary key data", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", action="append", type=argparse.FileType("rb"), ) @@ -86,7 +86,7 @@ def add_commands(subparsers, efuses): ) burn_key.add_argument( "keyfile", - help="File containing 256 bits of binary key data", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", nargs="?", action="append", metavar="KEYFILE", @@ -232,14 +232,21 @@ def burn_key(esp, efuses, args, digest=None): block = efuses.blocks[block_num] if digest is None: - data = datafile.read() + if keypurpose == "ECDSA_KEY": + sk = espsecure.load_ecdsa_signing_key(datafile) + data = sk.to_string() + if len(data) == 24: + # the private key is 24 bytes long for NIST192p, add 8 bytes of padding + data = b"\x00" * 8 + data + else: + data = datafile.read() else: data = datafile print(" - %s" % (efuse.name), end=" ") revers_msg = None if efuses[block.key_purpose_name].need_reverse(keypurpose): - revers_msg = "\tReversing byte order for AES-XTS hardware peripheral" + revers_msg = f"\tReversing byte order for {keypurpose} hardware peripheral" data = data[::-1] print( "-> [{}]".format( diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 3d83e86a3..07597b4d1 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -280,9 +280,10 @@ def test_read_protect_efuse4(self): ret_code=2, ) else: + key1_purpose = "USER" if arg_chip in ["esp32p4"] else "RESERVED" self.espefuse_py( f"burn_key BLOCK_KEY0 {IMAGES_DIR}/256bit USER \ - BLOCK_KEY1 {IMAGES_DIR}/256bit RESERVED \ + BLOCK_KEY1 {IMAGES_DIR}/256bit {key1_purpose} \ BLOCK_KEY2 {IMAGES_DIR}/256bit SECURE_BOOT_DIGEST0 \ BLOCK_KEY3 {IMAGES_DIR}/256bit SECURE_BOOT_DIGEST1 \ BLOCK_KEY4 {IMAGES_DIR}/256bit SECURE_BOOT_DIGEST2 \ @@ -1054,7 +1055,10 @@ def test_burn_key_512bit_non_consecutive_blocks_loop_around(self): "acadaeaf a8a9aaab a4a5a6a7 22a1a2a3" ) in output - @pytest.mark.skipif(arg_chip != "esp32h2", reason="Only for ESP32-H2 chips") + @pytest.mark.skipif( + arg_chip not in ["esp32h2", "esp32p4"], + reason="These chips support ECDSA_KEY", + ) def test_burn_key_ecdsa_key(self): self.espefuse_py( f"burn_key \ @@ -1077,7 +1081,10 @@ def test_burn_key_ecdsa_key(self): "00000000 00000000 00000000 00000000" ) in output - @pytest.mark.skipif(arg_chip != "esp32h2", reason="Only for ESP32-H2 chips") + @pytest.mark.skipif( + arg_chip not in ["esp32h2", "esp32p4"], + reason="These chips support ECDSA_KEY", + ) def test_burn_key_ecdsa_key_check_byte_order(self): self.espefuse_py( f"burn_key \ From aa22553daa82d129d4f4c67cb3a96d953d8a5ccf Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Tue, 12 Sep 2023 19:26:01 +0800 Subject: [PATCH 063/209] feat(efuse): Update key purpose table and tests --- espefuse/efuse/esp32p4/fields.py | 13 ++----------- test/test_espefuse.py | 2 +- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py index e0270d5a4..d88b59272 100644 --- a/espefuse/efuse/esp32p4/fields.py +++ b/espefuse/efuse/esp32p4/fields.py @@ -228,17 +228,7 @@ def set_efuse_timing(self): raise esptool.FatalError( "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq ) - - self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) - self.update_reg( - self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 - ) - self.update_reg( - self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 - ) - self.update_reg( - self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 - ) + # keep default timing settings def get_coding_scheme_warnings(self, silent=False): """Check if the coding scheme has detected any errors.""" @@ -392,6 +382,7 @@ class EfuseKeyPurposeField(EfuseField): ("SECURE_BOOT_DIGEST0", 9, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST0 (Secure Boot key digest) ("SECURE_BOOT_DIGEST1", 10, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST1 (Secure Boot key digest) ("SECURE_BOOT_DIGEST2", 11, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST2 (Secure Boot key digest) + ("KM_INIT_KEY", 12, None, None, "need_rd_protect"), # init key that is used for the generation of AES/ECDSA key ] # fmt: on KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 07597b4d1..cb8ada0d0 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -886,7 +886,7 @@ def test_burn_key_with_6_keys(self): BLOCK_KEY0 {IMAGES_DIR}/256bit XTS_AES_256_KEY_1 \ BLOCK_KEY1 {IMAGES_DIR}/256bit_1 XTS_AES_256_KEY_2 \ BLOCK_KEY2 {IMAGES_DIR}/256bit_2 XTS_AES_128_KEY" - if arg_chip in ["esp32c3", "esp32c6", "esp32p4"] or arg_chip in [ + if arg_chip in ["esp32c3", "esp32c6"] or arg_chip in [ "esp32h2", "esp32h2beta1", ]: From 31e08c64775bcdbc63379d92cdaebb7a79052cce Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 6 Sep 2023 13:44:42 +0200 Subject: [PATCH 064/209] feat(esp32-s3): Support >16MB quad flash chips Adds support for the W25Q256 and GD25Q256 flash chips. Closes https://github.com/espressif/esptool/issues/883 --- .gitlab-ci.yml | 13 +++++++-- esptool/__init__.py | 8 ++++-- .../stub_flasher/stub_flasher_32s3.json | 8 +++--- .../stub_flasher/stub_flasher_32s3beta2.json | 2 +- flasher_stub/include/stub_flasher.h | 10 +++---- flasher_stub/stub_commands.c | 10 +++---- flasher_stub/stub_flasher.c | 28 +++++++++++++++++-- flasher_stub/stub_write_flash.c | 6 ++-- 8 files changed, 59 insertions(+), 26 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a7c8fb35c..4f9afaf79 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -291,10 +291,19 @@ target_esp32s3: script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32S3 --chip esp32s3 --baud 115200 -target_esp32s3_32MB: +target_esp32s3_32MB_octal: extends: .target_esptool_test tags: - - esptool_esp32s3_32MB_target + - esptool_esp32s3_32MB_octal_target + variables: + ESPTOOL_TEST_FLASH_SIZE: "32" + script: + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32S3_32MB --chip esp32s3 --baud 115200 + +target_esp32s3_32MB_quad: + extends: .target_esptool_test + tags: + - esptool_esp32s3_32MB_quad_target variables: ESPTOOL_TEST_FLASH_SIZE: "32" script: diff --git a/esptool/__init__.py b/esptool/__init__.py index 0e8569497..4d015daea 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -834,7 +834,11 @@ def flash_xmc_startup(): if flash_size is not None: # Secure download mode esp.flash_set_parameters(flash_size_bytes(flash_size)) # Check if stub supports chosen flash size - if esp.IS_STUB and flash_size in ("32MB", "64MB", "128MB"): + if ( + esp.IS_STUB + and esp.CHIP_NAME != "ESP32-S3" + and flash_size_bytes(flash_size) > 16 * 1024 * 1024 + ): print( "WARNING: Flasher stub doesn't fully support flash size larger " "than 16MB, in case of failure use --no-stub." @@ -858,7 +862,7 @@ def flash_xmc_startup(): args.size = flash_size_bytes(size_str) if esp.IS_STUB and hasattr(args, "address") and hasattr(args, "size"): - if args.address + args.size > 0x1000000: + if esp.CHIP_NAME != "ESP32-S3" and args.address + args.size > 0x1000000: print( "WARNING: Flasher stub doesn't fully support flash size larger " "than 16MB, in case of failure use --no-stub." diff --git a/esptool/targets/stub_flasher/stub_flasher_32s3.json b/esptool/targets/stub_flasher/stub_flasher_32s3.json index a501e2f2b..5435ea6d0 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32s3.json +++ b/esptool/targets/stub_flasher/stub_flasher_32s3.json @@ -1,7 +1,7 @@ { - "entry": 1077381696, - "text": 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"text_start": 1077379072, "data": "WADKP7uLN0BPjDdAHJE3QNuMN0BvjDdA24w3QDqNN0AHjjdAeY43QCKON0BFizdAm403QPmNN0BdjTdAnI43QIaNN0CcjjdAPYw3QJyMN0DbjDdAOo03QFWMN0CHizdAYI83QOKQN0BeijdAApE3QF6KN0BeijdAXoo3QF6KN0BeijdAXoo3QF6KN0BeijdA+443QF6KN0D1jzdA4pA3QA==", "data_start": 1070279668 diff --git a/flasher_stub/include/stub_flasher.h b/flasher_stub/include/stub_flasher.h index 79b8a24d8..3cf1f6310 100644 --- a/flasher_stub/include/stub_flasher.h +++ b/flasher_stub/include/stub_flasher.h @@ -6,9 +6,8 @@ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD */ -#ifndef STUB_FLASHER_H_ -#define STUB_FLASHER_H_ - +#pragma once +#include #include /* Maximum write block size, used for various buffers. */ @@ -22,8 +21,9 @@ #define SECTORS_PER_BLOCK (FLASH_BLOCK_SIZE / FLASH_SECTOR_SIZE) /* 32-bit addressing is supported only by ESP32S3 */ -#if defined(ESP32S3) +#if defined(ESP32S3) && !defined(ESP32S3BETA2) #define FLASH_MAX_SIZE 64*1024*1024 +extern bool large_flash_mode; #else #define FLASH_MAX_SIZE 16*1024*1024 #endif @@ -108,5 +108,3 @@ typedef enum { ESP_CMD_NOT_IMPLEMENTED = 0xFF, } esp_command_error; - -#endif /* STUB_FLASHER_H_ */ diff --git a/flasher_stub/stub_commands.c b/flasher_stub/stub_commands.c index 169c266b9..041b2bab1 100644 --- a/flasher_stub/stub_commands.c +++ b/flasher_stub/stub_commands.c @@ -49,7 +49,7 @@ int handle_flash_erase(uint32_t addr, uint32_t len) { while (len > 0 && (addr % FLASH_BLOCK_SIZE != 0)) { #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode) { if (esp_rom_opiflash_erase_sector(addr / FLASH_SECTOR_SIZE) != 0) return 0x35; } else { if (SPIEraseSector(addr / FLASH_SECTOR_SIZE) != 0) return 0x35; @@ -63,7 +63,7 @@ int handle_flash_erase(uint32_t addr, uint32_t len) { while (len > FLASH_BLOCK_SIZE) { #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode) { if (esp_rom_opiflash_erase_block_64k(addr / FLASH_BLOCK_SIZE) != 0) return 0x36; } else { if (SPIEraseBlock(addr / FLASH_BLOCK_SIZE) != 0) return 0x36; @@ -77,7 +77,7 @@ int handle_flash_erase(uint32_t addr, uint32_t len) { while (len > 0) { #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode) { if (esp_rom_opiflash_erase_sector(addr / FLASH_SECTOR_SIZE) != 0) return 0x37; } else { if (SPIEraseSector(addr / FLASH_SECTOR_SIZE) != 0) return 0x37; @@ -112,7 +112,7 @@ void handle_flash_read(uint32_t addr, uint32_t len, uint32_t block_size, uint32_t n = len - num_sent; if (n > block_size) n = block_size; #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode) { res = SPIRead4B(1, addr, buf, n); } else { res = SPIRead(addr, (uint32_t *)buf, n); @@ -152,7 +152,7 @@ int handle_flash_get_md5sum(uint32_t addr, uint32_t len) { n = FLASH_SECTOR_SIZE; } #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode) { res = SPIRead4B(1, addr, buf, n); } else { res = SPIRead(addr, (uint32_t *)buf, n); diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c index bcbbd55eb..1ee47b1ee 100644 --- a/flasher_stub/stub_flasher.c +++ b/flasher_stub/stub_flasher.c @@ -123,6 +123,26 @@ static void disable_watchdogs() } #endif // WITH_USB_JTAG_SERIAL +#if ESP32S3 && !ESP32S3BETA2 +bool large_flash_mode = false; + +bool flash_larger_than_16mb() +{ + uint32_t flash_id; + esp_rom_opiflash_exec_cmd(1, SPI_FLASH_FASTRD_MODE, + CMD_RDID, 8, + 0, 0, + 0, + NULL, 0, + (uint8_t *)&flash_id, 24, + ESP_ROM_OPIFLASH_SEL_CS0, + false); + + uint8_t flid_lowbyte = (flash_id >> 16) & 0xFF; + return ((flid_lowbyte >= 0x19 && flid_lowbyte < 0x30) || (flid_lowbyte >= 0x39)); // See DETECTED_FLASH_SIZES in esptool +} +#endif // ESP32S3 + static void stub_handle_rx_byte(char byte) { int16_t r = SLIP_recv_byte(byte, (slip_state_t *)&ub.state); @@ -490,9 +510,11 @@ void stub_main() spi_flash_attach(spiconfig, 0); #endif #if ESP32S3 && !ESP32S3BETA2 - // Initialize OPI flash driver only when flash is detected octal. Otherwise, we don't need to - // initialize such a driver - if (ets_efuse_flash_octal_mode()) { + large_flash_mode = ets_efuse_flash_octal_mode() || flash_larger_than_16mb(); + + // Initialize OPI flash driver only when flash is detected octal or quad larger than 16MB. + // Otherwise, we don't need to initialize such a driver + if (large_flash_mode) { static const esp_rom_opiflash_def_t flash_driver = OPIFLASH_DRIVER(); esp_rom_opiflash_legacy_driver_init(&flash_driver); esp_rom_opiflash_wait_idle(); diff --git a/flasher_stub/stub_write_flash.c b/flasher_stub/stub_write_flash.c index e94d0b56c..d2127b743 100644 --- a/flasher_stub/stub_write_flash.c +++ b/flasher_stub/stub_write_flash.c @@ -214,7 +214,7 @@ esp_command_error handle_flash_begin(uint32_t total_size, uint32_t offset) { fs.last_error = ESP_OK; #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode) { esp_rom_opiflash_wait_idle(); } else { if (SPIUnlock() != 0) { @@ -266,7 +266,7 @@ static void start_next_erase(void) spi_write_enable(); spi_wait_ready(); #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode) { if (block_erase) { if (fs.next_erase_sector * FLASH_SECTOR_SIZE < (1 << 24)) { esp_rom_opiflash_wait_idle(); @@ -354,7 +354,7 @@ void handle_flash_data(void *data_buf, uint32_t length) { /* do the actual write */ #if defined(ESP32S3) && !defined(ESP32S3BETA2) - if (ets_efuse_flash_octal_mode()) { + if (large_flash_mode){ res = SPIWrite4B(1, fs.next_write, data_buf, length); } else { res = SPIWrite(fs.next_write, data_buf, length); From 3b8ea4fda1ad956870664cf8cc30b8aac2519f9a Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 19 Sep 2023 14:01:19 +0200 Subject: [PATCH 065/209] ci(dev_release): Upload dev releases to PyPI with GH Actions --- .../workflows/dev_release_esptool_pypi.yml | 42 +++++++++++++++++++ .gitlab-ci.yml | 22 ---------- 2 files changed, 42 insertions(+), 22 deletions(-) create mode 100644 .github/workflows/dev_release_esptool_pypi.yml diff --git a/.github/workflows/dev_release_esptool_pypi.yml b/.github/workflows/dev_release_esptool_pypi.yml new file mode 100644 index 000000000..a443a1323 --- /dev/null +++ b/.github/workflows/dev_release_esptool_pypi.yml @@ -0,0 +1,42 @@ +# This workflow will upload an esptool Python package when a dev release tag (e.g. "v4.7.dev2") is pushed + +name: PyPI dev release + +on: + push: + tags: + - v*.*.dev* + +jobs: + build_and_upload: + + runs-on: ubuntu-latest + + if: startsWith(github.ref, 'refs/tags/') && contains(github.ref_name, 'dev') + + steps: + - uses: actions/checkout@master + - name: Set up Python 3.8 + uses: actions/setup-python@master + with: + python-version: '3.8' + - name: Install dependencies + run: | + python -m pip install --upgrade pip + python -m pip install twine setuptools + + - name: Create development release ${{ github.ref_name }} + env: + TWINE_USERNAME: __token__ + TWINE_PASSWORD: ${{ secrets.PYPI_PASSWORD }} + TWINE_NON_INTERACTIVE: true + run: | + DEV_VERSION=$(echo "${{ github.ref_name }}" | grep -oE 'dev[0-9]+' | sed 's/dev//') + python ci/patch_dev_release.py --dev-no ${DEV_VERSION} esptool/__init__.py + git diff + python -m pip download esptool==$(python setup.py -V) && echo "Version ${{ github.ref_name }} already published, skipping..." && exit 1 + + echo "Packaging and publishing new esptool development release: ${{ github.ref_name }}" + python setup.py sdist + tar -ztvf dist/* + twine upload dist/* diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4f9afaf79..c517f5950 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -501,25 +501,3 @@ deploy_docs_production: DOCS_DEPLOY_SERVER_USER: "$DOCS_PROD_SERVER_USER" DOCS_DEPLOY_PATH: "$DOCS_PROD_PATH" DOCS_DEPLOY_URL_BASE: "https://docs.espressif.com/projects/esptool" - -deploy_dev_package: - <<: *test_template - rules: - - if: $CI_DEV_PUBLISH != null && $CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH - variables: - TWINE_NON_INTERACTIVE: "true" - TWINE_USERNAME: __token__ - TWINE_PASSWORD: ${PYPI_ESPTOOL_TOKEN} - stage: deploy_development_package - dependencies: [] - script: - - python -m pip install --upgrade pip - - python -m pip install twine setuptools - - python ci/patch_dev_release.py --dev-no ${CI_DEV_PUBLISH} esptool/__init__.py - # check what has been changed with git - - git diff - - python setup.py sdist - # skip release if it has already been released (with failure) - - python -m pip download esptool==$(python setup.py -V) && exit 1 - - tar -ztvf dist/* - - python -m twine upload dist/* From be492a47ef4c6a00ad4776ac1879361730e9cdd9 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 8 Sep 2023 14:07:33 +0200 Subject: [PATCH 066/209] ci: fix pipeline for building docs --- .gitlab-ci.yml | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c517f5950..7f56dfe26 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -438,8 +438,8 @@ build_docs: image: python:3.7-bullseye tags: - build_docs - only: - changes: + rules: + - changes: - "docs/**/*" - "CONTRIBUTING.rst" needs: [] @@ -461,10 +461,6 @@ build_docs: - deploy needs: - build_docs - only: - changes: - - "docs/**/*" - - "CONTRIBUTING.rst" script: - source ${CI_PROJECT_DIR}/docs/utils.sh - add_doc_server_ssh_keys $DOCS_DEPLOY_PRIVATEKEY $DOCS_DEPLOY_SERVER $DOCS_DEPLOY_SERVER_USER From 11a2864d768878869743ebac89285d108ec04702 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 23 Aug 2023 16:11:00 +0200 Subject: [PATCH 067/209] feat(merge_bin): add support for uf2 format --- .gitlab-ci.yml | 9 ++ docs/en/esptool/basic-commands.rst | 46 +++++- esptool/__init__.py | 33 +++- esptool/cmds.py | 58 ++++--- esptool/targets/esp32.py | 2 + esptool/targets/esp32c2.py | 2 + esptool/targets/esp32c3.py | 2 + esptool/targets/esp32c6.py | 2 + esptool/targets/esp32h2.py | 2 + esptool/targets/esp32p4.py | 2 + esptool/targets/esp32s2.py | 2 + esptool/targets/esp32s3.py | 2 + esptool/targets/esp8266.py | 2 + esptool/uf2_writer.py | 96 ++++++++++++ setup.py | 2 + test/test_merge_bin.py | 243 +++++++++++++++++++++++++++++ test/test_uf2_ids.py | 66 ++++++++ 17 files changed, 537 insertions(+), 34 deletions(-) create mode 100644 esptool/uf2_writer.py create mode 100644 test/test_uf2_ids.py diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7f56dfe26..0eb06ecd4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -65,6 +65,15 @@ version_check: reports: junit: test/report.xml +check_uf2_ids: + <<: *host_tests_template + allow_failure: true + variables: + COVERAGE_PROCESS_START: "${CI_PROJECT_DIR}/test/.covconf" + PYTEST_ADDOPTS: "-sv --junitxml=test/report.xml --color=yes" + script: + - coverage run -m pytest ${CI_PROJECT_DIR}/test/test_uf2_ids.py + host_tests: <<: *host_tests_template variables: diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index f05cc4f03..a74dc3de6 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -236,8 +236,7 @@ This information corresponds to the headers described in :ref:`image-format`. Merge Binaries for Flashing: merge_bin -------------------------------------- - -The ``merge_bin`` command will merge multiple binary files (of any kind) into a single file that can be flashed to a device later. Any gaps between the input files are padded with 0xFF bytes (same as unwritten flash contents). +The ``merge_bin`` command will merge multiple binary files (of any kind) into a single file that can be flashed to a device later. Any gaps between the input files are padded based on selected output format. For example: @@ -247,16 +246,12 @@ For example: Will create a file ``merged-flash.bin`` with the contents of the other 3 files. This file can be later be written to flash with ``esptool.py write_flash 0x0 merged-flash.bin``. -.. note: - - Because gaps between the input files are padded with 0xFF bytes, when the merged binary is written then any flash sectors between the individual files will be erased. To avoid this, write the files individually. -**Options:** +**Common options:** * The ``merge_bin`` command supports the same ``--flash_mode``, ``--flash_size`` and ``--flash_freq`` options as the ``write_flash`` command to override the bootloader flash header (see above for details). These options are applied to the output file contents in the same way as when writing to flash. Make sure to pass the ``--chip`` parameter if using these options, as the supported values and the bootloader offset both depend on the chip. -* The ``--target-offset 0xNNN`` option will create a merged binary that should be flashed at the specified offset, instead of at offset 0x0. -* The ``--fill-flash-size SIZE`` option will pad the merged binary with 0xFF bytes to the full flash specified size, for example ``--fill-flash-size 4MB`` will create a 4MB binary file. +* The ``--format`` option will change the format of the output file. For more information about formats see formats description below. * It is possible to append options from a text file with ``@filename``. As an example, this can be conveniently used with the ESP-IDF build system, which produces a ``flash_args`` file in the build directory of a project: .. code:: sh @@ -264,6 +259,41 @@ Will create a file ``merged-flash.bin`` with the contents of the other 3 files. cd build # The build directory of an ESP-IDF project esptool.py --chip {IDF_TARGET_NAME} merge_bin -o merged-flash.bin @flash_args + +RAW Output Format +^^^^^^^^^^^^^^^^^ + +The output of the command will be in ``raw`` format and gaps between individual files will be filled with `0xFF` bytes (same as unwritten flash contents). + +.. note:: + + Because gaps between the input files are padded with `0xFF` bytes, when the merged binary is written then any flash sectors between the individual files will be erased. To avoid this, write the files individually. + + +**RAW options:** + +* The ``--fill-flash-size SIZE`` option will pad the merged binary with `0xFF` bytes to the full flash specified size, for example ``--fill-flash-size 4MB`` will create a 4MB binary file. +* The ``--target-offset 0xNNN`` option will create a merged binary that should be flashed at the specified offset, instead of at offset 0x0. + + +UF2 Output Format +^^^^^^^^^^^^^^^^^ + +This command will generate a UF2 (`USB Flashing Format `_) binary. +This UF2 file can be copied to a USB mass storage device exposed by another ESP running the `ESP USB Bridge `_ project. The bridge MCU will use it to flash the target MCU. This is as simple copying (or "drag-and-dropping") the file to the exposed disk accessed by a file explorer in your machine. + +Gaps between the files will be filled with `0x00` bytes. + +**UF2 options:** + +* The ``--chunk-size`` option will set what portion of 512 byte block will be used for data. Common value is 256 bytes. By default the largest possible value will be used. +* The ``--md5-disable`` option will disable MD5 checksums at the end of each block. This can be useful for integration with e.g. `tinyuf2 `__. + +.. code:: sh + + esptool.py --chip {IDF_TARGET_NAME} merge_bin --format uf2 -o merged-flash.uf2 --flash_mode dio --flash_size 4MB 0x1000 bootloader.bin 0x8000 partition-table.bin 0x10000 app.bin + + Advanced Commands ----------------- diff --git a/esptool/__init__.py b/esptool/__init__.py index 4d015daea..1902e1fd2 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -587,18 +587,36 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): "--output", "-o", help="Output filename", type=str, required=True ) parser_merge_bin.add_argument( - "--format", "-f", help="Format of the output file", choices="raw", default="raw" - ) # for future expansion + "--format", + "-f", + help="Format of the output file", + choices=["raw", "uf2"], + default="raw", + ) + uf2_group = parser_merge_bin.add_argument_group("UF2 format") + uf2_group.add_argument( + "--chunk-size", + help="Specify the used data part of the 512 byte UF2 block. " + "A common value is 256. By default the largest possible value will be used.", + default=None, + type=arg_auto_chunk_size, + ) + uf2_group.add_argument( + "--md5-disable", + help="Disable MD5 checksum in UF2 output", + action="store_true", + ) add_spi_flash_subparsers(parser_merge_bin, allow_keep=True, auto_detect=False) - parser_merge_bin.add_argument( + raw_group = parser_merge_bin.add_argument_group("RAW format") + raw_group.add_argument( "--target-offset", "-t", help="Target offset where the output file will be flashed", type=arg_auto_int, default=0, ) - parser_merge_bin.add_argument( + raw_group.add_argument( "--fill-flash-size", help="If set, the final binary file will be padded with FF " "bytes up to this flash size.", @@ -910,6 +928,13 @@ def arg_auto_size(x): return x if x == "all" else arg_auto_int(x) +def arg_auto_chunk_size(string: str) -> int: + num = int(string, 0) + if num & 3 != 0: + raise argparse.ArgumentTypeError("Chunk size should be a 4-byte aligned number") + return num + + def get_port_list(): if list_ports is None: raise FatalError( diff --git a/esptool/cmds.py b/esptool/cmds.py index 77cfbee14..a8d89b2ab 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -25,6 +25,7 @@ timeout_per_mb, ) from .targets import CHIP_DEFS, CHIP_LIST, ROM_LIST +from .uf2_writer import UF2Writer from .util import ( FatalError, NotImplementedInROMError, @@ -1278,9 +1279,9 @@ def merge_bin(args): msg = ( "Please specify the chip argument" if args.chip == "auto" - else "Invalid chip choice: '{}'".format(args.chip) + else f"Invalid chip choice: '{args.chip}'" ) - msg = msg + " (choose from {})".format(", ".join(CHIP_LIST)) + msg = f"{msg} (choose from {', '.join(CHIP_LIST)})" raise FatalError(msg) # sort the files by offset. @@ -1291,32 +1292,45 @@ def merge_bin(args): first_addr = input_files[0][0] if first_addr < args.target_offset: raise FatalError( - "Output file target offset is 0x%x. Input file offset 0x%x is before this." - % (args.target_offset, first_addr) + f"Output file target offset is {args.target_offset:#x}. " + f"Input file offset {first_addr:#x} is before this." ) - if args.format != "raw": - raise FatalError( - "This version of esptool only supports the 'raw' output format" + if args.format == "uf2": + with UF2Writer( + chip_class.UF2_FAMILY_ID, + args.output, + args.chunk_size, + md5_enabled=not args.md5_disable, + ) as writer: + for addr, argfile in input_files: + print(f"Adding {argfile.name} at {addr:#x}") + image = argfile.read() + image = _update_image_flash_params(chip_class, addr, args, image) + writer.add_file(addr, image) + print( + f"Wrote {os.path.getsize(args.output):#x} bytes to file {args.output}, " + f"ready to be flashed with any ESP USB Bridge" ) - with open(args.output, "wb") as of: + elif args.format == "raw": + with open(args.output, "wb") as of: - def pad_to(flash_offs): - # account for output file offset if there is any - of.write(b"\xFF" * (flash_offs - args.target_offset - of.tell())) + def pad_to(flash_offs): + # account for output file offset if there is any + of.write(b"\xFF" * (flash_offs - args.target_offset - of.tell())) - for addr, argfile in input_files: - pad_to(addr) - image = argfile.read() - image = _update_image_flash_params(chip_class, addr, args, image) - of.write(image) - if args.fill_flash_size: - pad_to(flash_size_bytes(args.fill_flash_size)) - print( - "Wrote 0x%x bytes to file %s, ready to flash to offset 0x%x" - % (of.tell(), args.output, args.target_offset) - ) + for addr, argfile in input_files: + pad_to(addr) + image = argfile.read() + image = _update_image_flash_params(chip_class, addr, args, image) + of.write(image) + if args.fill_flash_size: + pad_to(flash_size_bytes(args.fill_flash_size)) + print( + f"Wrote {of.tell():#x} bytes to file {args.output}, " + f"ready to flash to offset {args.target_offset:#x}" + ) def version(args): diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index 0ccceabff..c4f372a7f 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -105,6 +105,8 @@ class ESP32ROM(ESPLoader): FLASH_ENCRYPTED_WRITE_ALIGN = 32 + UF2_FAMILY_ID = 0x1C5F21B0 + """ Try to read the BLOCK1 (encryption key) and check if it is valid """ def is_flash_encryption_key_valid(self): diff --git a/esptool/targets/esp32c2.py b/esptool/targets/esp32c2.py index f28ee24f4..ff8341869 100644 --- a/esptool/targets/esp32c2.py +++ b/esptool/targets/esp32c2.py @@ -61,6 +61,8 @@ class ESP32C2ROM(ESP32C3ROM): [0x4037C000, 0x403C0000, "IRAM"], ] + UF2_FAMILY_ID = 0x2B88D29C + def get_pkg_version(self): num_word = 1 return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 22) & 0x07 diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index bff0d5447..58dff2a4f 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -99,6 +99,8 @@ class ESP32C3ROM(ESP32ROM): [0x600FE000, 0x60100000, "MEM_INTERNAL2"], ] + UF2_FAMILY_ID = 0xD42BA06C + def get_pkg_version(self): num_word = 3 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07 diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index fd39c6e09..5c83d381b 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -101,6 +101,8 @@ class ESP32C6ROM(ESP32C3ROM): [0x600FE000, 0x60100000, "MEM_INTERNAL2"], ] + UF2_FAMILY_ID = 0x540DDF62 + def get_pkg_version(self): num_word = 3 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x07 diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py index 88a0bba18..66600c7da 100644 --- a/esptool/targets/esp32h2.py +++ b/esptool/targets/esp32h2.py @@ -29,6 +29,8 @@ class ESP32H2ROM(ESP32C6ROM): "12m": 0x2, } + UF2_FAMILY_ID = 0x332726F6 + def get_pkg_version(self): num_word = 4 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07 diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 74e6ff089..853116029 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -79,6 +79,8 @@ class ESP32P4ROM(ESP32ROM): [0x600FE000, 0x60100000, "MEM_INTERNAL2"], ] + UF2_FAMILY_ID = 0x3D308E94 + def get_pkg_version(self): # ESP32P4 TODO return 0 diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py index 2f321afd5..89d6b4e08 100644 --- a/esptool/targets/esp32s2.py +++ b/esptool/targets/esp32s2.py @@ -101,6 +101,8 @@ class ESP32S2ROM(ESP32ROM): [0x50000000, 0x50002000, "RTC_DATA"], ] + UF2_FAMILY_ID = 0xBFDD4EEE + def get_pkg_version(self): num_word = 4 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 72aa88fb1..6e6a72119 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -117,6 +117,8 @@ class ESP32S3ROM(ESP32ROM): [0x50000000, 0x50002000, "RTC_DATA"], ] + UF2_FAMILY_ID = 0xC47E5767 + def get_pkg_version(self): num_word = 3 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07 diff --git a/esptool/targets/esp8266.py b/esptool/targets/esp8266.py index 9027eb86e..e686abf6e 100644 --- a/esptool/targets/esp8266.py +++ b/esptool/targets/esp8266.py @@ -60,6 +60,8 @@ class ESP8266ROM(ESPLoader): [0x40201010, 0x402E1010, "IROM"], ] + UF2_FAMILY_ID = 0x7EAB61ED + def get_efuses(self): # Return the 128 bits of ESP8266 efuse as a single Python integer result = self.read_reg(0x3FF0005C) << 96 diff --git a/esptool/uf2_writer.py b/esptool/uf2_writer.py new file mode 100644 index 000000000..554c8450c --- /dev/null +++ b/esptool/uf2_writer.py @@ -0,0 +1,96 @@ +#!/usr/bin/env python +# +# SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: GPL-2.0-or-later +# Code was originally licensed under Apache 2.0 before the release of ESP-IDF v5.2 + +import hashlib +import os +import struct +from typing import List + +from esptool.util import div_roundup + + +class UF2Writer(object): + # The UF2 format is described here: https://github.com/microsoft/uf2 + UF2_BLOCK_SIZE = 512 + # max value of CHUNK_SIZE reduced by optional parts. Currently, MD5_PART only. + UF2_DATA_SIZE = 476 + UF2_MD5_PART_SIZE = 24 + UF2_FIRST_MAGIC = 0x0A324655 + UF2_SECOND_MAGIC = 0x9E5D5157 + UF2_FINAL_MAGIC = 0x0AB16F30 + UF2_FLAG_FAMILYID_PRESENT = 0x00002000 + UF2_FLAG_MD5_PRESENT = 0x00004000 + + def __init__( + self, + chip_id: int, + output_file: os.PathLike, + chunk_size: int, + md5_enabled: bool = True, + ) -> None: + if not md5_enabled: + self.UF2_MD5_PART_SIZE = 0 + self.UF2_FLAG_MD5_PRESENT = 0x00000000 + self.md5_enabled = md5_enabled + self.chip_id = chip_id + self.CHUNK_SIZE = ( + self.UF2_DATA_SIZE - self.UF2_MD5_PART_SIZE + if chunk_size is None + else chunk_size + ) + self.f = open(output_file, "wb") + + def __enter__(self) -> "UF2Writer": + return self + + def __exit__(self, exc_type: str, exc_val: int, exc_tb: List) -> None: + if self.f: + self.f.close() + + @staticmethod + def _to_uint32(num: int) -> bytes: + return struct.pack(" None: + assert len_chunk > 0 + assert len_chunk <= self.CHUNK_SIZE + assert block_no < blocks + block = struct.pack( + " None: + blocks = div_roundup(len(image), self.CHUNK_SIZE) + chunks = [ + image[i : i + self.CHUNK_SIZE] + for i in range(0, len(image), self.CHUNK_SIZE) + ] + for i, chunk in enumerate(chunks): + len_chunk = len(chunk) + self._write_block(addr, chunk, len_chunk, i, blocks) + addr += len_chunk diff --git a/setup.py b/setup.py index 13272e0f1..a9bd17412 100644 --- a/setup.py +++ b/setup.py @@ -101,6 +101,7 @@ def find_version(*file_paths): "Programming Language :: Python :: 3.8", "Programming Language :: Python :: 3.9", "Programming Language :: Python :: 3.10", + "Programming Language :: Python :: 3.11", ], python_requires=">=3.7", setup_requires=(["wheel"] if "bdist_wheel" in sys.argv else []), @@ -115,6 +116,7 @@ def find_version(*file_paths): "pre-commit", "pytest", "pytest-rerunfailures", + "requests", ], "hsm": [ "python-pkcs11", diff --git a/test/test_merge_bin.py b/test/test_merge_bin.py index ede9242a2..5ca7e0890 100755 --- a/test/test_merge_bin.py +++ b/test/test_merge_bin.py @@ -1,9 +1,14 @@ +import filecmp +import hashlib import itertools import os import os.path +import random +import struct import subprocess import sys import tempfile +from functools import partial IMAGES_DIR = os.path.join(os.path.abspath(os.path.dirname(__file__)), "images") @@ -13,6 +18,8 @@ try: from esptool.util import byte + from esptool.uf2_writer import UF2Writer + from esptool.targets import CHIP_DEFS except ImportError: need_to_install_package_err() @@ -189,3 +196,239 @@ def test_fill_flash_size_w_target_offset(self): assert bootloader == merged[: len(bootloader)] assert helloworld == merged[0xF000 : 0xF000 + len(helloworld)] self.assertAllFF(merged[0xF000 + len(helloworld) :]) + + +class UF2Block(object): + def __init__(self, bs): + self.length = len(bs) + + # See https://github.com/microsoft/uf2 for the format + first_part = "<" + "I" * 8 + # payload is between + last_part = " Date: Tue, 26 Sep 2023 11:25:08 +0200 Subject: [PATCH 068/209] feat(esp32c3): Support ECO6 and ECO7 magic numbers --- esptool/targets/esp32c3.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index 58dff2a4f..8a5005e04 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -31,8 +31,8 @@ class ESP32C3ROM(ESP32ROM): BOOTLOADER_FLASH_OFFSET = 0x0 - # Magic value for ESP32C3 eco 1+2 and ESP32C3 eco3 respectivly - CHIP_DETECT_MAGIC_VALUE = [0x6921506F, 0x1B31506F] + # Magic values for ESP32-C3 eco 1+2, eco 3, eco 6, and eco 7 respectively + CHIP_DETECT_MAGIC_VALUE = [0x6921506F, 0x1B31506F, 0x4881606F, 0x4361606F] UART_DATE_REG_ADDR = 0x60000000 + 0x7C From 21e8d2f0e91719b6fda82d16bd173b9c7497929b Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 26 Sep 2023 15:00:59 +0200 Subject: [PATCH 069/209] ci(gitlab_ci): Change only/except syntax to rules --- .gitlab-ci.yml | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0eb06ecd4..6b9474b9e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -43,8 +43,8 @@ cache: version_check: <<: *test_template - only: - - tags + rules: + - if: '$CI_COMMIT_TAG != null' script: - VERSION=$(esptool.py version | head -n 1) - | @@ -480,9 +480,12 @@ build_docs: deploy_docs_preview: extends: - .deploy_docs_template - except: - refs: - - master + rules: + - if: '$CI_COMMIT_REF_NAME == "master"' + when: never + - changes: + - "docs/**/*" + - "CONTRIBUTING.rst" variables: TYPE: "preview" DOCS_BUILD_DIR: "${CI_PROJECT_DIR}/docs/_build/" @@ -495,9 +498,8 @@ deploy_docs_preview: deploy_docs_production: extends: - .deploy_docs_template - only: - refs: - - master + rules: + - if: '$CI_COMMIT_REF_NAME == "master"' variables: TYPE: "production" DOCS_BUILD_DIR: "${CI_PROJECT_DIR}/docs/_build/" From 06b938ee6e0e3a917102bfa5b042aee66159502b Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 25 Sep 2023 16:29:01 +0800 Subject: [PATCH 070/209] fix(flasher_stub): fix usb-serial-jtag enabled non-related intr source --- esptool/targets/stub_flasher/stub_flasher_32c3.json | 4 ++-- esptool/targets/stub_flasher/stub_flasher_32c6.json | 4 ++-- esptool/targets/stub_flasher/stub_flasher_32h2.json | 4 ++-- esptool/targets/stub_flasher/stub_flasher_32s3.json | 4 ++-- esptool/targets/stub_flasher/stub_flasher_32s3beta2.json | 4 ++-- flasher_stub/stub_io.c | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/esptool/targets/stub_flasher/stub_flasher_32c3.json b/esptool/targets/stub_flasher/stub_flasher_32c3.json index 2ecf24c2c..3bec094ba 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32c3.json +++ b/esptool/targets/stub_flasher/stub_flasher_32c3.json @@ -1,7 +1,7 @@ { "entry": 1077413532, - "text": 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WRITE_REG(USB_DEVICE_INT_ENA_REG, USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA); ets_isr_unmask(1 << ETS_USB_INUM); return; } From fc878cf345a9f18132c822d25ede13fc5424a643 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Wed, 20 Sep 2023 12:57:20 +0200 Subject: [PATCH 071/209] fix(loader): Could not open serial port message adjusted --- esptool/loader.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/esptool/loader.py b/esptool/loader.py index 88f1b77d4..3e45bec01 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -301,8 +301,11 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): if isinstance(port, str): try: self._port = serial.serial_for_url(port) - except serial.serialutil.SerialException: - raise FatalError(f"Could not open {port}, the port doesn't exist") + except serial.serialutil.SerialException as e: + raise FatalError( + f"Could not open {port}, the port is busy or doesn't exist." + f"\n({e})\n" + ) else: self._port = port self._slip_reader = slip_reader(self._port, self.trace) From b7ecd77ddbcaf92e06652192c82417dd569561de Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 3 Oct 2023 11:22:28 +0200 Subject: [PATCH 072/209] ci(gitlab): Fix deploying docs to production --- .gitlab-ci.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6b9474b9e..22f1339be 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -500,6 +500,9 @@ deploy_docs_production: - .deploy_docs_template rules: - if: '$CI_COMMIT_REF_NAME == "master"' + changes: + - "docs/**/*" + - "CONTRIBUTING.rst" variables: TYPE: "production" DOCS_BUILD_DIR: "${CI_PROJECT_DIR}/docs/_build/" From ebc12d5524bcb77973e624f5116370ae22707c34 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 3 Oct 2023 11:23:12 +0200 Subject: [PATCH 073/209] ci(github): Fix pyinstaller builds on ubuntu --- .github/workflows/build_esptool.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index f5fcbe664..eeb7b076f 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -31,8 +31,8 @@ jobs: container: ${{ matrix.CONTAINER }} # use python container on ARM env: DISTPATH: esptool-${{ matrix.TARGET }} - STUBS_DIR: /esptool/targets/stub_flasher/ - EFUSE_DIR: /espefuse/efuse_defs/ + STUBS_DIR: ./esptool/targets/stub_flasher/ + EFUSE_DIR: ./espefuse/efuse_defs/ PIP_EXTRA_INDEX_URL: "https://dl.espressif.com/pypi" steps: - name: Checkout repository @@ -50,8 +50,8 @@ jobs: pip install --user -e . - name: Build with PyInstaller run: | - pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico --add-data=".${{ env.STUBS_DIR }}*.json${{ matrix.SEPARATOR }}${{ env.STUBS_DIR }}" esptool.py - pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico --add-data=".${{ env.EFUSE_DIR }}*.yaml${{ matrix.SEPARATOR }}${{ env.EFUSE_DIR }}" espefuse.py + pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico --add-data="${{ env.STUBS_DIR }}*.json${{ matrix.SEPARATOR }}${{ env.STUBS_DIR }}" esptool.py + pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico --add-data="${{ env.EFUSE_DIR }}*.yaml${{ matrix.SEPARATOR }}${{ env.EFUSE_DIR }}" espefuse.py pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico espsecure.py pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico esp_rfc2217_server.py - name: Sign binaries From 621c8e1836f7bed4b790389cd09f03c93651f989 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Thu, 5 Oct 2023 10:29:17 +0200 Subject: [PATCH 074/209] docs(basic-commands): added note for PowerShell users for merge_bin command Closes https://github.com/espressif/esptool/issues/923 --- docs/en/esptool/advanced-options.rst | 5 +++++ docs/en/esptool/basic-commands.rst | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/docs/en/esptool/advanced-options.rst b/docs/en/esptool/advanced-options.rst index 793853c44..d47ab515a 100644 --- a/docs/en/esptool/advanced-options.rst +++ b/docs/en/esptool/advanced-options.rst @@ -100,7 +100,12 @@ Passing ``--no-stub`` will disable certain options, as not all options are imple Specifying Arguments via File ----------------------------- +.. _specify_arguments_via_file: Anywhere on the esptool command line, you can specify a file name as ``@filename.txt`` to read one or more arguments from text file ``filename.txt``. Arguments can be separated by newlines or spaces, quotes can be used to enclose arguments that span multiple words. Arguments read from the text file are expanded exactly as if they had appeared in that order on the esptool command line. An example of this is available in the :ref:`merge_bin ` command description. + +.. note:: PowerShell users + + Because of `splatting `__ in PowerShell (method of passing a collection of parameter values to a command as a unit) there is a need to add quotes around @filename.txt ("@filename.txt") to be correctly resolved. diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index a74dc3de6..fe1db08dc 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -252,7 +252,7 @@ Will create a file ``merged-flash.bin`` with the contents of the other 3 files. * The ``merge_bin`` command supports the same ``--flash_mode``, ``--flash_size`` and ``--flash_freq`` options as the ``write_flash`` command to override the bootloader flash header (see above for details). These options are applied to the output file contents in the same way as when writing to flash. Make sure to pass the ``--chip`` parameter if using these options, as the supported values and the bootloader offset both depend on the chip. * The ``--format`` option will change the format of the output file. For more information about formats see formats description below. -* It is possible to append options from a text file with ``@filename``. As an example, this can be conveniently used with the ESP-IDF build system, which produces a ``flash_args`` file in the build directory of a project: +* It is possible to append options from a text file with ``@filename`` (see the advanced options page :ref:`Specifying Arguments via File ` section for details). As an example, this can be conveniently used with the ESP-IDF build system, which produces a ``flash_args`` file in the build directory of a project: .. code:: sh From 6c8149029e909001b86f578b87cda063ee42d447 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 9 Oct 2023 14:38:13 +0200 Subject: [PATCH 075/209] feat: Add support for Python 3.12 --- .github/workflows/test_esptool.yml | 23 ++++++++++++----------- setup.py | 1 + 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/.github/workflows/test_esptool.yml b/.github/workflows/test_esptool.yml index fb1947b35..0287eae76 100644 --- a/.github/workflows/test_esptool.yml +++ b/.github/workflows/test_esptool.yml @@ -8,7 +8,7 @@ jobs: strategy: matrix: - python-version: ['3.7', '3.8', '3.9', '3.10'] + python-version: ['3.7', '3.8', '3.9', '3.10', '3.11', '3.12'] steps: - name: Checkout ref commit @@ -19,6 +19,11 @@ jobs: with: python-version: ${{ matrix.python-version }} + - name: Install dependencies + run: | + python -m pip install --upgrade pip + pip install setuptools + - name: SoftHSM2 setup run: | sudo apt-get update @@ -28,23 +33,19 @@ jobs: sudo chown -R $(whoami) /var/lib/softhsm ./ci/setup_softhsm2.sh || exit 1 - - name: Test python components (fast) + - name: Install esptool and check if the installed versions can run run: | python setup.py build pip install --extra-index-url https://dl.espressif.com/pypi -e .[dev,hsm] - pytest test/test_imagegen.py - pytest test/test_espsecure.py - pytest test/test_espsecure_hsm.py - pytest test/test_merge_bin.py - pytest test/test_image_info.py - pytest test/test_modules.py - - - name: Check the installed versions can run - run: | esptool.py --help espefuse.py --help espsecure.py --help + - name: Test esptool and components + run: | + pytest -m host_test + pytest test/test_espsecure_hsm.py + - name: Build stub (Python 3.7 only) if: matrix.python-version == 3.7 run: | diff --git a/setup.py b/setup.py index a9bd17412..f6e084e7e 100644 --- a/setup.py +++ b/setup.py @@ -102,6 +102,7 @@ def find_version(*file_paths): "Programming Language :: Python :: 3.9", "Programming Language :: Python :: 3.10", "Programming Language :: Python :: 3.11", + "Programming Language :: Python :: 3.12", ], python_requires=">=3.7", setup_requires=(["wheel"] if "bdist_wheel" in sys.argv else []), From 114dc305328d247dd0dc2919c47b414869ac4a17 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Wed, 11 Oct 2023 10:10:24 +0200 Subject: [PATCH 076/209] feat(loader): Added hints for some serial port issues when rising port error Closes https://github.com/espressif/esp-idf/issues/12366 --- esptool/loader.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/esptool/loader.py b/esptool/loader.py index 3e45bec01..c45a45c37 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -302,9 +302,37 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): try: self._port = serial.serial_for_url(port) except serial.serialutil.SerialException as e: + port_issues = [ + [ # does not exist error + re.compile(r"Errno 2|FileNotFoundError", re.IGNORECASE), + "Check if the port is correct and ESP connected", + ], + [ # busy port error + re.compile(r"Access is denied", re.IGNORECASE), + "Check if the port is not used by another task", + ], + ] + if sys.platform.startswith("linux"): + port_issues.append( + [ # permission denied error + re.compile(r"Permission denied", re.IGNORECASE), + ( + "Try to add user into dialout group: " + "sudo usermod -a -G dialout $USER" + ), + ], + ) + + hint_msg = "" + for port_issue in port_issues: + if port_issue[0].search(str(e)): + hint_msg = f"\nHint: {port_issue[1]}\n" + break + raise FatalError( f"Could not open {port}, the port is busy or doesn't exist." f"\n({e})\n" + f"{hint_msg}" ) else: self._port = port From 80bdef4597b83857de8903c8592b67ace2aba01c Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 17 Oct 2023 10:04:29 +0200 Subject: [PATCH 077/209] feat: add support for get_security_info on esp32c3 ECO7 --- .../targets/stub_flasher/stub_flasher_32c3.json | 4 ++-- flasher_stub/include/rom_functions.h | 4 ++++ flasher_stub/ld/rom_32c3.ld | 2 +- flasher_stub/stub_commands.c | 7 +++++++ test/images/esp32c3_header_min_rev.bin | Bin 48 -> 48 bytes test/test_esptool.py | 2 +- 6 files changed, 15 insertions(+), 4 deletions(-) diff --git a/esptool/targets/stub_flasher/stub_flasher_32c3.json b/esptool/targets/stub_flasher/stub_flasher_32c3.json index 3bec094ba..3edf1457e 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32c3.json +++ b/esptool/targets/stub_flasher/stub_flasher_32c3.json @@ -1,7 +1,7 @@ { "entry": 1077413532, - "text": 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"text_start": 1077411840, - "data": "FEDIP3IKOEDCCjhAGgs4QL4LOEAqDDhA2As4QD4JOEB6CzhAugs4QC4LOEDuCDhAYgs4QO4IOEBMCjhAkgo4QMIKOEAaCzhAXgo4QKIJOEDSCThAWgo4QIIOOEDCCjhAQg04QDoOOEAuCDhAYg44QC4IOEAuCDhALgg4QC4IOEAuCDhALgg4QC4IOEAuCDhA3gw4QC4IOEBgDThAOg44QA==", + "data": "FEDIP4wKOEDcCjhANAs4QNgLOEBEDDhA8gs4QD4JOECUCzhA1As4QEgLOEDuCDhAfAs4QO4IOEBmCjhArAo4QNwKOEA0CzhAeAo4QKIJOEDsCThAdAo4QJwOOEDcCjhAXA04QFQOOEAuCDhAfA44QC4IOEAuCDhALgg4QC4IOEAuCDhALgg4QC4IOEAuCDhA+Aw4QC4IOEB6DThAVA44QA==", "data_start": 1070164912 } \ No newline at end of file diff --git a/flasher_stub/include/rom_functions.h b/flasher_stub/include/rom_functions.h index 84a920344..6259dae88 100644 --- a/flasher_stub/include/rom_functions.h +++ b/flasher_stub/include/rom_functions.h @@ -107,6 +107,10 @@ SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32 #if ESP32S2_OR_LATER uint32_t GetSecurityInfoProc(int* pMsg, int* pnErr, uint8_t *buf); // pMsg and pnErr unused in ROM +#if ESP32C3 +extern uint32_t _rom_eco_version; // rom constant to define ECO version +uint32_t GetSecurityInfoProcNewEco(int* pMsg, int* pnErr, uint8_t *buf); // GetSecurityInfo for C3 ECO7+ +#endif // ESP32C3 SpiFlashOpResult SPI_read_status_high(esp_rom_spiflash_chip_t *spi, uint32_t *status); #else /* Note: On ESP32 this was a static function whose first argument was elided by the diff --git a/flasher_stub/ld/rom_32c3.ld b/flasher_stub/ld/rom_32c3.ld index 40f112d41..ecaaf4928 100755 --- a/flasher_stub/ld/rom_32c3.ld +++ b/flasher_stub/ld/rom_32c3.ld @@ -67,6 +67,7 @@ send_packet = 0x400000a8; recv_packet = 0x400000ac; GetUartDevice = 0x400000b0; GetSecurityInfoProc = 0x4004b9da; +GetSecurityInfoProcNewEco = 0x4004d51e; /* manually added from esp32c3eco7-20230720; new address of function for eco7+ */ UartDwnLdProc = 0x400000b4; Uart_Init = 0x400000b8; ets_set_user_start = 0x400000bc; @@ -2197,4 +2198,3 @@ _global_impure_ptr = 0x3fcdffdc; */ _rom_chip_id = 0x40000010; _rom_eco_version = 0x40000014; - diff --git a/flasher_stub/stub_commands.c b/flasher_stub/stub_commands.c index 041b2bab1..11340e19d 100644 --- a/flasher_stub/stub_commands.c +++ b/flasher_stub/stub_commands.c @@ -254,7 +254,14 @@ esp_command_error handle_get_security_info() uint8_t buf[SECURITY_INFO_BYTES]; esp_command_error ret; + #ifdef ESP32C3 + if (_rom_eco_version >= 7) + ret = GetSecurityInfoProcNewEco(NULL, NULL, buf); + else + ret = GetSecurityInfoProc(NULL, NULL, buf); + #else ret = GetSecurityInfoProc(NULL, NULL, buf); + #endif // ESP32C3 if (ret == ESP_OK) SLIP_send_frame_data_buf(buf, sizeof(buf)); return ret; diff --git a/test/images/esp32c3_header_min_rev.bin b/test/images/esp32c3_header_min_rev.bin index 9c556e3ef07c319d45c61a09df2d29c4f7a7367c..1422b596fee093b4a950508acb12dec08b927bd1 100644 GIT binary patch delta 22 ccmXpo5O~SRB=COU+ItK@z{ Date: Thu, 19 Oct 2023 10:47:37 +0200 Subject: [PATCH 078/209] docs(troubleshooting): Explain issues when flashing with USB-Serial/JTAG or USB-OTG Closes https://github.com/espressif/esptool/issues/924 --- docs/en/troubleshooting.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/docs/en/troubleshooting.rst b/docs/en/troubleshooting.rst index ef516ee70..5d3e3dbf3 100644 --- a/docs/en/troubleshooting.rst +++ b/docs/en/troubleshooting.rst @@ -102,6 +102,17 @@ Early Stage Crash Use any of `serial terminal programs`_ to view the boot log. ({IDF_TARGET_NAME} baud rate is 115200bps). See if the program is crashing during early startup or outputting an error message. +.. only:: not esp8266 and not esp32 and not esp32c2 + + Issues When Using USB-Serial/JTAG or USB-OTG + -------------------------------------------- + + When working with ESP chips that implement a `USB-Serial/JTAG Controller `_ or a `USB-OTG console `_, it's essential to be aware of potential issues related to the loaded application interfering with or reprogramming the GPIO pins used for USB communication. + + If the application accidentally reconfigures the USB peripheral pins or disables the USB peripheral, the device disappears from the system. You can also encounter unstable flashing or errors like ``OSError: [Errno 71] Protocol error``. + + If that happens, try :ref:`manually entering the download mode ` and then using the :ref:`erase_flash ` command to wipe the flash memory. Then, make sure to fix the issue in the application before flashing again. + Serial Terminal Programs ------------------------ From c1476949559ff22e6fa0a2a2a8ecb0c6ecc9b5aa Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 19 Oct 2023 16:10:47 +0800 Subject: [PATCH 079/209] feat(espefuse): Update the way to complete the operation --- espefuse/efuse/esp32c2/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32c2/fields.py | 10 +++++++--- espefuse/efuse/esp32c3/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32c3/fields.py | 10 +++++++--- espefuse/efuse/esp32c6/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32c6/fields.py | 10 +++++++--- espefuse/efuse/esp32h2/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32h2/fields.py | 10 +++++++--- .../efuse/esp32h2beta1/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32h2beta1/fields.py | 10 +++++++--- espefuse/efuse/esp32p4/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32p4/fields.py | 10 +++++++--- espefuse/efuse/esp32s2/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32s2/fields.py | 10 +++++++--- espefuse/efuse/esp32s3/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32s3/fields.py | 10 +++++++--- .../efuse/esp32s3beta2/emulate_efuse_controller.py | 6 +++--- espefuse/efuse/esp32s3beta2/fields.py | 10 +++++++--- 18 files changed, 90 insertions(+), 54 deletions(-) diff --git a/espefuse/efuse/esp32c2/emulate_efuse_controller.py b/espefuse/efuse/esp32c2/emulate_efuse_controller.py index f08a170c4..26796dff8 100644 --- a/espefuse/efuse/esp32c2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c2/emulate_efuse_controller.py @@ -24,7 +24,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -55,10 +55,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index d2a6e1b6c..dda997e58 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -152,9 +152,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32c3/emulate_efuse_controller.py b/espefuse/efuse/esp32c3/emulate_efuse_controller.py index 6d39762ec..2d812a10d 100644 --- a/espefuse/efuse/esp32c3/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c3/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index 5f68c2ae4..7a09c65c5 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -160,9 +160,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32c6/emulate_efuse_controller.py b/espefuse/efuse/esp32c6/emulate_efuse_controller.py index bd7d4e4fd..a9e7d4d4a 100644 --- a/espefuse/efuse/esp32c6/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c6/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index 3f67ec06d..a62004f1a 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -160,9 +160,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32h2/emulate_efuse_controller.py b/espefuse/efuse/esp32h2/emulate_efuse_controller.py index 438061e6e..c8d3cd91a 100644 --- a/espefuse/efuse/esp32h2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32h2/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index 7f7d4cee4..cba9cb6d5 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -160,9 +160,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py b/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py index 937371339..b81e8e08f 100644 --- a/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index bef76f4e2..3e8f28928 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -160,9 +160,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32p4/emulate_efuse_controller.py b/espefuse/efuse/esp32p4/emulate_efuse_controller.py index a96439fdd..aa670aff7 100644 --- a/espefuse/efuse/esp32p4/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32p4/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py index d88b59272..b79816208 100644 --- a/espefuse/efuse/esp32p4/fields.py +++ b/espefuse/efuse/esp32p4/fields.py @@ -161,9 +161,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32s2/emulate_efuse_controller.py b/espefuse/efuse/esp32s2/emulate_efuse_controller.py index e926f3e71..497c91a5f 100644 --- a/espefuse/efuse/esp32s2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s2/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32s2/fields.py b/espefuse/efuse/esp32s2/fields.py index f38107367..a4113848b 100644 --- a/espefuse/efuse/esp32s2/fields.py +++ b/espefuse/efuse/esp32s2/fields.py @@ -160,9 +160,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32s3/emulate_efuse_controller.py b/espefuse/efuse/esp32s3/emulate_efuse_controller.py index 1d7569c7e..7e767b954 100644 --- a/espefuse/efuse/esp32s3/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s3/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index 6949184a3..604c4a45c 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -160,9 +160,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) diff --git a/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py b/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py index ae917b45f..0d81c0832 100644 --- a/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 017a0beae..26abb9f1f 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -160,9 +160,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) From 49dbfaff2aa611e0f0c2d858b8ba8a833275310a Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 25 Oct 2023 10:40:49 +0800 Subject: [PATCH 080/209] docs(boot_mode_selection): Correct secondary strapping pin boot mode levels Closes https://github.com/espressif/esptool/issues/928 --- docs/en/advanced-topics/boot-mode-selection.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index 875025397..62e187b5a 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -80,7 +80,7 @@ This guide explains how to select the boot mode correctly and describes the boot {IDF_TARGET_STRAP_BOOT_2_GPIO} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - .. only:: not esp32c3 + .. only:: esp32 or esp32s2 or esp32s3 {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be either left unconnected/floating, or driven Low, in order to enter the serial bootloader. @@ -241,7 +241,7 @@ Depending on the kind of hardware you have, it may also be possible to manually ``boot:0xNN (DESCRIPTION)`` is the hex value of the strapping pins, as represented in the `GPIO_STRAP register `__. The individual bit values are as follows: - + .. only:: esp32 - ``0x01`` - GPIO5 @@ -308,7 +308,7 @@ Depending on the kind of hardware you have, it may also be possible to manually clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 mode:DIO, clock div:1 - + .. only:: not esp32 :: From 51e1de28749eb812c0d1a3e18a249a575c8bdf01 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Wed, 4 Oct 2023 17:11:34 +0800 Subject: [PATCH 081/209] feat(espefuse): Adds efuse ADC calibration data for ESP32H2 --- espefuse/efuse/esp32h2/fields.py | 2 +- espefuse/efuse/esp32h2/mem_definition.py | 2 +- espefuse/efuse/esp32h2/operations.py | 46 ++++++++++-------------- espefuse/efuse_defs/esp32h2.yaml | 21 ++++++++--- 4 files changed, 36 insertions(+), 35 deletions(-) diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index cba9cb6d5..add5db76f 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -94,7 +94,7 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLK_VERSION_MAJOR"].get() == 1: + if self["BLK_VERSION_MINOR"].get() == 2: self.efuses += [ EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES diff --git a/espefuse/efuse/esp32h2/mem_definition.py b/espefuse/efuse/esp32h2/mem_definition.py index edf07f112..d08a71f0c 100644 --- a/espefuse/efuse/esp32h2/mem_definition.py +++ b/espefuse/efuse/esp32h2/mem_definition.py @@ -117,7 +117,7 @@ def __init__(self) -> None: self.KEYBLOCKS = [] - # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 + # if BLK_VERSION_MINOR is 2, these efuse fields are in BLOCK2 self.BLOCK2_CALIBRATION_EFUSES = [] self.CALC = [] diff --git a/espefuse/efuse/esp32h2/operations.py b/espefuse/efuse/esp32h2/operations.py index 20a76da96..d9445d152 100644 --- a/espefuse/efuse/esp32h2/operations.py +++ b/espefuse/efuse/esp32h2/operations.py @@ -193,38 +193,28 @@ def set_flash_voltage(esp, efuses, args): def adc_info(esp, efuses, args): print("") # fmt: off - if efuses["BLK_VERSION_MAJOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) + if efuses["BLK_VERSION_MINOR"].get() == 2: + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) print("") print("ADC1 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC1_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC1_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC1_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC1_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC1_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC1_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC1_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC1_MODE3_D2"].get())) - - print("") - print("ADC2 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC2_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC2_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC2_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC2_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC2_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC2_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) + print(" AVE_INITCODE_ATTEN0: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN0"].get())) + print(" AVE_INITCODE_ATTEN1: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN1"].get())) + print(" AVE_INITCODE_ATTEN2: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN2"].get())) + print(" AVE_INITCODE_ATTEN3: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN3"].get())) + + print(" HI_DOUT_ATTEN0: {}".format(efuses["ADC1_HI_DOUT_ATTEN0"].get())) + print(" HI_DOUT_ATTEN1: {}".format(efuses["ADC1_HI_DOUT_ATTEN1"].get())) + print(" HI_DOUT_ATTEN2: {}".format(efuses["ADC1_HI_DOUT_ATTEN2"].get())) + print(" HI_DOUT_ATTEN3: {}".format(efuses["ADC1_HI_DOUT_ATTEN3"].get())) + + print(" CH0_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH0_ATTEN0_INITCODE_DIFF"].get())) + print(" CH1_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH1_ATTEN0_INITCODE_DIFF"].get())) + print(" CH2_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH2_ATTEN0_INITCODE_DIFF"].get())) + print(" CH3_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH3_ATTEN0_INITCODE_DIFF"].get())) + print(" CH4_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH4_ATTEN0_INITCODE_DIFF"].get())) else: - print("BLK_VERSION_MAJOR = {}".format(efuses["BLK_VERSION_MAJOR"].get_meaning())) + print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get())) # fmt: on diff --git a/espefuse/efuse_defs/esp32h2.yaml b/espefuse/efuse_defs/esp32h2.yaml index 895751a8a..a86a01895 100644 --- a/espefuse/efuse_defs/esp32h2.yaml +++ b/espefuse/efuse_defs/esp32h2.yaml @@ -1,4 +1,4 @@ -VER_NO: 4df10f83de85f2d830b7c466aabb28e7 +VER_NO: b69ddcfb39a412df490e3facbbfb46b2 EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} @@ -75,10 +75,21 @@ EFUSES: BLK_VERSION_MINOR : {show: y, blk : 2, word: 4, pos : 2, len : 3, start: 130, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: 'BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1', rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[4:2]', bloc: 'B16[4:2]'} BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 5, len : 2, start: 133, type : 'uint:2', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[6:5]', bloc: 'B16[6:5]'} DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 2, word: 4, pos : 7, len : 1, start: 135, type : bool, wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[7]', bloc: 'B16[7]'} - RESERVED_2_136 : {show: n, blk : 2, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:8]', bloc: 'B17,B18,B19'} - SYS_DATA_PART1_5 : {show: n, blk : 2, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the fifth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA5_REG, bloc: 'B20,B21,B22,B23'} - SYS_DATA_PART1_6 : {show: n, blk : 2, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the sixth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA6_REG, bloc: 'B24,B25,B26,B27'} - SYS_DATA_PART1_7 : {show: n, blk : 2, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the seventh 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA7_REG, bloc: 'B28,B29,B30,B31'} + TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 8, len : 9, start: 136, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[16:8]', bloc: 'B17,B18[0]'} + ADC1_AVE_INITCODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 17, len : 10, start: 145, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[26:17]', bloc: 'B18[7:1],B19[2:0]'} + ADC1_AVE_INITCODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 27, len : 10, start: 155, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:27]', bloc: 'B19[7:3],B20[4:0]'} + ADC1_AVE_INITCODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 5, len : 10, start: 165, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[14:5]', bloc: 'B20[7:5],B21[6:0]'} + ADC1_AVE_INITCODE_ATTEN3 : {show: y, blk : 2, word: 5, pos: 15, len : 10, start: 175, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[24:15]', bloc: 'B21[7],B22,B23[0]'} + ADC1_HI_DOUT_ATTEN0 : {show: y, blk : 2, word: 5, pos: 25, len : 10, start: 185, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:25]', bloc: 'B23[7:1],B24[2:0]'} + ADC1_HI_DOUT_ATTEN1 : {show: y, blk : 2, word: 6, pos : 3, len : 10, start: 195, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[12:3]', bloc: 'B24[7:3],B25[4:0]'} + ADC1_HI_DOUT_ATTEN2 : {show: y, blk : 2, word: 6, pos: 13, len : 10, start: 205, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[22:13]', bloc: 'B25[7:5],B26[6:0]'} + ADC1_HI_DOUT_ATTEN3 : {show: y, blk : 2, word: 6, pos: 23, len : 10, start: 215, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:23]', bloc: 'B26[7],B27,B28[0]'} + ADC1_CH0_ATTEN0_INITCODE_DIFF : {show: y, blk : 2, word: 7, pos : 1, len : 4, start: 225, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[4:1]', bloc: 'B28[4:1]'} + ADC1_CH1_ATTEN0_INITCODE_DIFF : {show: y, blk : 2, word: 7, pos : 5, len : 4, start: 229, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[8:5]', bloc: 'B28[7:5],B29[0]'} + ADC1_CH2_ATTEN0_INITCODE_DIFF : {show: y, blk : 2, word: 7, pos : 9, len : 4, start: 233, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[12:9]', bloc: 'B29[4:1]'} + ADC1_CH3_ATTEN0_INITCODE_DIFF : {show: y, blk : 2, word: 7, pos: 13, len : 4, start: 237, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:13]', bloc: 'B29[7:5],B30[0]'} + ADC1_CH4_ATTEN0_INITCODE_DIFF : {show: y, blk : 2, word: 7, pos: 17, len : 4, start: 241, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[20:17]', bloc: 'B30[4:1]'} + RESERVED_2_245 : {show: n, blk : 2, word: 7, pos: 21, len : 11, start: 245, type : 'uint:11', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:21]', bloc: 'B30[7:5],B31'} BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} From 35e23d45174f151a9dd8ad24d73c43e133eeb4b0 Mon Sep 17 00:00:00 2001 From: 20162026 <36726858+20162026@users.noreply.github.com> Date: Thu, 26 Oct 2023 20:00:50 +0300 Subject: [PATCH 082/209] feat(rfc2217_server): Add hard reset sequence --- esp_rfc2217_server.py | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/esp_rfc2217_server.py b/esp_rfc2217_server.py index 9cf116aa2..8b9a1678e 100755 --- a/esp_rfc2217_server.py +++ b/esp_rfc2217_server.py @@ -37,7 +37,13 @@ import time from esptool.config import load_config_file -from esptool.reset import ClassicReset, CustomReset, DEFAULT_RESET_DELAY, UnixTightReset +from esptool.reset import ( + ClassicReset, + CustomReset, + DEFAULT_RESET_DELAY, + HardReset, + UnixTightReset, +) import serial import serial.rfc2217 @@ -63,14 +69,23 @@ class EspPortManager(serial.rfc2217.PortManager): def __init__(self, serial_port, connection, esp32r0_delay, logger=None): self.esp32r0_delay = esp32r0_delay + self.is_download_mode = False super(EspPortManager, self).__init__(serial_port, connection, logger) def _telnet_process_subnegotiation(self, suboption): if suboption[0:1] == COM_PORT_OPTION and suboption[1:2] == SET_CONTROL: if suboption[2:3] == SET_CONTROL_DTR_OFF: + self.is_download_mode = False self.serial.dtr = False return - elif suboption[2:3] == SET_CONTROL_RTS_ON and not self.serial.dtr: + elif suboption[2:3] == SET_CONTROL_RTS_OFF and not self.is_download_mode: + reset_thread = threading.Thread(target=self._hard_reset_thread) + reset_thread.daemon = True + reset_thread.name = "hard_reset_thread" + reset_thread.start() + return + elif suboption[2:3] == SET_CONTROL_DTR_ON and not self.is_download_mode: + self.is_download_mode = True reset_thread = threading.Thread(target=self._reset_thread) reset_thread.daemon = True reset_thread.name = "reset_thread" @@ -85,6 +100,14 @@ def _telnet_process_subnegotiation(self, suboption): # only in cases not handled above do the original implementation in PortManager super(EspPortManager, self)._telnet_process_subnegotiation(suboption) + def _hard_reset_thread(self): + """ + The reset logic used for hard resetting the chip. + """ + if self.logger: + self.logger.info("Activating hard reset in thread") + HardReset(self.serial)() + def _reset_thread(self): """ The reset logic is used from esptool.py because the RTS and DTR signals From f9b617959b2cc34e505a9d6afcef2051fff12ed2 Mon Sep 17 00:00:00 2001 From: Almir Okato Date: Thu, 21 Sep 2023 10:26:49 -0300 Subject: [PATCH 083/209] feat(elf2image): add ram-only-header argument The ram-only-header configuration makes only the RAM segments visible to the ROM bootloader placing them at the beginning of the file and altering the segment count from the image header with the quantity of these segments, and also writing only their checksum. This segment placement also may not result as optimal as the standard way regarding the padding gap use among the flash segments that could result in a less fragmented binary. The image built must then handle the basic hardware initialization and the flash mapping for code execution after ROM bootloader boot it. Signed-off-by: Marek Matej Signed-off-by: Almir Okato --- docs/en/esptool/basic-commands.rst | 6 ++- esptool/__init__.py | 11 ++++ esptool/bin_image.py | 85 +++++++++++++++++++++--------- esptool/cmds.py | 6 +++ test/test_imagegen.py | 24 +++++++-- 5 files changed, 103 insertions(+), 29 deletions(-) diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index fe1db08dc..880cb5fe3 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -211,6 +211,10 @@ By default, ``elf2image`` uses the sections in the ELF file to generate each seg In the above example, the output image file would be called ``my_esp_app.bin``. + The ``--ram-only-header`` configuration is mainly applicable for use within the Espressif's SIMPLE_BOOT option from 3rd party OSes such as ZephyrOS and NuttX OS. + This option makes only the RAM segments visible to the ROM bootloader placing them at the beginning of the file and altering the segment count from the image header with the quantity of these segments, and also writing only their checksum. This segment placement may result in a more fragmented binary because of flash alignment constraints. + It is strongly recommended to use this configuration with care, because the image built must then handle the basic hardware initialization and the flash mapping for code execution after ROM bootloader boot it. + .. _image-info: Output .bin Image Details: image_info @@ -279,7 +283,7 @@ The output of the command will be in ``raw`` format and gaps between individual UF2 Output Format ^^^^^^^^^^^^^^^^^ -This command will generate a UF2 (`USB Flashing Format `_) binary. +This command will generate a UF2 (`USB Flashing Format `_) binary. This UF2 file can be copied to a USB mass storage device exposed by another ESP running the `ESP USB Bridge `_ project. The bridge MCU will use it to flash the target MCU. This is as simple copying (or "drag-and-dropping") the file to the exposed disk accessed by a file explorer in your machine. Gaps between the files will be filled with `0x00` bytes. diff --git a/esptool/__init__.py b/esptool/__init__.py index 1902e1fd2..973d1fd5b 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -477,6 +477,17 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): "must be aligned to. Value 0xFF is used for padding, similar to erase_flash", default=None, ) + parser_elf2image.add_argument( + "--ram-only-header", + help="Order segments of the output so IRAM and DRAM are placed at the " + "beginning and force the main header segment number to RAM segments " + "quantity. This will make the other segments invisible to the ROM " + "loader. Use this argument with care because the ROM loader will load " + "only the RAM segments although the other segments being present in " + "the output.", + action="store_true", + default=None, + ) add_spi_flash_subparsers(parser_elf2image, allow_keep=False, auto_detect=False) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index fc3872b13..0f3ef2f64 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -571,7 +571,7 @@ class ESP32FirmwareImage(BaseFirmwareImage): IROM_ALIGN = 65536 - def __init__(self, load_file=None, append_digest=True): + def __init__(self, load_file=None, append_digest=True, ram_only_header=False): super(ESP32FirmwareImage, self).__init__() self.secure_pad = None self.flash_mode = 0 @@ -589,6 +589,7 @@ def __init__(self, load_file=None, append_digest=True): self.min_rev = 0 self.min_rev_full = 0 self.max_rev_full = 0 + self.ram_only_header = ram_only_header self.append_digest = append_digest @@ -701,33 +702,61 @@ def get_alignment_data_needed(segment): pad_len += self.IROM_ALIGN return pad_len - # try to fit each flash segment on a 64kB aligned boundary - # by padding with parts of the non-flash segments... - while len(flash_segments) > 0: - segment = flash_segments[0] - pad_len = get_alignment_data_needed(segment) - if pad_len > 0: # need to pad - if len(ram_segments) > 0 and pad_len > self.SEG_HEADER_LEN: - pad_segment = ram_segments[0].split_image(pad_len) - if len(ram_segments[0].data) == 0: - ram_segments.pop(0) - else: - pad_segment = ImageSegment(0, b"\x00" * pad_len, f.tell()) - checksum = self.save_segment(f, pad_segment, checksum) + if self.ram_only_header: + # write RAM segments first in order to get only RAM segments quantity + # and checksum (ROM bootloader will only care for RAM segments and its + # correct checksums) + for segment in ram_segments: + checksum = self.save_segment(f, segment, checksum) total_segments += 1 - else: + self.append_checksum(f, checksum) + + # reversing to match the same section order from linker script + flash_segments.reverse() + for segment in flash_segments: + pad_len = get_alignment_data_needed(segment) + while pad_len > 0: + pad_segment = ImageSegment(0, b"\x00" * pad_len, f.tell()) + self.save_segment(f, pad_segment) + total_segments += 1 + pad_len = get_alignment_data_needed(segment) # write the flash segment assert ( f.tell() + 8 ) % self.IROM_ALIGN == segment.addr % self.IROM_ALIGN - checksum = self.save_flash_segment(f, segment, checksum) - flash_segments.pop(0) + # save the flash segment but not saving its checksum neither + # saving the number of flash segments, since ROM bootloader + # should "not see" them + self.save_flash_segment(f, segment) + total_segments += 1 + else: # not self.ram_only_header + # try to fit each flash segment on a 64kB aligned boundary + # by padding with parts of the non-flash segments... + while len(flash_segments) > 0: + segment = flash_segments[0] + pad_len = get_alignment_data_needed(segment) + if pad_len > 0: # need to pad + if len(ram_segments) > 0 and pad_len > self.SEG_HEADER_LEN: + pad_segment = ram_segments[0].split_image(pad_len) + if len(ram_segments[0].data) == 0: + ram_segments.pop(0) + else: + pad_segment = ImageSegment(0, b"\x00" * pad_len, f.tell()) + checksum = self.save_segment(f, pad_segment, checksum) + total_segments += 1 + else: + # write the flash segment + assert ( + f.tell() + 8 + ) % self.IROM_ALIGN == segment.addr % self.IROM_ALIGN + checksum = self.save_flash_segment(f, segment, checksum) + flash_segments.pop(0) + total_segments += 1 + + # flash segments all written, so write any remaining RAM segments + for segment in ram_segments: + checksum = self.save_segment(f, segment, checksum) total_segments += 1 - - # flash segments all written, so write any remaining RAM segments - for segment in ram_segments: - checksum = self.save_segment(f, segment, checksum) - total_segments += 1 if self.secure_pad: # pad the image so that after signing it will end on a a 64KB boundary. @@ -759,8 +788,9 @@ def get_alignment_data_needed(segment): checksum = self.save_segment(f, pad_segment, checksum) total_segments += 1 - # done writing segments - self.append_checksum(f, checksum) + if not self.ram_only_header: + # done writing segments + self.append_checksum(f, checksum) image_length = f.tell() if self.secure_pad: @@ -769,7 +799,12 @@ def get_alignment_data_needed(segment): # kinda hacky: go back to the initial header and write the new segment count # that includes padding segments. This header is not checksummed f.seek(1) - f.write(bytes([total_segments])) + if self.ram_only_header: + # Update the header with the RAM segments quantity as it should be + # visible by the ROM bootloader + f.write(bytes([len(ram_segments)])) + else: + f.write(bytes([total_segments])) if self.append_digest: # calculate the SHA256 of the whole file and append it diff --git a/esptool/cmds.py b/esptool/cmds.py index a8d89b2ab..408c17f67 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -980,6 +980,11 @@ def elf2image(args): args.chip = "esp8266" print("Creating {} image...".format(args.chip)) + if args.ram_only_header: + print( + "RAM only visible in the header - only RAM segments are visible to the " + "ROM loader!" + ) if args.chip != "esp8266": image = CHIP_DEFS[args.chip].BOOTLOADER_IMAGE() @@ -990,6 +995,7 @@ def elf2image(args): image.min_rev = args.min_rev image.min_rev_full = args.min_rev_full image.max_rev_full = args.max_rev_full + image.ram_only_header = args.ram_only_header image.append_digest = args.append_digest elif args.version == "1": # ESP8266 image = ESP8266ROMFirmwareImage() diff --git a/test/test_imagegen.py b/test/test_imagegen.py index 1b0c98fc2..9756e3fc9 100755 --- a/test/test_imagegen.py +++ b/test/test_imagegen.py @@ -1,6 +1,7 @@ import hashlib import os import os.path +import re import struct import subprocess import sys @@ -113,7 +114,7 @@ def assertImageContainsSection(self, image, elf, section_name): f" segment(s) in bin image (image segments: {image.segments})" ) - def assertImageInfo(self, binpath, chip="esp8266"): + def assertImageInfo(self, binpath, chip="esp8266", assert_sha=False): """ Run esptool.py image_info on a binary file, assert no red flags about contents. @@ -126,7 +127,13 @@ def assertImageInfo(self, binpath, chip="esp8266"): except subprocess.CalledProcessError as e: print(e.output) raise - assert "invalid" not in output, "Checksum calculation should be valid" + assert re.search( + r"Checksum: [a-fA-F0-9]{2} \(valid\)", output + ), "Checksum calculation should be valid" + if assert_sha: + assert re.search( + r"Validation Hash: [a-fA-F0-9]{64} \(valid\)", output + ), "SHA256 should be valid" assert ( "warning" not in output.lower() ), "Should be no warnings in image_info output" @@ -267,7 +274,11 @@ def _test_elf2image(self, elfpath, binpath, extra_args=[]): try: self.run_elf2image("esp32", elfpath, extra_args=extra_args) image = esptool.bin_image.LoadFirmwareImage("esp32", binpath) - self.assertImageInfo(binpath, "esp32") + self.assertImageInfo( + binpath, + "esp32", + True if "--ram-only-header" not in extra_args else False, + ) return image finally: try_delete(binpath) @@ -322,6 +333,13 @@ def test_use_segments(self): image = self._test_elf2image(ELF, BIN, ["--use_segments"]) assert len(image.segments) == 2 + def test_ram_only_header(self): + ELF = "esp32-app-template.elf" + BIN = "esp32-app-template.bin" + # --ram-only-header produces just 2 visible segments in the bin + image = self._test_elf2image(ELF, BIN, ["--ram-only-header"]) + assert len(image.segments) == 2 + class TestESP8266FlashHeader(BaseTestCase): def test_2mb(self): From b1c778c06221dbe68b69a14152351124a8177741 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 1 Nov 2023 11:26:58 +0800 Subject: [PATCH 084/209] feat(esp32p4): Stub flasher support --- esptool/targets/esp32p4.py | 18 +- .../stub_flasher/stub_flasher_32p4.json | 7 + flasher_stub/Makefile | 8 +- flasher_stub/compare_stubs.py | 2 +- flasher_stub/include/soc_support.h | 14 + flasher_stub/ld/rom_32p4.ld | 619 ++++++++++++++++++ flasher_stub/ld/stub_32p4.ld | 43 ++ flasher_stub/stub_flasher.c | 2 +- flasher_stub/stub_write_flash.c | 2 + .../ram_helloworld/helloworld-esp32p4.bin | Bin 0 -> 128 bytes test/images/ram_helloworld/source/Makefile | 9 +- .../ram_helloworld/source/ld/app_32p4.ld | 32 + 12 files changed, 746 insertions(+), 10 deletions(-) create mode 100644 esptool/targets/stub_flasher/stub_flasher_32p4.json create mode 100644 flasher_stub/ld/rom_32p4.ld create mode 100644 flasher_stub/ld/stub_32p4.ld create mode 100644 test/images/ram_helloworld/helloworld-esp32p4.bin create mode 100644 test/images/ram_helloworld/source/ld/app_32p4.ld diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 853116029..333867a27 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -21,7 +21,7 @@ class ESP32P4ROM(ESP32ROM): DROM_MAP_START = 0x40000000 DROM_MAP_END = 0x44000000 - BOOTLOADER_FLASH_OFFSET = 0x0 + BOOTLOADER_FLASH_OFFSET = 0x2000 # First 2 sectors are reserved for FE purposes CHIP_DETECT_MAGIC_VALUE = [0x0] @@ -31,7 +31,13 @@ class ESP32P4ROM(ESP32ROM): EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044 MAC_EFUSE_REG = EFUSE_BASE + 0x044 - SPI_REG_BASE = 0x5008C000 + SPI_REG_BASE = 0x5008D000 # SPIMEM1 + SPI_USR_OFFS = 0x18 + SPI_USR1_OFFS = 0x1C + SPI_USR2_OFFS = 0x20 + SPI_MOSI_DLEN_OFFS = 0x24 + SPI_MISO_DLEN_OFFS = 0x28 + SPI_W0_OFFS = 0x58 EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030 # BLOCK0 read base address @@ -160,9 +166,10 @@ def change_baud(self, baud): ESPLoader.change_baud(self, baud) def _post_connect(self): - # ESP32-P4 doesn't have stub flasher support yet - self.stub_is_disabled = True - self.IS_STUB = False + pass + # TODO: Disable watchdogs when USB modes are supported in the stub + # if not self.sync_stub_detected: # Don't run if stub is reused + # self.disable_watchdogs() class ESP32P4StubLoader(ESP32P4ROM): @@ -180,6 +187,7 @@ def __init__(self, rom_loader): self.secure_download_mode = rom_loader.secure_download_mode self._port = rom_loader._port self._trace_enabled = rom_loader._trace_enabled + self.cache = rom_loader.cache self.flush_input() # resets _slip_reader diff --git a/esptool/targets/stub_flasher/stub_flasher_32p4.json b/esptool/targets/stub_flasher/stub_flasher_32p4.json new file mode 100644 index 000000000..6ed0687a3 --- /dev/null +++ b/esptool/targets/stub_flasher/stub_flasher_32p4.json @@ -0,0 +1,7 @@ +{ + "entry": 1341195718, + "text": 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+ "text_start": 1341194240, + "data": "DAD1T+4I8U86CfFPkgnxTzYK8U+iCvFPUArxT7YH8U/yCfFPMgrxT6YJ8U9mB/FP2gnxT2YH8U/ICPFPDAnxTzoJ8U+SCfFP2gjxTyAI8U9QCPFP1gjxT/oM8U86CfFPugvxT64M8U+yBvFP2AzxT7IG8U+yBvFPsgbxT7IG8U+yBvFPsgbxT7IG8U+yBvFPVgvxT7IG8U/WC/FPrgzxTw==", + "data_start": 1341533096 +} \ No newline at end of file diff --git a/flasher_stub/Makefile b/flasher_stub/Makefile index 307944ae8..8f4948c50 100644 --- a/flasher_stub/Makefile +++ b/flasher_stub/Makefile @@ -69,6 +69,7 @@ STUB_ELF_32H2_BETA_2 = $(BUILD_DIR)/$(STUB)_32h2beta2.elf STUB_ELF_32C2 = $(BUILD_DIR)/$(STUB)_32c2.elf STUB_ELF_32C6 = $(BUILD_DIR)/$(STUB)_32c6.elf STUB_ELF_32H2 = $(BUILD_DIR)/$(STUB)_32h2.elf +STUB_ELF_32P4 = $(BUILD_DIR)/$(STUB)_32p4.elf STUBS_ELF = ifneq ($(WITHOUT_ESP8266),1) @@ -92,7 +93,8 @@ STUBS_ELF += \ $(STUB_ELF_32H2_BETA_2) \ $(STUB_ELF_32C2) \ $(STUB_ELF_32C6) \ - $(STUB_ELF_32H2) + $(STUB_ELF_32H2) \ + $(STUB_ELF_32P4) endif .PHONY: all clean install @@ -171,5 +173,9 @@ $(STUB_ELF_32H2): $(SRCS) $(BUILD_DIR) ld/stub_32h2.ld @echo " CC(32H2) $^ -> $@" $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32H2=1 -Tstub_32h2.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) +$(STUB_ELF_32P4): $(SRCS) $(BUILD_DIR) ld/stub_32p4.ld + @echo " CC(32P4) $^ -> $@" + $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32P4=1 -Tstub_32p4.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + clean: $(Q) rm -rf $(BUILD_DIR) diff --git a/flasher_stub/compare_stubs.py b/flasher_stub/compare_stubs.py index a7b68d01f..6c8bb7f11 100755 --- a/flasher_stub/compare_stubs.py +++ b/flasher_stub/compare_stubs.py @@ -66,7 +66,7 @@ def diff(path_to_new, path_to_old): if __name__ == "__main__": same = True - for chip in [n for n in esptool.CHIP_LIST if n != "esp32p4"]: + for chip in esptool.CHIP_LIST: print("Comparing {} stub: ".format(chip), end="") chip = chip.replace("esp", "") diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index ace371337..6a5dd4632 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -55,6 +55,13 @@ #define IS_RISCV 1 #endif // ESP32H2 +#ifdef ESP32P4 +// TODO: Add support for USB modes when MP is available +// #define WITH_USB_JTAG_SERIAL 1 +// #define WITH_USB_OTG 1 +#define IS_RISCV 1 +#endif // ESP32P4 + // Increase CPU freq to speed up read/write operations over USB // Temporarily disabled on the S3 due to stability issues, will be fixed in the next minor release #define USE_MAX_CPU_FREQ ((WITH_USB_JTAG_SERIAL || WITH_USB_OTG) && !ESP32S3) @@ -154,6 +161,13 @@ #define DR_REG_LP_WDT_BASE 0x600B1C00 #endif +#ifdef ESP32P4 +#define UART_BASE_REG 0x500CA000 /* UART0 */ +#define SPI_BASE_REG 0x5008D000 /* SPI peripheral 1, used for SPI flash */ +#define SPI0_BASE_REG 0x5008C000 /* SPI peripheral 0, inner state machine */ +#define GPIO_BASE_REG 0x500E0000 +#endif + /********************************************************** * UART peripheral * diff --git a/flasher_stub/ld/rom_32p4.ld b/flasher_stub/ld/rom_32p4.ld new file mode 100644 index 000000000..51ac8cded --- /dev/null +++ b/flasher_stub/ld/rom_32p4.ld @@ -0,0 +1,619 @@ +/* ROM function interface esp32p4.rom.ld for esp32p4 + * + * + * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum f6516bd9708d890f63db87f8aed53ca7 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +PROVIDE ( SPIWrite = esp_rom_spiflash_write); +PROVIDE ( SPI_read_status_high = esp_rom_spiflash_read_statushigh); +PROVIDE ( SPI_write_status = esp_rom_spiflash_write_status); +PROVIDE ( SPIRead = esp_rom_spiflash_read); +PROVIDE ( SPIParamCfg = esp_rom_spiflash_config_param); +PROVIDE ( SPIEraseChip = esp_rom_spiflash_erase_chip); +PROVIDE ( SPIEraseSector = esp_rom_spiflash_erase_sector); +PROVIDE ( SPIEraseBlock = esp_rom_spiflash_erase_block); +PROVIDE ( SPI_Write_Encrypt_Enable = esp_rom_spiflash_write_encrypted_enable); +PROVIDE ( SPI_Write_Encrypt_Disable = esp_rom_spiflash_write_encrypted_disable); +PROVIDE ( SPI_Encrypt_Write = esp_rom_spiflash_write_encrypted); + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x4fc00018; +rtc_get_wakeup_cause = 0x4fc0001c; +pmu_enable_unhold_pads = 0x4fc00020; +ets_printf = 0x4fc00024; +ets_install_putc1 = 0x4fc00028; +ets_install_putc2 = 0x4fc0002c; +ets_install_uart_printf = 0x4fc00030; +ets_install_usb_printf = 0x4fc00034; +ets_get_printf_channel = 0x4fc00038; +ets_delay_us = 0x4fc0003c; +ets_get_cpu_frequency = 0x4fc00040; +ets_update_cpu_frequency = 0x4fc00044; +ets_install_lock = 0x4fc00048; +UartRxString = 0x4fc0004c; +UartGetCmdLn = 0x4fc00050; +uart_tx_one_char = 0x4fc00054; +uart_tx_one_char2 = 0x4fc00058; +uart_tx_one_char3 = 0x4fc0005c; +uart_rx_one_char = 0x4fc00060; +uart_rx_one_char_block = 0x4fc00064; +uart_rx_intr_handler = 0x4fc00068; +uart_rx_readbuff = 0x4fc0006c; +uartAttach = 0x4fc00070; +uart_tx_flush = 0x4fc00074; +uart_tx_wait_idle = 0x4fc00078; +uart_div_modify = 0x4fc0007c; +ets_write_char_uart = 0x4fc00080; +uart_tx_switch = 0x4fc00084; +uart_buff_switch = 0x4fc00088; +roundup2 = 0x4fc0008c; +multofup = 0x4fc00090; +software_reset = 0x4fc00094; +software_reset_cpu = 0x4fc00098; +ets_clk_assist_debug_clock_enable = 0x4fc0009c; +clear_super_wdt_reset_flag = 0x4fc000a0; +disable_default_watchdog = 0x4fc000a4; +ets_set_appcpu_boot_addr = 0x4fc000a8; +send_packet = 0x4fc000ac; +recv_packet = 0x4fc000b0; +GetUartDevice = 0x4fc000b4; +UartDwnLdProc = 0x4fc000b8; +GetSecurityInfoProc = 0x4fc000bc; +Uart_Init = 0x4fc000c0; +ets_set_user_start = 0x4fc000c4; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4fc1fffc; +ets_ops_table_ptr = 0x4ff3fff4; +g_saved_pc = 0x4ff3fff8; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x4fc000c8; +mz_free = 0x4fc000cc; +tdefl_compress = 0x4fc000d0; +tdefl_compress_buffer = 0x4fc000d4; +tdefl_compress_mem_to_heap = 0x4fc000d8; +tdefl_compress_mem_to_mem = 0x4fc000dc; +tdefl_compress_mem_to_output = 0x4fc000e0; +tdefl_get_adler32 = 0x4fc000e4; +tdefl_get_prev_return_status = 0x4fc000e8; +tdefl_init = 0x4fc000ec; +tdefl_write_image_to_png_file_in_memory = 0x4fc000f0; +tdefl_write_image_to_png_file_in_memory_ex = 0x4fc000f4; +tinfl_decompress = 0x4fc000f8; +tinfl_decompress_mem_to_callback = 0x4fc000fc; +tinfl_decompress_mem_to_heap = 0x4fc00100; +tinfl_decompress_mem_to_mem = 0x4fc00104; + + +/*************************************** + Group spi_extmem_common + ***************************************/ + +/* Functions */ +esp_rom_spi_cmd_config = 0x4fc00108; +esp_rom_spi_cmd_start = 0x4fc0010c; +esp_rom_spi_set_op_mode = 0x4fc00110; +esp_rom_spi_set_dtr_swap_mode = 0x4fc00114; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x4fc00118; +esp_rom_spiflash_write_encrypted = 0x4fc0011c; +esp_rom_spiflash_write_encrypted_dest = 0x4fc00120; +esp_rom_spiflash_write_encrypted_enable = 0x4fc00124; +esp_rom_spiflash_write_encrypted_disable = 0x4fc00128; +esp_rom_spiflash_erase_chip = 0x4fc0012c; +_esp_rom_spiflash_erase_sector = 0x4fc00130; +_esp_rom_spiflash_erase_block = 0x4fc00134; +_esp_rom_spiflash_write = 0x4fc00138; +_esp_rom_spiflash_read = 0x4fc0013c; +_esp_rom_spiflash_unlock = 0x4fc00140; +_SPIEraseArea = 0x4fc00144; +_SPI_write_enable = 0x4fc00148; +esp_rom_spiflash_erase_sector = 0x4fc0014c; +esp_rom_spiflash_erase_block = 0x4fc00150; +esp_rom_spiflash_write = 0x4fc00154; +esp_rom_spiflash_read = 0x4fc00158; +esp_rom_spiflash_unlock = 0x4fc0015c; +SPIEraseArea = 0x4fc00160; +SPI_write_enable = 0x4fc00164; +esp_rom_spiflash_config_param = 0x4fc00168; +esp_rom_spiflash_read_user_cmd = 0x4fc0016c; +esp_rom_spiflash_select_qio_pins = 0x4fc00170; +esp_rom_spi_flash_auto_sus_res = 0x4fc00174; +esp_rom_spi_flash_send_resume = 0x4fc00178; +esp_rom_spi_flash_update_id = 0x4fc0017c; +esp_rom_spiflash_config_clk = 0x4fc00180; +esp_rom_spiflash_config_readmode = 0x4fc00184; +esp_rom_spiflash_read_status = 0x4fc00188; +esp_rom_spiflash_read_statushigh = 0x4fc0018c; +esp_rom_spiflash_write_status = 0x4fc00190; +esp_rom_spiflash_write_disable = 0x4fc00194; +spi_cache_mode_switch = 0x4fc00198; +spi_common_set_dummy_output = 0x4fc0019c; +spi_common_set_flash_cs_timing = 0x4fc001a0; +esp_rom_spi_set_address_bit_len = 0x4fc001a4; +SPILock = 0x4fc001a8; +SPIMasterReadModeCnfig = 0x4fc001ac; +SPI_Common_Command = 0x4fc001b0; +SPI_WakeUp = 0x4fc001b4; +SPI_block_erase = 0x4fc001b8; +SPI_chip_erase = 0x4fc001bc; +SPI_init = 0x4fc001c0; +SPI_page_program = 0x4fc001c4; +SPI_read_data = 0x4fc001c8; +SPI_sector_erase = 0x4fc001cc; +SelectSpiFunction = 0x4fc001d0; +SetSpiDrvs = 0x4fc001d4; +Wait_SPI_Idle = 0x4fc001d8; +spi_dummy_len_fix = 0x4fc001dc; +Disable_QMode = 0x4fc001e0; +Enable_QMode = 0x4fc001e4; +spi_flash_attach = 0x4fc001e8; +spi_flash_get_chip_size = 0x4fc001ec; +spi_flash_guard_set = 0x4fc001f0; +spi_flash_guard_get = 0x4fc001f4; +spi_flash_read_encrypted = 0x4fc001f8; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4ff3ffec; +rom_spiflash_legacy_data = 0x4ff3ffe8; +g_flash_guard_ops = 0x4ff3fff0; + + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +systimer_hal_init = 0x4fc00228; +systimer_hal_deinit = 0x4fc0022c; +systimer_hal_set_tick_rate_ops = 0x4fc00230; +systimer_hal_get_counter_value = 0x4fc00234; +systimer_hal_get_time = 0x4fc00238; +systimer_hal_set_alarm_target = 0x4fc0023c; +systimer_hal_set_alarm_period = 0x4fc00240; +systimer_hal_get_alarm_value = 0x4fc00244; +systimer_hal_enable_alarm_int = 0x4fc00248; +systimer_hal_on_apb_freq_update = 0x4fc0024c; +systimer_hal_counter_value_advance = 0x4fc00250; +systimer_hal_enable_counter = 0x4fc00254; +systimer_hal_select_alarm_mode = 0x4fc00258; +systimer_hal_connect_alarm_counter = 0x4fc0025c; +systimer_hal_counter_can_stall_by_cpu = 0x4fc00260; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_L1_ICache_Line_Size = 0x4fc003c4; +Cache_Get_L1_DCache_Line_Size = 0x4fc003c8; +Cache_Get_L2_Cache_Line_Size = 0x4fc003cc; +Cache_Get_Mode = 0x4fc003d0; +Cache_Set_L2_Cache_Mode = 0x4fc003d4; +Cache_Address_Through_Cache = 0x4fc003d8; +ROM_Boot_Cache_Init = 0x4fc003dc; +Cache_Sync_Addr = 0x4fc003e0; +Cache_Invalidate_Addr = 0x4fc003e4; +Cache_Invalidate_Addr_Gid = 0x4fc003e8; +Cache_Clean_Addr = 0x4fc003ec; +Cache_Clean_Addr_Gid = 0x4fc003f0; +Cache_WriteBack_Addr = 0x4fc003f4; +Cache_WriteBack_Addr_Gid = 0x4fc003f8; +Cache_WriteBack_Invalidate_Addr = 0x4fc003fc; +Cache_WriteBack_Invalidate_Addr_Gid = 0x4fc00400; +Cache_Invalidate_All = 0x4fc00404; +Cache_Invalidate_All_Gid = 0x4fc00408; +Cache_Clean_All = 0x4fc0040c; +Cache_Clean_All_Gid = 0x4fc00410; +Cache_WriteBack_All = 0x4fc00414; +Cache_WriteBack_All_Gid = 0x4fc00418; +Cache_WriteBack_Invalidate_All = 0x4fc0041c; +Cache_WriteBack_Invalidate_All_Gid = 0x4fc00420; +Cache_Mask_All = 0x4fc00424; +Cache_Suspend_L1_CORE0_ICache_Autoload = 0x4fc00428; +Cache_Resume_L1_CORE0_ICache_Autoload = 0x4fc0042c; +Cache_Suspend_L1_CORE1_ICache_Autoload = 0x4fc00430; +Cache_Resume_L1_CORE1_ICache_Autoload = 0x4fc00434; +Cache_Suspend_L1_DCache_Autoload = 0x4fc00438; +Cache_Resume_L1_DCache_Autoload = 0x4fc0043c; +Cache_Suspend_L2_Cache_Autoload = 0x4fc00440; +Cache_Resume_L2_Cache_Autoload = 0x4fc00444; +Cache_Start_L1_CORE0_ICache_Preload = 0x4fc00448; +Cache_L1_CORE0_ICache_Preload_Done = 0x4fc0044c; +Cache_End_L1_CORE0_ICache_Preload = 0x4fc00450; +Cache_Start_L1_CORE1_ICache_Preload = 0x4fc00454; +Cache_L1_CORE1_ICache_Preload_Done = 0x4fc00458; +Cache_End_L1_CORE1_ICache_Preload = 0x4fc0045c; +Cache_Start_L1_DCache_Preload = 0x4fc00460; +Cache_L1_DCache_Preload_Done = 0x4fc00464; +Cache_End_L1_DCache_Preload = 0x4fc00468; +Cache_Start_L2_Cache_Preload = 0x4fc0046c; +Cache_L2_Cache_Preload_Done = 0x4fc00470; +Cache_End_L2_Cache_Preload = 0x4fc00474; +Cache_Config_L1_CORE0_ICache_Autoload = 0x4fc00478; +Cache_Enable_L1_CORE0_ICache_Autoload = 0x4fc0047c; +Cache_Disable_L1_CORE0_ICache_Autoload = 0x4fc00480; +Cache_Config_L1_CORE1_ICache_Autoload = 0x4fc00484; +Cache_Enable_L1_CORE1_ICache_Autoload = 0x4fc00488; +Cache_Disable_L1_CORE1_ICache_Autoload = 0x4fc0048c; +Cache_Config_L1_DCache_Autoload = 0x4fc00490; +Cache_Enable_L1_DCache_Autoload = 0x4fc00494; +Cache_Disable_L1_DCache_Autoload = 0x4fc00498; +Cache_Config_L2_Cache_Autoload = 0x4fc0049c; +Cache_Enable_L2_Cache_Autoload = 0x4fc004a0; +Cache_Disable_L2_Cache_Autoload = 0x4fc004a4; +Cache_Enable_L1_CORE0_ICache_PreLock = 0x4fc004a8; +Cache_Disable_L1_CORE0_ICache_PreLock = 0x4fc004ac; +Cache_Enable_L1_CORE1_ICache_PreLock = 0x4fc004b0; +Cache_Disable_L1_CORE1_ICache_PreLock = 0x4fc004b4; +Cache_Enable_L1_DCache_PreLock = 0x4fc004b8; +Cache_Disable_L1_DCache_PreLock = 0x4fc004bc; +Cache_Enable_L2_Cache_PreLock = 0x4fc004c0; +Cache_Disable_L2_Cache_PreLock = 0x4fc004c4; +Cache_Lock_Addr = 0x4fc004c8; +Cache_Unlock_Addr = 0x4fc004cc; +Cache_Disable_L1_CORE0_ICache = 0x4fc004d0; +Cache_Enable_L1_CORE0_ICache = 0x4fc004d4; +Cache_Suspend_L1_CORE0_ICache = 0x4fc004d8; +Cache_Resume_L1_CORE0_ICache = 0x4fc004dc; +Cache_Disable_L1_CORE1_ICache = 0x4fc004e0; +Cache_Enable_L1_CORE1_ICache = 0x4fc004e4; +Cache_Suspend_L1_CORE1_ICache = 0x4fc004e8; +Cache_Resume_L1_CORE1_ICache = 0x4fc004ec; +Cache_Disable_L1_DCache = 0x4fc004f0; +Cache_Enable_L1_DCache = 0x4fc004f4; +Cache_Suspend_L1_DCache = 0x4fc004f8; +Cache_Resume_L1_DCache = 0x4fc004fc; +Cache_Disable_L2_Cache = 0x4fc00500; +Cache_Enable_L2_Cache = 0x4fc00504; +Cache_Suspend_L2_Cache = 0x4fc00508; +Cache_Resume_L2_Cache = 0x4fc0050c; +Cache_FLASH_MMU_Init = 0x4fc00510; +Cache_PSRAM_MMU_Init = 0x4fc00514; +Cache_FLASH_MMU_Set = 0x4fc00518; +Cache_FLASH_MMU_Set_Secure = 0x4fc0051c; +Cache_PSRAM_MMU_Set = 0x4fc00520; +Cache_PSRAM_MMU_Set_Secure = 0x4fc00524; +Cache_Count_Flash_Pages = 0x4fc00528; +Cache_Flash_To_SPIRAM_Copy = 0x4fc0052c; +Cache_Travel_Tag_Memory = 0x4fc00530; +Cache_Travel_Tag_Memory2 = 0x4fc00534; +Cache_Get_Virtual_Addr = 0x4fc00538; +Cache_Set_IDROM_MMU_Size = 0x4fc0053c; +flash2spiram_instruction_offset = 0x4fc00540; +flash2spiram_rodata_offset = 0x4fc00544; +flash_instr_rodata_start_page = 0x4fc00548; +flash_instr_rodata_end_page = 0x4fc0054c; +Cache_Set_IDROM_MMU_Info = 0x4fc00550; +Cache_Get_IROM_MMU_End = 0x4fc00554; +Cache_Get_DROM_MMU_End = 0x4fc00558; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4ff3ffdc; +rom_cache_internal_table_ptr = 0x4ff3ffd8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x4fc0055c; +ets_clk_get_cpu_freq = 0x4fc00560; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_set_output_level = 0x4fc00564; +gpio_get_input_level = 0x4fc00568; +gpio_matrix_in = 0x4fc0056c; +gpio_matrix_out = 0x4fc00570; +gpio_bypass_matrix_in = 0x4fc00574; +gpio_output_disable = 0x4fc00578; +gpio_output_enable = 0x4fc0057c; +gpio_pad_input_disable = 0x4fc00580; +gpio_pad_input_enable = 0x4fc00584; +gpio_pad_pulldown = 0x4fc00588; +gpio_pad_pullup = 0x4fc0058c; +gpio_pad_select_gpio = 0x4fc00590; +gpio_pad_set_drv = 0x4fc00594; +gpio_pad_unhold = 0x4fc00598; +gpio_pad_hold = 0x4fc0059c; +gpio_lppad_select_mux = 0x4fc005a0; +gpio_ded_pad_set_drv = 0x4fc005a4; +gpio_ded_pad_pullup = 0x4fc005a8; +gpio_ded_pad_pulldown = 0x4fc005ac; +gpio_ded_pad_hold = 0x4fc005b0; +gpio_ded_pad_unhold = 0x4fc005b4; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x4fc005b8; +esprv_intc_int_set_threshold = 0x4fc005bc; +esprv_intc_int_enable = 0x4fc005c0; +esprv_intc_int_disable = 0x4fc005c4; +esprv_intc_int_set_type = 0x4fc005c8; +PROVIDE( intr_handler_set = 0x4fc005cc ); +intr_matrix_set = 0x4fc005d0; +ets_intr_lock = 0x4fc005d4; +ets_intr_unlock = 0x4fc005d8; +ets_isr_attach = 0x4fc005dc; +ets_isr_mask = 0x4fc005e0; +ets_isr_unmask = 0x4fc005e4; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x4fc005e8; +MD5Init = 0x4fc005ec; +MD5Update = 0x4fc005f0; +MD5Final = 0x4fc005f4; +crc32_le = 0x4fc005f8; +crc16_le = 0x4fc005fc; +crc8_le = 0x4fc00600; +crc32_be = 0x4fc00604; +crc16_be = 0x4fc00608; +crc8_be = 0x4fc0060c; +esp_crc8 = 0x4fc00610; +ets_sha_enable = 0x4fc00614; +ets_sha_disable = 0x4fc00618; +ets_sha_get_state = 0x4fc0061c; +ets_sha_init = 0x4fc00620; +ets_sha_process = 0x4fc00624; +ets_sha_starts = 0x4fc00628; +ets_sha_update = 0x4fc0062c; +ets_sha_finish = 0x4fc00630; +ets_sha_clone = 0x4fc00634; +ets_hmac_enable = 0x4fc00638; +ets_hmac_disable = 0x4fc0063c; +ets_hmac_calculate_message = 0x4fc00640; +ets_hmac_calculate_downstream = 0x4fc00644; +ets_hmac_invalidate_downstream = 0x4fc00648; +ets_jtag_enable_temporarily = 0x4fc0064c; +ets_aes_enable = 0x4fc00650; +ets_aes_disable = 0x4fc00654; +ets_aes_setkey = 0x4fc00658; +ets_aes_block = 0x4fc0065c; +ets_aes_setkey_dec = 0x4fc00660; +ets_aes_setkey_enc = 0x4fc00664; +ets_bigint_enable = 0x4fc00668; +ets_bigint_disable = 0x4fc0066c; +ets_bigint_multiply = 0x4fc00670; +ets_bigint_modmult = 0x4fc00674; +ets_bigint_modexp = 0x4fc00678; +ets_bigint_wait_finish = 0x4fc0067c; +ets_bigint_getz = 0x4fc00680; +ets_ds_enable = 0x4fc00684; +ets_ds_disable = 0x4fc00688; +ets_ds_start_sign = 0x4fc0068c; +ets_ds_is_busy = 0x4fc00690; +ets_ds_finish_sign = 0x4fc00694; +ets_ds_encrypt_params = 0x4fc00698; +ets_mgf1_sha256 = 0x4fc0069c; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4fc1fff8; +crc16_le_table_ptr = 0x4fc1fff4; +crc8_le_table_ptr = 0x4fc1fff0; +crc32_be_table_ptr = 0x4fc1ffec; +crc16_be_table_ptr = 0x4fc1ffe8; +crc8_be_table_ptr = 0x4fc1ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x4fc006a0; +ets_efuse_program = 0x4fc006a4; +ets_efuse_clear_program_registers = 0x4fc006a8; +ets_efuse_write_key = 0x4fc006ac; +ets_efuse_get_read_register_address = 0x4fc006b0; +ets_efuse_get_key_purpose = 0x4fc006b4; +ets_efuse_key_block_unused = 0x4fc006b8; +ets_efuse_find_unused_key_block = 0x4fc006bc; +ets_efuse_rs_calculate = 0x4fc006c0; +ets_efuse_count_unused_key_blocks = 0x4fc006c4; +ets_efuse_secure_boot_enabled = 0x4fc006c8; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4fc006cc; +ets_efuse_cache_encryption_enabled = 0x4fc006d0; +ets_efuse_download_modes_disabled = 0x4fc006d4; +ets_efuse_find_purpose = 0x4fc006d8; +ets_efuse_force_send_resume = 0x4fc006dc; +ets_efuse_get_flash_delay_us = 0x4fc006e0; +ets_efuse_get_uart_print_control = 0x4fc006e4; +ets_efuse_direct_boot_mode_disabled = 0x4fc006e8; +ets_efuse_security_download_modes_enabled = 0x4fc006ec; +ets_efuse_jtag_disabled = 0x4fc006f0; +ets_efuse_usb_print_is_disabled = 0x4fc006f4; +ets_efuse_usb_download_mode_disabled = 0x4fc006f8; +ets_efuse_usb_device_disabled = 0x4fc006fc; +ets_efuse_get_km_huk_gen_state = 0x4fc00700; +ets_efuse_get_km_deploy_only_once = 0x4fc00704; +ets_efuse_get_force_use_km_key = 0x4fc00708; +ets_efuse_xts_key_length_256 = 0x4fc0070c; +ets_efuse_get_km_key_lock = 0x4fc00710; + + +/*************************************** + Group key_mgr + ***************************************/ + +/* Functions */ +esp_rom_check_recover_key = 0x4fc00714; +esp_rom_km_huk_conf = 0x4fc00718; +esp_rom_km_huk_risk = 0x4fc0071c; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x4fc00720; +ets_rsa_pss_verify = 0x4fc00724; +ets_ecdsa_verify = 0x4fc00728; +ets_secure_boot_verify_bootloader_with_keys = 0x4fc0072c; +ets_secure_boot_verify_signature = 0x4fc00730; +ets_secure_boot_read_key_digests = 0x4fc00734; +ets_secure_boot_revoke_public_key_digest = 0x4fc00738; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x4fc008b0; +usb_serial_device_rx_one_char_block = 0x4fc008b4; +usb_serial_device_tx_flush = 0x4fc008b8; +usb_serial_device_tx_one_char = 0x4fc008bc; + + +/*************************************** + Group usb_dwcotg_uart + ***************************************/ + +/* Functions */ +Uart_Init_USB = 0x4fc008c0; +usb_serial_otg_rx_one_char = 0x4fc008c4; +usb_serial_otg_rx_one_char_block = 0x4fc008c8; +usb_serial_otg_tx_flush = 0x4fc008cc; +usb_serial_otg_tx_one_char = 0x4fc008d0; +/* Data (.data, .bss, .rodata) */ +uart_acm_dev = 0x4ff3ffd4; + + +/*************************************** + Group usb_dwcotg_module + ***************************************/ + +/* Functions */ +cdc_acm_class_handle_req = 0x4fc008d4; +cdc_acm_init = 0x4fc008d8; +cdc_acm_fifo_fill = 0x4fc008dc; +cdc_acm_rx_fifo_cnt = 0x4fc008e0; +cdc_acm_fifo_read = 0x4fc008e4; +cdc_acm_irq_tx_enable = 0x4fc008e8; +cdc_acm_irq_tx_disable = 0x4fc008ec; +cdc_acm_irq_state_enable = 0x4fc008f0; +cdc_acm_irq_state_disable = 0x4fc008f4; +cdc_acm_irq_tx_ready = 0x4fc008f8; +cdc_acm_irq_rx_enable = 0x4fc008fc; +cdc_acm_irq_rx_disable = 0x4fc00900; +cdc_acm_irq_rx_ready = 0x4fc00904; +cdc_acm_irq_is_pending = 0x4fc00908; +cdc_acm_irq_callback_set = 0x4fc0090c; +cdc_acm_line_ctrl_set = 0x4fc00910; +cdc_acm_line_ctrl_get = 0x4fc00914; +cdc_acm_poll_out = 0x4fc00918; +chip_usb_dw_did_persist = 0x4fc0091c; +chip_usb_dw_init = 0x4fc00920; +chip_usb_detach = 0x4fc00924; +chip_usb_dw_prepare_persist = 0x4fc00928; +chip_usb_get_persist_flags = 0x4fc0092c; +chip_usb_set_persist_flags = 0x4fc00930; +cpio_start = 0x4fc00934; +cpio_feed = 0x4fc00938; +cpio_done = 0x4fc0093c; +cpio_destroy = 0x4fc00940; +dfu_flash_init = 0x4fc00944; +dfu_flash_erase = 0x4fc00948; +dfu_flash_program = 0x4fc0094c; +dfu_flash_read = 0x4fc00950; +dfu_flash_attach = 0x4fc00954; +dfu_cpio_callback = 0x4fc00958; +dfu_updater_get_err = 0x4fc0095c; +dfu_updater_clear_err = 0x4fc00960; +dfu_updater_enable = 0x4fc00964; +dfu_updater_begin = 0x4fc00968; +dfu_updater_feed = 0x4fc0096c; +dfu_updater_end = 0x4fc00970; +dfu_updater_set_raw_addr = 0x4fc00974; +dfu_updater_flash_read = 0x4fc00978; +usb_dc_prepare_persist = 0x4fc0097c; +usb_dw_isr_handler = 0x4fc00980; +usb_dc_attach = 0x4fc00984; +usb_dc_detach = 0x4fc00988; +usb_dc_reset = 0x4fc0098c; +usb_dc_set_address = 0x4fc00990; +usb_dc_ep_check_cap = 0x4fc00994; +usb_dc_ep_configure = 0x4fc00998; +usb_dc_ep_set_stall = 0x4fc0099c; +usb_dc_ep_clear_stall = 0x4fc009a0; +usb_dc_ep_halt = 0x4fc009a4; +usb_dc_ep_is_stalled = 0x4fc009a8; +usb_dc_ep_enable = 0x4fc009ac; +usb_dc_ep_disable = 0x4fc009b0; +usb_dc_ep_flush = 0x4fc009b4; +usb_dc_ep_write_would_block = 0x4fc009b8; +usb_dc_ep_write = 0x4fc009bc; +usb_dc_ep_read_wait = 0x4fc009c0; +usb_dc_ep_read_continue = 0x4fc009c4; +usb_dc_ep_read = 0x4fc009c8; +usb_dc_ep_set_callback = 0x4fc009cc; +usb_dc_set_status_callback = 0x4fc009d0; +usb_dc_ep_mps = 0x4fc009d4; +usb_dc_check_poll_for_interrupts = 0x4fc009d8; +mac_addr_to_serial_str_desc = 0x4fc009dc; +usb_set_current_descriptor = 0x4fc009e0; +usb_get_descriptor = 0x4fc009e4; +usb_dev_resume = 0x4fc009e8; +usb_dev_get_configuration = 0x4fc009ec; +usb_set_config = 0x4fc009f0; +usb_deconfig = 0x4fc009f4; +usb_enable = 0x4fc009f8; +usb_disable = 0x4fc009fc; +usb_write_would_block = 0x4fc00a00; +usb_write = 0x4fc00a04; +usb_read = 0x4fc00a08; +usb_ep_set_stall = 0x4fc00a0c; +usb_ep_clear_stall = 0x4fc00a10; +usb_ep_read_wait = 0x4fc00a14; +usb_ep_read_continue = 0x4fc00a18; +usb_transfer_ep_callback = 0x4fc00a1c; +usb_transfer = 0x4fc00a20; +usb_cancel_transfer = 0x4fc00a24; +usb_transfer_sync = 0x4fc00a28; +usb_dfu_set_detach_cb = 0x4fc00a2c; +dfu_class_handle_req = 0x4fc00a30; +dfu_status_cb = 0x4fc00a34; +dfu_custom_handle_req = 0x4fc00a38; +usb_dfu_init = 0x4fc00a3c; +usb_dfu_force_detach = 0x4fc00a40; +usb_dev_deinit = 0x4fc00a44; +usb_dw_ctrl_deinit = 0x4fc00a48; +/* Data (.data, .bss, .rodata) */ +s_usb_osglue = 0x4ff3ffc8; diff --git a/flasher_stub/ld/stub_32p4.ld b/flasher_stub/ld/stub_32p4.ld new file mode 100644 index 000000000..84052ee17 --- /dev/null +++ b/flasher_stub/ld/stub_32p4.ld @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) PTE LTD + * All rights reserved + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin + * Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +MEMORY { + iram : org = 0x4FF10000, len = 0x4000 + dram : org = 0x4FF50000, len = 0x18000 +} + +ENTRY(stub_main) + +SECTIONS { + .text : ALIGN(4) { + *(.literal) + *(.text .text.*) + } > iram + + .bss : ALIGN(4) { + _bss_start = ABSOLUTE(.); + *(.bss) + _bss_end = ABSOLUTE(.); + } > dram + + .data : ALIGN(4) { + *(.data) + *(.rodata .rodata.*) + } > dram +} + +INCLUDE "rom_32p4.ld" diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c index 1ee47b1ee..b3e86d6b5 100644 --- a/flasher_stub/stub_flasher.c +++ b/flasher_stub/stub_flasher.c @@ -494,7 +494,7 @@ void stub_main() spi_flash_attach(); #else -#if !ESP32C2 && !ESP32C6 && !ESP32H2 +#if !ESP32C2 && !ESP32C6 && !ESP32H2 && !ESP32P4 uint32_t spiconfig = ets_efuse_get_spiconfig(); #else // ESP32C2/ESP32C6 doesn't support get spiconfig. diff --git a/flasher_stub/stub_write_flash.c b/flasher_stub/stub_write_flash.c index d2127b743..026f14e8f 100644 --- a/flasher_stub/stub_write_flash.c +++ b/flasher_stub/stub_write_flash.c @@ -102,6 +102,8 @@ static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x3fcdfff static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x3fcdfff0; #elif ESP32H2 static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x4084fff0; +#elif ESP32P4 +static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x4ff3ffec; #else static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x3ffae270; #endif diff --git a/test/images/ram_helloworld/helloworld-esp32p4.bin b/test/images/ram_helloworld/helloworld-esp32p4.bin new file mode 100644 index 0000000000000000000000000000000000000000..20dcef2b6fe17eccce3a6fd24f4a1ebddb7d5485 GIT binary patch literal 128 zcmaFK!~g`}{NDjdArSNbe-OzC5|aQj90iq*upKjJ`R*^w%EB<6;ne@<4GD}__cJhj z_ZI-ld!**%80BY $@" $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32H2=1 -Tapp_32h2.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) +$(APP_ELF_32P4): $(SRCS) $(BUILD_DIR) ld/app_32p4.ld + @echo " CC(32P4) $^ -> $@" + $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32P4=1 -Tapp_32p4.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + clean: $(Q) rm -rf $(BUILD_DIR) diff --git a/test/images/ram_helloworld/source/ld/app_32p4.ld b/test/images/ram_helloworld/source/ld/app_32p4.ld new file mode 100644 index 000000000..c758db9cd --- /dev/null +++ b/test/images/ram_helloworld/source/ld/app_32p4.ld @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +MEMORY { + iram : org = 0x4FF60000, len = 0x100 + dram : org = 0x4FF70000, len = 0x100 +} + +ENTRY(ram_main) + +SECTIONS { + .text : ALIGN(4) { + *(.literal) + *(.text .text.*) + } > iram + + .bss : ALIGN(4) { + _bss_start = ABSOLUTE(.); + *(.bss) + _bss_end = ABSOLUTE(.); + } > dram + + .data : ALIGN(4) { + *(.data) + *(.rodata .rodata.*) + } > dram +} + +INCLUDE "../../../../flasher_stub/ld/rom_32p4.ld" From 68343c97ce347f7abd02c0511dd92524fbc6fe14 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 1 Nov 2023 11:28:57 +0800 Subject: [PATCH 085/209] refactor(stub_flasher): Cleanup, make adding new targets easier --- esptool/loader.py | 4 +- esptool/targets/esp32.py | 2 - esptool/targets/esp32c3.py | 2 - esptool/targets/esp32c6.py | 2 - esptool/targets/esp32p4.py | 2 - esptool/targets/esp32s2.py | 2 - esptool/targets/esp32s3.py | 2 - flasher_stub/include/soc_support.h | 47 +++++++---- flasher_stub/ld/rom_32h2.ld | 7 +- flasher_stub/ld/stub_32.ld | 17 ---- flasher_stub/ld/stub_32c3.ld | 6 -- flasher_stub/ld/stub_32c6.ld | 17 ---- flasher_stub/ld/stub_32c6_beta.ld | 6 -- flasher_stub/ld/stub_32h2.ld | 6 -- flasher_stub/ld/stub_32h2_beta_1.ld | 6 -- flasher_stub/ld/stub_32h2_beta_2.ld | 6 -- flasher_stub/ld/stub_32p4.ld | 17 ---- flasher_stub/ld/stub_32s2.ld | 6 -- flasher_stub/ld/stub_32s3.ld | 6 -- flasher_stub/ld/stub_32s3_beta_2.ld | 6 -- flasher_stub/ld/stub_8266.ld | 17 ---- flasher_stub/stub_flasher.c | 79 ++++++++++--------- flasher_stub/stub_write_flash.c | 20 ++--- .../images/ram_helloworld/source/ld/app_32.ld | 17 ---- .../ram_helloworld/source/ld/app_32c2.ld | 7 -- .../ram_helloworld/source/ld/app_32c3.ld | 6 -- .../ram_helloworld/source/ld/app_32c6.ld | 6 -- .../ram_helloworld/source/ld/app_32h2.ld | 6 -- .../ram_helloworld/source/ld/app_32p4.ld | 6 -- .../ram_helloworld/source/ld/app_32s2.ld | 6 -- .../ram_helloworld/source/ld/app_32s3.ld | 6 -- .../ram_helloworld/source/ld/app_8266.ld | 17 ---- 32 files changed, 80 insertions(+), 282 deletions(-) diff --git a/esptool/loader.py b/esptool/loader.py index c45a45c37..bd1fcbab2 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -184,8 +184,6 @@ class ESPLoader(object): CHIP_NAME = "Espressif device" IS_STUB = False - FPGA_SLOW_BOOT = False - DEFAULT_PORT = "/dev/ttyUSB0" USES_RFC2217 = False @@ -628,7 +626,7 @@ def _construct_reset_strategy_sequence(self, mode): # This FPGA delay is for Espressif internal use if ( - self.FPGA_SLOW_BOOT + self.CHIP_NAME == "ESP32" and os.environ.get("ESPTOOL_ENV_FPGA", "").strip() == "1" ): delay = extra_delay = 7 diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index c4f372a7f..e9c66da52 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -17,8 +17,6 @@ class ESP32ROM(ESPLoader): IMAGE_CHIP_ID = 0 IS_STUB = False - FPGA_SLOW_BOOT = True - CHIP_DETECT_MAGIC_VALUE = [0x00F01D83] IROM_MAP_START = 0x400D0000 diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index 8a5005e04..47191b0c2 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -14,8 +14,6 @@ class ESP32C3ROM(ESP32ROM): CHIP_NAME = "ESP32-C3" IMAGE_CHIP_ID = 5 - FPGA_SLOW_BOOT = False - IROM_MAP_START = 0x42000000 IROM_MAP_END = 0x42800000 DROM_MAP_START = 0x3C000000 diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index 5c83d381b..c18bf9d1f 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -13,8 +13,6 @@ class ESP32C6ROM(ESP32C3ROM): CHIP_NAME = "ESP32-C6" IMAGE_CHIP_ID = 13 - FPGA_SLOW_BOOT = False - IROM_MAP_START = 0x42000000 IROM_MAP_END = 0x42800000 DROM_MAP_START = 0x42800000 diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 333867a27..23ff407c1 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -14,8 +14,6 @@ class ESP32P4ROM(ESP32ROM): CHIP_NAME = "ESP32-P4" IMAGE_CHIP_ID = 18 - FPGA_SLOW_BOOT = False - IROM_MAP_START = 0x40000000 IROM_MAP_END = 0x44000000 DROM_MAP_START = 0x40000000 diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py index 89d6b4e08..cd361f918 100644 --- a/esptool/targets/esp32s2.py +++ b/esptool/targets/esp32s2.py @@ -16,8 +16,6 @@ class ESP32S2ROM(ESP32ROM): CHIP_NAME = "ESP32-S2" IMAGE_CHIP_ID = 2 - FPGA_SLOW_BOOT = False - IROM_MAP_START = 0x40080000 IROM_MAP_END = 0x40B80000 DROM_MAP_START = 0x3F000000 diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 6e6a72119..3dc785216 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -19,8 +19,6 @@ class ESP32S3ROM(ESP32ROM): CHIP_DETECT_MAGIC_VALUE = [0x9] - FPGA_SLOW_BOOT = False - IROM_MAP_START = 0x42000000 IROM_MAP_END = 0x44000000 DROM_MAP_START = 0x3C000000 diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index 6a5dd4632..f57a740dc 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -63,11 +63,16 @@ #endif // ESP32P4 // Increase CPU freq to speed up read/write operations over USB -// Temporarily disabled on the S3 due to stability issues, will be fixed in the next minor release +// Disabled on the S3 due to stability issues, would require dbias adjustment. +// https://github.com/espressif/esptool/issues/832, https://github.com/espressif/esptool/issues/808 #define USE_MAX_CPU_FREQ ((WITH_USB_JTAG_SERIAL || WITH_USB_OTG) && !ESP32S3) +// Later chips don't support ets_efuse_get_spiconfig. +#define SUPPORT_CONFIG_SPI (ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 || ESP32C3 || ESP32H2BETA1 || ESP32H2BETA2 || ESP32C6BETA) + /********************************************************** * Per-SOC based peripheral register base addresses + * Sync with reg_base.h in ESP-IDF */ #ifdef ESP8266 #define UART_BASE_REG 0x60000000 /* UART0 */ @@ -380,21 +385,6 @@ * SYSTEM registers */ -#ifdef ESP32S3 -#define SYSTEM_CPU_PER_CONF_REG (SYSTEM_BASE_REG + 0x010) -#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) -#define SYSTEM_CPUPERIOD_SEL_V 0x3 -#define SYSTEM_CPUPERIOD_SEL_S 0 -#define SYSTEM_CPUPERIOD_MAX 1 // CPU_CLK frequency is 160 MHz - not actually max possible frequency, -// see https://github.com/espressif/esptool/issues/832 and https://github.com/espressif/esptool/issues/808 - -#define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x060) -#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) -#define SYSTEM_SOC_CLK_SEL_V 0x3 -#define SYSTEM_SOC_CLK_SEL_S 10 -#define SYSTEM_SOC_CLK_MAX 1 -#endif // ESP32S3 - #ifdef ESP32C3 #define SYSTEM_CPU_PER_CONF_REG (SYSTEM_BASE_REG + 0x008) #define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) @@ -450,3 +440,28 @@ #if ESP32S3_OR_LATER #define SECURITY_INFO_BYTES 20 #endif // ESP32S3_OR_LATER + +/********************************************************** + * Per-SOC address of the rom_spiflash_legacy_funcs symbol in ROM + * Can be retrieved with gdb: "info address rom_spiflash_legacy_funcs" + */ + +#if ESP32 || ESP32S2 || ESP32S3 +#define ROM_SPIFLASH_LEGACY 0x3ffae270 +#endif // ESP32 || ESP32S2 || ESP32S3 + +#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 +#define ROM_SPIFLASH_LEGACY 0x3fcdfff4 +#endif // ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 + +#if ESP32H2BETA1 || ESP32H2BETA2 +#define ROM_SPIFLASH_LEGACY 0x3fcdfff0 +#endif // ESP32H2BETA1 || ESP32H2BETA2 + +#if ESP32H2 +#define ROM_SPIFLASH_LEGACY 0x4084fff0 +#endif // ESP32H2 + +#if ESP32P4 +#define ROM_SPIFLASH_LEGACY 0x4ff3ffec +#endif // ESP32P4 diff --git a/flasher_stub/ld/rom_32h2.ld b/flasher_stub/ld/rom_32h2.ld index b736e491b..accb0adcf 100755 --- a/flasher_stub/ld/rom_32h2.ld +++ b/flasher_stub/ld/rom_32h2.ld @@ -1,8 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ /* ROM function interface esp32h2.rom.ld for esp32h2 * * @@ -22,7 +17,7 @@ PROVIDE ( SPI_read_status_high = esp_rom_spiflash_read_statushigh); PROVIDE ( SPI_write_status = esp_rom_spiflash_write_status); PROVIDE ( SPIRead = esp_rom_spiflash_read); PROVIDE ( SPIParamCfg = esp_rom_spiflash_config_param); -PROVIDE ( SPIEraseChip = esp_rom_spiflash_erase_chip); +PROVIDE ( SPIEraseChip = esp_rom_spiflash_erase_chip); PROVIDE ( SPIEraseSector = esp_rom_spiflash_erase_sector); PROVIDE ( SPIEraseBlock = esp_rom_spiflash_erase_block); PROVIDE ( SPI_Write_Encrypt_Enable = esp_rom_spiflash_write_encrypted_enable); diff --git a/flasher_stub/ld/stub_32.ld b/flasher_stub/ld/stub_32.ld index ca812c887..9ab825585 100644 --- a/flasher_stub/ld/stub_32.ld +++ b/flasher_stub/ld/stub_32.ld @@ -1,20 +1,3 @@ -/* - * Copyright (c) 2016 Cesanta Software Limited - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin - * Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - /* Note: stub is deliberately loaded close to the very top of available RAM, to reduce change of colliding with anything else... */ diff --git a/flasher_stub/ld/stub_32c3.ld b/flasher_stub/ld/stub_32c3.ld index b7c3e88aa..dc9d4201e 100644 --- a/flasher_stub/ld/stub_32c3.ld +++ b/flasher_stub/ld/stub_32c3.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40380000, len = 0x4000 dram : org = 0x3FC84000, len = 0x18000 diff --git a/flasher_stub/ld/stub_32c6.ld b/flasher_stub/ld/stub_32c6.ld index 994a010fb..91b8d3137 100644 --- a/flasher_stub/ld/stub_32c6.ld +++ b/flasher_stub/ld/stub_32c6.ld @@ -1,20 +1,3 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) PTE LTD - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin - * Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - MEMORY { iram : org = 0x40800000, len = 0x4000 dram : org = 0x40840000, len = 0x18000 diff --git a/flasher_stub/ld/stub_32c6_beta.ld b/flasher_stub/ld/stub_32c6_beta.ld index 89ab54df1..5acb1029b 100644 --- a/flasher_stub/ld/stub_32c6_beta.ld +++ b/flasher_stub/ld/stub_32c6_beta.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40380000, len = 0x4000 dram : org = 0x3FC84000, len = 0x18000 diff --git a/flasher_stub/ld/stub_32h2.ld b/flasher_stub/ld/stub_32h2.ld index 16559d807..c94f5939e 100644 --- a/flasher_stub/ld/stub_32h2.ld +++ b/flasher_stub/ld/stub_32h2.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40800000, len = 0x4000 dram : org = 0x40830000, len = 0x18000 diff --git a/flasher_stub/ld/stub_32h2_beta_1.ld b/flasher_stub/ld/stub_32h2_beta_1.ld index da6e273bf..62b16372c 100644 --- a/flasher_stub/ld/stub_32h2_beta_1.ld +++ b/flasher_stub/ld/stub_32h2_beta_1.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40380000, len = 0x4000 dram : org = 0x3FC84000, len = 0x18000 diff --git a/flasher_stub/ld/stub_32h2_beta_2.ld b/flasher_stub/ld/stub_32h2_beta_2.ld index 07876ae6e..903b497ee 100644 --- a/flasher_stub/ld/stub_32h2_beta_2.ld +++ b/flasher_stub/ld/stub_32h2_beta_2.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40380000, len = 0x4000 dram : org = 0x3FC84000, len = 0x18000 diff --git a/flasher_stub/ld/stub_32p4.ld b/flasher_stub/ld/stub_32p4.ld index 84052ee17..bf7e46a4e 100644 --- a/flasher_stub/ld/stub_32p4.ld +++ b/flasher_stub/ld/stub_32p4.ld @@ -1,20 +1,3 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) PTE LTD - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin - * Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - MEMORY { iram : org = 0x4FF10000, len = 0x4000 dram : org = 0x4FF50000, len = 0x18000 diff --git a/flasher_stub/ld/stub_32s2.ld b/flasher_stub/ld/stub_32s2.ld index 06a32ff37..ccec2b79c 100644 --- a/flasher_stub/ld/stub_32s2.ld +++ b/flasher_stub/ld/stub_32s2.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40028000, len = 0x18000 dram : org = 0x3FFD0000, len = 0x28000 diff --git a/flasher_stub/ld/stub_32s3.ld b/flasher_stub/ld/stub_32s3.ld index 08eaae1ec..98cce2284 100644 --- a/flasher_stub/ld/stub_32s3.ld +++ b/flasher_stub/ld/stub_32s3.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40378000, len = 0x18000 dram : org = 0x3FCA0000, len = 0x28000 diff --git a/flasher_stub/ld/stub_32s3_beta_2.ld b/flasher_stub/ld/stub_32s3_beta_2.ld index 86f5405fa..5105e30d9 100644 --- a/flasher_stub/ld/stub_32s3_beta_2.ld +++ b/flasher_stub/ld/stub_32s3_beta_2.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40378000, len = 0x18000 dram : org = 0x3FCA0000, len = 0x28000 diff --git a/flasher_stub/ld/stub_8266.ld b/flasher_stub/ld/stub_8266.ld index 9f837a456..a42b9b25e 100644 --- a/flasher_stub/ld/stub_8266.ld +++ b/flasher_stub/ld/stub_8266.ld @@ -1,20 +1,3 @@ -/* - * Copyright (c) 2016 Cesanta Software Limited - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin - * Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - /* Note: stub is deliberately loaded close to the very top of available RAM, to reduce change of colliding with anything else... */ diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c index b3e86d6b5..6b5885039 100644 --- a/flasher_stub/stub_flasher.c +++ b/flasher_stub/stub_flasher.c @@ -466,67 +466,72 @@ void stub_main() { const uint32_t greeting = 0x4941484f; /* OHAI */ - /* this points to stub_main now, clear for next boot */ + /* This points to stub_main now, clear for next boot. */ ets_set_user_start(0); + /* Increase CPU frequency and flashing speed if supported. */ #if USE_MAX_CPU_FREQ set_max_cpu_freq(); #endif // USE_MAX_CPU_FREQ + /* Disable all watchdogs to prevent the chip from resetting during longer operations. */ #if WITH_USB_JTAG_SERIAL disable_watchdogs(); #endif // WITH_USB_JTAG_SERIAL - /* zero bss */ + /* Zero the bss region. */ for(uint32_t *p = &_bss_start; p < &_bss_end; p++) { *p = 0; } + /* Send the OHAI greeting, stub will be reported as running. */ SLIP_send(&greeting, 4); + /* Configure the interrupts for receiving data from esptool on the host. */ ub.reading_buf = ub.buf_a; stub_io_init(&stub_handle_rx_byte); /* Configure default SPI flash functionality. Can be overriden later by esptool.py. */ -#ifdef ESP8266 - SelectSpiFunction(); - - spi_flash_attach(); -#else -#if !ESP32C2 && !ESP32C6 && !ESP32H2 && !ESP32P4 - uint32_t spiconfig = ets_efuse_get_spiconfig(); -#else - // ESP32C2/ESP32C6 doesn't support get spiconfig. - uint32_t spiconfig = 0; -#endif - uint32_t strapping = READ_REG(GPIO_STRAP_REG); - /* If GPIO1 (U0TXD) is pulled low and no other boot mode is - set in efuse, assume HSPI flash mode (same as normal boot) - */ - if (spiconfig == 0 && (strapping & 0x1c) == 0x08) { - spiconfig = 1; /* HSPI flash mode */ - } - spi_flash_attach(spiconfig, 0); -#endif -#if ESP32S3 && !ESP32S3BETA2 - large_flash_mode = ets_efuse_flash_octal_mode() || flash_larger_than_16mb(); - - // Initialize OPI flash driver only when flash is detected octal or quad larger than 16MB. - // Otherwise, we don't need to initialize such a driver - if (large_flash_mode) { - static const esp_rom_opiflash_def_t flash_driver = OPIFLASH_DRIVER(); - esp_rom_opiflash_legacy_driver_init(&flash_driver); - esp_rom_opiflash_wait_idle(); - } -#endif //ESP32S3 && !ESP32S3BETA2 - SPIParamCfg(0, FLASH_MAX_SIZE, FLASH_BLOCK_SIZE, FLASH_SECTOR_SIZE, - FLASH_PAGE_SIZE, FLASH_STATUS_MASK); + #ifdef ESP8266 + SelectSpiFunction(); + spi_flash_attach(); + #else + #if SUPPORT_CONFIG_SPI + uint32_t spiconfig = ets_efuse_get_spiconfig(); + #else + uint32_t spiconfig = 0; + #endif // SUPPORT_CONFIG_SPI + uint32_t strapping = READ_REG(GPIO_STRAP_REG); + /* If GPIO1 (U0TXD) is pulled low and no other boot mode is + set in efuse, assume HSPI flash mode (same as normal boot) + */ + if (spiconfig == 0 && (strapping & 0x1c) == 0x08) { + spiconfig = 1; /* HSPI flash mode */ + } + spi_flash_attach(spiconfig, 0); + #endif // ESP8266 + + /* Initialize the OPI flash driver if supported. */ + #if ESP32S3 && !ESP32S3BETA2 + large_flash_mode = ets_efuse_flash_octal_mode() || flash_larger_than_16mb(); + + // Initialize OPI flash driver only when flash is detected octal or quad larger than 16MB. + // Otherwise, we don't need to initialize such a driver + if (large_flash_mode) { + static const esp_rom_opiflash_def_t flash_driver = OPIFLASH_DRIVER(); + esp_rom_opiflash_legacy_driver_init(&flash_driver); + esp_rom_opiflash_wait_idle(); + } + #endif //ESP32S3 && !ESP32S3BETA2 + SPIParamCfg(0, FLASH_MAX_SIZE, FLASH_BLOCK_SIZE, FLASH_SECTOR_SIZE, + FLASH_PAGE_SIZE, FLASH_STATUS_MASK); + /* Configurations are done, now run the loop to receive and handle commands. */ cmd_loop(); - /* if cmd_loop returns, it's due to ESP_RUN_USER_CODE command. */ - + /* If cmd_loop returns, it's due to ESP_RUN_USER_CODE command. */ + /* Decrease CPU frequency back to the saved value before the stub flasher returns. */ #if USE_MAX_CPU_FREQ reset_cpu_freq(); #endif // USE_MAX_CPU_FREQ diff --git a/flasher_stub/stub_write_flash.c b/flasher_stub/stub_write_flash.c index 026f14e8f..e925d9f74 100644 --- a/flasher_stub/stub_write_flash.c +++ b/flasher_stub/stub_write_flash.c @@ -96,17 +96,7 @@ static void spi_write_enable(void) } #if ESP32_OR_LATER -#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 -static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x3fcdfff4; -#elif ESP32H2BETA1 || ESP32H2BETA2 -static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x3fcdfff0; -#elif ESP32H2 -static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x4084fff0; -#elif ESP32P4 -static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x4ff3ffec; -#else -static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)0x3ffae270; -#endif +static esp_rom_spiflash_chip_t *flashchip = (esp_rom_spiflash_chip_t *)ROM_SPIFLASH_LEGACY; /* Stub version of SPIUnlock() that replaces version in ROM. @@ -128,7 +118,7 @@ SpiFlashOpResult SPIUnlock(void) if (SPI_read_status_high(&status) != SPI_FLASH_RESULT_OK) { return SPI_FLASH_RESULT_ERR; } -#endif +#endif // ESP32S2_OR_LATER /* Clear all bits except QIE, if it is set. (This is different from ROM SPIUnlock, which keeps all bits as-is.) @@ -144,7 +134,7 @@ SpiFlashOpResult SPIUnlock(void) return SPI_FLASH_RESULT_OK; } -#endif +#endif // ESP32_OR_LATER #if defined(ESP32S3) && !defined(ESP32S3BETA2) static esp_rom_spiflash_result_t page_program_internal(int spi_num, uint32_t spi_addr, uint8_t* addr_source, uint32_t byte_length) @@ -205,7 +195,7 @@ static esp_rom_spiflash_result_t SPIWrite4B(int spi_num, uint32_t target, uint8_ esp_rom_opiflash_wait_idle(); return ESP_ROM_SPIFLASH_RESULT_OK; } -#endif // ESP32S3 +#endif // defined(ESP32S3) && !defined(ESP32S3BETA2) esp_command_error handle_flash_begin(uint32_t total_size, uint32_t offset) { fs.in_flash_mode = true; @@ -363,7 +353,7 @@ void handle_flash_data(void *data_buf, uint32_t length) { } #else res = SPIWrite(fs.next_write, data_buf, length); - #endif // ESP32S3 + #endif // defined(ESP32S3) && !defined(ESP32S3BETA2) if (res != 0) fs.last_error = ESP_FAILED_SPI_OP; fs.next_write += length; diff --git a/test/images/ram_helloworld/source/ld/app_32.ld b/test/images/ram_helloworld/source/ld/app_32.ld index ab5e15f7d..2301e0bea 100644 --- a/test/images/ram_helloworld/source/ld/app_32.ld +++ b/test/images/ram_helloworld/source/ld/app_32.ld @@ -1,20 +1,3 @@ -/* - * Copyright (c) 2016 Cesanta Software Limited - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin - * Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - MEMORY { iram : org = 0x4008c000, len = 0x1000 dram : org = 0x3ffc0000, len = 0xc000 diff --git a/test/images/ram_helloworld/source/ld/app_32c2.ld b/test/images/ram_helloworld/source/ld/app_32c2.ld index f9bb37b4e..cb792b06c 100644 --- a/test/images/ram_helloworld/source/ld/app_32c2.ld +++ b/test/images/ram_helloworld/source/ld/app_32c2.ld @@ -1,10 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - - MEMORY { iram : org = 0x40390000, len = 0x100 dram : org = 0x3FCD0000, len = 0x100 diff --git a/test/images/ram_helloworld/source/ld/app_32c3.ld b/test/images/ram_helloworld/source/ld/app_32c3.ld index a28a8a3aa..b9e1fe9db 100644 --- a/test/images/ram_helloworld/source/ld/app_32c3.ld +++ b/test/images/ram_helloworld/source/ld/app_32c3.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x403DFD00, len = 0x100 dram : org = 0x3FCDFD00, len = 0x100 diff --git a/test/images/ram_helloworld/source/ld/app_32c6.ld b/test/images/ram_helloworld/source/ld/app_32c6.ld index 91055f1ab..a046073a6 100644 --- a/test/images/ram_helloworld/source/ld/app_32c6.ld +++ b/test/images/ram_helloworld/source/ld/app_32c6.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40860000, len = 0x100 dram : org = 0x40870000, len = 0x100 diff --git a/test/images/ram_helloworld/source/ld/app_32h2.ld b/test/images/ram_helloworld/source/ld/app_32h2.ld index 766286255..1409330d1 100644 --- a/test/images/ram_helloworld/source/ld/app_32h2.ld +++ b/test/images/ram_helloworld/source/ld/app_32h2.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40804000, len = 0x100 dram : org = 0x40848000, len = 0x100 diff --git a/test/images/ram_helloworld/source/ld/app_32p4.ld b/test/images/ram_helloworld/source/ld/app_32p4.ld index c758db9cd..1a4589dd7 100644 --- a/test/images/ram_helloworld/source/ld/app_32p4.ld +++ b/test/images/ram_helloworld/source/ld/app_32p4.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x4FF60000, len = 0x100 dram : org = 0x4FF70000, len = 0x100 diff --git a/test/images/ram_helloworld/source/ld/app_32s2.ld b/test/images/ram_helloworld/source/ld/app_32s2.ld index 76811c12a..7caf884cd 100644 --- a/test/images/ram_helloworld/source/ld/app_32s2.ld +++ b/test/images/ram_helloworld/source/ld/app_32s2.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40020000, len = 0x8000 dram : org = 0x3FFC8000, len = 0x8000 diff --git a/test/images/ram_helloworld/source/ld/app_32s3.ld b/test/images/ram_helloworld/source/ld/app_32s3.ld index 4d3d5da4d..ca263a1ef 100644 --- a/test/images/ram_helloworld/source/ld/app_32s3.ld +++ b/test/images/ram_helloworld/source/ld/app_32s3.ld @@ -1,9 +1,3 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - MEMORY { iram : org = 0x40380000, len = 0x100 dram : org = 0x3FCA0000, len = 0x100 diff --git a/test/images/ram_helloworld/source/ld/app_8266.ld b/test/images/ram_helloworld/source/ld/app_8266.ld index 218b9e191..3b7a1e04d 100644 --- a/test/images/ram_helloworld/source/ld/app_8266.ld +++ b/test/images/ram_helloworld/source/ld/app_8266.ld @@ -1,20 +1,3 @@ -/* - * Copyright (c) 2016 Cesanta Software Limited - * All rights reserved - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin - * Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - MEMORY { iram : org = 0x40108000, len = 0x2000 dram : org = 0x3FFE8000, len = 0x100 From d7580de28a0072667af3d6ec4b9065e46c64fb56 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 1 Nov 2023 17:55:29 +0100 Subject: [PATCH 086/209] feat: add support for intel hex format --- docs/en/esptool/advanced-commands.rst | 2 +- docs/en/esptool/basic-commands.rst | 25 +++++++-- esptool/__init__.py | 27 ++++++++-- esptool/bin_image.py | 21 ++++++++ esptool/cmds.py | 15 ++++++ setup.py | 1 + test/test_esptool.py | 73 ++++++++++++++++++++++++--- test/test_image_info.py | 45 ++++++++++++++++- test/test_merge_bin.py | 66 ++++++++++++++++++++++++ 9 files changed, 258 insertions(+), 17 deletions(-) diff --git a/docs/en/esptool/advanced-commands.rst b/docs/en/esptool/advanced-commands.rst index 5143963a5..bfc9d2c0c 100644 --- a/docs/en/esptool/advanced-commands.rst +++ b/docs/en/esptool/advanced-commands.rst @@ -48,7 +48,7 @@ The ``dump_mem`` command will dump a region from the chip's memory space to a fi Load a Binary to RAM: load_ram ------------------------------ -The ``load_ram`` command allows the loading of an executable binary image (created with the ``elf2image`` or ``make_image`` commands) directly into RAM, and then immediately executes the program contained within it. +The ``load_ram`` command allows the loading of an executable binary image (created with the ``elf2image`` or ``make_image`` commands) directly into RAM, and then immediately executes the program contained within it. Command also supports ``.hex`` file created by ``merge_bin`` command from supported ``.bin`` files. :: diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index 880cb5fe3..ead5ac208 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -220,7 +220,7 @@ By default, ``elf2image`` uses the sections in the ELF file to generate each seg Output .bin Image Details: image_info ------------------------------------- -The ``image_info`` command outputs some information (load addresses, sizes, etc) about a ``.bin`` file created by ``elf2image``. +The ``image_info`` command outputs some information (load addresses, sizes, etc) about a ``.bin`` file created by ``elf2image``. Command also supports ``.hex`` file created by ``merge_bin`` command from supported ``.bin`` files. To view more information about the image, such as set flash size, frequency and mode, or extended header information, use the ``--version 2`` option. This extended output will become the default in a future major release. @@ -240,7 +240,7 @@ This information corresponds to the headers described in :ref:`image-format`. Merge Binaries for Flashing: merge_bin -------------------------------------- -The ``merge_bin`` command will merge multiple binary files (of any kind) into a single file that can be flashed to a device later. Any gaps between the input files are padded based on selected output format. +The ``merge_bin`` command will merge multiple binary files (of any kind) into a single file that can be flashed to a device later. Any gaps between the input files are padded based on the selected output format. For example: @@ -248,7 +248,7 @@ For example: esptool.py --chip {IDF_TARGET_NAME} merge_bin -o merged-flash.bin --flash_mode dio --flash_size 4MB 0x1000 bootloader.bin 0x8000 partition-table.bin 0x10000 app.bin -Will create a file ``merged-flash.bin`` with the contents of the other 3 files. This file can be later be written to flash with ``esptool.py write_flash 0x0 merged-flash.bin``. +Will create a file ``merged-flash.bin`` with the contents of the other 3 files. This file can be later written to flash with ``esptool.py write_flash 0x0 merged-flash.bin``. **Common options:** @@ -256,6 +256,7 @@ Will create a file ``merged-flash.bin`` with the contents of the other 3 files. * The ``merge_bin`` command supports the same ``--flash_mode``, ``--flash_size`` and ``--flash_freq`` options as the ``write_flash`` command to override the bootloader flash header (see above for details). These options are applied to the output file contents in the same way as when writing to flash. Make sure to pass the ``--chip`` parameter if using these options, as the supported values and the bootloader offset both depend on the chip. * The ``--format`` option will change the format of the output file. For more information about formats see formats description below. +* The input files can be in either ``bin`` or ``hex`` format and they will be automatically converted to type selected by ``--format`` argument. * It is possible to append options from a text file with ``@filename`` (see the advanced options page :ref:`Specifying Arguments via File ` section for details). As an example, this can be conveniently used with the ESP-IDF build system, which produces a ``flash_args`` file in the build directory of a project: .. code:: sh @@ -264,6 +265,22 @@ Will create a file ``merged-flash.bin`` with the contents of the other 3 files. esptool.py --chip {IDF_TARGET_NAME} merge_bin -o merged-flash.bin @flash_args +HEX Output Format +^^^^^^^^^^^^^^^^^ + +The output of the command will be in `Intel Hex format `__. The gaps between the files won't be padded. + +Intel Hex format offers distinct advantages when compared to the binary format, primarily in the following areas: + +* **Transport**: Intel Hex files are represented in ASCII text format, significantly increasing the likelihood of flawless transfers across various mediums. +* **Size**: Data is carefully allocated to specific memory addresses eliminating the need for unnecessary padding. Binary images often lack detailed addressing information, leading to the inclusion of data for all memory locations from the file's initial address to its end. +* **Validity Checks**: Each line in an Intel Hex file has a checksum to help find errors and make sure data stays unchanged. + +.. code:: sh + + esptool.py --chip {IDF_TARGET_NAME} merge_bin --format hex -o merged-flash.hex --flash_mode dio --flash_size 4MB 0x1000 bootloader.bin 0x8000 partition-table.bin 0x10000 app.bin + + RAW Output Format ^^^^^^^^^^^^^^^^^ @@ -290,7 +307,7 @@ Gaps between the files will be filled with `0x00` bytes. **UF2 options:** -* The ``--chunk-size`` option will set what portion of 512 byte block will be used for data. Common value is 256 bytes. By default the largest possible value will be used. +* The ``--chunk-size`` option will set what portion of 512 byte block will be used for data. A common value is 256 bytes. By default, the largest possible value will be used. * The ``--md5-disable`` option will disable MD5 checksums at the end of each block. This can be useful for integration with e.g. `tinyuf2 `__. .. code:: sh diff --git a/esptool/__init__.py b/esptool/__init__.py index 973d1fd5b..206b6fadd 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -38,6 +38,7 @@ import time import traceback +from esptool.bin_image import intel_hex_to_bin from esptool.cmds import ( DETECTED_FLASH_SIZES, chip_id, @@ -185,7 +186,9 @@ def add_spi_connection_arg(parent): parser_load_ram = subparsers.add_parser( "load_ram", help="Download an image to RAM and execute" ) - parser_load_ram.add_argument("filename", help="Firmware image") + parser_load_ram.add_argument( + "filename", help="Firmware image", action=AutoHex2BinAction + ) parser_dump_mem = subparsers.add_parser( "dump_mem", help="Dump arbitrary memory to disk" @@ -357,7 +360,9 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): parser_image_info = subparsers.add_parser( "image_info", help="Dump headers from a binary file (bootloader or application)" ) - parser_image_info.add_argument("filename", help="Image file to parse") + parser_image_info.add_argument( + "filename", help="Image file to parse", action=AutoHex2BinAction + ) parser_image_info.add_argument( "--version", "-v", @@ -601,7 +606,7 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): "--format", "-f", help="Format of the output file", - choices=["raw", "uf2"], + choices=["raw", "uf2", "hex"], default="raw", ) uf2_group = parser_merge_bin.add_argument_group("UF2 format") @@ -1057,6 +1062,20 @@ def __call__(self, parser, namespace, value, option_string=None): setattr(namespace, self.dest, value) +class AutoHex2BinAction(argparse.Action): + """Custom parser class for auto conversion of input files from hex to bin""" + + def __call__(self, parser, namespace, value, option_string=None): + try: + with open(value, "rb") as f: + # if hex file was detected replace hex file with converted temp bin + # otherwise keep the original file + value = intel_hex_to_bin(f).name + except IOError as e: + raise argparse.ArgumentError(self, e) + setattr(namespace, self.dest, value) + + class AddrFilenamePairAction(argparse.Action): """Custom parser class for the address/filename pairs passed as arguments""" @@ -1085,6 +1104,8 @@ def __call__(self, parser, namespace, values, option_string=None): "Must be pairs of an address " "and the binary filename to write there", ) + # check for intel hex files and convert them to bin + argfile = intel_hex_to_bin(argfile, address) pairs.append((address, argfile)) # Sort the addresses and check for overlapping diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 0f3ef2f64..b011b55b5 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -10,6 +10,10 @@ import os import re import struct +import tempfile +from typing import BinaryIO, Optional + +from intelhex import IntelHex from .loader import ESPLoader from .targets import ( @@ -36,6 +40,23 @@ def align_file_position(f, size): f.seek(align, 1) +def intel_hex_to_bin(file: BinaryIO, start_addr: Optional[int] = None) -> BinaryIO: + """Convert IntelHex file to temp binary file with padding from start_addr + If hex file was detected return temp bin file object; input file otherwise""" + INTEL_HEX_MAGIC = b":" + magic = file.read(1) + file.seek(0) + if magic == INTEL_HEX_MAGIC: + ih = IntelHex() + ih.loadhex(file.name) + file.close() + bin = tempfile.NamedTemporaryFile(suffix=".bin", delete=False) + ih.tobinfile(bin, start=start_addr) + return bin + else: + return file + + def LoadFirmwareImage(chip, image_file): """ Load a firmware image. Can be for any supported SoC. diff --git a/esptool/cmds.py b/esptool/cmds.py index 408c17f67..3a6f914e0 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -11,6 +11,8 @@ import time import zlib +from intelhex import IntelHex + from .bin_image import ELFFile, ImageSegment, LoadFirmwareImage from .bin_image import ( ESP8266ROMFirmwareImage, @@ -1337,6 +1339,19 @@ def pad_to(flash_offs): f"Wrote {of.tell():#x} bytes to file {args.output}, " f"ready to flash to offset {args.target_offset:#x}" ) + elif args.format == "hex": + out = IntelHex() + for addr, argfile in input_files: + ihex = IntelHex() + image = argfile.read() + image = _update_image_flash_params(chip_class, addr, args, image) + ihex.frombytes(image, addr) + out.merge(ihex) + out.write_hex_file(args.output) + print( + f"Wrote {os.path.getsize(args.output):#x} bytes to file {args.output}, " + f"ready to flash to offset {args.target_offset:#x}" + ) def version(args): diff --git a/setup.py b/setup.py index f6e084e7e..0f1b2826b 100644 --- a/setup.py +++ b/setup.py @@ -130,6 +130,7 @@ def find_version(*file_paths): "pyserial>=3.0", "reedsolo>=1.5.3,<1.8", "PyYAML>=5.1", + "intelhex", ], packages=find_packages(), include_package_data=True, diff --git a/test/test_esptool.py b/test/test_esptool.py index c399f9c06..c625ea983 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -24,6 +24,7 @@ import time from socket import AF_INET, SOCK_STREAM, socket from time import sleep +from typing import List from unittest.mock import MagicMock # Link command line options --port, --chip, --baud, --with-trace, and --preload-port @@ -389,6 +390,42 @@ def test_adjacent_flash(self): self.verify_readback(0, 4096, "images/sector.bin") self.verify_readback(4096, 50 * 1024, "images/fifty_kb.bin") + def test_short_flash_hex(self): + _, f = tempfile.mkstemp(suffix=".hex") + try: + self.run_esptool(f"merge_bin --format hex 0x0 images/one_kb.bin -o {f}") + self.run_esptool(f"write_flash 0x0 {f}") + self.verify_readback(0, 1024, "images/one_kb.bin") + finally: + os.unlink(f) + + def test_adjacent_flash_hex(self): + _, f1 = tempfile.mkstemp(suffix=".hex") + _, f2 = tempfile.mkstemp(suffix=".hex") + try: + self.run_esptool(f"merge_bin --format hex 0x0 images/sector.bin -o {f1}") + self.run_esptool( + f"merge_bin --format hex 0x1000 images/fifty_kb.bin -o {f2}" + ) + self.run_esptool(f"write_flash 0x0 {f1} 0x1000 {f2}") + self.verify_readback(0, 4096, "images/sector.bin") + self.verify_readback(4096, 50 * 1024, "images/fifty_kb.bin") + finally: + os.unlink(f1) + os.unlink(f2) + + def test_adjacent_flash_mixed(self): + _, f = tempfile.mkstemp(suffix=".hex") + try: + self.run_esptool( + f"merge_bin --format hex 0x1000 images/fifty_kb.bin -o {f}" + ) + self.run_esptool(f"write_flash 0x0 images/sector.bin 0x1000 {f}") + self.verify_readback(0, 4096, "images/sector.bin") + self.verify_readback(4096, 50 * 1024, "images/fifty_kb.bin") + finally: + os.unlink(f) + def test_adjacent_independent_flash(self): self.run_esptool("write_flash 0x0 images/sector.bin") self.verify_readback(0, 4096, "images/sector.bin") @@ -949,6 +986,15 @@ def test_explicit_set_size_freq_mode(self): class TestLoadRAM(EsptoolTestCase): # flashing an application not supporting USB-CDC will make # /dev/ttyACM0 disappear and USB-CDC tests will not work anymore + + def verify_output(self, expected_out: List[bytes]): + """Verify that at least one element of expected_out is in serial output""" + with serial.serial_for_url(arg_port, arg_baud) as p: + p.timeout = 5 + output = p.read(100) + print(f"Output: {output}") + assert any(item in output for item in expected_out) + @pytest.mark.quick_test def test_load_ram(self): """Verify load_ram command @@ -957,17 +1003,28 @@ def test_load_ram(self): "Hello world!\n" to the serial port. """ self.run_esptool(f"load_ram images/ram_helloworld/helloworld-{arg_chip}.bin") + self.verify_output( + [b"Hello world!", b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04'] + ) + + def test_load_ram_hex(self): + """Verify load_ram command with hex file as input + + The "hello world" binary programs for each chip print + "Hello world!\n" to the serial port. + """ + _, f = tempfile.mkstemp(suffix=".hex") try: - p = serial.serial_for_url(arg_port, arg_baud) - p.timeout = 5 - output = p.read(100) - print(f"Output: {output}") - assert ( - b"Hello world!" in output # xtensa - or b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04' in output # C3 + self.run_esptool( + f"merge_bin --format hex -o {f} 0x0 " + f"images/ram_helloworld/helloworld-{arg_chip}.bin" + ) + self.run_esptool(f"load_ram {f}") + self.verify_output( + [b"Hello world!", b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04'] ) finally: - p.close() + os.unlink(f) class TestDeepSleepFlash(EsptoolTestCase): diff --git a/test/test_image_info.py b/test/test_image_info.py index d9edef602..3dac7310a 100755 --- a/test/test_image_info.py +++ b/test/test_image_info.py @@ -2,6 +2,7 @@ import os.path import subprocess import sys +import tempfile from conftest import need_to_install_package_err @@ -40,7 +41,9 @@ def run_image_info(self, chip, file, version=None): ] if version is not None: cmd += ["--version", str(version)] - cmd += ["".join([IMAGES_DIR, os.sep, file])] + # if path was passed use the whole path + # if file does not exists try to use file from IMAGES_DIR directory + cmd += [file] if os.path.isfile(file) else ["".join([IMAGES_DIR, os.sep, file])] print("\nExecuting {}".format(" ".join(cmd))) try: @@ -189,3 +192,43 @@ def test_bootloader_info(self): assert "Bootloader version: 1" in out assert "ESP-IDF: v5.2-dev-254-g1950b15" in out assert "Compile time: Apr 25 2023 00:13:32" in out + + def test_intel_hex(self): + # This bootloader binary is built from "hello_world" project + # with default settings, IDF version is v5.2. + # File is converted to Intel Hex using merge_bin + + def convert_bin2hex(file): + subprocess.check_output( + [ + sys.executable, + "-m", + "esptool", + "--chip", + "esp32", + "merge_bin", + "--format", + "hex", + "0x0", + "".join([IMAGES_DIR, os.sep, "bootloader_esp32_v5_2.bin"]), + "-o", + file, + ] + ) + + fd, file = tempfile.mkstemp(suffix=".hex") + try: + convert_bin2hex(file) + out = self.run_image_info("esp32", file, "2") + assert "File size: 26768 (bytes)" in out + assert "Bootloader information" in out + assert "Bootloader version: 1" in out + assert "ESP-IDF: v5.2-dev-254-g1950b15" in out + assert "Compile time: Apr 25 2023 00:13:32" in out + finally: + try: + # make sure that file was closed before removing it + os.close(fd) + except OSError: + pass + os.unlink(file) diff --git a/test/test_merge_bin.py b/test/test_merge_bin.py index 5ca7e0890..83abbff92 100755 --- a/test/test_merge_bin.py +++ b/test/test_merge_bin.py @@ -197,6 +197,72 @@ def test_fill_flash_size_w_target_offset(self): assert helloworld == merged[0xF000 : 0xF000 + len(helloworld)] self.assertAllFF(merged[0xF000 + len(helloworld) :]) + def test_merge_mixed(self): + # convert bootloader to hex + hex = self.run_merge_bin( + "esp32", + [(0x1000, "bootloader_esp32.bin")], + options=["--format", "hex"], + ) + # create a temp file with hex content + with tempfile.NamedTemporaryFile(suffix=".hex", delete=False) as f: + f.write(hex) + # merge hex file with bin file + # output to bin file should be the same as in merge bin + bin + try: + merged = self.run_merge_bin( + "esp32", + [(0x1000, f.name), (0x10000, "ram_helloworld/helloworld-esp32.bin")], + ["--target-offset", "0x1000", "--fill-flash-size", "2MB"], + ) + finally: + os.unlink(f.name) + # full length is without target-offset arg + assert len(merged) == 0x200000 - 0x1000 + + bootloader = read_image("bootloader_esp32.bin") + helloworld = read_image("ram_helloworld/helloworld-esp32.bin") + assert bootloader == merged[: len(bootloader)] + assert helloworld == merged[0xF000 : 0xF000 + len(helloworld)] + self.assertAllFF(merged[0xF000 + len(helloworld) :]) + + def test_merge_bin2hex(self): + merged = self.run_merge_bin( + "esp32", + [ + (0x1000, "bootloader_esp32.bin"), + ], + options=["--format", "hex"], + ) + lines = merged.splitlines() + # hex format - :0300300002337A1E + # :03 0030 00 02337A 1E + # ^data_cnt/2 ^addr ^type ^data ^checksum + + # check for starting address - 0x1000 passed from arg + assert lines[0][3:7] == b"1000" + # pick a random line for testing the format + line = lines[random.randrange(0, len(lines))] + assert line[0] == ord(":") + data_len = int(b"0x" + line[1:3], 16) + # : + len + addr + type + data + checksum + assert len(line) == 1 + 2 + 4 + 2 + data_len * 2 + 2 + # last line is allways :00000001FF + assert lines[-1] == b":00000001FF" + # convert back and verify the result against the source bin file + with tempfile.NamedTemporaryFile(suffix=".hex", delete=False) as hex: + hex.write(merged) + merged_bin = self.run_merge_bin( + "esp32", + [(0x1000, hex.name)], + options=["--format", "raw"], + ) + source = read_image("bootloader_esp32.bin") + # verify that padding was done correctly + assert b"\xFF" * 0x1000 == merged_bin[:0x1000] + # verify the file itself + assert source == merged_bin[0x1000:] + class UF2Block(object): def __init__(self, bs): From 0536a6bec22be8e319e83bd8cb670d7b023dcd42 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 6 Nov 2023 12:20:54 +0800 Subject: [PATCH 087/209] feat(xip_psram): support xip psram feature on esp32p4 Expanded IROM / DROM range to include psram space as well --- esptool/targets/esp32p4.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 23ff407c1..0791ab65a 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -15,9 +15,9 @@ class ESP32P4ROM(ESP32ROM): IMAGE_CHIP_ID = 18 IROM_MAP_START = 0x40000000 - IROM_MAP_END = 0x44000000 + IROM_MAP_END = 0x4C000000 DROM_MAP_START = 0x40000000 - DROM_MAP_END = 0x44000000 + DROM_MAP_END = 0x4C000000 BOOTLOADER_FLASH_OFFSET = 0x2000 # First 2 sectors are reserved for FE purposes @@ -71,12 +71,12 @@ class ESP32P4ROM(ESP32ROM): MEMORY_MAP = [ [0x00000000, 0x00010000, "PADDING"], - [0x40000000, 0x44000000, "DROM"], + [0x40000000, 0x4C000000, "DROM"], [0x4FF00000, 0x4FFA0000, "DRAM"], [0x4FF00000, 0x4FFA0000, "BYTE_ACCESSIBLE"], [0x4FC00000, 0x4FC20000, "DROM_MASK"], [0x4FC00000, 0x4FC20000, "IROM_MASK"], - [0x40000000, 0x44000000, "IROM"], + [0x40000000, 0x4C000000, "IROM"], [0x4FF00000, 0x4FFA0000, "IRAM"], [0x50108000, 0x50110000, "RTC_IRAM"], [0x50108000, 0x50110000, "RTC_DRAM"], From 005c3e3c47fdb12176a411783c21189335509a36 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Tue, 7 Nov 2023 16:44:28 +0800 Subject: [PATCH 088/209] fix(espefuse): Fix ECDSA_FORCE_USE_HARDWARE_K for ECDSA key (esp32h2) --- espefuse/efuse/esp32h2/operations.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/espefuse/efuse/esp32h2/operations.py b/espefuse/efuse/esp32h2/operations.py index d9445d152..6debd0911 100644 --- a/espefuse/efuse/esp32h2/operations.py +++ b/espefuse/efuse/esp32h2/operations.py @@ -323,6 +323,15 @@ def burn_key(esp, efuses, args, digest=None): if efuses[block.key_purpose_name].is_writeable(): disable_wr_protect_key_purpose = True + if keypurpose == "ECDSA_KEY": + if efuses["ECDSA_FORCE_USE_HARDWARE_K"].get() == 0: + # For ECDSA key purpose block permanently enable + # the hardware TRNG supplied k mode (most secure mode) + print("\tECDSA_FORCE_USE_HARDWARE_K: 0 -> 1") + efuses["ECDSA_FORCE_USE_HARDWARE_K"].save(1) + else: + print("\tECDSA_FORCE_USE_HARDWARE_K is already '1'") + if disable_wr_protect_key_purpose: print("\tDisabling write to '%s'." % block.key_purpose_name) efuses[block.key_purpose_name].disable_write() From fcf2277a0bb300593542f231851b07d9b8df1c9f Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Tue, 7 Nov 2023 16:04:35 +0800 Subject: [PATCH 089/209] feat(espefuse): Support XTS_AES_256_KEY key_purpose for ESP32P4 --- espefuse/efuse/esp32p4/fields.py | 1 + espefuse/efuse/esp32p4/operations.py | 67 ++++++++++++++++++++++++++++ test/test_espefuse.py | 12 ++--- 3 files changed, 74 insertions(+), 6 deletions(-) diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py index b79816208..4b912ec5c 100644 --- a/espefuse/efuse/esp32p4/fields.py +++ b/espefuse/efuse/esp32p4/fields.py @@ -387,6 +387,7 @@ class EfuseKeyPurposeField(EfuseField): ("SECURE_BOOT_DIGEST1", 10, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST1 (Secure Boot key digest) ("SECURE_BOOT_DIGEST2", 11, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST2 (Secure Boot key digest) ("KM_INIT_KEY", 12, None, None, "need_rd_protect"), # init key that is used for the generation of AES/ECDSA key + ("XTS_AES_256_KEY", -1, "VIRTUAL", None, "no_need_rd_protect"), # Virtual purpose splits to XTS_AES_256_KEY_1 and XTS_AES_256_KEY_2 ] # fmt: on KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] diff --git a/espefuse/efuse/esp32p4/operations.py b/espefuse/efuse/esp32p4/operations.py index 093a04802..b24a73512 100644 --- a/espefuse/efuse/esp32p4/operations.py +++ b/espefuse/efuse/esp32p4/operations.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import argparse +import io import os # noqa: F401. It is used in IDF scripts import traceback @@ -191,6 +192,67 @@ def adc_info(esp, efuses, args): print("not supported yet") +def key_block_is_unused(block, key_purpose_block): + if not block.is_readable() or not block.is_writeable(): + return False + + if key_purpose_block.get() != "USER" or not key_purpose_block.is_writeable(): + return False + + if not block.get_bitstring().all(False): + return False + + return True + + +def get_next_key_block(efuses, current_key_block, block_name_list): + key_blocks = [b for b in efuses.blocks if b.key_purpose_name] + start = key_blocks.index(current_key_block) + + # Sort key blocks so that we pick the next free block (and loop around if necessary) + key_blocks = key_blocks[start:] + key_blocks[0:start] + + # Exclude any other blocks that will be be burned + key_blocks = [b for b in key_blocks if b.name not in block_name_list] + + for block in key_blocks: + key_purpose_block = efuses[block.key_purpose_name] + if key_block_is_unused(block, key_purpose_block): + return block + + return None + + +def split_512_bit_key(efuses, block_name_list, datafile_list, keypurpose_list): + i = keypurpose_list.index("XTS_AES_256_KEY") + block_name = block_name_list[i] + + block_num = efuses.get_index_block_by_name(block_name) + block = efuses.blocks[block_num] + + data = datafile_list[i].read() + if len(data) != 64: + raise esptool.FatalError( + "Incorrect key file size %d, XTS_AES_256_KEY should be 64 bytes" % len(data) + ) + + key_block_2 = get_next_key_block(efuses, block, block_name_list) + if not key_block_2: + raise esptool.FatalError("XTS_AES_256_KEY requires two free keyblocks") + + keypurpose_list.append("XTS_AES_256_KEY_1") + datafile_list.append(io.BytesIO(data[:32])) + block_name_list.append(block_name) + + keypurpose_list.append("XTS_AES_256_KEY_2") + datafile_list.append(io.BytesIO(data[32:])) + block_name_list.append(key_block_2.name) + + keypurpose_list.pop(i) + datafile_list.pop(i) + block_name_list.pop(i) + + def burn_key(esp, efuses, args, digest=None): if digest is None: datafile_list = args.keyfile[ @@ -206,6 +268,11 @@ def burn_key(esp, efuses, args, digest=None): 0 : len([name for name in args.keypurpose if name is not None]) : ] + if "XTS_AES_256_KEY" in keypurpose_list: + # XTS_AES_256_KEY is not an actual HW key purpose, needs to be split into + # XTS_AES_256_KEY_1 and XTS_AES_256_KEY_2 + split_512_bit_key(efuses, block_name_list, datafile_list, keypurpose_list) + util.check_duplicate_name_in_list(block_name_list) if len(block_name_list) != len(datafile_list) or len(block_name_list) != len( keypurpose_list diff --git a/test/test_espefuse.py b/test/test_espefuse.py index cb8ada0d0..c38f96b98 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -962,8 +962,8 @@ def test_burn_key_with_34_coding_scheme(self): self.check_data_block_in_log(output, f"{IMAGES_DIR}/192bit_2") @pytest.mark.skipif( - arg_chip not in ["esp32s2", "esp32s3"], - reason="512 bit keys are only supported on ESP32-S2 and S3", + arg_chip not in ["esp32s2", "esp32s3", "esp32p4"], + reason="512 bit keys are only supported on ESP32-S2, S3, and P4", ) def test_burn_key_512bit(self): self.espefuse_py( @@ -980,8 +980,8 @@ def test_burn_key_512bit(self): ) @pytest.mark.skipif( - arg_chip not in ["esp32s2", "esp32s3"], - reason="512 bit keys are only supported on ESP32-S2 and S3", + arg_chip not in ["esp32s2", "esp32s3", "esp32p4"], + reason="512 bit keys are only supported on ESP32-S2, S3, and P4", ) def test_burn_key_512bit_non_consecutive_blocks(self): # Burn efuses seperately to test different kinds @@ -1023,8 +1023,8 @@ def test_burn_key_512bit_non_consecutive_blocks(self): ) in output @pytest.mark.skipif( - arg_chip not in ["esp32s2", "esp32s3"], - reason="512 bit keys are only supported on ESP32-S2 and S3", + arg_chip not in ["esp32s2", "esp32s3", "esp32p4"], + reason="512 bit keys are only supported on ESP32-S2, S3, and P4", ) def test_burn_key_512bit_non_consecutive_blocks_loop_around(self): self.espefuse_py( From e2a24cad1175379dfc4af751fe0d6433f4f84e56 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 9 Nov 2023 16:04:38 +0100 Subject: [PATCH 090/209] feat(spi_connection): Support --spi-connection on all chips Closes https://github.com/espressif/esptool/issues/916 --- .gitlab-ci.yml | 4 ++ docs/en/advanced-topics/serial-protocol.rst | 10 ++-- docs/en/esptool/advanced-options.rst | 52 ++++++++++------- esptool/__init__.py | 65 +++++++++++---------- esptool/targets/esp32.py | 7 ++- esptool/targets/esp32c2.py | 5 ++ esptool/targets/esp32c3.py | 9 +++ esptool/targets/esp32c6.py | 9 +++ esptool/targets/esp32h2.py | 10 ++++ esptool/targets/esp32p4.py | 3 + esptool/targets/esp32s2.py | 9 +++ esptool/targets/esp32s3.py | 11 ++++ esptool/targets/esp8266.py | 9 +-- esptool/util.py | 2 +- test/test_esptool.py | 58 ++++++++++++++++-- 15 files changed, 197 insertions(+), 66 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 22f1339be..52f347cbb 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -282,6 +282,8 @@ target_esp32c3: extends: .target_esptool_test tags: - esptool_esp32c3_target + variables: + ESPTOOL_TEST_SPI_CONN: "6,2,7,4,10" script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32C3 --chip esp32c3 --baud 115200 @@ -329,6 +331,8 @@ target_esp32s3_jtag_serial: extends: .target_esptool_test tags: - esptool_esp32s3_jtag_serial_target + variables: + ESPTOOL_TEST_SPI_CONN: "12,13,11,9,10" script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32S3_JTAG_SERIAL --preload-port /dev/serial_ports/ESP32S3_PRELOAD --chip esp32s3 --baud 115200 diff --git a/docs/en/advanced-topics/serial-protocol.rst b/docs/en/advanced-topics/serial-protocol.rst index 83a7e3a6b..c2faa307b 100644 --- a/docs/en/advanced-topics/serial-protocol.rst +++ b/docs/en/advanced-topics/serial-protocol.rst @@ -384,7 +384,7 @@ The SPI _ATTACH command enables the SPI flash interface. It takes a 32-bit data .. only:: not esp8266 - On the {IDF_TARGET_NAME} stub loader, it is required to send this command before interacting with SPI flash. + On the {IDF_TARGET_NAME} stub loader sending this command before interacting with SPI flash is optional. On {IDF_TARGET_NAME} ROM loader, it is required to send this command before interacting with SPI flash. +------------------+----------------------------------------------------------------------------------------------------------------------------------+ | Value | Meaning | @@ -400,9 +400,11 @@ The SPI _ATTACH command enables the SPI flash interface. It takes a 32-bit data When writing the values of each pin as 6-bit numbers packed into the data word, each 6-bit value uses the following representation: - * Pin numbers 0 through 30 are represented as themselves. - * Pin numbers 32 & 33 are represented as values 30 & 31. - * It is not possible to represent pins 30 & 31 or pins higher than 33. This is the same 6-bit representation used by the ``SPI_PAD_CONFIG_xxx`` efuses. + .. only:: esp32 + + * Pin numbers 0 through 30 are represented as themselves. + * Pin numbers 32 & 33 are represented as values 30 & 31. + * It is not possible to represent pins 30 & 31 or pins higher than 33. This is the same 6-bit representation used by the ``SPI_PAD_CONFIG_xxx`` efuses. On {IDF_TARGET_NAME} ROM loader only, there is an additional 4 bytes in the data payload of this command. These bytes should all be set to zero. diff --git a/docs/en/esptool/advanced-options.rst b/docs/en/esptool/advanced-options.rst index d47ab515a..83ec8c73b 100644 --- a/docs/en/esptool/advanced-options.rst +++ b/docs/en/esptool/advanced-options.rst @@ -45,7 +45,7 @@ The ``--no-stub`` option disables uploading of a software "stub loader" that man Passing ``--no-stub`` will disable certain options, as not all options are implemented in every chip's ROM loader. -.. only:: esp32 +.. only:: not esp8266 Overriding SPI Flash Connections -------------------------------- @@ -61,42 +61,50 @@ Passing ``--no-stub`` will disable certain options, as not all options are imple The only exception to this is if the ``--no-stub`` option is also provided. In this case, efuse values are ignored and ``--spi-connection`` will default to ``--spi-connection SPI`` unless set to a different value. - SPI Mode - ^^^^^^^^ + .. only:: esp32 - ``--spi-connection SPI`` uses the default SPI pins: + SPI Mode + ^^^^^^^^ - * CLK = GPIO 6 - * Q = GPIO 7 - * D = GPIO 8 - * HD = GPIO 9 - * CS = GPIO 11 + ``--spi-connection SPI`` uses the default SPI pins: - During normal booting, this configuration is selected if all SPI pin efuses are unset and GPIO1 (U0TXD) is not pulled low (default). + * CLK = GPIO 6 + * Q = GPIO 7 + * D = GPIO 8 + * HD = GPIO 9 + * CS = GPIO 11 - This is the normal pin configuration for ESP32 chips that do not contain embedded flash. + During normal booting, this configuration is selected if all SPI pin efuses are unset and GPIO1 (U0TXD) is not pulled low (default). - HSPI Mode - ^^^^^^^^^ + This is the normal pin configuration for ESP32 chips that do not contain embedded flash. - ``--spi-connection HSPI`` uses the HSPI peripheral instead of the SPI peripheral for SPI flash communications, via the following HSPI pins: + HSPI Mode + ^^^^^^^^^ - * CLK = GPIO 14 - * Q = GPIO 12 - * D = GPIO 13 - * HD = GPIO 4 - * CS = GPIO 15 + ``--spi-connection HSPI`` uses the HSPI peripheral instead of the SPI peripheral for SPI flash communications, via the following HSPI pins: - During normal booting, this configuration is selected if all SPI pin efuses are unset and GPIO1 (U0TXD) is pulled low on reset. + * CLK = GPIO 14 + * Q = GPIO 12 + * D = GPIO 13 + * HD = GPIO 4 + * CS = GPIO 15 + + During normal booting, this configuration is selected if all SPI pin efuses are unset and GPIO1 (U0TXD) is pulled low on reset. Custom SPI Pin Configuration ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ``--spi-connection ,,,,`` allows a custom list of pins to be configured for the SPI flash connection. This can be used to emulate the flash configuration equivalent to a particular set of SPI pin efuses being burned. The values supplied are GPIO numbers. - For example, ``--spi-connection 6,17,8,11,16`` sets an identical configuration to the factory efuse configuration for ESP32s with embedded flash. + .. only:: esp32 + + For example, ``--spi-connection 6,17,8,11,16`` sets an identical configuration to the factory efuse configuration for ESP32s with embedded flash. + + When setting a custom pin configuration, the SPI peripheral (not HSPI) will be used unless the ``CLK`` pin value is set to 14 (HSPI CLK), in which case the HSPI peripheral will be used. + + .. note:: - When setting a custom pin configuration, the SPI peripheral (not HSPI) will be used unless the ``CLK`` pin value is set to 14 (HSPI CLK), in which case the HSPI peripheral will be used. + Some GPIO pins might be shared with other peripherals. Therefore, some SPI pad pin configurations might not work reliably or at all. Use a different combination of pins if you encounter issues. Specifying Arguments via File ----------------------------- diff --git a/esptool/__init__.py b/esptool/__init__.py index 206b6fadd..1fdb56f41 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -177,9 +177,9 @@ def add_spi_connection_arg(parent): parent.add_argument( "--spi-connection", "-sc", - help="ESP32-only argument. Override default SPI Flash connection. " + help="Override default SPI Flash connection. " "Value can be SPI, HSPI or a comma-separated list of 5 I/O numbers " - "to use for SPI flash (CLK,Q,D,HD,CS).", + "to use for SPI flash (CLK,Q,D,HD,CS). Not supported with ESP8266.", action=SpiConnectionAction, ) @@ -770,14 +770,22 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): "Keeping initial baud rate %d" % initial_baud ) - # override common SPI flash parameter stuff if configured to do so + # Override the common SPI flash parameter stuff if configured to do so if hasattr(args, "spi_connection") and args.spi_connection is not None: - if esp.CHIP_NAME != "ESP32": - raise FatalError( - "Chip %s does not support --spi-connection option." % esp.CHIP_NAME - ) - print("Configuring SPI flash mode...") - esp.flash_spi_attach(args.spi_connection) + spi_config = args.spi_connection + if args.spi_connection == "SPI": + value = 0 + elif args.spi_connection == "HSPI": + value = 1 + else: + esp.check_spi_connection(args.spi_connection) + # Encode the pin numbers as a 32-bit integer with packed 6-bit values, + # the same way the ESP ROM takes them + clk, q, d, hd, cs = args.spi_connection + spi_config = f"CLK:{clk}, Q:{q}, D:{d}, HD:{hd}, CS:{cs}" + value = (hd << 24) | (cs << 18) | (d << 12) | (q << 6) | clk + print(f"Configuring SPI flash mode ({spi_config})...") + esp.flash_spi_attach(value) elif args.no_stub: print("Enabling default SPI flash mode...") # ROM loader doesn't enable flash unless we explicitly do it @@ -846,6 +854,15 @@ def flash_xmc_startup(): "Try checking the chip connections or removing " "any other hardware connected to IOs." ) + if ( + hasattr(args, "spi_connection") + and args.spi_connection is not None + ): + print( + "Some GPIO pins might be used by other peripherals, " + "try using another --spi-connection combination." + ) + except FatalError as e: raise FatalError(f"Unable to verify flash chip connection ({e}).") @@ -1023,43 +1040,31 @@ class SpiConnectionAction(argparse.Action): """ def __call__(self, parser, namespace, value, option_string=None): - if value.upper() == "SPI": - value = 0 - elif value.upper() == "HSPI": - value = 1 + if value.upper() in ["SPI", "HSPI"]: + values = value.upper() elif "," in value: values = value.split(",") if len(values) != 5: raise argparse.ArgumentError( self, - "%s is not a valid list of comma-separate pin numbers. " - "Must be 5 numbers - CLK,Q,D,HD,CS." % value, + f"{value} is not a valid list of comma-separate pin numbers. " + "Must be 5 numbers - CLK,Q,D,HD,CS.", ) try: values = tuple(int(v, 0) for v in values) except ValueError: raise argparse.ArgumentError( self, - "%s is not a valid argument. All pins must be numeric values" - % values, - ) - if any([v for v in values if v > 33 or v < 0]): - raise argparse.ArgumentError( - self, "Pin numbers must be in the range 0-33." + f"{values} is not a valid argument. " + "All pins must be numeric values", ) - # encode the pin numbers as a 32-bit integer with packed 6-bit values, - # the same way ESP32 ROM takes them - # TODO: make this less ESP32 ROM specific somehow... - clk, q, d, hd, cs = values - value = (hd << 24) | (cs << 18) | (d << 12) | (q << 6) | clk else: raise argparse.ArgumentError( self, - "%s is not a valid spi-connection value. " - "Values are SPI, HSPI, or a sequence of 5 pin numbers CLK,Q,D,HD,CS)." - % value, + f"{value} is not a valid spi-connection value. " + "Values are SPI, HSPI, or a sequence of 5 pin numbers - CLK,Q,D,HD,CS.", ) - setattr(namespace, self.dest, value) + setattr(namespace, self.dest, values) class AutoHex2BinAction(argparse.Action): diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index e9c66da52..fd8e3f518 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -281,7 +281,7 @@ def read_efuse(self, n): return self.read_reg(self.EFUSE_RD_REG_BASE + (4 * n)) def chip_id(self): - raise NotSupportedError(self, "chip_id") + raise NotSupportedError(self, "Function chip_id") def read_mac(self, mac_type="BASE_MAC"): """Read MAC from EFUSE region""" @@ -374,6 +374,11 @@ def change_baud(self, baud): time.sleep(0.05) # get rid of garbage sent during baud rate change self.flush_input() + def check_spi_connection(self, spi_connection): + # Pins 30, 31 do not exist + if not set(spi_connection).issubset(set(range(0, 30)) | set((32, 33))): + raise FatalError("SPI Pin numbers must be in the range 0-29, 32, or 33.") + class ESP32StubLoader(ESP32ROM): """Access class for ESP32 stub loader, runs on top of ROM.""" diff --git a/esptool/targets/esp32c2.py b/esptool/targets/esp32c2.py index ff8341869..d353a71a5 100644 --- a/esptool/targets/esp32c2.py +++ b/esptool/targets/esp32c2.py @@ -8,6 +8,7 @@ from .esp32c3 import ESP32C3ROM from ..loader import ESPLoader +from ..util import FatalError class ESP32C2ROM(ESP32C3ROM): @@ -144,6 +145,10 @@ def is_flash_encryption_key_valid(self): return True return False + def check_spi_connection(self, spi_connection): + if not set(spi_connection).issubset(set(range(0, 21))): + raise FatalError("SPI Pin numbers must be in the range 0-20.") + class ESP32C2StubLoader(ESP32C2ROM): """Access class for ESP32C2 stub loader, runs on top of ROM. diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index 47191b0c2..e00e51786 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -228,6 +228,15 @@ def _post_connect(self): if not self.sync_stub_detected: # Don't run if stub is reused self.disable_watchdogs() + def check_spi_connection(self, spi_connection): + if not set(spi_connection).issubset(set(range(0, 22))): + raise FatalError("SPI Pin numbers must be in the range 0-21.") + if any([v for v in spi_connection if v in [18, 19]]): + print( + "WARNING: GPIO pins 18 and 19 are used by USB-Serial/JTAG, " + "consider using other pins for SPI flash connection." + ) + class ESP32C3StubLoader(ESP32C3ROM): """Access class for ESP32C3 stub loader, runs on top of ROM. diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index c18bf9d1f..0004afeb4 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -180,6 +180,15 @@ def is_flash_encryption_key_valid(self): return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes) + def check_spi_connection(self, spi_connection): + if not set(spi_connection).issubset(set(range(0, 31))): + raise FatalError("SPI Pin numbers must be in the range 0-30.") + if any([v for v in spi_connection if v in [12, 13]]): + print( + "WARNING: GPIO pins 12 and 13 are used by USB-Serial/JTAG, " + "consider using other pins for SPI flash connection." + ) + class ESP32C6StubLoader(ESP32C6ROM): """Access class for ESP32C6 stub loader, runs on top of ROM. diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py index 66600c7da..b042cd7a1 100644 --- a/esptool/targets/esp32h2.py +++ b/esptool/targets/esp32h2.py @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later from .esp32c6 import ESP32C6ROM +from ..util import FatalError class ESP32H2ROM(ESP32C6ROM): @@ -58,6 +59,15 @@ def get_crystal_freq(self): # ESP32H2 XTAL is fixed to 32MHz return 32 + def check_spi_connection(self, spi_connection): + if not set(spi_connection).issubset(set(range(0, 28))): + raise FatalError("SPI Pin numbers must be in the range 0-27.") + if any([v for v in spi_connection if v in [26, 27]]): + print( + "WARNING: GPIO pins 26 and 27 are used by USB-Serial/JTAG, " + "consider using other pins for SPI flash connection." + ) + class ESP32H2StubLoader(ESP32H2ROM): """Access class for ESP32H2 stub loader, runs on top of ROM. diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 0791ab65a..7d9f9bc97 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -169,6 +169,9 @@ def _post_connect(self): # if not self.sync_stub_detected: # Don't run if stub is reused # self.disable_watchdogs() + def check_spi_connection(self, spi_connection): + pass # TODO: Define GPIOs for --spi-connection + class ESP32P4StubLoader(ESP32P4ROM): """Access class for ESP32P4 stub loader, runs on top of ROM. diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py index cd361f918..19f5532c6 100644 --- a/esptool/targets/esp32s2.py +++ b/esptool/targets/esp32s2.py @@ -287,6 +287,15 @@ def hard_reset(self): def change_baud(self, baud): ESPLoader.change_baud(self, baud) + def check_spi_connection(self, spi_connection): + if not set(spi_connection).issubset(set(range(0, 22)) | set(range(26, 47))): + raise FatalError("SPI Pin numbers must be in the range 0-21, or 26-46.") + if any([v for v in spi_connection if v in [19, 20]]): + print( + "WARNING: GPIO pins 19 and 20 are used by USB-OTG, " + "consider using other pins for SPI flash connection." + ) + class ESP32S2StubLoader(ESP32S2ROM): """Access class for ESP32-S2 stub loader, runs on top of ROM. diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 3dc785216..f3d814455 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -349,6 +349,17 @@ def hard_reset(self): def change_baud(self, baud): ESPLoader.change_baud(self, baud) + def check_spi_connection(self, spi_connection): + if not set(spi_connection).issubset(set(range(0, 22)) | set(range(26, 49))): + raise FatalError("SPI Pin numbers must be in the range 0-21, or 26-48.") + if spi_connection[3] > 46: # hd_gpio_num must be <= SPI_GPIO_NUM_LIMIT (46) + raise FatalError("SPI HD Pin number must be <= 46.") + if any([v for v in spi_connection if v in [19, 20]]): + print( + "WARNING: GPIO pins 19 and 20 are used by USB-Serial/JTAG and USB-OTG, " + "consider using other pins for SPI flash connection." + ) + class ESP32S3StubLoader(ESP32S3ROM): """Access class for ESP32S3 stub loader, runs on top of ROM. diff --git a/esptool/targets/esp8266.py b/esptool/targets/esp8266.py index e686abf6e..58e465158 100644 --- a/esptool/targets/esp8266.py +++ b/esptool/targets/esp8266.py @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later from ..loader import ESPLoader -from ..util import FatalError, NotImplementedInROMError +from ..util import FatalError, NotSupportedError class ESP8266ROM(ESPLoader): @@ -170,9 +170,10 @@ def get_erase_size(self, offset, size): return (num_sectors - head_sectors) * sector_size def override_vddsdio(self, new_voltage): - raise NotImplementedInROMError( - "Overriding VDDSDIO setting only applies to ESP32" - ) + raise NotSupportedError(self, "Overriding VDDSDIO") + + def check_spi_connection(self, spi_connection): + raise NotSupportedError(self, "Setting --spi-connection") class ESP8266StubLoader(ESP8266ROM): diff --git a/esptool/util.py b/esptool/util.py index ecd41c0d9..fb4a57193 100644 --- a/esptool/util.py +++ b/esptool/util.py @@ -167,7 +167,7 @@ class NotSupportedError(FatalError): def __init__(self, esp, function_name): FatalError.__init__( self, - "Function %s is not supported for %s." % (function_name, esp.CHIP_NAME), + f"{function_name} is not supported by {esp.CHIP_NAME}.", ) diff --git a/test/test_esptool.py b/test/test_esptool.py index c625ea983..419beeb21 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -230,13 +230,16 @@ def teardown_class(self): # Restore the stored working directory os.chdir(self.stored_dir) - def readback(self, offset, length): + def readback(self, offset, length, spi_connection=None): """Read contents of flash back, return to caller.""" dump_file = tempfile.NamedTemporaryFile(delete=False) # a file we can read into try: - self.run_esptool( + cmd = ( f"--before default_reset read_flash {offset} {length} {dump_file.name}" ) + if spi_connection: + cmd += f" --spi-connection {spi_connection}" + self.run_esptool(cmd) with open(dump_file.name, "rb") as f: rb = f.read() @@ -248,8 +251,10 @@ def readback(self, offset, length): dump_file.close() os.unlink(dump_file.name) - def verify_readback(self, offset, length, compare_to, is_bootloader=False): - rb = self.readback(offset, length) + def verify_readback( + self, offset, length, compare_to, is_bootloader=False, spi_connection=None + ): + rb = self.readback(offset, length, spi_connection) with open(compare_to, "rb") as f: ct = f.read() if len(rb) != len(ct): @@ -764,6 +769,51 @@ def test_flash_id_trace(self): assert "Device:" in res +@pytest.mark.skipif( + os.getenv("ESPTOOL_TEST_SPI_CONN") is None, reason="Needs external flash" +) +class TestExternalFlash(EsptoolTestCase): + conn = os.getenv("ESPTOOL_TEST_SPI_CONN") + + def test_short_flash_to_external_stub(self): + # First flash internal flash, then external + self.run_esptool("write_flash 0x0 images/one_kb.bin") + self.run_esptool( + f"write_flash --spi-connection {self.conn} 0x0 images/sector.bin" + ) + + self.verify_readback(0, 1024, "images/one_kb.bin") + self.verify_readback(0, 1024, "images/sector.bin", spi_connection=self.conn) + + # First flash external flash, then internal + self.run_esptool( + f"write_flash --spi-connection {self.conn} 0x0 images/one_kb.bin" + ) + self.run_esptool("write_flash 0x0 images/sector.bin") + + self.verify_readback(0, 1024, "images/sector.bin") + self.verify_readback(0, 1024, "images/one_kb.bin", spi_connection=self.conn) + + def test_short_flash_to_external_ROM(self): + # First flash internal flash, then external + self.run_esptool("--no-stub write_flash 0x0 images/one_kb.bin") + self.run_esptool( + f"--no-stub write_flash --spi-connection {self.conn} 0x0 images/sector.bin" + ) + + self.verify_readback(0, 1024, "images/one_kb.bin") + self.verify_readback(0, 1024, "images/sector.bin", spi_connection=self.conn) + + # First flash external flash, then internal + self.run_esptool( + f"--no-stub write_flash --spi-connection {self.conn} 0x0 images/one_kb.bin" + ) + self.run_esptool("--no-stub write_flash 0x0 images/sector.bin") + + self.verify_readback(0, 1024, "images/sector.bin") + self.verify_readback(0, 1024, "images/one_kb.bin", spi_connection=self.conn) + + @pytest.mark.skipif( os.name == "nt", reason="Temporarily disabled on windows" ) # TODO: ESPTOOL-673 From 8a5fb4ec3dcdfc5cef4ee35e3ea388a820be3732 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 9 Nov 2023 16:05:44 +0100 Subject: [PATCH 091/209] fix(spi_connection): Unattach previously attached SPI flash Closes https://github.com/espressif/esptool/issues/243 --- .../targets/stub_flasher/stub_flasher_32.json | 6 +- .../stub_flasher/stub_flasher_32c2.json | 4 +- .../stub_flasher/stub_flasher_32c3.json | 4 +- .../stub_flasher/stub_flasher_32c6.json | 4 +- .../stub_flasher/stub_flasher_32c6beta.json | 4 +- .../stub_flasher/stub_flasher_32h2.json | 4 +- .../stub_flasher/stub_flasher_32h2beta1.json | 4 +- .../stub_flasher/stub_flasher_32h2beta2.json | 4 +- .../stub_flasher/stub_flasher_32p4.json | 4 +- .../stub_flasher/stub_flasher_32s2.json | 6 +- .../stub_flasher/stub_flasher_32s3.json | 6 +- .../stub_flasher/stub_flasher_32s3beta2.json | 8 +- flasher_stub/Makefile | 6 +- flasher_stub/include/soc_support.h | 106 +++++++++++++++++- flasher_stub/stub_commands.c | 10 ++ 15 files changed, 144 insertions(+), 36 deletions(-) diff --git a/esptool/targets/stub_flasher/stub_flasher_32.json b/esptool/targets/stub_flasher/stub_flasher_32.json index 23a283fa9..0ea270e33 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32.json +++ b/esptool/targets/stub_flasher/stub_flasher_32.json @@ -1,7 +1,7 @@ { - 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"text_start": 1077379072, - "data": "WADKP7OLN0BHjDdAFJE3QNOMN0BnjDdA04w3QDKNN0D/jTdAcY43QBqON0A9izdAk403QPGNN0BVjTdAlI43QH6NN0CUjjdANYw3QJSMN0DTjDdAMo03QE2MN0B/izdAWI83QNqQN0BWijdA+pA3QFaKN0BWijdAVoo3QFaKN0BWijdAVoo3QFaKN0BWijdA8443QFaKN0DtjzdA2pA3QA==", - "data_start": 1070279668 + "data": "DADKPxeIN0CriDdAw403QDeJN0DLiDdAN4k3QJaJN0C2ijdAKIs3QNGKN0ChhzdASIo3QKiKN0C5iTdATIs3QOGJN0BMizdAmYg3QPiIN0A3iTdAlok3QLGIN0DjhzdABIw3QIWNN0DAhjdAp403QMCGN0DAhjdAwIY3QMCGN0DAhjdAwIY3QMCGN0DAhjdAqYs3QMCGN0CZjDdAhY03QA==", + "data_start": 1070279592 } \ No newline at end of file diff --git a/flasher_stub/Makefile b/flasher_stub/Makefile index 8f4948c50..ac51cd05a 100644 --- a/flasher_stub/Makefile +++ b/flasher_stub/Makefile @@ -139,7 +139,7 @@ $(STUB_ELF_32S2): $(SRCS) $(BUILD_DIR) ld/stub_32s2.ld $(STUB_ELF_32S3_BETA_2): $(SRCS) $(BUILD_DIR) ld/stub_32s3_beta_2.ld @echo " CC(32S3) $^ -> $@" - $(Q) $(CROSS_32S3)gcc $(CFLAGS) -DESP32S3=1 -DESP32S3BETA2=1 -Tstub_32s3_beta_2.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + $(Q) $(CROSS_32S3)gcc $(CFLAGS) -DESP32S3BETA2=1 -Tstub_32s3_beta_2.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) $(STUB_ELF_32S3): $(SRCS) $(BUILD_DIR) ld/stub_32s3.ld @echo " CC(32S3) $^ -> $@" @@ -155,11 +155,11 @@ $(STUB_ELF_32C6BETA): $(SRCS) $(BUILD_DIR) ld/stub_32c6_beta.ld $(STUB_ELF_32H2_BETA_1): $(SRCS) $(BUILD_DIR) ld/stub_32h2_beta_1.ld @echo " CC(32H2BETA1) $^ -> $@" - $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32H2BETA1=1 -DESP32H2BETA1=1 -Tstub_32h2_beta_1.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32H2BETA1=1 -Tstub_32h2_beta_1.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) $(STUB_ELF_32H2_BETA_2): $(SRCS) $(BUILD_DIR) ld/stub_32h2_beta_2.ld @echo " CC(32H2BETA2) $^ -> $@" - $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32H2BETA2=1 -DESP32H2BETA2=1 -Tstub_32h2_beta_2.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32H2BETA2=1 -Tstub_32h2_beta_2.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) $(STUB_ELF_32C2): $(SRCS) $(BUILD_DIR) ld/stub_32c2.ld @echo " CC(32C2) $^ -> $@" diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index f57a740dc..f095adbb5 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -/* SoC-level support for ESP8266/ESP32. +/* SoC-level support. * * Provide a unified register-level interface. * @@ -23,6 +23,7 @@ #define WRITE_REG(REG, VAL) *((volatile uint32_t *)(REG)) = (VAL) #define REG_SET_MASK(reg, mask) WRITE_REG((reg), (READ_REG(reg)|(mask))) #define REG_CLR_MASK(reg, mask) WRITE_REG((reg), (READ_REG(reg)&(~(mask)))) +#define REG_SET_FIELD(_r, _f, _v) (WRITE_REG((_r),((READ_REG(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S))))) #define ESP32_OR_LATER !(ESP8266) #define ESP32S2_OR_LATER !(ESP8266 || ESP32) @@ -84,6 +85,7 @@ #define SPI_BASE_REG 0x3ff42000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x3ff43000 /* SPI peripheral 0, inner state machine */ #define GPIO_BASE_REG 0x3ff44000 /* GPIO */ +#define DR_REG_IO_MUX_BASE 0x3ff49000 #endif #ifdef ESP32S2 @@ -94,6 +96,7 @@ #define USB_BASE_REG 0x60080000 #define RTCCNTL_BASE_REG 0x3f408000 #define SYSTEM_BASE_REG 0x3F4C0000 +#define DR_REG_IO_MUX_BASE 0x3f409000 #endif #ifdef ESP32S3 @@ -105,6 +108,19 @@ #define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ #define USB_DEVICE_BASE_REG 0x60038000 #define SYSTEM_BASE_REG 0x600C0000 +#define DR_REG_IO_MUX_BASE 0x60009000 +#endif + +#ifdef ESP32S3BETA2 +#define UART_BASE_REG 0x60000000 /* UART0 */ +#define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ +#define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ +#define GPIO_BASE_REG 0x60004000 /* GPIO */ +#define USB_BASE_REG 0x60080000 +#define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ +#define USB_DEVICE_BASE_REG 0x60038000 +#define SYSTEM_BASE_REG 0x600C0000 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32C3 @@ -115,6 +131,7 @@ #define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ #define USB_DEVICE_BASE_REG 0x60043000 #define SYSTEM_BASE_REG 0x600C0000 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32C6BETA @@ -122,6 +139,7 @@ #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ #define GPIO_BASE_REG 0x60004000 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32H2BETA1 @@ -130,6 +148,7 @@ #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ #define GPIO_BASE_REG 0x60004000 #define RTCCNTL_BASE_REG 0x60008000 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32H2BETA2 @@ -137,6 +156,7 @@ #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ #define GPIO_BASE_REG 0x60004000 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32C2 @@ -144,6 +164,7 @@ #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ #define GPIO_BASE_REG 0x60004000 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32C6 @@ -154,6 +175,7 @@ #define USB_DEVICE_BASE_REG 0x6000F000 #define DR_REG_PCR_BASE 0x60096000 #define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32H2 @@ -164,6 +186,7 @@ #define USB_DEVICE_BASE_REG 0x6000F000 #define DR_REG_PCR_BASE 0x60096000 #define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_IO_MUX_BASE 0x60009000 #endif #ifdef ESP32P4 @@ -171,6 +194,7 @@ #define SPI_BASE_REG 0x5008D000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x5008C000 /* SPI peripheral 0, inner state machine */ #define GPIO_BASE_REG 0x500E0000 +#define DR_REG_IO_MUX_BASE 0x500E1000 #endif /********************************************************** @@ -427,7 +451,7 @@ #define PCR_SOC_CLK_SEL_V 0x3 #define PCR_SOC_CLK_SEL_S 16 #define PCR_SOC_CLK_MAX 1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK) -#endif // ESP32C6 +#endif // ESP32H2 /********************************************************** * Per-SOC security info buffer size @@ -446,9 +470,9 @@ * Can be retrieved with gdb: "info address rom_spiflash_legacy_funcs" */ -#if ESP32 || ESP32S2 || ESP32S3 +#if ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 #define ROM_SPIFLASH_LEGACY 0x3ffae270 -#endif // ESP32 || ESP32S2 || ESP32S3 +#endif // ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 #if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 #define ROM_SPIFLASH_LEGACY 0x3fcdfff4 @@ -465,3 +489,77 @@ #if ESP32P4 #define ROM_SPIFLASH_LEGACY 0x4ff3ffec #endif // ESP32P4 + +/********************************************************** + * IO-MUX peripheral + */ + +#define MCU_SEL 0x7 +#define MCU_SEL_S 12 + +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#if ESP32 +// PERIPHS_IO_MUX_SD_... +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x60) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x68) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x64) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x5c) +#define FUNC_GPIO 2 +#endif // ESP32 + +#if ESP32S2 +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x7c) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x80) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x84) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x78) +#define FUNC_GPIO 1 +#endif // ESP32S2 + +#if ESP32C3 +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x40) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x48) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x44) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x3c) +#define FUNC_GPIO 1 +#endif // ESP32C3 + +#if ESP32S3 || ESP32S3BETA2 +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x7c) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x80) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x84) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x78) +#define FUNC_GPIO 1 +#endif // ESP32S3 || ESP32S3BETA2 + +#if ESP32C2 +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x40) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x48) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x44) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x3c) +#define FUNC_GPIO 1 +#endif // ESP32C2 + +#if ESP32C6 || ESP32C6BETA +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x78) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x68) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x7c) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x64) +#define FUNC_GPIO 1 +#endif // ESP32C6 || ESP32C6BETA + +#if ESP32H2 || ESP32H2BETA1 || ESP32H2BETA2 +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x50) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x44) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x54) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x40) +#define FUNC_GPIO 1 +#endif // ESP32H2 || ESP32H2BETA1 || ESP32H2BETA2 + +#if ESP32P4 +#define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x7c) +#define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x80) +#define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x84) +#define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x78) +#define FUNC_GPIO 1 +#endif // ESP32P4 diff --git a/flasher_stub/stub_commands.c b/flasher_stub/stub_commands.c index 11340e19d..f2b658245 100644 --- a/flasher_stub/stub_commands.c +++ b/flasher_stub/stub_commands.c @@ -186,6 +186,16 @@ esp_command_error handle_spi_attach(uint32_t hspi_config_arg) see https://github.com/themadinventor/esptool/issues/98 */ SelectSpiFunction(); #else + /* Stub calls spi_flash_attach automatically when it boots, + therefore, we need to "unattach" the flash before attaching again + with different configuration to avoid issues. */ + + // Configure the SPI flash pins back as classic GPIOs + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_GPIO); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIQ_U, FUNC_GPIO); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPID_U, FUNC_GPIO); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICS0_U, FUNC_GPIO); + /* spi_flash_attach calls SelectSpiFunction() and another function to initialise SPI flash interface. From 35dfbde8515723b1ec5d3d67c38150a983243820 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 7 Nov 2023 15:37:53 +0100 Subject: [PATCH 092/209] fix(tests/intelhex): make sure file is closed on Windows --- test/test_esptool.py | 19 ++++++++++++++----- test/test_merge_bin.py | 10 +++++----- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/test/test_esptool.py b/test/test_esptool.py index 419beeb21..dd1dd0a7f 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -396,22 +396,27 @@ def test_adjacent_flash(self): self.verify_readback(4096, 50 * 1024, "images/fifty_kb.bin") def test_short_flash_hex(self): - _, f = tempfile.mkstemp(suffix=".hex") + fd, f = tempfile.mkstemp(suffix=".hex") try: self.run_esptool(f"merge_bin --format hex 0x0 images/one_kb.bin -o {f}") + # make sure file is closed before running next command (mainly for Windows) + os.close(fd) self.run_esptool(f"write_flash 0x0 {f}") self.verify_readback(0, 1024, "images/one_kb.bin") finally: os.unlink(f) def test_adjacent_flash_hex(self): - _, f1 = tempfile.mkstemp(suffix=".hex") - _, f2 = tempfile.mkstemp(suffix=".hex") + fd1, f1 = tempfile.mkstemp(suffix=".hex") + fd2, f2 = tempfile.mkstemp(suffix=".hex") try: self.run_esptool(f"merge_bin --format hex 0x0 images/sector.bin -o {f1}") + # make sure file is closed before running next command (mainly for Windows) + os.close(fd1) self.run_esptool( f"merge_bin --format hex 0x1000 images/fifty_kb.bin -o {f2}" ) + os.close(fd2) self.run_esptool(f"write_flash 0x0 {f1} 0x1000 {f2}") self.verify_readback(0, 4096, "images/sector.bin") self.verify_readback(4096, 50 * 1024, "images/fifty_kb.bin") @@ -420,11 +425,13 @@ def test_adjacent_flash_hex(self): os.unlink(f2) def test_adjacent_flash_mixed(self): - _, f = tempfile.mkstemp(suffix=".hex") + fd, f = tempfile.mkstemp(suffix=".hex") try: self.run_esptool( f"merge_bin --format hex 0x1000 images/fifty_kb.bin -o {f}" ) + # make sure file is closed before running next command (mainly for Windows) + os.close(fd) self.run_esptool(f"write_flash 0x0 images/sector.bin 0x1000 {f}") self.verify_readback(0, 4096, "images/sector.bin") self.verify_readback(4096, 50 * 1024, "images/fifty_kb.bin") @@ -1063,12 +1070,14 @@ def test_load_ram_hex(self): The "hello world" binary programs for each chip print "Hello world!\n" to the serial port. """ - _, f = tempfile.mkstemp(suffix=".hex") + fd, f = tempfile.mkstemp(suffix=".hex") try: self.run_esptool( f"merge_bin --format hex -o {f} 0x0 " f"images/ram_helloworld/helloworld-{arg_chip}.bin" ) + # make sure file is closed before running next command (mainly for Windows) + os.close(fd) self.run_esptool(f"load_ram {f}") self.verify_output( [b"Hello world!", b'\xce?\x13\x05\x04\xd0\x97A\x11"\xc4\x06\xc67\x04'] diff --git a/test/test_merge_bin.py b/test/test_merge_bin.py index 83abbff92..c15cc0151 100755 --- a/test/test_merge_bin.py +++ b/test/test_merge_bin.py @@ -252,11 +252,11 @@ def test_merge_bin2hex(self): # convert back and verify the result against the source bin file with tempfile.NamedTemporaryFile(suffix=".hex", delete=False) as hex: hex.write(merged) - merged_bin = self.run_merge_bin( - "esp32", - [(0x1000, hex.name)], - options=["--format", "raw"], - ) + merged_bin = self.run_merge_bin( + "esp32", + [(0x1000, hex.name)], + options=["--format", "raw"], + ) source = read_image("bootloader_esp32.bin") # verify that padding was done correctly assert b"\xFF" * 0x1000 == merged_bin[:0x1000] From 6ffa14b5d98f5e04e3fe4fe664647a0571d34c7a Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 10 Nov 2023 16:08:11 +0100 Subject: [PATCH 093/209] fix(load_ram): check for overlaps in bss section Newer toolchains now store jump table in the data section which results in .bss section to be used more as well. This change should ensure that we avoid overwriting the bss section of the flasher stub when writing to RAM. --- esptool/bin_image.py | 7 +++++++ esptool/loader.py | 12 +++++++----- esptool/targets/stub_flasher/stub_flasher_32.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_32c2.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_32c3.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_32c6.json | 3 ++- .../targets/stub_flasher/stub_flasher_32c6beta.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_32h2.json | 3 ++- .../targets/stub_flasher/stub_flasher_32h2beta1.json | 3 ++- .../targets/stub_flasher/stub_flasher_32h2beta2.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_32p4.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_32s2.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_32s3.json | 3 ++- .../targets/stub_flasher/stub_flasher_32s3beta2.json | 3 ++- esptool/targets/stub_flasher/stub_flasher_8266.json | 3 ++- flasher_stub/wrap_stub.py | 4 ++++ 16 files changed, 44 insertions(+), 18 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index b011b55b5..55ca6359e 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -1135,6 +1135,7 @@ class ESP32H2FirmwareImage(ESP32C6FirmwareImage): class ELFFile(object): SEC_TYPE_PROGBITS = 0x01 SEC_TYPE_STRTAB = 0x03 + SEC_TYPE_NOBITS = 0x08 # e.g. .bss section SEC_TYPE_INITARRAY = 0x0E SEC_TYPE_FINIARRAY = 0x0F @@ -1225,6 +1226,7 @@ def read_section_header(offs): all_sections = [read_section_header(offs) for offs in section_header_offsets] prog_sections = [s for s in all_sections if s[1] in ELFFile.PROG_SEC_TYPES] + nobits_secitons = [s for s in all_sections if s[1] == ELFFile.SEC_TYPE_NOBITS] # search for the string table section if not (shstrndx * self.LEN_SEC_HEADER) in section_header_offsets: @@ -1256,6 +1258,11 @@ def read_data(offs, size): if lma != 0 and size > 0 ] self.sections = prog_sections + self.nobits_sections = [ + ELFSection(lookup_string(n_offs), lma, b"") + for (n_offs, _type, lma, size, offs) in nobits_secitons + if lma != 0 and size > 0 + ] def _read_segments(self, f, segment_header_offs, segment_header_count, shstrndx): f.seek(segment_header_offs) diff --git a/esptool/loader.py b/esptool/loader.py index bd1fcbab2..6061fded7 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -170,6 +170,8 @@ def __init__(self, json_path): self.data = None self.data_start = None + self.bss_start = stub.get("bss_start") + class ESPLoader(object): """Base class providing access to ESP ROM & software stub bootloaders. @@ -780,17 +782,17 @@ def mem_begin(self, size, blocks, blocksize, offset): stub = StubFlasher(get_stub_json_path(self.CHIP_NAME)) load_start = offset load_end = offset + size - for start, end in [ - (stub.data_start, stub.data_start + len(stub.data)), - (stub.text_start, stub.text_start + len(stub.text)), + for stub_start, stub_end in [ + (stub.bss_start, stub.data_start + len(stub.data)), # DRAM = bss+data + (stub.text_start, stub.text_start + len(stub.text)), # IRAM ]: - if load_start < end and load_end > start: + if load_start < stub_end and load_end > stub_start: raise FatalError( "Software loader is resident at 0x%08x-0x%08x. " "Can't load binary at overlapping address range 0x%08x-0x%08x. " "Either change binary loading address, or use the --no-stub " "option to disable the software loader." - % (start, end, load_start, load_end) + % (stub_start, stub_end, load_start, load_end) ) return self.check_command( diff --git a/esptool/targets/stub_flasher/stub_flasher_32.json b/esptool/targets/stub_flasher/stub_flasher_32.json index 0ea270e33..56221e30b 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32.json +++ b/esptool/targets/stub_flasher/stub_flasher_32.json @@ -3,5 +3,6 @@ "text": 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"text_start": 1074520064, "data": "DMD8P+znC0B/6AtAZ+0LQAbpC0Cf6AtABukLQGXpC0CC6gtA9OoLQJ3qC0CV5wtAGuoLQHTqC0CI6QtAGOsLQLDpC0AY6wtAbegLQMroC0AG6QtAZekLQIXoC0DI6wtAKe0LQLjmC0BL7QtAuOYLQLjmC0C45gtAuOYLQLjmC0C45gtAuOYLQLjmC0Bv6wtAuOYLQEnsC0Ap7QtA", - "data_start": 1073605544 + "data_start": 1073605544, + "bss_start": 1073528832 } \ No newline at end of file diff --git a/esptool/targets/stub_flasher/stub_flasher_32c2.json b/esptool/targets/stub_flasher/stub_flasher_32c2.json index 1b80bd7bf..f10ec7b48 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32c2.json +++ b/esptool/targets/stub_flasher/stub_flasher_32c2.json @@ -3,5 +3,6 @@ "text": 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6ciKksCp3IYb8IHeQklcMQiEsG5kbREJhLHIhLpcXAsa9/4IhLSYoAsaYAEaBAAzix7ICxi8AkiEl0CnApiICBiUAIZv84DCUQXX8KiNAIpAiEgwAMhEwIDGW8gAwKTEWEgUnPAJGIwAGEgAADKPHs0KRkPx8+AADQOBgkWBgBCAoMCommiJAIpAikgwbc9ZCBitjPQdnvN0GBgCiISd8w6BhBAwSYCODbQIcA8Z1/tIhJF0LYiElZ73gIg0AGz0AHEAAIqEg7iCLzAzi3QPHMgJG2/+GBwAiDQGLPAATQAAyoSINACvdABxAACKhICMgIO4gwswQIW784DCUYUj8KiNgIpAyEgwAMxEwIDGWogAwOTEgIIRGCQAAAIFl/AykfPcbNAAEQOBAkUBABCAnMCokiiJgIpAikgxNA5Yi/gADQODgkTDMwCJhKAzzJyMVITP8ciEo+jIhV/wb/yojckIABjQAAIIhKGa4Gtx/HAmSYSgGAQDSISRdCxwTISj8fPY5YgZB/jFM/CojIsLwIgIAImEmJzwdBg4AoiEnfMOgYQQMEmAjg20CHCPGNf4AANIhJF0LYiElZ73eG90LLSICAHIhJgAcQAAioYvMIO4gdzzhgiEmMTn8kiEoDBYAGEAAZqGaMwtmMsPw4CYQYgMAAAhA4OCRKmYhMvyAzMAqLwwDZrkMMQX8+kMxLvw6NDIDAE0GUmE0YmE1smE2AUH8wAAAYiE1UiE0av+yITaGAAAADA9x+vtCJxFiJxJqZGe/AoZ5//eWB4YCANIhJF0LHFNGyf8A8Rr8IRv8PQ9SYTRiYTWyYTZyYTMBLfzAAAByITMhBPwyJxFCJxI6PwEo/MAAALIhNmIhNVIhNDHj+yjDCyIpw/Hh+3jP1me4hj4BYiElDOLQNsCmQw9Br/tQNMCmIwJGTQDGMQIAx7ICRi4ApiMCBiUAQdX74CCUQCKQIhK8ADIRMCAxlgIBMCkxFkIFJzwChiQAxhIAAAAMo8ezRHz4kqSwAANA4GCRYGAEICgwKiaaIkAikCKSDBtz1oIGK2M9B2e83YYGAHIhJ3zDcGEEDBJgI4NtAhxzxtT9AADSISRdC4IhJYe93iINABs9ABxAACKhIO4gi8wM4t0DxzICxtv/BggAAAAiDQGLPAATQAAyoSINACvdABxAACKhICMgIO4gwswQQaj74CCUQCKQIhK8ACIRIPAxlo8AICkx8PCExggADKN892KksBsjAANA4DCRMDAE8Pcw+vNq/0D/kPKfDD0Cli/+AAJA4OCRIMzAIqD/96ICxkAAhgIAAByDBtMA0iEkXQshYvsnte/yRQBtDxtVRusADOLHMhkyDQEiDQCAMxEgIyAAHEAAIqEg7iAr3cLMEDGD++AglKoiMCKQIhIMACIRIDAxICkx1hMCDKQbJAAEQOBAkUBABDA5MDo0QXj7ijNAM5AykwxNApbz/f0DAAJA4OCRIMzAd4N8YqAOxzYaQg0BIg0AgEQRICQgABxAACKhIO4g0s0CwswQQWn74CCUqiJAIpBCEgwARBFAIDFASTHWEgIMphtGAAZA4GCRYGAEICkwKiZhXvuKImAikCKSDG0ElvL9MkUAAARA4OCRQMzAdwIIG1X9AkYCAAAAIkUBK1UGc//wYIRm9gKGswAirv8qZiF6++BmEWoiKAIiYSYhePtyISZqYvgGFpcFdzwdBg4AAACCISd8w4BhBAwSYCODbQIckwZb/dIhJF0LkiEll73gG90LLSICAKIhJgAcQAAioYvMIO4gpzzhYiEmDBIAFkAAIqELIuAiEGDMwAAGQODgkSr/DOLHsgJGMAByISXQJ8CmIgKGJQBBLPvgIJRAIpAi0g8iEgwAMhEwIDGW8gAwKTEWMgUnPAJGJACGEgAADKPHs0SRT/t8+AADQOBgkWBgBCAoMCommiJAIpAikgwbc9aCBitjPQdnvN2GBgCCISd8w4BhBAwSYCODbQIco8Yr/QAA0iEkXQuSISWXvd4iDQAbPQAcQAAioSDuIIvMDOLdA8cyAkbb/wYIAAAAIg0BizwAE0AAMqEiDQAr3QAcQAAioSAjICDuIMLMEGH/+uAglGAikCLSDzISDAAzETAgMZaCADA5MSAghMYIAIEk+wykfPcbNAAEQOBAkUBABCAnMCokiiJgIpAikgxNA5Yi/gADQODgkTDMwDEa++AiESozOAMyYSYxGPuiISYqIygCImEoFgoGpzweRg4AciEnfMNwYQQMEmAjg20CHLPG9/wAAADSISRdC4IhJYe93RvdCy0iAgCSISYAHEAAIqGLzCDuIJc84aIhJgwSABpAACKhYiEoCyLgIhAqZgAKQODgkaDMwGJhKHHi+oIhKHB1wJIhKzHf+oAnwJAiEDoicmEqPQUntQE9AkGW+vozbQ83tG0GEgAhwPosUzliBm4APFMhvfp9DTliDCZGbABdC9IhJEYAAP0GIYv6J7XhoiEqYiEociErYCrAMcn6cCIQKiMiAgAbqiJFAKJhKhtVC29WH/0GDAAAMgIAYsb9MkUAMgIBMkUBMgICOyIyRQI7VfY24xYGATICADJFAGYmBSICASJFAWpV/QaioLB8+YKksHKhAAa9/iGc+iiyB+IChpb8wCAkJzwgRg8AgiEnfMOAYQQMEmAjg20CLAMGrPwAAF0L0iEkRgAA/QaSISWXvdkb3QstIgIAABxAACKhi8wg7iDAICQnPOHAICQAAkDg4JF8giDMEH0NRgEAAAt3wsz4oiEkd7oC9ozxIbD6MbD6TQxSYTRyYTOyYTZFlAALIrIhNnIhM1IhNCDuEAwPFkwGhgwAAACCISd8w4BhBAwSYCODbQIskwYPAHIhJF0LkiEll7fgG3cLJyICAAAcQAAioSDuIIvMtozk4DB0wsz44OhBhgoAoiEnfMOgYQQMEmAjg20CLKMhX/o5YoYPAAAAciEkXQtiISVnt9kyBwAbd0FZ+hv/KKSAIhEwIiAppPZPB8bd/3IhJF0LIVL6LCM5YgwGhgEAciEkXQt89iYWFEsmzGJGAwALd8LM+IIhJHe4AvaM8YFI+iF4+jF4+sl4TQxSYTRiYTVyYTOCYTKyYTbFhQCCITKSISiiISYLIpnokiEq4OIQomgQciEzoiEkUiE0siE2YiE1+fjiaBSSaBWg18CwxcD9BpZWDjFl+vjYLQwFfgDw4PRNAvDw9X0MDHhiITWyITZGJQAAAJICAKICAurpkgIB6pma7vr+4gIDmpqa/5qe4gIEmv+anuICBZr/mp7iAgaa/5qe4gIHmv+a7ur/iyI6kkc5wEAjQbAisLCQYEYCAAAyAgAbIjru6v8qOb0CRzPvMUf6LQ5CYTFiYTVyYTOCYTKyYTZFdQAxQfrtAi0PxXQAQiExciEzsiE2QHfAgiEyQTr6YiE1/QKMhy0LsDjAxub/AAAA/xEhAfrq7+nS/QbcVvii8O7AfO/g94NGAgAAAAAMDN0M8q/9MS36UiEpKCNiISTQIsDQVcDaZtEJ+ikjOA1xCPpSYSnKU1kNcDXADAIMFfAlg2JhJCAgdFaCAELTgEAlgxaSAMH++S0MBSkAyQ2CISmcKJHl+Sg5FrIA8C8x8CLA1iIAxoP7MqDHId/5li8BjB9GS/oh3PkyIgPME4ZI+jKgyDlShkb6KC2MEsZE+iHo+QEU+sAAAAEW+sAAAEZA+sg9zByGPvoio+gBDvrAAADADADGOvriYSIMfEaN+gEO+sAAAAwcDAMGCAAAyC34PfAsICAgtMwSxpT6Rif7Mi0DIi0CxTIAMqAADBwgw4PGIvt4fWhtWF1ITTg9KC0MDAH0+cAAAO0CDBLgwpOGHvsAAAHu+cAAAAwMBhj7ACHC+UhdOC1JAiHA+TkCBvr/Qb75DAI4BMKgyDDCgykEQbr5PQwMHCkEMMKDBgz7xzICxvT9xvv9AiFDkqEQwiFC0iFB4iFA8iE/mhEN8AAACAAAYBwAAGAAAABgEAAAYCH8/xLB8OkBwCAA6AIJMckh2REh+P/AIADIAsDAdJzs0Zb5RgQAAAAx9P/AIAAoAzgNICB0wAMAC8xmDOqG9P8h7/8IMcAgAOkCyCHYEegBEsEQDfAAAAD4AgBgEAIAYAACAGAAAAAIIfz/wCAAOAIwMCRWQ/8h+f9B+v/AIAA5AjH3/8AgAEkDwCAASANWdP/AIAAoAgwTICAEMCIwDfAAAIAAAAAAQP///wAEAgBgEsHwySHBbPkJMShM2REWgghF+v8WIggoTAzzDA0nowwoLDAiEAwTINOD0NB0EBEgRfj/FmL/Id7/Me7/wCAAOQLAIAAyIgBWY/8x1//AIAAoAyAgJFZC/ygsMeX/QEIRIWH50DKDIeT/ICQQQeT/wCAAKQQhz//AIAA5AsAgADgCVnP/DBIcA9Ajk90CKEzQIsApTCgs2tLZLAgxyCHYERLBEA3wAAAATEoAQBLB4MlhwUH5+TH4POlBCXHZUe0C97MB/QMWHwTYHNrf0NxBBgEAAACF8v8oTKYSBCgsJ63yRe3/FpL/KBxNDz0OAe7/wAAAICB0jDIioMQpXCgcSDz6IvBEwCkcSTwIcchh2FHoQfgxEsEgDfAAAAD/DwAAUSb5EsHwCTEMFEJFADBMQUklQfr/ORUpNTAwtEoiKiMgLEEpRQwCImUFAVf5wAAACDEyoMUgI5MSwRAN8AAAADA7AEASwfAJMTKgwDeSESKg2wH7/8AAACKg3EYEAAAAADKg2zeSCAH2/8AAACKg3QH0/8AAAAgxEsEQDfAAAAASwfDJIdkRCTHNAjrSRgIAACIMAMLMAcX6/9ec8wIhA8IhAtgREsEQDfAAAFgQAABwEAAAGJgAQBxLAEA0mABAAJkAQJH7/xLB4Mlh6UH5MQlx2VGQEcDtAiLREM0DAfX/wAAA8fb4hgoA3QzHvwHdD00NPQEtDgHw/8AAACAgdPxCTQ09ASLREAHs/8AAANDugNDMwFYc/SHl/zLREBA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- "data_start": 1073720488 + "data_start": 1073720488, + "bss_start": 1073643776 } \ No newline at end of file diff --git a/flasher_stub/wrap_stub.py b/flasher_stub/wrap_stub.py index 504d9f883..f63db4f25 100755 --- a/flasher_stub/wrap_stub.py +++ b/flasher_stub/wrap_stub.py @@ -39,6 +39,10 @@ def wrap_stub(elf_file): except ValueError: pass + for s in e.nobits_sections: + if s.name == ".bss": + stub["bss_start"] = s.addr + # Pad text with NOPs to mod 4. if len(stub["text"]) % 4 != 0: stub["text"] += (4 - (len(stub["text"]) % 4)) * "\0" From 64cefc8dc737eafa592995e69706815efdf73b40 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Wed, 22 Nov 2023 17:24:07 +0100 Subject: [PATCH 094/209] fix(esptool): Rephrase the --ram-only-header command message Signed-off-by: Marek Matej --- esptool/cmds.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 3a6f914e0..87abb880f 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -983,10 +983,7 @@ def elf2image(args): print("Creating {} image...".format(args.chip)) if args.ram_only_header: - print( - "RAM only visible in the header - only RAM segments are visible to the " - "ROM loader!" - ) + print("ROM segments hidden - only RAM segments are visible to the ROM loader!") if args.chip != "esp8266": image = CHIP_DEFS[args.chip].BOOTLOADER_IMAGE() From 936f26b478cf13d2d6101a92f65bd8aa735f4805 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Tue, 14 Nov 2023 08:51:29 +0100 Subject: [PATCH 095/209] fix(test_esptool): Fixed connection issue on Windows --- test/test_esptool.py | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/test/test_esptool.py b/test/test_esptool.py index dd1dd0a7f..5c15d18fb 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -669,11 +669,14 @@ def test_show_security_info(self): assert "Crypt Count" in res assert "Key Purposes" in res if arg_chip != "esp32s2": - esp = esptool.get_default_connected_device( - [arg_port], arg_port, 10, 115200, arg_chip - ) - assert f"Chip ID: {esp.IMAGE_CHIP_ID}" in res - assert "API Version" in res + try: + esp = esptool.get_default_connected_device( + [arg_port], arg_port, 10, 115200, arg_chip + ) + assert f"Chip ID: {esp.IMAGE_CHIP_ID}" in res + assert "API Version" in res + finally: + esp._port.close() assert "Secure Boot" in res assert "Flash Encryption" in res From 4e4b881c48b12797aa70ff6747c76a21ccf12e65 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Thu, 9 Nov 2023 14:22:12 +0100 Subject: [PATCH 096/209] fix(esp32c2): Recommend using higher baud rate if connection fails --- docs/en/esptool/serial-connection.rst | 6 ++++++ esptool/loader.py | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/docs/en/esptool/serial-connection.rst b/docs/en/esptool/serial-connection.rst index ed710edd4..e6e4ab93c 100644 --- a/docs/en/esptool/serial-connection.rst +++ b/docs/en/esptool/serial-connection.rst @@ -40,6 +40,12 @@ When communicating with the {IDF_TARGET_NAME} ROM serial bootloader, the followi | Flow control | None | +---------------------+-------------------+ +.. only:: esp32c2 + + .. note:: + + You might experience issues when using low baud rates on {IDF_TARGET_NAME}. If you encounter any problems when connecting, please use at least 115200 or higher. + .. only:: esp8266 .. note:: diff --git a/esptool/loader.py b/esptool/loader.py index 6061fded7..bc08a919f 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -682,8 +682,17 @@ def connect( print("") # end 'Connecting...' line if last_error is not None: + additional_msg = "" + if self.CHIP_NAME == "ESP32-C2" and self._port.baudrate < 115200: + additional_msg = ( + "\nNote: Please set a higher baud rate (--baud)" + " if ESP32-C2 doesn't connect" + " (at least 115200 Bd is recommended)." + ) + raise FatalError( "Failed to connect to {}: {}" + f"{additional_msg}" "\nFor troubleshooting steps visit: " "https://docs.espressif.com/projects/esptool/en/latest/troubleshooting.html".format( # noqa E501 self.CHIP_NAME, last_error From 43906a50bab2273374dae99940ba7c1654e49f34 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 22 Nov 2023 13:47:19 +0100 Subject: [PATCH 097/209] docs(serial-protocol): add images and flowchart --- .../diag/command_packet_format.diag | 13 +++++++ .../diag/download_procedure_chart.diag | 39 +++++++++++++++++++ .../diag/response_packet_format.diag | 13 +++++++ docs/en/advanced-topics/serial-protocol.rst | 21 +++++++++- 4 files changed, 84 insertions(+), 2 deletions(-) create mode 100644 docs/en/advanced-topics/diag/command_packet_format.diag create mode 100644 docs/en/advanced-topics/diag/download_procedure_chart.diag create mode 100644 docs/en/advanced-topics/diag/response_packet_format.diag diff --git a/docs/en/advanced-topics/diag/command_packet_format.diag b/docs/en/advanced-topics/diag/command_packet_format.diag new file mode 100644 index 000000000..ffb09c03a --- /dev/null +++ b/docs/en/advanced-topics/diag/command_packet_format.diag @@ -0,0 +1,13 @@ +packetdiag command_packet_format{ + colwidth = 16 + node_width = 50 + node_height = 50 + default_fontsize = 16 + + 0: "0x00"; + 1: "Cmd"; + 2-3: "Size"; + 4-7: "Checksum"; + 8-15: "Data" [color = lightgrey]; + 16-31: "..." [color = lightgrey]; +} diff --git a/docs/en/advanced-topics/diag/download_procedure_chart.diag b/docs/en/advanced-topics/diag/download_procedure_chart.diag new file mode 100644 index 000000000..5bbc2081b --- /dev/null +++ b/docs/en/advanced-topics/diag/download_procedure_chart.diag @@ -0,0 +1,39 @@ +blockdiag download_procedure_diagram { + node_height = 40; + node_width = 150; + span_width = 40; + span_height = 45; + default_fontsize = 12 + orientation = portrait; + edge_layout = flowchart; + default_group_color = none; + + // nodes + start [label = "Start", shape = flowchart.terminator]; + sync [label = "Synchronization", shape = box]; + success_cond [label = "Success?", shape = flowchart.condition]; + erase_data [label = "Erase data", shape = box]; + transmit_data [label = "Transmit data", shape = box]; + finish_cond [label = "Finish?", shape = flowchart.condition]; + transmit_finish [label = "Transmit finish frame", shape = box]; + finish [label = "Finish", shape = flowchart.terminator]; + // fake nodes to adjust shape and edge label position + succ_fin [shape = none]; + fincon_fin [shape = none]; + + // edges + start -> sync -> success_cond; + success_cond -> erase_data [label = "Yes"]; + erase_data -> transmit_data; + transmit_data -> finish_cond; + success_cond -- succ_fin [label = "Timeout"]; + finish_cond -> transmit_finish [label = "Yes"]; + finish_cond -- fincon_fin [label = "Failure"]; + succ_fin -- fincon_fin; + fincon_fin -> finish; + transmit_finish -> finish; + + // group + group{transmit_finish, fincon_fin}; + group{erase_data, succ_fin}; +} diff --git a/docs/en/advanced-topics/diag/response_packet_format.diag b/docs/en/advanced-topics/diag/response_packet_format.diag new file mode 100644 index 000000000..8a0b00904 --- /dev/null +++ b/docs/en/advanced-topics/diag/response_packet_format.diag @@ -0,0 +1,13 @@ +packetdiag command_packet_format{ + colwidth = 16 + node_width = 50 + node_height = 50 + default_fontsize = 16 + + 0: "0x01"; + 1: "Cmd"; + 2-3: "Size"; + 4-7: "Value"; + 8-15: "Data" [color = lightgrey]; + 16-31: "..." [color = lightgrey]; +} diff --git a/docs/en/advanced-topics/serial-protocol.rst b/docs/en/advanced-topics/serial-protocol.rst index c2faa307b..90b0b9932 100644 --- a/docs/en/advanced-topics/serial-protocol.rst +++ b/docs/en/advanced-topics/serial-protocol.rst @@ -27,7 +27,7 @@ The host computer sends a SLIP encoded command request to the ESP chip. The ESP Low Level Protocol ^^^^^^^^^^^^^^^^^^ -The bootloader protocol uses `SLIP `_ packet framing for data transmissions in both directions. +The bootloader protocol uses `SLIP `_ packet framing for data transmissions in both directions. Each SLIP packet begins and ends with ``0xC0``. Within the packet, all occurrences of ``0xC0`` and ``0xDB`` are replaced with ``0xDB 0xDC`` and ``0xDB 0xDD``, respectively. The replacing is to be done **after** the checksum and lengths are calculated, so the packet length may be longer than the ``size`` field below. @@ -36,6 +36,11 @@ Command Packet Each command is a SLIP packet initiated by the host and results in a response packet. Inside the packet, the packet consists of a header and a variable-length body. All multi-byte fields are little-endian. +.. packetdiag:: diag/command_packet_format.diag + :caption: Command packet format + :align: center + + +--------+-------------+--------------------------------------------------------------------------------------------------------------------+ | Byte | Name | Comment | +========+=============+====================================================================================================================+ @@ -55,6 +60,10 @@ Response Packet Each received command will result in a response SLIP packet sent from the ESP chip to the host. Contents of the response packet is: +.. packetdiag:: diag/response_packet_format.diag + :caption: Command packet format + :align: center + +--------+-------------+--------------------------------------------------------------------------------------------------------------+ | Byte | Name | Comment | +========+=============+==============================================================================================================+ @@ -270,7 +279,7 @@ ROM loaders will not recognise these commands. Checksum ^^^^^^^^ -The checksum field is ignored (can be zero) for all comands except for MEM_DATA, FLASH_DATA, and FLASH_DEFL_DATA. +The checksum field is ignored (can be zero) for all commands except for MEM_DATA, FLASH_DATA, and FLASH_DEFL_DATA. Each of the ``_DATA`` command packets (like ``FLASH_DEFL_DATA``, ``MEM_DATA``) has the same "data payload" format: @@ -297,6 +306,14 @@ To calculate checksum, start with seed value 0xEF and XOR each individual byte i Functional Description ---------------------- +.. blockdiag:: diag/download_procedure_chart.diag + :caption: Download procedure flow chart + :align: center + + +.. note:: + This flow chart is used to illustrate the download procedure (writing to flash), other commands have different flows. + Initial Synchronisation ^^^^^^^^^^^^^^^^^^^^^^^ .. list:: From b8b59542f9d8109b18e9476ce5d38dce7dc01607 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Tue, 28 Nov 2023 14:31:07 +0100 Subject: [PATCH 098/209] fix: fixed exit() to be used from right module --- espefuse/efuse/esp32c2/fields.py | 5 +++-- espefuse/efuse/esp32c3/fields.py | 5 +++-- espefuse/efuse/esp32c6/fields.py | 5 +++-- espefuse/efuse/esp32h2/fields.py | 5 +++-- espefuse/efuse/esp32h2beta1/fields.py | 5 +++-- espefuse/efuse/esp32p4/fields.py | 5 +++-- espefuse/efuse/esp32s2/fields.py | 5 +++-- espefuse/efuse/esp32s3/fields.py | 5 +++-- espefuse/efuse/esp32s3beta2/fields.py | 5 +++-- setup.py | 2 +- 10 files changed, 28 insertions(+), 19 deletions(-) diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index dda997e58..cba599e63 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -198,7 +199,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -212,7 +213,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index 7a09c65c5..05914e429 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -206,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -220,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index a62004f1a..5e0a449e5 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -206,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -220,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index add5db76f..46182607b 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -206,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -220,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index 3e8f28928..16bc78f04 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -206,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -220,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py index 4b912ec5c..415a6b33d 100644 --- a/espefuse/efuse/esp32p4/fields.py +++ b/espefuse/efuse/esp32p4/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -207,7 +208,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -221,7 +222,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32s2/fields.py b/espefuse/efuse/esp32s2/fields.py index a4113848b..15d927529 100644 --- a/espefuse/efuse/esp32s2/fields.py +++ b/espefuse/efuse/esp32s2/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -206,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -220,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index 604c4a45c..7cd8cd952 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -206,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -220,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 26abb9f1f..0622350b1 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -206,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -220,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): diff --git a/setup.py b/setup.py index 0f1b2826b..c80122659 100644 --- a/setup.py +++ b/setup.py @@ -16,7 +16,7 @@ "Please see the installation section in the esptool documentation" " for instructions on how to install it." ) - exit(1) + sys.exit(1) # Example code to pull version from esptool module with regex, taken from From 6284a830dc750db81cdf533f04fb0dd1cb443885 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Mon, 20 Nov 2023 13:31:17 +0100 Subject: [PATCH 099/209] fix(testloadram): Windows assertion error --- test/test_esptool.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/test_esptool.py b/test/test_esptool.py index 5c15d18fb..14cf7f0f7 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -1049,7 +1049,7 @@ class TestLoadRAM(EsptoolTestCase): def verify_output(self, expected_out: List[bytes]): """Verify that at least one element of expected_out is in serial output""" - with serial.serial_for_url(arg_port, arg_baud) as p: + with serial.serial_for_url(arg_port, arg_baud, rtscts=True) as p: p.timeout = 5 output = p.read(100) print(f"Output: {output}") From d0873e3b46b96ced93833962b55c42f84b024cc8 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Mon, 20 Nov 2023 13:34:37 +0100 Subject: [PATCH 100/209] docs(advanced-topics): Fixed strapping pin for Automatic Bootloader section --- docs/en/advanced-topics/boot-mode-selection.rst | 2 +- test/test_esptool.py | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index 62e187b5a..56468ada2 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -125,7 +125,7 @@ Automatic Bootloader As an example of auto-reset curcuitry implementation, check the `schematic `_ of the ESP32 DevKitC development board: -- The **Micro USB 5V & USB-UART** section shows the ``DTR`` and ``RTS`` control lines of the USB to serial converter chip connected to ``GPIO0`` and ``EN`` pins of the ESP module. +- The **Micro USB 5V & USB-UART** section shows the ``DTR`` and ``RTS`` control lines of the USB to serial converter chip connected to ``{IDF_TARGET_STRAP_BOOT_GPIO}`` and ``EN`` pins of the ESP module. - Some OS and/or drivers may activate ``RTS`` and or ``DTR`` automatically when opening the serial port (true only for some serial terminal programs, not ``esptool.py``), pulling them low together and holding the ESP in reset. If ``RTS`` is wired directly to ``EN`` then RTS/CTS "hardware flow control" needs to be disabled in the serial program to avoid this. An additional circuitry is implemented in order to avoid this problem - if both ``RTS`` and ``DTR`` are asserted together, this doesn't reset the chip. The schematic shows this specific circuit with two transistors and its truth table. - If this circuitry is implemented (all Espressif boards have it), adding a capacitor between the ``EN`` pin and ``GND`` (in the 1uF-10uF range) is necessary for the reset circuitry to work reliably. This is shown in the **ESP32 Module** section of the schematic. diff --git a/test/test_esptool.py b/test/test_esptool.py index 14cf7f0f7..5cb221d1b 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -1049,6 +1049,12 @@ class TestLoadRAM(EsptoolTestCase): def verify_output(self, expected_out: List[bytes]): """Verify that at least one element of expected_out is in serial output""" + # Setting rtscts to true enables hardware flow control. + # This removes unwanted RTS logic level changes for some machines + # (and, therefore, chip resets) + # when the port is opened by the following function. + # As a result, the app loaded to RAM has a chance to run and send + # "Hello world" data without unwanted chip reset. with serial.serial_for_url(arg_port, arg_baud, rtscts=True) as p: p.timeout = 5 output = p.read(100) From 1abecfb9cfb185c04d322b523ee4f3e8b97b1dfb Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 5 Dec 2023 15:43:30 +0100 Subject: [PATCH 101/209] ci(commitizen): Automatic changelog, revamp GH release process --- .cz.toml | 24 +++++++ .github/workflows/build_esptool.yml | 65 +++++++++---------- CHANGELOG.md | 98 +++++++++++++++++++++++++++++ ci/gh_changelog_template.md.j2 | 22 +++++++ esptool/__init__.py | 2 +- setup.py | 1 + 6 files changed, 174 insertions(+), 38 deletions(-) create mode 100644 .cz.toml create mode 100644 CHANGELOG.md create mode 100644 ci/gh_changelog_template.md.j2 diff --git a/.cz.toml b/.cz.toml new file mode 100644 index 000000000..ce0e7715c --- /dev/null +++ b/.cz.toml @@ -0,0 +1,24 @@ +[tool.commitizen] +version = "4.6.2" +update_changelog_on_bump = true +tag_format = "v$version" +changelog_start_rev = "v4.2.1" +changelog_merge_prerelease = true +annotated_tag = true +bump_message = "change: Update version to $new_version" +version_files = [ + "esptool/__init__.py:__version__" +] +change_type_order = [ + "BREAKING CHANGE", + "New Features", + "Bug Fixes", + "Code Refactoring", + "Performance Improvements" +] + +[tool.commitizen.change_type_map] +feat = "New Features" +fix = "Bug Fixes" +refactor = "Code Refactoring" +perf = "Performance Improvements" \ No newline at end of file diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index eeb7b076f..1e3f4a0b9 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -83,52 +83,43 @@ jobs: create_release: name: Create GitHub release - if: startsWith(github.ref, 'refs/tags/') + if: startsWith(github.ref, 'refs/tags/') && !(contains(github.ref_name, 'dev')) needs: build-esptool-binaries runs-on: ubuntu-latest - outputs: - upload_url: ${{ steps.create_release.outputs.upload_url }} - VERSION: ${{ steps.get_version.outputs.VERSION }} + permissions: + contents: write steps: - - name: Create release - id: create_release - uses: actions/create-release@v1 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - with: - tag_name: ${{ github.ref }} - release_name: Version ${{ github.ref }} - draft: true - prerelease: false - name: Get version id: get_version - run: echo ::set-output name=VERSION::${GITHUB_REF/refs\/tags\//} + run: echo "VERSION=${GITHUB_REF#refs/tags/v}" >> $GITHUB_OUTPUT shell: bash - - upload_assets: - name: Upload release assets - if: startsWith(github.ref, 'refs/tags/') - needs: create_release - runs-on: ubuntu-latest - strategy: - matrix: - TARGET: [macos, linux-amd64, win64, arm, arm64] - env: - DISTPATH: esptool-${{ needs.create_release.outputs.VERSION }}-${{ matrix.TARGET }} - steps: + - name: Checkout + uses: actions/checkout@master + with: + fetch-depth: 0 + - name: Install dependencies + run: | + python -m pip install --upgrade pip + pip install --user -e ".[dev]" + - name: Generate changelog + run: | + cz changelog ${{ steps.get_version.outputs.VERSION }} --template ci/gh_changelog_template.md.j2 --file-name changelog_body.md + cat changelog_body.md - name: Download built binaries uses: actions/download-artifact@master - - name: Rename and package binaries + - name: Compress and rename binaries run: | - mv esptool-${{ matrix.TARGET }} ${{ env.DISTPATH }} - zip -r ${{ env.DISTPATH }}.zip ./${{ env.DISTPATH }}/* - - name: Upload release assets - id: upload-release-asset - uses: actions/upload-release-asset@v1 + for dir in esptool-*; do + zip -r "esptool-v${{ steps.get_version.outputs.VERSION }}-${dir#esptool-}.zip" "$dir" + done + - name: Create release + id: create_release + uses: softprops/action-gh-release@v1 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} with: - upload_url: ${{ needs.create_release.outputs.upload_url }} - asset_path: "${{ env.DISTPATH }}.zip" - asset_name: "${{ env.DISTPATH }}.zip" - asset_content_type: application/zip + body_path: changelog_body.md + name: Version ${{ steps.get_version.outputs.VERSION }} + draft: true + prerelease: false + files: esptool-v${{ steps.get_version.outputs.VERSION }}-*.zip diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 000000000..eb25d5c79 --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,98 @@ +## v4.6.2 (2023-06-12) + +### Bug Fixes + +- **CH9102F**: Suggest to install new serial drivers if writing to RAM fails +- **compressed upload**: Accept short data blocks with only Adler-32 bytes + +## v4.6.1 (2023-06-01) + +### Bug Fixes + +- **ESP32-S3**: Correct RTC WDT registers to fix resets during flashing + +## v4.6 (2023-05-29) + +### New Features + +- **esptool**: add option to dump whole flash based on detected size + +### Bug Fixes + +- inconsistent usage of dirs separator +- USB-JTAG-Serial PID detection error +- Set flash parameters even with --flash_size keep +- **ESP32-C6**: Fix get_pkg_version and get_{major,minor}_chip_version + +## v4.5.1 (2023-02-28) + +### Bug Fixes + +- **ESP32-S3**: Temporarily disable increasing CPU freq +- Unknown chip (ID or magic number) error +- **ESP32-S3**: Lower CPU freq to improve flasher stub stability +- **rfc2217_server**: Use new reset sequences + +## v4.5 (2023-02-10) + +### New Features + +- **stub**: Add ESP32-S3 octal flash support +- **esp32h2**: Enable USB-JTAG/Serial mode in the stub flasher +- **bootloader reset**: Allow custom reset strategy setting with a config file +- Allow configuration with a config file +- **bootloader reset**: Tighter transitions on Unix systems +- **ci**: Publish development releases with custom pipeline +- **esp32c6 stub**: Increase CPU frequency and write/read speeds over USB-JTAG/Serial +- **esp32c6 stub**: Enable USB-JTAG/Serial +- **flash_id**: Print the flash type if available for the chip + +### Bug Fixes + +- **cmds**: Make clear that flash type is from eFuse and not detection +- **load config file**: Sort unknown config options +- **esp32c6**: Workaround for bad MSPI frequency in HS mode +- **flasher_stub**: Correct boundaries for SPIWrite4B and SPIRead4B +- **secure download mode**: Reconnect if ROM refuses to respond +- **secure download mode**: Fix SDM detection on S2/S3 +- **ci**: Merge two "ci" directories and build_tools into one +- **ci**: The development release job should not run by default +- **setup**: Use latest reedsolo package which can be installed with Python3.10 and Cython +- **write_flash**: Fix `--erase-all` option +- **espefuse**: Close serial port even when espefuse fails +- **espefuse**: Fix compatibility with Bitstring>=4 + +### Code Refactoring + +- Comply with black 23.1 style +- Optimize unnecessary chip interrogations +- **connection attempt**: Decouple reset sequence settings + +## v4.4 (2022-11-21) + +### New Features + +- **flasher_stub**: Increase CPU frequency and write/read speeds over native USB (USB-OTG) +- **flasher_stub**: Increase CPU frequency and write/read speeds over USB-JTAG/Serial +- Readable error message for serial-related issues +- Detect Guru Meditation errors + +### Bug Fixes + +- Add workaround for breaking changes of bitstring==4 +- close unused ports while get_default_connected_device + +## v4.3 (2022-09-14) + +### New Features + +- **image_info**: Print application information if possible +- Add Macronix flash memory density definitions +- **write_flash**: Prevent flashing incompatible images +- Recover from serial errors when flashing +- Add stub flasher error messages definitions +- **image_info**: Image type autodetection + +### Code Refactoring + +- **elf2image**: Simplify bootloader image selection diff --git a/ci/gh_changelog_template.md.j2 b/ci/gh_changelog_template.md.j2 new file mode 100644 index 000000000..a58bce964 --- /dev/null +++ b/ci/gh_changelog_template.md.j2 @@ -0,0 +1,22 @@ +{# This changelog template is used for automatically generated GH release notes. #} +{# It is passed to commitizen's --template option in a GH Actions workflow run. #} + +{% for entry in tree %} + +{% for change_key, changes in entry.changes.items() %} + +{% if change_key %} +### {{ change_key }} +{% endif %} + +{% for change in changes %} +{% if change.scope %} +- **{{ change.scope }}**: {{ change.message }} +{% elif change.message %} +- {{ change.message }} +{% endif %} +{% endfor %} +{% endfor %} +{% endfor %} + +Thanks to , and others for contributing to this release! diff --git a/esptool/__init__.py b/esptool/__init__.py index 1fdb56f41..e35c903ba 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.7-dev" +__version__ = "4.6.2" import argparse import inspect diff --git a/setup.py b/setup.py index c80122659..67912bc0b 100644 --- a/setup.py +++ b/setup.py @@ -118,6 +118,7 @@ def find_version(*file_paths): "pytest", "pytest-rerunfailures", "requests", + "commitizen", ], "hsm": [ "python-pkcs11", From 0d31643554d3dabe6f15b523e1598fc3f7c3b776 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 5 Dec 2023 15:51:14 +0100 Subject: [PATCH 102/209] ci(dangerjs_gh): Use new shared-github-dangerjs linter --- .github/workflows/dangerjs.yml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml index ab9f002a6..c84b5dccb 100644 --- a/.github/workflows/dangerjs.yml +++ b/.github/workflows/dangerjs.yml @@ -1,4 +1,4 @@ -name: DangerJS Check +name: DangerJS Pull Request linter on: pull_request_target: types: [opened, edited, reopened, synchronize] @@ -12,11 +12,14 @@ jobs: runs-on: ubuntu-latest steps: - name: Check out PR head - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: ref: ${{ github.event.pull_request.head.sha }} - + - name: DangerJS pull request linter - uses: espressif/github-actions/danger_pr_review@master + uses: espressif/shared-github-dangerjs@v1 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + instructions-contributions-file: 'CONTRIBUTING.rst' + instructions-gitlab-mirror: 'true' From 38efd90996dc8804f437c7af54b6f00498a62fa2 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 6 Dec 2023 10:35:41 +0100 Subject: [PATCH 103/209] change(pre_commit): Bump pre-commit checks --- .pre-commit-config.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index f2fdbc737..04f91d000 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1,15 +1,15 @@ repos: - repo: https://github.com/PyCQA/flake8 - rev: 4.0.1 + rev: 6.1.0 hooks: - id: flake8 additional_dependencies: [flake8-import-order] - repo: https://github.com/psf/black - rev: 22.3.0 + rev: 23.11.0 hooks: - id: black - repo: https://github.com/espressif/conventional-precommit-linter - rev: v1.2.1 + rev: v1.4.0 hooks: - id: conventional-precommit-linter stages: [commit-msg] From 0b49bc2ba001ea0635a426170d6bfe2a929fe0c9 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Tue, 28 Nov 2023 08:53:18 +0100 Subject: [PATCH 104/209] fix(esp32c2): Added get_flash_cap and get_flash_vendor Closes https://github.com/espressif/esptool/issues/932 --- esptool/targets/esp32c2.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/esptool/targets/esp32c2.py b/esptool/targets/esp32c2.py index d353a71a5..edfc3b1c0 100644 --- a/esptool/targets/esp32c2.py +++ b/esptool/targets/esp32c2.py @@ -85,6 +85,16 @@ def get_major_chip_version(self): num_word = 1 return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 20) & 0x3 + def get_flash_cap(self): + # ESP32-C2 doesn't have eFuse field FLASH_CAP. + # Can't get info about the flash chip. + return 0 + + def get_flash_vendor(self): + # ESP32-C2 doesn't have eFuse field FLASH_VENDOR. + # Can't get info about the flash chip. + return "" + def get_crystal_freq(self): # The crystal detection algorithm of ESP32/ESP8266 works for ESP32-C2 as well. return ESPLoader.get_crystal_freq(self) From 5b79bb268108e6242876592ff3089f0cb65d834b Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Mon, 11 Dec 2023 10:25:41 +0100 Subject: [PATCH 105/209] feat(test_esptool): Added test for embedded and detected flash size match --- test/test_esptool.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/test/test_esptool.py b/test/test_esptool.py index 5cb221d1b..279b8ebdf 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -778,6 +778,22 @@ def test_flash_id_trace(self): assert "Manufacturer:" in res assert "Device:" in res + @pytest.mark.quick_test + @pytest.mark.skipif( + arg_chip not in ["esp32c2"], + reason="This test make sense only for EPS32-C2", + ) + def test_flash_size(self): + """Test ESP32-C2 efuse block for flash size feature""" + # ESP32-C2 class inherits methods from ESP32-C3 class + # but it does not have the same amount of efuse blocks + # the methods are overwritten + # in case anything changes this test will fail to remind us + res = self.run_esptool("flash_id") + lines = res.splitlines() + for line in lines: + assert "embedded flash" not in line.lower() + @pytest.mark.skipif( os.getenv("ESPTOOL_TEST_SPI_CONN") is None, reason="Needs external flash" From af5e8d09a42e5b409feac2c350a2a44157a5c68f Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 13 Dec 2023 12:05:18 +0100 Subject: [PATCH 106/209] change: Update version to 4.7.0 --- .cz.toml | 2 +- CHANGELOG.md | 58 +++++++++++++++++++++++++++++++++++++++++++++ esptool/__init__.py | 2 +- 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/.cz.toml b/.cz.toml index ce0e7715c..cca4ea574 100644 --- a/.cz.toml +++ b/.cz.toml @@ -1,5 +1,5 @@ [tool.commitizen] -version = "4.6.2" +version = "4.7.0" update_changelog_on_bump = true tag_format = "v$version" changelog_start_rev = "v4.2.1" diff --git a/CHANGELOG.md b/CHANGELOG.md index eb25d5c79..447147995 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,3 +1,61 @@ +## v4.7.0 (2023-12-13) + +### New Features + +- **test_esptool**: Added test for embedded and detected flash size match +- **spi_connection**: Support --spi-connection on all chips +- **espefuse**: Support XTS_AES_256_KEY key_purpose for ESP32P4 +- **xip_psram**: support xip psram feature on esp32p4 +- add support for intel hex format +- **esp32p4**: Stub flasher support +- **elf2image**: add ram-only-header argument +- **rfc2217_server**: Add hard reset sequence +- **espefuse**: Adds efuse ADC calibration data for ESP32H2 +- **espefuse**: Update the way to complete the operation +- add support for get_security_info on esp32c3 ECO7 +- **loader**: Added hints for some serial port issues when rising port error +- Add support for Python 3.12 +- **esp32c3**: Support ECO6 and ECO7 magic numbers +- **merge_bin**: add support for uf2 format +- **esp32-s3**: Support >16MB quad flash chips +- **efuse**: Update key purpose table and tests +- **efuse**: ESP32P4 adds ecdsa_key support +- **espefuse**: Add support for esp32p4 chip +- **esptool**: added target to esp32p4 +- **espsecure**: Allow prompting for HSM PIN in read_hsm_config +- **esptool**: Add new packages for ESP32C3 and flash efuses +- **esptool**: Add tests for get_chip_features +- **esptool**: Add PICO package for ESP32S3 and flash/psram efuses +- **get_security_info**: Improved the output format and added more details + +### Bug Fixes + +- **esp32c2**: Added get_flash_cap and get_flash_vendor +- **testloadram**: Windows assertion error +- fixed exit() to be used from right module +- **esp32c2**: Recommend using higher baud rate if connection fails +- **test_esptool**: Fixed connection issue on Windows +- **esptool**: Rephrase the --ram-only-header command message +- **load_ram**: check for overlaps in bss section +- **tests/intelhex**: make sure file is closed on Windows +- **spi_connection**: Unattach previously attached SPI flash +- **espefuse**: Fix ECDSA_FORCE_USE_HARDWARE_K for ECDSA key (esp32h2) +- **loader**: Could not open serial port message adjusted +- **flasher_stub**: fix usb-serial-jtag enabled non-related intr source +- **bin_image**: Check only ELF sections when searching for .flash.appdesc +- **danger-github**: Fir Danger GitHub token permission +- Fix redirection of STDOUT +- **autodetection**: Remove the ESP32-S2 ROM class from get_security_info autodetection +- assert in esp32 exclusive workaround +- **elf2image**: fix text/rodata mapping overlap issue on uni-idrom bus chips +- **dangerGH**: Update token permissions - allow Danger to add comments to PR +- **expand file args**: Correctly print the expanded command +- **esp32-c2**: Enable flashing in secure download mode + +### Code Refactoring + +- **stub_flasher**: Cleanup, make adding new targets easier + ## v4.6.2 (2023-06-12) ### Bug Fixes diff --git a/esptool/__init__.py b/esptool/__init__.py index e35c903ba..ffe6db787 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.6.2" +__version__ = "4.7.0" import argparse import inspect From dc67f3bb3d712e4b74c0829992ca52c75fdbaaf9 Mon Sep 17 00:00:00 2001 From: Karolina Surma <33810531+befeleme@users.noreply.github.com> Date: Thu, 14 Dec 2023 15:53:05 +0100 Subject: [PATCH 107/209] fix(esptool): Remove the shebang from uf2_writer.py This is not a script, so there' no need for it. --- esptool/uf2_writer.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/esptool/uf2_writer.py b/esptool/uf2_writer.py index 554c8450c..81772d424 100644 --- a/esptool/uf2_writer.py +++ b/esptool/uf2_writer.py @@ -1,5 +1,3 @@ -#!/usr/bin/env python -# # SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: GPL-2.0-or-later # Code was originally licensed under Apache 2.0 before the release of ESP-IDF v5.2 From 85915e79d856724f601ca16f28fb5c70ed6d6aac Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 19 Dec 2023 14:12:47 +0100 Subject: [PATCH 108/209] ci(danger): Disable changelog update checks --- .gitlab-ci.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 52f347cbb..ed1410e09 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -22,6 +22,8 @@ include: file: danger.yaml run-danger-mr-linter: stage: pre-check + variables: + ENABLE_CHECK_UPDATED_CHANGELOG: 'false' # cache the pip download directory in all jobs variables: From 1595874cf6d4832da1456e55b6de2edcd0a4147d Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 20 Dec 2023 19:49:05 +0800 Subject: [PATCH 109/209] feat(esp32c5): add target esp32c5 beta3 ROM version: 20230803 --- espefuse/__init__.py | 4 + espefuse/efuse/esp32c5beta3/__init__.py | 3 + .../esp32c5beta3/emulate_efuse_controller.py | 92 ++++ espefuse/efuse/esp32c5beta3/fields.py | 456 ++++++++++++++++++ espefuse/efuse/esp32c5beta3/mem_definition.py | 169 +++++++ espefuse/efuse/esp32c5beta3/operations.py | 413 ++++++++++++++++ espsecure/__init__.py | 4 +- esptool/bin_image.py | 11 + esptool/loader.py | 7 +- esptool/targets/__init__.py | 2 + esptool/targets/esp32c5beta3.py | 99 ++++ .../stub_flasher/stub_flasher_32c5beta3.json | 8 + flasher_stub/Makefile | 6 + flasher_stub/include/rom_functions.h | 4 +- flasher_stub/include/soc_support.h | 25 +- flasher_stub/ld/rom_32c5_beta_3.ld | 429 ++++++++++++++++ flasher_stub/ld/stub_32c5_beta_3.ld | 26 + flasher_stub/stub_flasher.c | 6 +- 18 files changed, 1750 insertions(+), 14 deletions(-) create mode 100644 espefuse/efuse/esp32c5beta3/__init__.py create mode 100644 espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py create mode 100644 espefuse/efuse/esp32c5beta3/fields.py create mode 100644 espefuse/efuse/esp32c5beta3/mem_definition.py create mode 100644 espefuse/efuse/esp32c5beta3/operations.py create mode 100644 esptool/targets/esp32c5beta3.py create mode 100644 esptool/targets/stub_flasher/stub_flasher_32c5beta3.json create mode 100755 flasher_stub/ld/rom_32c5_beta_3.ld create mode 100644 flasher_stub/ld/stub_32c5_beta_3.ld diff --git a/espefuse/__init__.py b/espefuse/__init__.py index 777d53f41..849c3a270 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -11,6 +11,7 @@ import espefuse.efuse.esp32 as esp32_efuse import espefuse.efuse.esp32c2 as esp32c2_efuse import espefuse.efuse.esp32c3 as esp32c3_efuse +import espefuse.efuse.esp32c5beta3 as esp32c5beta3_efuse import espefuse.efuse.esp32c6 as esp32c6_efuse import espefuse.efuse.esp32h2 as esp32h2_efuse import espefuse.efuse.esp32h2beta1 as esp32h2beta1_efuse @@ -49,6 +50,9 @@ "esp32c2": DefChip("ESP32-C2", esp32c2_efuse, esptool.targets.ESP32C2ROM), "esp32c3": DefChip("ESP32-C3", esp32c3_efuse, esptool.targets.ESP32C3ROM), "esp32c6": DefChip("ESP32-C6", esp32c6_efuse, esptool.targets.ESP32C6ROM), + "esp32c5beta3": DefChip( + "ESP32-C5(beta3)", esp32c5beta3_efuse, esptool.targets.ESP32C5BETA3ROM + ), "esp32h2": DefChip("ESP32-H2", esp32h2_efuse, esptool.targets.ESP32H2ROM), "esp32p4": DefChip("ESP32-P4", esp32p4_efuse, esptool.targets.ESP32P4ROM), "esp32h2beta1": DefChip( diff --git a/espefuse/efuse/esp32c5beta3/__init__.py b/espefuse/efuse/esp32c5beta3/__init__.py new file mode 100644 index 000000000..a3b55a802 --- /dev/null +++ b/espefuse/efuse/esp32c5beta3/__init__.py @@ -0,0 +1,3 @@ +from . import operations +from .emulate_efuse_controller import EmulateEfuseController +from .fields import EspEfuses diff --git a/espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py b/espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py new file mode 100644 index 000000000..27816831a --- /dev/null +++ b/espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py @@ -0,0 +1,92 @@ +# This file describes eFuses controller for ESP32-C5 beta3 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from ..emulate_efuse_controller_base import EmulateEfuseControllerBase, FatalError + + +class EmulateEfuseController(EmulateEfuseControllerBase): + """The class for virtual efuse operation. Using for HOST_TEST.""" + + CHIP_NAME = "ESP32-C5(beta3)" + mem = None + debug = False + + def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + super(EmulateEfuseController, self).__init__(efuse_file, debug) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) + + """ esptool method start >>""" + + def get_major_chip_version(self): + return 0 + + def get_minor_chip_version(self): + return 0 + + def get_crystal_freq(self): + return 40 # MHz (common for all chips) + + def get_security_info(self): + return { + "flags": 0, + "flash_crypt_cnt": 0, + "key_purposes": 0, + "chip_id": 0, + "api_version": 0, + } + + """ << esptool method end """ + + def handle_writing_event(self, addr, value): + if addr == self.REGS.EFUSE_CMD_REG: + if value & self.REGS.EFUSE_PGM_CMD: + self.copy_blocks_wr_regs_to_rd_regs(updated_block=(value >> 2) & 0xF) + self.clean_blocks_wr_regs() + self.check_rd_protection_area() + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) + elif value == self.REGS.EFUSE_READ_CMD: + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) + self.save_to_file() + + def get_bitlen_of_block(self, blk, wr=False): + if blk.id == 0: + if wr: + return 32 * 8 + else: + return 32 * blk.len + else: + if wr: + rs_coding = 32 * 3 + return 32 * 8 + rs_coding + else: + return 32 * blk.len + + def handle_coding_scheme(self, blk, data): + if blk.id != 0: + # CODING_SCHEME RS applied only for all blocks except BLK0. + coded_bytes = 12 + data.pos = coded_bytes * 8 + plain_data = data.readlist("32*uint:8")[::-1] + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(coded_bytes) + # 32 byte of data + 12 bytes RS + calc_encoded_data = list(rs.encode([x for x in plain_data])) + data.pos = 0 + if calc_encoded_data != data.readlist("44*uint:8")[::-1]: + raise FatalError("Error in coding scheme data") + data = data[coded_bytes * 8 :] + if blk.len < 8: + data = data[(8 - blk.len) * 32 :] + return data diff --git a/espefuse/efuse/esp32c5beta3/fields.py b/espefuse/efuse/esp32c5beta3/fields.py new file mode 100644 index 000000000..416eb5807 --- /dev/null +++ b/espefuse/efuse/esp32c5beta3/fields.py @@ -0,0 +1,456 @@ +# This file describes eFuses for ESP32-C5 beta3 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import binascii +import struct +import sys +import time + +from bitstring import BitArray + +import esptool + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from .. import base_fields +from .. import util + + +class EfuseBlock(base_fields.EfuseBlockBase): + def len_of_burn_unit(self): + # The writing register window is 8 registers for any blocks. + # len in bytes + return 8 * 4 + + def __init__(self, parent, param, skip_read=False): + parent.read_coding_scheme() + super(EfuseBlock, self).__init__(parent, param, skip_read=skip_read) + + def apply_coding_scheme(self): + data = self.get_raw(from_read=False)[::-1] + if len(data) < self.len_of_burn_unit(): + add_empty_bytes = self.len_of_burn_unit() - len(data) + data = data + (b"\x00" * add_empty_bytes) + if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS: + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(12) + # 32 byte of data + 12 bytes RS + encoded_data = rs.encode([x for x in data]) + words = struct.unpack("<" + "I" * 11, encoded_data) + # returns 11 words (8 words of data + 3 words of RS coding) + else: + # takes 32 bytes + words = struct.unpack("<" + ("I" * (len(data) // 4)), data) + # returns 8 words + return words + + +class EspEfuses(base_fields.EspEfusesBase): + """ + Wrapper object to manage the efuse fields in a connected ESP bootloader + """ + + debug = False + do_not_confirm = False + + def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() + self._esp = esp + self.debug = debug + self.do_not_confirm = do_not_confirm + if esp.CHIP_NAME != "ESP32-C5(beta3)": + raise esptool.FatalError( + "Expected the 'esp' param for ESP32-C5(beta3) chip but got for '%s'." + % (esp.CHIP_NAME) + ) + if not skip_connect: + flags = self._esp.get_security_info()["flags"] + GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE = 1 << 2 + if flags & GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE: + raise esptool.FatalError( + "Secure Download Mode is enabled. The tool can not read eFuses." + ) + self.blocks = [ + EfuseBlock(self, self.Blocks.get(block), skip_read=skip_connect) + for block in self.Blocks.BLOCKS + ] + if not skip_connect: + self.get_coding_scheme_warnings() + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] + self.efuses += [ + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS + ] + if skip_connect: + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + else: + if self["BLK_VERSION_MINOR"].get() == 1: + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + self.efuses += [ + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC + ] + + def __getitem__(self, efuse_name): + """Return the efuse field with the given name""" + for e in self.efuses: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): + return e + new_fields = False + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + new_fields = True + if new_fields: + for e in self.efuses: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): + return e + raise KeyError + + def read_coding_scheme(self): + self.coding_scheme = self.REGS.CODING_SCHEME_RS + + def print_status_regs(self): + print("") + self.blocks[0].print_block(self.blocks[0].err_bitarray, "err__regs", debug=True) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG) + ) + ) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG) + ) + ) + + def efuse_controller_setup(self): + self.set_efuse_timing() + self.clear_pgm_registers() + self.wait_efuse_idle() + + def write_efuses(self, block): + self.efuse_program(block) + return self.get_coding_scheme_warnings(silent=True) + + def clear_pgm_registers(self): + self.wait_efuse_idle() + for r in range( + self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4 + ): + self.write_reg(r, 0) + + def wait_efuse_idle(self): + deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT + while time.time() < deadline: + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return + raise esptool.FatalError( + "Timed out waiting for Efuse controller command to complete" + ) + + def efuse_program(self, block): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE) + self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2)) + self.wait_efuse_idle() + self.clear_pgm_registers() + self.efuse_read() + + def efuse_read(self): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE) + # need to add a delay after triggering EFUSE_READ_CMD, as ROM loader checks some + # efuse registers after each command is completed + # if ENABLE_SECURITY_DOWNLOAD or DIS_DOWNLOAD_MODE is enabled by the current cmd, then we need to try to reconnect to the chip. + try: + self.write_reg( + self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_READ_CMD, delay_after_us=1000 + ) + self.wait_efuse_idle() + except esptool.FatalError: + secure_download_mode_before = self._esp.secure_download_mode + + try: + self._esp = self.reconnect_chip(self._esp) + except esptool.FatalError: + print("Can not re-connect to the chip") + if not self["DIS_DOWNLOAD_MODE"].get() and self[ + "DIS_DOWNLOAD_MODE" + ].get(from_read=False): + print( + "This is the correct behavior as we are actually burning " + "DIS_DOWNLOAD_MODE which disables the connection to the chip" + ) + print("DIS_DOWNLOAD_MODE is enabled") + print("Successful") + sys.exit(0) # finish without errors + raise + + print("Established a connection with the chip") + if self._esp.secure_download_mode and not secure_download_mode_before: + print("Secure download mode is enabled") + if not self["ENABLE_SECURITY_DOWNLOAD"].get() and self[ + "ENABLE_SECURITY_DOWNLOAD" + ].get(from_read=False): + print( + "espefuse tool can not continue to work in Secure download mode" + ) + print("ENABLE_SECURITY_DOWNLOAD is enabled") + print("Successful") + sys.exit(0) # finish without errors + raise + + def set_efuse_timing(self): + """Set timing registers for burning efuses""" + # Configure clock + apb_freq = self.get_crystal_freq() + if apb_freq not in [40, 48]: + raise esptool.FatalError( + "The eFuse supports only xtal=40M and 48M (xtal was %d)" % apb_freq + ) + + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 + ) + + def get_coding_scheme_warnings(self, silent=False): + """Check if the coding scheme has detected any errors.""" + old_addr_reg = 0 + reg_value = 0 + ret_fail = False + for block in self.blocks: + if block.id == 0: + words = [ + self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) + for offs in range(5) + ] + block.err_bitarray.pos = 0 + for word in reversed(words): + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) + block.num_errors = block.err_bitarray.count(True) + block.fail = block.num_errors != 0 + else: + addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[ + block.id + ] + if err_num_mask is None or err_num_offs is None or fail_bit is None: + continue + if addr_reg != old_addr_reg: + old_addr_reg = addr_reg + reg_value = self.read_reg(addr_reg) + block.fail = reg_value & (1 << fail_bit) != 0 + block.num_errors = (reg_value >> err_num_offs) & err_num_mask + ret_fail |= block.fail + if not silent and (block.fail or block.num_errors): + print( + "Error(s) in BLOCK%d [ERRORS:%d FAIL:%d]" + % (block.id, block.num_errors, block.fail) + ) + if (self.debug or ret_fail) and not silent: + self.print_status_regs() + return ret_fail + + def summary(self): + # TODO add support set_flash_voltage - "Flash voltage (VDD_SPI)" + return "" + + +class EfuseField(base_fields.EfuseFieldBase): + @staticmethod + def convert(parent, efuse): + return { + "mac": EfuseMacField, + "keypurpose": EfuseKeyPurposeField, + "t_sensor": EfuseTempSensor, + "adc_tp": EfuseAdcPointCalibration, + "wafer": EfuseWafer, + }.get(efuse.class_type, EfuseField)(parent, efuse) + + +class EfuseWafer(EfuseField): + def get(self, from_read=True): + hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 + lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 + return (hi_bits << 3) + lo_bits + + def save(self, new_value): + raise esptool.FatalError("Burning %s is not supported" % self.name) + + +class EfuseTempSensor(EfuseField): + def get(self, from_read=True): + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * 0.1 + + +class EfuseAdcPointCalibration(EfuseField): + def get(self, from_read=True): + STEP_SIZE = 4 + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * STEP_SIZE + + +class EfuseMacField(EfuseField): + def check_format(self, new_value_str): + if new_value_str is None: + raise esptool.FatalError( + "Required MAC Address in AA:CD:EF:01:02:03 format!" + ) + num_bytes = 8 if self.name == "MAC_EUI64" else 6 + if new_value_str.count(":") != num_bytes - 1: + raise esptool.FatalError( + f"MAC Address needs to be a {num_bytes}-byte hexadecimal format " + "separated by colons (:)!" + ) + hexad = new_value_str.replace(":", "").split(" ", 1)[0] + hexad = hexad.split(" ", 1)[0] if self.is_field_calculated() else hexad + if len(hexad) != num_bytes * 2: + raise esptool.FatalError( + f"MAC Address needs to be a {num_bytes}-byte hexadecimal number " + f"({num_bytes * 2} hexadecimal characters)!" + ) + # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', + bindata = binascii.unhexlify(hexad) + + if not self.is_field_calculated(): + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") + return bindata + + def check(self): + errs, fail = self.parent.get_block_errors(self.block) + if errs != 0 or fail: + output = "Block%d has ERRORS:%d FAIL:%d" % (self.block, errs, fail) + else: + output = "OK" + return "(" + output + ")" + + def get(self, from_read=True): + if self.name == "CUSTOM_MAC": + mac = self.get_raw(from_read)[::-1] + elif self.name == "MAC": + mac = self.get_raw(from_read) + elif self.name == "MAC_EUI64": + mac = self.parent["MAC"].get_bitstring(from_read).copy() + mac_ext = self.parent["MAC_EXT"].get_bitstring(from_read) + mac.insert(mac_ext, 24) + mac = mac.bytes + else: + mac = self.get_raw(from_read) + return "%s %s" % (util.hexify(mac, ":"), self.check()) + + def save(self, new_value): + def print_field(e, new_value): + print( + " - '{}' ({}) {} -> {}".format( + e.name, e.description, e.get_bitstring(), new_value + ) + ) + + if self.name == "CUSTOM_MAC": + bitarray_mac = self.convert_to_bitstring(new_value) + print_field(self, bitarray_mac) + super(EfuseMacField, self).save(new_value) + else: + # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, + # as it's written in the factory. + raise esptool.FatalError(f"Burning {self.name} is not supported") + + +# fmt: off +class EfuseKeyPurposeField(EfuseField): + KEY_PURPOSES = [ + ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) + ("RESERVED", 1, None, None, "no_need_rd_protect"), # Reserved + ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) + ("HMAC_DOWN_ALL", 5, None, None, "need_rd_protect"), # HMAC Downstream mode + ("HMAC_DOWN_JTAG", 6, None, None, "need_rd_protect"), # JTAG soft enable key (uses HMAC Downstream mode) + ("HMAC_DOWN_DIGITAL_SIGNATURE", 7, None, None, "need_rd_protect"), # Digital Signature peripheral key (uses HMAC Downstream mode) + ("HMAC_UP", 8, None, None, "need_rd_protect"), # HMAC Upstream mode + ("SECURE_BOOT_DIGEST0", 9, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST0 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST1", 10, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST1 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST2", 11, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST2 (Secure Boot key digest) + ] +# fmt: on + KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] + DIGEST_KEY_PURPOSES = [name[0] for name in KEY_PURPOSES if name[2] == "DIGEST"] + + def check_format(self, new_value_str): + # str convert to int: "XTS_AES_128_KEY" - > str(4) + # if int: 4 -> str(4) + raw_val = new_value_str + for purpose_name in self.KEY_PURPOSES: + if purpose_name[0] == new_value_str: + raw_val = str(purpose_name[1]) + break + if raw_val.isdigit(): + if int(raw_val) not in [p[1] for p in self.KEY_PURPOSES if p[1] > 0]: + raise esptool.FatalError("'%s' can not be set (value out of range)" % raw_val) + else: + raise esptool.FatalError("'%s' unknown name" % raw_val) + return raw_val + + def need_reverse(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[3] == "Reverse" + + def need_rd_protect(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[4] == "need_rd_protect" + + def get(self, from_read=True): + for p in self.KEY_PURPOSES: + if p[1] == self.get_raw(from_read): + return p[0] + return "FORBIDDEN_STATE" + + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + + def save(self, new_value): + raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") + return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32c5beta3/mem_definition.py b/espefuse/efuse/esp32c5beta3/mem_definition.py new file mode 100644 index 000000000..f1b99495b --- /dev/null +++ b/espefuse/efuse/esp32c5beta3/mem_definition.py @@ -0,0 +1,169 @@ +# This file describes eFuses fields and registers for ESP32-C5 beta3 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os + +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) + + +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 + + # EFUSE registers & command/conf values + DR_REG_EFUSE_BASE = 0x600B0800 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C + EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 + EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 + EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 + EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C + EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 + EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC + EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 + EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 + EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 + + BLOCK_ERRORS = [ + # error_reg, err_num_mask, err_num_offs, fail_bit + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 + ] + + # EFUSE_WR_TIM_CONF2_REG + EFUSE_PWR_OFF_NUM_S = 0 + EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + + +class EfuseDefineBlocks(EfuseBlocksBase): + __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE + __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG + # List of efuse blocks + # fmt: off + BLOCKS = [ + # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose + ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), + ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), + ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), + ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), + ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), + ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), + ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), + ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), + ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), + ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), + ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), + ] + # fmt: on + + def get_burn_block_data_names(self): + list_of_names = [] + for block in self.BLOCKS: + blk = self.get(block) + if blk.name: + list_of_names.append(blk.name) + if blk.alias: + for alias in blk.alias: + list_of_names.append(alias) + return list_of_names + + +class EfuseDefineFields(EfuseFieldsBase): + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + f = Field() + f.name = "MAC_EUI64" + f.block = 1 + f.bit_len = 64 + f.type = f"bytes:{f.bit_len // 8}" + f.category = "MAC" + f.class_type = "mac" + f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32c5beta3/operations.py b/espefuse/efuse/esp32c5beta3/operations.py new file mode 100644 index 000000000..ed97563a7 --- /dev/null +++ b/espefuse/efuse/esp32c5beta3/operations.py @@ -0,0 +1,413 @@ +# This file includes the operations with eFuses for ESP32-C5 beta3 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import argparse +import os # noqa: F401. It is used in IDF scripts +import traceback + +import espsecure + +import esptool + +from . import fields +from .. import util +from ..base_operations import ( + add_common_commands, + add_force_write_always, + add_show_sensitive_info_option, + burn_bit, + burn_block_data, + burn_efuse, + check_error, + dump, + read_protect_efuse, + summary, + write_protect_efuse, +) + + +def protect_options(p): + p.add_argument( + "--no-write-protect", + help="Disable write-protecting of the key. The key remains writable. " + "(The keys use the RS coding scheme that does not support " + "post-write data changes. Forced write can damage RS encoding bits.) " + "The write-protecting of keypurposes does not depend on the option, " + "it will be set anyway.", + action="store_true", + ) + p.add_argument( + "--no-read-protect", + help="Disable read-protecting of the key. The key remains readable software." + "The key with keypurpose[USER, RESERVED and *_DIGEST] " + "will remain readable anyway. For the rest keypurposes the read-protection " + "will be defined the option (Read-protect by default).", + action="store_true", + ) + + +def add_commands(subparsers, efuses): + add_common_commands(subparsers, efuses) + burn_key = subparsers.add_parser( + "burn_key", help="Burn the key block with the specified name" + ) + protect_options(burn_key) + add_force_write_always(burn_key) + add_show_sensitive_info_option(burn_key) + burn_key.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data", + action="append", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + + burn_key_digest = subparsers.add_parser( + "burn_key_digest", + help="Parse a RSA public key and burn the digest to key efuse block", + ) + protect_options(burn_key_digest) + add_force_write_always(burn_key_digest) + add_show_sensitive_info_option(burn_key_digest) + burn_key_digest.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + action="append", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key_digest.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + + p = subparsers.add_parser( + "set_flash_voltage", + help="Permanently set the internal flash voltage regulator " + "to either 1.8V, 3.3V or OFF. " + "This means GPIO45 can be high or low at reset without " + "changing the flash voltage.", + ) + p.add_argument("voltage", help="Voltage selection", choices=["1.8V", "3.3V", "OFF"]) + + p = subparsers.add_parser( + "burn_custom_mac", help="Burn a 48-bit Custom MAC Address to EFUSE BLOCK3." + ) + p.add_argument( + "mac", + help="Custom MAC Address to burn given in hexadecimal format with bytes " + "separated by colons (e.g. AA:CD:EF:01:02:03).", + type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), + ) + add_force_write_always(p) + + p = subparsers.add_parser("get_custom_mac", help="Prints the Custom MAC Address.") + + +def burn_custom_mac(esp, efuses, args): + efuses["CUSTOM_MAC"].save(args.mac) + if not efuses.burn_all(check_batch_mode=True): + return + get_custom_mac(esp, efuses, args) + print("Successful") + + +def get_custom_mac(esp, efuses, args): + print("Custom MAC Address: {}".format(efuses["CUSTOM_MAC"].get())) + + +def set_flash_voltage(esp, efuses, args): + raise esptool.FatalError("set_flash_voltage is not supported!") + + +def adc_info(esp, efuses, args): + print("") + # fmt: off + if efuses["BLK_VERSION_MINOR"].get() == 1: + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + + print("") + print("ADC1 Calibration data stored in efuse BLOCK2:") + print(f"OCODE: {efuses['OCODE'].get()}") + print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") + print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") + print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") + print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") + print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") + print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") + print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") + print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") + print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") + print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") + print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") + print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") + print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") + print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") + print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") + else: + print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) + # fmt: on + + +def burn_key(esp, efuses, args, digest=None): + if digest is None: + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + else: + datafile_list = digest[0 : len([name for name in digest if name is not None]) :] + efuses.force_write_always = args.force_write_always + block_name_list = args.block[ + 0 : len([name for name in args.block if name is not None]) : + ] + keypurpose_list = args.keypurpose[ + 0 : len([name for name in args.keypurpose if name is not None]) : + ] + + util.check_duplicate_name_in_list(block_name_list) + if len(block_name_list) != len(datafile_list) or len(block_name_list) != len( + keypurpose_list + ): + raise esptool.FatalError( + "The number of blocks (%d), datafile (%d) and keypurpose (%d) " + "should be the same." + % (len(block_name_list), len(datafile_list), len(keypurpose_list)) + ) + + print("Burn keys to blocks:") + for block_name, datafile, keypurpose in zip( + block_name_list, datafile_list, keypurpose_list + ): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + + block_num = efuses.get_index_block_by_name(block_name) + block = efuses.blocks[block_num] + + if digest is None: + data = datafile.read() + else: + data = datafile + + print(" - %s" % (efuse.name), end=" ") + revers_msg = None + if efuses[block.key_purpose_name].need_reverse(keypurpose): + revers_msg = "\tReversing byte order for AES-XTS hardware peripheral" + data = data[::-1] + print( + "-> [{}]".format( + util.hexify(data, " ") + if args.show_sensitive_info + else " ".join(["??"] * len(data)) + ) + ) + if revers_msg: + print(revers_msg) + if len(data) != num_bytes: + raise esptool.FatalError( + "Incorrect key file size %d. Key file must be %d bytes (%d bits) " + "of raw binary key data." % (len(data), num_bytes, num_bytes * 8) + ) + + if efuses[block.key_purpose_name].need_rd_protect(keypurpose): + read_protect = False if args.no_read_protect else True + else: + read_protect = False + write_protect = not args.no_write_protect + + # using efuse instead of a block gives the advantage of checking it as the whole field. + efuse.save(data) + + disable_wr_protect_key_purpose = False + if efuses[block.key_purpose_name].get() != keypurpose: + if efuses[block.key_purpose_name].is_writeable(): + print( + "\t'%s': '%s' -> '%s'." + % ( + block.key_purpose_name, + efuses[block.key_purpose_name].get(), + keypurpose, + ) + ) + efuses[block.key_purpose_name].save(keypurpose) + disable_wr_protect_key_purpose = True + else: + raise esptool.FatalError( + "It is not possible to change '%s' to '%s' " + "because write protection bit is set." + % (block.key_purpose_name, keypurpose) + ) + else: + print("\t'%s' is already '%s'." % (block.key_purpose_name, keypurpose)) + if efuses[block.key_purpose_name].is_writeable(): + disable_wr_protect_key_purpose = True + + if disable_wr_protect_key_purpose: + print("\tDisabling write to '%s'." % block.key_purpose_name) + efuses[block.key_purpose_name].disable_write() + + if read_protect: + print("\tDisabling read to key block") + efuse.disable_read() + + if write_protect: + print("\tDisabling write to key block") + efuse.disable_write() + print("") + + if not write_protect: + print("Keys will remain writeable (due to --no-write-protect)") + if args.no_read_protect: + print("Keys will remain readable (due to --no-read-protect)") + + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") + + +def burn_key_digest(esp, efuses, args): + digest_list = [] + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + block_list = args.block[ + 0 : len([block for block in args.block if block is not None]) : + ] + for block_name, datafile in zip(block_list, datafile_list): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + digest = espsecure._digest_sbv2_public_key(datafile) + if len(digest) != num_bytes: + raise esptool.FatalError( + "Incorrect digest size %d. Digest must be %d bytes (%d bits) " + "of raw binary key data." % (len(digest), num_bytes, num_bytes * 8) + ) + digest_list.append(digest) + burn_key(esp, efuses, args, digest=digest_list) + + +def espefuse(esp, efuses, args, command): + parser = argparse.ArgumentParser() + subparsers = parser.add_subparsers(dest="operation") + add_commands(subparsers, efuses) + try: + cmd_line_args = parser.parse_args(command.split()) + except SystemExit: + traceback.print_stack() + raise esptool.FatalError('"{}" - incorrect command'.format(command)) + if cmd_line_args.operation == "execute_scripts": + configfiles = cmd_line_args.configfiles + index = cmd_line_args.index + # copy arguments from args to cmd_line_args + vars(cmd_line_args).update(vars(args)) + if cmd_line_args.operation == "execute_scripts": + cmd_line_args.configfiles = configfiles + cmd_line_args.index = index + if cmd_line_args.operation is None: + parser.print_help() + parser.exit(1) + operation_func = globals()[cmd_line_args.operation] + # each 'operation' is a module-level function of the same name + operation_func(esp, efuses, cmd_line_args) + + +def execute_scripts(esp, efuses, args): + efuses.batch_mode_cnt += 1 + del args.operation + scripts = args.scripts + del args.scripts + + for file in scripts: + with open(file.name, "r") as file: + exec(compile(file.read(), file.name, "exec")) + + if args.debug: + for block in efuses.blocks: + data = block.get_bitstring(from_read=False) + block.print_block(data, "regs_for_burn", args.debug) + + efuses.batch_mode_cnt -= 1 + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") diff --git a/espsecure/__init__.py b/espsecure/__init__.py index 3e5ef2039..b4b50d632 100755 --- a/espsecure/__init__.py +++ b/espsecure/__init__.py @@ -1712,7 +1712,7 @@ def main(custom_commandline=None): "--aes_xts", "-x", help="Decrypt data using AES-XTS as used on " - "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6 and ESP32-P4", + "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5 and ESP32-P4", action="store_true", ) p.add_argument( @@ -1752,7 +1752,7 @@ def main(custom_commandline=None): "--aes_xts", "-x", help="Encrypt data using AES-XTS as used on " - "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6 and ESP32-P4", + "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5 and ESP32-P4", action="store_true", ) p.add_argument( diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 55ca6359e..4e917316d 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -19,6 +19,7 @@ from .targets import ( ESP32C2ROM, ESP32C3ROM, + ESP32C5BETA3ROM, ESP32C6BETAROM, ESP32C6ROM, ESP32H2BETA1ROM, @@ -82,6 +83,7 @@ def select_image_class(f, chip): "esp32h2beta2": ESP32H2BETA2FirmwareImage, "esp32c2": ESP32C2FirmwareImage, "esp32c6": ESP32C6FirmwareImage, + "esp32c5beta3": ESP32C5BETA3FirmwareImage, "esp32h2": ESP32H2FirmwareImage, "esp32p4": ESP32P4FirmwareImage, }[chip](f) @@ -1114,6 +1116,15 @@ def set_mmu_page_size(self, size): ESP32C6ROM.BOOTLOADER_IMAGE = ESP32C6FirmwareImage +class ESP32C5BETA3FirmwareImage(ESP32C6FirmwareImage): + """ESP32C5BETA3 Firmware Image almost exactly the same as ESP32C6FirmwareImage""" + + ROM_LOADER = ESP32C5BETA3ROM + + +ESP32C5BETA3ROM.BOOTLOADER_IMAGE = ESP32C5BETA3FirmwareImage + + class ESP32P4FirmwareImage(ESP32FirmwareImage): """ESP32P4 Firmware Image almost exactly the same as ESP32FirmwareImage""" diff --git a/esptool/loader.py b/esptool/loader.py index bc08a919f..802531f2d 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -1454,7 +1454,12 @@ def get_crystal_freq(self): # See the self.XTAL_CLK_DIVIDER parameter for this factor. uart_div = self.read_reg(self.UART_CLKDIV_REG) & self.UART_CLKDIV_MASK est_xtal = (self._port.baudrate * uart_div) / 1e6 / self.XTAL_CLK_DIVIDER - norm_xtal = 40 if est_xtal > 33 else 26 + if est_xtal > 45: + norm_xtal = 48 + elif est_xtal > 33: + norm_xtal = 40 + else: + norm_xtal = 26 if abs(norm_xtal - est_xtal) > 1: print( "WARNING: Detected crystal freq %.2fMHz is quite different to " diff --git a/esptool/targets/__init__.py b/esptool/targets/__init__.py index dd1ba485d..16e204ed4 100644 --- a/esptool/targets/__init__.py +++ b/esptool/targets/__init__.py @@ -1,6 +1,7 @@ from .esp32 import ESP32ROM from .esp32c2 import ESP32C2ROM from .esp32c3 import ESP32C3ROM +from .esp32c5beta3 import ESP32C5BETA3ROM from .esp32c6 import ESP32C6ROM from .esp32c6beta import ESP32C6BETAROM from .esp32h2 import ESP32H2ROM @@ -25,6 +26,7 @@ "esp32h2beta2": ESP32H2BETA2ROM, "esp32c2": ESP32C2ROM, "esp32c6": ESP32C6ROM, + "esp32c5beta3": ESP32C5BETA3ROM, "esp32h2": ESP32H2ROM, "esp32p4": ESP32P4ROM, } diff --git a/esptool/targets/esp32c5beta3.py b/esptool/targets/esp32c5beta3.py new file mode 100644 index 000000000..0eeedc710 --- /dev/null +++ b/esptool/targets/esp32c5beta3.py @@ -0,0 +1,99 @@ +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import struct +import time + +from .esp32c6 import ESP32C6ROM +from ..loader import ESPLoader + + +class ESP32C5BETA3ROM(ESP32C6ROM): + CHIP_NAME = "ESP32-C5(beta3)" + IMAGE_CHIP_ID = 17 + + IROM_MAP_START = 0x41000000 + IROM_MAP_END = 0x41800000 + DROM_MAP_START = 0x41000000 + DROM_MAP_END = 0x41800000 + + # Magic value for ESP32C5(beta3) + CHIP_DETECT_MAGIC_VALUE = [0xE10D8082] + + FLASH_FREQUENCY = { + "80m": 0xF, + "40m": 0x0, + "20m": 0x2, + } + + MEMORY_MAP = [ + [0x00000000, 0x00010000, "PADDING"], + [0x41800000, 0x42000000, "DROM"], + [0x40800000, 0x40880000, "DRAM"], + [0x40800000, 0x40880000, "BYTE_ACCESSIBLE"], + [0x4004A000, 0x40050000, "DROM_MASK"], + [0x40000000, 0x4004A000, "IROM_MASK"], + [0x41000000, 0x41800000, "IROM"], + [0x40800000, 0x40880000, "IRAM"], + [0x50000000, 0x50004000, "RTC_IRAM"], + [0x50000000, 0x50004000, "RTC_DRAM"], + [0x600FE000, 0x60100000, "MEM_INTERNAL2"], + ] + + def get_chip_description(self): + chip_name = { + 0: "ESP32-C5 beta3 (QFN40)", + }.get(self.get_pkg_version(), "unknown ESP32-C5 beta3") + major_rev = self.get_major_chip_version() + minor_rev = self.get_minor_chip_version() + return f"{chip_name} (revision v{major_rev}.{minor_rev})" + + def get_crystal_freq(self): + # The crystal detection algorithm of ESP32/ESP8266 + # works for ESP32-C5 beta3 as well. + return ESPLoader.get_crystal_freq(self) + + def change_baud(self, baud): + rom_with_48M_XTAL = not self.IS_STUB and self.get_crystal_freq() == 48 + if rom_with_48M_XTAL: + # The code is copied over from ESPLoader.change_baud(). + # Probably this is just a temporary solution until the next chip revision. + + # The ROM code thinks it uses a 40 MHz XTAL. Recompute the baud rate + # in order to trick the ROM code to set the correct baud rate for + # a 48 MHz XTAL. + false_rom_baud = baud * 40 // 48 + + print(f"Changing baud rate to {baud}") + self.command( + self.ESP_CHANGE_BAUDRATE, struct.pack(" $@" $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C6=1 -Tstub_32c6.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) +$(STUB_ELF_32C5_BETA_3): $(SRCS) $(BUILD_DIR) ld/stub_32c5_beta_3.ld + @echo " CC(32C5BETA3) $^ -> $@" + $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C5BETA3=1 -Tstub_32c5_beta_3.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + $(STUB_ELF_32H2): $(SRCS) $(BUILD_DIR) ld/stub_32h2.ld @echo " CC(32H2) $^ -> $@" $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32H2=1 -Tstub_32h2.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) diff --git a/flasher_stub/include/rom_functions.h b/flasher_stub/include/rom_functions.h index 6259dae88..ca0237220 100644 --- a/flasher_stub/include/rom_functions.h +++ b/flasher_stub/include/rom_functions.h @@ -18,11 +18,11 @@ int uart_rx_one_char(uint8_t *ch); uint8_t uart_rx_one_char_block(); int uart_tx_one_char(char ch); -#if ESP32C6 || ESP32H2 +#if ESP32C6 || ESP32H2 || ESP32C5BETA3 /* uart_tx_one_char doesn't send data to USB device serial, needs to be replaced */ int uart_tx_one_char2(char ch); #define uart_tx_one_char(ch) uart_tx_one_char2(ch) -#endif // ESP32C6 || ESP32H2 +#endif // ESP32C6 || ESP32H2 || ESP32C5BETA3 void uart_div_modify(uint32_t uart_no, uint32_t baud_div); diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index f095adbb5..d77430765 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -46,6 +46,11 @@ #define WITH_USB_OTG 1 #endif // ESP32S3 +#ifdef ESP32C5BETA3 +#define WITH_USB_JTAG_SERIAL 1 +#define IS_RISCV 1 +#endif // ESP32C5BETA3 + #ifdef ESP32C6 #define WITH_USB_JTAG_SERIAL 1 #define IS_RISCV 1 @@ -167,7 +172,7 @@ #define DR_REG_IO_MUX_BASE 0x60009000 #endif -#ifdef ESP32C6 +#if ESP32C6 || ESP32C5BETA3 #define UART_BASE_REG 0x60000000 /* UART0 */ #define SPI_BASE_REG 0x60003000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x60002000 /* SPI peripheral 0, inner state machine */ @@ -325,14 +330,14 @@ #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ #endif // ESP32S3 -#ifdef ESP32C6 +#if ESP32C6 || ESP32C5BETA3 #define UART_USB_JTAG_SERIAL 3 #define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xC0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */ #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ -#endif // ESP32C6 +#endif // ESP32C6 || ESP32C5BETA3 #ifdef ESP32H2 #define UART_USB_JTAG_SERIAL 3 @@ -384,7 +389,7 @@ #define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 31) #endif -#ifdef ESP32C6 +#if ESP32C6 || ESP32C5BETA3 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG #define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_SWD_CONFIG_REG @@ -437,6 +442,14 @@ #define SYSTEM_SOC_CLK_MAX 1 #endif // ESP32S2 +#ifdef ESP32C5BETA3 +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) +#define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) +#define PCR_SOC_CLK_SEL_V 0x3 +#define PCR_SOC_CLK_SEL_S 16 +#define PCR_SOC_CLK_MAX 3 // CPU_CLK frequency is 240 MHz (source is PLL_F240_CLK) +#endif // ESP32C5BETA3 + #ifdef ESP32C6 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) #define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) @@ -474,7 +487,7 @@ #define ROM_SPIFLASH_LEGACY 0x3ffae270 #endif // ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 -#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 +#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5BETA3 #define ROM_SPIFLASH_LEGACY 0x3fcdfff4 #endif // ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 @@ -540,7 +553,7 @@ #define FUNC_GPIO 1 #endif // ESP32C2 -#if ESP32C6 || ESP32C6BETA +#if ESP32C6 || ESP32C6BETA || ESP32C5BETA3 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x78) #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x68) #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x7c) diff --git a/flasher_stub/ld/rom_32c5_beta_3.ld b/flasher_stub/ld/rom_32c5_beta_3.ld new file mode 100755 index 000000000..d9c3d3e5e --- /dev/null +++ b/flasher_stub/ld/rom_32c5_beta_3.ld @@ -0,0 +1,429 @@ +/* ROM function interface esp32c5.rom.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +PROVIDE ( SPIWrite = esp_rom_spiflash_write); +PROVIDE ( SPI_read_status_high = esp_rom_spiflash_read_statushigh); +PROVIDE ( SPI_write_status = esp_rom_spiflash_write_status); +PROVIDE ( SPIRead = esp_rom_spiflash_read); +PROVIDE ( SPIParamCfg = esp_rom_spiflash_config_param); +PROVIDE ( SPIEraseChip = esp_rom_spiflash_erase_chip); +PROVIDE ( SPIEraseSector = esp_rom_spiflash_erase_sector); +PROVIDE ( SPIEraseBlock = esp_rom_spiflash_erase_block); +PROVIDE ( SPI_Write_Encrypt_Enable = esp_rom_spiflash_write_encrypted_enable); +PROVIDE ( SPI_Write_Encrypt_Disable = esp_rom_spiflash_write_encrypted_disable); +PROVIDE ( SPI_Encrypt_Write = esp_rom_spiflash_write_encrypted); + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +rtc_get_wakeup_cause = 0x4000001c; +pmu_enable_unhold_pads = 0x40000020; +ets_printf = 0x40000024; +ets_install_putc1 = 0x40000028; +ets_install_putc2 = 0x4000002c; +ets_install_uart_printf = 0x40000030; +ets_install_usb_printf = 0x40000034; +ets_get_printf_channel = 0x40000038; +ets_delay_us = 0x4000003c; +ets_get_cpu_frequency = 0x40000040; +ets_update_cpu_frequency = 0x40000044; +ets_install_lock = 0x40000048; +UartRxString = 0x4000004c; +UartGetCmdLn = 0x40000050; +uart_tx_one_char = 0x40000054; +uart_tx_one_char2 = 0x40000058; +uart_tx_one_char3 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +uart_buff_switch = 0x40000088; +roundup2 = 0x4000008c; +multofup = 0x40000090; +software_reset = 0x40000094; +software_reset_cpu = 0x40000098; +ets_clk_assist_debug_clock_enable = 0x4000009c; +clear_super_wdt_reset_flag = 0x400000a0; +disable_default_watchdog = 0x400000a4; +esp_rom_set_rtc_wake_addr = 0x400000a8; +esp_rom_get_rtc_wake_addr = 0x400000ac; +send_packet = 0x400000b0; +recv_packet = 0x400000b4; +GetUartDevice = 0x400000b8; +UartDwnLdProc = 0x400000bc; +GetSecurityInfoProc = 0x400000c0; +Uart_Init = 0x400000c4; +ets_set_user_start = 0x400000c8; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4004fffc; +ets_ops_table_ptr = 0x4087fff8; +g_saved_pc = 0x4087fffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000cc; +mz_free = 0x400000d0; +tdefl_compress = 0x400000d4; +tdefl_compress_buffer = 0x400000d8; +tdefl_compress_mem_to_heap = 0x400000dc; +tdefl_compress_mem_to_mem = 0x400000e0; +tdefl_compress_mem_to_output = 0x400000e4; +tdefl_get_adler32 = 0x400000e8; +tdefl_get_prev_return_status = 0x400000ec; +tdefl_init = 0x400000f0; +tdefl_write_image_to_png_file_in_memory = 0x400000f4; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f8; +tinfl_decompress = 0x400000fc; +tinfl_decompress_mem_to_callback = 0x40000100; +tinfl_decompress_mem_to_heap = 0x40000104; +tinfl_decompress_mem_to_mem = 0x40000108; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x4000010c; +esp_rom_spiflash_write_encrypted = 0x40000110; +esp_rom_spiflash_write_encrypted_dest = 0x40000114; +esp_rom_spiflash_write_encrypted_enable = 0x40000118; +esp_rom_spiflash_write_encrypted_disable = 0x4000011c; +esp_rom_spiflash_erase_chip = 0x40000120; +_esp_rom_spiflash_erase_sector = 0x40000124; +_esp_rom_spiflash_erase_block = 0x40000128; +_esp_rom_spiflash_write = 0x4000012c; +_esp_rom_spiflash_read = 0x40000130; +_esp_rom_spiflash_unlock = 0x40000134; +_SPIEraseArea = 0x40000138; +_SPI_write_enable = 0x4000013c; +esp_rom_spiflash_erase_sector = 0x40000140; +esp_rom_spiflash_erase_block = 0x40000144; +esp_rom_spiflash_write = 0x40000148; +esp_rom_spiflash_read = 0x4000014c; +esp_rom_spiflash_unlock = 0x40000150; +SPIEraseArea = 0x40000154; +SPI_write_enable = 0x40000158; +esp_rom_spiflash_config_param = 0x4000015c; +esp_rom_spiflash_read_user_cmd = 0x40000160; +esp_rom_spiflash_select_qio_pins = 0x40000164; +esp_rom_spi_flash_auto_sus_res = 0x40000168; +esp_rom_spi_flash_send_resume = 0x4000016c; +esp_rom_spi_flash_update_id = 0x40000170; +esp_rom_spiflash_config_clk = 0x40000174; +esp_rom_spiflash_config_readmode = 0x40000178; +esp_rom_spiflash_read_status = 0x4000017c; +esp_rom_spiflash_read_statushigh = 0x40000180; +esp_rom_spiflash_write_status = 0x40000184; +esp_rom_spiflash_write_disable = 0x40000188; +spi_cache_mode_switch = 0x4000018c; +spi_common_set_dummy_output = 0x40000190; +spi_common_set_flash_cs_timing = 0x40000194; +esp_rom_spi_set_address_bit_len = 0x40000198; +SPILock = 0x4000019c; +SPIMasterReadModeCnfig = 0x400001a0; +SPI_Common_Command = 0x400001a4; +SPI_WakeUp = 0x400001a8; +SPI_block_erase = 0x400001ac; +SPI_chip_erase = 0x400001b0; +SPI_init = 0x400001b4; +SPI_page_program = 0x400001b8; +SPI_read_data = 0x400001bc; +SPI_sector_erase = 0x400001c0; +SelectSpiFunction = 0x400001c4; +SetSpiDrvs = 0x400001c8; +Wait_SPI_Idle = 0x400001cc; +spi_dummy_len_fix = 0x400001d0; +Disable_QMode = 0x400001d4; +Enable_QMode = 0x400001d8; +spi_flash_attach = 0x400001dc; +spi_flash_get_chip_size = 0x400001e0; +spi_flash_guard_set = 0x400001e4; +spi_flash_guard_get = 0x400001e8; +spi_flash_read_encrypted = 0x400001ec; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4087fff0; +rom_spiflash_legacy_data = 0x4087ffec; +g_flash_guard_ops = 0x4087fff4; + + +/*************************************** + Group hal_wdt + ***************************************/ + +/* Functions */ +wdt_hal_init = 0x40000390; +wdt_hal_deinit = 0x40000394; +wdt_hal_config_stage = 0x40000398; +wdt_hal_write_protect_disable = 0x4000039c; +wdt_hal_write_protect_enable = 0x400003a0; +wdt_hal_enable = 0x400003a4; +wdt_hal_disable = 0x400003a8; +wdt_hal_handle_intr = 0x400003ac; +wdt_hal_feed = 0x400003b0; +wdt_hal_set_flashboot_en = 0x400003b4; +wdt_hal_is_enabled = 0x400003b8; + + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +systimer_hal_init = 0x400003bc; +systimer_hal_deinit = 0x400003c0; +systimer_hal_set_tick_rate_ops = 0x400003c4; +systimer_hal_get_counter_value = 0x400003c8; +systimer_hal_get_time = 0x400003cc; +systimer_hal_set_alarm_target = 0x400003d0; +systimer_hal_set_alarm_period = 0x400003d4; +systimer_hal_get_alarm_value = 0x400003d8; +systimer_hal_enable_alarm_int = 0x400003dc; +systimer_hal_on_apb_freq_update = 0x400003e0; +systimer_hal_counter_value_advance = 0x400003e4; +systimer_hal_enable_counter = 0x400003e8; +systimer_hal_select_alarm_mode = 0x400003ec; +systimer_hal_connect_alarm_counter = 0x400003f0; +systimer_hal_counter_can_stall_by_cpu = 0x400003f4; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_ICache_Line_Size = 0x40000624; +Cache_Get_Mode = 0x40000628; +Cache_Address_Through_Cache = 0x4000062c; +ROM_Boot_Cache_Init = 0x40000630; +MMU_Set_Page_Mode = 0x40000634; +MMU_Get_Page_Mode = 0x40000638; +Cache_Invalidate_ICache_Items = 0x4000063c; +Cache_Op_Addr = 0x40000640; +Cache_Invalidate_Addr = 0x40000644; +Cache_Invalidate_ICache_All = 0x40000648; +Cache_Mask_All = 0x4000064c; +Cache_UnMask_Dram0 = 0x40000650; +Cache_Suspend_ICache_Autoload = 0x40000654; +Cache_Resume_ICache_Autoload = 0x40000658; +Cache_Start_ICache_Preload = 0x4000065c; +Cache_ICache_Preload_Done = 0x40000660; +Cache_End_ICache_Preload = 0x40000664; +Cache_Config_ICache_Autoload = 0x40000668; +Cache_Enable_ICache_Autoload = 0x4000066c; +Cache_Disable_ICache_Autoload = 0x40000670; +Cache_Enable_ICache_PreLock = 0x40000674; +Cache_Disable_ICache_PreLock = 0x40000678; +Cache_Lock_ICache_Items = 0x4000067c; +Cache_Unlock_ICache_Items = 0x40000680; +Cache_Lock_Addr = 0x40000684; +Cache_Unlock_Addr = 0x40000688; +Cache_Disable_ICache = 0x4000068c; +Cache_Enable_ICache = 0x40000690; +Cache_Suspend_ICache = 0x40000694; +Cache_Resume_ICache = 0x40000698; +Cache_Freeze_ICache_Enable = 0x4000069c; +Cache_Freeze_ICache_Disable = 0x400006a0; +Cache_Set_IDROM_MMU_Size = 0x400006a4; +Cache_Get_IROM_MMU_End = 0x400006a8; +Cache_Get_DROM_MMU_End = 0x400006ac; +Cache_MMU_Init = 0x400006b0; +Cache_MSPI_MMU_Set = 0x400006b4; +Cache_MSPI_MMU_Set_Secure = 0x400006b8; +Cache_Travel_Tag_Memory = 0x400006bc; +Cache_Get_Virtual_Addr = 0x400006c0; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4087ffcc; +rom_cache_internal_table_ptr = 0x4087ffc8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x400006c4; +ets_clk_get_cpu_freq = 0x400006c8; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_set_output_level = 0x400006cc; +gpio_get_input_level = 0x400006d0; +gpio_matrix_in = 0x400006d4; +gpio_matrix_out = 0x400006d8; +gpio_bypass_matrix_in = 0x400006dc; +gpio_output_disable = 0x400006e0; +gpio_output_enable = 0x400006e4; +gpio_pad_input_disable = 0x400006e8; +gpio_pad_input_enable = 0x400006ec; +gpio_pad_pulldown = 0x400006f0; +gpio_pad_pullup = 0x400006f4; +gpio_pad_select_gpio = 0x400006f8; +gpio_pad_set_drv = 0x400006fc; +gpio_pad_unhold = 0x40000700; +gpio_pad_hold = 0x40000704; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x40000708; +esprv_intc_int_set_threshold = 0x4000070c; +esprv_intc_int_enable = 0x40000710; +esprv_intc_int_disable = 0x40000714; +esprv_intc_int_set_type = 0x40000718; +PROVIDE( intr_handler_set = 0x4000071c ); +intr_matrix_set = 0x40000720; +ets_intr_lock = 0x40000724; +ets_intr_unlock = 0x40000728; +ets_isr_attach = 0x4000072c; +ets_isr_mask = 0x40000730; +ets_isr_unmask = 0x40000734; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x40000738; +MD5Init = 0x4000073c; +MD5Update = 0x40000740; +MD5Final = 0x40000744; +crc32_le = 0x40000748; +crc16_le = 0x4000074c; +crc8_le = 0x40000750; +crc32_be = 0x40000754; +crc16_be = 0x40000758; +crc8_be = 0x4000075c; +esp_crc8 = 0x40000760; +ets_sha_enable = 0x40000764; +ets_sha_disable = 0x40000768; +ets_sha_get_state = 0x4000076c; +ets_sha_init = 0x40000770; +ets_sha_process = 0x40000774; +ets_sha_starts = 0x40000778; +ets_sha_update = 0x4000077c; +ets_sha_finish = 0x40000780; +ets_sha_clone = 0x40000784; +ets_hmac_enable = 0x40000788; +ets_hmac_disable = 0x4000078c; +ets_hmac_calculate_message = 0x40000790; +ets_hmac_calculate_downstream = 0x40000794; +ets_hmac_invalidate_downstream = 0x40000798; +ets_jtag_enable_temporarily = 0x4000079c; +ets_aes_enable = 0x400007a0; +ets_aes_disable = 0x400007a4; +ets_aes_setkey = 0x400007a8; +ets_aes_block = 0x400007ac; +ets_aes_setkey_dec = 0x400007b0; +ets_aes_setkey_enc = 0x400007b4; +ets_bigint_enable = 0x400007b8; +ets_bigint_disable = 0x400007bc; +ets_bigint_multiply = 0x400007c0; +ets_bigint_modmult = 0x400007c4; +ets_bigint_modexp = 0x400007c8; +ets_bigint_wait_finish = 0x400007cc; +ets_bigint_getz = 0x400007d0; +ets_ds_enable = 0x400007d4; +ets_ds_disable = 0x400007d8; +ets_ds_start_sign = 0x400007dc; +ets_ds_is_busy = 0x400007e0; +ets_ds_finish_sign = 0x400007e4; +ets_ds_encrypt_params = 0x400007e8; +ets_mgf1_sha256 = 0x400007ec; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4004fff8; +crc16_le_table_ptr = 0x4004fff4; +crc8_le_table_ptr = 0x4004fff0; +crc32_be_table_ptr = 0x4004ffec; +crc16_be_table_ptr = 0x4004ffe8; +crc8_be_table_ptr = 0x4004ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x400007f0; +ets_efuse_program = 0x400007f4; +ets_efuse_clear_program_registers = 0x400007f8; +ets_efuse_write_key = 0x400007fc; +ets_efuse_get_read_register_address = 0x40000800; +ets_efuse_get_key_purpose = 0x40000804; +ets_efuse_key_block_unused = 0x40000808; +ets_efuse_find_unused_key_block = 0x4000080c; +ets_efuse_rs_calculate = 0x40000810; +ets_efuse_count_unused_key_blocks = 0x40000814; +ets_efuse_secure_boot_enabled = 0x40000818; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000081c; +ets_efuse_cache_encryption_enabled = 0x40000820; +ets_efuse_download_modes_disabled = 0x40000824; +ets_efuse_find_purpose = 0x40000828; +ets_efuse_force_send_resume = 0x4000082c; +ets_efuse_get_flash_delay_us = 0x40000830; +ets_efuse_get_uart_print_control = 0x40000834; +ets_efuse_direct_boot_mode_disabled = 0x40000838; +ets_efuse_security_download_modes_enabled = 0x4000083c; +ets_efuse_jtag_disabled = 0x40000840; +ets_efuse_usb_print_is_disabled = 0x40000844; +ets_efuse_usb_download_mode_disabled = 0x40000848; +ets_efuse_usb_device_disabled = 0x4000084c; +ets_efuse_secure_boot_fast_wake_enabled = 0x40000850; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x40000854; +ets_rsa_pss_verify = 0x40000858; +ets_ecdsa_verify = 0x4000085c; +ets_secure_boot_verify_bootloader_with_keys = 0x40000860; +ets_secure_boot_verify_signature = 0x40000864; +ets_secure_boot_read_key_digests = 0x40000868; +ets_secure_boot_revoke_public_key_digest = 0x4000086c; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x40000a6c; +usb_serial_device_rx_one_char_block = 0x40000a70; +usb_serial_device_tx_flush = 0x40000a74; +usb_serial_device_tx_one_char = 0x40000a78; + diff --git a/flasher_stub/ld/stub_32c5_beta_3.ld b/flasher_stub/ld/stub_32c5_beta_3.ld new file mode 100644 index 000000000..e1133674e --- /dev/null +++ b/flasher_stub/ld/stub_32c5_beta_3.ld @@ -0,0 +1,26 @@ +MEMORY { + iram : org = 0x40800000, len = 0x4000 + dram : org = 0x40840000, len = 0x18000 +} + +ENTRY(stub_main) + +SECTIONS { + .text : ALIGN(4) { + *(.literal) + *(.text .text.*) + } > iram + + .bss : ALIGN(4) { + _bss_start = ABSOLUTE(.); + *(.bss) + _bss_end = ABSOLUTE(.); + } > dram + + .data : ALIGN(4) { + *(.data) + *(.rodata .rodata.*) + } > dram +} + +INCLUDE "rom_32c5_beta_3.ld" diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c index 6b5885039..967bff5ec 100644 --- a/flasher_stub/stub_flasher.c +++ b/flasher_stub/stub_flasher.c @@ -63,7 +63,7 @@ static bool can_use_max_cpu_freq() #endif } -#if ESP32C6 || ESP32H2 +#if ESP32C6 || ESP32H2 || ESP32C5BETA3 static uint32_t pcr_sysclk_conf_reg = 0; #else static uint32_t cpu_per_conf_reg = 0; @@ -75,7 +75,7 @@ static void set_max_cpu_freq() if (can_use_max_cpu_freq()) { /* Set CPU frequency to max. This also increases SPI speed. */ - #if ESP32C6 || ESP32H2 + #if ESP32C6 || ESP32H2 || ESP32C5BETA3 pcr_sysclk_conf_reg = READ_REG(PCR_SYSCLK_CONF_REG); WRITE_REG(PCR_SYSCLK_CONF_REG, (pcr_sysclk_conf_reg & ~PCR_SOC_CLK_SEL_M) | (PCR_SOC_CLK_MAX << PCR_SOC_CLK_SEL_S)); #else @@ -92,7 +92,7 @@ static void reset_cpu_freq() { /* Restore saved sysclk_conf and cpu_per_conf registers. Use only if set_max_cpu_freq() has been called. */ - #if ESP32C6 || ESP32H2 + #if ESP32C6 || ESP32H2 || ESP32C5BETA3 if (can_use_max_cpu_freq() && pcr_sysclk_conf_reg != 0) { WRITE_REG(PCR_SYSCLK_CONF_REG, (READ_REG(PCR_SYSCLK_CONF_REG) & ~PCR_SOC_CLK_SEL_M) | (pcr_sysclk_conf_reg & PCR_SOC_CLK_SEL_M)); From d15a58ab917065b82ad551ce4f9aae3f242e1132 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 2 Jan 2024 13:34:37 +0100 Subject: [PATCH 110/209] ci(dev_releasing): Let patch_dev_release.py accept any version specifier --- .../workflows/dev_release_esptool_pypi.yml | 3 +-- ci/patch_dev_release.py | 19 ++++++++----------- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/.github/workflows/dev_release_esptool_pypi.yml b/.github/workflows/dev_release_esptool_pypi.yml index a443a1323..61cd63038 100644 --- a/.github/workflows/dev_release_esptool_pypi.yml +++ b/.github/workflows/dev_release_esptool_pypi.yml @@ -31,8 +31,7 @@ jobs: TWINE_PASSWORD: ${{ secrets.PYPI_PASSWORD }} TWINE_NON_INTERACTIVE: true run: | - DEV_VERSION=$(echo "${{ github.ref_name }}" | grep -oE 'dev[0-9]+' | sed 's/dev//') - python ci/patch_dev_release.py --dev-no ${DEV_VERSION} esptool/__init__.py + python ci/patch_dev_release.py --version ${{ github.ref_name }} esptool/__init__.py git diff python -m pip download esptool==$(python setup.py -V) && echo "Version ${{ github.ref_name }} already published, skipping..." && exit 1 diff --git a/ci/patch_dev_release.py b/ci/patch_dev_release.py index a157c8f3f..9cd9feff7 100644 --- a/ci/patch_dev_release.py +++ b/ci/patch_dev_release.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later @@ -6,23 +6,20 @@ import re LINE_RE = re.compile(r"^__version__ = ['\"]([^'\"]*)['\"]") -NEW_LINE = '__version__ = "{}"' +NEW_LINE = '__version__ = "{}"\n' -def get_new_version(old_version, dev_number): - assert old_version.endswith("-dev") - return old_version.replace("-dev", ".dev{}".format(dev_number), 1) +def patch_file(path, new_version): + assert ".dev" in new_version + new_version = new_version.lstrip("v") - -def patch_file(path, dev_number): with open(path, "r") as fin: lines = fin.readlines() for i, line in enumerate(lines, start=0): m = LINE_RE.search(line) if m: - old_version = m.group(1) - lines[i] = NEW_LINE.format(get_new_version(old_version, dev_number)) + lines[i] = NEW_LINE.format(new_version) break with open(path, "w") as fout: @@ -33,10 +30,10 @@ def main(): parser = argparse.ArgumentParser() parser.add_argument("file", help="Path to script with __version__") parser.add_argument( - "--dev-no", type=int, help="Number N to patch the version to '.devN'" + "--version", help="Development version specifier to patch the version to" ) args = parser.parse_args() - patch_file(args.file, args.dev_no) + patch_file(args.file, args.version) if __name__ == "__main__": From 3e1bfa2eb454949b6af0298ca88cbe1c4f2f549f Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Mon, 18 Dec 2023 14:15:58 +0100 Subject: [PATCH 111/209] fix: ignore resetting on unsupported ports Closes https://github.com/espressif/esptool/issues/762 --- esptool/reset.py | 32 +++++++++++++++++++++++++------- esptool/util.py | 14 ++++++++++++++ test/test_esptool.py | 24 ++++++++++++++++++++++++ 3 files changed, 63 insertions(+), 7 deletions(-) diff --git a/esptool/reset.py b/esptool/reset.py index 39b9a15a4..6223b5d98 100644 --- a/esptool/reset.py +++ b/esptool/reset.py @@ -3,11 +3,12 @@ # # SPDX-License-Identifier: GPL-2.0-or-later +import errno import os import struct import time -from .util import FatalError +from .util import FatalError, PrintOnce # Used for resetting into bootloader on Unix-like systems if os.name != "nt": @@ -26,11 +27,28 @@ class ResetStrategy(object): + print_once = PrintOnce() + def __init__(self, port, reset_delay=DEFAULT_RESET_DELAY): self.port = port self.reset_delay = reset_delay - def __call__(): + def __call__(self): + try: + self.reset() + except OSError as e: + # ENOTTY for TIOCMSET; EINVAL for TIOCMGET + if e.errno in [errno.ENOTTY, errno.EINVAL]: + self.print_once( + "WARNING: Chip was NOT reset. Setting RTS/DTR lines is not " + f"supported for port '{self.port.name}'. Set --before and --after " + "arguments to 'no_reset' and switch to bootloader manually to " + "avoid this warning." + ) + else: + raise + + def reset(self): pass def _setDTR(self, state): @@ -63,7 +81,7 @@ class ClassicReset(ResetStrategy): Classic reset sequence, sets DTR and RTS lines sequentially. """ - def __call__(self): + def reset(self): self._setDTR(False) # IO0=HIGH self._setRTS(True) # EN=LOW, chip in reset time.sleep(0.1) @@ -79,7 +97,7 @@ class UnixTightReset(ResetStrategy): which allows setting DTR and RTS lines at the same time. """ - def __call__(self): + def reset(self): self._setDTRandRTS(False, False) self._setDTRandRTS(True, True) self._setDTRandRTS(False, True) # IO0=HIGH & EN=LOW, chip in reset @@ -96,7 +114,7 @@ class USBJTAGSerialReset(ResetStrategy): is connecting via its USB-JTAG-Serial peripheral. """ - def __call__(self): + def reset(self): self._setRTS(False) self._setDTR(False) # Idle time.sleep(0.1) @@ -121,7 +139,7 @@ def __init__(self, port, uses_usb_otg=False): super().__init__(port) self.uses_usb_otg = uses_usb_otg - def __call__(self): + def reset(self): self._setRTS(True) # EN->LOW if self.uses_usb_otg: # Give the chip some time to come out of reset, @@ -162,7 +180,7 @@ class CustomReset(ResetStrategy): "U": "self._setDTRandRTS({})", } - def __call__(self): + def reset(self): exec(self.constructed_strategy) def __init__(self, port, seq_str): diff --git a/esptool/util.py b/esptool/util.py index fb4a57193..71bf5da17 100644 --- a/esptool/util.py +++ b/esptool/util.py @@ -99,6 +99,20 @@ def get_file_size(path_to_file): return file_size +class PrintOnce: + """ + Class for printing messages just once. Can be useful when running in a loop + """ + + def __init__(self) -> None: + self.already_printed = False + + def __call__(self, text) -> None: + if not self.already_printed: + print(text) + self.already_printed = True + + class FatalError(RuntimeError): """ Wrapper class for runtime errors that aren't caused by internal bugs, but by diff --git a/test/test_esptool.py b/test/test_esptool.py index 279b8ebdf..a825e6ce0 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -1204,6 +1204,30 @@ def test_highspeed_flash_virtual_port(self): ) self.verify_readback(0, 50 * 1024, "images/fifty_kb.bin") + @pytest.fixture + def pty_port(self): + import pty + + master_fd, slave_fd = pty.openpty() + yield os.ttyname(slave_fd) + os.close(master_fd) + os.close(slave_fd) + + @pytest.mark.host_test + def test_pty_port(self, pty_port): + cmd = [sys.executable, "-m", "esptool", "--port", pty_port, "chip_id"] + output = subprocess.run( + cmd, + cwd=TEST_DIR, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + ) + # no chip connected so command should fail + assert output.returncode != 0 + output = output.stdout.decode("utf-8") + print(output) # for logging + assert "WARNING: Chip was NOT reset." in output + @pytest.mark.quick_test class TestReadWriteMemory(EsptoolTestCase): From 35f0456aa0121300dcd624406ca759cbb701f860 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Fri, 15 Dec 2023 15:09:54 +0100 Subject: [PATCH 112/209] fix(esptool): Proper alignment for SoCs with offset load Update the --ram-only-header segments handling for the ESP32 and ESP32-S2 SoC. Signed-off-by: Marek Matej --- esptool/bin_image.py | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 4e917316d..e7038f044 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -738,15 +738,23 @@ def get_alignment_data_needed(segment): flash_segments.reverse() for segment in flash_segments: pad_len = get_alignment_data_needed(segment) - while pad_len > 0: - pad_segment = ImageSegment(0, b"\x00" * pad_len, f.tell()) - self.save_segment(f, pad_segment) - total_segments += 1 - pad_len = get_alignment_data_needed(segment) - # write the flash segment - assert ( - f.tell() + 8 - ) % self.IROM_ALIGN == segment.addr % self.IROM_ALIGN + # Some chips have a non-zero load offset (eg. 0x1000) + # therefore we shift the ROM segments "-load_offset" + # so it will be aligned properly after it is flashed + align_min = ( + self.ROM_LOADER.BOOTLOADER_FLASH_OFFSET - self.SEG_HEADER_LEN + ) + if pad_len < align_min: + print("Unable to align the segment!") + break + pad_len -= self.ROM_LOADER.BOOTLOADER_FLASH_OFFSET + pad_segment = ImageSegment(0, b"\x00" * pad_len, f.tell()) + self.save_segment(f, pad_segment) + total_segments += 1 + # check the alignment + assert (f.tell() + 8 + self.ROM_LOADER.BOOTLOADER_FLASH_OFFSET) % ( + self.IROM_ALIGN + ) == segment.addr % self.IROM_ALIGN # save the flash segment but not saving its checksum neither # saving the number of flash segments, since ROM bootloader # should "not see" them From b1aa7798cfab3d76afbd56002e3b662e261cfa52 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 3 Jan 2024 13:55:31 +0100 Subject: [PATCH 113/209] fix(read_flash): flush transmit buffer less often to inrease throughput Closes https://github.com/espressif/esptool/issues/936 --- esptool/targets/stub_flasher/stub_flasher_32c3.json | 8 ++++---- esptool/targets/stub_flasher/stub_flasher_32c5beta3.json | 8 ++++---- esptool/targets/stub_flasher/stub_flasher_32c6.json | 8 ++++---- esptool/targets/stub_flasher/stub_flasher_32h2.json | 8 ++++---- esptool/targets/stub_flasher/stub_flasher_32s3.json | 8 ++++---- flasher_stub/stub_io.c | 9 ++++++++- 6 files changed, 28 insertions(+), 21 deletions(-) diff --git a/esptool/targets/stub_flasher/stub_flasher_32c3.json b/esptool/targets/stub_flasher/stub_flasher_32c3.json index 439e043d0..788ae646d 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32c3.json +++ b/esptool/targets/stub_flasher/stub_flasher_32c3.json @@ -1,8 +1,8 @@ { - "entry": 1077413532, - "text": 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+171,15 @@ void stub_tx_one_char(char c) #endif // WITH_USB_OTG uart_tx_one_char(c); #if WITH_USB_JTAG_SERIAL + static unsigned short transferred_without_flush = 0; if (stub_uses_usb_jtag_serial()){ - stub_tx_flush(); + // Defer flushing until we have a (full - 1) packet or a end of packet (0xc0) byte to increase throughput. + // Note that deferring flushing until we have a full packet can cause hang-ups on some platforms. + ++transferred_without_flush; + if (c == '\xc0' || transferred_without_flush >= 63) { + stub_tx_flush(); + transferred_without_flush = 0; + } } #endif // WITH_USB_JTAG_SERIAL } From 220e4b1662650828e2659f11608a6f03acdec194 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 10 Jan 2024 16:59:43 +0100 Subject: [PATCH 114/209] fix(read_flash): add flash size arg to enable reading past 2MB without stub --- docs/en/esptool/basic-commands.rst | 5 +++ esptool/__init__.py | 67 +++++++++++++++++------------- esptool/targets/esp32.py | 16 ++++--- test/test_esptool.py | 42 +++++++++++++++---- 4 files changed, 88 insertions(+), 42 deletions(-) diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index ead5ac208..33070671a 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -113,6 +113,11 @@ It is also possible to autodetect flash size by using ``ALL`` as size. The above esptool.py -p PORT -b 460800 read_flash 0 ALL flash_contents.bin +.. note:: + + When using the ``read_flash`` command in combination with the ``--no-stub`` argument, it may be necessary to also set the ``--flash_size`` argument to ensure proper reading of the flash contents by the ROM. + + .. note:: If ``write_flash`` updated the boot image's :ref:`flash mode and flash size ` during flashing then these bytes may be different when read back. diff --git a/esptool/__init__.py b/esptool/__init__.py index ffe6db787..2227f5762 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -217,7 +217,12 @@ def add_spi_connection_arg(parent): default="0xFFFFFFFF", ) - def add_spi_flash_subparsers(parent, allow_keep, auto_detect): + def add_spi_flash_subparsers( + parent: argparse.ArgumentParser, + allow_keep: bool, + auto_detect: bool, + size_only: bool = False, + ): """Add common parser arguments for SPI flash properties""" extra_keep_args = ["keep"] if allow_keep else [] @@ -234,33 +239,35 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): extra_fs_message = "" flash_sizes = [] - parent.add_argument( - "--flash_freq", - "-ff", - help="SPI Flash frequency", - choices=extra_keep_args - + [ - "80m", - "60m", - "48m", - "40m", - "30m", - "26m", - "24m", - "20m", - "16m", - "15m", - "12m", - ], - default=os.environ.get("ESPTOOL_FF", "keep" if allow_keep else None), - ) - parent.add_argument( - "--flash_mode", - "-fm", - help="SPI Flash mode", - choices=extra_keep_args + ["qio", "qout", "dio", "dout"], - default=os.environ.get("ESPTOOL_FM", "keep" if allow_keep else "qio"), - ) + if not size_only: + parent.add_argument( + "--flash_freq", + "-ff", + help="SPI Flash frequency", + choices=extra_keep_args + + [ + "80m", + "60m", + "48m", + "40m", + "30m", + "26m", + "24m", + "20m", + "16m", + "15m", + "12m", + ], + default=os.environ.get("ESPTOOL_FF", "keep" if allow_keep else None), + ) + parent.add_argument( + "--flash_mode", + "-fm", + help="SPI Flash mode", + choices=extra_keep_args + ["qio", "qout", "dio", "dout"], + default=os.environ.get("ESPTOOL_FM", "keep" if allow_keep else "qio"), + ) + parent.add_argument( "--flash_size", "-fs", @@ -540,7 +547,9 @@ def add_spi_flash_subparsers(parent, allow_keep, auto_detect): parser_read_flash = subparsers.add_parser( "read_flash", help="Read SPI flash content" ) - add_spi_connection_arg(parser_read_flash) + add_spi_flash_subparsers( + parser_read_flash, allow_keep=True, auto_detect=True, size_only=True + ) parser_read_flash.add_argument("address", help="Start address", type=arg_auto_int) parser_read_flash.add_argument( "size", diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index fd8e3f518..690fdbb91 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -329,11 +329,17 @@ def read_flash_slow(self, offset, length, progress_fn): data = b"" while len(data) < length: block_len = min(BLOCK_LEN, length - len(data)) - r = self.check_command( - "read flash block", - self.ESP_READ_FLASH_SLOW, - struct.pack(" Date: Tue, 5 Dec 2023 17:39:16 +0800 Subject: [PATCH 115/209] feat(espefuse): Adds new efuses for esp32c6 and esp32h2 --- espefuse/efuse_defs/esp32c6.yaml | 12 +++++++++--- espefuse/efuse_defs/esp32h2.yaml | 25 ++++++++++++++----------- 2 files changed, 23 insertions(+), 14 deletions(-) diff --git a/espefuse/efuse_defs/esp32c6.yaml b/espefuse/efuse_defs/esp32c6.yaml index aee94306f..7afb4871e 100644 --- a/espefuse/efuse_defs/esp32c6.yaml +++ b/espefuse/efuse_defs/esp32c6.yaml @@ -1,4 +1,4 @@ -VER_NO: 709e8ea096e8a03a10006d40d5451a49 +VER_NO: df46b69f0ed3913114ba53d3a0b2b843 EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} @@ -61,8 +61,14 @@ EFUSES: RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:16]', bloc: 'B6,B7'} - MAC_SPI_RESERVED : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} - SPI_PAD_CONF_1 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + ACTIVE_HP_DBIAS : {show: y, blk : 1, word: 2, pos : 0, len : 5, start : 64, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the active hp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[4:0]', bloc: 'B8[4:0]'} + ACTIVE_LP_DBIAS : {show: y, blk : 1, word: 2, pos : 5, len : 5, start : 69, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the active lp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[9:5]', bloc: 'B8[7:5],B9[1:0]'} + LSLP_HP_DBG : {show: y, blk : 1, word: 2, pos: 10, len : 2, start : 74, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the lslp hp dbg, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[11:10]', bloc: 'B9[3:2]'} + LSLP_HP_DBIAS : {show: y, blk : 1, word: 2, pos: 12, len : 4, start : 76, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the lslp hp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[15:12]', bloc: 'B9[7:4]'} + DSLP_LP_DBG : {show: y, blk : 1, word: 2, pos: 16, len : 3, start : 80, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the dslp lp dbg, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[18:16]', bloc: 'B10[2:0]'} + DSLP_LP_DBIAS : {show: y, blk : 1, word: 2, pos: 19, len : 4, start : 83, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the dslp lp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[22:19]', bloc: 'B10[6:3]'} + DBIAS_VOL_GAP : {show: y, blk : 1, word: 2, pos: 23, len : 5, start : 87, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the hp and lp dbias vol gap, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[27:23]', bloc: 'B10[7],B11[3:0]'} + SPI_PAD_CONF_1 : {show: n, blk : 1, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:28]', bloc: 'B11[7:4]'} SPI_PAD_CONF_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 4, start: 114, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[21:18]', bloc: 'B14[5:2]'} WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 22, len : 2, start: 118, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:22]', bloc: 'B14[7:6]'} diff --git a/espefuse/efuse_defs/esp32h2.yaml b/espefuse/efuse_defs/esp32h2.yaml index a86a01895..7e2b246fc 100644 --- a/espefuse/efuse_defs/esp32h2.yaml +++ b/espefuse/efuse_defs/esp32h2.yaml @@ -1,4 +1,4 @@ -VER_NO: b69ddcfb39a412df490e3facbbfb46b2 +VER_NO: ef562916e77cf77203c1a4c0cff35ac5 EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} @@ -56,17 +56,20 @@ EFUSES: RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'} - RXIQ_VERSION : {show: y, blk : 1, word: 2, pos : 0, len : 3, start : 64, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[2:0]', bloc: 'B8[2:0]'} - RXIQ_0 : {show: y, blk : 1, word: 2, pos : 3, len : 7, start : 67, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 0, rloc: 'EFUSE_RD_MAC_SYS_2_REG[9:3]', bloc: 'B8[7:3],B9[1:0]'} - RXIQ_1 : {show: y, blk : 1, word: 2, pos: 10, len : 7, start : 74, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: RF Calibration data. RXIQ data 1, rloc: 'EFUSE_RD_MAC_SYS_2_REG[16:10]', bloc: 'B9[7:2],B10[0]'} - RESERVED_1_81 : {show: n, blk : 1, word: 2, pos: 17, len : 15, start : 81, type : 'uint:15', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:17]', bloc: 'B10[7:1],B11'} - MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} - WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} - WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 21, len : 2, start: 117, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[22:21]', bloc: 'B14[6:5]'} + RXIQ_VERSION : {show: y, blk : 1, word: 2, pos : 0, len : 3, start : 64, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores RF Calibration data. RXIQ version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[2:0]', bloc: 'B8[2:0]'} + RXIQ_0 : {show: y, blk : 1, word: 2, pos : 3, len : 7, start : 67, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores RF Calibration data. RXIQ data 0, rloc: 'EFUSE_RD_MAC_SYS_2_REG[9:3]', bloc: 'B8[7:3],B9[1:0]'} + RXIQ_1 : {show: y, blk : 1, word: 2, pos: 10, len : 7, start : 74, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores RF Calibration data. RXIQ data 1, rloc: 'EFUSE_RD_MAC_SYS_2_REG[16:10]', bloc: 'B9[7:2],B10[0]'} + ACTIVE_HP_DBIAS : {show: y, blk : 1, word: 2, pos: 17, len : 5, start : 81, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the PMU active hp dbias, rloc: 'EFUSE_RD_MAC_SYS_2_REG[21:17]', bloc: 'B10[5:1]'} + ACTIVE_LP_DBIAS : {show: y, blk : 1, word: 2, pos: 22, len : 5, start : 86, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the PMU active lp dbias, rloc: 'EFUSE_RD_MAC_SYS_2_REG[26:22]', bloc: 'B10[7:6],B11[2:0]'} + DSLP_DBIAS : {show: y, blk : 1, word: 2, pos: 27, len : 4, start : 91, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the PMU sleep dbias, rloc: 'EFUSE_RD_MAC_SYS_2_REG[30:27]', bloc: 'B11[6:3]'} + DBIAS_VOL_GAP : {show: y, blk : 1, word: 2, pos: 31, len : 5, start : 95, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the low 1 bit of dbias_vol_gap, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31]', bloc: 'B11[7],B12[3:0]'} + MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 4, len : 14, start: 100, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_3_REG[17:4]', bloc: 'B12[7:4],B13,B14[1:0]'} + WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 3, start: 114, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the wafer version minor, rloc: 'EFUSE_RD_MAC_SYS_3_REG[20:18]', bloc: 'B14[4:2]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 21, len : 2, start: 117, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the wafer version major, rloc: 'EFUSE_RD_MAC_SYS_3_REG[22:21]', bloc: 'B14[6:5]'} DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 23, len : 1, start: 119, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_MAC_SYS_3_REG[23]', bloc: 'B14[7]'} - FLASH_CAP : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} - FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[28:27]', bloc: 'B15[4:3]'} - FLASH_VENDOR : {show: y, blk : 1, word: 3, pos: 29, len : 3, start: 125, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:29]', bloc: 'B15[7:5]'} + FLASH_CAP : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the flash cap, rloc: 'EFUSE_RD_MAC_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the flash temp, rloc: 'EFUSE_RD_MAC_SYS_3_REG[28:27]', bloc: 'B15[4:3]'} + FLASH_VENDOR : {show: y, blk : 1, word: 3, pos: 29, len : 3, start: 125, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the flash vendor, rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:29]', bloc: 'B15[7:5]'} PKG_VERSION : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} RESERVED_1_131 : {show: n, blk : 1, word: 4, pos : 3, len : 29, start: 131, type : 'uint:29', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_4_REG[31:3]', bloc: 'B16[7:3],B17,B18,B19'} SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_5_REG, bloc: 'B20,B21,B22,B23'} From 19305a8e27f70d8143af42c739ad122d4a339a9e Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Tue, 16 Jan 2024 19:11:23 +0800 Subject: [PATCH 116/209] feat(espefuse): check_error --recover chip even if there are num_errors --- espefuse/efuse/base_operations.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/espefuse/efuse/base_operations.py b/espefuse/efuse/base_operations.py index 5e3475e49..d95b3095b 100644 --- a/espefuse/efuse/base_operations.py +++ b/espefuse/efuse/base_operations.py @@ -684,7 +684,8 @@ def burn_bit(esp, efuses, args): def get_error_summary(efuses): - error_in_blocks = efuses.get_coding_scheme_warnings() + efuses.get_coding_scheme_warnings() + error_in_blocks = any(blk.fail or blk.num_errors != 0 for blk in efuses.blocks) if not error_in_blocks: return False writable = True From faa88a7a94bc149d0ae56404921ca435c45b241b Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 16 Jan 2024 10:35:37 +0100 Subject: [PATCH 117/209] feat: add advisory port locking Closes https://github.com/espressif/esptool/issues/946 --- esp_rfc2217_server.py | 2 +- esptool/loader.py | 2 +- setup.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/esp_rfc2217_server.py b/esp_rfc2217_server.py index 8b9a1678e..cf83a183b 100755 --- a/esp_rfc2217_server.py +++ b/esp_rfc2217_server.py @@ -256,7 +256,7 @@ def main(): logging.getLogger("rfc2217").setLevel(level) # connect to serial port - ser = serial.serial_for_url(args.SERIALPORT, do_not_open=True) + ser = serial.serial_for_url(args.SERIALPORT, do_not_open=True, exclusive=True) ser.timeout = 3 # required so that the reader thread can exit # reset control line as no _remote_ "terminal" has been connected yet ser.dtr = False diff --git a/esptool/loader.py b/esptool/loader.py index 802531f2d..56aab58e4 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -300,7 +300,7 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): if isinstance(port, str): try: - self._port = serial.serial_for_url(port) + self._port = serial.serial_for_url(port, exclusive=True) except serial.serialutil.SerialException as e: port_issues = [ [ # does not exist error diff --git a/setup.py b/setup.py index 67912bc0b..39d88e02c 100644 --- a/setup.py +++ b/setup.py @@ -128,7 +128,7 @@ def find_version(*file_paths): "bitstring>=3.1.6", "cryptography>=2.1.4", "ecdsa>=0.16.0", - "pyserial>=3.0", + "pyserial>=3.3", "reedsolo>=1.5.3,<1.8", "PyYAML>=5.1", "intelhex", From 5861fb70802b213e14fb8f8b05376540eed46e82 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Mon, 15 Jan 2024 17:31:25 +0100 Subject: [PATCH 118/209] fix: Index image segments from 0 instead of 1 idf.py (for example in idf.py monitor command) numbers the segments starting from 0, but current esptool.py image_view numbers them starting from 1. This MR unifies the behaviors between idf.py and esptool.py image_view --version 2 (which will be the default version of image_view in new v 5.0). --- esptool/cmds.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 87abb880f..a12427112 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -793,7 +793,7 @@ def get_key_from_value(dict, val): format_str = "{:7} {:#07x} {:#010x} {:#010x} {}" app_desc = None bootloader_desc = None - for idx, seg in enumerate(image.segments, start=1): + for idx, seg in enumerate(image.segments): segs = seg.get_memory_type(image) seg_name = ", ".join(segs) if "DROM" in segs: # The DROM segment starts with the esp_app_desc_t struct From b8f69d9517c9646ff6d530ae2f812b58c6e28417 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Tue, 16 Jan 2024 09:59:23 +0100 Subject: [PATCH 119/209] ci: Edit tests to take new segment indexing into account --- test/test_image_info.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/test_image_info.py b/test/test_image_info.py index 3dac7310a..f84c62473 100755 --- a/test/test_image_info.py +++ b/test/test_image_info.py @@ -101,7 +101,7 @@ def test_v2_esp32c3(self): # Segments assert ( - "2 0x01864 0x3fcd6114 0x00000034 DRAM, BYTE_ACCESSIBLE" in out + "1 0x01864 0x3fcd6114 0x00000034 DRAM, BYTE_ACCESSIBLE" in out ), "Wrong segment info" # Footer @@ -126,7 +126,7 @@ def test_v2_esp8266(self): assert "Flash mode: QIO" in out, "Wrong flash mode" assert "Checksum: 0x6b (valid)" in out, "Invalid checksum" assert "Segments: 1" in out, "Wrong number of segments" - assert "1 0x00014 0x40100000 0x00000008 IRAM" in out, "Wrong segment info" + assert "0 0x00014 0x40100000 0x00000008 IRAM" in out, "Wrong segment info" def test_image_type_detection(self): # ESP8266, version 1 and 2 From a95aa8dbf6d74bb093dcf653c37c18ca46ca8963 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Thu, 18 Jan 2024 15:18:11 +0100 Subject: [PATCH 120/209] ci: Add ESP32-P4 target and tests --- .gitlab-ci.yml | 8 ++++++++ test/test_esptool.py | 12 +++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index ed1410e09..2a193172b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -383,6 +383,14 @@ target_esp32h2_jtag_serial: script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32H2_JTAG_SERIAL --preload-port /dev/serial_ports/ESP32H2_PRELOAD --chip esp32h2 --baud 115200 +# ESP32P4 +target_esp32p4: + extends: .target_esptool_test + tags: + - esptool_esp32p4_target + script: + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32P4 --chip esp32p4 --baud 115200 + .windows_test: stage: test variables: diff --git a/test/test_esptool.py b/test/test_esptool.py index ba7a93e21..967972621 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -184,7 +184,7 @@ def run_esptool_process(cmd): preload and arg_preload_port and arg_chip - in ["esp32c3", "esp32s3", "esp32c6", "esp32h2"] # With USB-JTAG/Serial + in ["esp32c3", "esp32s3", "esp32c6", "esp32h2", "esp32p4"] # With U-JS ): port_index = base_cmd.index("--port") + 1 base_cmd[port_index] = arg_preload_port # Set the port to the preload one @@ -1012,9 +1012,7 @@ class TestKeepImageSettings(EsptoolTestCase): def setup_class(self): super(TestKeepImageSettings, self).setup_class() self.BL_IMAGE = f"images/bootloader_{arg_chip}.bin" - self.flash_offset = ( - 0x1000 if arg_chip in ("esp32", "esp32s2") else 0 - ) # bootloader offset + self.flash_offset = esptool.CHIP_DEFS[arg_chip].BOOTLOADER_FLASH_OFFSET with open(self.BL_IMAGE, "rb") as f: self.header = f.read(8) @@ -1085,7 +1083,7 @@ def test_explicit_set_size_freq_mode(self): @pytest.mark.skipif( - arg_chip in ["esp32s2", "esp32s3"], + arg_chip in ["esp32s2", "esp32s3", "esp32p4"], reason="Not supported on targets with USB-CDC.", ) class TestLoadRAM(EsptoolTestCase): @@ -1169,7 +1167,7 @@ class TestBootloaderHeaderRewriteCases(EsptoolTestCase): ) @pytest.mark.quick_test def test_flash_header_rewrite(self): - bl_offset = 0x1000 if arg_chip in ("esp32", "esp32s2") else 0 + bl_offset = esptool.CHIP_DEFS[arg_chip].BOOTLOADER_FLASH_OFFSET bl_image = f"images/bootloader_{arg_chip}.bin" output = self.run_esptool( @@ -1187,7 +1185,7 @@ def test_flash_header_rewrite(self): def test_flash_header_no_magic_no_rewrite(self): # first image doesn't start with magic byte, second image does # but neither are valid bootloader binary images for either chip - bl_offset = 0x1000 if arg_chip in ("esp32", "esp32s2") else 0 + bl_offset = esptool.CHIP_DEFS[arg_chip].BOOTLOADER_FLASH_OFFSET for image in ["images/one_kb.bin", "images/one_kb_all_ef.bin"]: output = self.run_esptool( f"write_flash -fm dout -ff 20m {bl_offset:#x} {image}" From 4ed54e83924fcc06365a3ccb5a3d5c7d8695f16b Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 17 Jan 2024 15:57:07 +0100 Subject: [PATCH 121/209] docs: Add instructions on how to update --- .github/ISSUE_TEMPLATE/bug-report-no-hw.yml | 2 +- .github/ISSUE_TEMPLATE/issue-with-hw.yml | 2 +- docs/en/esptool/flashing-firmware.rst | 2 + docs/en/installation.rst | 51 ++++++++++++++++++++- 4 files changed, 53 insertions(+), 4 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report-no-hw.yml b/.github/ISSUE_TEMPLATE/bug-report-no-hw.yml index 278dfe3ae..40dc5fa17 100644 --- a/.github/ISSUE_TEMPLATE/bug-report-no-hw.yml +++ b/.github/ISSUE_TEMPLATE/bug-report-no-hw.yml @@ -14,7 +14,7 @@ body: id: version attributes: label: Esptool Version - description: The output of `git describe` if working with the sources, output of `esptool.py version` otherwise. If possible, consider updating esptool. + description: The output of `git describe` if working with the sources, output of `esptool.py version` otherwise. If possible, consider [updating esptool](https://docs.espressif.com/projects/esptool/en/latest/installation.html#how-to-update). placeholder: ex. v4.0.1, commit v4.1-10-g2059335aa validations: required: true diff --git a/.github/ISSUE_TEMPLATE/issue-with-hw.yml b/.github/ISSUE_TEMPLATE/issue-with-hw.yml index 69c84acb2..a2ae0bd70 100644 --- a/.github/ISSUE_TEMPLATE/issue-with-hw.yml +++ b/.github/ISSUE_TEMPLATE/issue-with-hw.yml @@ -21,7 +21,7 @@ body: id: version attributes: label: Esptool Version - description: The output of `git describe` if working with the sources, output of `esptool.py version` otherwise. If possible, consider updating esptool. + description: The output of `git describe` if working with the sources, output of `esptool.py version` otherwise. If possible, consider [updating esptool](https://docs.espressif.com/projects/esptool/en/latest/installation.html#how-to-update). placeholder: ex. v4.0.1, commit v4.1-10-g2059335aa validations: required: true diff --git a/docs/en/esptool/flashing-firmware.rst b/docs/en/esptool/flashing-firmware.rst index e99675840..83392ebc1 100644 --- a/docs/en/esptool/flashing-firmware.rst +++ b/docs/en/esptool/flashing-firmware.rst @@ -1,3 +1,5 @@ +.. _flashing: + Flashing Firmware ================= diff --git a/docs/en/installation.rst b/docs/en/installation.rst index 7fe9f876e..4fcfc1ea2 100644 --- a/docs/en/installation.rst +++ b/docs/en/installation.rst @@ -1,8 +1,14 @@ -.. _installation: - Installation and Dependencies ============================= +.. _installation: + +How to Install +-------------- + +Global Installation +^^^^^^^^^^^^^^^^^^^ + You will need `Python 3.7 or newer `_ installed on your system to use the latest version of ``esptool.py``. If your use case requires Python 2.7, 3.4, 3.5, or 3.6, please use ``esptool.py`` v3.3.* instead. @@ -21,3 +27,44 @@ After installing, you will have ``esptool.py`` installed into the default Python .. note:: If you actually plan to do development work with esptool itself, see :ref:`development-setup` for more information. + +Virtual Environment Installation +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To ensure that ``esptool.py`` is used in isolation, and any changes made during its usage won't affect other Python environments or SDK installations, it is advised to install it in a virtual environment and use it directly if possible (more information in the :ref:`flashing` article). + +Creating a virtual environment (venv) is a good practice. This is particularly helpful for users who may be concerned about interfering with existing installations (e.g. in an environment of a development-setup framework). Here's a quick guide: + +- Create a virtual environment and choose its name, e.g. 'esptoolenv': ``python -m venv esptoolenv`` +- Activate the virtual environment: + + - On Windows: ``esptoolenv\Scripts\activate`` + - On Linux or MacOS: ``source esptoolenv/bin/activate`` + +- Install the latest ``esptool.py`` version within the active virtual environment: ``pip install esptool`` +- You can now use it within this virtual environment without affecting your system-wide installations: ``esptool.py `` +- When you're done using ``esptool.py``, deactivate the virtual environment: ``deactivate``. The environment can be reused by activating it again. +- If you no longer need the virtual environment, you can remove it by deleting the ``esptoolenv`` directory. + +How to Update +------------- + +Standalone +^^^^^^^^^^ + +If you are using ``esptool.py`` as a standalone tool (as a global installation or in a virtual environment), updating to the latest version released on the `PyPI `_ index is simple: + +:: + + $ pip install --upgrade esptool + +As a Component +^^^^^^^^^^^^^^ + +If ``esptool.py`` is installed as a component of a development framework (e.g. `ESP-IDF `_, `Arduino `_, or `PlatformIO `_), it is advised to follow the update guide of used framework for instructions and not to update the tool directly. + +If updating directly is unavoidable, make sure you update to a compatible version by staying on the same MAJOR version number (explaned in the :ref:`versions` article). For instance, if your currently installed ``esptool.py`` is ``v3.3.1``, only update to ``v3.*.*``. You risk introducing incompatible changes by updating to ``v4.*.*`` or higher. + +:: + + $ pip install esptool==3.3.2 From 85a3e1f534a70417208f59f6eb75bcf9c42b39a9 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Sat, 25 Nov 2023 16:02:05 +0800 Subject: [PATCH 122/209] feat(espefuse): Postpone some efuses to burn them at the very end --- espefuse/__init__.py | 9 +++ espefuse/efuse/base_fields.py | 106 ++++++++++++++++++++++++++++++++-- test/test_espefuse.py | 26 +++++++++ 3 files changed, 137 insertions(+), 4 deletions(-) diff --git a/espefuse/__init__.py b/espefuse/__init__.py index 849c3a270..71689662c 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -214,6 +214,12 @@ def main(custom_commandline=None, esp=None): "Use with caution.", action="store_true", ) + init_parser.add_argument( + "--postpone", + help="Postpone burning some efuses from BLOCK0 at the end, " + "(efuses which disable access to blocks or chip).", + action="store_true", + ) common_args, remaining_args = init_parser.parse_known_args(custom_commandline) debug_mode = common_args.debug or ("dump" in remaining_args) @@ -263,6 +269,8 @@ def main(custom_commandline=None, esp=None): if there_are_multiple_burn_commands_in_args: efuses.batch_mode_cnt += 1 + efuses.postpone = common_args.postpone + try: for rem_args in grouped_remaining_args: args, unused_args = parser.parse_known_args(rem_args, namespace=common_args) @@ -289,6 +297,7 @@ def main(custom_commandline=None, esp=None): efuses.batch_mode_cnt -= 1 if not efuses.burn_all(check_batch_mode=True): raise esptool.FatalError("BURN was not done") + print("Successful") finally: if not external_esp and not common_args.virt and esp._port: esp._port.close() diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index ab12f0312..8ad6616f9 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -445,6 +445,7 @@ class EspEfusesBase(object): coding_scheme = None force_write_always = None batch_mode_cnt = 0 + postpone = False def __iter__(self): return self.efuses.__iter__() @@ -489,6 +490,59 @@ def update_efuses(self): for efuse in self.efuses: efuse.update(self.blocks[efuse.block].bitarray) + def postpone_efuses_from_block0_to_burn(self, block): + postpone_efuses = {} + + if block.id != 0: + return postpone_efuses + + # We need to check this list of efuses. If we are going to burn an efuse + # from this list, then we need to split the burn operation into two + # steps. The first step involves burning efuses not in this list. In + # case of an error during this step, we can recover by burning the + # efuses from this list at the very end. This approach provides the + # ability to recover efuses if an error occurs during the initial burn + # operation. + + # List the efuses here that must be burned at the very end, such as read + # and write protection fields, as well as efuses that disable + # communication with the espefuse tool. + efuses_list = ["WR_DIS", "RD_DIS"] + if self._esp.CHIP_NAME == "ESP32": + # Efuses below disables communication with the espefuse tool. + efuses_list.append("UART_DOWNLOAD_DIS") + # other efuses that are better to burn at the very end. + efuses_list.append("ABS_DONE_1") + efuses_list.append("FLASH_CRYPT_CNT") + else: + # Efuses below disables communication with the espefuse tool. + efuses_list.append("ENABLE_SECURITY_DOWNLOAD") + efuses_list.append("DIS_DOWNLOAD_MODE") + # other efuses that are better to burn at the very end. + efuses_list.append("SPI_BOOT_CRYPT_CNT") + efuses_list.append("SECURE_BOOT_EN") + + def get_raw_value_from_write(self, efuse_name): + return self[efuse_name].get_bitstring(from_read=False) + + for efuse_name in efuses_list: + postpone_efuses[efuse_name] = get_raw_value_from_write(self, efuse_name) + + if any(value != 0 for value in postpone_efuses.values()): + if self.debug: + print("These BLOCK0 efuses will be burned later at the very end:") + print(postpone_efuses) + # exclude these efuses from the first burn (postpone them till the end). + for key_name in postpone_efuses.keys(): + self[key_name].reset() + return postpone_efuses + + def recover_postponed_efuses_from_block0_to_burn(self, postpone_efuses): + if any(value != 0 for value in postpone_efuses.values()): + print("Burn postponed efuses from BLOCK0.") + for key_name in postpone_efuses.keys(): + self[key_name].save(postpone_efuses[key_name]) + def burn_all(self, check_batch_mode=False): if check_batch_mode: if self.batch_mode_cnt != 0: @@ -508,18 +562,44 @@ def burn_all(self, check_batch_mode=False): have_wr_data_for_burn = True if not have_wr_data_for_burn: print("Nothing to burn, see messages above.") - return + return True EspEfusesBase.confirm("", self.do_not_confirm) - # Burn from BLKn -> BLK0. Because BLK0 can set rd or/and wr protection bits. - for block in reversed(self.blocks): + def burn_block(block, postponed_efuses): old_fail = block.fail old_num_errors = block.num_errors block.burn() if (block.fail and old_fail != block.fail) or ( block.num_errors and block.num_errors > old_num_errors ): + if postponed_efuses: + print("The postponed efuses were not burned due to an error.") + print("\t1. Try to fix a coding error by this cmd:") + print("\t 'espefuse.py check_error --recovery'") + command_string = " ".join( + f"{key} {value}" + for key, value in postponed_efuses.items() + if value.any(True) + ) + print("\t2. Then run the cmd to burn all postponed efuses:") + print(f"\t 'espefuse.py burn_efuse {command_string}'") + raise esptool.FatalError("Error(s) were detected in eFuses") + + # Burn from BLKn -> BLK0. Because BLK0 can set rd or/and wr protection bits. + for block in reversed(self.blocks): + postponed_efuses = ( + self.postpone_efuses_from_block0_to_burn(block) + if self.postpone + else None + ) + + burn_block(block, postponed_efuses) + + if postponed_efuses: + self.recover_postponed_efuses_from_block0_to_burn(postponed_efuses) + burn_block(block, postponed_efuses) + print("Reading updated efuses...") self.read_coding_scheme() self.read_blocks() @@ -628,6 +708,10 @@ def convert_to_bitstring(self, new_value): def check_new_value(self, bitarray_new_value): bitarray_old_value = self.get_bitstring() | self.get_bitstring(from_read=False) + + if not bitarray_new_value.any(True) and not bitarray_old_value.any(True): + return + if bitarray_new_value.len != bitarray_old_value.len: raise esptool.FatalError( "For {} efuse, the length of the new value is wrong, " @@ -635,7 +719,10 @@ def check_new_value(self, bitarray_new_value): self.name, bitarray_old_value.len, bitarray_new_value.len ) ) - if bitarray_new_value == bitarray_old_value: + if ( + bitarray_new_value == bitarray_old_value + or bitarray_new_value & self.get_bitstring() == bitarray_new_value + ): error_msg = "\tThe same value for {} ".format(self.name) error_msg += "is already burned. Do not change the efuse." print(error_msg) @@ -752,3 +839,14 @@ def get_info(self): if name is not None: output += f"\n Purpose: {self.parent[name].get()}\n " return output + + def reset(self): + # resets a efuse that is prepared for burning + bitarray_field = self.convert_to_bitstring(0) + block = self.parent.blocks[self.block] + wr_bitarray_temp = block.wr_bitarray.copy() + position = wr_bitarray_temp.length - ( + self.word * 32 + self.pos + bitarray_field.len + ) + wr_bitarray_temp.overwrite(bitarray_field, pos=position) + block.wr_bitarray = wr_bitarray_temp diff --git a/test/test_espefuse.py b/test/test_espefuse.py index c38f96b98..531aa6f77 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -1977,3 +1977,29 @@ def test_burn_ecdsa_key(self): "key due to a hardware bug (please see TRM for more details)", ret_code=2, ) + + +class TestPostponedEfuses(EfuseTestCase): + def test_postpone_efuses(self): + if arg_chip == "esp32": + cmd = f"--postpone \ + burn_efuse UART_DOWNLOAD_DIS 1 \ + burn_key BLOCK1 {IMAGES_DIR}/256bit \ + burn_efuse ABS_DONE_1 1 FLASH_CRYPT_CNT 1" + num = 1 + else: + sb_digest_name = ( + "SECURE_BOOT_DIGEST" if arg_chip == "esp32c2" else "SECURE_BOOT_DIGEST0" + ) + cmd = f"--postpone \ + burn_efuse ENABLE_SECURITY_DOWNLOAD 1 DIS_DOWNLOAD_MODE 1 \ + SECURE_VERSION 1 \ + burn_key BLOCK_KEY0 {IMAGES_DIR}/256bit {sb_digest_name} \ + burn_efuse SPI_BOOT_CRYPT_CNT 1 SECURE_BOOT_EN 1" + num = 3 if arg_chip == "esp32c2" else 4 + output = self.espefuse_py(cmd) + assert f"BURN BLOCK{num} - OK" in output + assert "BURN BLOCK0 - OK" in output + assert "Burn postponed efuses from BLOCK0" in output + assert "BURN BLOCK0 - OK" in output + assert "Successful" in output From aea43c4eb75788ed094156011bb6e7138b12f88d Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 19 Jan 2024 16:13:14 +0100 Subject: [PATCH 123/209] fix(merge_bin): treat files starting with colon as raw files --- esptool/bin_image.py | 22 +++++++++++++--------- test/test_merge_bin.py | 10 ++++++++++ 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index e7038f044..d260ef92a 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -13,7 +13,7 @@ import tempfile from typing import BinaryIO, Optional -from intelhex import IntelHex +from intelhex import HexRecordError, IntelHex from .loader import ESPLoader from .targets import ( @@ -47,14 +47,18 @@ def intel_hex_to_bin(file: BinaryIO, start_addr: Optional[int] = None) -> Binary INTEL_HEX_MAGIC = b":" magic = file.read(1) file.seek(0) - if magic == INTEL_HEX_MAGIC: - ih = IntelHex() - ih.loadhex(file.name) - file.close() - bin = tempfile.NamedTemporaryFile(suffix=".bin", delete=False) - ih.tobinfile(bin, start=start_addr) - return bin - else: + try: + if magic == INTEL_HEX_MAGIC: + ih = IntelHex() + ih.loadhex(file.name) + file.close() + bin = tempfile.NamedTemporaryFile(suffix=".bin", delete=False) + ih.tobinfile(bin, start=start_addr) + return bin + else: + return file + except HexRecordError: + # file started with HEX magic but the rest was not according to the standard return file diff --git a/test/test_merge_bin.py b/test/test_merge_bin.py index c15cc0151..8723f1b0a 100755 --- a/test/test_merge_bin.py +++ b/test/test_merge_bin.py @@ -263,6 +263,16 @@ def test_merge_bin2hex(self): # verify the file itself assert source == merged_bin[0x1000:] + def test_hex_header_raw_file(self): + # use raw binary file starting with colon + with tempfile.NamedTemporaryFile(delete=False) as f: + f.write(b":") + try: + merged = self.run_merge_bin("esp32", [(0x0, f.name)]) + assert merged == b":" + finally: + os.unlink(f.name) + class UF2Block(object): def __init__(self, bs): From 2c882ccf4a3a6ccd228ea2135e9918798f4f7090 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 19 Jan 2024 16:22:07 +0100 Subject: [PATCH 124/209] change(test): generate valid UTF8 binaries for UF2 tests --- test/test_merge_bin.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/test_merge_bin.py b/test/test_merge_bin.py index 8723f1b0a..1369223fd 100755 --- a/test/test_merge_bin.py +++ b/test/test_merge_bin.py @@ -330,7 +330,7 @@ class TestUF2: def generate_binary(self, size): with tempfile.NamedTemporaryFile(delete=False) as f: for _ in range(size): - f.write(struct.pack("B", random.randrange(0, 1 << 8))) + f.write(struct.pack("B", random.randrange(0, 1 << 7))) return f.name @staticmethod From ae7f1cf5f8b5396a7ca3690410ff69c6da730b49 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Wed, 24 Jan 2024 13:20:26 +0100 Subject: [PATCH 125/209] fix: Fixed glitches on RTS line when no_reset option on Windows --- esptool/loader.py | 12 +++++++++++- test/test_esptool.py | 3 --- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/esptool/loader.py b/esptool/loader.py index 56aab58e4..ee74a78ae 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -300,7 +300,17 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): if isinstance(port, str): try: - self._port = serial.serial_for_url(port, exclusive=True) + self._port = serial.serial_for_url( + port, exclusive=True, do_not_open=True + ) + if sys.platform == "win32": + # When opening a port on Windows, + # the RTS/DTR (active low) lines + # need to be set to False (pulled high) + # to avoid unwanted chip reset + self._port.rts = False + self._port.dtr = False + self._port.open() except serial.serialutil.SerialException as e: port_issues = [ [ # does not exist error diff --git a/test/test_esptool.py b/test/test_esptool.py index 967972621..7b251ef9f 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -869,9 +869,6 @@ def test_short_flash_to_external_ROM(self): self.verify_readback(0, 1024, "images/one_kb.bin", spi_connection=self.conn) -@pytest.mark.skipif( - os.name == "nt", reason="Temporarily disabled on windows" -) # TODO: ESPTOOL-673 class TestStubReuse(EsptoolTestCase): def test_stub_reuse_with_synchronization(self): """Keep the flasher stub running and reuse it the next time.""" From 859643e4280c1aa78a80eba44a0418addead1c68 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 19 Jan 2024 12:24:48 +0100 Subject: [PATCH 126/209] feat(esp32p4): Enable USB-serial/JTAG in flasher stub --- .../stub_flasher/stub_flasher_32p4.json | 8 +++---- flasher_stub/include/rom_functions.h | 4 ++-- flasher_stub/include/soc_support.h | 22 +++++++++++++++---- flasher_stub/stub_io.c | 6 ++++- 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/esptool/targets/stub_flasher/stub_flasher_32p4.json b/esptool/targets/stub_flasher/stub_flasher_32p4.json index 274c62616..6f37e91b2 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32p4.json +++ b/esptool/targets/stub_flasher/stub_flasher_32p4.json @@ -1,8 +1,8 @@ { - "entry": 1341195718, - "text": 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ESP32C5BETA3 || ESP32P4 /* uart_tx_one_char doesn't send data to USB device serial, needs to be replaced */ int uart_tx_one_char2(char ch); #define uart_tx_one_char(ch) uart_tx_one_char2(ch) -#endif // ESP32C6 || ESP32H2 || ESP32C5BETA3 +#endif // ESP32C6 || ESP32H2 || ESP32C5BETA3 || ESP32P4 void uart_div_modify(uint32_t uart_no, uint32_t baud_div); diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index d77430765..38627368c 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -62,8 +62,8 @@ #endif // ESP32H2 #ifdef ESP32P4 -// TODO: Add support for USB modes when MP is available -// #define WITH_USB_JTAG_SERIAL 1 +#define WITH_USB_JTAG_SERIAL 1 +// TODO: Add support for USB OTG when MP is available // #define WITH_USB_OTG 1 #define IS_RISCV 1 #endif // ESP32P4 @@ -71,7 +71,8 @@ // Increase CPU freq to speed up read/write operations over USB // Disabled on the S3 due to stability issues, would require dbias adjustment. // https://github.com/espressif/esptool/issues/832, https://github.com/espressif/esptool/issues/808 -#define USE_MAX_CPU_FREQ ((WITH_USB_JTAG_SERIAL || WITH_USB_OTG) && !ESP32S3) +// Disabled for P4 because it is already running on high (360MHz) CPU frequency +#define USE_MAX_CPU_FREQ ((WITH_USB_JTAG_SERIAL || WITH_USB_OTG) && !ESP32S3 && !ESP32P4) // Later chips don't support ets_efuse_get_spiconfig. #define SUPPORT_CONFIG_SPI (ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 || ESP32C3 || ESP32H2BETA1 || ESP32H2BETA2 || ESP32C6BETA) @@ -199,6 +200,8 @@ #define SPI_BASE_REG 0x5008D000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x5008C000 /* SPI peripheral 0, inner state machine */ #define GPIO_BASE_REG 0x500E0000 +#define USB_DEVICE_BASE_REG 0x500D2000 +#define DR_REG_LP_WDT_BASE 0x50116000 #define DR_REG_IO_MUX_BASE 0x500E1000 #endif @@ -348,6 +351,17 @@ #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ #endif // ESP32H2 +#if ESP32P4 +#define UART_USB_OTG 5 +#define UART_USB_JTAG_SERIAL 6 + +#define DR_REG_INTERRUPT_MATRIX_BASE 0x500D6000 +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) /* USB-JTAG-Serial, CORE0_USB_DEVICE_INT_MAP_REG */ + +#define CLIC_EXT_INTR_NUM_OFFSET 16 /* For CLIC first 16 intrrupts are reserved as internal */ +#define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ +#endif + #ifdef WITH_USB_JTAG_SERIAL #define USB_DEVICE_INT_ENA_REG (USB_DEVICE_BASE_REG + 0x010) #define USB_DEVICE_INT_CLR_REG (USB_DEVICE_BASE_REG + 0x014) @@ -389,7 +403,7 @@ #define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 31) #endif -#if ESP32C6 || ESP32C5BETA3 +#if ESP32C6 || ESP32C5BETA3 || ESP32P4 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG #define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_SWD_CONFIG_REG diff --git a/flasher_stub/stub_io.c b/flasher_stub/stub_io.c index d0b08dd24..f86f67e7a 100644 --- a/flasher_stub/stub_io.c +++ b/flasher_stub/stub_io.c @@ -65,7 +65,11 @@ static void stub_configure_rx_uart(void) #if WITH_USB_JTAG_SERIAL if (stub_uses_usb_jtag_serial()) { #if IS_RISCV - WRITE_REG(INTERRUPT_CORE0_USB_INTR_MAP_REG, ETS_USB_INUM); // Route USB interrupt to CPU + #if ESP32P4 + WRITE_REG(INTERRUPT_CORE0_USB_INTR_MAP_REG, ETS_USB_INUM + CLIC_EXT_INTR_NUM_OFFSET); + #else + WRITE_REG(INTERRUPT_CORE0_USB_INTR_MAP_REG, ETS_USB_INUM); // Route USB interrupt to CPU + #endif esprv_intc_int_set_priority(ETS_USB_INUM, 1); #else WRITE_REG(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG, ETS_USB_INUM); From 4987d5ac15b4a536f55cbe85dfb2f413fb63094c Mon Sep 17 00:00:00 2001 From: gnought <1684105+gnought@users.noreply.github.com> Date: Mon, 29 Jan 2024 12:28:32 +0800 Subject: [PATCH 127/209] fix: close file gracefully in espsecure --- espsecure/__init__.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/espsecure/__init__.py b/espsecure/__init__.py index b4b50d632..3d805492e 100755 --- a/espsecure/__init__.py +++ b/espsecure/__init__.py @@ -11,6 +11,7 @@ import tempfile import zlib from collections import namedtuple +from io import IOBase from cryptography import exceptions from cryptography.hazmat.backends import default_backend @@ -1802,8 +1803,11 @@ def main(custom_commandline=None): finally: for arg_name in vars(args): obj = getattr(args, arg_name) - if isinstance(obj, OutFileType): + if isinstance(obj, (OutFileType, IOBase)): obj.close() + elif isinstance(obj, list): + for f in [o for o in obj if isinstance(o, IOBase)]: + f.close() def _main(): From f5bb8bcf7f8af10c8a3f7c0bf0981c9cc49978e2 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Mon, 22 Jan 2024 12:49:59 +0100 Subject: [PATCH 128/209] feat: Use ruff instead of flake8 and black both in pre-commit and CI --- .gitlab-ci.yml | 8 ++--- .pre-commit-config.yaml | 13 +++---- .ruff.toml | 59 ++++++++++++++++++++++++++++++++ espefuse/efuse/base_fields.py | 5 +-- espefuse/efuse/esp32c2/fields.py | 5 ++- esptool/bin_image.py | 2 +- esptool/cmds.py | 5 +-- setup.cfg | 27 --------------- setup.py | 5 +-- 9 files changed, 78 insertions(+), 51 deletions(-) create mode 100644 .ruff.toml delete mode 100644 setup.cfg diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2a193172b..423ddbf14 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -128,12 +128,12 @@ check_python_style: codequality: code_quality_report.json when: on_failure script: - # This step installs any 'dev' dependencies (ie flake8, Black) + # This step installs any 'dev' dependencies (ie ruff) # The runner should cache the downloads, so still quite fast. - pip install -e .[dev] --prefer-binary - - python -m flake8 --exit-zero --format gl-codeclimate --output-file code_quality_report.json - - python -m flake8 - - python -m black --check --diff . + - python -m ruff check --exit-zero --output-format=gitlab --output-file=code_quality_report.json + - python -m ruff check + - python -m ruff format .run_esptool: &run_esptool | esptool.py --help diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 04f91d000..bc3f02815 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1,13 +1,10 @@ repos: - - repo: https://github.com/PyCQA/flake8 - rev: 6.1.0 + - repo: https://github.com/astral-sh/ruff-pre-commit + rev: v0.1.14 hooks: - - id: flake8 - additional_dependencies: [flake8-import-order] - - repo: https://github.com/psf/black - rev: 23.11.0 - hooks: - - id: black + - id: ruff # Runs ruff linter (replaces flake8) + args: [--fix, --exit-non-zero-on-fix] # --fix for fixing errors + - id: ruff-format - repo: https://github.com/espressif/conventional-precommit-linter rev: v1.4.0 hooks: diff --git a/.ruff.toml b/.ruff.toml new file mode 100644 index 000000000..1a1d17fda --- /dev/null +++ b/.ruff.toml @@ -0,0 +1,59 @@ +# https://docs.astral.sh/ruff/settings/ +# Exclude a variety of commonly ignored directories. +exclude = [ + ".eggs", + ".git", + "__pycache__" +] + +line-length = 88 + +select = ['E', 'F', 'W'] +ignore = ["E203"] + +# Assume Python 3.7 +target-version = "py37" + +[per-file-ignores] + + +# tests often manipulate sys.path before importing the main tools, so ignore import order violations +"test/*.py" = ["E402"] + +# multiple spaces after ',' and long lines - used for visual layout of eFuse data +"espefuse/efuse/*/mem_definition.py" = ["E241", "E501"] +"espefuse/efuse/*/operations.py" = ["E241", "E501", "F401"] +"espefuse/efuse/*/fields.py" = ["E241", "E501"] + +# ignore long lines - used for RS encoding pairs +"test/test_modules.py" = ["E501"] + +# don't check for unused imports in __init__.py files +"__init__.py" = ["F401"] + +# allow definition from star imports in docs config +"docs/conf_common.py" = ["F405"] + + + +[lint] +# Enable Pyflakes (`F`) and a subset of the pycodestyle (`E`) codes by default. +# Unlike Flake8, Ruff doesn't enable pycodestyle warnings (`W`) or +# McCabe complexity (`C901`) by default. +select = ["E4", "E7", "E9", "F"] +ignore = [] + +# Allow fix for all enabled rules (when `--fix`) is provided. +fixable = ["ALL"] +unfixable = [] + +# Allow unused variables when underscore-prefixed. +dummy-variable-rgx = "^(_+|(_+[a-zA-Z0-9_]*[a-zA-Z0-9]+?))$" + + +# ruff-format hook configuration +[format] +quote-style = "double" +indent-style = "space" +docstring-code-format = true + diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index 8ad6616f9..13ce90b2c 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -58,8 +58,9 @@ def check_arg_value(efuse, new_value): elif efuse.efuse_type.startswith("bytes"): if new_value is None: raise esptool.FatalError( - "New value required for efuse '{}' " - "(given None)".format(efuse.name) + "New value required for efuse '{}' (given None)".format( + efuse.name + ) ) if len(new_value) * 8 != efuse.bitarray.len: raise esptool.FatalError( diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index cba599e63..bfbcae632 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -368,15 +368,14 @@ def print_field(e, new_value): class EfuseKeyPurposeField(EfuseField): + # fmt: off KEY_PURPOSES = [ - # fmt: off ("USER", 0, None), # User purposes (software-only use) ("XTS_AES_128_KEY", 1, None), # (whole 256bits) flash/PSRAM encryption ("XTS_AES_128_KEY_DERIVED_FROM_128_EFUSE_BITS", 2, None), # (lo 128bits) flash/PSRAM encryption ("SECURE_BOOT_DIGEST", 3, "DIGEST"), # (hi 128bits) Secure Boot key digest - # fmt: on - ] + ] # fmt: on KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] DIGEST_KEY_PURPOSES = [name[0] for name in KEY_PURPOSES if name[2] == "DIGEST"] diff --git a/esptool/bin_image.py b/esptool/bin_image.py index d260ef92a..7ce2204bd 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -1252,7 +1252,7 @@ def read_section_header(offs): nobits_secitons = [s for s in all_sections if s[1] == ELFFile.SEC_TYPE_NOBITS] # search for the string table section - if not (shstrndx * self.LEN_SEC_HEADER) in section_header_offsets: + if (shstrndx * self.LEN_SEC_HEADER) not in section_header_offsets: raise FatalError("ELF file has no STRTAB section at shstrndx %d" % shstrndx) _, sec_type, _, sec_size, sec_offs = read_section_header( shstrndx * self.LEN_SEC_HEADER diff --git a/esptool/cmds.py b/esptool/cmds.py index a12427112..29b0b3993 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -892,8 +892,9 @@ def get_key_from_value(dict, val): ESP8266V2FirmwareImage.IMAGE_V2_MAGIC, ]: raise FatalError( - "This is not a valid image " - "(invalid magic number: {:#x})".format(magic) + "This is not a valid image " "(invalid magic number: {:#x})".format( + magic + ) ) if args.chip == "auto": diff --git a/setup.cfg b/setup.cfg deleted file mode 100644 index 67c9fa70a..000000000 --- a/setup.cfg +++ /dev/null @@ -1,27 +0,0 @@ -[flake8] -exclude = .git,__pycache__,.eggs,build -ignore = - # multiple spaces before operator - used for visual indent of constants in some files - E221, - -per-file-ignores = - # tests often manipulate sys.path before importing the main tools, so ignore import order violations - test/*.py: E402, - - # multiple spaces after ',' and long lines - used for visual layout of eFuse data - espefuse/efuse/*/mem_definition.py: E241, E501, - espefuse/efuse/*/operations.py: E241, E501, F401, - espefuse/efuse/*/fields.py: E241, E501, - - # ignore long lines - used for RS encoding pairs - test/test_modules.py: E501, - - # don't check for unused imports in __init__.py files - __init__.py: F401, - - # allow definition from star imports in docs config - docs/conf_common.py: F405, - -# Compatibility with Black -max-line-length = 88 -extend-ignore = E203, W503, diff --git a/setup.py b/setup.py index 39d88e02c..dfa428c8d 100644 --- a/setup.py +++ b/setup.py @@ -108,12 +108,9 @@ def find_version(*file_paths): setup_requires=(["wheel"] if "bdist_wheel" in sys.argv else []), extras_require={ "dev": [ - "flake8>=3.2.0", - "flake8-import-order", - "flake8-gl-codeclimate", + "ruff>=0.1.14", "pyelftools", "coverage~=6.0", - "black", "pre-commit", "pytest", "pytest-rerunfailures", From 334e61622b4e0fa5dedb90f0e2f3be56d24d1f21 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Fri, 26 Jan 2024 13:35:11 +0100 Subject: [PATCH 129/209] docs(esptool): Reflect change from flake8 and black to ruff --- CONTRIBUTING.rst | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index 6b9d5536e..e15518f9f 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -85,24 +85,22 @@ To use the tool, first install ``pre-commit``. Then enable the ``pre-commit`` an $ python -m pip install pre-commit $ pre-commit install -t pre-commit -t commit-msg -On the first commit ``pre-commit`` will install the hooks, subsequent checks will be significantly faster. If an error is found an appropriate error message will be displayed. If the error was with ``black`` then the tool will fix them for you automatically. Review the changes and re-stage for commit if you are happy with them. +On the first commit ``pre-commit`` will install the hooks, subsequent checks will be significantly faster. If an error is found an appropriate error message will be displayed. Review the changes and re-stage for commit if you are happy with them. Conventional Commits """""""""""""""""""" ``esptool.py`` complies with the `Conventional Commits standard `_. Every commit message is checked with `Conventional Precommit Linter `_, ensuring it adheres to the standard. -Flake8 -"""""" -``esptool.py`` complies with `flake8 `_ style guide enforcement. +Ruff +"""" -Black -""""" +``esptool.py`` is `PEP8 ` compliant and enforces this style guide. For compliancy checking, we use `ruff `. +``Ruff`` also auto-format files in the same style as previously used ``black``. -All files should be formatted using the `Black `_ auto-formatter. -``Black``, ``flake8``, and ``Conventional Precommit Linter`` tools will be automatically run by ``pre-commit`` if that is configured. To check your code manually before submitting, run ``python -m flake8`` and ``black .`` (the tools are installed as part of the development requirements shown at the beginning of this document). +``Ruff`` and ``Conventional Precommit Linter`` tools will be automatically run by ``pre-commit`` if that is configured. To check your code manually before submitting, run ``python -m ruff`` (this tool is installed as part of the development requirements shown at the beginning of this document). When you submit a Pull Request, the GitHub Actions automated build system will run automated checks using these tools. From 50622b5d2b675f51564209933a70a8ce8ed726d6 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 30 Jan 2024 09:34:31 +0100 Subject: [PATCH 130/209] docs: Correct bootloader offsets Closes https://github.com/espressif/esptool/issues/953 --- docs/en/advanced-topics/boot-mode-selection.rst | 2 +- docs/en/esptool/advanced-commands.rst | 2 +- docs/en/esptool/flash-modes.rst | 2 +- docs/en/esptool/flashing-firmware.rst | 12 +++++++----- docs/en/troubleshooting.rst | 2 +- 5 files changed, 11 insertions(+), 9 deletions(-) diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index 56468ada2..24ba24349 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -2,7 +2,7 @@ {IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO8", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46"} -{IDF_TARGET_BOOTLOADER_OFFSET:default="0",esp32="1000", esp32s2="1000"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0", esp32="1000", esp32s2="1000", esp32p4="2000"} .. _boot-mode: diff --git a/docs/en/esptool/advanced-commands.rst b/docs/en/esptool/advanced-commands.rst index bfc9d2c0c..d19309497 100644 --- a/docs/en/esptool/advanced-commands.rst +++ b/docs/en/esptool/advanced-commands.rst @@ -1,4 +1,4 @@ -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000", esp32p4="0x2000"} .. _advanced-commands: diff --git a/docs/en/esptool/flash-modes.rst b/docs/en/esptool/flash-modes.rst index 37d3033b7..e7e10c406 100644 --- a/docs/en/esptool/flash-modes.rst +++ b/docs/en/esptool/flash-modes.rst @@ -1,4 +1,4 @@ -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000", esp32p4="0x2000"} {IDF_TARGET_FLASH_FREQ_F:default="80", esp32c2="60", esp32h2="48"} diff --git a/docs/en/esptool/flashing-firmware.rst b/docs/en/esptool/flashing-firmware.rst index 83392ebc1..6c4276b05 100644 --- a/docs/en/esptool/flashing-firmware.rst +++ b/docs/en/esptool/flashing-firmware.rst @@ -1,3 +1,5 @@ +{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000", esp32p4="0x2000"} + .. _flashing: Flashing Firmware @@ -42,10 +44,10 @@ It is also possible to assemble the command manually, please see the :ref:`espto ESP-IDF ^^^^^^^ -ESP-IDF outputs the full esptool command used for flashing after the build is finished:: +ESP-IDF outputs the full esptool command used for flashing after the build is finished, for example:: Project build complete. To flash, run this command: - python esptool.py -p (PORT) -b 460800 --before default_reset --after hard_reset --chip esp32 write_flash --flash_mode dio --flash_size detect --flash_freq 40m 0x1000 build/bootloader/bootloader.bin 0x8000 build/partition_table/partition-table.bin 0x10000 build/hello_world.bin + python esptool.py -p (PORT) -b 460800 --before default_reset --after hard_reset --chip {IDF_TARGET_PATH_NAME} write_flash --flash_mode dio --flash_size detect --flash_freq 40m {IDF_TARGET_BOOTLOADER_OFFSET} build/bootloader/bootloader.bin 0x8000 build/partition_table/partition-table.bin 0x10000 build/hello_world.bin or run 'idf.py -p (PORT) flash' Arduino @@ -56,11 +58,11 @@ The full esptool command is hidden from the user by default. To expose it, open PlatformIO ^^^^^^^^^^ -To do a verbose upload and see the exact esptool invocation, run ``pio run -v -t upload`` in the terminal. In the generated output, there is the full esptool command, e.g.: +To do a verbose upload and see the exact esptool invocation, run ``pio run -v -t upload`` in the terminal. In the generated output, there is the full esptool command, you will see something like: :: - “.../.platformio/penv/bin/python2.7” “.../.platformio/packages/tool-esptoolpy/esptool.py” --chip esp32 --port “/dev/cu.usbserial001” --baud 921600 --before default_reset --after hard_reset write_flash -z --flash_mode dio --flash_freq 40m --flash_size detect 0x1000 .../.platformio/packages/framework-arduinoespressif32/tools/sdk/bin/bootloader_dio_40m.bin 0x8000 .../project_folder/.pio/build/esp32doit-devkit-v1/partitions.bin 0xe000 .../.platformio/packages/framework-arduinoespressif32/tools/partitions/boot_app0.bin 0x10000 .pio/build/esp32doit-devkit-v1/firmware.bin + “.../.platformio/penv/bin/python2.7” “.../.platformio/packages/tool-esptoolpy/esptool.py” --chip {IDF_TARGET_PATH_NAME} --port “/dev/cu.usbserial001” --baud 921600 --before default_reset --after hard_reset write_flash -z --flash_mode dio --flash_freq 40m --flash_size detect {IDF_TARGET_BOOTLOADER_OFFSET} .../.platformio/packages/framework-arduinoespressif32/tools/sdk/bin/bootloader_dio_40m.bin 0x8000 .../project_folder/.pio/build/esp32doit-devkit-v1/partitions.bin 0xe000 .../.platformio/packages/framework-arduinoespressif32/tools/partitions/boot_app0.bin 0x10000 .pio/build/esp32doit-devkit-v1/firmware.bin Flashing @@ -70,7 +72,7 @@ If you split the output, you’ll find the ``write_flash`` command with a list o Change ``PORT`` to the name of :ref:`actually used serial port ` and run the command. A successful flash looks like this:: - $ python esptool.py -p /dev/tty.usbserial-0001 -b 460800 --before default_reset --after hard_reset --chip esp32 write_flash --flash_mode dio --flash_size detect --flash_freq 40m 0x1000 build/bootloader/bootloader.bin 0x8000 build/partition_table/partition-table.bin 0x10000 build/hello_world.bin + $ python esptool.py -p /dev/tty.usbserial-0001 -b 460800 --before default_reset --after hard_reset --chip {IDF_TARGET_PATH_NAME} write_flash --flash_mode dio --flash_size detect --flash_freq 40m {IDF_TARGET_BOOTLOADER_OFFSET} build/bootloader/bootloader.bin 0x8000 build/partition_table/partition-table.bin 0x10000 build/hello_world.bin esptool.py v3.2-dev Serial port /dev/tty.usbserial-0001 Connecting......... diff --git a/docs/en/troubleshooting.rst b/docs/en/troubleshooting.rst index 5d3e3dbf3..820bfa297 100644 --- a/docs/en/troubleshooting.rst +++ b/docs/en/troubleshooting.rst @@ -1,4 +1,4 @@ -{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000", esp32p4="0x2000"} .. _troubleshooting: From df4dc50377eaa6b2130d8e260b210c862c93e3a5 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 30 Jan 2024 10:05:36 +0100 Subject: [PATCH 131/209] refactor(style): Comply with black>=24.0.0 --- .gitlab-ci.yml | 1 + esptool/cmds.py | 16 ++++++++++------ esptool/loader.py | 12 +++++++----- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 423ddbf14..0fe401bd1 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -41,6 +41,7 @@ cache: - host_test dependencies: [] before_script: + - pip install --upgrade pip - pip install -e .[dev] --prefer-binary version_check: diff --git a/esptool/cmds.py b/esptool/cmds.py index 29b0b3993..09a97c4bd 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -815,9 +815,11 @@ def get_key_from_value(dict, val): print( "Checksum: {:#02x} ({})".format( image.checksum, - "valid" - if image.checksum == calc_checksum - else "invalid - calculated {:02x}".format(calc_checksum), + ( + "valid" + if image.checksum == calc_checksum + else "invalid - calculated {:02x}".format(calc_checksum) + ), ) ) try: @@ -941,9 +943,11 @@ def get_key_from_value(dict, val): print( "Checksum: {:02x} ({})".format( image.checksum, - "valid" - if image.checksum == calc_checksum - else "invalid - calculated {:02x}".format(calc_checksum), + ( + "valid" + if image.checksum == calc_checksum + else "invalid - calculated {:02x}".format(calc_checksum) + ), ) ) try: diff --git a/esptool/loader.py b/esptool/loader.py index ee74a78ae..3a03b0f5a 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -1651,12 +1651,14 @@ def __str__(self): while len(s) > 0: line = s[:16] ascii_line = "".join( - c - if ( - c == " " - or (c in string.printable and c not in string.whitespace) + ( + c + if ( + c == " " + or (c in string.printable and c not in string.whitespace) + ) + else "." ) - else "." for c in line.decode("ascii", "replace") ) s = s[16:] From 0796576df97bcfcbbeac43be03da9d9fb240fafe Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Thu, 1 Feb 2024 09:21:56 +0100 Subject: [PATCH 132/209] ci: Use ruff instead of flake8 and black in github CI --- .github/workflows/test_esptool.yml | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/.github/workflows/test_esptool.yml b/.github/workflows/test_esptool.yml index 0287eae76..d0e6e84f5 100644 --- a/.github/workflows/test_esptool.yml +++ b/.github/workflows/test_esptool.yml @@ -69,10 +69,8 @@ jobs: - name: Checkout uses: actions/checkout@master - - name: Lint with flake8 + - name: Lint and format with ruff run: | pip install --extra-index-url https://dl.espressif.com/pypi -e .[dev] - python -m flake8 - - - name: Check formatting with Black - uses: psf/black@stable + python -m ruff check + python -m ruff format From 65a3b5db279779f9874e2273928b2b5c51262a00 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Tue, 30 Jan 2024 13:32:23 +0100 Subject: [PATCH 133/209] fix: ROM doesn't attach in-package flash chips --- esptool/__init__.py | 30 ++++++++++++++++++++++++------ esptool/targets/esp32.py | 17 +++++++++++++++++ 2 files changed, 41 insertions(+), 6 deletions(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 2227f5762..021ce08f5 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -779,6 +779,13 @@ def add_spi_flash_subparsers( "Keeping initial baud rate %d" % initial_baud ) + def _define_spi_conn(spi_connection): + """Prepare SPI configuration string and value for flash_spi_attach()""" + clk, q, d, hd, cs = spi_connection + spi_config_txt = f"CLK:{clk}, Q:{q}, D:{d}, HD:{hd}, CS:{cs}" + value = (hd << 24) | (cs << 18) | (d << 12) | (q << 6) | clk + return spi_config_txt, value + # Override the common SPI flash parameter stuff if configured to do so if hasattr(args, "spi_connection") and args.spi_connection is not None: spi_config = args.spi_connection @@ -790,15 +797,26 @@ def add_spi_flash_subparsers( esp.check_spi_connection(args.spi_connection) # Encode the pin numbers as a 32-bit integer with packed 6-bit values, # the same way the ESP ROM takes them - clk, q, d, hd, cs = args.spi_connection - spi_config = f"CLK:{clk}, Q:{q}, D:{d}, HD:{hd}, CS:{cs}" - value = (hd << 24) | (cs << 18) | (d << 12) | (q << 6) | clk + spi_config, value = _define_spi_conn(args.spi_connection) print(f"Configuring SPI flash mode ({spi_config})...") esp.flash_spi_attach(value) elif args.no_stub: - print("Enabling default SPI flash mode...") - # ROM loader doesn't enable flash unless we explicitly do it - esp.flash_spi_attach(0) + if esp.CHIP_NAME != "ESP32" or esp.secure_download_mode: + print("Enabling default SPI flash mode...") + # ROM loader doesn't enable flash unless we explicitly do it + esp.flash_spi_attach(0) + else: + # ROM doesn't attach in-package flash chips + spi_chip_pads = esp.get_chip_spi_pads() + spi_config_txt, value = _define_spi_conn(spi_chip_pads) + if spi_chip_pads != (0, 0, 0, 0, 0): + print( + "Attaching flash from eFuses' SPI pads configuration" + f"({spi_config_txt})..." + ) + else: + print("Enabling default SPI flash mode...") + esp.flash_spi_attach(value) # XMC chip startup sequence XMC_VENDOR_ID = 0x20 diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index 690fdbb91..d3ae70bb8 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -36,6 +36,9 @@ class ESP32ROM(ESPLoader): SPI_MISO_DLEN_OFFS = 0x2C EFUSE_RD_REG_BASE = 0x3FF5A000 + EFUSE_BLK0_RDATA3_REG_OFFS = EFUSE_RD_REG_BASE + 0x00C + EFUSE_BLK0_RDATA5_REG_OFFS = EFUSE_RD_REG_BASE + 0x014 + EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE + 0x18 EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 7 # EFUSE_RD_DISABLE_DL_ENCRYPT @@ -276,6 +279,20 @@ def get_chip_features(self): return features + def get_chip_spi_pads(self): + """Read chip spi pad config + return: clk, q, d, hd, cd + """ + efuse_blk0_rdata5 = self.read_reg(self.EFUSE_BLK0_RDATA5_REG_OFFS) + spi_pad_clk = efuse_blk0_rdata5 & 0x1F + spi_pad_q = (efuse_blk0_rdata5 >> 5) & 0x1F + spi_pad_d = (efuse_blk0_rdata5 >> 10) & 0x1F + spi_pad_cs = (efuse_blk0_rdata5 >> 15) & 0x1F + + efuse_blk0_rdata3_reg = self.read_reg(self.EFUSE_BLK0_RDATA3_REG_OFFS) + spi_pad_hd = (efuse_blk0_rdata3_reg >> 4) & 0x1F + return spi_pad_clk, spi_pad_q, spi_pad_d, spi_pad_hd, spi_pad_cs + def read_efuse(self, n): """Read the nth word of the ESP3x EFUSE region.""" return self.read_reg(self.EFUSE_RD_REG_BASE + (4 * n)) From c070031b43984c7713a7cfead39cf75df24431bc Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Tue, 30 Jan 2024 10:38:56 +0100 Subject: [PATCH 134/209] feat(err_defs): Add ROM bootloader flash error definitions Closes https://github.com/espressif/esptool/issues/952 --- esptool/util.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/esptool/util.py b/esptool/util.py index 71bf5da17..152761885 100644 --- a/esptool/util.py +++ b/esptool/util.py @@ -142,6 +142,12 @@ def WithResult(message, result): 0x109: "CRC or checksum was invalid", 0x10A: "Version was invalid", 0x10B: "MAC address was invalid", + 0x6001: "Flash operation failed", + 0x6002: "Flash operation timed out", + 0x6003: "Flash not initialised properly", + 0x6004: "Operation not supported by the host SPI bus", + 0x6005: "Operation not supported by the flash chip", + 0x6006: "Can't write, protection enabled", # Flasher stub error codes 0xC000: "Bad data length", 0xC100: "Bad data checksum", From 7e034ca3bb2d9c529cddc2bd74ad4d4a54c378e5 Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 5 Feb 2024 14:37:09 +0100 Subject: [PATCH 135/209] ci(pyinstaller): Limit version to v5.3.12 PyInstaller >=6.0 seems to cause significantly more false positives from antivirus programs Closes https://github.com/espressif/esptool/issues/944 --- .github/workflows/build_esptool.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index 1e3f4a0b9..26c2a5389 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -44,9 +44,10 @@ jobs: with: python-version: 3.8 - name: Install dependencies + # PyInstaller >=6.0 results in significantly more antivirus false positives run: | python -m pip install --upgrade pip - pip install pyinstaller + pip install pyinstaller==5.13.2 pip install --user -e . - name: Build with PyInstaller run: | From a9f06039c5fbda6c3a4b6f31289e2129b9ee179a Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Mon, 5 Feb 2024 16:40:58 +0100 Subject: [PATCH 136/209] ci(changelog_template): Add a reminder about virus scanning --- ci/gh_changelog_template.md.j2 | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/ci/gh_changelog_template.md.j2 b/ci/gh_changelog_template.md.j2 index a58bce964..5dc2df5db 100644 --- a/ci/gh_changelog_template.md.j2 +++ b/ci/gh_changelog_template.md.j2 @@ -20,3 +20,9 @@ {% endfor %} Thanks to , and others for contributing to this release! + +# Results of checking the release against common anti-virus SW + + + +The failures are probably false positives. You can mark esptool as safe in your anti-virus SW, or [install esptool from source](https://docs.espressif.com/projects/esptool/en/latest/installation.html). From ebb8b80d6d88ed865338b73c4c414d2b1cc1b693 Mon Sep 17 00:00:00 2001 From: "Francisco Blas (klondike) Izquierdo Riera" Date: Sun, 28 Jan 2024 05:40:55 +0100 Subject: [PATCH 137/209] feat(espefuse): Allow the espefuse.py to work when coding scheme == 3 Signed-off-by: Francisco Blas (klondike) Izquierdo Riera Closes https://github.com/espressif/esptool/pull/950 --- docs/en/espefuse/index.rst | 2 +- espefuse/efuse/esp32/emulate_efuse_controller.py | 6 +++++- espefuse/efuse/esp32/fields.py | 6 +++++- esptool/targets/esp32.py | 9 ++++++--- test/test_espefuse.py | 13 +++++++++++++ 5 files changed, 30 insertions(+), 6 deletions(-) diff --git a/docs/en/espefuse/index.rst b/docs/en/espefuse/index.rst index 7c8c40c88..9045eb6e5 100644 --- a/docs/en/espefuse/index.rst +++ b/docs/en/espefuse/index.rst @@ -76,7 +76,7 @@ The coding scheme helps the eFuse controller to detect an error of the eFuse blo .. only:: esp32 - * ``None`` no need any special encoding data. BLOCK0. + * ``None`` no need any special encoding data. BLOCK0 is always None. * ``3/4``, requires encoding data. The BLOCK length is reduced from 256 bits to 192 bits. * ``Repeat`` not supported by this tool and IDF. The BLOCK length is reduced from 256 bits to 128 bits. diff --git a/espefuse/efuse/esp32/emulate_efuse_controller.py b/espefuse/efuse/esp32/emulate_efuse_controller.py index da7cd44d6..5b5882f36 100644 --- a/espefuse/efuse/esp32/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32/emulate_efuse_controller.py @@ -75,10 +75,14 @@ def handle_writing_event(self, addr, value): self.save_to_file() def read_raw_coding_scheme(self): - return ( + coding_scheme = ( self.read_efuse(self.REGS.EFUSE_CODING_SCHEME_WORD) & self.REGS.EFUSE_CODING_SCHEME_MASK ) + if coding_scheme == self.REGS.CODING_SCHEME_NONE_RECOVERY: + return self.REGS.CODING_SCHEME_NONE + else: + return coding_scheme def write_raw_coding_scheme(self, value): self.write_efuse( diff --git a/espefuse/efuse/esp32/fields.py b/espefuse/efuse/esp32/fields.py index 7ca5fc356..7a9c9d46a 100644 --- a/espefuse/efuse/esp32/fields.py +++ b/espefuse/efuse/esp32/fields.py @@ -157,10 +157,14 @@ def __getitem__(self, efuse_name): raise KeyError def read_coding_scheme(self): - self.coding_scheme = ( + coding_scheme = ( self.read_efuse(self.REGS.EFUSE_CODING_SCHEME_WORD) & self.REGS.EFUSE_CODING_SCHEME_MASK ) + if coding_scheme == self.REGS.CODING_SCHEME_NONE_RECOVERY: + self.coding_scheme = self.REGS.CODING_SCHEME_NONE + else: + self.coding_scheme = coding_scheme def print_status_regs(self): print("") diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index d3ae70bb8..09804eaec 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -272,9 +272,12 @@ def get_chip_features(self): coding_scheme = word6 & 0x3 features += [ "Coding Scheme %s" - % {0: "None", 1: "3/4", 2: "Repeat (UNSUPPORTED)", 3: "Invalid"}[ - coding_scheme - ] + % { + 0: "None", + 1: "3/4", + 2: "Repeat (UNSUPPORTED)", + 3: "None (may contain encoding data)", + }[coding_scheme] ] return features diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 531aa6f77..514be6e8c 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -113,6 +113,9 @@ def get_esptool(self): def _set_34_coding_scheme(self): self.espefuse_py("burn_efuse CODING_SCHEME 1") + def _set_none_recovery_coding_scheme(self): + self.espefuse_py("burn_efuse CODING_SCHEME 3") + def check_data_block_in_log( self, log, file_path, repeat=1, reverse_order=False, offset=0 ): @@ -1683,6 +1686,16 @@ def test_burn_bit_with_34_coding_scheme(self): ret_code=2, ) + @pytest.mark.skipif(arg_chip != "esp32", reason="ESP32-only") + def test_burn_bit_with_none_recovery_coding_scheme(self): + self._set_none_recovery_coding_scheme() + self.espefuse_py("burn_bit BLOCK3 0 1 2 4 8 16 32 64 96 128 160 192 224 255") + self.espefuse_py( + "summary", + check_msg="17 01 01 00 01 00 00 00 01 00 00 00 01 00 00 " + "00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 80", + ) + @pytest.mark.skipif( arg_chip != "esp32", reason="Tests are only for esp32. (TODO: add for all chips)" From 9c0d990e69d809db9a1a3bfdcd4da035f1c45c8a Mon Sep 17 00:00:00 2001 From: "radim.karnis" Date: Wed, 7 Feb 2024 13:54:55 +0100 Subject: [PATCH 138/209] ci(gh_actions): Start build jobs by platform, specify runners --- .github/workflows/build_esptool.yml | 33 +++++++++++++++++------------ 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index 26c2a5389..b5efd34db 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -4,30 +4,35 @@ on: [push, pull_request] jobs: build-esptool-binaries: - name: Build esptool binaries for ${{ matrix.os }} - runs-on: ${{ matrix.os }} + name: Build esptool binaries for ${{ matrix.platform }} + runs-on: ${{ matrix.RUN_ON }} strategy: matrix: - os: [macos-latest, ubuntu-20.04, windows-latest, ARM, ARM64] + platform: [macos, windows, linux-amd64, linux-arm32, linux-arm64] include: - - os: macos-latest + - platform: macos TARGET: macos SEPARATOR: ':' - - os: ubuntu-20.04 - TARGET: linux-amd64 - SEPARATOR: ':' - - os: windows-latest + RUN_ON: macos-latest + - platform: windows TARGET: win64 EXTEN: .exe SEPARATOR: ';' - - os: ARM + RUN_ON: windows-latest + - platform: linux-amd64 + TARGET: linux-amd64 + SEPARATOR: ':' + RUN_ON: ubuntu-20.04 + - platform: linux-arm32 CONTAINER: python:3.8-bullseye - TARGET: arm + TARGET: linux-arm32 SEPARATOR: ':' - - os: ARM64 + RUN_ON: [ARM, self-hosted, linux] + - platform: linux-arm64 CONTAINER: python:3.8-bullseye - TARGET: arm64 + TARGET: linux-arm64 SEPARATOR: ':' + RUN_ON: [ARM64, self-hosted, linux] container: ${{ matrix.CONTAINER }} # use python container on ARM env: DISTPATH: esptool-${{ matrix.TARGET }} @@ -39,7 +44,7 @@ jobs: uses: actions/checkout@master - name: Set up Python 3.8 # Skip setting python on ARM because of missing compatibility: https://github.com/actions/setup-python/issues/108 - if: matrix.os != 'ARM' && matrix.os != 'ARM64' + if: matrix.platform != 'linux-arm32' && matrix.platform != 'linux-arm64' uses: actions/setup-python@master with: python-version: 3.8 @@ -56,7 +61,7 @@ jobs: pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico espsecure.py pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico esp_rfc2217_server.py - name: Sign binaries - if: matrix.os == 'windows-latest' && github.event_name != 'pull_request' + if: matrix.platform == 'windows' && github.event_name != 'pull_request' env: CERTIFICATE: ${{ secrets.CERTIFICATE }} CERTIFICATE_PASSWORD: ${{ secrets.CERTIFICATE_PASSWORD }} From 4b08466c8ac9ef2c4149447b8f90c611be01a959 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Mon, 12 Feb 2024 16:28:43 +0100 Subject: [PATCH 139/209] docs(sphinx-lint): Add sphinx-lint to pre-commit, GH and GL pipelines --- .github/workflows/test_esptool.yml | 5 ++--- .gitlab-ci.yml | 12 ++---------- .pre-commit-config.yaml | 6 ++++++ setup.py | 1 - 4 files changed, 10 insertions(+), 14 deletions(-) diff --git a/.github/workflows/test_esptool.yml b/.github/workflows/test_esptool.yml index d0e6e84f5..e464e9559 100644 --- a/.github/workflows/test_esptool.yml +++ b/.github/workflows/test_esptool.yml @@ -69,8 +69,7 @@ jobs: - name: Checkout uses: actions/checkout@master - - name: Lint and format with ruff + - name: Run pre-commit hooks run: | pip install --extra-index-url https://dl.espressif.com/pypi -e .[dev] - python -m ruff check - python -m ruff format + pre-commit run --all-files diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0fe401bd1..eeb5402f3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -119,22 +119,14 @@ host_tests_hsm: script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espsecure_hsm.py -check_python_style: +run_pre_commit_hooks: stage: test image: python:3.7-bullseye tags: - host_test - artifacts: - reports: - codequality: code_quality_report.json - when: on_failure script: - # This step installs any 'dev' dependencies (ie ruff) - # The runner should cache the downloads, so still quite fast. - pip install -e .[dev] --prefer-binary - - python -m ruff check --exit-zero --output-format=gitlab --output-file=code_quality_report.json - - python -m ruff check - - python -m ruff format + - pre-commit run --all-files .run_esptool: &run_esptool | esptool.py --help diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index bc3f02815..d5d84e8a3 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -5,6 +5,12 @@ repos: - id: ruff # Runs ruff linter (replaces flake8) args: [--fix, --exit-non-zero-on-fix] # --fix for fixing errors - id: ruff-format + - repo: https://github.com/sphinx-contrib/sphinx-lint + rev: v0.6.8 + hooks: + - id: sphinx-lint + name: Lint RST files in docs folder using Sphinx Lint + files: ^((docs/en)/.*\.(rst|inc))|CONTRIBUTING.rst$ - repo: https://github.com/espressif/conventional-precommit-linter rev: v1.4.0 hooks: diff --git a/setup.py b/setup.py index dfa428c8d..2e5fa78e9 100644 --- a/setup.py +++ b/setup.py @@ -108,7 +108,6 @@ def find_version(*file_paths): setup_requires=(["wheel"] if "bdist_wheel" in sys.argv else []), extras_require={ "dev": [ - "ruff>=0.1.14", "pyelftools", "coverage~=6.0", "pre-commit", From a69d5b6f2a00bdbad74737b092d7ca876215d81e Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Mon, 5 Feb 2024 14:35:12 +0100 Subject: [PATCH 140/209] docs(sphinx-lint): Fix issues reported by sphinx-lint before adding it to pre-commit --- CONTRIBUTING.rst | 7 +- docs/en/espefuse/burn-bit-cmd.rst | 4 +- docs/en/espefuse/burn-block-data-cmd.rst | 2 +- docs/en/espefuse/burn-custom-mac-cmd.rst | 22 +-- docs/en/espefuse/burn-key-cmd.rst | 34 ++--- docs/en/espefuse/burn-key-digest-cmd.rst | 40 +++--- docs/en/espefuse/check-error-cmd.rst | 2 +- docs/en/espefuse/dump-cmd.rst | 3 +- docs/en/espefuse/inc/summary_ESP32-C2.rst | 30 ++-- docs/en/espefuse/inc/summary_ESP32-C3.rst | 74 +++++----- docs/en/espefuse/inc/summary_ESP32-C6.rst | 108 +++++++------- docs/en/espefuse/inc/summary_ESP32-H2.rst | 104 +++++++------- docs/en/espefuse/inc/summary_ESP32-P4.rst | 135 +++++++++--------- docs/en/espefuse/inc/summary_ESP32-S2.rst | 80 +++++------ docs/en/espefuse/inc/summary_ESP32-S3.rst | 86 +++++------ docs/en/espefuse/inc/summary_ESP32.rst | 32 ++--- docs/en/espefuse/index.rst | 4 +- .../espefuse/read-write-protections-cmd.rst | 4 +- docs/en/espefuse/set-flash-voltage-cmd.rst | 10 +- docs/en/esptool/serial-connection.rst | 6 +- 20 files changed, 395 insertions(+), 392 deletions(-) diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index e15518f9f..a9eb83104 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -96,7 +96,7 @@ Conventional Commits Ruff """" -``esptool.py`` is `PEP8 ` compliant and enforces this style guide. For compliancy checking, we use `ruff `. +``esptool.py`` is `PEP8 `_ compliant and enforces this style guide. For compliancy checking, we use `ruff `_. ``Ruff`` also auto-format files in the same style as previously used ``black``. @@ -104,6 +104,11 @@ Ruff When you submit a Pull Request, the GitHub Actions automated build system will run automated checks using these tools. +Shinx-lint +"""""""""" + +The documentation is checked for stylistic and formal issues by ``sphinx-lint``. + Automated Integration Tests ^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/espefuse/burn-bit-cmd.rst b/docs/en/espefuse/burn-bit-cmd.rst index 13f22ede6..11b180bf4 100644 --- a/docs/en/espefuse/burn-bit-cmd.rst +++ b/docs/en/espefuse/burn-bit-cmd.rst @@ -31,7 +31,7 @@ Burning bits to BLOCK2: Check all blocks for burn... idx, BLOCK_NAME, Conclusion [02] BLOCK2 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -65,7 +65,7 @@ Burning In Multiple Blocks idx, BLOCK_NAME, Conclusion [02] BLOCK2 is empty, will burn the new value [03] BLOCK3 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN diff --git a/docs/en/espefuse/burn-block-data-cmd.rst b/docs/en/espefuse/burn-block-data-cmd.rst index 333c5db84..0b0951960 100644 --- a/docs/en/espefuse/burn-block-data-cmd.rst +++ b/docs/en/espefuse/burn-block-data-cmd.rst @@ -31,7 +31,7 @@ Optional arguments: Check all blocks for burn... idx, BLOCK_NAME, Conclusion [03] BLOCK3 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN diff --git a/docs/en/espefuse/burn-custom-mac-cmd.rst b/docs/en/espefuse/burn-custom-mac-cmd.rst index 3ccebfae6..fe1ea178a 100644 --- a/docs/en/espefuse/burn-custom-mac-cmd.rst +++ b/docs/en/espefuse/burn-custom-mac-cmd.rst @@ -35,7 +35,7 @@ If ``CUSTOM_MAC`` is placed in an eFuse block with a coding scheme and already h Check all blocks for burn... idx, BLOCK_NAME, Conclusion [03] BLOCK3 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -47,12 +47,12 @@ If ``CUSTOM_MAC`` is placed in an eFuse block with a coding scheme and already h > espefuse.py summary ... MAC_VERSION (BLOCK3): Version of the MAC field = Custom MAC in BLOCK3 R/W (0x01) - CUSTOM_MAC (BLOCK3): Custom MAC - = 48:63:92:15:72:16 (CRC 0x75 OK) R/W + CUSTOM_MAC (BLOCK3): Custom MAC + = 48:63:92:15:72:16 (CRC 0x75 OK) R/W CUSTOM_MAC_CRC (BLOCK3): CRC of custom MAC = 117 R/W (0x75) ... - BLOCK3 (BLOCK3): Variable Block 3 - = 75 48 63 92 15 72 16 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 R/W + BLOCK3 (BLOCK3): Variable Block 3 + = 75 48 63 92 15 72 16 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 R/W .. only:: esp32c2 @@ -75,7 +75,7 @@ If ``CUSTOM_MAC`` is placed in an eFuse block with a coding scheme and already h (to write): 0x0400000000000000 (coding scheme = NONE) [01] BLOCK1 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -88,8 +88,8 @@ If ``CUSTOM_MAC`` is placed in an eFuse block with a coding scheme and already h > espefuse.py summary ... CUSTOM_MAC_USED (BLOCK0) Enable CUSTOM_MAC programming = True R/W (0b1) - CUSTOM_MAC (BLOCK1) Custom MAC addr - = 48:63:92:15:72:16 (OK) R/W + CUSTOM_MAC (BLOCK1) Custom MAC addr + = 48:63:92:15:72:16 (OK) R/W .. only:: esp32c3 or esp32s2 or esp32s3 @@ -105,7 +105,7 @@ If ``CUSTOM_MAC`` is placed in an eFuse block with a coding scheme and already h Check all blocks for burn... idx, BLOCK_NAME, Conclusion [03] BLOCK_USR_DATA is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -116,5 +116,5 @@ If ``CUSTOM_MAC`` is placed in an eFuse block with a coding scheme and already h > espefuse.py summary ... - CUSTOM_MAC (BLOCK3) Custom MAC Address - = 48:63:92:15:72:16 (OK) R/W \ No newline at end of file + CUSTOM_MAC (BLOCK3) Custom MAC Address + = 48:63:92:15:72:16 (OK) R/W diff --git a/docs/en/espefuse/burn-key-cmd.rst b/docs/en/espefuse/burn-key-cmd.rst index ebaa8ebd6..92922519e 100644 --- a/docs/en/espefuse/burn-key-cmd.rst +++ b/docs/en/espefuse/burn-key-cmd.rst @@ -78,7 +78,7 @@ Optional arguments: .. only:: esp32h2 - {IDF_TARGET_NAME} has the ECDSA accelerator for signature purposes and supports private keys based on the NIST192p or NIST256p curve. These two commands below can be used to generate such keys (``PEM`` file). The ``burn_key`` command with the ``ECDSA_KEY`` purpose takes the ``PEM`` file and writes the private key into a eFuse block. The key is written to the block in reverse byte order. + {IDF_TARGET_NAME} has the ECDSA accelerator for signature purposes and supports private keys based on the NIST192p or NIST256p curve. These two commands below can be used to generate such keys (``PEM`` file). The ``burn_key`` command with the ``ECDSA_KEY`` purpose takes the ``PEM`` file and writes the private key into a eFuse block. The key is written to the block in reverse byte order. For NIST192p, the private key is 192 bits long, so 8 padding bytes ("0x00") are added. @@ -166,7 +166,7 @@ Usage .. code-block:: none - > espefuse.py burn_key flash_encryption 256bit_fe_key.bin + > espefuse.py burn_key flash_encryption 256bit_fe_key.bin === Run "burn_key" command === Sensitive data will be hidden (see --show-sensitive-info) @@ -177,13 +177,13 @@ Usage Disabling write to key block Burn keys in efuse blocks. - The key block will be read and write protected + The key block will be read and write protected Check all blocks for burn... idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value [01] BLOCK1 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -196,15 +196,15 @@ Usage > espefuse.py summary ... - BLOCK1 (BLOCK1): Flash encryption key - = ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? -/- + BLOCK1 (BLOCK1): Flash encryption key + = ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? -/- Byte order for flash encryption key is reversed. Content of flash encryption key file ("256bit_fe_key.bin"): .. code-block:: none 0001 0203 0405 0607 0809 0a0b 0c0d 0e0f 1011 1213 1415 1617 1819 1a1b 1c1d 1e1f - + When the ``no protection`` option is used then you can see the burned key: .. code-block:: none @@ -219,12 +219,12 @@ Usage Key is left unprotected as per --no-protect-key argument. Burn keys in efuse blocks. - The key block will left readable and writeable (due to --no-protect-key) + The key block will left readable and writeable (due to --no-protect-key) Check all blocks for burn... idx, BLOCK_NAME, Conclusion [01] BLOCK1 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -236,8 +236,8 @@ Usage > espefuse.py summary ... - BLOCK1 (BLOCK1): Flash encryption key - = 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 R/W + BLOCK1 (BLOCK1): Flash encryption key + = 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 R/W .. only:: esp32s2 or esp32s3 @@ -280,7 +280,7 @@ Usage [00] BLOCK0 is empty, will burn the new value [04] BLOCK_KEY0 is empty, will burn the new value [05] BLOCK_KEY1 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -297,12 +297,12 @@ Usage ... BLOCK_KEY0 (BLOCK4) Purpose: XTS_AES_256_KEY_1 - Encryption key0 or user data - = 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 R/- + Encryption key0 or user data + = 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 R/- BLOCK_KEY1 (BLOCK5) Purpose: XTS_AES_256_KEY_2 - Encryption key1 or user data - = 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 R/- + Encryption key1 or user data + = 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 R/- .. only:: esp32c2 @@ -336,7 +336,7 @@ Usage idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value [03] BLOCK_KEY0 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN diff --git a/docs/en/espefuse/burn-key-digest-cmd.rst b/docs/en/espefuse/burn-key-digest-cmd.rst index 1a6e50971..4402a8c92 100644 --- a/docs/en/espefuse/burn-key-digest-cmd.rst +++ b/docs/en/espefuse/burn-key-digest-cmd.rst @@ -3,7 +3,7 @@ Burn key Digest =============== -The ``espefuse.py burn_key_digest`` command parses a RSA public key and burns the digest to eFuse block for use with `Secure Boot V2 `_. +The ``espefuse.py burn_key_digest`` command parses a RSA public key and burns the digest to eFuse block for use with `Secure Boot V2 `_. Positional arguments: @@ -11,7 +11,7 @@ Positional arguments: :not esp32 and not esp32c2: - ``block`` - Name of key block. - ``Keyfile``. Key file to digest (PEM format). - :not esp32 and not esp32c2: - ``Key purpose``. The purpose of this key [``SECURE_BOOT_DIGEST0``, ``SECURE_BOOT_DIGEST1``, ``SECURE_BOOT_DIGEST2``]. + :not esp32 and not esp32c2: - ``Key purpose``. The purpose of this key [``SECURE_BOOT_DIGEST0``, ``SECURE_BOOT_DIGEST1``, ``SECURE_BOOT_DIGEST2``]. .. only:: not esp32 and not esp32c2 @@ -55,7 +55,7 @@ Usage idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value [02] BLOCK2 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -66,8 +66,8 @@ Usage > espefuse.py summary ... - BLOCK2 (BLOCK2): Secure boot key - = a2 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/- + BLOCK2 (BLOCK2): Secure boot key + = a2 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/- .. only:: esp32c2 @@ -75,7 +75,7 @@ Usage .. code-block:: none - > espefuse.py burn_key_digest secure_boot_v2_ecdsa192.pem + > espefuse.py burn_key_digest secure_boot_v2_ecdsa192.pem === Run "burn_key_digest" command === Sensitive data will be hidden (see --show-sensitive-info) @@ -87,7 +87,7 @@ Usage idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value [03] BLOCK_KEY0 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -97,18 +97,18 @@ Usage Successful > espefuse.py summary - ... + ... XTS_KEY_LENGTH_256 (BLOCK0) Flash encryption key length = 128 bits key R/W (0b0) ... BLOCK_KEY0 (BLOCK3) BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryp - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 c2 bd 9c 1a b4 b7 44 22 59 c6 d3 12 0b 79 1f R/- - tion - BLOCK_KEY0_LOW_128 (BLOCK3) BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/- - Encryption + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 c2 bd 9c 1a b4 b7 44 22 59 c6 d3 12 0b 79 1f R/- + tion + BLOCK_KEY0_LOW_128 (BLOCK3) BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/- + Encryption BLOCK_KEY0_HI_128 (BLOCK3) BLOCK_KEY0 - higher 128-bits. 128-bits key of Secu - = 02 c2 bd 9c 1a b4 b7 44 22 59 c6 d3 12 0b 79 1f R/- - re Boot. + = 02 c2 bd 9c 1a b4 b7 44 22 59 c6 d3 12 0b 79 1f R/- + re Boot. .. only:: esp32c3 or esp32s2 or esp32s3 @@ -143,7 +143,7 @@ Usage [04] BLOCK_KEY0 is empty, will burn the new value [05] BLOCK_KEY1 is empty, will burn the new value [06] BLOCK_KEY2 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -162,13 +162,13 @@ Usage ... BLOCK_KEY0 (BLOCK4) Purpose: SECURE_BOOT_DIGEST0 - Encryption key0 or user data - = a2 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/- + Encryption key0 or user data + = a2 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/- BLOCK_KEY1 (BLOCK5) Purpose: SECURE_BOOT_DIGEST1 - Encryption key1 or user data + Encryption key1 or user data = a3 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/- BLOCK_KEY2 (BLOCK6) Purpose: SECURE_BOOT_DIGEST2 - Encryption key2 or user data + Encryption key2 or user data = a4 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/- diff --git a/docs/en/espefuse/check-error-cmd.rst b/docs/en/espefuse/check-error-cmd.rst index 8d3a56003..0723adf2c 100644 --- a/docs/en/espefuse/check-error-cmd.rst +++ b/docs/en/espefuse/check-error-cmd.rst @@ -74,7 +74,7 @@ Repairs encoding errors in eFuse blocks, if possible. BLOCK0 ( ) [0 ] err__regs: 00000000 00000000 00000000 00000000 00000000 00000000 EFUSE_RD_RS_ERR0_REG 0x00008990 EFUSE_RD_RS_ERR1_REG 0x00000000 - Recovery of block coding errors. + Recovery of block coding errors. This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN diff --git a/docs/en/espefuse/dump-cmd.rst b/docs/en/espefuse/dump-cmd.rst index a1a09a277..01324529e 100644 --- a/docs/en/espefuse/dump-cmd.rst +++ b/docs/en/espefuse/dump-cmd.rst @@ -59,7 +59,7 @@ The order of registers in the dump: .. only:: not esp32 and not esp32c2 .. code-block:: none - + > espefuse.py dump Connecting.... @@ -111,4 +111,3 @@ These dump files can be written to another chip: > espefuse.py burn_block_data BLOCK0 backup/chip1/blk0.bin \ BLOCK1 backup/chip1/blk1.bin \ BLOCK2 backup/chip1/blk2.bin - \ No newline at end of file diff --git a/docs/en/espefuse/inc/summary_ESP32-C2.rst b/docs/en/espefuse/inc/summary_ESP32-C2.rst index 0c29a2556..f42d80d43 100644 --- a/docs/en/espefuse/inc/summary_ESP32-C2.rst +++ b/docs/en/espefuse/inc/summary_ESP32-C2.rst @@ -16,11 +16,11 @@ Flash fuses: FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) - mmand during SPI boot + mmand during SPI boot FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) nit of ms. If the value is less than 15; the waiti ng time is the configurable value. Otherwise; the - waiting time is twice the configurable value + waiting time is twice the configurable value Identity fuses: DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) @@ -36,31 +36,31 @@ Mac fuses: CUSTOM_MAC_USED (BLOCK0) True if MAC_CUSTOM is burned = False R/W (0b0) - CUSTOM_MAC (BLOCK1) Custom MAC address - = 00:00:00:00:00:00 (OK) R/W - MAC (BLOCK2) MAC address - = 10:97:bd:f0:e5:28 (OK) R/W + CUSTOM_MAC (BLOCK1) Custom MAC address + = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK2) MAC address + = 10:97:bd:f0:e5:28 (OK) R/W Security fuses: DIS_DOWNLOAD_ICACHE (BLOCK0) The bit be set to disable icache in download mode = False R/W (0b0) DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) The bit be set to disable manual encryption = False R/W (0b0) SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) - and disables otherwise + and disables otherwise XTS_KEY_LENGTH_256 (BLOCK0) Flash encryption key length = 128 bits key R/W (0b0) DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) - :0] = 0; 1; 2; 4; 5; 6; 7) + :0] = 0; 1; 2; 4; 5; 6; 7) ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) SECURE_BOOT_EN (BLOCK0) The bit be set to enable secure boot = False R/W (0b0) SECURE_VERSION (BLOCK0) Secure version for anti-rollback = 0 R/W (0x0) BLOCK_KEY0 (BLOCK3) BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryp - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - tion - BLOCK_KEY0_LOW_128 (BLOCK3) BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - Encryption + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + tion + BLOCK_KEY0_LOW_128 (BLOCK3) BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Encryption BLOCK_KEY0_HI_128 (BLOCK3) BLOCK_KEY0 - higher 128-bits. 128-bits key of Secu - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - re Boot + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + re Boot Wdt fuses: WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) diff --git a/docs/en/espefuse/inc/summary_ESP32-C3.rst b/docs/en/espefuse/inc/summary_ESP32-C3.rst index b1a19ea79..c20b5c58d 100644 --- a/docs/en/espefuse/inc/summary_ESP32-C3.rst +++ b/docs/en/espefuse/inc/summary_ESP32-C3.rst @@ -2,7 +2,7 @@ > espefuse.py -p PORT summary - Connecting.... + Connecting.... Detecting chip type... ESP32-C3 === Run "summary" command === @@ -34,18 +34,18 @@ DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) ERR_RST_ENABLE (BLOCK0) Use BLOCK0 to check error record registers = with check R/W (0b1) - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Flash fuses: FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) nit of ms. If the value is less than 15; the waiti - ng time is the configurable value; Otherwise; the - waiting time is twice the configurable value + ng time is the configurable value; Otherwise; the + waiting time is twice the configurable value FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) - mmand during SPI boot + mmand during SPI boot Identity fuses: DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) @@ -55,34 +55,34 @@ BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 2 R/W (0b010) WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) - OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID - = 25 60 04 96 c3 fd 41 6f be ed 2c 51 1d e3 7e 21 R/W + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 25 60 04 96 c3 fd 41 6f be ed 2c 51 1d e3 7e 21 R/W BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = With calibration R/W (0b01) WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 3 R/W (0x3) - << 3 + WAFER_VERSION_MINOR_LO (read only) + << 3 + WAFER_VERSION_MINOR_LO (read only) Jtag fuses: SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) d number 1 means disable ). JTAG can be enabled in - HMAC module + HMAC module DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) - is disabled permanently + is disabled permanently Mac fuses: - MAC (BLOCK1) MAC address - = 58:cf:79:0f:96:8c (OK) R/W - CUSTOM_MAC (BLOCK3) Custom MAC address - = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK1) MAC address + = 58:cf:79:0f:96:8c (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC address + = 00:00:00:00:00:00 (OK) R/W Security fuses: DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) - oot_mode[3:0] is 0; 1; 2; 3; 6; 7) + oot_mode[3:0] is 0; 1; 2; 3; 6; 7) DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) - hip into download mode + hip into download mode DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) - ownload boot modes + ownload boot modes SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) - and disables otherwise + and disables otherwise SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) @@ -94,36 +94,36 @@ KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) - boot + boot DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) - :0] = 0; 1; 2; 3; 6; 7) + :0] = 0; 1; 2; 3; 6; 7) ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) + ure) BLOCK_KEY0 (BLOCK4) Purpose: USER - Key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY1 (BLOCK5) Purpose: USER - Key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY2 (BLOCK6) Purpose: USER - Key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY3 (BLOCK7) Purpose: USER - Key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY4 (BLOCK8) Purpose: USER - Key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY5 (BLOCK9) Purpose: USER - Key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Spi Pad fuses: SPI_PAD_CONFIG_CLK (BLOCK1) SPI PAD CLK = 0 R/W (0b000000) @@ -140,7 +140,7 @@ Usb fuses: DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) - jtag in module of usb device + jtag in module of usb device DIS_USB_SERIAL_JTAG (BLOCK0) USB-Serial-JTAG = Enable R/W (0b0) USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) diff --git a/docs/en/espefuse/inc/summary_ESP32-C6.rst b/docs/en/espefuse/inc/summary_ESP32-C6.rst index 39411b778..fdfc78bce 100644 --- a/docs/en/espefuse/inc/summary_ESP32-C6.rst +++ b/docs/en/espefuse/inc/summary_ESP32-C6.rst @@ -2,7 +2,7 @@ > espefuse.py -p PORT summary - Connecting.... + Connecting.... Detecting chip type... ESP32-C6 === Run "summary" command === @@ -12,27 +12,27 @@ WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) SWAP_UART_SDIO_EN (BLOCK0) Represents whether pad of uart and sdio is swapped = False R/W (0b0) - or not. 1: swapped. 0: not swapped + or not. 1: swapped. 0: not swapped DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0) - 1: disabled. 0: enabled + 1: disabled. 0: enabled DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) - abled. 1: disabled. 0: enabled + abled. 1: disabled. 0: enabled DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) - enabled. 1: disabled. 0: enabled + enabled. 1: disabled. 0: enabled UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Flash fuses: FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) in unit of ms. When the value less than 15; the wa iting time is the programmed value. Otherwise; the - waiting time is 2 times the programmed value + waiting time is 2 times the programmed value FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) sume command during SPI boot. 1: forced. 0:not for - ced + ced FLASH_CAP (BLOCK1) = 0 R/W (0b000) FLASH_TEMP (BLOCK1) = 0 R/W (0b00) FLASH_VENDOR (BLOCK1) = 0 R/W (0b000) @@ -45,41 +45,41 @@ BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Jtag fuses: JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) ag and pad_to_jtag through strapping gpio15 when b - oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are - equal to 0 is enabled or disabled. 1: enabled. 0: - disabled + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled. 1: enabled. 0: + disabled SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) - dd number: disabled. Even number: enabled + dd number: disabled. Even number: enabled DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) - y(permanently). 1: disabled. 0: enabled + y(permanently). 1: disabled. 0: enabled Mac fuses: - MAC (BLOCK1) MAC address - = 60:55:f9:f6:03:24 (OK) R/W - MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W - CUSTOM_MAC (BLOCK3) Custom MAC - = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK1) MAC address + = 60:55:f9:f6:03:24 (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W Security fuses: DIS_DOWNLOAD_ICACHE (BLOCK0) Represents whether icache is disabled or enabled i = False R/W (0b0) - n Download mode. 1: disabled. 0: enabled + n Download mode. 1: disabled. 0: enabled DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) nto download mode is disabled or enabled. 1: disab - led. 0: enabled + led. 0: enabled SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) e_download is disabled or enabled. 1: disabled. 0: - enabled + enabled DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) led or enabled(except in SPI boot mode). 1: disabl - ed. 0: enabled + ed. 0: enabled SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) - and disables otherwise + and disables otherwise SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) @@ -90,64 +90,64 @@ KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) - clock random divide mode + clock random divide mode CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) - nabled. 0: disabled + nabled. 0: disabled SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) - led. 1: enabled. 0: disabled + led. 1: enabled. 0: disabled SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) - is enabled or disabled. 1: enabled. 0: disabled + is enabled or disabled. 1: enabled. 0: disabled DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) - abled. 1: disabled. 0: enabled + abled. 1: disabled. 0: enabled ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) - disabled. 1: enabled. 0: disabled + disabled. 1: enabled. 0: disabled SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) - ck feature + ck feature SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) or enabled when Secure Boot is enabled. 1: disabl - ed. 0: enabled + ed. 0: enabled BLOCK_KEY0 (BLOCK4) Purpose: USER - Key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY1 (BLOCK5) Purpose: USER - Key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY2 (BLOCK6) Purpose: USER - Key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY3 (BLOCK7) Purpose: USER - Key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY4 (BLOCK8) Purpose: USER - Key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY5 (BLOCK9) Purpose: USER - Key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Usb fuses: DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) tag is disabled or enabled. 1: disabled. 0: enable - d + d DIS_USB_SERIAL_JTAG (BLOCK0) Represents whether USB-Serial-JTAG is disabled or = False R/W (0b0) - enabled. 1: disabled. 0: enabled + enabled. 1: disabled. 0: enabled USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) - . 1: exchanged. 0: not exchanged + . 1: exchanged. 0: not exchanged DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) - isabled or enabled. 1: disabled. 0: enabled + isabled or enabled. 1: disabled. 0: enabled DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) nction is disabled or enabled. 1: disabled. 0: ena - bled + bled Vdd fuses: VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) - io. 1: functioned. 0: not functioned + io. 1: functioned. 0: not functioned Wdt fuses: WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) diff --git a/docs/en/espefuse/inc/summary_ESP32-H2.rst b/docs/en/espefuse/inc/summary_ESP32-H2.rst index 0032586bd..53c48e830 100644 --- a/docs/en/espefuse/inc/summary_ESP32-H2.rst +++ b/docs/en/espefuse/inc/summary_ESP32-H2.rst @@ -2,7 +2,7 @@ > espefuse.py -p PORT summary - Connecting.... + Connecting.... Detecting chip type... ESP32-H2 === Run "summary" command === @@ -12,29 +12,29 @@ WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0) - 1: disabled. 0: enabled + 1: disabled. 0: enabled POWERGLITCH_EN (BLOCK0) Represents whether power glitch function is enable = False R/W (0b0) - d. 1: enabled. 0: disabled + d. 1: enabled. 0: disabled DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) - abled. 1: disabled. 0: enabled + abled. 1: disabled. 0: enabled DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) - enabled. 1: disabled. 0: enabled + enabled. 1: disabled. 0: enabled UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) HYS_EN_PAD0 (BLOCK0) Set bits to enable hysteresis function of PAD0~5 = 0 R/W (0b000000) HYS_EN_PAD1 (BLOCK0) Set bits to enable hysteresis function of PAD6~27 = 0 R/W (0b0000000000000000000000) - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Flash fuses: FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) in unit of ms. When the value less than 15; the wa iting time is the programmed value. Otherwise; the - waiting time is 2 times the programmed value + waiting time is 2 times the programmed value FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) sume command during SPI boot. 1: forced. 0:not for - ced + ced FLASH_CAP (BLOCK1) = 0 R/W (0b000) FLASH_TEMP (BLOCK1) = 0 R/W (0b00) FLASH_VENDOR (BLOCK1) = 0 R/W (0b000) @@ -44,8 +44,8 @@ WAFER_VERSION_MAJOR (BLOCK1) = 0 R/W (0b00) DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0) PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) DISABLE_BLK_VERSION_MAJOR (BLOCK2) Disables check of blk version major = False R/W (0b0) @@ -53,32 +53,32 @@ Jtag fuses: JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) ag and pad_to_jtag through strapping gpio25 when b - oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are - equal to 0 + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) - dd number: disabled. Even number: enabled + dd number: disabled. Even number: enabled DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) - y(permanently). 1: disabled. 0: enabled + y(permanently). 1: disabled. 0: enabled Mac fuses: - MAC (BLOCK1) MAC address - = 60:55:f9:f7:2c:05 (OK) R/W - MAC_EXT (BLOCK1) Stores the extended bits of MAC address = ff:fe (OK) R/W - CUSTOM_MAC (BLOCK3) Custom MAC - = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK1) MAC address + = 60:55:f9:f7:2c:05 (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = ff:fe (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W Security fuses: DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) nto download mode is disabled or enabled. 1: disab - led. 0: enabled + led. 0: enabled SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) e_download is disabled or enabled. 1: disabled. 0: - enabled + enabled DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) led or enabled(except in SPI boot mode). 1: disabl - ed. 0: enabled + ed. 0: enabled SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) - and disables otherwise + and disables otherwise SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) @@ -89,65 +89,65 @@ KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) - clock random divide mode + clock random divide mode ECDSA_FORCE_USE_HARDWARE_K (BLOCK0) Represents whether hardware random number k is for = False R/W (0b0) ced used in ESDCA. 1: force used. 0: not force use - d + d CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) - nabled. 0: disabled + nabled. 0: disabled SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) - led. 1: enabled. 0: disabled + led. 1: enabled. 0: disabled SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) - is enabled or disabled. 1: enabled. 0: disabled + is enabled or disabled. 1: enabled. 0: disabled DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) - abled. 1: disabled. 0: enabled + abled. 1: disabled. 0: enabled ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) - disabled. 1: enabled. 0: disabled + disabled. 1: enabled. 0: disabled SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) - ck feature + ck feature SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) or enabled when Secure Boot is enabled. 1: disabl - ed. 0: enabled + ed. 0: enabled BLOCK_KEY0 (BLOCK4) Purpose: USER - Key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY1 (BLOCK5) Purpose: USER - Key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY2 (BLOCK6) Purpose: USER - Key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY3 (BLOCK7) Purpose: USER - Key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY4 (BLOCK8) Purpose: USER - Key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY5 (BLOCK9) Purpose: USER - Key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Usb fuses: DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) tag is disabled or enabled. 1: disabled. 0: enable - d + d USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) - . 1: exchanged. 0: not exchanged + . 1: exchanged. 0: not exchanged DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Set this bit to disable USB-Serial-JTAG print duri = False R/W (0b0) - ng rom boot + ng rom boot DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) nction is disabled or enabled. 1: disabled. 0: ena - bled + bled Vdd fuses: VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) - io. 1: functioned. 0: not functioned + io. 1: functioned. 0: not functioned Wdt fuses: WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) diff --git a/docs/en/espefuse/inc/summary_ESP32-P4.rst b/docs/en/espefuse/inc/summary_ESP32-P4.rst index 74421869c..e03d5f06a 100644 --- a/docs/en/espefuse/inc/summary_ESP32-P4.rst +++ b/docs/en/espefuse/inc/summary_ESP32-P4.rst @@ -12,27 +12,27 @@ WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) POWERGLITCH_EN (BLOCK0) Represents whether power glitch function is enable = False R/W (0b0) - d. 1: enabled. 0: disabled + d. 1: enabled. 0: disabled DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) - abled. 1: disabled. 0: enabled + abled. 1: disabled. 0: enabled KM_HUK_GEN_STATE_LOW (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000000) - mode. Odd of 1 is invalid; even of 1 is valid + mode. Odd of 1 is invalid; even of 1 is valid KM_HUK_GEN_STATE_HIGH (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000) - mode. Odd of 1 is invalid; even of 1 is valid + mode. Odd of 1 is invalid; even of 1 is valid KM_RND_SWITCH_CYCLE (BLOCK0) Set bits to control key manager random number swit = 0 R/W (0b00) ch cycle. 0: control by register. 1: 8 km clk cycl - es. 2: 16 km cycles. 3: 32 km cycles + es. 2: 16 km cycles. 3: 32 km cycles KM_DEPLOY_ONLY_ONCE (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0) - can only be deployed once. 1 is true; 0 is false. - Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + can only be deployed once. 1 is true; 0 is false. + Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) - enabled. 1: disabled. 0: enabled + enabled. 1: disabled. 0: enabled UART_PRINT_CONTROL (BLOCK0) Represents the type of UART printing. 00: force en = 0 R/W (0b00) able printing. 01: enable printing when GPIO8 is r - eset at low level. 10: enable printing when GPIO8 + eset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing HYS_EN_PAD (BLOCK0) Represents whether the hysteresis function of corr = False R/W (0b0) - esponding PAD is enabled. 1: enabled. 0:disabled + esponding PAD is enabled. 1: enabled. 0:disabled DCDC_VSET (BLOCK0) Set the dcdc voltage default = 0 R/W (0b00000) PXA0_TIEH_SEL_0 (BLOCK0) TBD = 0 R/W (0b00) PXA0_TIEH_SEL_1 (BLOCK0) TBD = 0 R/W (0b00) @@ -42,63 +42,63 @@ HP_PWR_SRC_SEL (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) DCDC_VSET_EN (BLOCK0) Select dcdc vset use efuse_dcdc_vset = False R/W (0b0) DIS_SWD (BLOCK0) Set this bit to disable super-watchdog = False R/W (0b0) - BLOCK_SYS_DATA1 (BLOCK2) System data part 1 - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - + BLOCK_SYS_DATA1 (BLOCK2) System data part 1 + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Flash fuses: FLASH_TYPE (BLOCK0) The type of interfaced flash. 0: four data lines; = False R/W (0b0) - 1: eight data lines + 1: eight data lines FLASH_PAGE_SIZE (BLOCK0) Set flash page size = 0 R/W (0b00) FLASH_ECC_EN (BLOCK0) Set this bit to enable ecc for flash boot = False R/W (0b0) FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) in unit of ms. When the value less than 15; the wa iting time is the programmed value. Otherwise; the - waiting time is 2 times the programmed value + waiting time is 2 times the programmed value FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) sume command during SPI boot. 1: forced. 0:not for - ced - + ced + Jtag fuses: JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) ag and pad_to_jtag through strapping gpio15 when b - oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are - equal to 0 is enabled or disabled. 1: enabled. 0: - disabled + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled. 1: enabled. 0: + disabled SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) - dd number: disabled. Even number: enabled + dd number: disabled. Even number: enabled DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) - y(permanently). 1: disabled. 0: enabled - + y(permanently). 1: disabled. 0: enabled + Mac fuses: - MAC (BLOCK1) MAC address - = 00:00:00:00:00:00 (OK) R/W - MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W + MAC (BLOCK1) MAC address + = 00:00:00:00:00:00 (OK) R/W + MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M - = 00:00:00:00:00:00:00:00 (OK) R/W - AC_EXT[1]:MAC[3]:MAC[4]:MAC[5] - + = 00:00:00:00:00:00:00:00 (OK) R/W + AC_EXT[1]:MAC[3]:MAC[4]:MAC[5] + Security fuses: DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) nto download mode is disabled or enabled. 1: disab - led. 0: enabled + led. 0: enabled SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Set this bit to disable accessing MSPI flash/MSPI = False R/W (0b0) - ram by SYS AXI matrix during boot_mode_download + ram by SYS AXI matrix during boot_mode_download DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) led or enabled(except in SPI boot mode). 1: disabl - ed. 0: enabled + ed. 0: enabled FORCE_USE_KEY_MANAGER_KEY (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0) must come from key manager.. 1 is true; 0 is false - . Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + . Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds FORCE_DISABLE_SW_INIT_KEY (BLOCK0) Set this bit to disable software written init key; = False R/W (0b0) - and force use efuse_init_key + and force use efuse_init_key XTS_KEY_LENGTH_256 (BLOCK0) Set this bit to configure flash encryption use xts = False R/W (0b0) - -128 key; else use xts-256 key + -128 key; else use xts-256 key SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) - and disables otherwise + and disables otherwise SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) @@ -109,68 +109,67 @@ KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) - clock random divide mode + clock random divide mode ECDSA_ENABLE_SOFT_K (BLOCK0) Represents whether hardware random number k is for = False R/W (0b0) ced used in ESDCA. 1: force used. 0: not force use - d + d CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = False R/W (0b0) - nabled. 0: disabled + nabled. 0: disabled SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) - led. 1: enabled. 0: disabled + led. 1: enabled. 0: disabled SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) - is enabled or disabled. 1: enabled. 0: disabled + is enabled or disabled. 1: enabled. 0: disabled DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) - abled. 1: disabled. 0: enabled + abled. 1: disabled. 0: enabled LOCK_KM_KEY (BLOCK0) TBD = False R/W (0b0) ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) - disabled. 1: enabled. 0: disabled + disabled. 1: enabled. 0: disabled SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) - ck feature + ck feature SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) or enabled when Secure Boot is enabled. 1: disabl - ed. 0: enabled + ed. 0: enabled BLOCK_KEY0 (BLOCK4) Purpose: USER - Key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY1 (BLOCK5) Purpose: USER - Key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY2 (BLOCK6) Purpose: USER - Key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY3 (BLOCK7) Purpose: USER - Key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY4 (BLOCK8) Purpose: USER - Key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY5 (BLOCK9) Purpose: USER - Key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Usb fuses: USB_DEVICE_EXCHG_PINS (BLOCK0) Enable usb device exchange pins of D+ and D- = False R/W (0b0) USB_OTG11_EXCHG_PINS (BLOCK0) Enable usb otg11 exchange pins of D+ and D- = False R/W (0b0) DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) tag is disabled or enabled. 1: disabled. 0: enable - d + d USB_PHY_SEL (BLOCK0) TBD = False R/W (0b0) DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download via USB-OTG = False R/W (0b0) DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) - isabled or enabled. 1: disabled. 0: enabled + isabled or enabled. 1: disabled. 0: enabled DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) nction is disabled or enabled. 1: disabled. 0: ena - bled - + bled + Wdt fuses: WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00) is selected at startup. 1: selected. 0: not select - ed + ed DIS_WDT (BLOCK0) Set this bit to disable watch dog = False R/W (0b0) - \ No newline at end of file diff --git a/docs/en/espefuse/inc/summary_ESP32-S2.rst b/docs/en/espefuse/inc/summary_ESP32-S2.rst index 85617bfa4..8589c3620 100644 --- a/docs/en/espefuse/inc/summary_ESP32-S2.rst +++ b/docs/en/espefuse/inc/summary_ESP32-S2.rst @@ -34,27 +34,27 @@ DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) DIS_DCACHE (BLOCK0) Set this bit to disable Dcache = False R/W (0b0) DIS_TWAI (BLOCK0) Set this bit to disable the TWAI Controller functi = False R/W (0b0) - on + on DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0) - ace + ace DIS_LEGACY_SPI_BOOT (BLOCK0) Set this bit to disable Legacy SPI boot mode = False R/W (0b0) UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot message = UART0 R/W (0b0) - s + s UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) - en SPI flash is initialized - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + en SPI flash is initialized + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Flash fuses: FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up; = 0 R/W (0x0) in unit of (ms/2). When the value is 15; delay is - 7.5 ms + 7.5 ms FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) FORCE_SEND_RESUME (BLOCK0) If set; forces ROM code to send an SPI flash resum = False R/W (0b0) - e command during SPI boot + e command during SPI boot FLASH_VERSION (BLOCK1) Flash version = 1 R/W (0x1) Identity fuses: @@ -67,11 +67,11 @@ PSRAM_VERSION (BLOCK1) PSRAM version = 0 R/W (0x0) PKG_VERSION (BLOCK1) Package version = 0 R/W (0x0) WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) - OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID - = d9 8f 05 d0 86 77 53 db 80 6c ee 40 df 5d ef b0 R/W + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = d9 8f 05 d0 86 77 53 db 80 6c ee 40 df 5d ef b0 R/W BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2 = ADC calib V1 R/W (0b001) WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) - << 3 + WAFER_VERSION_MINOR_LO (read only) + << 3 + WAFER_VERSION_MINOR_LO (read only) Jtag fuses: SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled; JT = False R/W (0b0) @@ -79,20 +79,20 @@ HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) Mac fuses: - MAC (BLOCK1) MAC address - = 7c:df:a1:00:48:34 (OK) R/W - CUSTOM_MAC (BLOCK3) Custom MAC - = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK1) MAC address + = 7c:df:a1:00:48:34 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W Security fuses: DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) - hip into download mode + hip into download mode DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) - des + des SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) - and disabled otherwise + and disabled otherwise SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) @@ -104,36 +104,36 @@ KEY_PURPOSE_5 (BLOCK0) Purpose of KEY5 = USER R/W (0x0) SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable aggressive secure boot key = False R/W (0b0) - revocation mode + revocation mode DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable all download boot modes = False R/W (0b0) ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode ( = False R/W (0b0) - read/write flash only) + read/write flash only) SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) + ure) BLOCK_KEY0 (BLOCK4) Purpose: USER - Key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY1 (BLOCK5) Purpose: USER - Key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY2 (BLOCK6) Purpose: USER - Key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY3 (BLOCK7) Purpose: USER - Key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY4 (BLOCK8) Purpose: USER - Key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY5 (BLOCK9) Purpose: USER - Key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Spi Pad fuses: SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) @@ -154,19 +154,19 @@ USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external USB PHY = False R/W (0b0) USB_FORCE_NOPERSIST (BLOCK0) If set; forces USB BVALID to 1 = False R/W (0b0) DIS_USB_DOWNLOAD_MODE (BLOCK0) Set this bit to disable use of USB OTG in UART dow = False R/W (0b0) - nload boot mode + nload boot mode Vdd fuses: VDD_SPI_XPD (BLOCK0) If VDD_SPI_FORCE is 1; this value determines if th = False R/W (0b0) - e VDD_SPI regulator is powered on - VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage + e VDD_SPI regulator is powered on + VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage = VDD_SPI connects to 1.8 V LDO R/W (0b0) VDD_SPI_FORCE (BLOCK0) Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TI = False R/W (0b0) - EH to configure VDD_SPI LDO + EH to configure VDD_SPI LDO Wdt fuses: WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) - ock cycle + ock cycle Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). diff --git a/docs/en/espefuse/inc/summary_ESP32-S3.rst b/docs/en/espefuse/inc/summary_ESP32-S3.rst index 25c64ac27..dbd4b0585 100644 --- a/docs/en/espefuse/inc/summary_ESP32-S3.rst +++ b/docs/en/espefuse/inc/summary_ESP32-S3.rst @@ -18,23 +18,23 @@ DIS_DIRECT_BOOT (BLOCK0) Disable direct boot mode = False R/W (0b0) UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) - en SPI flash is initialized - BLOCK_USR_DATA (BLOCK3) User data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + en SPI flash is initialized + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Flash fuses: FLASH_TPUW (BLOCK0) Configures flash waiting time after power-up; in u = 0 R/W (0x0) nit of ms. If the value is less than 15; the waiti ng time is the configurable value. Otherwise; the - waiting time is twice the configurable value + waiting time is twice the configurable value FLASH_ECC_MODE (BLOCK0) Flash ECC mode in ROM = 16to18 byte R/W (0b0) FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) FLASH_PAGE_SIZE (BLOCK0) Set Flash page size = 0 R/W (0b00) FLASH_ECC_EN (BLOCK0) Set 1 to enable ECC for flash boot = False R/W (0b0) FORCE_SEND_RESUME (BLOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0) - mmand during SPI boot + mmand during SPI boot Identity fuses: DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) @@ -44,40 +44,40 @@ BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR = 0 R/W (0b000) WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) - OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = No calib R/W (0b00) WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) - << 3 + WAFER_VERSION_MINOR_LO (read only) + << 3 + WAFER_VERSION_MINOR_LO (read only) Jtag fuses: SOFT_DIS_JTAG (BLOCK0) Set these bits to disable JTAG in the soft way (od = 0 R/W (0b000) d number 1 means disable ). JTAG can be enabled in - HMAC module + HMAC module DIS_PAD_JTAG (BLOCK0) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0) - is disabled permanently + is disabled permanently STRAP_JTAG_SEL (BLOCK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0) ag and pad_to_jtag through strapping gpio10 when b oth reg_dis_usb_jtag and reg_dis_pad_jtag are equa - l to 0 + l to 0 Mac fuses: - MAC (BLOCK1) MAC address - = 7c:df:a1:e0:00:58 (OK) R/W - CUSTOM_MAC (BLOCK3) Custom MAC - = 00:00:00:00:00:00 (OK) R/W + MAC (BLOCK1) MAC address + = 7c:df:a1:e0:00:58 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W Security fuses: DIS_DOWNLOAD_ICACHE (BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0) - oot_mode[3:0] is 0; 1; 2; 3; 6; 7) + oot_mode[3:0] is 0; 1; 2; 3; 6; 7) DIS_DOWNLOAD_DCACHE (BLOCK0) Set this bit to disable Dcache in download mode ( = False R/W (0b0) - boot_mode[3:0] is 0; 1; 2; 3; 6; 7) + boot_mode[3:0] is 0; 1; 2; 3; 6; 7) DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) - hip into download mode + hip into download mode DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Set this bit to disable flash encryption when in d = False R/W (0b0) - ownload boot modes + ownload boot modes SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) - and disabled otherwise + and disabled otherwise SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) @@ -89,36 +89,36 @@ KEY_PURPOSE_5 (BLOCK0) Purpose of Key5 = USER R/W (0x0) SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable revoking aggressive secure = False R/W (0b0) - boot + boot DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0) - :0] = 0; 1; 2; 3; 6; 7) + :0] = 0; 1; 2; 3; 6; 7) ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode = False R/W (0b0) SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) - ure) + ure) BLOCK_KEY0 (BLOCK4) Purpose: USER - Key0 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY1 (BLOCK5) Purpose: USER - Key1 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY2 (BLOCK6) Purpose: USER - Key2 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY3 (BLOCK7) Purpose: USER - Key3 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY4 (BLOCK8) Purpose: USER - Key4 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W BLOCK_KEY5 (BLOCK9) Purpose: USER - Key5 or user data - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Spi Pad fuses: SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) @@ -138,26 +138,26 @@ USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external PHY = False R/W (0b0) DIS_USB_JTAG (BLOCK0) Set this bit to disable function of usb switch to = False R/W (0b0) - jtag in module of usb device + jtag in module of usb device DIS_USB_SERIAL_JTAG (BLOCK0) Set this bit to disable usb device = False R/W (0b0) USB_PHY_SEL (BLOCK0) This bit is used to switch internal PHY and extern = internal PHY is assigned to USB Device while external PHY is assigned to USB OTG R/W (0b0) - al PHY for USB OTG and USB Device + al PHY for USB OTG and USB Device DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) USB printing = Enable R/W (0b0) DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable UART download mode through = False R/W (0b0) - USB + USB DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download through USB-OTG = False R/W (0b0) Vdd fuses: VDD_SPI_XPD (BLOCK0) SPI regulator power up signal = False R/W (0b0) - VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage + VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage = VDD_SPI connects to 1.8 V LDO R/W (0b0) VDD_SPI_FORCE (BLOCK0) Set this bit and force to use the configuration of = False R/W (0b0) - eFuse to configure VDD_SPI + eFuse to configure VDD_SPI Wdt fuses: WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) - ock cycle + ock cycle Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). diff --git a/docs/en/espefuse/inc/summary_ESP32.rst b/docs/en/espefuse/inc/summary_ESP32.rst index 59f303815..ff4d018f0 100644 --- a/docs/en/espefuse/inc/summary_ESP32.rst +++ b/docs/en/espefuse/inc/summary_ESP32.rst @@ -19,16 +19,16 @@ DIS_CACHE (BLOCK0): Disables cache = False R/W (0b0) CHIP_CPU_FREQ_LOW (BLOCK0): If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the = False R/W (0b0) ESP32's max CPU frequency is rated for 160MHz. 24 - 0MHz otherwise + 0MHz otherwise CHIP_CPU_FREQ_RATED (BLOCK0): If set; the ESP32's maximum CPU frequency has been = True R/W (0b1) - rated + rated BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0) CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 51 R/W (0x33) VOL_LEVEL_HP_INV (BLOCK0): This field stores the voltage level for CPU to run = 0 R/W (0b00) at 240 MHz; or for flash/PSRAM to run at 80 MHz.0 x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: leve - l 4. (RO) - CODING_SCHEME (BLOCK0): Efuse variable block length scheme + l 4. (RO) + CODING_SCHEME (BLOCK0): Efuse variable block length scheme = NONE (BLK1-3 len=256 bits) R/W (0b00) CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1) DISABLE_SDIO_HOST (BLOCK0): = False R/W (0b0) @@ -36,7 +36,7 @@ Flash fuses: FLASH_CRYPT_CNT (BLOCK0): Flash encryption is enabled if this field has an o = 0 R/W (0b0000000) - dd number of bits set + dd number of bits set FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0) Identity fuses: @@ -46,34 +46,34 @@ CHIP_VER_REV2 (BLOCK0): = True R/W (0b1) WAFER_VERSION_MINOR (BLOCK0): = 0 R/W (0b00) WAFER_VERSION_MAJOR (BLOCK0): calc WAFER VERSION MAJOR from CHIP_VER_REV1 and CH = 3 R/W (0b011) - IP_VER_REV2 and apb_ctl_date (read only) + IP_VER_REV2 and apb_ctl_date (read only) PKG_VERSION (BLOCK0): calc Chip package = CHIP_PACKAGE_4BIT << 3 + CHIP_ = 1 R/W (0x1) - PACKAGE (read only) + PACKAGE (read only) Jtag fuses: JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0) Mac fuses: - MAC (BLOCK0): MAC address - = 94:b9:7e:5a:6e:58 (CRC 0xe2 OK) R/W + MAC (BLOCK0): MAC address + = 94:b9:7e:5a:6e:58 (CRC 0xe2 OK) R/W MAC_CRC (BLOCK0): CRC8 for MAC address = 226 R/W (0xe2) MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00) Security fuses: UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode. Valid for ESP32 V3 and = False R/W (0b0) - newer; only + newer; only ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0) ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0) DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0) DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0) KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0) SECURE_VERSION (BLOCK3): Secure version for anti-rollback = 0 R/W (0x00000000) - BLOCK1 (BLOCK1): Flash encryption key - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK2 (BLOCK2): Security boot key - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W - BLOCK3 (BLOCK3): Variable Block 3 - = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK1 (BLOCK1): Flash encryption key + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK2 (BLOCK2): Security boot key + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK3 (BLOCK3): Variable Block 3 + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W Spi Pad fuses: SPI_PAD_CONFIG_HD (BLOCK0): read for SPI_pad_config_hd = 0 R/W (0b00000) diff --git a/docs/en/espefuse/index.rst b/docs/en/espefuse/index.rst index 9045eb6e5..ba5009123 100644 --- a/docs/en/espefuse/index.rst +++ b/docs/en/espefuse/index.rst @@ -75,7 +75,7 @@ The coding scheme helps the eFuse controller to detect an error of the eFuse blo {IDF_TARGET_NAME} supports the following coding schemes: .. only:: esp32 - + * ``None`` no need any special encoding data. BLOCK0 is always None. * ``3/4``, requires encoding data. The BLOCK length is reduced from 256 bits to 192 bits. * ``Repeat`` not supported by this tool and IDF. The BLOCK length is reduced from 256 bits to 128 bits. @@ -83,7 +83,7 @@ The coding scheme helps the eFuse controller to detect an error of the eFuse blo BLOCK1-3 can have any of this coding scheme. It depends on the ``CODING_SCHEME`` eFuse. .. only:: not esp32 - + * ``None`` no need any special encoding data, but internally it copies data four times. BLOCK0. * ``RS`` (Reed-Solomon), it uses 6 bytes of automatic error correction. diff --git a/docs/en/espefuse/read-write-protections-cmd.rst b/docs/en/espefuse/read-write-protections-cmd.rst index c6c6364cb..3ae6f740e 100644 --- a/docs/en/espefuse/read-write-protections-cmd.rst +++ b/docs/en/espefuse/read-write-protections-cmd.rst @@ -51,7 +51,7 @@ Usage Check all blocks for burn... idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -71,7 +71,7 @@ Usage Check all blocks for burn... idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN diff --git a/docs/en/espefuse/set-flash-voltage-cmd.rst b/docs/en/espefuse/set-flash-voltage-cmd.rst index 719a76c6c..950cad4a1 100644 --- a/docs/en/espefuse/set-flash-voltage-cmd.rst +++ b/docs/en/espefuse/set-flash-voltage-cmd.rst @@ -13,7 +13,7 @@ The ``espefuse.py set_flash_voltage`` command permanently sets the internal flas Positional arguments: -- ``voltage`` - Voltage selection ['1.8V', '3.3V', 'OFF']. +- ``voltage`` - Voltage selection ['1.8V', '3.3V', 'OFF']. .. only:: esp32c2 or esp32c3 @@ -111,7 +111,7 @@ Once an efuse is burned it cannot be un-burned. However, changes can be made by Check all blocks for burn... idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -132,7 +132,7 @@ Once an efuse is burned it cannot be un-burned. However, changes can be made by Check all blocks for burn... idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN @@ -146,13 +146,13 @@ Once an efuse is burned it cannot be un-burned. However, changes can be made by > espefuse.py set_flash_voltage OFF === Run "set_flash_voltage" command === - Disable internal flash voltage regulator (VDD_SPI). SPI flash will + Disable internal flash voltage regulator (VDD_SPI). SPI flash will VDD_SPI setting complete. Check all blocks for burn... idx, BLOCK_NAME, Conclusion [00] BLOCK0 is empty, will burn the new value - . + . This is an irreversible operation! Type 'BURN' (all capitals) to continue. BURN diff --git a/docs/en/esptool/serial-connection.rst b/docs/en/esptool/serial-connection.rst index e6e4ab93c..32eed2754 100644 --- a/docs/en/esptool/serial-connection.rst +++ b/docs/en/esptool/serial-connection.rst @@ -19,7 +19,7 @@ However, if you are wiring the chip yourself to a USB/Serial adapter or similar Note that TX (transmit) on the ESP chip is connected to RX (receive) on the serial port connection, and vice versa. -Do not connect the chip to 5V TTL serial adapters, and especially not to "standard" RS-232 adapters! 3.3V serial only!  +Do not connect the chip to 5V TTL serial adapters, and especially not to "standard" RS-232 adapters! 3.3V serial only! .. _serial-port-settings: @@ -28,7 +28,7 @@ Serial Port Settings When communicating with the {IDF_TARGET_NAME} ROM serial bootloader, the following serial port settings are recommended: -+---------------------+-------------------+  ++---------------------+-------------------+ | Baud rate | {IDF_TARGET_BAUD_RATE} | +---------------------+-------------------+ | Data bits | 8 | @@ -41,7 +41,7 @@ When communicating with the {IDF_TARGET_NAME} ROM serial bootloader, the followi +---------------------+-------------------+ .. only:: esp32c2 - + .. note:: You might experience issues when using low baud rates on {IDF_TARGET_NAME}. If you encounter any problems when connecting, please use at least 115200 or higher. From 7d732d6a31ef90bdf7c737dff9787764f14521b9 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Mon, 12 Feb 2024 17:10:05 +0100 Subject: [PATCH 141/209] docs(sphinx-lint): Add previous commit to .git-blame-ignore-revs --- .git-blame-ignore-revs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs index ad56ec888..e31ea0100 100644 --- a/.git-blame-ignore-revs +++ b/.git-blame-ignore-revs @@ -10,3 +10,6 @@ b57f69bd13222b1753446a0f7c17386eda1dc2c9 # Formating with Black 45f1da954eeab4897fb852894fae0c1b901b3926 + +# Refactoring documentation +6282f98dbfca58add4992c259c0aac3c3ec64d3f From d2f15bf98127ec9861b8d6b3ef9805fe35455f67 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 9 Feb 2024 08:38:52 +0100 Subject: [PATCH 142/209] docs: add esp32p4 target to docs --- .gitlab-ci.yml | 2 +- docs/_static/esptool_versions.js | 1 + docs/conf_common.py | 26 ++++------- .../advanced-topics/boot-mode-selection.rst | 45 ++++++++++--------- .../advanced-topics/firmware-image-format.rst | 4 +- docs/en/esptool/advanced-options.rst | 2 +- docs/en/esptool/flash-modes.rst | 2 +- docs/requirements.txt | 2 +- 8 files changed, 40 insertions(+), 44 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index eeb5402f3..97dd36be2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -468,7 +468,7 @@ build_docs: script: - cd docs - pip install -r requirements.txt --prefer-binary - - build-docs -l en -t {esp8266,esp32,esp32s2,esp32c3,esp32s3,esp32c2,esp32c6,esp32h2} + - build-docs -l en -t {esp8266,esp32,esp32s2,esp32c3,esp32s3,esp32c2,esp32c6,esp32h2,esp32p4} .deploy_docs_template: stage: deploy_docs diff --git a/docs/_static/esptool_versions.js b/docs/_static/esptool_versions.js index b5e0fab54..409ecf2e9 100644 --- a/docs/_static/esptool_versions.js +++ b/docs/_static/esptool_versions.js @@ -12,5 +12,6 @@ var DOCUMENTATION_VERSIONS = { { text: "ESP32-C2", value: "esp32c2" }, { text: "ESP32-C6", value: "esp32c6" }, { text: "ESP32-H2", value: "esp32h2" }, + { text: "ESP32-P4", value: "esp32p4" }, ] }; diff --git a/docs/conf_common.py b/docs/conf_common.py index 3d82118d5..03e69fc86 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -10,6 +10,7 @@ "esp32c2", "esp32c6", "esp32h2", + "esp32p4", ] # link roles config @@ -31,27 +32,16 @@ "espsecure/*", ] -ESP32S2_DOCS = ESP32_DOCS - -ESP32C3_DOCS = ESP32S2_DOCS - -ESP32S3_DOCS = ESP32S2_DOCS - -ESP32C2_DOCS = ESP32S3_DOCS - -ESP32C6_DOCS = ESP32C2_DOCS - -ESP32H2_DOCS = ESP32C6_DOCS - conditional_include_dict = { "esp8266": ESP8266_DOCS, "esp32": ESP32_DOCS, - "esp32s2": ESP32S2_DOCS, - "esp32c3": ESP32C3_DOCS, - "esp32s3": ESP32S3_DOCS, - "esp32c2": ESP32C2_DOCS, - "esp32c6": ESP32C6_DOCS, - "esp32h2": ESP32H2_DOCS, + "esp32s2": ESP32_DOCS, + "esp32c3": ESP32_DOCS, + "esp32s3": ESP32_DOCS, + "esp32c2": ESP32_DOCS, + "esp32c6": ESP32_DOCS, + "esp32h2": ESP32_DOCS, + "esp32p4": ESP32_DOCS, } # Extra options required by sphinx_idf_theme diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index 24ba24349..da51cbacc 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -1,6 +1,6 @@ -{IDF_TARGET_STRAP_BOOT_GPIO:default="GPIO9", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0"} +{IDF_TARGET_STRAP_BOOT_GPIO:default="GPIO9", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0", esp32p4="GPIO35"} -{IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO8", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46"} +{IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO8", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46", esp32p4="GPIO36"} {IDF_TARGET_BOOTLOADER_OFFSET:default="0", esp32="1000", esp32s2="1000", esp32p4="2000"} @@ -65,13 +65,16 @@ This guide explains how to select the boot mode correctly and describes the boot The {IDF_TARGET_NAME} will enter the serial bootloader when {IDF_TARGET_STRAP_BOOT_GPIO} is held low on reset. Otherwise it will run the program in flash. - +---------------+----------------------------------------+ - | {IDF_TARGET_STRAP_BOOT_GPIO} Input | Mode | - +===============+========================================+ - | Low/GND | ROM serial bootloader for esptool | - +---------------+----------------------------------------+ - | High/VCC | Normal execution mode | - +---------------+----------------------------------------+ + .. list-table:: + :widths: 10 25 + :header-rows: 1 + + * - {IDF_TARGET_STRAP_BOOT_GPIO} Input + - Mode + * - Low/GND + - ROM serial bootloader for esptool + * - High/VCC + - Normal execution mode {IDF_TARGET_STRAP_BOOT_GPIO} has an internal pullup resistor, so if it is left unconnected then it will pull high. @@ -84,7 +87,7 @@ This guide explains how to select the boot mode correctly and describes the boot {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be either left unconnected/floating, or driven Low, in order to enter the serial bootloader. - .. only:: esp32c3 or esp32c2 or esp32h2 or esp32c6 + .. only:: esp32c3 or esp32c2 or esp32h2 or esp32c6 or esp32p4 {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be driven High, in order to enter the serial bootloader reliably. The strapping combination of {IDF_TARGET_STRAP_BOOT_2_GPIO} = 0 and {IDF_TARGET_STRAP_BOOT_GPIO} = 0 is invalid and will trigger unexpected behavior. @@ -133,13 +136,15 @@ As an example of auto-reset curcuitry implementation, check the `schematic `__. - The value can be read in {IDF_TARGET_NAME} code via the `get_reset_reason() ROM function `__. + ``rst:0xNN (REASON)`` is an enumerated value (and description) of the reason for the reset. A mapping between the hex value and each reason can be found in the `ESP-IDF source under RESET_REASON enum `__. + The value can be read in {IDF_TARGET_NAME} code via the `get_reset_reason() ROM function `__. - ``boot:0xNN (DESCRIPTION)`` is the hex value of the strapping pins, as represented in the `GPIO_STRAP register `__. + ``boot:0xNN (DESCRIPTION)`` is the hex value of the strapping pins, as represented in the `GPIO_STRAP register `__. The individual bit values are as follows: diff --git a/docs/en/advanced-topics/firmware-image-format.rst b/docs/en/advanced-topics/firmware-image-format.rst index 48cb90669..e3ebf350c 100644 --- a/docs/en/advanced-topics/firmware-image-format.rst +++ b/docs/en/advanced-topics/firmware-image-format.rst @@ -47,7 +47,7 @@ The image header is 8 bytes long: +--------+--------------------------------------------------------------------------------------------------+ -.. only:: esp32s2 or esp32s3 +.. only:: esp32s2 or esp32s3 or esp32p4 +--------+------------------------------------------------------------------------------------------------+ | Byte | Description | @@ -89,7 +89,7 @@ The image header is 8 bytes long: Flash frequency with value ``0`` can mean either 80MHz or 40MHz based on MSPI clock source mode. -.. only:: not (esp8266 or esp32c6 or esp32s3 or esp32s2) +.. only:: not (esp8266 or esp32c6 or esp32s3 or esp32s2 or esp32p4) +--------+------------------------------------------------------------------------------------------------+ | Byte | Description | diff --git a/docs/en/esptool/advanced-options.rst b/docs/en/esptool/advanced-options.rst index 83ec8c73b..a8cb4c84f 100644 --- a/docs/en/esptool/advanced-options.rst +++ b/docs/en/esptool/advanced-options.rst @@ -22,7 +22,7 @@ The ``--before`` argument allows you to specify whether the chip needs resetting * ``--before default_reset`` is the default, which uses DTR & RTS serial control lines (see :ref:`entering-the-bootloader`) to try to reset the chip into bootloader mode. * ``--before no_reset`` will skip DTR/RTS control signal assignments and just start sending a serial synchronisation command to the chip. This is useful if your chip doesn't have DTR/RTS, or for some serial interfaces (like Arduino board onboard serial) which behave differently when DTR/RTS are toggled. * ``--before no_reset_no_sync`` will skip DTR/RTS control signal assignments and skip also the serial synchronization command. This is useful if your chip is already running the :ref:`stub bootloader ` and you want to avoid resetting the chip and uploading the stub again. - :esp32c3 or esp32s3 or esp32c6 or esp32h2: * ``--before usb_reset`` will use custom reset sequence for USB-JTAG-Serial (used for example for ESP chips connected through the USB-JTAG-Serial peripheral). Usually, this option doesn't have to be used directly. Esptool should be able to detect connection through USB-JTAG-Serial. + :esp32c3 or esp32s3 or esp32c6 or esp32h2 or esp32p4: * ``--before usb_reset`` will use custom reset sequence for USB-JTAG-Serial (used for example for ESP chips connected through the USB-JTAG-Serial peripheral). Usually, this option doesn't have to be used directly. Esptool should be able to detect connection through USB-JTAG-Serial. Reset After Operation ^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/esptool/flash-modes.rst b/docs/en/esptool/flash-modes.rst index e7e10c406..b9d18686d 100644 --- a/docs/en/esptool/flash-modes.rst +++ b/docs/en/esptool/flash-modes.rst @@ -60,7 +60,7 @@ Size of the SPI flash, given in megabytes. Valid values are: ``keep``, ``detect``, ``1MB``, ``2MB``, ``4MB``, ``8MB``, ``16MB`` -.. only:: esp32s2 or esp32s3 +.. only:: esp32s2 or esp32s3 or esp32p4 Valid values are: ``keep``, ``detect``, ``1MB``, ``2MB``, ``4MB``, ``8MB``, ``16MB``, ``32MB``, ``64MB``, ``128MB`` diff --git a/docs/requirements.txt b/docs/requirements.txt index 34d2904ed..948dda348 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1 +1 @@ -esp-docs==1.4.* +esp-docs~=1.5 From 7a9de1cfad49cad76c4c5558183bbb1af8aac265 Mon Sep 17 00:00:00 2001 From: Tomas Sebestik Date: Wed, 14 Feb 2024 09:22:32 +0100 Subject: [PATCH 143/209] ci(github-actions): update ci actions for Jira integration --- .github/workflows/issue_comment.yml | 2 +- .github/workflows/new_issues.yml | 2 +- .github/workflows/new_prs.yml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/issue_comment.yml b/.github/workflows/issue_comment.yml index 200c49eca..fa1548bb1 100644 --- a/.github/workflows/issue_comment.yml +++ b/.github/workflows/issue_comment.yml @@ -10,7 +10,7 @@ jobs: steps: - uses: actions/checkout@master - name: Sync issue comments to Jira - uses: espressif/github-actions/sync_issues_to_jira@master + uses: espressif/sync-jira-actions@v1 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} JIRA_PASS: ${{ secrets.JIRA_PASS }} diff --git a/.github/workflows/new_issues.yml b/.github/workflows/new_issues.yml index f79bdcae6..fd891e342 100644 --- a/.github/workflows/new_issues.yml +++ b/.github/workflows/new_issues.yml @@ -10,7 +10,7 @@ jobs: steps: - uses: actions/checkout@master - name: Sync GitHub issues to Jira project - uses: espressif/github-actions/sync_issues_to_jira@master + uses: espressif/sync-jira-actions@v1 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} JIRA_PASS: ${{ secrets.JIRA_PASS }} diff --git a/.github/workflows/new_prs.yml b/.github/workflows/new_prs.yml index 05a56b2f5..b98e828bb 100644 --- a/.github/workflows/new_prs.yml +++ b/.github/workflows/new_prs.yml @@ -13,7 +13,7 @@ jobs: steps: - uses: actions/checkout@master - name: Sync PRs to Jira project - uses: espressif/github-actions/sync_issues_to_jira@master + uses: espressif/sync-jira-actions@v1 with: cron_job: true env: From f0cb79ae0ab23cb33c169e1cf052ad3a023bcd12 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Fri, 16 Feb 2024 17:00:55 +0200 Subject: [PATCH 144/209] feat(espefuse): Adds new efuses for esp32p4 --- espefuse/efuse/esp32p4/mem_definition.py | 11 ------ espefuse/efuse_defs/esp32p4.yaml | 44 +++++++++++++++++------- 2 files changed, 31 insertions(+), 24 deletions(-) diff --git a/espefuse/efuse/esp32p4/mem_definition.py b/espefuse/efuse/esp32p4/mem_definition.py index 1d56f8d86..73ab05e28 100644 --- a/espefuse/efuse/esp32p4/mem_definition.py +++ b/espefuse/efuse/esp32p4/mem_definition.py @@ -12,7 +12,6 @@ EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase, - Field, ) @@ -152,16 +151,6 @@ def __init__(self) -> None: self.BLOCK2_CALIBRATION_EFUSES.append(efuse) self.ALL_EFUSES[i] = None - f = Field() - f.name = "MAC_EUI64" - f.block = 1 - f.bit_len = 64 - f.type = f"bytes:{f.bit_len // 8}" - f.category = "MAC" - f.class_type = "mac" - f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" - self.CALC.append(f) - for efuse in self.ALL_EFUSES: if efuse is not None: self.EFUSES.append(efuse) diff --git a/espefuse/efuse_defs/esp32p4.yaml b/espefuse/efuse_defs/esp32p4.yaml index fe10b2eda..93d8288df 100644 --- a/espefuse/efuse_defs/esp32p4.yaml +++ b/espefuse/efuse_defs/esp32p4.yaml @@ -1,4 +1,4 @@ -VER_NO: 95ae7b662df04208c40c69564ea06a28 +VER_NO: 6b72374c237a3473c8832aadee437405 EFUSES: WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} @@ -17,8 +17,7 @@ EFUSES: USB_DEVICE_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: USB intphy of usb device signle-end input high threshold; 1.76V to 2V. Step by 80mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} USB_OTG11_DREFH : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: USB intphy of usb otg11 signle-end input high threshold; 1.76V to 2V. Step by 80mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} USB_PHY_SEL : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} - KM_HUK_GEN_STATE_LOW : {show: y, blk : 0, word: 1, pos: 26, len : 6, start : 58, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:26]', bloc: 'B7[7:2]'} - KM_HUK_GEN_STATE_HIGH : {show: y, blk : 0, word: 2, pos : 0, len : 3, start : 64, type : 'uint:3', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[2:0]', bloc: 'B8[2:0]'} + KM_HUK_GEN_STATE : {show: y, blk : 0, word: 1, pos: 26, len : 9, start : 58, type : 'uint:9', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:26]', bloc: 'B7[7:2],B8[2:0]'} KM_RND_SWITCH_CYCLE : {show: y, blk : 0, word: 2, pos : 3, len : 2, start : 67, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[4:3]', bloc: 'B8[4:3]'} KM_DEPLOY_ONLY_ONCE : {show: y, blk : 0, word: 2, pos : 5, len : 4, start : 69, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[8:5]', bloc: 'B8[7:5],B9[0]'} FORCE_USE_KEY_MANAGER_KEY : {show: y, blk : 0, word: 2, pos : 9, len : 4, start : 73, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[12:9]', bloc: 'B9[4:1]'} @@ -39,7 +38,7 @@ EFUSES: SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} ECDSA_ENABLE_SOFT_K : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} - SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} RESERVE_0_118 : {show: n, blk : 0, word: 3, pos: 22, len : 1, start: 118, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[22]', bloc: 'B14[6]'} FLASH_TYPE : {show: y, blk : 0, word: 3, pos: 23, len : 1, start: 119, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'The type of interfaced flash. 0: four data lines; 1: eight data lines', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23]', bloc: 'B14[7]'} @@ -59,10 +58,10 @@ EFUSES: SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 25, len : 1, start: 153, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'} HYS_EN_PAD : {show: y, blk : 0, word: 4, pos: 26, len : 1, start: 154, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[26]', bloc: 'B19[2]'} DCDC_VSET : {show: y, blk : 0, word: 4, pos: 27, len : 5, start: 155, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set the dcdc voltage default, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:27]', bloc: 'B19[7:3]'} - PXA0_TIEH_SEL_0 : {show: y, blk : 0, word: 5, pos : 0, len : 2, start: 160, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_0, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1:0]', bloc: 'B20[1:0]'} - PXA0_TIEH_SEL_1 : {show: y, blk : 0, word: 5, pos : 2, len : 2, start: 162, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_1, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[3:2]', bloc: 'B20[3:2]'} - PXA0_TIEH_SEL_2 : {show: y, blk : 0, word: 5, pos : 4, len : 2, start: 164, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_2, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[5:4]', bloc: 'B20[5:4]'} - PXA0_TIEH_SEL_3 : {show: y, blk : 0, word: 5, pos : 6, len : 2, start: 166, type : 'uint:2', wr_dis: null, rd_dis: null, alt : 0PXA_TIEH_SEL_3, dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[7:6]', bloc: 'B20[7:6]'} + PXA0_TIEH_SEL_0 : {show: y, blk : 0, word: 5, pos : 0, len : 2, start: 160, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1:0]', bloc: 'B20[1:0]'} + PXA0_TIEH_SEL_1 : {show: y, blk : 0, word: 5, pos : 2, len : 2, start: 162, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[3:2]', bloc: 'B20[3:2]'} + PXA0_TIEH_SEL_2 : {show: y, blk : 0, word: 5, pos : 4, len : 2, start: 164, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[5:4]', bloc: 'B20[5:4]'} + PXA0_TIEH_SEL_3 : {show: y, blk : 0, word: 5, pos : 6, len : 2, start: 166, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[7:6]', bloc: 'B20[7:6]'} KM_DISABLE_DEPLOY_MODE : {show: y, blk : 0, word: 5, pos : 8, len : 4, start: 168, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[11:8]', bloc: 'B21[3:0]'} USB_DEVICE_DREFL : {show: n, blk : 0, word: 5, pos: 12, len : 2, start: 172, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb device single-end input low threhold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13:12]', bloc: 'B21[5:4]'} USB_OTG11_DREFL : {show: n, blk : 0, word: 5, pos: 14, len : 2, start: 174, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb otg11 single-end input low threhold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[15:14]', bloc: 'B21[7:6]'} @@ -73,15 +72,34 @@ EFUSES: DIS_SWD : {show: y, blk : 0, word: 5, pos: 21, len : 1, start: 181, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable super-watchdog, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[21]', bloc: 'B22[5]'} RESERVE_0_182 : {show: n, blk : 0, word: 5, pos: 22, len : 10, start: 182, type : 'uint:10', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:22]', bloc: 'B22[7:6],B23'} MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} - MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'} - MAC_RESERVED_1 : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} - MAC_RESERVED_0 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + RESERVED_1_16 : {show: n, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'uint:16', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS_1_REG[31:16]', bloc: 'B6,B7'} + WAFER_VERSION_MINOR : {show: y, blk : 1, word: 2, pos : 0, len : 4, start : 64, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Minor chip version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[3:0]', bloc: 'B8[3:0]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 2, pos : 4, len : 2, start : 68, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Major chip version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[5:4]', bloc: 'B8[5:4]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 2, pos : 6, len : 1, start : 70, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_MAC_SYS_2_REG[6]', bloc: 'B8[6]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 1, word: 2, pos : 7, len : 1, start : 71, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_MAC_SYS_2_REG[7]', bloc: 'B8[7]'} + BLK_VERSION_MINOR : {show: y, blk : 1, word: 2, pos : 8, len : 3, start : 72, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SYS_2_REG[10:8]', bloc: 'B9[2:0]'} + BLK_VERSION_MAJOR : {show: y, blk : 1, word: 2, pos: 11, len : 2, start : 75, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SYS_2_REG[12:11]', bloc: 'B9[4:3]'} + FLASH_CAP : {show: y, blk : 1, word: 2, pos: 13, len : 3, start : 77, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Flash capacity, rloc: 'EFUSE_RD_MAC_SYS_2_REG[15:13]', bloc: 'B9[7:5]'} + FLASH_TEMP : {show: y, blk : 1, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Flash temperature, rloc: 'EFUSE_RD_MAC_SYS_2_REG[17:16]', bloc: 'B10[1:0]'} + FLASH_VENDOR : {show: y, blk : 1, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Flash vendor, rloc: 'EFUSE_RD_MAC_SYS_2_REG[20:18]', bloc: 'B10[4:2]'} + PSRAM_CAP : {show: y, blk : 1, word: 2, pos: 21, len : 2, start : 85, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PSRAM capacity, rloc: 'EFUSE_RD_MAC_SYS_2_REG[22:21]', bloc: 'B10[6:5]'} + PSRAM_TEMP : {show: y, blk : 1, word: 2, pos: 23, len : 2, start : 87, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PSRAM temperature, rloc: 'EFUSE_RD_MAC_SYS_2_REG[24:23]', bloc: 'B10[7],B11[0]'} + PSRAM_VENDOR : {show: y, blk : 1, word: 2, pos: 25, len : 2, start : 89, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PSRAM vendor, rloc: 'EFUSE_RD_MAC_SYS_2_REG[26:25]', bloc: 'B11[2:1]'} + PKG_VERSION : {show: y, blk : 1, word: 2, pos: 27, len : 3, start : 91, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS_2_REG[29:27]', bloc: 'B11[5:3]'} + RESERVED_1_94 : {show: n, blk : 1, word: 2, pos: 30, len : 2, start : 94, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS_2_REG[31:30]', bloc: 'B11[7:6]'} MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} SYS_DATA_PART0_0 : {show: n, blk : 1, word: 3, pos: 18, len : 14, start: 114, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first 14 bits of the zeroth part of system data, rloc: 'EFUSE_RD_MAC_SYS_3_REG[31:18]', bloc: 'B14[7:2],B15'} SYS_DATA_PART0_1 : {show: n, blk : 1, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_4_REG, bloc: 'B16,B17,B18,B19'} SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SYS_5_REG, bloc: 'B20,B21,B22,B23'} - BLOCK_SYS_DATA1 : {show: y, blk : 2, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 21, rd_dis: null, alt : SYS_DATA_PART1, dict : '', desc: System data part 1, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} - BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + SYS_DATA_PART1_4 : {show: n, blk : 2, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the fourth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA4_REG, bloc: 'B16,B17,B18,B19'} + SYS_DATA_PART1_5 : {show: n, blk : 2, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the fifth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA5_REG, bloc: 'B20,B21,B22,B23'} + SYS_DATA_PART1_6 : {show: n, blk : 2, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the sixth 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA6_REG, bloc: 'B24,B25,B26,B27'} + SYS_DATA_PART1_7 : {show: n, blk : 2, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Stores the seventh 32 bits of the first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA7_REG, bloc: 'B28,B29,B30,B31'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} From 0d981da8d45f1ee057e099f2916788f39a7f7792 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 15 Feb 2024 18:44:41 +0200 Subject: [PATCH 145/209] feat(espefuse): Update adc_info commands for all chips --- espefuse/efuse/esp32c2/operations.py | 19 ++++----- espefuse/efuse/esp32c3/operations.py | 40 +++++------------- espefuse/efuse/esp32c5beta3/operations.py | 27 +----------- espefuse/efuse/esp32c6/operations.py | 36 ++++++++-------- espefuse/efuse/esp32h2/operations.py | 31 +++++++------- espefuse/efuse/esp32h2beta1/fields.py | 2 +- espefuse/efuse/esp32h2beta1/operations.py | 47 ++++++++------------- espefuse/efuse/esp32s2/operations.py | 49 +++++++++------------- espefuse/efuse/esp32s3/operations.py | 50 +++++++++-------------- espefuse/efuse/esp32s3beta2/operations.py | 50 +++++++++-------------- test/test_espefuse.py | 11 +++++ 11 files changed, 138 insertions(+), 224 deletions(-) diff --git a/espefuse/efuse/esp32c2/operations.py b/espefuse/efuse/esp32c2/operations.py index fb7324e97..d23f6a721 100644 --- a/espefuse/efuse/esp32c2/operations.py +++ b/espefuse/efuse/esp32c2/operations.py @@ -153,18 +153,13 @@ def adc_info(esp, efuses, args): print("") # fmt: off if efuses["BLK_VERSION_MINOR"].get() == 1: - print(" RF_REF_I_BIAS_CONFIG: {}".format(efuses["RF_REF_I_BIAS_CONFIG"].get())) - - print(" LDO_VOL_BIAS_CONFIG_LOW: {}".format(efuses["LDO_VOL_BIAS_CONFIG_LOW"].get())) - print(" LDO_VOL_BIAS_CONFIG_HIGH: {}".format(efuses["LDO_VOL_BIAS_CONFIG_HIGH"].get())) - - print(" PVT_LOW: {}".format(efuses["PVT_LOW"].get())) - print(" PVT_HIGH: {}".format(efuses["PVT_HIGH"].get())) - - print(" ADC_CALIBRATION_0: {}".format(efuses["ADC_CALIBRATION_0"].get())) - print(" ADC_CALIBRATION_1: {}".format(efuses["ADC_CALIBRATION_1"].get())) - print(" ADC_CALIBRATION_2: {}".format(efuses["ADC_CALIBRATION_2"].get())) - + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + print("ADC OCode = ", efuses["OCODE"].get()) + print("ADC1:") + print("INIT_CODE_ATTEN0 = ", efuses["ADC1_INIT_CODE_ATTEN0"].get()) + print("INIT_CODE_ATTEN3 = ", efuses["ADC1_INIT_CODE_ATTEN3"].get()) + print("CAL_VOL_ATTEN0 = ", efuses["ADC1_CAL_VOL_ATTEN0"].get()) + print("CAL_VOL_ATTEN3 = ", efuses["ADC1_CAL_VOL_ATTEN3"].get()) else: print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) # fmt: on diff --git a/espefuse/efuse/esp32c3/operations.py b/espefuse/efuse/esp32c3/operations.py index 59f446904..ff6310957 100644 --- a/espefuse/efuse/esp32c3/operations.py +++ b/espefuse/efuse/esp32c3/operations.py @@ -195,35 +195,17 @@ def adc_info(esp, efuses, args): print("") # fmt: off if efuses["BLK_VERSION_MAJOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) - - print("") - print("ADC1 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC1_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC1_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC1_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC1_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC1_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC1_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC1_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC1_MODE3_D2"].get())) - - print("") - print("ADC2 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC2_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC2_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC2_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC2_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC2_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC2_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + print("ADC OCode = ", efuses["OCODE"].get()) + print("ADC1:") + print("INIT_CODE_ATTEN0 = ", efuses["ADC1_INIT_CODE_ATTEN0"].get()) + print("INIT_CODE_ATTEN1 = ", efuses["ADC1_INIT_CODE_ATTEN1"].get()) + print("INIT_CODE_ATTEN2 = ", efuses["ADC1_INIT_CODE_ATTEN2"].get()) + print("INIT_CODE_ATTEN3 = ", efuses["ADC1_INIT_CODE_ATTEN3"].get()) + print("CAL_VOL_ATTEN0 = ", efuses["ADC1_CAL_VOL_ATTEN0"].get()) + print("CAL_VOL_ATTEN1 = ", efuses["ADC1_CAL_VOL_ATTEN1"].get()) + print("CAL_VOL_ATTEN2 = ", efuses["ADC1_CAL_VOL_ATTEN2"].get()) + print("CAL_VOL_ATTEN3 = ", efuses["ADC1_CAL_VOL_ATTEN3"].get()) else: print("BLK_VERSION_MAJOR = {}".format(efuses["BLK_VERSION_MAJOR"].get_meaning())) # fmt: on diff --git a/espefuse/efuse/esp32c5beta3/operations.py b/espefuse/efuse/esp32c5beta3/operations.py index ed97563a7..8ad39340f 100644 --- a/espefuse/efuse/esp32c5beta3/operations.py +++ b/espefuse/efuse/esp32c5beta3/operations.py @@ -192,32 +192,7 @@ def set_flash_voltage(esp, efuses, args): def adc_info(esp, efuses, args): - print("") - # fmt: off - if efuses["BLK_VERSION_MINOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) - - print("") - print("ADC1 Calibration data stored in efuse BLOCK2:") - print(f"OCODE: {efuses['OCODE'].get()}") - print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") - print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") - print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") - print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") - print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") - print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") - print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") - print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") - print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") - print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") - print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") - print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") - print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") - print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") - print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") - else: - print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) - # fmt: on + print("not supported yet") def burn_key(esp, efuses, args, digest=None): diff --git a/espefuse/efuse/esp32c6/operations.py b/espefuse/efuse/esp32c6/operations.py index f8e450fa0..9307ecac3 100644 --- a/espefuse/efuse/esp32c6/operations.py +++ b/espefuse/efuse/esp32c6/operations.py @@ -196,25 +196,23 @@ def adc_info(esp, efuses, args): # fmt: off if efuses["BLK_VERSION_MINOR"].get() == 1: print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) - - print("") - print("ADC1 Calibration data stored in efuse BLOCK2:") - print(f"OCODE: {efuses['OCODE'].get()}") - print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") - print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") - print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") - print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") - print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") - print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") - print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") - print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") - print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") - print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") - print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") - print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") - print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") - print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") - print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") + print("ADC OCode = ", efuses["OCODE"].get()) + print("ADC1:") + print("INIT_CODE_ATTEN0 = ", efuses['ADC1_INIT_CODE_ATTEN0'].get()) + print("INIT_CODE_ATTEN1 = ", efuses['ADC1_INIT_CODE_ATTEN1'].get()) + print("INIT_CODE_ATTEN2 = ", efuses['ADC1_INIT_CODE_ATTEN2'].get()) + print("INIT_CODE_ATTEN3 = ", efuses['ADC1_INIT_CODE_ATTEN3'].get()) + print("CAL_VOL_ATTEN0 = ", efuses['ADC1_CAL_VOL_ATTEN0'].get()) + print("CAL_VOL_ATTEN1 = ", efuses['ADC1_CAL_VOL_ATTEN1'].get()) + print("CAL_VOL_ATTEN2 = ", efuses['ADC1_CAL_VOL_ATTEN2'].get()) + print("CAL_VOL_ATTEN3 = ", efuses['ADC1_CAL_VOL_ATTEN3'].get()) + print("INIT_CODE_ATTEN0_CH0 = ", efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()) + print("INIT_CODE_ATTEN0_CH1 = ", efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()) + print("INIT_CODE_ATTEN0_CH2 = ", efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()) + print("INIT_CODE_ATTEN0_CH3 = ", efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()) + print("INIT_CODE_ATTEN0_CH4 = ", efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()) + print("INIT_CODE_ATTEN0_CH5 = ", efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()) + print("INIT_CODE_ATTEN0_CH6 = ", efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()) else: print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) # fmt: on diff --git a/espefuse/efuse/esp32h2/operations.py b/espefuse/efuse/esp32h2/operations.py index 6debd0911..2aac7448b 100644 --- a/espefuse/efuse/esp32h2/operations.py +++ b/espefuse/efuse/esp32h2/operations.py @@ -195,24 +195,21 @@ def adc_info(esp, efuses, args): # fmt: off if efuses["BLK_VERSION_MINOR"].get() == 2: print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) - print("") - print("ADC1 readings stored in efuse BLOCK2:") - print(" AVE_INITCODE_ATTEN0: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN0"].get())) - print(" AVE_INITCODE_ATTEN1: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN1"].get())) - print(" AVE_INITCODE_ATTEN2: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN2"].get())) - print(" AVE_INITCODE_ATTEN3: {}".format(efuses["ADC1_AVE_INITCODE_ATTEN3"].get())) - - print(" HI_DOUT_ATTEN0: {}".format(efuses["ADC1_HI_DOUT_ATTEN0"].get())) - print(" HI_DOUT_ATTEN1: {}".format(efuses["ADC1_HI_DOUT_ATTEN1"].get())) - print(" HI_DOUT_ATTEN2: {}".format(efuses["ADC1_HI_DOUT_ATTEN2"].get())) - print(" HI_DOUT_ATTEN3: {}".format(efuses["ADC1_HI_DOUT_ATTEN3"].get())) - - print(" CH0_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH0_ATTEN0_INITCODE_DIFF"].get())) - print(" CH1_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH1_ATTEN0_INITCODE_DIFF"].get())) - print(" CH2_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH2_ATTEN0_INITCODE_DIFF"].get())) - print(" CH3_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH3_ATTEN0_INITCODE_DIFF"].get())) - print(" CH4_ATTEN0_INITCODE_DIFF: {}".format(efuses["ADC1_CH4_ATTEN0_INITCODE_DIFF"].get())) + print("ADC1:") + print("AVE_INITCODE_ATTEN0 = ", efuses["ADC1_AVE_INITCODE_ATTEN0"].get()) + print("AVE_INITCODE_ATTEN1 = ", efuses["ADC1_AVE_INITCODE_ATTEN1"].get()) + print("AVE_INITCODE_ATTEN2 = ", efuses["ADC1_AVE_INITCODE_ATTEN2"].get()) + print("AVE_INITCODE_ATTEN3 = ", efuses["ADC1_AVE_INITCODE_ATTEN3"].get()) + print("HI_DOUT_ATTEN0 = ", efuses["ADC1_HI_DOUT_ATTEN0"].get()) + print("HI_DOUT_ATTEN1 = ", efuses["ADC1_HI_DOUT_ATTEN1"].get()) + print("HI_DOUT_ATTEN2 = ", efuses["ADC1_HI_DOUT_ATTEN2"].get()) + print("HI_DOUT_ATTEN3 = ", efuses["ADC1_HI_DOUT_ATTEN3"].get()) + print("CH0_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH0_ATTEN0_INITCODE_DIFF"].get()) + print("CH1_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH1_ATTEN0_INITCODE_DIFF"].get()) + print("CH2_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH2_ATTEN0_INITCODE_DIFF"].get()) + print("CH3_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH3_ATTEN0_INITCODE_DIFF"].get()) + print("CH4_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH4_ATTEN0_INITCODE_DIFF"].get()) else: print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get())) # fmt: on diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index 16bc78f04..165734989 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -95,7 +95,7 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLK_VERSION_MAJOR"].get() == 1: + if self["BLK_VERSION_MINOR"].get() == 2: self.efuses += [ EfuseField.convert(self, efuse) for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES diff --git a/espefuse/efuse/esp32h2beta1/operations.py b/espefuse/efuse/esp32h2beta1/operations.py index 9f602544a..f884b8aa5 100644 --- a/espefuse/efuse/esp32h2beta1/operations.py +++ b/espefuse/efuse/esp32h2beta1/operations.py @@ -193,38 +193,25 @@ def set_flash_voltage(esp, efuses, args): def adc_info(esp, efuses, args): print("") # fmt: off - if efuses["BLK_VERSION_MAJOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) - + if efuses["BLK_VERSION_MINOR"].get() == 2: + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) print("") - print("ADC1 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC1_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC1_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC1_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC1_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC1_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC1_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC1_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC1_MODE3_D2"].get())) - - print("") - print("ADC2 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC2_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC2_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC2_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC2_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC2_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC2_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) + print("ADC1:") + print("AVE_INITCODE_ATTEN0 = ", efuses["ADC1_AVE_INITCODE_ATTEN0"].get()) + print("AVE_INITCODE_ATTEN1 = ", efuses["ADC1_AVE_INITCODE_ATTEN1"].get()) + print("AVE_INITCODE_ATTEN2 = ", efuses["ADC1_AVE_INITCODE_ATTEN2"].get()) + print("AVE_INITCODE_ATTEN3 = ", efuses["ADC1_AVE_INITCODE_ATTEN3"].get()) + print("HI_DOUT_ATTEN0 = ", efuses["ADC1_HI_DOUT_ATTEN0"].get()) + print("HI_DOUT_ATTEN1 = ", efuses["ADC1_HI_DOUT_ATTEN1"].get()) + print("HI_DOUT_ATTEN2 = ", efuses["ADC1_HI_DOUT_ATTEN2"].get()) + print("HI_DOUT_ATTEN3 = ", efuses["ADC1_HI_DOUT_ATTEN3"].get()) + print("CH0_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH0_ATTEN0_INITCODE_DIFF"].get()) + print("CH1_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH1_ATTEN0_INITCODE_DIFF"].get()) + print("CH2_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH2_ATTEN0_INITCODE_DIFF"].get()) + print("CH3_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH3_ATTEN0_INITCODE_DIFF"].get()) + print("CH4_ATTEN0_INITCODE_DIFF = ", efuses["ADC1_CH4_ATTEN0_INITCODE_DIFF"].get()) else: - print("BLK_VERSION_MAJOR = {}".format(efuses["BLK_VERSION_MAJOR"].get_meaning())) + print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get())) # fmt: on diff --git a/espefuse/efuse/esp32s2/operations.py b/espefuse/efuse/esp32s2/operations.py index 5ccfac3c9..3f015e221 100644 --- a/espefuse/efuse/esp32s2/operations.py +++ b/espefuse/efuse/esp32s2/operations.py @@ -238,37 +238,26 @@ def adc_info(esp, efuses, args): print("") # fmt: off if efuses["BLK_VERSION_MINOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) - - print("") - print("ADC1 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC1_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC1_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC1_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC1_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC1_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC1_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC1_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC1_MODE3_D2"].get())) - - print("") - print("ADC2 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC2_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC2_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC2_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC2_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC2_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC2_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + print("TADC_CALIB = {}C".format(efuses["ADC_CALIB"].get())) + print("RTCCALIB_V1IDX_A10H = ", efuses["RTCCALIB_V1IDX_A10H"].get()) + print("RTCCALIB_V1IDX_A11H = ", efuses["RTCCALIB_V1IDX_A11H"].get()) + print("RTCCALIB_V1IDX_A12H = ", efuses["RTCCALIB_V1IDX_A12H"].get()) + print("RTCCALIB_V1IDX_A13H = ", efuses["RTCCALIB_V1IDX_A13H"].get()) + print("RTCCALIB_V1IDX_A20H = ", efuses["RTCCALIB_V1IDX_A20H"].get()) + print("RTCCALIB_V1IDX_A21H = ", efuses["RTCCALIB_V1IDX_A21H"].get()) + print("RTCCALIB_V1IDX_A22H = ", efuses["RTCCALIB_V1IDX_A22H"].get()) + print("RTCCALIB_V1IDX_A23H = ", efuses["RTCCALIB_V1IDX_A23H"].get()) + print("RTCCALIB_V1IDX_A10L = ", efuses["RTCCALIB_V1IDX_A10L"].get()) + print("RTCCALIB_V1IDX_A11L = ", efuses["RTCCALIB_V1IDX_A11L"].get()) + print("RTCCALIB_V1IDX_A12L = ", efuses["RTCCALIB_V1IDX_A12L"].get()) + print("RTCCALIB_V1IDX_A13L = ", efuses["RTCCALIB_V1IDX_A13L"].get()) + print("RTCCALIB_V1IDX_A20L = ", efuses["RTCCALIB_V1IDX_A20L"].get()) + print("RTCCALIB_V1IDX_A21L = ", efuses["RTCCALIB_V1IDX_A21L"].get()) + print("RTCCALIB_V1IDX_A22L = ", efuses["RTCCALIB_V1IDX_A22L"].get()) + print("RTCCALIB_V1IDX_A23L = ", efuses["RTCCALIB_V1IDX_A23L"].get()) else: - print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) + print("BLK_VERSION_MINOR = ", efuses["BLK_VERSION_MINOR"].get_meaning()) # fmt: on diff --git a/espefuse/efuse/esp32s3/operations.py b/espefuse/efuse/esp32s3/operations.py index 9331374da..912ae3f0c 100644 --- a/espefuse/efuse/esp32s3/operations.py +++ b/espefuse/efuse/esp32s3/operations.py @@ -237,37 +237,27 @@ def adc_info(esp, efuses, args): print("") # fmt: off if efuses["BLK_VERSION_MAJOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) - - print("") - print("ADC1 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC1_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC1_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC1_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC1_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC1_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC1_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC1_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC1_MODE3_D2"].get())) - - print("") - print("ADC2 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC2_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC2_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC2_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC2_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC2_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC2_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + print("ADC OCode = ", efuses["OCODE"].get()) + print("ADC1:") + print("INIT_CODE_ATTEN0 = ", efuses["ADC1_INIT_CODE_ATTEN0"].get()) + print("INIT_CODE_ATTEN1 = ", efuses["ADC1_INIT_CODE_ATTEN1"].get()) + print("INIT_CODE_ATTEN2 = ", efuses["ADC1_INIT_CODE_ATTEN2"].get()) + print("INIT_CODE_ATTEN3 = ", efuses["ADC1_INIT_CODE_ATTEN3"].get()) + print("CAL_VOL_ATTEN0 = ", efuses["ADC1_CAL_VOL_ATTEN0"].get()) + print("CAL_VOL_ATTEN1 = ", efuses["ADC1_CAL_VOL_ATTEN1"].get()) + print("CAL_VOL_ATTEN2 = ", efuses["ADC1_CAL_VOL_ATTEN2"].get()) + print("CAL_VOL_ATTEN3 = ", efuses["ADC1_CAL_VOL_ATTEN3"].get()) + print("ADC2:") + print("INIT_CODE_ATTEN0 = ", efuses["ADC2_INIT_CODE_ATTEN0"].get()) + print("INIT_CODE_ATTEN1 = ", efuses["ADC2_INIT_CODE_ATTEN1"].get()) + print("INIT_CODE_ATTEN2 = ", efuses["ADC2_INIT_CODE_ATTEN2"].get()) + print("INIT_CODE_ATTEN3 = ", efuses["ADC2_INIT_CODE_ATTEN3"].get()) + print("CAL_VOL_ATTEN0 = ", efuses["ADC2_CAL_VOL_ATTEN0"].get()) + print("CAL_VOL_ATTEN1 = ", efuses["ADC2_CAL_VOL_ATTEN1"].get()) + print("CAL_VOL_ATTEN2 = ", efuses["ADC2_CAL_VOL_ATTEN2"].get()) else: - print("BLK_VERSION_MAJOR = {}".format(efuses["BLK_VERSION_MAJOR"].get_meaning())) + print("BLK_VERSION_MAJOR = ", efuses["BLK_VERSION_MAJOR"].get_meaning()) # fmt: on diff --git a/espefuse/efuse/esp32s3beta2/operations.py b/espefuse/efuse/esp32s3beta2/operations.py index e17d773e1..229a92902 100644 --- a/espefuse/efuse/esp32s3beta2/operations.py +++ b/espefuse/efuse/esp32s3beta2/operations.py @@ -237,37 +237,27 @@ def adc_info(esp, efuses, args): print("") # fmt: off if efuses["BLK_VERSION_MAJOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_SENSOR_CAL"].get())) - - print("") - print("ADC1 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC1_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC1_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC1_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC1_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC1_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC1_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC1_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC1_MODE3_D2"].get())) - - print("") - print("ADC2 readings stored in efuse BLOCK2:") - print(" MODE0 D1 reading (250mV): {}".format(efuses["ADC2_MODE0_D1"].get())) - print(" MODE0 D2 reading (600mV): {}".format(efuses["ADC2_MODE0_D2"].get())) - - print(" MODE1 D1 reading (250mV): {}".format(efuses["ADC2_MODE1_D1"].get())) - print(" MODE1 D2 reading (800mV): {}".format(efuses["ADC2_MODE1_D2"].get())) - - print(" MODE2 D1 reading (250mV): {}".format(efuses["ADC2_MODE2_D1"].get())) - print(" MODE2 D2 reading (1000mV): {}".format(efuses["ADC2_MODE2_D2"].get())) - - print(" MODE3 D1 reading (250mV): {}".format(efuses["ADC2_MODE3_D1"].get())) - print(" MODE3 D2 reading (2000mV): {}".format(efuses["ADC2_MODE3_D2"].get())) + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + print("ADC OCode = ", efuses["OCODE"].get()) + print("ADC1:") + print("INIT_CODE_ATTEN0 = ", efuses["ADC1_INIT_CODE_ATTEN0"].get()) + print("INIT_CODE_ATTEN1 = ", efuses["ADC1_INIT_CODE_ATTEN1"].get()) + print("INIT_CODE_ATTEN2 = ", efuses["ADC1_INIT_CODE_ATTEN2"].get()) + print("INIT_CODE_ATTEN3 = ", efuses["ADC1_INIT_CODE_ATTEN3"].get()) + print("CAL_VOL_ATTEN0 = ", efuses["ADC1_CAL_VOL_ATTEN0"].get()) + print("CAL_VOL_ATTEN1 = ", efuses["ADC1_CAL_VOL_ATTEN1"].get()) + print("CAL_VOL_ATTEN2 = ", efuses["ADC1_CAL_VOL_ATTEN2"].get()) + print("CAL_VOL_ATTEN3 = ", efuses["ADC1_CAL_VOL_ATTEN3"].get()) + print("ADC2:") + print("INIT_CODE_ATTEN0 = ", efuses["ADC2_INIT_CODE_ATTEN0"].get()) + print("INIT_CODE_ATTEN1 = ", efuses["ADC2_INIT_CODE_ATTEN1"].get()) + print("INIT_CODE_ATTEN2 = ", efuses["ADC2_INIT_CODE_ATTEN2"].get()) + print("INIT_CODE_ATTEN3 = ", efuses["ADC2_INIT_CODE_ATTEN3"].get()) + print("CAL_VOL_ATTEN0 = ", efuses["ADC2_CAL_VOL_ATTEN0"].get()) + print("CAL_VOL_ATTEN1 = ", efuses["ADC2_CAL_VOL_ATTEN1"].get()) + print("CAL_VOL_ATTEN2 = ", efuses["ADC2_CAL_VOL_ATTEN2"].get()) else: - print("BLK_VERSION_MAJOR = {}".format(efuses["BLK_VERSION_MAJOR"].get_meaning())) + print("BLK_VERSION_MAJOR = ", efuses["BLK_VERSION_MAJOR"].get_meaning()) # fmt: on diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 514be6e8c..04e259132 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -198,6 +198,17 @@ def test_adc_info(self): self.espefuse_py("adc_info -h") self.espefuse_py("adc_info") + def test_adc_info_2(self): + if arg_chip == "esp32": + self.espefuse_py("burn_efuse BLK3_PART_RESERVE 1") + elif arg_chip in ["esp32c3", "esp32s3", "esp32s3beta2"]: + self.espefuse_py("burn_efuse BLK_VERSION_MAJOR 1") + elif arg_chip in ["esp32c2", "esp32s2", "esp32c6"]: + self.espefuse_py("burn_efuse BLK_VERSION_MINOR 1") + elif arg_chip in ["esp32h2", "esp32h2beta1"]: + self.espefuse_py("burn_efuse BLK_VERSION_MINOR 2") + self.espefuse_py("adc_info") + def test_check_error(self): self.espefuse_py("check_error -h") self.espefuse_py("check_error") From 13cf59f2b810eed4afcb32668ddc931fa429760e Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 16 Feb 2024 13:26:26 +0100 Subject: [PATCH 146/209] ci: add pre-commit hook for codespell --- .codespellrc | 4 ++++ .pre-commit-config.yaml | 4 ++++ CONTRIBUTING.rst | 8 ++++++++ 3 files changed, 16 insertions(+) create mode 100644 .codespellrc diff --git a/.codespellrc b/.codespellrc new file mode 100644 index 000000000..3f052e961 --- /dev/null +++ b/.codespellrc @@ -0,0 +1,4 @@ +[codespell] +skip = *.bin,test/images/efuse/*,docs/en/espefuse/inc/* +ignore-words-list = bloc,ser,dout,exten +write-changes = false diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index d5d84e8a3..464843542 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -11,6 +11,10 @@ repos: - id: sphinx-lint name: Lint RST files in docs folder using Sphinx Lint files: ^((docs/en)/.*\.(rst|inc))|CONTRIBUTING.rst$ + - repo: https://github.com/codespell-project/codespell + rev: v2.2.5 + hooks: + - id: codespell - repo: https://github.com/espressif/conventional-precommit-linter rev: v1.4.0 hooks: diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index a9eb83104..721024583 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -109,6 +109,14 @@ Shinx-lint The documentation is checked for stylistic and formal issues by ``sphinx-lint``. + +Codespell check +""""""""""""""" + +This repository utilizes an automatic `spell checker `_ integrated into the pre-commit process. If any spelling issues are detected, the recommended corrections will be applied automatically to the file, ready for commit. +In the event of false positives, you can adjust the configuration in the `.codespell.rc`. To exclude files from the spell check, utilize the `skip` keyword followed by comma-separated paths to the files (wildcards are supported). Additionally, to exclude specific words from the spell check, employ the `ignore-words-list` keyword followed by comma-separated words to be skipped. + + Automated Integration Tests ^^^^^^^^^^^^^^^^^^^^^^^^^^^ From dca10bc9ea8052d40522ac50dba0348d13144568 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 16 Feb 2024 13:40:19 +0100 Subject: [PATCH 147/209] change: fix typos and spelling errors by codespell --- CONTRIBUTING.rst | 4 ++-- docs/en/advanced-topics/serial-protocol.rst | 2 +- docs/en/espefuse/burn-key-cmd.rst | 6 +++--- docs/en/espefuse/read-write-protections-cmd.rst | 2 +- docs/en/esptool/advanced-commands.rst | 2 +- docs/en/installation.rst | 2 +- esp_rfc2217_server.py | 2 +- espefuse/efuse/base_fields.py | 4 ++-- espefuse/efuse_defs/esp32c6.yaml | 4 ++-- espefuse/efuse_defs/esp32h2.yaml | 4 ++-- espefuse/efuse_defs/esp32p4.yaml | 4 ++-- esptool/__init__.py | 2 +- esptool/cmds.py | 2 +- esptool/loader.py | 4 ++-- esptool/targets/esp32.py | 2 +- esptool/targets/esp32c2.py | 2 +- flasher_stub/Makefile | 2 +- flasher_stub/include/miniz.h | 6 +++--- flasher_stub/include/soc_support.h | 2 +- flasher_stub/stub_flasher.c | 4 ++-- test/elf2image/esp32-too-many-sections/Makefile | 2 +- test/images/ram_helloworld/source/Makefile | 2 +- test/test_espefuse.py | 6 +++--- test/test_esptool.py | 16 +++++++++------- test/test_imagegen.py | 4 ++-- test/test_merge_bin.py | 2 +- test/test_uf2_ids.py | 2 +- 27 files changed, 49 insertions(+), 47 deletions(-) diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index 721024583..11ec9aec4 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -96,7 +96,7 @@ Conventional Commits Ruff """" -``esptool.py`` is `PEP8 `_ compliant and enforces this style guide. For compliancy checking, we use `ruff `_. +``esptool.py`` is `PEP8 `_ compliant and enforces this style guide. For compliance checking, we use `ruff `_. ``Ruff`` also auto-format files in the same style as previously used ``black``. @@ -131,7 +131,7 @@ The following tests run automatically by GitHub Actions for each Pull Request. Y * ``test_mergebin.py`` tests the ``merge_bin`` command * ``test_modules.py`` tests the modules used by ``esptool.py`` for regressions * ``test_espsecure.py`` tests ``espsecure.py`` functionality -* ``test_espsecure_hsm.py`` tests support of extarnal HSM signing in ``espsecure.py``. These tests require additional prerequisites, see ``SoftHSM2 setup`` in the `tests workflow definition `_ for more information. +* ``test_espsecure_hsm.py`` tests support of external HSM signing in ``espsecure.py``. These tests require additional prerequisites, see ``SoftHSM2 setup`` in the `tests workflow definition `_ for more information. The following tests are not run automatically by GitHub Actions, because they need real connected hardware. Therefore, they need to be run locally in a command line: diff --git a/docs/en/advanced-topics/serial-protocol.rst b/docs/en/advanced-topics/serial-protocol.rst index 90b0b9932..48c85eec9 100644 --- a/docs/en/advanced-topics/serial-protocol.rst +++ b/docs/en/advanced-topics/serial-protocol.rst @@ -265,7 +265,7 @@ Supported by stub loader only ROM loaders will not recognise these commands. +------------+-------------------+-----------------------------------+-------------------------------------------------------------------------------------------------------------------------+----------+ -| Byte | Name | Descripton | Input | Output | +| Byte | Name | Description | Input | Output | +============+===================+===================================+=========================================================================================================================+==========+ | ``0xd0`` | ERASE_FLASH | Erase entire flash chip | | | +------------+-------------------+-----------------------------------+-------------------------------------------------------------------------------------------------------------------------+----------+ diff --git a/docs/en/espefuse/burn-key-cmd.rst b/docs/en/espefuse/burn-key-cmd.rst index 92922519e..c6a7714c2 100644 --- a/docs/en/espefuse/burn-key-cmd.rst +++ b/docs/en/espefuse/burn-key-cmd.rst @@ -42,14 +42,14 @@ Optional arguments: .. only:: esp32 - {IDF_TARGET_NAME} supportes keys: + {IDF_TARGET_NAME} supports keys: * Secure boot key. Use ``secure_boot_v1`` or ``secure_boot_v2`` as block name. The key is placed in BLOCK2. * Flash encryption key. Use ``flash_encryption`` as block name. The key is placed in BLOCK1. Keys for ``flash_encryption`` and ``secure_boot_v1`` will be burned as read and write protected. The hardware will still have access to them. These keys are burned in reversed byte order. - Key for ``secure_boot_v2`` will be burned only as write protected. The key must be readable because the software need acces to it. + Key for ``secure_boot_v2`` will be burned only as write protected. The key must be readable because the software need access to it. .. warning:: @@ -57,7 +57,7 @@ Optional arguments: .. only:: not esp32 and not esp32c2 - {IDF_TARGET_NAME} supportes eFuse key purposes. This means that each eFuse block has a special eFuse field that indicates which key is in the eFuse block. During the burn operation this eFuse key purpose is burned as well with write protection (the ``--no-write-protect`` flag has no effect on this field). The {IDF_TARGET_NAME} chip supports the following key purposes: + {IDF_TARGET_NAME} supports eFuse key purposes. This means that each eFuse block has a special eFuse field that indicates which key is in the eFuse block. During the burn operation this eFuse key purpose is burned as well with write protection (the ``--no-write-protect`` flag has no effect on this field). The {IDF_TARGET_NAME} chip supports the following key purposes: .. list:: diff --git a/docs/en/espefuse/read-write-protections-cmd.rst b/docs/en/espefuse/read-write-protections-cmd.rst index 3ae6f740e..e1611e538 100644 --- a/docs/en/espefuse/read-write-protections-cmd.rst +++ b/docs/en/espefuse/read-write-protections-cmd.rst @@ -10,7 +10,7 @@ There are two commands (to get the correct list of eFuse fields that can be prot Positional arguments: -- eFuse name. It can recieve a list of eFuse names (like EFUSE_NAME1 EFUSE_NAME2 etc.). +- eFuse name. It can receive a list of eFuse names (like EFUSE_NAME1 EFUSE_NAME2 etc.). Read protection prevents software from reading eFuse fields, only hardware can access such eFuses. Such eFuses are read as zero and the data is marked as ``??`` in this tool. diff --git a/docs/en/esptool/advanced-commands.rst b/docs/en/esptool/advanced-commands.rst index d19309497..caa54c5e4 100644 --- a/docs/en/esptool/advanced-commands.rst +++ b/docs/en/esptool/advanced-commands.rst @@ -94,7 +94,7 @@ The ``--bytes`` argument determines how many status register bytes are read. .. note:: - Not all flash chips support all of these comands. Consult the specific flash chip datasheet for details. + Not all flash chips support all of these commands. Consult the specific flash chip datasheet for details. .. _write-flash-status: diff --git a/docs/en/installation.rst b/docs/en/installation.rst index 4fcfc1ea2..3a3828b8c 100644 --- a/docs/en/installation.rst +++ b/docs/en/installation.rst @@ -63,7 +63,7 @@ As a Component If ``esptool.py`` is installed as a component of a development framework (e.g. `ESP-IDF `_, `Arduino `_, or `PlatformIO `_), it is advised to follow the update guide of used framework for instructions and not to update the tool directly. -If updating directly is unavoidable, make sure you update to a compatible version by staying on the same MAJOR version number (explaned in the :ref:`versions` article). For instance, if your currently installed ``esptool.py`` is ``v3.3.1``, only update to ``v3.*.*``. You risk introducing incompatible changes by updating to ``v4.*.*`` or higher. +If updating directly is unavoidable, make sure you update to a compatible version by staying on the same MAJOR version number (explained in the :ref:`versions` article). For instance, if your currently installed ``esptool.py`` is ``v3.3.1``, only update to ``v3.*.*``. You risk introducing incompatible changes by updating to ``v4.*.*`` or higher. :: diff --git a/esp_rfc2217_server.py b/esp_rfc2217_server.py index cf83a183b..7beaa610b 100755 --- a/esp_rfc2217_server.py +++ b/esp_rfc2217_server.py @@ -9,7 +9,7 @@ # This is a modified version of rfc2217_server.py provided by the pyserial package # (pythonhosted.org/pyserial/examples.html#single-port-tcp-ip-serial-bridge-rfc-2217). # It uses a custom PortManager to properly apply the RTS & DTR signals -# for reseting ESP chips. +# for resetting ESP chips. # # Run the following command on the server side to make # connection between /dev/ttyUSB1 and TCP port 4000: diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index 13ce90b2c..4cecd09d2 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -317,7 +317,7 @@ def check_wr_data(self): if rd_chunk == wr_chunk: print( "wr_chunk == rd_chunk. " - "Countinue with empty chunk." + "Continue with empty chunk." ) wr_data[i : i + 6 * 8 :].set(0) else: @@ -736,7 +736,7 @@ def check_new_value(self, bitarray_new_value): else: if self.name not in ["WR_DIS", "RD_DIS"]: # WR_DIS, RD_DIS fields can have already set bits. - # Do not neeed to check below condition for them. + # Do not need to check below condition for them. if bitarray_new_value | bitarray_old_value != bitarray_new_value: error_msg = "\tNew value contains some bits that cannot be cleared " error_msg += "(value will be {})".format( diff --git a/espefuse/efuse_defs/esp32c6.yaml b/espefuse/efuse_defs/esp32c6.yaml index 7afb4871e..db8be540b 100644 --- a/espefuse/efuse_defs/esp32c6.yaml +++ b/espefuse/efuse_defs/esp32c6.yaml @@ -14,8 +14,8 @@ EFUSES: SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} - USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} - USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} diff --git a/espefuse/efuse_defs/esp32h2.yaml b/espefuse/efuse_defs/esp32h2.yaml index 7e2b246fc..7dddf5108 100644 --- a/espefuse/efuse_defs/esp32h2.yaml +++ b/espefuse/efuse_defs/esp32h2.yaml @@ -14,8 +14,8 @@ EFUSES: SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} - USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} - USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threhold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} diff --git a/espefuse/efuse_defs/esp32p4.yaml b/espefuse/efuse_defs/esp32p4.yaml index 93d8288df..419e86fd4 100644 --- a/espefuse/efuse_defs/esp32p4.yaml +++ b/espefuse/efuse_defs/esp32p4.yaml @@ -63,8 +63,8 @@ EFUSES: PXA0_TIEH_SEL_2 : {show: y, blk : 0, word: 5, pos : 4, len : 2, start: 164, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[5:4]', bloc: 'B20[5:4]'} PXA0_TIEH_SEL_3 : {show: y, blk : 0, word: 5, pos : 6, len : 2, start: 166, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[7:6]', bloc: 'B20[7:6]'} KM_DISABLE_DEPLOY_MODE : {show: y, blk : 0, word: 5, pos : 8, len : 4, start: 168, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: TBD, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[11:8]', bloc: 'B21[3:0]'} - USB_DEVICE_DREFL : {show: n, blk : 0, word: 5, pos: 12, len : 2, start: 172, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb device single-end input low threhold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13:12]', bloc: 'B21[5:4]'} - USB_OTG11_DREFL : {show: n, blk : 0, word: 5, pos: 14, len : 2, start: 174, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb otg11 single-end input low threhold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[15:14]', bloc: 'B21[7:6]'} + USB_DEVICE_DREFL : {show: n, blk : 0, word: 5, pos: 12, len : 2, start: 172, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13:12]', bloc: 'B21[5:4]'} + USB_OTG11_DREFL : {show: n, blk : 0, word: 5, pos: 14, len : 2, start: 174, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[15:14]', bloc: 'B21[7:6]'} RESERVE_0_176 : {show: n, blk : 0, word: 5, pos: 16, len : 2, start: 176, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[17:16]', bloc: 'B22[1:0]'} HP_PWR_SRC_SEL : {show: y, blk : 0, word: 5, pos: 18, len : 1, start: 178, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'HP system power source select. 0:LDO. 1: DCDC', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[18]', bloc: 'B22[2]'} DCDC_VSET_EN : {show: y, blk : 0, word: 5, pos: 19, len : 1, start: 179, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Select dcdc vset use efuse_dcdc_vset, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[19]', bloc: 'B22[3]'} diff --git a/esptool/__init__.py b/esptool/__init__.py index 021ce08f5..556847b0c 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -475,7 +475,7 @@ def add_spi_flash_subparsers( parser_elf2image.add_argument( "--use_segments", help="If set, ELF segments will be used instead of ELF sections " - "to genereate the image.", + "to generate the image.", action="store_true", ) parser_elf2image.add_argument( diff --git a/esptool/cmds.py b/esptool/cmds.py index 09a97c4bd..beee92f79 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -1275,7 +1275,7 @@ def get_security_info(esp, args): hard_dis_jtag = get_security_flag_status("HARD_DIS_JTAG", flags) soft_dis_jtag = get_security_flag_status("SOFT_DIS_JTAG", flags) if hard_dis_jtag: - print("JTAG: Permenantly Disabled") + print("JTAG: Permanently Disabled") elif soft_dis_jtag: print("JTAG: Software Access Disabled") if get_security_flag_status("DIS_USB", flags): diff --git a/esptool/loader.py b/esptool/loader.py index 3a03b0f5a..55a941299 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -201,7 +201,7 @@ class ESPLoader(object): ESP_WRITE_REG = 0x09 ESP_READ_REG = 0x0A - # Some comands supported by ESP32 and later chips ROM bootloader (or -8266 w/ stub) + # Some commands supported by ESP32 and later chips ROM bootloader (or -8266 w/ stub) ESP_SPI_SET_PARAMS = 0x0B ESP_SPI_ATTACH = 0x0D ESP_READ_FLASH_SLOW = 0x0E # ROM only, much slower than the stub flash read @@ -509,7 +509,7 @@ def sync(self): # ROM bootloaders send some non-zero "val" response. The flasher stub sends 0. # If we receive 0 then it probably indicates that the chip wasn't or couldn't be - # reseted properly and esptool is talking to the flasher stub. + # reset properly and esptool is talking to the flasher stub. self.sync_stub_detected = val == 0 for _ in range(7): diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index 09804eaec..cd839da1a 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -124,7 +124,7 @@ def is_flash_encryption_key_valid(self): # When ESP32 has not generated AES/encryption key in BLOCK1, # the contents will be readable and 0. # If the flash encryption is enabled it is expected to have a valid - # non-zero key. We break out on first occurance of non-zero value + # non-zero key. We break out on first occurrence of non-zero value key_word = [0] * 7 for i in range(len(key_word)): key_word[i] = self.read_efuse(14 + i) diff --git a/esptool/targets/esp32c2.py b/esptool/targets/esp32c2.py index edfc3b1c0..3f59eb5d0 100644 --- a/esptool/targets/esp32c2.py +++ b/esptool/targets/esp32c2.py @@ -146,7 +146,7 @@ def is_flash_encryption_key_valid(self): # When chip has not generated AES/encryption key in BLOCK3, # the contents will be readable and 0. # If the flash encryption is enabled it is expected to have a valid - # non-zero key. We break out on first occurance of non-zero value + # non-zero key. We break out on first occurrence of non-zero value key_word = [0] * 7 if key_len_256 else [0] * 3 for i in range(len(key_word)): key_word[i] = self.read_reg(self.EFUSE_BLOCK_KEY0_REG + i * 4) diff --git a/flasher_stub/Makefile b/flasher_stub/Makefile index 63312020b..1d78f4d0c 100644 --- a/flasher_stub/Makefile +++ b/flasher_stub/Makefile @@ -31,7 +31,7 @@ -include local.mk # Prefix for each cross compiler (can include a directory path) -# These can be overriden via environment variables or on the make command line +# These can be overridden via environment variables or on the make command line CROSS_8266 ?= xtensa-lx106-elf- CROSS_32 ?= xtensa-esp32-elf- CROSS_32S2 ?= xtensa-esp32s2-elf- diff --git a/flasher_stub/include/miniz.h b/flasher_stub/include/miniz.h index 65e96640e..bf1554a06 100644 --- a/flasher_stub/include/miniz.h +++ b/flasher_stub/include/miniz.h @@ -618,7 +618,7 @@ enum /* flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression. */ /* On return: */ /* Function returns a pointer to the compressed data, or NULL on failure. */ -/* *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data. */ +/* *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on incompressible data. */ /* The caller must free() the returned block when it's no longer needed. */ void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); @@ -786,7 +786,7 @@ enum /* pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress. */ /* On return: */ /* Function returns a pointer to the decompressed data, or NULL on failure. */ -/* *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data. */ +/* *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on incompressible data. */ /* The caller must call mz_free() on the returned block when it's no longer needed. */ void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); @@ -1310,7 +1310,7 @@ mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive * /* An archive must be manually finalized by calling this function for it to be valid. */ mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip); -/* Finalizes a heap archive, returning a poiner to the heap block and its size. */ +/* Finalizes a heap archive, returning a pointer to the heap block and its size. */ /* The heap block will be allocated using the mz_zip_archive's alloc/realloc callbacks. */ mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **ppBuf, size_t *pSize); diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index 38627368c..eed774bdc 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -358,7 +358,7 @@ #define DR_REG_INTERRUPT_MATRIX_BASE 0x500D6000 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) /* USB-JTAG-Serial, CORE0_USB_DEVICE_INT_MAP_REG */ -#define CLIC_EXT_INTR_NUM_OFFSET 16 /* For CLIC first 16 intrrupts are reserved as internal */ +#define CLIC_EXT_INTR_NUM_OFFSET 16 /* For CLIC first 16 interrupts are reserved as internal */ #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ #endif diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c index 967bff5ec..445e42567 100644 --- a/flasher_stub/stub_flasher.c +++ b/flasher_stub/stub_flasher.c @@ -37,7 +37,7 @@ typedef struct { } uart_buf_t; static volatile uart_buf_t ub; -/* esptool protcol "checksum" is XOR of 0xef and each byte of +/* esptool protocol "checksum" is XOR of 0xef and each byte of data payload. */ static uint8_t calculate_checksum(uint8_t *buf, int length) { @@ -492,7 +492,7 @@ void stub_main() stub_io_init(&stub_handle_rx_byte); /* Configure default SPI flash functionality. - Can be overriden later by esptool.py. */ + Can be overridden later by esptool.py. */ #ifdef ESP8266 SelectSpiFunction(); spi_flash_attach(); diff --git a/test/elf2image/esp32-too-many-sections/Makefile b/test/elf2image/esp32-too-many-sections/Makefile index 33ae71c80..c724f907f 100644 --- a/test/elf2image/esp32-too-many-sections/Makefile +++ b/test/elf2image/esp32-too-many-sections/Makefile @@ -52,7 +52,7 @@ all: $(BIN) $(BIN): $(OBJ) $(CC) -o $@ $^ $(LDFLAGS) -# By default, make uses sh as script langage, use bash to generate the C file +# By default, make uses sh as script language, use bash to generate the C file $(SRC): SHELL:=$(BASH) $(SRC): @$(generate_c_code) diff --git a/test/images/ram_helloworld/source/Makefile b/test/images/ram_helloworld/source/Makefile index 2d7eca65a..672da257e 100644 --- a/test/images/ram_helloworld/source/Makefile +++ b/test/images/ram_helloworld/source/Makefile @@ -1,7 +1,7 @@ # Makefile to compile the helloworld app for esptool tests # Prefix for each cross compiler (can include a directory path) -# These can be overriden via environment variables or on the make command line +# These can be overridden via environment variables or on the make command line CROSS_8266 ?= xtensa-lx106-elf- CROSS_32 ?= xtensa-esp32-elf- CROSS_32S2 ?= xtensa-esp32s2-elf- diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 04e259132..2f1a6a65e 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -522,7 +522,7 @@ def test_set_flash_voltage_off2(self): ) -@pytest.mark.skipif(arg_chip != "esp32c3", reason="Not necessary fo all chips") +@pytest.mark.skipif(arg_chip != "esp32c3", reason="Not necessary for all chips") class TestValueArgForBurnEfuseCommands(EfuseTestCase): def test_efuse_is_bool_given_none(self): self.espefuse_py("burn_efuse SECURE_BOOT_KEY_REVOKE0") @@ -998,7 +998,7 @@ def test_burn_key_512bit(self): reason="512 bit keys are only supported on ESP32-S2, S3, and P4", ) def test_burn_key_512bit_non_consecutive_blocks(self): - # Burn efuses seperately to test different kinds + # Burn efuses separately to test different kinds # of "key used" detection criteria self.espefuse_py( f"burn_key \ @@ -1779,7 +1779,7 @@ def test_2_secure_boot_v1(self): class TestExecuteScriptsCommands(EfuseTestCase): @classmethod def setup_class(self): - # Save the current working directory to be resotred later + # Save the current working directory to be restored later self.stored_dir = os.getcwd() @classmethod diff --git a/test/test_esptool.py b/test/test_esptool.py index 7b251ef9f..78cab4360 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -137,7 +137,7 @@ def run_esptool(self, args, baud=None, chip=None, port=None, preload=True): """ Run esptool with the specified arguments. --chip, --port and --baud are filled in automatically from the command line. - (These can be overriden with their respective params.) + (These can be overridden with their respective params.) Additional args passed in args parameter as a string. @@ -221,7 +221,7 @@ def run_esptool_error(self, args, baud=None): def setup_class(self): print() print(50 * "*") - # Save the current working directory to be resotred later + # Save the current working directory to be restored later self.stored_dir = os.getcwd() os.chdir(TEST_DIR) @@ -457,7 +457,7 @@ def test_last_bytes_of_32M_flash(self): image_size = 1024 offset = flash_size - image_size self.run_esptool("write_flash {} images/one_kb.bin".format(hex(offset))) - # Some of the functons cannot handle 32-bit addresses - i.e. addresses accessing + # Some of the functions cannot handle 32-bit addresses - i.e. addresses accessing # the higher 16MB will manipulate with the lower 16MB flash area. offset2 = offset & 0xFFFFFF self.run_esptool("write_flash {} images/one_kb_all_ef.bin".format(hex(offset2))) @@ -469,7 +469,7 @@ def test_last_bytes_of_32M_flash(self): def test_write_larger_area_to_32M_flash(self): offset = 18 * 1024 * 1024 self.run_esptool("write_flash {} images/one_mb.bin".format(hex(offset))) - # Some of the functons cannot handle 32-bit addresses - i.e. addresses accessing + # Some of the functions cannot handle 32-bit addresses - i.e. addresses accessing # the higher 16MB will manipulate with the lower 16MB flash area. offset2 = offset & 0xFFFFFF self.run_esptool("write_flash {} images/one_kb_all_ef.bin".format(hex(offset2))) @@ -1424,7 +1424,7 @@ def test_load_config_file(self): output = self.run_esptool("version") assert f"Loaded custom configuration from {config_file_path}" not in output - # Correct header, but options are unparseable + # Correct header, but options are unparsable faulty_config = "[esptool]\n" "connect_attempts = 5\n" "connect_attempts = 9\n" with self.ConfigFile(config_file_path, faulty_config): output = self.run_esptool("version") @@ -1435,10 +1435,12 @@ def test_load_config_file(self): ) # Correct header, unknown option (or a typo) - faulty_config = "[esptool]\n" "connect_attempts = 9\n" "timout = 2\n" "bits = 2" + faulty_config = ( + "[esptool]\n" "connect_attempts = 9\n" "timoout = 2\n" "bits = 2" + ) with self.ConfigFile(config_file_path, faulty_config): output = self.run_esptool("version") - assert "Ignoring unknown config file options: bits, timout" in output + assert "Ignoring unknown config file options: bits, timoout" in output # Test other config files (setup.cfg, tox.ini) are loaded config_file_path = os.path.join(os.getcwd(), "tox.ini") diff --git a/test/test_imagegen.py b/test/test_imagegen.py index 9756e3fc9..9ca354260 100755 --- a/test/test_imagegen.py +++ b/test/test_imagegen.py @@ -41,7 +41,7 @@ def segment_matches_section(segment, section): class BaseTestCase: @classmethod def setup_class(self): - # Save the current working directory to be resotred later + # Save the current working directory to be restored later self.stored_dir = os.getcwd() os.chdir(TEST_DIR) @@ -415,7 +415,7 @@ class TestELFSHA256(BaseTestCase): 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}, }; - This leaves zeroes only for the fiels of SHA-256 and the test will fail + This leaves zeroes only for the fields of SHA-256 and the test will fail if the placement of zeroes are tested at the wrong place. 00000000: e907 0020 780f 0840 ee00 0000 0000 0000 ... x..@........ diff --git a/test/test_merge_bin.py b/test/test_merge_bin.py index 1369223fd..c4f97673b 100755 --- a/test/test_merge_bin.py +++ b/test/test_merge_bin.py @@ -247,7 +247,7 @@ def test_merge_bin2hex(self): data_len = int(b"0x" + line[1:3], 16) # : + len + addr + type + data + checksum assert len(line) == 1 + 2 + 4 + 2 + data_len * 2 + 2 - # last line is allways :00000001FF + # last line is always :00000001FF assert lines[-1] == b":00000001FF" # convert back and verify the result against the source bin file with tempfile.NamedTemporaryFile(suffix=".hex", delete=False) as hex: diff --git a/test/test_uf2_ids.py b/test/test_uf2_ids.py index f50a0e4ca..1919013f7 100644 --- a/test/test_uf2_ids.py +++ b/test/test_uf2_ids.py @@ -41,7 +41,7 @@ def test_check_uf2family_ids(uf2_json): def test_check_uf2(uf2_json): """Check if all non-beta chip definition has UF2 family id in esptool - and also in Miscrosoft repo + and also in Microsoft repo """ # remove beta chip definitions esptool_chips = set( From 7bb6b7aa3d5e1a36e0da57345e6fa9cbfdc0bcc5 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Thu, 22 Feb 2024 09:08:02 +0100 Subject: [PATCH 148/209] fix(intelhex): catch unicode decode errors when convering hex to binary --- esptool/bin_image.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 7ce2204bd..69544fb26 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -57,7 +57,7 @@ def intel_hex_to_bin(file: BinaryIO, start_addr: Optional[int] = None) -> Binary return bin else: return file - except HexRecordError: + except (HexRecordError, UnicodeDecodeError): # file started with HEX magic but the rest was not according to the standard return file From 21850b1716311ad1d0b20343419f068066664e77 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 22 Feb 2024 13:55:23 +0200 Subject: [PATCH 149/209] feat(esptool): Adds wafer and pkg versions --- esptool/targets/esp32p4.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 7d9f9bc97..6a6ce3447 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -86,16 +86,16 @@ class ESP32P4ROM(ESP32ROM): UF2_FAMILY_ID = 0x3D308E94 def get_pkg_version(self): - # ESP32P4 TODO - return 0 + num_word = 2 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 27) & 0x07 def get_minor_chip_version(self): - # ESP32P4 TODO - return 0 + num_word = 2 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F def get_major_chip_version(self): - # ESP32P4 TODO - return 0 + num_word = 2 + return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 4) & 0x03 def get_chip_description(self): chip_name = { From e3324a556b17090ae78230ae0f8be1fe76993022 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 16 Feb 2024 15:43:20 +0100 Subject: [PATCH 150/209] feat: print flash voltage in flash_id command Closes https://github.com/espressif/esptool/issues/224 --- docs/en/espefuse/set-flash-voltage-cmd.rst | 2 +- esptool/cmds.py | 1 + esptool/targets/esp32.py | 78 +++++++++++++++++----- esptool/targets/esp32c3.py | 3 + esptool/targets/esp32p4.py | 3 + esptool/targets/esp32s2.py | 9 +++ esptool/targets/esp32s3.py | 9 +++ esptool/targets/esp8266.py | 3 + 8 files changed, 92 insertions(+), 16 deletions(-) diff --git a/docs/en/espefuse/set-flash-voltage-cmd.rst b/docs/en/espefuse/set-flash-voltage-cmd.rst index 950cad4a1..6340858ca 100644 --- a/docs/en/espefuse/set-flash-voltage-cmd.rst +++ b/docs/en/espefuse/set-flash-voltage-cmd.rst @@ -15,7 +15,7 @@ Positional arguments: - ``voltage`` - Voltage selection ['1.8V', '3.3V', 'OFF']. -.. only:: esp32c2 or esp32c3 +.. only:: not esp32 and not esp32s2 and not esp32s3 .. note:: diff --git a/esptool/cmds.py b/esptool/cmds.py index beee92f79..52a09ef01 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -1108,6 +1108,7 @@ def flash_id(esp, args): flash_type_str = flash_type_dict.get(flash_type) if flash_type_str: print(f"Flash type set in eFuse: {flash_type_str}") + esp.get_flash_voltage() def read_flash(esp, args): diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index cd839da1a..2b2a2bbc4 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -5,6 +5,7 @@ import struct import time +from typing import Optional from ..loader import ESPLoader from ..util import FatalError, NotSupportedError @@ -49,6 +50,11 @@ class ESP32ROM(ESPLoader): EFUSE_RD_ABS_DONE_0_MASK = 1 << 4 EFUSE_RD_ABS_DONE_1_MASK = 1 << 5 + EFUSE_VDD_SPI_REG = EFUSE_RD_REG_BASE + 0x10 + VDD_SPI_XPD = 1 << 14 # XPD_SDIO_REG + VDD_SPI_TIEH = 1 << 15 # XPD_SDIO_TIEH + VDD_SPI_FORCE = 1 << 16 # XPD_SDIO_FORCE + DR_REG_SYSCON_BASE = 0x3FF66000 APB_CTL_DATE_ADDR = DR_REG_SYSCON_BASE + 0x7C APB_CTL_DATE_V = 0x1 @@ -64,6 +70,17 @@ class ESP32ROM(ESPLoader): TIMERS_RTC_CALI_VALUE = 0x01FFFFFF TIMERS_RTC_CALI_VALUE_S = 7 + GPIO_STRAP_REG = 0x3FF44038 + GPIO_STRAP_VDDSPI_MASK = 1 << 5 # GPIO_STRAP_VDDSDIO + + RTC_CNTL_SDIO_CONF_REG = 0x3FF48074 + RTC_CNTL_XPD_SDIO_REG = 1 << 31 + RTC_CNTL_DREFH_SDIO_M = 3 << 29 + RTC_CNTL_DREFM_SDIO_M = 3 << 27 + RTC_CNTL_DREFL_SDIO_M = 3 << 25 + RTC_CNTL_SDIO_FORCE = 1 << 22 + RTC_CNTL_SDIO_PD_EN = 1 << 21 + FLASH_SIZES = { "1MB": 0x00, "2MB": 0x10, @@ -315,32 +332,63 @@ def read_mac(self, mac_type="BASE_MAC"): def get_erase_size(self, offset, size): return size + def _get_efuse_flash_voltage(self) -> Optional[str]: + efuse = self.read_reg(self.EFUSE_VDD_SPI_REG) + # check efuse setting + if efuse & (self.VDD_SPI_FORCE | self.VDD_SPI_XPD | self.VDD_SPI_TIEH): + return "3.3V" + elif efuse & (self.VDD_SPI_FORCE | self.VDD_SPI_XPD): + return "1.8V" + elif efuse & self.VDD_SPI_FORCE: + return "OFF" + return None + + def _get_rtc_cntl_flash_voltage(self) -> Optional[str]: + reg = self.read_reg(self.RTC_CNTL_SDIO_CONF_REG) + # check if override is set in RTC_CNTL_SDIO_CONF_REG + if reg & self.RTC_CNTL_SDIO_FORCE: + if reg & self.RTC_CNTL_DREFH_SDIO_M: + return "1.9V" + elif reg & self.RTC_CNTL_XPD_SDIO_REG: + return "1.8V" + else: + return "OFF" + return None + + def get_flash_voltage(self): + """Get flash voltage setting and print it to the console.""" + voltage = self._get_rtc_cntl_flash_voltage() + source = "RTC_CNTL" + if not voltage: + voltage = self._get_efuse_flash_voltage() + source = "eFuse" + if not voltage: + strap_reg = self.read_reg(self.GPIO_STRAP_REG) + strap_reg &= self.GPIO_STRAP_VDDSPI_MASK + voltage = "1.8V" if strap_reg else "3.3V" + source = "a strapping pin" + print(f"Flash voltage set by {source} to {voltage}") + def override_vddsdio(self, new_voltage): new_voltage = new_voltage.upper() if new_voltage not in self.OVERRIDE_VDDSDIO_CHOICES: raise FatalError( - "The only accepted VDDSDIO overrides are '1.8V', '1.9V' and 'OFF'" + f"The only accepted VDDSDIO overrides are {', '.join(self.OVERRIDE_VDDSDIO_CHOICES)}" ) - RTC_CNTL_SDIO_CONF_REG = 0x3FF48074 - RTC_CNTL_XPD_SDIO_REG = 1 << 31 - RTC_CNTL_DREFH_SDIO_M = 3 << 29 - RTC_CNTL_DREFM_SDIO_M = 3 << 27 - RTC_CNTL_DREFL_SDIO_M = 3 << 25 - # RTC_CNTL_SDIO_TIEH = (1 << 23) - # not used here, setting TIEH=1 would set 3.3V output, + # RTC_CNTL_SDIO_TIEH is not used here, setting TIEH=1 would set 3.3V output, # not safe for esptool.py to do - RTC_CNTL_SDIO_FORCE = 1 << 22 - RTC_CNTL_SDIO_PD_EN = 1 << 21 - reg_val = RTC_CNTL_SDIO_FORCE # override efuse setting - reg_val |= RTC_CNTL_SDIO_PD_EN + reg_val = self.RTC_CNTL_SDIO_FORCE # override efuse setting + reg_val |= self.RTC_CNTL_SDIO_PD_EN if new_voltage != "OFF": - reg_val |= RTC_CNTL_XPD_SDIO_REG # enable internal LDO + reg_val |= self.RTC_CNTL_XPD_SDIO_REG # enable internal LDO if new_voltage == "1.9V": reg_val |= ( - RTC_CNTL_DREFH_SDIO_M | RTC_CNTL_DREFM_SDIO_M | RTC_CNTL_DREFL_SDIO_M + self.RTC_CNTL_DREFH_SDIO_M + | self.RTC_CNTL_DREFM_SDIO_M + | self.RTC_CNTL_DREFL_SDIO_M ) # boost voltage - self.write_reg(RTC_CNTL_SDIO_CONF_REG, reg_val) + self.write_reg(self.RTC_CNTL_SDIO_CONF_REG, reg_val) print("VDDSDIO regulator set to %s" % new_voltage) def read_flash_slow(self, offset, length, progress_fn): diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index e00e51786..0ef0905c9 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -152,6 +152,9 @@ def get_crystal_freq(self): # ESP32C3 XTAL is fixed to 40MHz return 40 + def get_flash_voltage(self): + pass # not supported on ESP32-C3 + def override_vddsdio(self, new_voltage): raise NotImplementedInROMError( "VDD_SDIO overrides are not supported for ESP32-C3" diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 6a6ce3447..7b4a35fbe 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -112,6 +112,9 @@ def get_crystal_freq(self): # ESP32P4 XTAL is fixed to 40MHz return 40 + def get_flash_voltage(self): + pass # not supported on ESP32-P4 + def override_vddsdio(self, new_voltage): raise NotImplementedInROMError( "VDD_SDIO overrides are not supported for ESP32-P4" diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py index 19f5532c6..5c7c6b7bb 100644 --- a/esptool/targets/esp32s2.py +++ b/esptool/targets/esp32s2.py @@ -81,6 +81,7 @@ class ESP32S2ROM(ESP32ROM): GPIO_STRAP_REG = 0x3F404038 GPIO_STRAP_SPI_BOOT_MASK = 0x8 # Not download mode + GPIO_STRAP_VDDSPI_MASK = 1 << 4 RTC_CNTL_OPTION1_REG = 0x3F408128 RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1 # Is download mode forced over USB? @@ -99,6 +100,11 @@ class ESP32S2ROM(ESP32ROM): [0x50000000, 0x50002000, "RTC_DATA"], ] + EFUSE_VDD_SPI_REG = EFUSE_BASE + 0x34 + VDD_SPI_XPD = 1 << 4 + VDD_SPI_TIEH = 1 << 5 + VDD_SPI_FORCE = 1 << 6 + UF2_FAMILY_ID = 0xBFDD4EEE def get_pkg_version(self): @@ -183,6 +189,9 @@ def get_crystal_freq(self): # ESP32-S2 XTAL is fixed to 40MHz return 40 + def _get_rtc_cntl_flash_voltage(self): + return None # not supported on ESP32-S2 + def override_vddsdio(self, new_voltage): raise NotImplementedInROMError( "VDD_SDIO overrides are not supported for ESP32-S2" diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index f3d814455..7531f4ae0 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -95,6 +95,7 @@ class ESP32S3ROM(ESP32ROM): GPIO_STRAP_REG = 0x60004038 GPIO_STRAP_SPI_BOOT_MASK = 0x8 # Not download mode + GPIO_STRAP_VDDSPI_MASK = 1 << 4 RTC_CNTL_OPTION1_REG = 0x6000812C RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1 # Is download mode forced over USB? @@ -115,6 +116,11 @@ class ESP32S3ROM(ESP32ROM): [0x50000000, 0x50002000, "RTC_DATA"], ] + EFUSE_VDD_SPI_REG = EFUSE_BASE + 0x34 + VDD_SPI_XPD = 1 << 4 + VDD_SPI_TIEH = 1 << 5 + VDD_SPI_FORCE = 1 << 6 + UF2_FAMILY_ID = 0xC47E5767 def get_pkg_version(self): @@ -251,6 +257,9 @@ def get_secure_boot_enabled(self): & self.EFUSE_SECURE_BOOT_EN_MASK ) + def _get_rtc_cntl_flash_voltage(self): + return None # not supported on ESP32-S3 + def override_vddsdio(self, new_voltage): raise NotImplementedInROMError( "VDD_SDIO overrides are not supported for ESP32-S3" diff --git a/esptool/targets/esp8266.py b/esptool/targets/esp8266.py index 58e465158..4bd3dc895 100644 --- a/esptool/targets/esp8266.py +++ b/esptool/targets/esp8266.py @@ -169,6 +169,9 @@ def get_erase_size(self, offset, size): else: return (num_sectors - head_sectors) * sector_size + def get_flash_voltage(self): + pass # not supported on ESP8266 + def override_vddsdio(self, new_voltage): raise NotSupportedError(self, "Overriding VDDSDIO") From 18904454dcb2b80568f14e4fd7f41b5bb577378b Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Thu, 22 Feb 2024 13:15:07 +0100 Subject: [PATCH 151/209] feat(cmds/write_flash): Recalculated SHA digest for image binary --- esptool/bin_image.py | 2 ++ esptool/cmds.py | 76 ++++++++++++++++++++++++++------------------ 2 files changed, 47 insertions(+), 31 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 69544fb26..6a75d02ac 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -619,6 +619,7 @@ def __init__(self, load_file=None, append_digest=True, ram_only_header=False): self.ram_only_header = ram_only_header self.append_digest = append_digest + self.data_length = None if load_file is not None: start = load_file.tell() @@ -637,6 +638,7 @@ def __init__(self, load_file=None, append_digest=True, ram_only_header=False): calc_digest = hashlib.sha256() calc_digest.update(load_file.read(end - start)) self.calc_digest = calc_digest.digest() # TODO: decide what to do here? + self.data_length = end - start self.verify() diff --git a/esptool/cmds.py b/esptool/cmds.py index 52a09ef01..29826ef35 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -10,6 +10,7 @@ import sys import time import zlib +import itertools from intelhex import IntelHex @@ -238,7 +239,9 @@ def detect_flash_size(esp, args=None): return flash_size -def _update_image_flash_params(esp, address, args, image): +def _update_image_flash_params( + esp, address, args, image +): # TODO check the flash params if they are valid """ Modify the flash mode & size bytes if this looks like an executable bootloader image """ @@ -276,49 +279,60 @@ def _update_image_flash_params(esp, address, args, image): # After the 8-byte header comes the extended header for chips others than ESP8266. # The 15th byte of the extended header indicates if the image is protected by - # a SHA256 checksum. In that case we should not modify the header because - # the checksum check would fail. - sha_implies_keep = args.chip != "esp8266" and image[8 + 15] == 1 - - def print_keep_warning(arg_to_keep, arg_used): - print( - "Warning: Image file at {addr} is protected with a hash checksum, " - "so not changing the flash {arg} setting. " - "Use the --flash_{arg}=keep option instead of --flash_{arg}={arg_orig} " - "in order to remove this warning, or use the --dont-append-digest option " - "for the elf2image command in order to generate an image file " - "without a hash checksum".format( - addr=hex(address), arg=arg_to_keep, arg_orig=arg_used - ) - ) + # a SHA256 checksum. In that case we recalculate the SHA digest after modifying the header. + sha_appended = args.chip != "esp8266" and image[8 + 15] == 1 if args.flash_mode != "keep": - new_flash_mode = FLASH_MODES[args.flash_mode] - if flash_mode != new_flash_mode and sha_implies_keep: - print_keep_warning("mode", args.flash_mode) - else: - flash_mode = new_flash_mode + flash_mode = FLASH_MODES[args.flash_mode] flash_freq = flash_size_freq & 0x0F if args.flash_freq != "keep": - new_flash_freq = esp.parse_flash_freq_arg(args.flash_freq) - if flash_freq != new_flash_freq and sha_implies_keep: - print_keep_warning("frequency", args.flash_freq) - else: - flash_freq = new_flash_freq + flash_freq = esp.parse_flash_freq_arg(args.flash_freq) flash_size = flash_size_freq & 0xF0 if args.flash_size != "keep": - new_flash_size = esp.parse_flash_size_arg(args.flash_size) - if flash_size != new_flash_size and sha_implies_keep: - print_keep_warning("size", args.flash_size) - else: - flash_size = new_flash_size + flash_size = esp.parse_flash_size_arg(args.flash_size) flash_params = struct.pack(b"BB", flash_mode, flash_size + flash_freq) if flash_params != image[2:4]: print("Flash params set to 0x%04x" % struct.unpack(">H", flash_params)) image = image[0:2] + flash_params + image[4:] + + # recalculate the SHA digest if it was appended + if sha_appended: + # Since the changes are only made for images located in the bootloader offset, + # we can assume that the image is always a bootloader image. + # For merged binaries, we check the bootloader SHA when parameters are changed. + image_object = esp.BOOTLOADER_IMAGE(io.BytesIO(image)) + # get the image header, extended header (if present) and data + image_data_before_sha = image[: image_object.data_length] + # get the image data after the SHA digest (primary for merged binaries) + image_data_after_sha = image[ + (image_object.data_length + image_object.SHA256_DIGEST_LEN) : + ] + + sha_digest_calculated = hashlib.sha256(image_data_before_sha).digest() + image = bytes( + itertools.chain( + image_data_before_sha, sha_digest_calculated, image_data_after_sha + ) + ) + + # get the SHA digest newly stored in the image and compare it to the calculated one + image_stored_sha = image[ + image_object.data_length : image_object.data_length + + image_object.SHA256_DIGEST_LEN + ] + + if hexify(sha_digest_calculated) == hexify(image_stored_sha): + print("SHA digest in image updated") + else: + print( + "WARNING: SHA recalculation for binary failed!\n" + f"\tExpected calculated SHA: {hexify(sha_digest_calculated)}\n" + f"\tSHA stored in binary: {hexify(image_stored_sha)}" + ) + return image From 0f800dacf6827517f834faad210b30cf94598f29 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Tue, 27 Feb 2024 14:43:58 +0100 Subject: [PATCH 152/209] feat: Added warning when secure boot enabled Warning message that the flash settings parameters won't be changed because of enabled secure boot --- esptool/cmds.py | 8 +++++++- esptool/targets/esp8266.py | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 29826ef35..984225a86 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -569,7 +569,13 @@ def write_flash(esp, args): if len(image) == 0: print("WARNING: File %s is empty" % argfile.name) continue - image = _update_image_flash_params(esp, address, args, image) + + if not esp.get_secure_boot_enabled(): + image = _update_image_flash_params(esp, address, args, image) + else: + print( + "WARNING: Secure boot is enabled, so not changing any flash settings." + ) calcmd5 = hashlib.md5(image).hexdigest() uncsize = len(image) if compress: diff --git a/esptool/targets/esp8266.py b/esptool/targets/esp8266.py index 4bd3dc895..9f8d7c17d 100644 --- a/esptool/targets/esp8266.py +++ b/esptool/targets/esp8266.py @@ -178,6 +178,9 @@ def override_vddsdio(self, new_voltage): def check_spi_connection(self, spi_connection): raise NotSupportedError(self, "Setting --spi-connection") + def get_secure_boot_enabled(self): + return False # ESP8266 doesn't have security features + class ESP8266StubLoader(ESP8266ROM): """Access class for ESP8266 stub loader, runs on top of ROM.""" From d9c19c18679a8785cd19512990a791edb1d01315 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Wed, 28 Feb 2024 12:49:32 +0100 Subject: [PATCH 153/209] refactor(test/esptool): Updated tests according to SHA recomputation for binary --- esptool/cmds.py | 4 +--- test/test_esptool.py | 17 ++++++----------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 984225a86..b4bf46bb0 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -239,9 +239,7 @@ def detect_flash_size(esp, args=None): return flash_size -def _update_image_flash_params( - esp, address, args, image -): # TODO check the flash params if they are valid +def _update_image_flash_params(esp, address, args, image): """ Modify the flash mode & size bytes if this looks like an executable bootloader image """ diff --git a/test/test_esptool.py b/test/test_esptool.py index 78cab4360..5f7975760 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -1043,11 +1043,7 @@ def test_detect_size_changes_size(self): ) readback = self.readback(self.flash_offset, 8) assert self.header[:3] == readback[:3] # first 3 bytes unchanged - if arg_chip in ["esp8266", "esp32"]: - assert self.header[3] != readback[3] # size_freq byte changed - else: - # Not changed because protected by SHA256 digest - assert self.header[3] == readback[3] # size_freq byte unchanged + assert self.header[3] != readback[3] # size_freq byte changed assert self.header[4:] == readback[4:] # rest unchanged @pytest.mark.skipif( @@ -1171,13 +1167,12 @@ def test_flash_header_rewrite(self): f"write_flash -fm dout -ff 20m {bl_offset:#x} {bl_image}" ) if arg_chip in ["esp8266", "esp32"]: - # There is no SHA256 digest so the header can be changed - ESP8266 doesn't - # support this; The test image for ESP32 just doesn't have it. - "Flash params set to" in output + # ESP8266 doesn't support this; The test image for ESP32 just doesn't have it. + assert "Flash params set to" in output else: - assert "Flash params set to" not in output - "not changing the flash mode setting" in output - "not changing the flash frequency setting" in output + assert "Flash params set to" in output + # Since SHA recalculation is supported for changed bootloader header + assert "SHA digest in image updated" in output def test_flash_header_no_magic_no_rewrite(self): # first image doesn't start with magic byte, second image does From c8d49fa895f1eed5b5b218da0de3ca12322e7848 Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Thu, 29 Feb 2024 14:16:23 +0100 Subject: [PATCH 154/209] docs: Updated documentation to reflect changes of SHA256 digest recomputation --- docs/en/advanced-topics/firmware-image-format.rst | 4 +++- docs/en/esptool/basic-commands.rst | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/en/advanced-topics/firmware-image-format.rst b/docs/en/advanced-topics/firmware-image-format.rst index e3ebf350c..10d81bb57 100644 --- a/docs/en/advanced-topics/firmware-image-format.rst +++ b/docs/en/advanced-topics/firmware-image-format.rst @@ -6,6 +6,8 @@ {IDF_TARGET_FLASH_FREQ_2:default="20", esp32c2="15", esp32h2="12"} +{IDF_TARGET_BOOTLOADER_OFFSET:default="0x0", esp32="0x1000", esp32s2="0x1000", esp32p4="0x2000"} + .. _image-format: @@ -108,7 +110,7 @@ The image header is 8 bytes long: +--------+------------------------------------------------------------------------------------------------+ -``esptool.py`` overrides the 2nd and 3rd (start from 0) bytes according to the SPI flash info provided through command line option, but only if there is no SHA256 digest appended after the image. Therefore, if you would like to change SPI flash info during flashing, i.e. with the ``esptool.py write_flash`` command, then generate images without SHA256 digests. This can be achieved by running ``esptool.py elf2image`` with the ``--dont-append-digest`` argument. +``esptool.py`` overrides the 2nd and 3rd (counted from 0) bytes according to the SPI flash info provided through the command line option. These bytes are only overridden if this is a bootloader image (an image written to a correct bootloader offset of {IDF_TARGET_BOOTLOADER_OFFSET}), in this case, the appended SHA256 digest is also updated to reflect the header changes. Generating images without SHA256 digest can be achieved by running ``esptool.py elf2image`` with the ``--dont-append-digest`` argument. .. only:: esp8266 diff --git a/docs/en/esptool/basic-commands.rst b/docs/en/esptool/basic-commands.rst index 33070671a..d313bca9d 100644 --- a/docs/en/esptool/basic-commands.rst +++ b/docs/en/esptool/basic-commands.rst @@ -192,7 +192,7 @@ The ``elf2image`` command converts an ELF file (from compiler/linker output) int This command does not require a serial connection. ``elf2image`` also accepts the `Flash Modes <#flash-modes>`__ arguments ``--flash_freq`` and ``--flash_mode``, which can be used to set the default values in the image header. This is important when generating any image which will be booted directly by the chip. -These values can also be overwritten via the ``write_flash`` command, see the `write_flash command <#write-binary-data-to-flash-write-flash>`__ for details. However, if you want to overwrite these values via the ``write_flash`` command then use the ``--dont-append-digest`` argument of the ``elf2image`` command in order to skip appending a SHA256 digest after the image. The SHA256 digest would be invalidated by rewriting the image header, therefore, it is not allowed. +These values can also be overwritten via the ``write_flash`` command, see the `write_flash command <#write-binary-data-to-flash-write-flash>`__ for details. Overwriting these values via the ``write_flash`` command will produce an image with a recalculated SHA256 digest, otherwise, the image SHA256 digest would be invalidated by rewriting the image header. There is an option to skip appending a SHA256 digest after the image with ``--dont-append-digest`` argument of the ``elf2image`` command. By default, ``elf2image`` uses the sections in the ELF file to generate each segment in the binary executable. To use segments (PHDRs) instead, pass the ``--use_segments`` option. From d7dc6a325a43e75122ed577ed532c426391d35f5 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 12 Mar 2024 11:56:10 +0800 Subject: [PATCH 155/209] feat(esp32c5): base support of esp32c5 mp (no stub) --- espefuse/__init__.py | 2 + espefuse/efuse/esp32c5/__init__.py | 3 + .../efuse/esp32c5/emulate_efuse_controller.py | 92 ++++ espefuse/efuse/esp32c5/fields.py | 456 ++++++++++++++++++ espefuse/efuse/esp32c5/mem_definition.py | 169 +++++++ espefuse/efuse/esp32c5/operations.py | 413 ++++++++++++++++ esptool/bin_image.py | 11 + esptool/targets/__init__.py | 2 + esptool/targets/esp32c5.py | 99 ++++ 9 files changed, 1247 insertions(+) create mode 100644 espefuse/efuse/esp32c5/__init__.py create mode 100644 espefuse/efuse/esp32c5/emulate_efuse_controller.py create mode 100644 espefuse/efuse/esp32c5/fields.py create mode 100644 espefuse/efuse/esp32c5/mem_definition.py create mode 100644 espefuse/efuse/esp32c5/operations.py create mode 100644 esptool/targets/esp32c5.py diff --git a/espefuse/__init__.py b/espefuse/__init__.py index 71689662c..7ef04489a 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -11,6 +11,7 @@ import espefuse.efuse.esp32 as esp32_efuse import espefuse.efuse.esp32c2 as esp32c2_efuse import espefuse.efuse.esp32c3 as esp32c3_efuse +import espefuse.efuse.esp32c5 as esp32c5_efuse import espefuse.efuse.esp32c5beta3 as esp32c5beta3_efuse import espefuse.efuse.esp32c6 as esp32c6_efuse import espefuse.efuse.esp32h2 as esp32h2_efuse @@ -50,6 +51,7 @@ "esp32c2": DefChip("ESP32-C2", esp32c2_efuse, esptool.targets.ESP32C2ROM), "esp32c3": DefChip("ESP32-C3", esp32c3_efuse, esptool.targets.ESP32C3ROM), "esp32c6": DefChip("ESP32-C6", esp32c6_efuse, esptool.targets.ESP32C6ROM), + "esp32c5": DefChip("ESP32-C5", esp32c5_efuse, esptool.targets.ESP32C5ROM), "esp32c5beta3": DefChip( "ESP32-C5(beta3)", esp32c5beta3_efuse, esptool.targets.ESP32C5BETA3ROM ), diff --git a/espefuse/efuse/esp32c5/__init__.py b/espefuse/efuse/esp32c5/__init__.py new file mode 100644 index 000000000..a3b55a802 --- /dev/null +++ b/espefuse/efuse/esp32c5/__init__.py @@ -0,0 +1,3 @@ +from . import operations +from .emulate_efuse_controller import EmulateEfuseController +from .fields import EspEfuses diff --git a/espefuse/efuse/esp32c5/emulate_efuse_controller.py b/espefuse/efuse/esp32c5/emulate_efuse_controller.py new file mode 100644 index 000000000..5f634da15 --- /dev/null +++ b/espefuse/efuse/esp32c5/emulate_efuse_controller.py @@ -0,0 +1,92 @@ +# This file describes eFuses controller for ESP32-C5 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from ..emulate_efuse_controller_base import EmulateEfuseControllerBase, FatalError + + +class EmulateEfuseController(EmulateEfuseControllerBase): + """The class for virtual efuse operation. Using for HOST_TEST.""" + + CHIP_NAME = "ESP32-C5" + mem = None + debug = False + + def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + super(EmulateEfuseController, self).__init__(efuse_file, debug) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) + + """ esptool method start >>""" + + def get_major_chip_version(self): + return 0 + + def get_minor_chip_version(self): + return 0 + + def get_crystal_freq(self): + return 40 # MHz (common for all chips) + + def get_security_info(self): + return { + "flags": 0, + "flash_crypt_cnt": 0, + "key_purposes": 0, + "chip_id": 0, + "api_version": 0, + } + + """ << esptool method end """ + + def handle_writing_event(self, addr, value): + if addr == self.REGS.EFUSE_CMD_REG: + if value & self.REGS.EFUSE_PGM_CMD: + self.copy_blocks_wr_regs_to_rd_regs(updated_block=(value >> 2) & 0xF) + self.clean_blocks_wr_regs() + self.check_rd_protection_area() + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) + elif value == self.REGS.EFUSE_READ_CMD: + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) + self.save_to_file() + + def get_bitlen_of_block(self, blk, wr=False): + if blk.id == 0: + if wr: + return 32 * 8 + else: + return 32 * blk.len + else: + if wr: + rs_coding = 32 * 3 + return 32 * 8 + rs_coding + else: + return 32 * blk.len + + def handle_coding_scheme(self, blk, data): + if blk.id != 0: + # CODING_SCHEME RS applied only for all blocks except BLK0. + coded_bytes = 12 + data.pos = coded_bytes * 8 + plain_data = data.readlist("32*uint:8")[::-1] + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(coded_bytes) + # 32 byte of data + 12 bytes RS + calc_encoded_data = list(rs.encode([x for x in plain_data])) + data.pos = 0 + if calc_encoded_data != data.readlist("44*uint:8")[::-1]: + raise FatalError("Error in coding scheme data") + data = data[coded_bytes * 8 :] + if blk.len < 8: + data = data[(8 - blk.len) * 32 :] + return data diff --git a/espefuse/efuse/esp32c5/fields.py b/espefuse/efuse/esp32c5/fields.py new file mode 100644 index 000000000..9724c9a72 --- /dev/null +++ b/espefuse/efuse/esp32c5/fields.py @@ -0,0 +1,456 @@ +# This file describes eFuses for ESP32-C5 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import binascii +import struct +import sys +import time + +from bitstring import BitArray + +import esptool + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from .. import base_fields +from .. import util + + +class EfuseBlock(base_fields.EfuseBlockBase): + def len_of_burn_unit(self): + # The writing register window is 8 registers for any blocks. + # len in bytes + return 8 * 4 + + def __init__(self, parent, param, skip_read=False): + parent.read_coding_scheme() + super(EfuseBlock, self).__init__(parent, param, skip_read=skip_read) + + def apply_coding_scheme(self): + data = self.get_raw(from_read=False)[::-1] + if len(data) < self.len_of_burn_unit(): + add_empty_bytes = self.len_of_burn_unit() - len(data) + data = data + (b"\x00" * add_empty_bytes) + if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS: + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(12) + # 32 byte of data + 12 bytes RS + encoded_data = rs.encode([x for x in data]) + words = struct.unpack("<" + "I" * 11, encoded_data) + # returns 11 words (8 words of data + 3 words of RS coding) + else: + # takes 32 bytes + words = struct.unpack("<" + ("I" * (len(data) // 4)), data) + # returns 8 words + return words + + +class EspEfuses(base_fields.EspEfusesBase): + """ + Wrapper object to manage the efuse fields in a connected ESP bootloader + """ + + debug = False + do_not_confirm = False + + def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() + self._esp = esp + self.debug = debug + self.do_not_confirm = do_not_confirm + if esp.CHIP_NAME != "ESP32-C5": + raise esptool.FatalError( + "Expected the 'esp' param for ESP32-C5 chip but got for '%s'." + % (esp.CHIP_NAME) + ) + if not skip_connect: + flags = self._esp.get_security_info()["flags"] + GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE = 1 << 2 + if flags & GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE: + raise esptool.FatalError( + "Secure Download Mode is enabled. The tool can not read eFuses." + ) + self.blocks = [ + EfuseBlock(self, self.Blocks.get(block), skip_read=skip_connect) + for block in self.Blocks.BLOCKS + ] + if not skip_connect: + self.get_coding_scheme_warnings() + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] + self.efuses += [ + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS + ] + if skip_connect: + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + else: + if self["BLK_VERSION_MINOR"].get() == 1: + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + self.efuses += [ + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC + ] + + def __getitem__(self, efuse_name): + """Return the efuse field with the given name""" + for e in self.efuses: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): + return e + new_fields = False + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + new_fields = True + if new_fields: + for e in self.efuses: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): + return e + raise KeyError + + def read_coding_scheme(self): + self.coding_scheme = self.REGS.CODING_SCHEME_RS + + def print_status_regs(self): + print("") + self.blocks[0].print_block(self.blocks[0].err_bitarray, "err__regs", debug=True) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG) + ) + ) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG) + ) + ) + + def efuse_controller_setup(self): + self.set_efuse_timing() + self.clear_pgm_registers() + self.wait_efuse_idle() + + def write_efuses(self, block): + self.efuse_program(block) + return self.get_coding_scheme_warnings(silent=True) + + def clear_pgm_registers(self): + self.wait_efuse_idle() + for r in range( + self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4 + ): + self.write_reg(r, 0) + + def wait_efuse_idle(self): + deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT + while time.time() < deadline: + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return + raise esptool.FatalError( + "Timed out waiting for Efuse controller command to complete" + ) + + def efuse_program(self, block): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE) + self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2)) + self.wait_efuse_idle() + self.clear_pgm_registers() + self.efuse_read() + + def efuse_read(self): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE) + # need to add a delay after triggering EFUSE_READ_CMD, as ROM loader checks some + # efuse registers after each command is completed + # if ENABLE_SECURITY_DOWNLOAD or DIS_DOWNLOAD_MODE is enabled by the current cmd, then we need to try to reconnect to the chip. + try: + self.write_reg( + self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_READ_CMD, delay_after_us=1000 + ) + self.wait_efuse_idle() + except esptool.FatalError: + secure_download_mode_before = self._esp.secure_download_mode + + try: + self._esp = self.reconnect_chip(self._esp) + except esptool.FatalError: + print("Can not re-connect to the chip") + if not self["DIS_DOWNLOAD_MODE"].get() and self[ + "DIS_DOWNLOAD_MODE" + ].get(from_read=False): + print( + "This is the correct behavior as we are actually burning " + "DIS_DOWNLOAD_MODE which disables the connection to the chip" + ) + print("DIS_DOWNLOAD_MODE is enabled") + print("Successful") + sys.exit(0) # finish without errors + raise + + print("Established a connection with the chip") + if self._esp.secure_download_mode and not secure_download_mode_before: + print("Secure download mode is enabled") + if not self["ENABLE_SECURITY_DOWNLOAD"].get() and self[ + "ENABLE_SECURITY_DOWNLOAD" + ].get(from_read=False): + print( + "espefuse tool can not continue to work in Secure download mode" + ) + print("ENABLE_SECURITY_DOWNLOAD is enabled") + print("Successful") + sys.exit(0) # finish without errors + raise + + def set_efuse_timing(self): + """Set timing registers for burning efuses""" + # Configure clock + apb_freq = self.get_crystal_freq() + if apb_freq not in [40, 48]: + raise esptool.FatalError( + "The eFuse supports only xtal=40M and 48M (xtal was %d)" % apb_freq + ) + + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 + ) + + def get_coding_scheme_warnings(self, silent=False): + """Check if the coding scheme has detected any errors.""" + old_addr_reg = 0 + reg_value = 0 + ret_fail = False + for block in self.blocks: + if block.id == 0: + words = [ + self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) + for offs in range(5) + ] + block.err_bitarray.pos = 0 + for word in reversed(words): + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) + block.num_errors = block.err_bitarray.count(True) + block.fail = block.num_errors != 0 + else: + addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[ + block.id + ] + if err_num_mask is None or err_num_offs is None or fail_bit is None: + continue + if addr_reg != old_addr_reg: + old_addr_reg = addr_reg + reg_value = self.read_reg(addr_reg) + block.fail = reg_value & (1 << fail_bit) != 0 + block.num_errors = (reg_value >> err_num_offs) & err_num_mask + ret_fail |= block.fail + if not silent and (block.fail or block.num_errors): + print( + "Error(s) in BLOCK%d [ERRORS:%d FAIL:%d]" + % (block.id, block.num_errors, block.fail) + ) + if (self.debug or ret_fail) and not silent: + self.print_status_regs() + return ret_fail + + def summary(self): + # TODO add support set_flash_voltage - "Flash voltage (VDD_SPI)" + return "" + + +class EfuseField(base_fields.EfuseFieldBase): + @staticmethod + def convert(parent, efuse): + return { + "mac": EfuseMacField, + "keypurpose": EfuseKeyPurposeField, + "t_sensor": EfuseTempSensor, + "adc_tp": EfuseAdcPointCalibration, + "wafer": EfuseWafer, + }.get(efuse.class_type, EfuseField)(parent, efuse) + + +class EfuseWafer(EfuseField): + def get(self, from_read=True): + hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 + lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 + return (hi_bits << 3) + lo_bits + + def save(self, new_value): + raise esptool.FatalError("Burning %s is not supported" % self.name) + + +class EfuseTempSensor(EfuseField): + def get(self, from_read=True): + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * 0.1 + + +class EfuseAdcPointCalibration(EfuseField): + def get(self, from_read=True): + STEP_SIZE = 4 + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * STEP_SIZE + + +class EfuseMacField(EfuseField): + def check_format(self, new_value_str): + if new_value_str is None: + raise esptool.FatalError( + "Required MAC Address in AA:CD:EF:01:02:03 format!" + ) + num_bytes = 8 if self.name == "MAC_EUI64" else 6 + if new_value_str.count(":") != num_bytes - 1: + raise esptool.FatalError( + f"MAC Address needs to be a {num_bytes}-byte hexadecimal format " + "separated by colons (:)!" + ) + hexad = new_value_str.replace(":", "").split(" ", 1)[0] + hexad = hexad.split(" ", 1)[0] if self.is_field_calculated() else hexad + if len(hexad) != num_bytes * 2: + raise esptool.FatalError( + f"MAC Address needs to be a {num_bytes}-byte hexadecimal number " + f"({num_bytes * 2} hexadecimal characters)!" + ) + # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', + bindata = binascii.unhexlify(hexad) + + if not self.is_field_calculated(): + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") + return bindata + + def check(self): + errs, fail = self.parent.get_block_errors(self.block) + if errs != 0 or fail: + output = "Block%d has ERRORS:%d FAIL:%d" % (self.block, errs, fail) + else: + output = "OK" + return "(" + output + ")" + + def get(self, from_read=True): + if self.name == "CUSTOM_MAC": + mac = self.get_raw(from_read)[::-1] + elif self.name == "MAC": + mac = self.get_raw(from_read) + elif self.name == "MAC_EUI64": + mac = self.parent["MAC"].get_bitstring(from_read).copy() + mac_ext = self.parent["MAC_EXT"].get_bitstring(from_read) + mac.insert(mac_ext, 24) + mac = mac.bytes + else: + mac = self.get_raw(from_read) + return "%s %s" % (util.hexify(mac, ":"), self.check()) + + def save(self, new_value): + def print_field(e, new_value): + print( + " - '{}' ({}) {} -> {}".format( + e.name, e.description, e.get_bitstring(), new_value + ) + ) + + if self.name == "CUSTOM_MAC": + bitarray_mac = self.convert_to_bitstring(new_value) + print_field(self, bitarray_mac) + super(EfuseMacField, self).save(new_value) + else: + # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, + # as it's written in the factory. + raise esptool.FatalError(f"Burning {self.name} is not supported") + + +# fmt: off +class EfuseKeyPurposeField(EfuseField): + KEY_PURPOSES = [ + ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) + ("RESERVED", 1, None, None, "no_need_rd_protect"), # Reserved + ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) + ("HMAC_DOWN_ALL", 5, None, None, "need_rd_protect"), # HMAC Downstream mode + ("HMAC_DOWN_JTAG", 6, None, None, "need_rd_protect"), # JTAG soft enable key (uses HMAC Downstream mode) + ("HMAC_DOWN_DIGITAL_SIGNATURE", 7, None, None, "need_rd_protect"), # Digital Signature peripheral key (uses HMAC Downstream mode) + ("HMAC_UP", 8, None, None, "need_rd_protect"), # HMAC Upstream mode + ("SECURE_BOOT_DIGEST0", 9, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST0 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST1", 10, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST1 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST2", 11, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST2 (Secure Boot key digest) + ] +# fmt: on + KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] + DIGEST_KEY_PURPOSES = [name[0] for name in KEY_PURPOSES if name[2] == "DIGEST"] + + def check_format(self, new_value_str): + # str convert to int: "XTS_AES_128_KEY" - > str(4) + # if int: 4 -> str(4) + raw_val = new_value_str + for purpose_name in self.KEY_PURPOSES: + if purpose_name[0] == new_value_str: + raw_val = str(purpose_name[1]) + break + if raw_val.isdigit(): + if int(raw_val) not in [p[1] for p in self.KEY_PURPOSES if p[1] > 0]: + raise esptool.FatalError("'%s' can not be set (value out of range)" % raw_val) + else: + raise esptool.FatalError("'%s' unknown name" % raw_val) + return raw_val + + def need_reverse(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[3] == "Reverse" + + def need_rd_protect(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[4] == "need_rd_protect" + + def get(self, from_read=True): + for p in self.KEY_PURPOSES: + if p[1] == self.get_raw(from_read): + return p[0] + return "FORBIDDEN_STATE" + + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + + def save(self, new_value): + raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") + return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32c5/mem_definition.py b/espefuse/efuse/esp32c5/mem_definition.py new file mode 100644 index 000000000..40786d33f --- /dev/null +++ b/espefuse/efuse/esp32c5/mem_definition.py @@ -0,0 +1,169 @@ +# This file describes eFuses fields and registers for ESP32-C5 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os + +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) + + +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 + + # EFUSE registers & command/conf values + DR_REG_EFUSE_BASE = 0x600B0800 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C + EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 + EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 + EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 + EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C + EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 + EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC + EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 + EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 + EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 + + BLOCK_ERRORS = [ + # error_reg, err_num_mask, err_num_offs, fail_bit + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 + ] + + # EFUSE_WR_TIM_CONF2_REG + EFUSE_PWR_OFF_NUM_S = 0 + EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + + +class EfuseDefineBlocks(EfuseBlocksBase): + __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE + __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG + # List of efuse blocks + # fmt: off + BLOCKS = [ + # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose + ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), + ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), + ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), + ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), + ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), + ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), + ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), + ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), + ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), + ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), + ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), + ] + # fmt: on + + def get_burn_block_data_names(self): + list_of_names = [] + for block in self.BLOCKS: + blk = self.get(block) + if blk.name: + list_of_names.append(blk.name) + if blk.alias: + for alias in blk.alias: + list_of_names.append(alias) + return list_of_names + + +class EfuseDefineFields(EfuseFieldsBase): + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + f = Field() + f.name = "MAC_EUI64" + f.block = 1 + f.bit_len = 64 + f.type = f"bytes:{f.bit_len // 8}" + f.category = "MAC" + f.class_type = "mac" + f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32c5/operations.py b/espefuse/efuse/esp32c5/operations.py new file mode 100644 index 000000000..20f2e67a4 --- /dev/null +++ b/espefuse/efuse/esp32c5/operations.py @@ -0,0 +1,413 @@ +# This file includes the operations with eFuses for ESP32-C5 chip +# +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import argparse +import os # noqa: F401. It is used in IDF scripts +import traceback + +import espsecure + +import esptool + +from . import fields +from .. import util +from ..base_operations import ( + add_common_commands, + add_force_write_always, + add_show_sensitive_info_option, + burn_bit, + burn_block_data, + burn_efuse, + check_error, + dump, + read_protect_efuse, + summary, + write_protect_efuse, +) + + +def protect_options(p): + p.add_argument( + "--no-write-protect", + help="Disable write-protecting of the key. The key remains writable. " + "(The keys use the RS coding scheme that does not support " + "post-write data changes. Forced write can damage RS encoding bits.) " + "The write-protecting of keypurposes does not depend on the option, " + "it will be set anyway.", + action="store_true", + ) + p.add_argument( + "--no-read-protect", + help="Disable read-protecting of the key. The key remains readable software." + "The key with keypurpose[USER, RESERVED and *_DIGEST] " + "will remain readable anyway. For the rest keypurposes the read-protection " + "will be defined the option (Read-protect by default).", + action="store_true", + ) + + +def add_commands(subparsers, efuses): + add_common_commands(subparsers, efuses) + burn_key = subparsers.add_parser( + "burn_key", help="Burn the key block with the specified name" + ) + protect_options(burn_key) + add_force_write_always(burn_key) + add_show_sensitive_info_option(burn_key) + burn_key.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data", + action="append", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + + burn_key_digest = subparsers.add_parser( + "burn_key_digest", + help="Parse a RSA public key and burn the digest to key efuse block", + ) + protect_options(burn_key_digest) + add_force_write_always(burn_key_digest) + add_show_sensitive_info_option(burn_key_digest) + burn_key_digest.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + action="append", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key_digest.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + + p = subparsers.add_parser( + "set_flash_voltage", + help="Permanently set the internal flash voltage regulator " + "to either 1.8V, 3.3V or OFF. " + "This means GPIO45 can be high or low at reset without " + "changing the flash voltage.", + ) + p.add_argument("voltage", help="Voltage selection", choices=["1.8V", "3.3V", "OFF"]) + + p = subparsers.add_parser( + "burn_custom_mac", help="Burn a 48-bit Custom MAC Address to EFUSE BLOCK3." + ) + p.add_argument( + "mac", + help="Custom MAC Address to burn given in hexadecimal format with bytes " + "separated by colons (e.g. AA:CD:EF:01:02:03).", + type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), + ) + add_force_write_always(p) + + p = subparsers.add_parser("get_custom_mac", help="Prints the Custom MAC Address.") + + +def burn_custom_mac(esp, efuses, args): + efuses["CUSTOM_MAC"].save(args.mac) + if not efuses.burn_all(check_batch_mode=True): + return + get_custom_mac(esp, efuses, args) + print("Successful") + + +def get_custom_mac(esp, efuses, args): + print("Custom MAC Address: {}".format(efuses["CUSTOM_MAC"].get())) + + +def set_flash_voltage(esp, efuses, args): + raise esptool.FatalError("set_flash_voltage is not supported!") + + +def adc_info(esp, efuses, args): + print("") + # fmt: off + if efuses["BLK_VERSION_MINOR"].get() == 1: + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + + print("") + print("ADC1 Calibration data stored in efuse BLOCK2:") + print(f"OCODE: {efuses['OCODE'].get()}") + print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") + print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") + print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") + print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") + print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") + print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") + print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") + print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") + print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") + print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") + print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") + print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") + print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") + print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") + print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") + else: + print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) + # fmt: on + + +def burn_key(esp, efuses, args, digest=None): + if digest is None: + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + else: + datafile_list = digest[0 : len([name for name in digest if name is not None]) :] + efuses.force_write_always = args.force_write_always + block_name_list = args.block[ + 0 : len([name for name in args.block if name is not None]) : + ] + keypurpose_list = args.keypurpose[ + 0 : len([name for name in args.keypurpose if name is not None]) : + ] + + util.check_duplicate_name_in_list(block_name_list) + if len(block_name_list) != len(datafile_list) or len(block_name_list) != len( + keypurpose_list + ): + raise esptool.FatalError( + "The number of blocks (%d), datafile (%d) and keypurpose (%d) " + "should be the same." + % (len(block_name_list), len(datafile_list), len(keypurpose_list)) + ) + + print("Burn keys to blocks:") + for block_name, datafile, keypurpose in zip( + block_name_list, datafile_list, keypurpose_list + ): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + + block_num = efuses.get_index_block_by_name(block_name) + block = efuses.blocks[block_num] + + if digest is None: + data = datafile.read() + else: + data = datafile + + print(" - %s" % (efuse.name), end=" ") + revers_msg = None + if efuses[block.key_purpose_name].need_reverse(keypurpose): + revers_msg = "\tReversing byte order for AES-XTS hardware peripheral" + data = data[::-1] + print( + "-> [{}]".format( + util.hexify(data, " ") + if args.show_sensitive_info + else " ".join(["??"] * len(data)) + ) + ) + if revers_msg: + print(revers_msg) + if len(data) != num_bytes: + raise esptool.FatalError( + "Incorrect key file size %d. Key file must be %d bytes (%d bits) " + "of raw binary key data." % (len(data), num_bytes, num_bytes * 8) + ) + + if efuses[block.key_purpose_name].need_rd_protect(keypurpose): + read_protect = False if args.no_read_protect else True + else: + read_protect = False + write_protect = not args.no_write_protect + + # using efuse instead of a block gives the advantage of checking it as the whole field. + efuse.save(data) + + disable_wr_protect_key_purpose = False + if efuses[block.key_purpose_name].get() != keypurpose: + if efuses[block.key_purpose_name].is_writeable(): + print( + "\t'%s': '%s' -> '%s'." + % ( + block.key_purpose_name, + efuses[block.key_purpose_name].get(), + keypurpose, + ) + ) + efuses[block.key_purpose_name].save(keypurpose) + disable_wr_protect_key_purpose = True + else: + raise esptool.FatalError( + "It is not possible to change '%s' to '%s' " + "because write protection bit is set." + % (block.key_purpose_name, keypurpose) + ) + else: + print("\t'%s' is already '%s'." % (block.key_purpose_name, keypurpose)) + if efuses[block.key_purpose_name].is_writeable(): + disable_wr_protect_key_purpose = True + + if disable_wr_protect_key_purpose: + print("\tDisabling write to '%s'." % block.key_purpose_name) + efuses[block.key_purpose_name].disable_write() + + if read_protect: + print("\tDisabling read to key block") + efuse.disable_read() + + if write_protect: + print("\tDisabling write to key block") + efuse.disable_write() + print("") + + if not write_protect: + print("Keys will remain writeable (due to --no-write-protect)") + if args.no_read_protect: + print("Keys will remain readable (due to --no-read-protect)") + + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") + + +def burn_key_digest(esp, efuses, args): + digest_list = [] + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + block_list = args.block[ + 0 : len([block for block in args.block if block is not None]) : + ] + for block_name, datafile in zip(block_list, datafile_list): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + digest = espsecure._digest_sbv2_public_key(datafile) + if len(digest) != num_bytes: + raise esptool.FatalError( + "Incorrect digest size %d. Digest must be %d bytes (%d bits) " + "of raw binary key data." % (len(digest), num_bytes, num_bytes * 8) + ) + digest_list.append(digest) + burn_key(esp, efuses, args, digest=digest_list) + + +def espefuse(esp, efuses, args, command): + parser = argparse.ArgumentParser() + subparsers = parser.add_subparsers(dest="operation") + add_commands(subparsers, efuses) + try: + cmd_line_args = parser.parse_args(command.split()) + except SystemExit: + traceback.print_stack() + raise esptool.FatalError('"{}" - incorrect command'.format(command)) + if cmd_line_args.operation == "execute_scripts": + configfiles = cmd_line_args.configfiles + index = cmd_line_args.index + # copy arguments from args to cmd_line_args + vars(cmd_line_args).update(vars(args)) + if cmd_line_args.operation == "execute_scripts": + cmd_line_args.configfiles = configfiles + cmd_line_args.index = index + if cmd_line_args.operation is None: + parser.print_help() + parser.exit(1) + operation_func = globals()[cmd_line_args.operation] + # each 'operation' is a module-level function of the same name + operation_func(esp, efuses, cmd_line_args) + + +def execute_scripts(esp, efuses, args): + efuses.batch_mode_cnt += 1 + del args.operation + scripts = args.scripts + del args.scripts + + for file in scripts: + with open(file.name, "r") as file: + exec(compile(file.read(), file.name, "exec")) + + if args.debug: + for block in efuses.blocks: + data = block.get_bitstring(from_read=False) + block.print_block(data, "regs_for_burn", args.debug) + + efuses.batch_mode_cnt -= 1 + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 6a75d02ac..77f780491 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -19,6 +19,7 @@ from .targets import ( ESP32C2ROM, ESP32C3ROM, + ESP32C5ROM, ESP32C5BETA3ROM, ESP32C6BETAROM, ESP32C6ROM, @@ -87,6 +88,7 @@ def select_image_class(f, chip): "esp32h2beta2": ESP32H2BETA2FirmwareImage, "esp32c2": ESP32C2FirmwareImage, "esp32c6": ESP32C6FirmwareImage, + "esp32c5": ESP32C5FirmwareImage, "esp32c5beta3": ESP32C5BETA3FirmwareImage, "esp32h2": ESP32H2FirmwareImage, "esp32p4": ESP32P4FirmwareImage, @@ -1130,6 +1132,15 @@ def set_mmu_page_size(self, size): ESP32C6ROM.BOOTLOADER_IMAGE = ESP32C6FirmwareImage +class ESP32C5FirmwareImage(ESP32C6FirmwareImage): + """ESP32C5 Firmware Image almost exactly the same as ESP32C6FirmwareImage""" + + ROM_LOADER = ESP32C5ROM + + +ESP32C5ROM.BOOTLOADER_IMAGE = ESP32C5FirmwareImage + + class ESP32C5BETA3FirmwareImage(ESP32C6FirmwareImage): """ESP32C5BETA3 Firmware Image almost exactly the same as ESP32C6FirmwareImage""" diff --git a/esptool/targets/__init__.py b/esptool/targets/__init__.py index 16e204ed4..676daf285 100644 --- a/esptool/targets/__init__.py +++ b/esptool/targets/__init__.py @@ -1,6 +1,7 @@ from .esp32 import ESP32ROM from .esp32c2 import ESP32C2ROM from .esp32c3 import ESP32C3ROM +from .esp32c5 import ESP32C5ROM from .esp32c5beta3 import ESP32C5BETA3ROM from .esp32c6 import ESP32C6ROM from .esp32c6beta import ESP32C6BETAROM @@ -26,6 +27,7 @@ "esp32h2beta2": ESP32H2BETA2ROM, "esp32c2": ESP32C2ROM, "esp32c6": ESP32C6ROM, + "esp32c5": ESP32C5ROM, "esp32c5beta3": ESP32C5BETA3ROM, "esp32h2": ESP32H2ROM, "esp32p4": ESP32P4ROM, diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py new file mode 100644 index 000000000..9d1d54a3e --- /dev/null +++ b/esptool/targets/esp32c5.py @@ -0,0 +1,99 @@ +# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import struct +import time + +from .esp32c6 import ESP32C6ROM +from ..loader import ESPLoader + + +class ESP32C5ROM(ESP32C6ROM): + CHIP_NAME = "ESP32-C5" + IMAGE_CHIP_ID = 23 + + IROM_MAP_START = 0x42000000 + IROM_MAP_END = 0x42800000 + DROM_MAP_START = 0x42800000 + DROM_MAP_END = 0x43000000 + + # Magic value for ESP32C5 + CHIP_DETECT_MAGIC_VALUE = [0xE10D8082] + + FLASH_FREQUENCY = { + "80m": 0xF, + "40m": 0x0, + "20m": 0x2, + } + + MEMORY_MAP = [ + [0x00000000, 0x00010000, "PADDING"], + [0x42800000, 0x43000000, "DROM"], + [0x40800000, 0x40860000, "DRAM"], + [0x40800000, 0x40860000, "BYTE_ACCESSIBLE"], + [0x4003A000, 0x40040000, "DROM_MASK"], + [0x40000000, 0x4003A000, "IROM_MASK"], + [0x42000000, 0x42800000, "IROM"], + [0x40800000, 0x40860000, "IRAM"], + [0x50000000, 0x50004000, "RTC_IRAM"], + [0x50000000, 0x50004000, "RTC_DRAM"], + [0x600FE000, 0x60100000, "MEM_INTERNAL2"], + ] + + def get_chip_description(self): + chip_name = { + 0: "ESP32-C5 (QFN40)", + }.get(self.get_pkg_version(), "unknown ESP32-C5") + major_rev = self.get_major_chip_version() + minor_rev = self.get_minor_chip_version() + return f"{chip_name} (revision v{major_rev}.{minor_rev})" + + def get_crystal_freq(self): + # The crystal detection algorithm of ESP32/ESP8266 + # works for ESP32-C5 as well. + return ESPLoader.get_crystal_freq(self) + + def change_baud(self, baud): + rom_with_48M_XTAL = not self.IS_STUB and self.get_crystal_freq() == 48 + if rom_with_48M_XTAL: + # The code is copied over from ESPLoader.change_baud(). + # Probably this is just a temporary solution until the next chip revision. + + # The ROM code thinks it uses a 40 MHz XTAL. Recompute the baud rate + # in order to trick the ROM code to set the correct baud rate for + # a 48 MHz XTAL. + false_rom_baud = baud * 40 // 48 + + print(f"Changing baud rate to {baud}") + self.command( + self.ESP_CHANGE_BAUDRATE, struct.pack(" Date: Tue, 12 Mar 2024 13:39:37 +0800 Subject: [PATCH 156/209] feat(esp32c5): skipped the stub check for esp32c5 mp --- .gitlab-ci.yml | 1 + .../efuse/esp32c5/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32c5/fields.py | 2 +- espefuse/efuse/esp32c5/mem_definition.py | 2 +- espefuse/efuse/esp32c5/operations.py | 2 +- esptool/targets/esp32c5.py | 67 +++++++++---------- flasher_stub/compare_stubs.py | 4 ++ 7 files changed, 40 insertions(+), 40 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 97dd36be2..df31e7781 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -96,6 +96,7 @@ host_tests: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32s3 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32s3beta2 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2beta1 + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c5 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c6 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32p4 diff --git a/espefuse/efuse/esp32c5/emulate_efuse_controller.py b/espefuse/efuse/esp32c5/emulate_efuse_controller.py index 5f634da15..40cc06fdc 100644 --- a/espefuse/efuse/esp32c5/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c5/emulate_efuse_controller.py @@ -1,6 +1,6 @@ # This file describes eFuses controller for ESP32-C5 chip # -# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later diff --git a/espefuse/efuse/esp32c5/fields.py b/espefuse/efuse/esp32c5/fields.py index 9724c9a72..ecfefd277 100644 --- a/espefuse/efuse/esp32c5/fields.py +++ b/espefuse/efuse/esp32c5/fields.py @@ -1,6 +1,6 @@ # This file describes eFuses for ESP32-C5 chip # -# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later diff --git a/espefuse/efuse/esp32c5/mem_definition.py b/espefuse/efuse/esp32c5/mem_definition.py index 40786d33f..bb31cad75 100644 --- a/espefuse/efuse/esp32c5/mem_definition.py +++ b/espefuse/efuse/esp32c5/mem_definition.py @@ -1,6 +1,6 @@ # This file describes eFuses fields and registers for ESP32-C5 chip # -# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later diff --git a/espefuse/efuse/esp32c5/operations.py b/espefuse/efuse/esp32c5/operations.py index 20f2e67a4..c2011ea9b 100644 --- a/espefuse/efuse/esp32c5/operations.py +++ b/espefuse/efuse/esp32c5/operations.py @@ -1,6 +1,6 @@ # This file includes the operations with eFuses for ESP32-C5 chip # -# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py index 9d1d54a3e..802cc52ab 100644 --- a/esptool/targets/esp32c5.py +++ b/esptool/targets/esp32c5.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: GPL-2.0-or-later @@ -18,8 +18,12 @@ class ESP32C5ROM(ESP32C6ROM): DROM_MAP_START = 0x42800000 DROM_MAP_END = 0x43000000 + PCR_SYSCLK_CONF_REG = 0x60096110 + PCR_SYSCLK_XTAL_FREQ_V = 0x7F << 24 + PCR_SYSCLK_XTAL_FREQ_S = 24 + # Magic value for ESP32C5 - CHIP_DETECT_MAGIC_VALUE = [0xE10D8082] + CHIP_DETECT_MAGIC_VALUE = [0x8082C5DC] FLASH_FREQUENCY = { "80m": 0xF, @@ -43,7 +47,7 @@ class ESP32C5ROM(ESP32C6ROM): def get_chip_description(self): chip_name = { - 0: "ESP32-C5 (QFN40)", + 0: "ESP32-C5", }.get(self.get_pkg_version(), "unknown ESP32-C5") major_rev = self.get_major_chip_version() minor_rev = self.get_minor_chip_version() @@ -54,21 +58,31 @@ def get_crystal_freq(self): # works for ESP32-C5 as well. return ESPLoader.get_crystal_freq(self) + def get_crystal_freq_rom_expect(self): + return ( + self.read_reg(self.PCR_SYSCLK_CONF_REG) & self.PCR_SYSCLK_XTAL_FREQ_V + ) >> self.PCR_SYSCLK_XTAL_FREQ_S + def change_baud(self, baud): - rom_with_48M_XTAL = not self.IS_STUB and self.get_crystal_freq() == 48 - if rom_with_48M_XTAL: - # The code is copied over from ESPLoader.change_baud(). - # Probably this is just a temporary solution until the next chip revision. - - # The ROM code thinks it uses a 40 MHz XTAL. Recompute the baud rate - # in order to trick the ROM code to set the correct baud rate for - # a 48 MHz XTAL. - false_rom_baud = baud * 40 // 48 - - print(f"Changing baud rate to {baud}") - self.command( - self.ESP_CHANGE_BAUDRATE, struct.pack(" Date: Wed, 13 Mar 2024 10:53:56 +0800 Subject: [PATCH 157/209] ci(esp32c5): add host test for esp32c5 Skipped some eFuse tests because eFuse of c5 has not been supported yet --- espefuse/efuse_defs/esp32c5.yaml | 112 +++++++++++++++++++++++++++++++ test/test_espefuse.py | 19 +++++- 2 files changed, 129 insertions(+), 2 deletions(-) create mode 100644 espefuse/efuse_defs/esp32c5.yaml diff --git a/espefuse/efuse_defs/esp32c5.yaml b/espefuse/efuse_defs/esp32c5.yaml new file mode 100644 index 000000000..db8be540b --- /dev/null +++ b/espefuse/efuse_defs/esp32c5.yaml @@ -0,0 +1,112 @@ +VER_NO: df46b69f0ed3913114ba53d3a0b2b843 +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + SWAP_UART_SDIO_EN : {show: y, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + DIS_DOWNLOAD_ICACHE : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} + RPT4_RESERVED0_1 : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} + RPT4_RESERVED0_0 : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} + RPT4_RESERVED1_0 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : DPA_SEC_LEVEL, dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} + CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} + RPT4_RESERVED2_1 : {show: n, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RPT4_RESERVED2_0 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + RPT4_RESERVED3_5 : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + RPT4_RESERVED3_4 : {show: n, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + RPT4_RESERVED3_3 : {show: n, blk : 0, word: 4, pos : 9, len : 1, start: 137, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[9]', bloc: 'B17[1]'} + RPT4_RESERVED3_2 : {show: n, blk : 0, word: 4, pos: 10, len : 2, start: 138, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[11:10]', bloc: 'B17[3:2]'} + RPT4_RESERVED3_1 : {show: n, blk : 0, word: 4, pos: 12, len : 1, start: 140, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[12]', bloc: 'B17[4]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos: 13, len : 1, start: 141, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[13]', bloc: 'B17[5]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos: 14, len : 16, start: 142, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[29:14]', bloc: 'B17[7:6],B18,B19[5:0]'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 30, len : 1, start: 158, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[30]', bloc: 'B19[6]'} + RPT4_RESERVED3_0 : {show: n, blk : 0, word: 4, pos: 31, len : 1, start: 159, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31]', bloc: 'B19[7]'} + DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 0, len : 1, start: 160, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[0]', bloc: 'B20[0]'} + DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 1, len : 1, start: 161, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1]', bloc: 'B20[1]'} + RESERVED_0_162 : {show: n, blk : 0, word: 5, pos : 2, len : 22, start: 162, type : 'uint:22', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:2]', bloc: 'B20[7:2],B21,B22'} + RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:16]', bloc: 'B6,B7'} + ACTIVE_HP_DBIAS : {show: y, blk : 1, word: 2, pos : 0, len : 5, start : 64, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the active hp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[4:0]', bloc: 'B8[4:0]'} + ACTIVE_LP_DBIAS : {show: y, blk : 1, word: 2, pos : 5, len : 5, start : 69, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the active lp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[9:5]', bloc: 'B8[7:5],B9[1:0]'} + LSLP_HP_DBG : {show: y, blk : 1, word: 2, pos: 10, len : 2, start : 74, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the lslp hp dbg, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[11:10]', bloc: 'B9[3:2]'} + LSLP_HP_DBIAS : {show: y, blk : 1, word: 2, pos: 12, len : 4, start : 76, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the lslp hp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[15:12]', bloc: 'B9[7:4]'} + DSLP_LP_DBG : {show: y, blk : 1, word: 2, pos: 16, len : 3, start : 80, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the dslp lp dbg, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[18:16]', bloc: 'B10[2:0]'} + DSLP_LP_DBIAS : {show: y, blk : 1, word: 2, pos: 19, len : 4, start : 83, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the dslp lp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[22:19]', bloc: 'B10[6:3]'} + DBIAS_VOL_GAP : {show: y, blk : 1, word: 2, pos: 23, len : 5, start : 87, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the hp and lp dbias vol gap, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[27:23]', bloc: 'B10[7],B11[3:0]'} + SPI_PAD_CONF_1 : {show: n, blk : 1, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:28]', bloc: 'B11[7:4]'} + SPI_PAD_CONF_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 4, start: 114, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[21:18]', bloc: 'B14[5:2]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 22, len : 2, start: 118, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:22]', bloc: 'B14[7:6]'} + PKG_VERSION : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'} + BLK_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'} + FLASH_CAP : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} + FLASH_TEMP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'} + FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 5, len : 3, start: 133, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[7:5]', bloc: 'B16[7:5]'} + RESERVED_1_136 : {show: n, blk : 1, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:8]', bloc: 'B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SPI_SYS_5_REG, bloc: 'B20,B21,B22,B23'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 0, len : 9, start: 128, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[8:0]', bloc: 'B16,B17[0]'} + OCODE : {show: y, blk : 2, word: 4, pos : 9, len : 8, start: 137, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[16:9]', bloc: 'B17[7:1],B18[0]'} + ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 17, len : 10, start: 145, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[26:17]', bloc: 'B18[7:1],B19[2:0]'} + ADC1_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 27, len : 10, start: 155, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:27]', bloc: 'B19[7:3],B20[4:0]'} + ADC1_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 5, len : 10, start: 165, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[14:5]', bloc: 'B20[7:5],B21[6:0]'} + ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 5, pos: 15, len : 10, start: 175, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[24:15]', bloc: 'B21[7],B22,B23[0]'} + ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 5, pos: 25, len : 10, start: 185, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:25]', bloc: 'B23[7:1],B24[2:0]'} + ADC1_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 6, pos : 3, len : 10, start: 195, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[12:3]', bloc: 'B24[7:3],B25[4:0]'} + ADC1_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 6, pos: 13, len : 10, start: 205, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[22:13]', bloc: 'B25[7:5],B26[6:0]'} + ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 6, pos: 23, len : 10, start: 215, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:23]', bloc: 'B26[7],B27,B28[0]'} + ADC1_INIT_CODE_ATTEN0_CH0 : {show: y, blk : 2, word: 7, pos : 1, len : 4, start: 225, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch0, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[4:1]', bloc: 'B28[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH1 : {show: y, blk : 2, word: 7, pos : 5, len : 4, start: 229, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch1, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[8:5]', bloc: 'B28[7:5],B29[0]'} + ADC1_INIT_CODE_ATTEN0_CH2 : {show: y, blk : 2, word: 7, pos : 9, len : 4, start: 233, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[12:9]', bloc: 'B29[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH3 : {show: y, blk : 2, word: 7, pos: 13, len : 4, start: 237, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:13]', bloc: 'B29[7:5],B30[0]'} + ADC1_INIT_CODE_ATTEN0_CH4 : {show: y, blk : 2, word: 7, pos: 17, len : 4, start: 241, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch4, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[20:17]', bloc: 'B30[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH5 : {show: y, blk : 2, word: 7, pos: 21, len : 4, start: 245, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch5, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[24:21]', bloc: 'B30[7:5],B31[0]'} + ADC1_INIT_CODE_ATTEN0_CH6 : {show: y, blk : 2, word: 7, pos: 25, len : 4, start: 249, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch6, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[28:25]', bloc: 'B31[4:1]'} + RESERVED_2_253 : {show: n, blk : 2, word: 7, pos: 29, len : 3, start: 253, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:29]', bloc: 'B31[7:5]'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 2f1a6a65e..250880c8e 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -348,6 +348,8 @@ def test_burn_and_read_protect_efuse(self): ) +# TODO: [ESP32C5] IDF-8629 +@pytest.mark.skipif(arg_chip == "esp32c5", reason="Not supported yet") class TestWriteProtectionCommands(EfuseTestCase): def test_write_protect_efuse(self): self.espefuse_py("write_protect_efuse -h") @@ -454,7 +456,17 @@ def test_burn_custom_mac_with_34_coding_scheme(self): @pytest.mark.skipif( - arg_chip in ["esp32c2", "esp32h2beta1", "esp32c3", "esp32c6", "esp32h2", "esp32p4"], + # TODO: [ESP32C5] IDF-8629 + arg_chip + in [ + "esp32c2", + "esp32h2beta1", + "esp32c3", + "esp32c6", + "esp32h2", + "esp32p4", + "esp32c5", + ], reason=f"TODO: add support set_flash_voltage for {arg_chip}", ) class TestSetFlashVoltageCommands(EfuseTestCase): @@ -666,7 +678,8 @@ def test_burn_mac_custom_efuse(self): self.espefuse_py("get_custom_mac", check_msg=f"aa:cd:ef:01:02:03 {crc_msg}") @pytest.mark.skipif( - arg_chip == "esp32p4", reason="No such eFuses, will be defined later" + arg_chip in ["esp32p4", "esp32c5"], # TODO: [ESP32C5] IDF-8629 + reason="No such eFuses, will be defined later", ) def test_burn_efuse(self): self.espefuse_py("burn_efuse -h") @@ -1776,6 +1789,8 @@ def test_2_secure_boot_v1(self): ) +# TODO: [ESP32C5] IDF-8629 +@pytest.mark.skipif(arg_chip == "esp32c5", reason="Not supported yet") class TestExecuteScriptsCommands(EfuseTestCase): @classmethod def setup_class(self): From 321887e5d5d4ebd95530529e449865b72916ebc1 Mon Sep 17 00:00:00 2001 From: wanlei Date: Wed, 28 Feb 2024 12:33:09 +0800 Subject: [PATCH 158/209] feat(esp32c61): add c61 basic flash support (no_stub) --- .gitlab-ci.yml | 1 + espefuse/__init__.py | 2 + espefuse/efuse/esp32c61/__init__.py | 3 + .../esp32c61/emulate_efuse_controller.py | 92 ++++ espefuse/efuse/esp32c61/fields.py | 453 ++++++++++++++++++ espefuse/efuse/esp32c61/mem_definition.py | 169 +++++++ espefuse/efuse/esp32c61/operations.py | 420 ++++++++++++++++ espefuse/efuse_defs/esp32c61.yaml | 91 ++++ espsecure/__init__.py | 4 +- esptool/bin_image.py | 11 + esptool/targets/__init__.py | 2 + esptool/targets/esp32c61.py | 84 ++++ flasher_stub/compare_stubs.py | 3 +- test/test_espefuse.py | 21 +- 14 files changed, 1347 insertions(+), 9 deletions(-) create mode 100644 espefuse/efuse/esp32c61/__init__.py create mode 100644 espefuse/efuse/esp32c61/emulate_efuse_controller.py create mode 100644 espefuse/efuse/esp32c61/fields.py create mode 100644 espefuse/efuse/esp32c61/mem_definition.py create mode 100644 espefuse/efuse/esp32c61/operations.py create mode 100644 espefuse/efuse_defs/esp32c61.yaml create mode 100644 esptool/targets/esp32c61.py diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index df31e7781..0d9162ad5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -98,6 +98,7 @@ host_tests: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2beta1 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c5 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c6 + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c61 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32p4 # some .coverage files in sub-directories are not collected on some runners, move them first diff --git a/espefuse/__init__.py b/espefuse/__init__.py index 7ef04489a..1bada3e7e 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -14,6 +14,7 @@ import espefuse.efuse.esp32c5 as esp32c5_efuse import espefuse.efuse.esp32c5beta3 as esp32c5beta3_efuse import espefuse.efuse.esp32c6 as esp32c6_efuse +import espefuse.efuse.esp32c61 as esp32c61_efuse import espefuse.efuse.esp32h2 as esp32h2_efuse import espefuse.efuse.esp32h2beta1 as esp32h2beta1_efuse import espefuse.efuse.esp32p4 as esp32p4_efuse @@ -51,6 +52,7 @@ "esp32c2": DefChip("ESP32-C2", esp32c2_efuse, esptool.targets.ESP32C2ROM), "esp32c3": DefChip("ESP32-C3", esp32c3_efuse, esptool.targets.ESP32C3ROM), "esp32c6": DefChip("ESP32-C6", esp32c6_efuse, esptool.targets.ESP32C6ROM), + "esp32c61": DefChip("ESP32-C61", esp32c61_efuse, esptool.targets.ESP32C61ROM), "esp32c5": DefChip("ESP32-C5", esp32c5_efuse, esptool.targets.ESP32C5ROM), "esp32c5beta3": DefChip( "ESP32-C5(beta3)", esp32c5beta3_efuse, esptool.targets.ESP32C5BETA3ROM diff --git a/espefuse/efuse/esp32c61/__init__.py b/espefuse/efuse/esp32c61/__init__.py new file mode 100644 index 000000000..a3b55a802 --- /dev/null +++ b/espefuse/efuse/esp32c61/__init__.py @@ -0,0 +1,3 @@ +from . import operations +from .emulate_efuse_controller import EmulateEfuseController +from .fields import EspEfuses diff --git a/espefuse/efuse/esp32c61/emulate_efuse_controller.py b/espefuse/efuse/esp32c61/emulate_efuse_controller.py new file mode 100644 index 000000000..ab513aca8 --- /dev/null +++ b/espefuse/efuse/esp32c61/emulate_efuse_controller.py @@ -0,0 +1,92 @@ +# This file describes eFuses controller for ESP32-C61 chip +# +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from ..emulate_efuse_controller_base import EmulateEfuseControllerBase, FatalError + + +class EmulateEfuseController(EmulateEfuseControllerBase): + """The class for virtual efuse operation. Using for HOST_TEST.""" + + CHIP_NAME = "ESP32-C61" + mem = None + debug = False + + def __init__(self, efuse_file=None, debug=False): + self.Blocks = EfuseDefineBlocks + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + super(EmulateEfuseController, self).__init__(efuse_file, debug) + self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + + """ esptool method start >>""" + + def get_major_chip_version(self): + return 0 + + def get_minor_chip_version(self): + return 0 + + def get_crystal_freq(self): + return 40 # MHz (common for all chips) + + def get_security_info(self): + return { + "flags": 0, + "flash_crypt_cnt": 0, + "key_purposes": 0, + "chip_id": 0, + "api_version": 0, + } + + """ << esptool method end """ + + def handle_writing_event(self, addr, value): + if addr == self.REGS.EFUSE_CMD_REG: + if value & self.REGS.EFUSE_PGM_CMD: + self.copy_blocks_wr_regs_to_rd_regs(updated_block=(value >> 2) & 0xF) + self.clean_blocks_wr_regs() + self.check_rd_protection_area() + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + elif value == self.REGS.EFUSE_READ_CMD: + self.write_reg(addr, 0) + self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.save_to_file() + + def get_bitlen_of_block(self, blk, wr=False): + if blk.id == 0: + if wr: + return 32 * 8 + else: + return 32 * blk.len + else: + if wr: + rs_coding = 32 * 3 + return 32 * 8 + rs_coding + else: + return 32 * blk.len + + def handle_coding_scheme(self, blk, data): + if blk.id != 0: + # CODING_SCHEME RS applied only for all blocks except BLK0. + coded_bytes = 12 + data.pos = coded_bytes * 8 + plain_data = data.readlist("32*uint:8")[::-1] + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(coded_bytes) + # 32 byte of data + 12 bytes RS + calc_encoded_data = list(rs.encode([x for x in plain_data])) + data.pos = 0 + if calc_encoded_data != data.readlist("44*uint:8")[::-1]: + raise FatalError("Error in coding scheme data") + data = data[coded_bytes * 8 :] + if blk.len < 8: + data = data[(8 - blk.len) * 32 :] + return data diff --git a/espefuse/efuse/esp32c61/fields.py b/espefuse/efuse/esp32c61/fields.py new file mode 100644 index 000000000..176041345 --- /dev/null +++ b/espefuse/efuse/esp32c61/fields.py @@ -0,0 +1,453 @@ +# This file describes eFuses for ESP32-C61 chip +# +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import binascii +import struct +import time + +from bitstring import BitArray + +import esptool + +import reedsolo + +from .mem_definition import EfuseDefineBlocks, EfuseDefineFields, EfuseDefineRegisters +from .. import base_fields +from .. import util + + +class EfuseBlock(base_fields.EfuseBlockBase): + def len_of_burn_unit(self): + # The writing register window is 8 registers for any blocks. + # len in bytes + return 8 * 4 + + def __init__(self, parent, param, skip_read=False): + parent.read_coding_scheme() + super(EfuseBlock, self).__init__(parent, param, skip_read=skip_read) + + def apply_coding_scheme(self): + data = self.get_raw(from_read=False)[::-1] + if len(data) < self.len_of_burn_unit(): + add_empty_bytes = self.len_of_burn_unit() - len(data) + data = data + (b"\x00" * add_empty_bytes) + if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS: + # takes 32 bytes + # apply RS encoding + rs = reedsolo.RSCodec(12) + # 32 byte of data + 12 bytes RS + encoded_data = rs.encode([x for x in data]) + words = struct.unpack("<" + "I" * 11, encoded_data) + # returns 11 words (8 words of data + 3 words of RS coding) + else: + # takes 32 bytes + words = struct.unpack("<" + ("I" * (len(data) // 4)), data) + # returns 8 words + return words + + +class EspEfuses(base_fields.EspEfusesBase): + """ + Wrapper object to manage the efuse fields in a connected ESP bootloader + """ + + debug = False + do_not_confirm = False + + def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + self.Blocks = EfuseDefineBlocks() + self.Fields = EfuseDefineFields() + self.REGS = EfuseDefineRegisters + self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() + self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() + self._esp = esp + self.debug = debug + self.do_not_confirm = do_not_confirm + if esp.CHIP_NAME != "ESP32-C61": + raise esptool.FatalError( + "Expected the 'esp' param for ESP32-C61 chip but got for '%s'." + % (esp.CHIP_NAME) + ) + if not skip_connect: + flags = self._esp.get_security_info()["flags"] + GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE = 1 << 2 + if flags & GET_SECURITY_INFO_FLAG_SECURE_DOWNLOAD_ENABLE: + raise esptool.FatalError( + "Secure Download Mode is enabled. The tool can not read eFuses." + ) + self.blocks = [ + EfuseBlock(self, self.Blocks.get(block), skip_read=skip_connect) + for block in self.Blocks.BLOCKS + ] + if not skip_connect: + self.get_coding_scheme_warnings() + self.efuses = [EfuseField.convert(self, efuse) for efuse in self.Fields.EFUSES] + self.efuses += [ + EfuseField.convert(self, efuse) for efuse in self.Fields.KEYBLOCKS + ] + if skip_connect: + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + else: + if self["BLK_VERSION_MINOR"].get() == 1: + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + self.efuses += [ + EfuseField.convert(self, efuse) for efuse in self.Fields.CALC + ] + + def __getitem__(self, efuse_name): + """Return the efuse field with the given name""" + for e in self.efuses: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): + return e + new_fields = False + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES: + if efuse.name == efuse_name or any( + x == efuse_name for x in efuse.alt_names + ): + self.efuses += [ + EfuseField.convert(self, efuse) + for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + ] + new_fields = True + if new_fields: + for e in self.efuses: + if efuse_name == e.name or any(x == efuse_name for x in e.alt_names): + return e + raise KeyError + + def read_coding_scheme(self): + self.coding_scheme = self.REGS.CODING_SCHEME_RS + + def print_status_regs(self): + print("") + self.blocks[0].print_block(self.blocks[0].err_bitarray, "err__regs", debug=True) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG) + ) + ) + print( + "{:27} 0x{:08x}".format( + "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG) + ) + ) + + def efuse_controller_setup(self): + self.set_efuse_timing() + self.clear_pgm_registers() + self.wait_efuse_idle() + + def write_efuses(self, block): + self.efuse_program(block) + return self.get_coding_scheme_warnings(silent=True) + + def clear_pgm_registers(self): + self.wait_efuse_idle() + for r in range( + self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4 + ): + self.write_reg(r, 0) + + def wait_efuse_idle(self): + deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT + while time.time() < deadline: + # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: + if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: + return + raise esptool.FatalError( + "Timed out waiting for Efuse controller command to complete" + ) + + def efuse_program(self, block): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE) + self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2)) + self.wait_efuse_idle() + self.clear_pgm_registers() + self.efuse_read() + + def efuse_read(self): + self.wait_efuse_idle() + self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE) + # need to add a delay after triggering EFUSE_READ_CMD, as ROM loader checks some + # efuse registers after each command is completed + # if ENABLE_SECURITY_DOWNLOAD or DIS_DOWNLOAD_MODE is enabled by the current cmd, then we need to try to reconnect to the chip. + try: + self.write_reg( + self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_READ_CMD, delay_after_us=1000 + ) + self.wait_efuse_idle() + except esptool.FatalError: + secure_download_mode_before = self._esp.secure_download_mode + + try: + self._esp = self.reconnect_chip(self._esp) + except esptool.FatalError: + print("Can not re-connect to the chip") + if not self["DIS_DOWNLOAD_MODE"].get() and self[ + "DIS_DOWNLOAD_MODE" + ].get(from_read=False): + print( + "This is the correct behavior as we are actually burning " + "DIS_DOWNLOAD_MODE which disables the connection to the chip" + ) + print("DIS_DOWNLOAD_MODE is enabled") + print("Successful") + exit(0) # finish without errors + raise + + print("Established a connection with the chip") + if self._esp.secure_download_mode and not secure_download_mode_before: + print("Secure download mode is enabled") + if not self["ENABLE_SECURITY_DOWNLOAD"].get() and self[ + "ENABLE_SECURITY_DOWNLOAD" + ].get(from_read=False): + print( + "espefuse tool can not continue to work in Secure download mode" + ) + print("ENABLE_SECURITY_DOWNLOAD is enabled") + print("Successful") + exit(0) # finish without errors + raise + + def set_efuse_timing(self): + """Set timing registers for burning efuses""" + # Configure clock + apb_freq = self.get_crystal_freq() + if apb_freq != 40: + raise esptool.FatalError( + "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq + ) + + self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF) + self.update_reg( + self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000 + ) + self.update_reg( + self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190 + ) + + def get_coding_scheme_warnings(self, silent=False): + """Check if the coding scheme has detected any errors.""" + old_addr_reg = 0 + reg_value = 0 + ret_fail = False + for block in self.blocks: + if block.id == 0: + words = [ + self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4) + for offs in range(5) + ] + block.err_bitarray.pos = 0 + for word in reversed(words): + block.err_bitarray.overwrite(BitArray("uint:32=%d" % word)) + block.num_errors = block.err_bitarray.count(True) + block.fail = block.num_errors != 0 + else: + addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[ + block.id + ] + if err_num_mask is None or err_num_offs is None or fail_bit is None: + continue + if addr_reg != old_addr_reg: + old_addr_reg = addr_reg + reg_value = self.read_reg(addr_reg) + block.fail = reg_value & (1 << fail_bit) != 0 + block.num_errors = (reg_value >> err_num_offs) & err_num_mask + ret_fail |= block.fail + if not silent and (block.fail or block.num_errors): + print( + "Error(s) in BLOCK%d [ERRORS:%d FAIL:%d]" + % (block.id, block.num_errors, block.fail) + ) + if (self.debug or ret_fail) and not silent: + self.print_status_regs() + return ret_fail + + def summary(self): + # TODO add support set_flash_voltage - "Flash voltage (VDD_SPI)" + return "" + + +class EfuseField(base_fields.EfuseFieldBase): + @staticmethod + def convert(parent, efuse): + return { + "mac": EfuseMacField, + "keypurpose": EfuseKeyPurposeField, + "t_sensor": EfuseTempSensor, + "adc_tp": EfuseAdcPointCalibration, + "wafer": EfuseWafer, + }.get(efuse.class_type, EfuseField)(parent, efuse) + + +class EfuseWafer(EfuseField): + def get(self, from_read=True): + hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1 + lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read) + assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3 + return (hi_bits << 3) + lo_bits + + def save(self, new_value): + raise esptool.FatalError("Burning %s is not supported" % self.name) + + +class EfuseTempSensor(EfuseField): + def get(self, from_read=True): + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * 0.1 + + +class EfuseAdcPointCalibration(EfuseField): + def get(self, from_read=True): + STEP_SIZE = 4 + value = self.get_bitstring(from_read) + sig = -1 if value[0] else 1 + return sig * value[1:].uint * STEP_SIZE + + +class EfuseMacField(EfuseField): + def check_format(self, new_value_str): + if new_value_str is None: + raise esptool.FatalError( + "Required MAC Address in AA:CD:EF:01:02:03 format!" + ) + num_bytes = 8 if self.name == "MAC_EUI64" else 6 + if new_value_str.count(":") != num_bytes - 1: + raise esptool.FatalError( + f"MAC Address needs to be a {num_bytes}-byte hexadecimal format " + "separated by colons (:)!" + ) + hexad = new_value_str.replace(":", "").split(" ", 1)[0] + hexad = hexad.split(" ", 1)[0] if self.is_field_calculated() else hexad + if len(hexad) != num_bytes * 2: + raise esptool.FatalError( + f"MAC Address needs to be a {num_bytes}-byte hexadecimal number " + f"({num_bytes * 2} hexadecimal characters)!" + ) + # order of bytearray = b'\xaa\xcd\xef\x01\x02\x03', + bindata = binascii.unhexlify(hexad) + + if not self.is_field_calculated(): + # unicast address check according to + # https://tools.ietf.org/html/rfc7042#section-2.1 + if esptool.util.byte(bindata, 0) & 0x01: + raise esptool.FatalError("Custom MAC must be a unicast MAC!") + return bindata + + def check(self): + errs, fail = self.parent.get_block_errors(self.block) + if errs != 0 or fail: + output = "Block%d has ERRORS:%d FAIL:%d" % (self.block, errs, fail) + else: + output = "OK" + return "(" + output + ")" + + def get(self, from_read=True): + if self.name == "CUSTOM_MAC": + mac = self.get_raw(from_read)[::-1] + elif self.name == "MAC": + mac = self.get_raw(from_read) + elif self.name == "MAC_EUI64": + mac = self.parent["MAC"].get_bitstring(from_read).copy() + mac_ext = self.parent["MAC_EXT"].get_bitstring(from_read) + mac.insert(mac_ext, 24) + mac = mac.bytes + else: + mac = self.get_raw(from_read) + return "%s %s" % (util.hexify(mac, ":"), self.check()) + + def save(self, new_value): + def print_field(e, new_value): + print( + " - '{}' ({}) {} -> {}".format( + e.name, e.description, e.get_bitstring(), new_value + ) + ) + + if self.name == "CUSTOM_MAC": + bitarray_mac = self.convert_to_bitstring(new_value) + print_field(self, bitarray_mac) + super(EfuseMacField, self).save(new_value) + else: + # Writing the BLOCK1 (MAC_SPI_8M_0) default MAC is not possible, + # as it's written in the factory. + raise esptool.FatalError(f"Burning {self.name} is not supported") + + +# fmt: off +class EfuseKeyPurposeField(EfuseField): + KEY_PURPOSES = [ + ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) + ("ECDSA_KEY", 1, None, "Reverse", "need_rd_protect"), # ECDSA key + ("XTS_AES_256_KEY_1", 2, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_1 (flash/PSRAM encryption) + ("XTS_AES_256_KEY_2", 3, None, "Reverse", "need_rd_protect"), # XTS_AES_256_KEY_2 (flash/PSRAM encryption) + ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) + ("HMAC_DOWN_ALL", 5, None, None, "need_rd_protect"), # HMAC Downstream mode + ("HMAC_DOWN_JTAG", 6, None, None, "need_rd_protect"), # JTAG soft enable key (uses HMAC Downstream mode) + ("HMAC_DOWN_DIGITAL_SIGNATURE", 7, None, None, "need_rd_protect"), # Digital Signature peripheral key (uses HMAC Downstream mode) + ("HMAC_UP", 8, None, None, "need_rd_protect"), # HMAC Upstream mode + ("SECURE_BOOT_DIGEST0", 9, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST0 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST1", 10, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST1 (Secure Boot key digest) + ("SECURE_BOOT_DIGEST2", 11, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST2 (Secure Boot key digest) + ] +# fmt: on + KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] + DIGEST_KEY_PURPOSES = [name[0] for name in KEY_PURPOSES if name[2] == "DIGEST"] + + def check_format(self, new_value_str): + # str convert to int: "XTS_AES_128_KEY" - > str(4) + # if int: 4 -> str(4) + raw_val = new_value_str + for purpose_name in self.KEY_PURPOSES: + if purpose_name[0] == new_value_str: + raw_val = str(purpose_name[1]) + break + if raw_val.isdigit(): + if int(raw_val) not in [p[1] for p in self.KEY_PURPOSES if p[1] > 0]: + raise esptool.FatalError("'%s' can not be set (value out of range)" % raw_val) + else: + raise esptool.FatalError("'%s' unknown name" % raw_val) + return raw_val + + def need_reverse(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[3] == "Reverse" + + def need_rd_protect(self, new_key_purpose): + for key in self.KEY_PURPOSES: + if key[0] == new_key_purpose: + return key[4] == "need_rd_protect" + + def get(self, from_read=True): + for p in self.KEY_PURPOSES: + if p[1] == self.get_raw(from_read): + return p[0] + return "FORBIDDEN_STATE" + + def get_name(self, raw_val): + for key in self.KEY_PURPOSES: + if key[1] == raw_val: + return key[0] + + def save(self, new_value): + raw_val = int(self.check_format(str(new_value))) + str_new_value = self.get_name(raw_val) + if self.name == "KEY_PURPOSE_5" and str_new_value.startswith("XTS_AES"): + raise esptool.FatalError(f"{self.name} can not have {str_new_value} key due to a hardware bug (please see TRM for more details)") + return super(EfuseKeyPurposeField, self).save(raw_val) diff --git a/espefuse/efuse/esp32c61/mem_definition.py b/espefuse/efuse/esp32c61/mem_definition.py new file mode 100644 index 000000000..0b8f7048d --- /dev/null +++ b/espefuse/efuse/esp32c61/mem_definition.py @@ -0,0 +1,169 @@ +# This file describes eFuses fields and registers for ESP32-C61 chip +# +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os + +import yaml + +from ..mem_definition_base import ( + EfuseBlocksBase, + EfuseFieldsBase, + EfuseRegistersBase, + Field, +) + + +class EfuseDefineRegisters(EfuseRegistersBase): + EFUSE_MEM_SIZE = 0x01FC + 4 + + # EFUSE registers & command/conf values + DR_REG_EFUSE_BASE = 0x600B4800 + EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE + EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 + EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 + EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x1CC + EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x1D0 + EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x1D4 + EFUSE_RD_RS_ERR0_REG = DR_REG_EFUSE_BASE + 0x1C0 + EFUSE_RD_RS_ERR1_REG = DR_REG_EFUSE_BASE + 0x1C4 + EFUSE_RD_REPEAT_ERR0_REG = DR_REG_EFUSE_BASE + 0x17C + EFUSE_RD_REPEAT_ERR1_REG = DR_REG_EFUSE_BASE + 0x180 + EFUSE_RD_REPEAT_ERR2_REG = DR_REG_EFUSE_BASE + 0x184 + EFUSE_RD_REPEAT_ERR3_REG = DR_REG_EFUSE_BASE + 0x188 + EFUSE_RD_REPEAT_ERR4_REG = DR_REG_EFUSE_BASE + 0x18C + EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x1E8 + EFUSE_RD_TIM_CONF_REG = DR_REG_EFUSE_BASE + 0x1EC + EFUSE_WR_TIM_CONF1_REG = DR_REG_EFUSE_BASE + 0x1F0 + EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x1F4 + EFUSE_DATE_REG = DR_REG_EFUSE_BASE + 0x1FC + EFUSE_WRITE_OP_CODE = 0x5A5A + EFUSE_READ_OP_CODE = 0x5AA5 + EFUSE_PGM_CMD_MASK = 0x3 + EFUSE_PGM_CMD = 0x2 + EFUSE_READ_CMD = 0x1 + + BLOCK_ERRORS = [ + # error_reg, err_num_mask, err_num_offs, fail_bit + (EFUSE_RD_REPEAT_ERR0_REG, None, None, None), # BLOCK0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 0, 3), # MAC_SPI_8M_0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 4, 7), # BLOCK_SYS_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 8, 11), # BLOCK_USR_DATA + (EFUSE_RD_RS_ERR0_REG, 0x7, 12, 15), # BLOCK_KEY0 + (EFUSE_RD_RS_ERR0_REG, 0x7, 16, 19), # BLOCK_KEY1 + (EFUSE_RD_RS_ERR0_REG, 0x7, 20, 23), # BLOCK_KEY2 + (EFUSE_RD_RS_ERR0_REG, 0x7, 24, 27), # BLOCK_KEY3 + (EFUSE_RD_RS_ERR0_REG, 0x7, 28, 31), # BLOCK_KEY4 + (EFUSE_RD_RS_ERR1_REG, 0x7, 0, 3), # BLOCK_KEY5 + (EFUSE_RD_RS_ERR1_REG, 0x7, 4, 7), # BLOCK_SYS_DATA2 + ] + + # EFUSE_WR_TIM_CONF2_REG + EFUSE_PWR_OFF_NUM_S = 0 + EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S + + # EFUSE_WR_TIM_CONF1_REG + EFUSE_PWR_ON_NUM_S = 8 + EFUSE_PWR_ON_NUM_M = 0x0000FFFF << EFUSE_PWR_ON_NUM_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_CLK_DIV_S = 0 + EFUSE_DAC_CLK_DIV_M = 0xFF << EFUSE_DAC_CLK_DIV_S + + # EFUSE_DAC_CONF_REG + EFUSE_DAC_NUM_S = 9 + EFUSE_DAC_NUM_M = 0xFF << EFUSE_DAC_NUM_S + + +class EfuseDefineBlocks(EfuseBlocksBase): + __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE + __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG + # List of efuse blocks + # fmt: off + BLOCKS = [ + # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose + ("BLOCK0", [], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 6, None), + ("MAC_SPI_8M_0", ["BLOCK1"], 1, __base_rd_regs + 0x044, __base_wr_regs, 20, None, 6, None), + ("BLOCK_SYS_DATA", ["BLOCK2"], 2, __base_rd_regs + 0x05C, __base_wr_regs, 21, None, 8, None), + ("BLOCK_USR_DATA", ["BLOCK3"], 3, __base_rd_regs + 0x07C, __base_wr_regs, 22, None, 8, None), + ("BLOCK_KEY0", ["BLOCK4"], 4, __base_rd_regs + 0x09C, __base_wr_regs, 23, 0, 8, "KEY_PURPOSE_0"), + ("BLOCK_KEY1", ["BLOCK5"], 5, __base_rd_regs + 0x0BC, __base_wr_regs, 24, 1, 8, "KEY_PURPOSE_1"), + ("BLOCK_KEY2", ["BLOCK6"], 6, __base_rd_regs + 0x0DC, __base_wr_regs, 25, 2, 8, "KEY_PURPOSE_2"), + ("BLOCK_KEY3", ["BLOCK7"], 7, __base_rd_regs + 0x0FC, __base_wr_regs, 26, 3, 8, "KEY_PURPOSE_3"), + ("BLOCK_KEY4", ["BLOCK8"], 8, __base_rd_regs + 0x11C, __base_wr_regs, 27, 4, 8, "KEY_PURPOSE_4"), + ("BLOCK_KEY5", ["BLOCK9"], 9, __base_rd_regs + 0x13C, __base_wr_regs, 28, 5, 8, "KEY_PURPOSE_5"), + ("BLOCK_SYS_DATA2", ["BLOCK10"], 10, __base_rd_regs + 0x15C, __base_wr_regs, 29, 6, 8, None), + ] + # fmt: on + + def get_burn_block_data_names(self): + list_of_names = [] + for block in self.BLOCKS: + blk = self.get(block) + if blk.name: + list_of_names.append(blk.name) + if blk.alias: + for alias in blk.alias: + list_of_names.append(alias) + return list_of_names + + +class EfuseDefineFields(EfuseFieldsBase): + def __init__(self) -> None: + # List of efuse fields from TRM the chapter eFuse Controller. + self.EFUSES = [] + + self.KEYBLOCKS = [] + + # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 + self.BLOCK2_CALIBRATION_EFUSES = [] + + self.CALC = [] + + dir_name = os.path.dirname(os.path.abspath(__file__)) + dir_name, file_name = os.path.split(dir_name) + file_name = file_name + ".yaml" + dir_name, _ = os.path.split(dir_name) + efuse_file = os.path.join(dir_name, "efuse_defs", file_name) + with open(f"{efuse_file}", "r") as r_file: + e_desc = yaml.safe_load(r_file) + super().__init__(e_desc) + + for i, efuse in enumerate(self.ALL_EFUSES): + if efuse.name in [ + "BLOCK_USR_DATA", + "BLOCK_KEY0", + "BLOCK_KEY1", + "BLOCK_KEY2", + "BLOCK_KEY3", + "BLOCK_KEY4", + "BLOCK_KEY5", + "BLOCK_SYS_DATA2", + ]: + if efuse.name == "BLOCK_USR_DATA": + efuse.bit_len = 256 + efuse.type = "bytes:32" + self.KEYBLOCKS.append(efuse) + self.ALL_EFUSES[i] = None + + elif efuse.category == "calibration": + self.BLOCK2_CALIBRATION_EFUSES.append(efuse) + self.ALL_EFUSES[i] = None + + f = Field() + f.name = "MAC_EUI64" + f.block = 1 + f.bit_len = 64 + f.type = f"bytes:{f.bit_len // 8}" + f.category = "MAC" + f.class_type = "mac" + f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" + self.CALC.append(f) + + for efuse in self.ALL_EFUSES: + if efuse is not None: + self.EFUSES.append(efuse) + + self.ALL_EFUSES = [] diff --git a/espefuse/efuse/esp32c61/operations.py b/espefuse/efuse/esp32c61/operations.py new file mode 100644 index 000000000..41892679d --- /dev/null +++ b/espefuse/efuse/esp32c61/operations.py @@ -0,0 +1,420 @@ +# This file includes the operations with eFuses for ESP32-C61 chip +# +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import argparse +import os # noqa: F401. It is used in IDF scripts +import traceback + +import espsecure + +import esptool + +from . import fields +from .. import util +from ..base_operations import ( + add_common_commands, + add_force_write_always, + add_show_sensitive_info_option, + burn_bit, + burn_block_data, + burn_efuse, + check_error, + dump, + read_protect_efuse, + summary, + write_protect_efuse, +) + + +def protect_options(p): + p.add_argument( + "--no-write-protect", + help="Disable write-protecting of the key. The key remains writable. " + "(The keys use the RS coding scheme that does not support " + "post-write data changes. Forced write can damage RS encoding bits.) " + "The write-protecting of keypurposes does not depend on the option, " + "it will be set anyway.", + action="store_true", + ) + p.add_argument( + "--no-read-protect", + help="Disable read-protecting of the key. The key remains readable software." + "The key with keypurpose[USER, RESERVED and *_DIGEST] " + "will remain readable anyway. For the rest keypurposes the read-protection " + "will be defined the option (Read-protect by default).", + action="store_true", + ) + + +def add_commands(subparsers, efuses): + add_common_commands(subparsers, efuses) + burn_key = subparsers.add_parser( + "burn_key", help="Burn the key block with the specified name" + ) + protect_options(burn_key) + add_force_write_always(burn_key) + add_show_sensitive_info_option(burn_key) + burn_key.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", + action="append", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key.add_argument( + "keyfile", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.KEY_PURPOSES_NAME, + ) + + burn_key_digest = subparsers.add_parser( + "burn_key_digest", + help="Parse a RSA public key and burn the digest to key efuse block", + ) + protect_options(burn_key_digest) + add_force_write_always(burn_key_digest) + add_show_sensitive_info_option(burn_key_digest) + burn_key_digest.add_argument( + "block", + help="Key block to burn", + action="append", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + action="append", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + action="append", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + for _ in efuses.BLOCKS_FOR_KEYS: + burn_key_digest.add_argument( + "block", + help="Key block to burn", + nargs="?", + action="append", + metavar="BLOCK", + choices=efuses.BLOCKS_FOR_KEYS, + ) + burn_key_digest.add_argument( + "keyfile", + help="Key file to digest (PEM format)", + nargs="?", + action="append", + metavar="KEYFILE", + type=argparse.FileType("rb"), + ) + burn_key_digest.add_argument( + "keypurpose", + help="Purpose to set.", + nargs="?", + action="append", + metavar="KEYPURPOSE", + choices=fields.EfuseKeyPurposeField.DIGEST_KEY_PURPOSES, + ) + + p = subparsers.add_parser( + "set_flash_voltage", + help="Permanently set the internal flash voltage regulator " + "to either 1.8V, 3.3V or OFF. " + "This means GPIO45 can be high or low at reset without " + "changing the flash voltage.", + ) + p.add_argument("voltage", help="Voltage selection", choices=["1.8V", "3.3V", "OFF"]) + + p = subparsers.add_parser( + "burn_custom_mac", help="Burn a 48-bit Custom MAC Address to EFUSE BLOCK3." + ) + p.add_argument( + "mac", + help="Custom MAC Address to burn given in hexadecimal format with bytes " + "separated by colons (e.g. AA:CD:EF:01:02:03).", + type=fields.base_fields.CheckArgValue(efuses, "CUSTOM_MAC"), + ) + add_force_write_always(p) + + p = subparsers.add_parser("get_custom_mac", help="Prints the Custom MAC Address.") + + +def burn_custom_mac(esp, efuses, args): + efuses["CUSTOM_MAC"].save(args.mac) + if not efuses.burn_all(check_batch_mode=True): + return + get_custom_mac(esp, efuses, args) + print("Successful") + + +def get_custom_mac(esp, efuses, args): + print("Custom MAC Address: {}".format(efuses["CUSTOM_MAC"].get())) + + +def set_flash_voltage(esp, efuses, args): + raise esptool.FatalError("set_flash_voltage is not supported!") + + +def adc_info(esp, efuses, args): + print("") + # fmt: off + if efuses["BLK_VERSION_MINOR"].get() == 1: + print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + + print("") + print("ADC1 Calibration data stored in efuse BLOCK2:") + print(f"OCODE: {efuses['OCODE'].get()}") + print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") + print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") + print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") + print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") + print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") + print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") + print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") + print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") + print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") + print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") + print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") + print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") + print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") + print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") + print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") + else: + print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) + # fmt: on + + +def burn_key(esp, efuses, args, digest=None): + if digest is None: + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + else: + datafile_list = digest[0 : len([name for name in digest if name is not None]) :] + efuses.force_write_always = args.force_write_always + block_name_list = args.block[ + 0 : len([name for name in args.block if name is not None]) : + ] + keypurpose_list = args.keypurpose[ + 0 : len([name for name in args.keypurpose if name is not None]) : + ] + + util.check_duplicate_name_in_list(block_name_list) + if len(block_name_list) != len(datafile_list) or len(block_name_list) != len( + keypurpose_list + ): + raise esptool.FatalError( + "The number of blocks (%d), datafile (%d) and keypurpose (%d) " + "should be the same." + % (len(block_name_list), len(datafile_list), len(keypurpose_list)) + ) + + print("Burn keys to blocks:") + for block_name, datafile, keypurpose in zip( + block_name_list, datafile_list, keypurpose_list + ): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + + block_num = efuses.get_index_block_by_name(block_name) + block = efuses.blocks[block_num] + + if digest is None: + if keypurpose == "ECDSA_KEY": + sk = espsecure._load_ecdsa_signing_key(datafile) + data = sk.to_string() + if len(data) == 24: + # the private key is 24 bytes long for NIST192p, and 8 bytes of padding + data = b"\x00" * 8 + data + else: + data = datafile.read() + else: + data = datafile + + print(" - %s" % (efuse.name), end=" ") + revers_msg = None + if efuses[block.key_purpose_name].need_reverse(keypurpose): + revers_msg = f"\tReversing byte order for {keypurpose} hardware peripheral" + data = data[::-1] + print( + "-> [{}]".format( + util.hexify(data, " ") + if args.show_sensitive_info + else " ".join(["??"] * len(data)) + ) + ) + if revers_msg: + print(revers_msg) + if len(data) != num_bytes: + raise esptool.FatalError( + "Incorrect key file size %d. Key file must be %d bytes (%d bits) " + "of raw binary key data." % (len(data), num_bytes, num_bytes * 8) + ) + + if efuses[block.key_purpose_name].need_rd_protect(keypurpose): + read_protect = False if args.no_read_protect else True + else: + read_protect = False + write_protect = not args.no_write_protect + + # using efuse instead of a block gives the advantage of checking it as the whole field. + efuse.save(data) + + disable_wr_protect_key_purpose = False + if efuses[block.key_purpose_name].get() != keypurpose: + if efuses[block.key_purpose_name].is_writeable(): + print( + "\t'%s': '%s' -> '%s'." + % ( + block.key_purpose_name, + efuses[block.key_purpose_name].get(), + keypurpose, + ) + ) + efuses[block.key_purpose_name].save(keypurpose) + disable_wr_protect_key_purpose = True + else: + raise esptool.FatalError( + "It is not possible to change '%s' to '%s' " + "because write protection bit is set." + % (block.key_purpose_name, keypurpose) + ) + else: + print("\t'%s' is already '%s'." % (block.key_purpose_name, keypurpose)) + if efuses[block.key_purpose_name].is_writeable(): + disable_wr_protect_key_purpose = True + + if disable_wr_protect_key_purpose: + print("\tDisabling write to '%s'." % block.key_purpose_name) + efuses[block.key_purpose_name].disable_write() + + if read_protect: + print("\tDisabling read to key block") + efuse.disable_read() + + if write_protect: + print("\tDisabling write to key block") + efuse.disable_write() + print("") + + if not write_protect: + print("Keys will remain writeable (due to --no-write-protect)") + if args.no_read_protect: + print("Keys will remain readable (due to --no-read-protect)") + + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") + + +def burn_key_digest(esp, efuses, args): + digest_list = [] + datafile_list = args.keyfile[ + 0 : len([name for name in args.keyfile if name is not None]) : + ] + block_list = args.block[ + 0 : len([block for block in args.block if block is not None]) : + ] + for block_name, datafile in zip(block_list, datafile_list): + efuse = None + for block in efuses.blocks: + if block_name == block.name or block_name in block.alias: + efuse = efuses[block.name] + if efuse is None: + raise esptool.FatalError("Unknown block name - %s" % (block_name)) + num_bytes = efuse.bit_len // 8 + digest = espsecure._digest_sbv2_public_key(datafile) + if len(digest) != num_bytes: + raise esptool.FatalError( + "Incorrect digest size %d. Digest must be %d bytes (%d bits) " + "of raw binary key data." % (len(digest), num_bytes, num_bytes * 8) + ) + digest_list.append(digest) + burn_key(esp, efuses, args, digest=digest_list) + + +def espefuse(esp, efuses, args, command): + parser = argparse.ArgumentParser() + subparsers = parser.add_subparsers(dest="operation") + add_commands(subparsers, efuses) + try: + cmd_line_args = parser.parse_args(command.split()) + except SystemExit: + traceback.print_stack() + raise esptool.FatalError('"{}" - incorrect command'.format(command)) + if cmd_line_args.operation == "execute_scripts": + configfiles = cmd_line_args.configfiles + index = cmd_line_args.index + # copy arguments from args to cmd_line_args + vars(cmd_line_args).update(vars(args)) + if cmd_line_args.operation == "execute_scripts": + cmd_line_args.configfiles = configfiles + cmd_line_args.index = index + if cmd_line_args.operation is None: + parser.print_help() + parser.exit(1) + operation_func = globals()[cmd_line_args.operation] + # each 'operation' is a module-level function of the same name + operation_func(esp, efuses, cmd_line_args) + + +def execute_scripts(esp, efuses, args): + efuses.batch_mode_cnt += 1 + del args.operation + scripts = args.scripts + del args.scripts + + for file in scripts: + with open(file.name, "r") as file: + exec(compile(file.read(), file.name, "exec")) + + if args.debug: + for block in efuses.blocks: + data = block.get_bitstring(from_read=False) + block.print_block(data, "regs_for_burn", args.debug) + + efuses.batch_mode_cnt -= 1 + if not efuses.burn_all(check_batch_mode=True): + return + print("Successful") diff --git a/espefuse/efuse_defs/esp32c61.yaml b/espefuse/efuse_defs/esp32c61.yaml new file mode 100644 index 000000000..4600e0da5 --- /dev/null +++ b/espefuse/efuse_defs/esp32c61.yaml @@ -0,0 +1,91 @@ +VER_NO: 709e8ea096e8a03a10006d40d5451a49 +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_SERIAL_JTAG : {show: y, blk : 0, word: 1, pos: 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[4]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[5]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 15, len : 2, start : 47, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[16:15]', bloc: 'B5[7:6]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 17, len : 2, start : 49, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:17]', bloc: 'B6[1:0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[2]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[3]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[5:4]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 1, pos: 23, len : 3, start : 55, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25:23]', bloc: 'B7[0],B6[7:6]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[1]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 1, pos: 27, len : 1, start : 59, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[27]', bloc: 'B7[2]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 1, pos: 28, len : 1, start : 60, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28]', bloc: 'B7[3]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 0, len : 4, start : 64, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[3:0]', bloc: 'B8[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 4, len : 4, start : 68, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[7:4]', bloc: 'B8[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 2, pos : 8, len : 4, start : 72, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[11:8]', bloc: 'B9[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 2, pos : 12,len : 4, start: 76, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:12]', bloc: 'B9[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 2, pos : 16, len : 4, start: 80, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[19:16]', bloc: 'B10[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 2, pos: 20, len : 4, start: 84, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23:20]', bloc: 'B10[7:4]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 2, pos: 24, len : 2, start: 88, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : DPA_SEC_LEVEL, dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[25:24]', bloc: 'B11[1:0]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 2, pos: 26, len : 1, start: 90, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[26]', bloc: 'B11[2]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 2, pos: 27, len : 1, start: 91, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27]', bloc: 'B11[3]'} + FLASH_TPUW : {show: y, blk : 0, word: 2, pos: 28, len : 4, start: 92, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 3, pos : 0, len : 1, start: 96, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[0]', bloc: 'B12[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 3, pos : 1, len : 1, start: 97, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[1]', bloc: 'B12[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 3, pos : 2, len : 1, start: 98, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[2]', bloc: 'B12[2]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 3, pos : 3, len : 1, start: 99, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3]', bloc: 'B12[3]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 3, pos : 4, len : 1, start: 100, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[4]', bloc: 'B12[4]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 3, pos : 5, len : 2, start: 101, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[6:5]', bloc: 'B12[6:5]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 3, pos: 7, len : 1, start: 103, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7]', bloc: 'B12[7]'} + SECURE_VERSION : {show: y, blk : 0, word: 3, pos: 8, len : 16, start: 104, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23:8]', bloc: 'B14,B13'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 3, pos: 24, len : 1, start: 120, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[24]', bloc: 'B15[0]'} + HAS_EN_PAD : {show: y, blk : 0, word: 3, pos: 25, len : 1, start: 121, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[25]', bloc: 'B15[1]'} + XTS_DPA_CLK_ENABLE : {show: y, blk : 0, word: 3, pos: 26, len : 1, start: 122, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26]', bloc: 'B15[2]'} + XTS_DPA_PSEUDO_LEVEL : {show: y, blk : 0, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[28:27]', bloc: 'B15[4:3]'} + DIS_WIFI6 : {show: y, blk : 0, word: 3, pos: 29, len : 1, start: 125, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Disable wifi6', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[29]', bloc: 'B15[5]'} + ECDSA_DISABLE_P192 : {show: y, blk : 0, word: 3, pos: 30, len : 1, start: 126, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'ECDSA disable P192', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[30]', bloc: 'B15[6]'} + ECC_FORCE_CONST_TIME : {show: y, blk : 0, word: 3, pos: 31, len : 1, start: 127, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'ECC force const time', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31]', bloc: 'B15[7]'} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:16]', bloc: 'B6,B7'} + MAC_SPI_RESERVED : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} + SPI_PAD_CONF_1 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + SPI_PAD_CONF_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 4, start: 114, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[21:18]', bloc: 'B14[5:2]'} + WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 22, len : 2, start: 118, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:22]', bloc: 'B14[7:6]'} + PKG_VERSION : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} + BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'} + BLK_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'} + FLASH_CAP : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} + FLASH_TEMP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'} + FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 5, len : 3, start: 133, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[7:5]', bloc: 'B16[7:5]'} + RESERVED_1_136 : {show: n, blk : 1, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:8]', bloc: 'B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SPI_SYS_5_REG, bloc: 'B20,B21,B22,B23'} + OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} + TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 0, len : 9, start: 128, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[8:0]', bloc: 'B16,B17[0]'} + OCODE : {show: y, blk : 2, word: 4, pos : 9, len : 8, start: 137, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[16:9]', bloc: 'B17[7:1],B18[0]'} + ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 17, len : 10, start: 145, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[26:17]', bloc: 'B18[7:1],B19[2:0]'} + ADC1_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 27, len : 10, start: 155, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:27]', bloc: 'B19[7:3],B20[4:0]'} + ADC1_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 5, len : 10, start: 165, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[14:5]', bloc: 'B20[7:5],B21[6:0]'} + ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 5, pos: 15, len : 10, start: 175, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[24:15]', bloc: 'B21[7],B22,B23[0]'} + ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 5, pos: 25, len : 10, start: 185, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:25]', bloc: 'B23[7:1],B24[2:0]'} + ADC1_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 6, pos : 3, len : 10, start: 195, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[12:3]', bloc: 'B24[7:3],B25[4:0]'} + ADC1_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 6, pos: 13, len : 10, start: 205, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[22:13]', bloc: 'B25[7:5],B26[6:0]'} + ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 6, pos: 23, len : 10, start: 215, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:23]', bloc: 'B26[7],B27,B28[0]'} + ADC1_INIT_CODE_ATTEN0_CH0 : {show: y, blk : 2, word: 7, pos : 1, len : 4, start: 225, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch0, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[4:1]', bloc: 'B28[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH1 : {show: y, blk : 2, word: 7, pos : 5, len : 4, start: 229, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch1, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[8:5]', bloc: 'B28[7:5],B29[0]'} + ADC1_INIT_CODE_ATTEN0_CH2 : {show: y, blk : 2, word: 7, pos : 9, len : 4, start: 233, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[12:9]', bloc: 'B29[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH3 : {show: y, blk : 2, word: 7, pos: 13, len : 4, start: 237, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:13]', bloc: 'B29[7:5],B30[0]'} + ADC1_INIT_CODE_ATTEN0_CH4 : {show: y, blk : 2, word: 7, pos: 17, len : 4, start: 241, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch4, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[20:17]', bloc: 'B30[4:1]'} + ADC1_INIT_CODE_ATTEN0_CH5 : {show: y, blk : 2, word: 7, pos: 21, len : 4, start: 245, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch5, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[24:21]', bloc: 'B30[7:5],B31[0]'} + ADC1_INIT_CODE_ATTEN0_CH6 : {show: y, blk : 2, word: 7, pos: 25, len : 4, start: 249, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch6, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[28:25]', bloc: 'B31[4:1]'} + RESERVED_2_253 : {show: n, blk : 2, word: 7, pos: 29, len : 3, start: 253, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:29]', bloc: 'B31[7:5]'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espsecure/__init__.py b/espsecure/__init__.py index 3d805492e..c6b44f941 100755 --- a/espsecure/__init__.py +++ b/espsecure/__init__.py @@ -1713,7 +1713,7 @@ def main(custom_commandline=None): "--aes_xts", "-x", help="Decrypt data using AES-XTS as used on " - "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5 and ESP32-P4", + "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5, ESP32-C61 and ESP32-P4", action="store_true", ) p.add_argument( @@ -1753,7 +1753,7 @@ def main(custom_commandline=None): "--aes_xts", "-x", help="Encrypt data using AES-XTS as used on " - "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5 and ESP32-P4", + "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5, ESP32-C61 and ESP32-P4", action="store_true", ) p.add_argument( diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 77f780491..a54620200 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -23,6 +23,7 @@ ESP32C5BETA3ROM, ESP32C6BETAROM, ESP32C6ROM, + ESP32C61ROM, ESP32H2BETA1ROM, ESP32H2BETA2ROM, ESP32H2ROM, @@ -88,6 +89,7 @@ def select_image_class(f, chip): "esp32h2beta2": ESP32H2BETA2FirmwareImage, "esp32c2": ESP32C2FirmwareImage, "esp32c6": ESP32C6FirmwareImage, + "esp32c61": ESP32C61FirmwareImage, "esp32c5": ESP32C5FirmwareImage, "esp32c5beta3": ESP32C5BETA3FirmwareImage, "esp32h2": ESP32H2FirmwareImage, @@ -1132,6 +1134,15 @@ def set_mmu_page_size(self, size): ESP32C6ROM.BOOTLOADER_IMAGE = ESP32C6FirmwareImage +class ESP32C61FirmwareImage(ESP32C6FirmwareImage): + """ESP32C61 Firmware Image almost exactly the same as ESP32C6FirmwareImage""" + + ROM_LOADER = ESP32C61ROM + + +ESP32C61ROM.BOOTLOADER_IMAGE = ESP32C61FirmwareImage + + class ESP32C5FirmwareImage(ESP32C6FirmwareImage): """ESP32C5 Firmware Image almost exactly the same as ESP32C6FirmwareImage""" diff --git a/esptool/targets/__init__.py b/esptool/targets/__init__.py index 676daf285..30c08605d 100644 --- a/esptool/targets/__init__.py +++ b/esptool/targets/__init__.py @@ -4,6 +4,7 @@ from .esp32c5 import ESP32C5ROM from .esp32c5beta3 import ESP32C5BETA3ROM from .esp32c6 import ESP32C6ROM +from .esp32c61 import ESP32C61ROM from .esp32c6beta import ESP32C6BETAROM from .esp32h2 import ESP32H2ROM from .esp32h2beta1 import ESP32H2BETA1ROM @@ -27,6 +28,7 @@ "esp32h2beta2": ESP32H2BETA2ROM, "esp32c2": ESP32C2ROM, "esp32c6": ESP32C6ROM, + "esp32c61": ESP32C61ROM, "esp32c5": ESP32C5ROM, "esp32c5beta3": ESP32C5BETA3ROM, "esp32h2": ESP32H2ROM, diff --git a/esptool/targets/esp32c61.py b/esptool/targets/esp32c61.py new file mode 100644 index 000000000..96f8ff93e --- /dev/null +++ b/esptool/targets/esp32c61.py @@ -0,0 +1,84 @@ +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import struct + +from .esp32c6 import ESP32C6ROM + + +class ESP32C61ROM(ESP32C6ROM): + CHIP_NAME = "ESP32-C61" + IMAGE_CHIP_ID = 20 + + # Magic value for ESP32C61 + CHIP_DETECT_MAGIC_VALUE = [0x33F0206F] + + UART_DATE_REG_ADDR = 0x60000000 + 0x7C + + EFUSE_BASE = 0x600B4800 + EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044 + MAC_EFUSE_REG = EFUSE_BASE + 0x044 + + EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030 # BLOCK0 read base address + + EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY0_SHIFT = 0 + EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY1_SHIFT = 4 + EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY2_SHIFT = 8 + EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY3_SHIFT = 12 + EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY4_SHIFT = 16 + EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x34 + EFUSE_PURPOSE_KEY5_SHIFT = 20 + + EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE + EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20 + + EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x030 + EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 23 + + EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x034 + EFUSE_SECURE_BOOT_EN_MASK = 1 << 26 + + MEMORY_MAP = [ + [0x00000000, 0x00010000, "PADDING"], + [0x41800000, 0x42000000, "DROM"], + [0x40800000, 0x40860000, "DRAM"], + [0x40800000, 0x40860000, "BYTE_ACCESSIBLE"], + [0x4004AC00, 0x40050000, "DROM_MASK"], + [0x40000000, 0x4004AC00, "IROM_MASK"], + [0x41000000, 0x41800000, "IROM"], + [0x40800000, 0x40860000, "IRAM"], + [0x50000000, 0x50004000, "RTC_IRAM"], + [0x50000000, 0x50004000, "RTC_DRAM"], + [0x600FE000, 0x60100000, "MEM_INTERNAL2"], + ] + + def get_chip_description(self): + chip_name = { + 0: "ESP32-C61", + }.get(self.get_pkg_version(), "unknown ESP32-C61") + major_rev = self.get_major_chip_version() + minor_rev = self.get_minor_chip_version() + return f"{chip_name} (revision v{major_rev}.{minor_rev})" + + def get_chip_features(self): + return ["WiFi 6", "BT 5"] + + def read_mac(self, mac_type="BASE_MAC"): + """Read MAC from EFUSE region""" + mac0 = self.read_reg(self.MAC_EFUSE_REG) + mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC + base_mac = struct.pack(">II", mac1, mac0)[2:] + # BASE MAC: 60:55:f9:f7:2c:a2 + macs = { + "BASE_MAC": tuple(base_mac), + } + return macs.get(mac_type, None) + + +# TODO: IDF-9241, stub flasher support diff --git a/flasher_stub/compare_stubs.py b/flasher_stub/compare_stubs.py index ccaab5638..74843f0fb 100755 --- a/flasher_stub/compare_stubs.py +++ b/flasher_stub/compare_stubs.py @@ -69,7 +69,8 @@ def diff(path_to_new, path_to_old): for chip in esptool.CHIP_LIST: print("Comparing {} stub: ".format(chip), end="") # TODO: [ESP32C5] ESPTOOL-825 remove when supported stub flasher - if chip == "esp32c5": + # TODO: [ESP32C61] IDF-9241 remove when supported stub flasher + if chip in ["esp32c5", "esp32c61"]: print(f"{chip} has not supported stub yet, skipping...") continue diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 250880c8e..2c3dda7a9 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -215,6 +215,8 @@ def test_check_error(self): self.espefuse_py("check_error --recovery") +# TODO: [ESP32C61] IDF-9238 +@pytest.mark.skipif(arg_chip == "esp32c61", reason="Not supported yet") class TestReadProtectionCommands(EfuseTestCase): def test_read_protect_efuse(self): self.espefuse_py("read_protect_efuse -h") @@ -348,8 +350,8 @@ def test_burn_and_read_protect_efuse(self): ) -# TODO: [ESP32C5] IDF-8629 -@pytest.mark.skipif(arg_chip == "esp32c5", reason="Not supported yet") +# TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 +@pytest.mark.skipif(arg_chip in ["esp32c5", "esp32c61"], reason="Not supported yet") class TestWriteProtectionCommands(EfuseTestCase): def test_write_protect_efuse(self): self.espefuse_py("write_protect_efuse -h") @@ -456,7 +458,7 @@ def test_burn_custom_mac_with_34_coding_scheme(self): @pytest.mark.skipif( - # TODO: [ESP32C5] IDF-8629 + # TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 arg_chip in [ "esp32c2", @@ -466,6 +468,7 @@ def test_burn_custom_mac_with_34_coding_scheme(self): "esp32h2", "esp32p4", "esp32c5", + "esp32c61", ], reason=f"TODO: add support set_flash_voltage for {arg_chip}", ) @@ -677,8 +680,14 @@ def test_burn_mac_custom_efuse(self): self.espefuse_py("burn_efuse CUSTOM_MAC AA:CD:EF:01:02:03") self.espefuse_py("get_custom_mac", check_msg=f"aa:cd:ef:01:02:03 {crc_msg}") + # TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 @pytest.mark.skipif( - arg_chip in ["esp32p4", "esp32c5"], # TODO: [ESP32C5] IDF-8629 + arg_chip + in [ + "esp32p4", + "esp32c5", + "esp32c61", + ], reason="No such eFuses, will be defined later", ) def test_burn_efuse(self): @@ -1789,8 +1798,8 @@ def test_2_secure_boot_v1(self): ) -# TODO: [ESP32C5] IDF-8629 -@pytest.mark.skipif(arg_chip == "esp32c5", reason="Not supported yet") +# TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 +@pytest.mark.skipif(arg_chip in ["esp32c5", "esp32c61"], reason="Not supported yet") class TestExecuteScriptsCommands(EfuseTestCase): @classmethod def setup_class(self): From 2dc7d1f16ffaa63d456ccbdd522dd057bd21c359 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Wed, 13 Mar 2024 22:05:03 +0200 Subject: [PATCH 159/209] feat(espefuse): Updates efuses for C5 and C61 --- .gitlab-ci.yml | 1 + espefuse/efuse/esp32c5/fields.py | 11 +- espefuse/efuse/esp32c5/operations.py | 31 +--- espefuse/efuse/esp32c5beta3/fields.py | 11 +- espefuse/efuse/esp32c5beta3/operations.py | 4 +- .../esp32c61/emulate_efuse_controller.py | 6 +- espefuse/efuse/esp32c61/fields.py | 26 ++-- espefuse/efuse/esp32c61/mem_definition.py | 11 -- espefuse/efuse/esp32c61/operations.py | 92 ++++++++--- espefuse/efuse_defs/esp32c5.yaml | 143 +++++++----------- espefuse/efuse_defs/esp32c5beta3.yaml | 85 +++++++++++ espefuse/efuse_defs/esp32c61.yaml | 132 +++++++--------- .../esp32xx/execute_efuse_script.py | 4 +- .../esp32xx/execute_efuse_script2.py | 2 +- test/test_espefuse.py | 84 +++++----- 15 files changed, 339 insertions(+), 304 deletions(-) create mode 100644 espefuse/efuse_defs/esp32c5beta3.yaml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0d9162ad5..967a157ee 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -97,6 +97,7 @@ host_tests: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32s3beta2 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2beta1 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c5 + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c5beta3 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c6 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c61 - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2 diff --git a/espefuse/efuse/esp32c5/fields.py b/espefuse/efuse/esp32c5/fields.py index ecfefd277..c3d44649d 100644 --- a/espefuse/efuse/esp32c5/fields.py +++ b/espefuse/efuse/esp32c5/fields.py @@ -95,11 +95,11 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLK_VERSION_MINOR"].get() == 1: - self.efuses += [ - EfuseField.convert(self, efuse) - for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES - ] + # if self["BLK_VERSION_MINOR"].get() == 1: + # self.efuses += [ + # EfuseField.convert(self, efuse) + # for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + # ] self.efuses += [ EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] @@ -398,6 +398,7 @@ def print_field(e, new_value): class EfuseKeyPurposeField(EfuseField): KEY_PURPOSES = [ ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) + ("ECDSA_KEY", 1, None, "Reverse", "need_rd_protect"), # ECDSA key ("RESERVED", 1, None, None, "no_need_rd_protect"), # Reserved ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) ("HMAC_DOWN_ALL", 5, None, None, "need_rd_protect"), # HMAC Downstream mode diff --git a/espefuse/efuse/esp32c5/operations.py b/espefuse/efuse/esp32c5/operations.py index c2011ea9b..76ac62ef5 100644 --- a/espefuse/efuse/esp32c5/operations.py +++ b/espefuse/efuse/esp32c5/operations.py @@ -65,7 +65,7 @@ def add_commands(subparsers, efuses): ) burn_key.add_argument( "keyfile", - help="File containing 256 bits of binary key data", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", action="append", type=argparse.FileType("rb"), ) @@ -86,7 +86,7 @@ def add_commands(subparsers, efuses): ) burn_key.add_argument( "keyfile", - help="File containing 256 bits of binary key data", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", nargs="?", action="append", metavar="KEYFILE", @@ -192,32 +192,7 @@ def set_flash_voltage(esp, efuses, args): def adc_info(esp, efuses, args): - print("") - # fmt: off - if efuses["BLK_VERSION_MINOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) - - print("") - print("ADC1 Calibration data stored in efuse BLOCK2:") - print(f"OCODE: {efuses['OCODE'].get()}") - print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") - print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") - print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") - print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") - print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") - print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") - print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") - print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") - print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") - print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") - print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") - print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") - print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") - print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") - print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") - else: - print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) - # fmt: on + print("not supported yet") def burn_key(esp, efuses, args, digest=None): diff --git a/espefuse/efuse/esp32c5beta3/fields.py b/espefuse/efuse/esp32c5beta3/fields.py index 416eb5807..fc345686e 100644 --- a/espefuse/efuse/esp32c5beta3/fields.py +++ b/espefuse/efuse/esp32c5beta3/fields.py @@ -95,11 +95,11 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLK_VERSION_MINOR"].get() == 1: - self.efuses += [ - EfuseField.convert(self, efuse) - for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES - ] + # if self["BLK_VERSION_MINOR"].get() == 1: + # self.efuses += [ + # EfuseField.convert(self, efuse) + # for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + # ] self.efuses += [ EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] @@ -398,6 +398,7 @@ def print_field(e, new_value): class EfuseKeyPurposeField(EfuseField): KEY_PURPOSES = [ ("USER", 0, None, None, "no_need_rd_protect"), # User purposes (software-only use) + ("ECDSA_KEY", 1, None, "Reverse", "need_rd_protect"), # ECDSA key ("RESERVED", 1, None, None, "no_need_rd_protect"), # Reserved ("XTS_AES_128_KEY", 4, None, "Reverse", "need_rd_protect"), # XTS_AES_128_KEY (flash/PSRAM encryption) ("HMAC_DOWN_ALL", 5, None, None, "need_rd_protect"), # HMAC Downstream mode diff --git a/espefuse/efuse/esp32c5beta3/operations.py b/espefuse/efuse/esp32c5beta3/operations.py index 8ad39340f..2ee4c24b6 100644 --- a/espefuse/efuse/esp32c5beta3/operations.py +++ b/espefuse/efuse/esp32c5beta3/operations.py @@ -65,7 +65,7 @@ def add_commands(subparsers, efuses): ) burn_key.add_argument( "keyfile", - help="File containing 256 bits of binary key data", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", action="append", type=argparse.FileType("rb"), ) @@ -86,7 +86,7 @@ def add_commands(subparsers, efuses): ) burn_key.add_argument( "keyfile", - help="File containing 256 bits of binary key data", + help="File containing 256 bits of binary key data. For the ECDSA_KEY purpose use PEM file.", nargs="?", action="append", metavar="KEYFILE", diff --git a/espefuse/efuse/esp32c61/emulate_efuse_controller.py b/espefuse/efuse/esp32c61/emulate_efuse_controller.py index ab513aca8..22e4da277 100644 --- a/espefuse/efuse/esp32c61/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c61/emulate_efuse_controller.py @@ -22,7 +22,7 @@ def __init__(self, efuse_file=None, debug=False): self.Fields = EfuseDefineFields() self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) """ esptool method start >>""" @@ -53,10 +53,10 @@ def handle_writing_event(self, addr, value): self.clean_blocks_wr_regs() self.check_rd_protection_area() self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) elif value == self.REGS.EFUSE_READ_CMD: self.write_reg(addr, 0) - self.write_reg(self.REGS.EFUSE_STATUS_REG, 1) + self.write_reg(self.REGS.EFUSE_CMD_REG, 0) self.save_to_file() def get_bitlen_of_block(self, blk, wr=False): diff --git a/espefuse/efuse/esp32c61/fields.py b/espefuse/efuse/esp32c61/fields.py index 176041345..db00fb0eb 100644 --- a/espefuse/efuse/esp32c61/fields.py +++ b/espefuse/efuse/esp32c61/fields.py @@ -6,6 +6,7 @@ import binascii import struct +import sys import time from bitstring import BitArray @@ -94,11 +95,11 @@ def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES ] else: - if self["BLK_VERSION_MINOR"].get() == 1: - self.efuses += [ - EfuseField.convert(self, efuse) - for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES - ] + # if self["BLK_VERSION_MINOR"].get() == 1: + # self.efuses += [ + # EfuseField.convert(self, efuse) + # for efuse in self.Fields.BLOCK2_CALIBRATION_EFUSES + # ] self.efuses += [ EfuseField.convert(self, efuse) for efuse in self.Fields.CALC ] @@ -160,9 +161,13 @@ def clear_pgm_registers(self): def wait_efuse_idle(self): deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT while time.time() < deadline: - # if self.read_reg(self.REGS.EFUSE_CMD_REG) == 0: - if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1: - return + cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0: + # Due to a hardware error, we have to read READ_CMD again + # to make sure the efuse clock is normal. + # For PGM_CMD it is not necessary. + return raise esptool.FatalError( "Timed out waiting for Efuse controller command to complete" ) @@ -202,7 +207,7 @@ def efuse_read(self): ) print("DIS_DOWNLOAD_MODE is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise print("Established a connection with the chip") @@ -216,7 +221,7 @@ def efuse_read(self): ) print("ENABLE_SECURITY_DOWNLOAD is enabled") print("Successful") - exit(0) # finish without errors + sys.exit(0) # finish without errors raise def set_efuse_timing(self): @@ -404,6 +409,7 @@ class EfuseKeyPurposeField(EfuseField): ("SECURE_BOOT_DIGEST0", 9, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST0 (Secure Boot key digest) ("SECURE_BOOT_DIGEST1", 10, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST1 (Secure Boot key digest) ("SECURE_BOOT_DIGEST2", 11, "DIGEST", None, "no_need_rd_protect"), # SECURE_BOOT_DIGEST2 (Secure Boot key digest) + ("XTS_AES_256_KEY", -1, "VIRTUAL", None, "no_need_rd_protect"), # Virtual purpose splits to XTS_AES_256_KEY_1 and XTS_AES_256_KEY_2 ] # fmt: on KEY_PURPOSES_NAME = [name[0] for name in KEY_PURPOSES] diff --git a/espefuse/efuse/esp32c61/mem_definition.py b/espefuse/efuse/esp32c61/mem_definition.py index 0b8f7048d..be9279e3a 100644 --- a/espefuse/efuse/esp32c61/mem_definition.py +++ b/espefuse/efuse/esp32c61/mem_definition.py @@ -12,7 +12,6 @@ EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase, - Field, ) @@ -152,16 +151,6 @@ def __init__(self) -> None: self.BLOCK2_CALIBRATION_EFUSES.append(efuse) self.ALL_EFUSES[i] = None - f = Field() - f.name = "MAC_EUI64" - f.block = 1 - f.bit_len = 64 - f.type = f"bytes:{f.bit_len // 8}" - f.category = "MAC" - f.class_type = "mac" - f.description = "calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:MAC_EXT[1]:MAC[3]:MAC[4]:MAC[5]" - self.CALC.append(f) - for efuse in self.ALL_EFUSES: if efuse is not None: self.EFUSES.append(efuse) diff --git a/espefuse/efuse/esp32c61/operations.py b/espefuse/efuse/esp32c61/operations.py index 41892679d..b678c2ac8 100644 --- a/espefuse/efuse/esp32c61/operations.py +++ b/espefuse/efuse/esp32c61/operations.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import argparse +import io import os # noqa: F401. It is used in IDF scripts import traceback @@ -192,32 +193,68 @@ def set_flash_voltage(esp, efuses, args): def adc_info(esp, efuses, args): - print("") - # fmt: off - if efuses["BLK_VERSION_MINOR"].get() == 1: - print("Temperature Sensor Calibration = {}C".format(efuses["TEMP_CALIB"].get())) + print("not supported yet") - print("") - print("ADC1 Calibration data stored in efuse BLOCK2:") - print(f"OCODE: {efuses['OCODE'].get()}") - print(f"INIT_CODE_ATTEN0: {efuses['ADC1_INIT_CODE_ATTEN0'].get()}") - print(f"INIT_CODE_ATTEN1: {efuses['ADC1_INIT_CODE_ATTEN1'].get()}") - print(f"INIT_CODE_ATTEN2: {efuses['ADC1_INIT_CODE_ATTEN2'].get()}") - print(f"INIT_CODE_ATTEN3: {efuses['ADC1_INIT_CODE_ATTEN3'].get()}") - print(f"CAL_VOL_ATTEN0: {efuses['ADC1_CAL_VOL_ATTEN0'].get()}") - print(f"CAL_VOL_ATTEN1: {efuses['ADC1_CAL_VOL_ATTEN1'].get()}") - print(f"CAL_VOL_ATTEN2: {efuses['ADC1_CAL_VOL_ATTEN2'].get()}") - print(f"CAL_VOL_ATTEN3: {efuses['ADC1_CAL_VOL_ATTEN3'].get()}") - print(f"INIT_CODE_ATTEN0_CH0: {efuses['ADC1_INIT_CODE_ATTEN0_CH0'].get()}") - print(f"INIT_CODE_ATTEN0_CH1: {efuses['ADC1_INIT_CODE_ATTEN0_CH1'].get()}") - print(f"INIT_CODE_ATTEN0_CH2: {efuses['ADC1_INIT_CODE_ATTEN0_CH2'].get()}") - print(f"INIT_CODE_ATTEN0_CH3: {efuses['ADC1_INIT_CODE_ATTEN0_CH3'].get()}") - print(f"INIT_CODE_ATTEN0_CH4: {efuses['ADC1_INIT_CODE_ATTEN0_CH4'].get()}") - print(f"INIT_CODE_ATTEN0_CH5: {efuses['ADC1_INIT_CODE_ATTEN0_CH5'].get()}") - print(f"INIT_CODE_ATTEN0_CH6: {efuses['ADC1_INIT_CODE_ATTEN0_CH6'].get()}") - else: - print("BLK_VERSION_MINOR = {}".format(efuses["BLK_VERSION_MINOR"].get_meaning())) - # fmt: on + +def key_block_is_unused(block, key_purpose_block): + if not block.is_readable() or not block.is_writeable(): + return False + + if key_purpose_block.get() != "USER" or not key_purpose_block.is_writeable(): + return False + + if not block.get_bitstring().all(False): + return False + + return True + + +def get_next_key_block(efuses, current_key_block, block_name_list): + key_blocks = [b for b in efuses.blocks if b.key_purpose_name] + start = key_blocks.index(current_key_block) + + # Sort key blocks so that we pick the next free block (and loop around if necessary) + key_blocks = key_blocks[start:] + key_blocks[0:start] + + # Exclude any other blocks that will be be burned + key_blocks = [b for b in key_blocks if b.name not in block_name_list] + + for block in key_blocks: + key_purpose_block = efuses[block.key_purpose_name] + if key_block_is_unused(block, key_purpose_block): + return block + + return None + + +def split_512_bit_key(efuses, block_name_list, datafile_list, keypurpose_list): + i = keypurpose_list.index("XTS_AES_256_KEY") + block_name = block_name_list[i] + + block_num = efuses.get_index_block_by_name(block_name) + block = efuses.blocks[block_num] + + data = datafile_list[i].read() + if len(data) != 64: + raise esptool.FatalError( + "Incorrect key file size %d, XTS_AES_256_KEY should be 64 bytes" % len(data) + ) + + key_block_2 = get_next_key_block(efuses, block, block_name_list) + if not key_block_2: + raise esptool.FatalError("XTS_AES_256_KEY requires two free keyblocks") + + keypurpose_list.append("XTS_AES_256_KEY_1") + datafile_list.append(io.BytesIO(data[:32])) + block_name_list.append(block_name) + + keypurpose_list.append("XTS_AES_256_KEY_2") + datafile_list.append(io.BytesIO(data[32:])) + block_name_list.append(key_block_2.name) + + keypurpose_list.pop(i) + datafile_list.pop(i) + block_name_list.pop(i) def burn_key(esp, efuses, args, digest=None): @@ -235,6 +272,11 @@ def burn_key(esp, efuses, args, digest=None): 0 : len([name for name in args.keypurpose if name is not None]) : ] + if "XTS_AES_256_KEY" in keypurpose_list: + # XTS_AES_256_KEY is not an actual HW key purpose, needs to be split into + # XTS_AES_256_KEY_1 and XTS_AES_256_KEY_2 + split_512_bit_key(efuses, block_name_list, datafile_list, keypurpose_list) + util.check_duplicate_name_in_list(block_name_list) if len(block_name_list) != len(datafile_list) or len(block_name_list) != len( keypurpose_list diff --git a/espefuse/efuse_defs/esp32c5.yaml b/espefuse/efuse_defs/esp32c5.yaml index db8be540b..46a9fe7da 100644 --- a/espefuse/efuse_defs/esp32c5.yaml +++ b/espefuse/efuse_defs/esp32c5.yaml @@ -1,28 +1,31 @@ -VER_NO: df46b69f0ed3913114ba53d3a0b2b843 +VER_NO: 64acd55d57b7452dbb6838b7237c795b EFUSES: - WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS0_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} - SWAP_UART_SDIO_EN : {show: y, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} - DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} - DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} - DIS_DOWNLOAD_ICACHE : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} - DIS_USB_SERIAL_JTAG : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} - DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} - SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} - DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : DIS_CAN, dict : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} - JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} - SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} - DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} - DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + RESERVE_0_39 : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + RESERVE_0_42 : {show: n, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: n, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} - USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} - VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} - RPT4_RESERVED0_2 : {show: n, blk : 0, word: 1, pos: 27, len : 2, start : 59, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'} - RPT4_RESERVED0_1 : {show: n, blk : 0, word: 1, pos: 29, len : 1, start : 61, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'} - RPT4_RESERVED0_0 : {show: n, blk : 0, word: 1, pos: 30, len : 2, start : 62, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'} - RPT4_RESERVED1_0 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'} - WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + RESERVE_0_59 : {show: n, blk : 0, word: 1, pos: 27, len : 5, start : 59, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:27]', bloc: 'B7[7:3]'} + KM_DISABLE_DEPLOY_MODE : {show: y, blk : 0, word: 2, pos : 0, len : 4, start : 64, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled.\\', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[3:0]', bloc: 'B8[3:0]'} + KM_RND_SWITCH_CYCLE : {show: y, blk : 0, word: 2, pos : 4, len : 2, start : 68, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[5:4]', bloc: 'B8[5:4]'} + KM_DEPLOY_ONLY_ONCE : {show: y, blk : 0, word: 2, pos : 6, len : 4, start : 70, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[9:6]', bloc: 'B8[7:6],B9[1:0]'} + FORCE_USE_KEY_MANAGER_KEY : {show: y, blk : 0, word: 2, pos: 10, len : 4, start : 74, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[13:10]', bloc: 'B9[5:2]'} + FORCE_DISABLE_SW_INIT_KEY : {show: y, blk : 0, word: 2, pos: 14, len : 1, start : 78, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable software written init key; and force use efuse_init_key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[14]', bloc: 'B9[6]'} + RESERVE_0_79 : {show: n, blk : 0, word: 2, pos: 15, len : 1, start : 79, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15]', bloc: 'B9[7]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} @@ -33,72 +36,42 @@ EFUSES: KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} - SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : DPA_SEC_LEVEL, dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} - CRYPT_DPA_ENABLE : {show: y, blk : 0, word: 3, pos: 18, len : 1, start: 114, type : bool, wr_dis : 1, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'} - RPT4_RESERVED2_1 : {show: n, blk : 0, word: 3, pos: 19, len : 1, start: 115, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'} - SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} - SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} - RPT4_RESERVED2_0 : {show: n, blk : 0, word: 3, pos: 22, len : 6, start: 118, type : 'uint:6', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} + RESERVE_0_114 : {show: n, blk : 0, word: 3, pos: 18, len : 2, start: 114, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19:18]', bloc: 'B14[3:2]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RESERVE_0_118 : {show: n, blk : 0, word: 3, pos: 22, len : 5, start: 118, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26:22]', bloc: 'B14[7:6],B15[2:0]'} + KM_XTS_KEY_LENGTH_256 : {show: y, blk : 0, word: 3, pos: 27, len : 1, start: 123, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bitto configure flash encryption use xts-128 key. else use xts-256 key, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27]', bloc: 'B15[3]'} FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} - DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} - DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} - DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} - RPT4_RESERVED3_5 : {show: n, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} - ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + LOCK_KM_KEY : {show: y, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} - RPT4_RESERVED3_4 : {show: n, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} - RPT4_RESERVED3_3 : {show: n, blk : 0, word: 4, pos : 9, len : 1, start: 137, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[9]', bloc: 'B17[1]'} - RPT4_RESERVED3_2 : {show: n, blk : 0, word: 4, pos: 10, len : 2, start: 138, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[11:10]', bloc: 'B17[3:2]'} - RPT4_RESERVED3_1 : {show: n, blk : 0, word: 4, pos: 12, len : 1, start: 140, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[12]', bloc: 'B17[4]'} - FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos: 13, len : 1, start: 141, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[13]', bloc: 'B17[5]'} - SECURE_VERSION : {show: y, blk : 0, word: 4, pos: 14, len : 16, start: 142, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[29:14]', bloc: 'B17[7:6],B18,B19[5:0]'} - SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 30, len : 1, start: 158, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[30]', bloc: 'B19[6]'} - RPT4_RESERVED3_0 : {show: n, blk : 0, word: 4, pos: 31, len : 1, start: 159, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31]', bloc: 'B19[7]'} - DISABLE_WAFER_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 0, len : 1, start: 160, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[0]', bloc: 'B20[0]'} - DISABLE_BLK_VERSION_MAJOR : {show: y, blk : 0, word: 5, pos : 1, len : 1, start: 161, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1]', bloc: 'B20[1]'} - RESERVED_0_162 : {show: n, blk : 0, word: 5, pos : 2, len : 22, start: 162, type : 'uint:22', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[23:2]', bloc: 'B20[7:2],B21,B22'} - RPT4_RESERVED4_0 : {show: n, blk : 0, word: 5, pos: 24, len : 8, start: 184, type : 'uint:8', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:24]', bloc: B23} - MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} - MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:16]', bloc: 'B6,B7'} - ACTIVE_HP_DBIAS : {show: y, blk : 1, word: 2, pos : 0, len : 5, start : 64, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the active hp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[4:0]', bloc: 'B8[4:0]'} - ACTIVE_LP_DBIAS : {show: y, blk : 1, word: 2, pos : 5, len : 5, start : 69, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the active lp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[9:5]', bloc: 'B8[7:5],B9[1:0]'} - LSLP_HP_DBG : {show: y, blk : 1, word: 2, pos: 10, len : 2, start : 74, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the lslp hp dbg, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[11:10]', bloc: 'B9[3:2]'} - LSLP_HP_DBIAS : {show: y, blk : 1, word: 2, pos: 12, len : 4, start : 76, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the lslp hp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[15:12]', bloc: 'B9[7:4]'} - DSLP_LP_DBG : {show: y, blk : 1, word: 2, pos: 16, len : 3, start : 80, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the dslp lp dbg, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[18:16]', bloc: 'B10[2:0]'} - DSLP_LP_DBIAS : {show: y, blk : 1, word: 2, pos: 19, len : 4, start : 83, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the dslp lp dbias, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[22:19]', bloc: 'B10[6:3]'} - DBIAS_VOL_GAP : {show: y, blk : 1, word: 2, pos: 23, len : 5, start : 87, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the hp and lp dbias vol gap, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[27:23]', bloc: 'B10[7],B11[3:0]'} - SPI_PAD_CONF_1 : {show: n, blk : 1, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:28]', bloc: 'B11[7:4]'} - SPI_PAD_CONF_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} - WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 4, start: 114, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[21:18]', bloc: 'B14[5:2]'} - WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 22, len : 2, start: 118, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:22]', bloc: 'B14[7:6]'} - PKG_VERSION : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} - BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'} - BLK_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'} - FLASH_CAP : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} - FLASH_TEMP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'} - FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 5, len : 3, start: 133, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[7:5]', bloc: 'B16[7:5]'} - RESERVED_1_136 : {show: n, blk : 1, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:8]', bloc: 'B17,B18,B19'} - SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SPI_SYS_5_REG, bloc: 'B20,B21,B22,B23'} - OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} - TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 0, len : 9, start: 128, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[8:0]', bloc: 'B16,B17[0]'} - OCODE : {show: y, blk : 2, word: 4, pos : 9, len : 8, start: 137, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[16:9]', bloc: 'B17[7:1],B18[0]'} - ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 17, len : 10, start: 145, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[26:17]', bloc: 'B18[7:1],B19[2:0]'} - ADC1_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 27, len : 10, start: 155, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:27]', bloc: 'B19[7:3],B20[4:0]'} - ADC1_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 5, len : 10, start: 165, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[14:5]', bloc: 'B20[7:5],B21[6:0]'} - ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 5, pos: 15, len : 10, start: 175, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[24:15]', bloc: 'B21[7],B22,B23[0]'} - ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 5, pos: 25, len : 10, start: 185, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:25]', bloc: 'B23[7:1],B24[2:0]'} - ADC1_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 6, pos : 3, len : 10, start: 195, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[12:3]', bloc: 'B24[7:3],B25[4:0]'} - ADC1_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 6, pos: 13, len : 10, start: 205, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[22:13]', bloc: 'B25[7:5],B26[6:0]'} - ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 6, pos: 23, len : 10, start: 215, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:23]', bloc: 'B26[7],B27,B28[0]'} - ADC1_INIT_CODE_ATTEN0_CH0 : {show: y, blk : 2, word: 7, pos : 1, len : 4, start: 225, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch0, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[4:1]', bloc: 'B28[4:1]'} - ADC1_INIT_CODE_ATTEN0_CH1 : {show: y, blk : 2, word: 7, pos : 5, len : 4, start: 229, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch1, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[8:5]', bloc: 'B28[7:5],B29[0]'} - ADC1_INIT_CODE_ATTEN0_CH2 : {show: y, blk : 2, word: 7, pos : 9, len : 4, start: 233, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[12:9]', bloc: 'B29[4:1]'} - ADC1_INIT_CODE_ATTEN0_CH3 : {show: y, blk : 2, word: 7, pos: 13, len : 4, start: 237, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:13]', bloc: 'B29[7:5],B30[0]'} - ADC1_INIT_CODE_ATTEN0_CH4 : {show: y, blk : 2, word: 7, pos: 17, len : 4, start: 241, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch4, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[20:17]', bloc: 'B30[4:1]'} - ADC1_INIT_CODE_ATTEN0_CH5 : {show: y, blk : 2, word: 7, pos: 21, len : 4, start: 245, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch5, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[24:21]', bloc: 'B30[7:5],B31[0]'} - ADC1_INIT_CODE_ATTEN0_CH6 : {show: y, blk : 2, word: 7, pos: 25, len : 4, start: 249, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch6, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[28:25]', bloc: 'B31[4:1]'} - RESERVED_2_253 : {show: n, blk : 2, word: 7, pos: 29, len : 3, start: 253, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:29]', bloc: 'B31[7:5]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos : 9, len : 16, start: 137, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[24:9]', bloc: 'B17[7:1],B18,B19[0]'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 25, len : 1, start: 153, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'} + HYS_EN_PAD : {show: y, blk : 0, word: 4, pos: 26, len : 1, start: 154, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[26]', bloc: 'B19[2]'} + XTS_DPA_PSEUDO_LEVEL : {show: y, blk : 0, word: 4, pos: 27, len : 2, start: 155, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[28:27]', bloc: 'B19[4:3]'} + XTS_DPA_CLK_ENABLE : {show: y, blk : 0, word: 4, pos: 29, len : 1, start: 157, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable.\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[29]', bloc: 'B19[5]'} + RESERVE_0_158 : {show: n, blk : 0, word: 4, pos: 30, len : 2, start: 158, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:30]', bloc: 'B19[7:6]'} + HUK_GEN_STATE : {show: y, blk : 0, word: 5, pos : 0, len : 9, start: 160, type : 'uint:9', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid.\\, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[8:0]', bloc: 'B20,B21[0]'} + XTAL_48M_SEL : {show: y, blk : 0, word: 5, pos : 9, len : 3, start: 169, type : 'uint:3', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[11:9]', bloc: 'B21[3:1]'} + XTAL_48M_SEL_MODE : {show: y, blk : 0, word: 5, pos: 12, len : 1, start: 172, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[12]', bloc: 'B21[4]'} + ECDSA_DISABLE_P192 : {show: y, blk : 0, word: 5, pos: 13, len : 1, start: 173, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13]', bloc: 'B21[5]'} + ECC_FORCE_CONST_TIME : {show: y, blk : 0, word: 5, pos: 14, len : 1, start: 174, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[14]', bloc: 'B21[6]'} + RESERVE_0_175 : {show: n, blk : 0, word: 5, pos: 15, len : 17, start: 175, type : 'uint:17', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:15]', bloc: 'B21[7],B22,B23'} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS1_REG[31:16]', bloc: 'B6,B7'} + MAC_RESERVED_0 : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS2_REG[13:0]', bloc: 'B8,B9[5:0]'} + MAC_RESERVED_1 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + SYS_DATA_PART0_0 : {show: n, blk : 1, word: 3, pos: 18, len : 14, start: 114, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: 'EFUSE_RD_MAC_SYS3_REG[31:18]', bloc: 'B14[7:2],B15'} + SYS_DATA_PART0_1 : {show: n, blk : 1, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS4_REG, bloc: 'B16,B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the second 32-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS5_REG, bloc: 'B20,B21,B22,B23'} + BLOCK_SYS_DATA1 : {show: y, blk : 2, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: System data part 1 (reserved), rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} diff --git a/espefuse/efuse_defs/esp32c5beta3.yaml b/espefuse/efuse_defs/esp32c5beta3.yaml new file mode 100644 index 000000000..46a9fe7da --- /dev/null +++ b/espefuse/efuse_defs/esp32c5beta3.yaml @@ -0,0 +1,85 @@ +VER_NO: 64acd55d57b7452dbb6838b7237c795b +EFUSES: + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS0_REG, bloc: 'B0,B1,B2,B3'} + RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} + RESERVE_0_39 : {show: n, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + RESERVE_0_42 : {show: n, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + DIS_USB_SERIAL_JTAG : {show: n, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_TWAI : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 15, len : 1, start : 47, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[15]', bloc: 'B5[7]'} + SOFT_DIS_JTAG : {show: y, blk : 0, word: 1, pos: 16, len : 3, start : 48, type : 'uint:3', wr_dis : 31, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:16]', bloc: 'B6[2:0]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 23, len : 2, start : 55, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 25, len : 1, start : 57, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + RESERVE_0_59 : {show: n, blk : 0, word: 1, pos: 27, len : 5, start : 59, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:27]', bloc: 'B7[7:3]'} + KM_DISABLE_DEPLOY_MODE : {show: y, blk : 0, word: 2, pos : 0, len : 4, start : 64, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled.\\', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[3:0]', bloc: 'B8[3:0]'} + KM_RND_SWITCH_CYCLE : {show: y, blk : 0, word: 2, pos : 4, len : 2, start : 68, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[5:4]', bloc: 'B8[5:4]'} + KM_DEPLOY_ONLY_ONCE : {show: y, blk : 0, word: 2, pos : 6, len : 4, start : 70, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[9:6]', bloc: 'B8[7:6],B9[1:0]'} + FORCE_USE_KEY_MANAGER_KEY : {show: y, blk : 0, word: 2, pos: 10, len : 4, start : 74, type : 'uint:4', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[13:10]', bloc: 'B9[5:2]'} + FORCE_DISABLE_SW_INIT_KEY : {show: y, blk : 0, word: 2, pos: 14, len : 1, start : 78, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bit to disable software written init key; and force use efuse_init_key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[14]', bloc: 'B9[6]'} + RESERVE_0_79 : {show: n, blk : 0, word: 2, pos: 15, len : 1, start : 79, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15]', bloc: 'B9[7]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 2, pos: 16, len : 2, start : 80, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 2, pos: 18, len : 3, start : 82, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 2, pos: 21, len : 1, start : 85, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[21]', bloc: 'B10[5]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 2, pos: 22, len : 1, start : 86, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[22]', bloc: 'B10[6]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23]', bloc: 'B10[7]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27:24]', bloc: 'B11[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + KEY_PURPOSE_2 : {show: y, blk : 0, word: 3, pos : 0, len : 4, start : 96, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3:0]', bloc: 'B12[3:0]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 3, pos : 4, len : 4, start: 100, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7:4]', bloc: 'B12[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 3, pos : 8, len : 4, start: 104, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 3, pos: 12, len : 4, start: 108, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 3, pos: 16, len : 2, start: 112, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'} + RESERVE_0_114 : {show: n, blk : 0, word: 3, pos: 18, len : 2, start: 114, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19:18]', bloc: 'B14[3:2]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 3, pos: 20, len : 1, start: 116, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 3, pos: 21, len : 1, start: 117, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'} + RESERVE_0_118 : {show: n, blk : 0, word: 3, pos: 22, len : 5, start: 118, type : 'uint:5', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26:22]', bloc: 'B14[7:6],B15[2:0]'} + KM_XTS_KEY_LENGTH_256 : {show: y, blk : 0, word: 3, pos: 27, len : 1, start: 123, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set this bitto configure flash encryption use xts-128 key. else use xts-256 key, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27]', bloc: 'B15[3]'} + FLASH_TPUW : {show: y, blk : 0, word: 3, pos: 28, len : 4, start: 124, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 4, pos : 0, len : 1, start: 128, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 4, pos : 1, len : 1, start: 129, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 4, pos : 2, len : 1, start: 130, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[2]', bloc: 'B16[2]'} + LOCK_KM_KEY : {show: y, blk : 0, word: 4, pos : 3, len : 1, start: 131, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[3]', bloc: 'B16[3]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 4, pos : 4, len : 1, start: 132, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[4]', bloc: 'B16[4]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 4, pos : 5, len : 1, start: 133, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[5]', bloc: 'B16[5]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 4, pos : 6, len : 2, start: 134, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[7:6]', bloc: 'B16[7:6]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 4, pos : 8, len : 1, start: 136, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[8]', bloc: 'B17[0]'} + SECURE_VERSION : {show: y, blk : 0, word: 4, pos : 9, len : 16, start: 137, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[24:9]', bloc: 'B17[7:1],B18,B19[0]'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 4, pos: 25, len : 1, start: 153, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[25]', bloc: 'B19[1]'} + HYS_EN_PAD : {show: y, blk : 0, word: 4, pos: 26, len : 1, start: 154, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[26]', bloc: 'B19[2]'} + XTS_DPA_PSEUDO_LEVEL : {show: y, blk : 0, word: 4, pos: 27, len : 2, start: 155, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[28:27]', bloc: 'B19[4:3]'} + XTS_DPA_CLK_ENABLE : {show: y, blk : 0, word: 4, pos: 29, len : 1, start: 157, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable.\\', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[29]', bloc: 'B19[5]'} + RESERVE_0_158 : {show: n, blk : 0, word: 4, pos: 30, len : 2, start: 158, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:30]', bloc: 'B19[7:6]'} + HUK_GEN_STATE : {show: y, blk : 0, word: 5, pos : 0, len : 9, start: 160, type : 'uint:9', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid.\\, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[8:0]', bloc: 'B20,B21[0]'} + XTAL_48M_SEL : {show: y, blk : 0, word: 5, pos : 9, len : 3, start: 169, type : 'uint:3', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[11:9]', bloc: 'B21[3:1]'} + XTAL_48M_SEL_MODE : {show: y, blk : 0, word: 5, pos: 12, len : 1, start: 172, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[12]', bloc: 'B21[4]'} + ECDSA_DISABLE_P192 : {show: y, blk : 0, word: 5, pos: 13, len : 1, start: 173, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13]', bloc: 'B21[5]'} + ECC_FORCE_CONST_TIME : {show: y, blk : 0, word: 5, pos: 14, len : 1, start: 174, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[14]', bloc: 'B21[6]'} + RESERVE_0_175 : {show: n, blk : 0, word: 5, pos: 15, len : 17, start: 175, type : 'uint:17', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[31:15]', bloc: 'B21[7],B22,B23'} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SYS1_REG[31:16]', bloc: 'B6,B7'} + MAC_RESERVED_0 : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS2_REG[13:0]', bloc: 'B8,B9[5:0]'} + MAC_RESERVED_1 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + SYS_DATA_PART0_0 : {show: n, blk : 1, word: 3, pos: 18, len : 14, start: 114, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: 'EFUSE_RD_MAC_SYS3_REG[31:18]', bloc: 'B14[7:2],B15'} + SYS_DATA_PART0_1 : {show: n, blk : 1, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS4_REG, bloc: 'B16,B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the second 32-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS5_REG, bloc: 'B20,B21,B22,B23'} + BLOCK_SYS_DATA1 : {show: y, blk : 2, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: System data part 1 (reserved), rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} + RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} + CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} + RESERVED_3_248 : {show: n, blk : 3, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA7_REG[31:24]', bloc: B31} + BLOCK_KEY0 : {show: y, blk : 4, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 23, rd_dis : 0, alt : KEY0, dict : '', desc: Key0 or user data, rloc: EFUSE_RD_KEY0_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY1 : {show: y, blk : 5, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 24, rd_dis : 1, alt : KEY1, dict : '', desc: Key1 or user data, rloc: EFUSE_RD_KEY1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY2 : {show: y, blk : 6, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 25, rd_dis : 2, alt : KEY2, dict : '', desc: Key2 or user data, rloc: EFUSE_RD_KEY2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} + BLOCK_SYS_DATA2 : {show: y, blk: 10, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 29, rd_dis : 6, alt : SYS_DATA_PART2, dict : '', desc: System data part 2 (reserved), rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} diff --git a/espefuse/efuse_defs/esp32c61.yaml b/espefuse/efuse_defs/esp32c61.yaml index 4600e0da5..ffec87b7c 100644 --- a/espefuse/efuse_defs/esp32c61.yaml +++ b/espefuse/efuse_defs/esp32c61.yaml @@ -1,83 +1,61 @@ -VER_NO: 709e8ea096e8a03a10006d40d5451a49 +VER_NO: beb6fa3bf4a43a464c3365fda28815f5 EFUSES: - WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'} + WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS0_REG, bloc: 'B0,B1,B2,B3'} RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'} - DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} - DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} - DIS_USB_SERIAL_JTAG : {show: y, blk : 0, word: 1, pos: 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} - DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} - SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} - JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} - DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[4]'} - DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[5]'} - USB_DREFH : {show: n, blk : 0, word: 1, pos: 15, len : 2, start : 47, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[16:15]', bloc: 'B5[7:6]'} - USB_DREFL : {show: n, blk : 0, word: 1, pos: 17, len : 2, start : 49, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:17]', bloc: 'B6[1:0]'} - USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[2]'} - VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[3]'} - WDT_DELAY_SEL : {show: y, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[5:4]'} - SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 1, pos: 23, len : 3, start : 55, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25:23]', bloc: 'B7[0],B6[7:6]'} - SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[1]'} - SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 1, pos: 27, len : 1, start : 59, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[27]', bloc: 'B7[2]'} - SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 1, pos: 28, len : 1, start : 60, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28]', bloc: 'B7[3]'} - KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos: 0, len : 4, start : 64, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[3:0]', bloc: 'B8[3:0]'} - KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos: 4, len : 4, start : 68, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[7:4]', bloc: 'B8[7:4]'} + DIS_ICACHE : {show: y, blk : 0, word: 1, pos : 7, len : 1, start : 39, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'} + DIS_USB_JTAG : {show: y, blk : 0, word: 1, pos : 8, len : 1, start : 40, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'} + DIS_USB_SERIAL_JTAG : {show: n, blk : 0, word: 1, pos : 9, len : 1, start : 41, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'} + DIS_FORCE_DOWNLOAD : {show: y, blk : 0, word: 1, pos: 10, len : 1, start : 42, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'} + SPI_DOWNLOAD_MSPI_DIS : {show: y, blk : 0, word: 1, pos: 11, len : 1, start : 43, type : bool, wr_dis : 17, rd_dis: null, alt : '', dict : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'} + JTAG_SEL_ENABLE : {show: y, blk : 0, word: 1, pos: 12, len : 1, start : 44, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[12]', bloc: 'B5[4]'} + DIS_PAD_JTAG : {show: y, blk : 0, word: 1, pos: 13, len : 1, start : 45, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'} + DIS_DOWNLOAD_MANUAL_ENCRYPT : {show: y, blk : 0, word: 1, pos: 14, len : 1, start : 46, type : bool, wr_dis : 2, rd_dis: null, alt : '', dict : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'} + USB_DREFH : {show: n, blk : 0, word: 1, pos: 15, len : 2, start : 47, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[16:15]', bloc: 'B5[7],B6[0]'} + USB_DREFL : {show: n, blk : 0, word: 1, pos: 17, len : 2, start : 49, type : 'uint:2', wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18:17]', bloc: 'B6[2:1]'} + USB_EXCHG_PINS : {show: y, blk : 0, word: 1, pos: 19, len : 1, start : 51, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'} + VDD_SPI_AS_GPIO : {show: y, blk : 0, word: 1, pos: 20, len : 1, start : 52, type : bool, wr_dis : 30, rd_dis: null, alt : '', dict : '', desc: 'Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[20]', bloc: 'B6[4]'} + WDT_DELAY_SEL : {show: y, blk : 0, word: 1, pos: 21, len : 2, start : 53, type : 'uint:2', wr_dis : 3, rd_dis: null, alt : '', dict : '', desc: 'Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22:21]', bloc: 'B6[6:5]'} + SPI_BOOT_CRYPT_CNT : {show: y, blk : 0, word: 1, pos: 23, len : 3, start : 55, type : 'uint:3', wr_dis : 4, rd_dis: null, alt : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25:23]', bloc: 'B6[7],B7[1:0]'} + SECURE_BOOT_KEY_REVOKE0 : {show: y, blk : 0, word: 1, pos: 26, len : 1, start : 58, type : bool, wr_dis : 5, rd_dis: null, alt : '', dict : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'} + SECURE_BOOT_KEY_REVOKE1 : {show: y, blk : 0, word: 1, pos: 27, len : 1, start : 59, type : bool, wr_dis : 6, rd_dis: null, alt : '', dict : '', desc: Revoke 2nd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[27]', bloc: 'B7[3]'} + SECURE_BOOT_KEY_REVOKE2 : {show: y, blk : 0, word: 1, pos: 28, len : 1, start : 60, type : bool, wr_dis : 7, rd_dis: null, alt : '', dict : '', desc: Revoke 3rd secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28]', bloc: 'B7[4]'} + RESERVE_0_61 : {show: n, blk : 0, word: 1, pos: 29, len : 3, start : 61, type : 'uint:3', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:29]', bloc: 'B7[7:5]'} + KEY_PURPOSE_0 : {show: y, blk : 0, word: 2, pos : 0, len : 4, start : 64, type : 'uint:4', wr_dis : 8, rd_dis: null, alt : KEY0_PURPOSE, dict : '', desc: Represents the purpose of Key0, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[3:0]', bloc: 'B8[3:0]'} + KEY_PURPOSE_1 : {show: y, blk : 0, word: 2, pos : 4, len : 4, start : 68, type : 'uint:4', wr_dis : 9, rd_dis: null, alt : KEY1_PURPOSE, dict : '', desc: Represents the purpose of Key1, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[7:4]', bloc: 'B8[7:4]'} KEY_PURPOSE_2 : {show: y, blk : 0, word: 2, pos : 8, len : 4, start : 72, type : 'uint:4', wr_dis : 10, rd_dis: null, alt : KEY2_PURPOSE, dict : '', desc: Represents the purpose of Key2, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[11:8]', bloc: 'B9[3:0]'} - KEY_PURPOSE_3 : {show: y, blk : 0, word: 2, pos : 12,len : 4, start: 76, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:12]', bloc: 'B9[7:4]'} - KEY_PURPOSE_4 : {show: y, blk : 0, word: 2, pos : 16, len : 4, start: 80, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[19:16]', bloc: 'B10[3:0]'} - KEY_PURPOSE_5 : {show: y, blk : 0, word: 2, pos: 20, len : 4, start: 84, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23:20]', bloc: 'B10[7:4]'} - SEC_DPA_LEVEL : {show: y, blk : 0, word: 2, pos: 24, len : 2, start: 88, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : DPA_SEC_LEVEL, dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[25:24]', bloc: 'B11[1:0]'} - SECURE_BOOT_EN : {show: y, blk : 0, word: 2, pos: 26, len : 1, start: 90, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[26]', bloc: 'B11[2]'} - SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 2, pos: 27, len : 1, start: 91, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27]', bloc: 'B11[3]'} - FLASH_TPUW : {show: y, blk : 0, word: 2, pos: 28, len : 4, start: 92, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} - DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 3, pos : 0, len : 1, start: 96, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[0]', bloc: 'B12[0]'} - DIS_DIRECT_BOOT : {show: y, blk : 0, word: 3, pos : 1, len : 1, start: 97, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[1]', bloc: 'B12[1]'} - DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 3, pos : 2, len : 1, start: 98, type : bool, wr_dis : 18, rd_dis: null, alt : DIS_USB_PRINT, dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[2]', bloc: 'B12[2]'} - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 3, pos : 3, len : 1, start: 99, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3]', bloc: 'B12[3]'} - ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 3, pos : 4, len : 1, start: 100, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[4]', bloc: 'B12[4]'} - UART_PRINT_CONTROL : {show: y, blk : 0, word: 3, pos : 5, len : 2, start: 101, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict: '{0: "Enable", 1: "Enable when GPIO8 is low at reset", 2: "Enable when GPIO8 is high at reset", 3: "Disable"}', desc: Set the default UARTboot message output mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[6:5]', bloc: 'B12[6:5]'} - FORCE_SEND_RESUME : {show: y, blk : 0, word: 3, pos: 7, len : 1, start: 103, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7]', bloc: 'B12[7]'} - SECURE_VERSION : {show: y, blk : 0, word: 3, pos: 8, len : 16, start: 104, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23:8]', bloc: 'B14,B13'} - SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 3, pos: 24, len : 1, start: 120, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[24]', bloc: 'B15[0]'} - HAS_EN_PAD : {show: y, blk : 0, word: 3, pos: 25, len : 1, start: 121, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[25]', bloc: 'B15[1]'} - XTS_DPA_CLK_ENABLE : {show: y, blk : 0, word: 3, pos: 26, len : 1, start: 122, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26]', bloc: 'B15[2]'} - XTS_DPA_PSEUDO_LEVEL : {show: y, blk : 0, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[28:27]', bloc: 'B15[4:3]'} - DIS_WIFI6 : {show: y, blk : 0, word: 3, pos: 29, len : 1, start: 125, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'Disable wifi6', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[29]', bloc: 'B15[5]'} - ECDSA_DISABLE_P192 : {show: y, blk : 0, word: 3, pos: 30, len : 1, start: 126, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'ECDSA disable P192', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[30]', bloc: 'B15[6]'} - ECC_FORCE_CONST_TIME : {show: y, blk : 0, word: 3, pos: 31, len : 1, start: 127, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: 'ECC force const time', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31]', bloc: 'B15[7]'} - MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SPI_SYS_0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} - MAC_EXT : {show: y, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'bytes:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the extended bits of MAC address, rloc: 'EFUSE_RD_MAC_SPI_SYS_1_REG[31:16]', bloc: 'B6,B7'} - MAC_SPI_RESERVED : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[13:0]', bloc: 'B8,B9[5:0]'} - SPI_PAD_CONF_1 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the first part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} - SPI_PAD_CONF_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second part of SPI_PAD_CONF, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} - WAFER_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 18, len : 4, start: 114, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[21:18]', bloc: 'B14[5:2]'} - WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 22, len : 2, start: 118, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[23:22]', bloc: 'B14[7:6]'} - PKG_VERSION : {show: y, blk : 1, word: 3, pos: 24, len : 3, start: 120, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[26:24]', bloc: 'B15[2:0]'} - BLK_VERSION_MINOR : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'} - BLK_VERSION_MAJOR : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'} - FLASH_CAP : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'} - FLASH_TEMP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'} - FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 5, len : 3, start: 133, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: '', rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[7:5]', bloc: 'B16[7:5]'} - RESERVED_1_136 : {show: n, blk : 1, word: 4, pos : 8, len : 24, start: 136, type : 'uint:24', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:8]', bloc: 'B17,B18,B19'} - SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Stores the second 32 bits of the zeroth part of system data, rloc: EFUSE_RD_MAC_SPI_SYS_5_REG, bloc: 'B20,B21,B22,B23'} - OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'} - TEMP_CALIB : {show: y, blk : 2, word: 4, pos : 0, len : 9, start: 128, type : 'uint:9', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[8:0]', bloc: 'B16,B17[0]'} - OCODE : {show: y, blk : 2, word: 4, pos : 9, len : 8, start: 137, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[16:9]', bloc: 'B17[7:1],B18[0]'} - ADC1_INIT_CODE_ATTEN0 : {show: y, blk : 2, word: 4, pos: 17, len : 10, start: 145, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[26:17]', bloc: 'B18[7:1],B19[2:0]'} - ADC1_INIT_CODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 27, len : 10, start: 155, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:27]', bloc: 'B19[7:3],B20[4:0]'} - ADC1_INIT_CODE_ATTEN2 : {show: y, blk : 2, word: 5, pos : 5, len : 10, start: 165, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[14:5]', bloc: 'B20[7:5],B21[6:0]'} - ADC1_INIT_CODE_ATTEN3 : {show: y, blk : 2, word: 5, pos: 15, len : 10, start: 175, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[24:15]', bloc: 'B21[7],B22,B23[0]'} - ADC1_CAL_VOL_ATTEN0 : {show: y, blk : 2, word: 5, pos: 25, len : 10, start: 185, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:25]', bloc: 'B23[7:1],B24[2:0]'} - ADC1_CAL_VOL_ATTEN1 : {show: y, blk : 2, word: 6, pos : 3, len : 10, start: 195, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[12:3]', bloc: 'B24[7:3],B25[4:0]'} - ADC1_CAL_VOL_ATTEN2 : {show: y, blk : 2, word: 6, pos: 13, len : 10, start: 205, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[22:13]', bloc: 'B25[7:5],B26[6:0]'} - ADC1_CAL_VOL_ATTEN3 : {show: y, blk : 2, word: 6, pos: 23, len : 10, start: 215, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 calibration voltage at atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:23]', bloc: 'B26[7],B27,B28[0]'} - ADC1_INIT_CODE_ATTEN0_CH0 : {show: y, blk : 2, word: 7, pos : 1, len : 4, start: 225, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch0, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[4:1]', bloc: 'B28[4:1]'} - ADC1_INIT_CODE_ATTEN0_CH1 : {show: y, blk : 2, word: 7, pos : 5, len : 4, start: 229, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch1, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[8:5]', bloc: 'B28[7:5],B29[0]'} - ADC1_INIT_CODE_ATTEN0_CH2 : {show: y, blk : 2, word: 7, pos : 9, len : 4, start: 233, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[12:9]', bloc: 'B29[4:1]'} - ADC1_INIT_CODE_ATTEN0_CH3 : {show: y, blk : 2, word: 7, pos: 13, len : 4, start: 237, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:13]', bloc: 'B29[7:5],B30[0]'} - ADC1_INIT_CODE_ATTEN0_CH4 : {show: y, blk : 2, word: 7, pos: 17, len : 4, start: 241, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch4, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[20:17]', bloc: 'B30[4:1]'} - ADC1_INIT_CODE_ATTEN0_CH5 : {show: y, blk : 2, word: 7, pos: 21, len : 4, start: 245, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch5, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[24:21]', bloc: 'B30[7:5],B31[0]'} - ADC1_INIT_CODE_ATTEN0_CH6 : {show: y, blk : 2, word: 7, pos: 25, len : 4, start: 249, type : 'uint:4', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: ADC1 init code at atten0 ch6, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[28:25]', bloc: 'B31[4:1]'} - RESERVED_2_253 : {show: n, blk : 2, word: 7, pos: 29, len : 3, start: 253, type : 'uint:3', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:29]', bloc: 'B31[7:5]'} + KEY_PURPOSE_3 : {show: y, blk : 0, word: 2, pos: 12, len : 4, start : 76, type : 'uint:4', wr_dis : 11, rd_dis: null, alt : KEY3_PURPOSE, dict : '', desc: Represents the purpose of Key3, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:12]', bloc: 'B9[7:4]'} + KEY_PURPOSE_4 : {show: y, blk : 0, word: 2, pos: 16, len : 4, start : 80, type : 'uint:4', wr_dis : 12, rd_dis: null, alt : KEY4_PURPOSE, dict : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[19:16]', bloc: 'B10[3:0]'} + KEY_PURPOSE_5 : {show: y, blk : 0, word: 2, pos: 20, len : 4, start : 84, type : 'uint:4', wr_dis : 13, rd_dis: null, alt : KEY5_PURPOSE, dict : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[23:20]', bloc: 'B10[7:4]'} + SEC_DPA_LEVEL : {show: y, blk : 0, word: 2, pos: 24, len : 2, start : 88, type : 'uint:2', wr_dis : 14, rd_dis: null, alt : '', dict : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[25:24]', bloc: 'B11[1:0]'} + SECURE_BOOT_EN : {show: y, blk : 0, word: 2, pos: 26, len : 1, start : 90, type : bool, wr_dis : 15, rd_dis: null, alt : '', dict : '', desc: 'Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[26]', bloc: 'B11[2]'} + SECURE_BOOT_AGGRESSIVE_REVOKE : {show: y, blk : 0, word: 2, pos: 27, len : 1, start : 91, type : bool, wr_dis : 16, rd_dis: null, alt : '', dict : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[27]', bloc: 'B11[3]'} + FLASH_TPUW : {show: y, blk : 0, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[31:28]', bloc: 'B11[7:4]'} + DIS_DOWNLOAD_MODE : {show: y, blk : 0, word: 3, pos : 0, len : 1, start : 96, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[0]', bloc: 'B12[0]'} + DIS_DIRECT_BOOT : {show: y, blk : 0, word: 3, pos : 1, len : 1, start : 97, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[1]', bloc: 'B12[1]'} + DIS_USB_SERIAL_JTAG_ROM_PRINT : {show: y, blk : 0, word: 3, pos : 2, len : 1, start : 98, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[2]', bloc: 'B12[2]'} + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: {show: y, blk : 0, word: 3, pos : 3, len : 1, start : 99, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3]', bloc: 'B12[3]'} + ENABLE_SECURITY_DOWNLOAD : {show: y, blk : 0, word: 3, pos : 4, len : 1, start: 100, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: 'Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[4]', bloc: 'B12[4]'} + UART_PRINT_CONTROL : {show: y, blk : 0, word: 3, pos : 5, len : 2, start: 101, type : 'uint:2', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the types of UART printing, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[6:5]', bloc: 'B12[6:5]'} + FORCE_SEND_RESUME : {show: y, blk : 0, word: 3, pos : 7, len : 1, start: 103, type : bool, wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents whether ROM code is forced to send a resume command during SPI boot, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[7]', bloc: 'B12[7]'} + SECURE_VERSION : {show: y, blk : 0, word: 3, pos : 8, len : 16, start: 104, type : 'uint:16', wr_dis : 18, rd_dis: null, alt : '', dict : '', desc: Represents the version used by ESP-IDF anti-rollback feature, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[23:8]', bloc: 'B13,B14'} + SECURE_BOOT_DISABLE_FAST_WAKE : {show: y, blk : 0, word: 3, pos: 24, len : 1, start: 120, type : bool, wr_dis : 19, rd_dis: null, alt : '', dict : '', desc: Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[24]', bloc: 'B15[0]'} + HYS_EN_PAD : {show: y, blk : 0, word: 3, pos: 25, len : 1, start: 121, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[25]', bloc: 'B15[1]'} + XTS_DPA_CLK_ENABLE : {show: y, blk : 0, word: 3, pos: 26, len : 1, start: 122, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26]', bloc: 'B15[2]'} + XTS_DPA_PSEUDO_LEVEL : {show: y, blk : 0, word: 3, pos: 27, len : 2, start: 123, type : 'uint:2', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[28:27]', bloc: 'B15[4:3]'} + DIS_WIFI6 : {show: y, blk : 0, word: 3, pos: 29, len : 1, start: 125, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled.\\', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[29]', bloc: 'B15[5]'} + ECDSA_DISABLE_P192 : {show: y, blk : 0, word: 3, pos: 30, len : 1, start: 126, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[30]', bloc: 'B15[6]'} + ECC_FORCE_CONST_TIME : {show: y, blk : 0, word: 3, pos: 31, len : 1, start: 127, type : bool, wr_dis: null, rd_dis: null, alt : '', dict : '', desc: 'Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31]', bloc: 'B15[7]'} + REPEAT_DATA3 : {show: n, blk : 0, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: EFUSE_RD_REPEAT_DATA3_REG, bloc: 'B16,B17,B18,B19'} + REPEAT_DATA4 : {show: n, blk : 0, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: EFUSE_RD_REPEAT_DATA4_REG, bloc: 'B20,B21,B22,B23'} + MAC : {show: y, blk : 1, word: 0, pos : 0, len : 48, start : 0, type : 'bytes:6', wr_dis : 20, rd_dis: null, alt : MAC_FACTORY, dict : '', desc: MAC address, rloc: EFUSE_RD_MAC_SYS0_REG, bloc: 'B0,B1,B2,B3,B4,B5'} + RESERVE_1_48 : {show: n, blk : 1, word: 1, pos: 16, len : 16, start : 48, type : 'uint:16', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_MAC_SYS1_REG[31:16]', bloc: 'B6,B7'} + MAC_RESERVED_0 : {show: n, blk : 1, word: 2, pos : 0, len : 14, start : 64, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS2_REG[13:0]', bloc: 'B8,B9[5:0]'} + MAC_RESERVED_1 : {show: n, blk : 1, word: 2, pos: 14, len : 18, start : 78, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS2_REG[31:14]', bloc: 'B9[7:6],B10,B11'} + MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'} + SYS_DATA_PART0_0 : {show: n, blk : 1, word: 3, pos: 18, len : 14, start: 114, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: 'EFUSE_RD_MAC_SYS3_REG[31:18]', bloc: 'B14[7:2],B15'} + SYS_DATA_PART0_1 : {show: n, blk : 1, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS4_REG, bloc: 'B16,B17,B18,B19'} + SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the second 32-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS5_REG, bloc: 'B20,B21,B22,B23'} + BLOCK_SYS_DATA1 : {show: y, blk : 2, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: System data part 1 (reserved), rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'} BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'} RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24} CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'} diff --git a/test/efuse_scripts/esp32xx/execute_efuse_script.py b/test/efuse_scripts/esp32xx/execute_efuse_script.py index d09417573..9ccb0e408 100644 --- a/test/efuse_scripts/esp32xx/execute_efuse_script.py +++ b/test/efuse_scripts/esp32xx/execute_efuse_script.py @@ -1,6 +1,6 @@ # flake8: noqa # fmt: off -espefuse(esp, efuses, args, 'burn_efuse DIS_FORCE_DOWNLOAD 1 DIS_CAN 1 DIS_DOWNLOAD_MODE 1') +espefuse(esp, efuses, args, 'burn_efuse DIS_FORCE_DOWNLOAD 1 DIS_DOWNLOAD_MODE 1') espefuse(esp, efuses, args, 'burn_bit BLOCK_USR_DATA 64 66 69 72 78 82 83 90') espefuse(esp, efuses, args, 'read_protect_efuse BLOCK_SYS_DATA2') espefuse(esp, efuses, args, 'write_protect_efuse BLOCK_SYS_DATA2') @@ -17,8 +17,6 @@ # Checks written eFuses if efuses["DIS_FORCE_DOWNLOAD"].get() != 1: raise esptool.FatalError("DIS_FORCE_DOWNLOAD was not set") -if efuses["DIS_CAN"].get() != 1: - raise esptool.FatalError("DIS_CAN was not set") if efuses["DIS_DOWNLOAD_MODE"].get() != 1: raise esptool.FatalError("DIS_DOWNLOAD_MODE was not set") diff --git a/test/efuse_scripts/esp32xx/execute_efuse_script2.py b/test/efuse_scripts/esp32xx/execute_efuse_script2.py index 7ece204fb..af01379eb 100644 --- a/test/efuse_scripts/esp32xx/execute_efuse_script2.py +++ b/test/efuse_scripts/esp32xx/execute_efuse_script2.py @@ -1,6 +1,6 @@ # flake8: noqa # fmt: off -espefuse(esp, efuses, args, 'burn_efuse DIS_FORCE_DOWNLOAD 1 DIS_CAN 1 DIS_DOWNLOAD_MODE 1') +espefuse(esp, efuses, args, 'burn_efuse DIS_FORCE_DOWNLOAD 1 DIS_DOWNLOAD_MODE 1') if efuses["DIS_FORCE_DOWNLOAD"].get() != 0: raise esptool.FatalError("Burn should be at the end") diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 2c3dda7a9..5824ab56b 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -1,7 +1,8 @@ # HOST_TEST for espefuse.py using the pytest framework # # Supports esp32, esp32s2, esp32s3beta2, esp32s3, -# esp32c3, esp32h2beta1, esp32c2, esp32c6, esp32p4 +# esp32c3, esp32h2beta1, esp32c2, esp32c6, esp32p4, +# esp32c61, esp32c5, esp32c5beta3. # # How to use: # @@ -215,8 +216,6 @@ def test_check_error(self): self.espefuse_py("check_error --recovery") -# TODO: [ESP32C61] IDF-9238 -@pytest.mark.skipif(arg_chip == "esp32c61", reason="Not supported yet") class TestReadProtectionCommands(EfuseTestCase): def test_read_protect_efuse(self): self.espefuse_py("read_protect_efuse -h") @@ -296,7 +295,11 @@ def test_read_protect_efuse4(self): ret_code=2, ) else: - key1_purpose = "USER" if arg_chip in ["esp32p4"] else "RESERVED" + key1_purpose = ( + "USER" + if arg_chip in ["esp32p4", "esp32c61", "esp32c5", "esp32c5beta3"] + else "RESERVED" + ) self.espefuse_py( f"burn_key BLOCK_KEY0 {IMAGES_DIR}/256bit USER \ BLOCK_KEY1 {IMAGES_DIR}/256bit {key1_purpose} \ @@ -350,8 +353,6 @@ def test_burn_and_read_protect_efuse(self): ) -# TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 -@pytest.mark.skipif(arg_chip in ["esp32c5", "esp32c61"], reason="Not supported yet") class TestWriteProtectionCommands(EfuseTestCase): def test_write_protect_efuse(self): self.espefuse_py("write_protect_efuse -h") @@ -371,7 +372,7 @@ def test_write_protect_efuse(self): efuse_lists2 = "RD_DIS KEY_PURPOSE_0 KEY_PURPOSE_2" else: efuse_lists = """RD_DIS DIS_ICACHE DIS_FORCE_DOWNLOAD - DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT + DIS_DOWNLOAD_MANUAL_ENCRYPT USB_EXCHG_PINS WDT_DELAY_SEL SPI_BOOT_CRYPT_CNT SECURE_BOOT_KEY_REVOKE0 SECURE_BOOT_KEY_REVOKE1 SECURE_BOOT_KEY_REVOKE2 KEY_PURPOSE_0 KEY_PURPOSE_1 @@ -379,11 +380,16 @@ def test_write_protect_efuse(self): SECURE_BOOT_EN SECURE_BOOT_AGGRESSIVE_REVOKE FLASH_TPUW DIS_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL - MAC OPTIONAL_UNIQUE_ID + MAC BLOCK_USR_DATA BLOCK_KEY0 BLOCK_KEY1 BLOCK_KEY2 BLOCK_KEY3 BLOCK_KEY4 BLOCK_KEY5""" - if arg_chip not in ["esp32h2", "esp32h2beta1"] and arg_chip not in [ - "esp32c6" + if arg_chip not in [ + "esp32h2", + "esp32h2beta1", + "esp32c6", + "esp32c61", + "esp32c5", + "esp32c5beta3", ]: efuse_lists += """ DIS_DOWNLOAD_ICACHE SPI_PAD_CONFIG_CLK SPI_PAD_CONFIG_Q @@ -458,19 +464,13 @@ def test_burn_custom_mac_with_34_coding_scheme(self): @pytest.mark.skipif( - # TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 arg_chip - in [ - "esp32c2", - "esp32h2beta1", - "esp32c3", - "esp32c6", - "esp32h2", - "esp32p4", - "esp32c5", - "esp32c61", + not in [ + "esp32", + "esp32s2", + "esp32s3", ], - reason=f"TODO: add support set_flash_voltage for {arg_chip}", + reason=f"{arg_chip} does not support set_flash_voltage", ) class TestSetFlashVoltageCommands(EfuseTestCase): def test_set_flash_voltage_1_8v(self): @@ -680,16 +680,6 @@ def test_burn_mac_custom_efuse(self): self.espefuse_py("burn_efuse CUSTOM_MAC AA:CD:EF:01:02:03") self.espefuse_py("get_custom_mac", check_msg=f"aa:cd:ef:01:02:03 {crc_msg}") - # TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 - @pytest.mark.skipif( - arg_chip - in [ - "esp32p4", - "esp32c5", - "esp32c61", - ], - reason="No such eFuses, will be defined later", - ) def test_burn_efuse(self): self.espefuse_py("burn_efuse -h") if arg_chip == "esp32": @@ -716,23 +706,21 @@ def test_burn_efuse(self): SECURE_BOOT_EN 1 \ UART_PRINT_CONTROL 1" ) - self.espefuse_py( - "burn_efuse \ - OPTIONAL_UNIQUE_ID 0x2328ad5ac9145f698f843a26d6eae168", - check_msg="-> 0x2328ad5ac9145f698f843a26d6eae168", - ) - output = self.espefuse_py("summary -d") - assert ( - "read_regs: d6eae168 8f843a26 c9145f69 2328ad5a " - "00000000 00000000 00000000 00000000" - ) in output - assert "= 68 e1 ea d6 26 3a 84 8f 69 5f 14 c9 5a ad 28 23 R/W" in output - efuse_from_blk2 = "BLK_VERSION_MAJOR" - if arg_chip == "esp32s2": - efuse_from_blk2 = "BLK_VERSION_MINOR" - if arg_chip != "esp32c6": + if arg_chip not in ["esp32c5", "esp32c5beta3", "esp32c61"]: + # chips having the OPTIONAL_UNIQUE_ID field + self.espefuse_py( + "burn_efuse \ + OPTIONAL_UNIQUE_ID 0x2328ad5ac9145f698f843a26d6eae168", + check_msg="-> 0x2328ad5ac9145f698f843a26d6eae168", + ) + output = self.espefuse_py("summary -d") + assert ( + "read_regs: d6eae168 8f843a26 c9145f69 2328ad5a " + "00000000 00000000 00000000 00000000" + ) in output + assert "= 68 e1 ea d6 26 3a 84 8f 69 5f 14 c9 5a ad 28 23 R/W" in output self.espefuse_py( - f"burn_efuse {efuse_from_blk2} 1", + "burn_bit BLOCK_SYS_DATA 1", check_msg="Burn into BLOCK_SYS_DATA is forbidden " "(RS coding scheme does not allow this).", ret_code=2, @@ -1798,8 +1786,6 @@ def test_2_secure_boot_v1(self): ) -# TODO: [ESP32C5] IDF-8629, [ESP32C61] IDF-9238 -@pytest.mark.skipif(arg_chip in ["esp32c5", "esp32c61"], reason="Not supported yet") class TestExecuteScriptsCommands(EfuseTestCase): @classmethod def setup_class(self): From 296a635e9ac06122f7bec5a2777a691adb3fa31f Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Mon, 11 Mar 2024 13:06:23 +0100 Subject: [PATCH 160/209] fix(esptool): clear boot control register on ESP32-S3 https://github.com/espressif/arduino-esp32/issues/6762 https://github.com/espressif/esp-idf/issues/13287 --- esptool/targets/esp32s3.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 7531f4ae0..aa07e20f2 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -352,6 +352,12 @@ def hard_reset(self): if uses_usb_otg: self._check_if_can_reset() + # Clear force download boot mode to avoid the chip being stuck in download mode after reset + # workaround for issue: https://github.com/espressif/arduino-esp32/issues/6762 + self.write_reg( + self.RTC_CNTL_OPTION1_REG, 0, self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK + ) + print("Hard resetting via RTS pin...") HardReset(self._port, uses_usb_otg)() From d44592d773616f391751f1c6aa1fe9c5280d26d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Thu, 14 Mar 2024 15:28:41 +0100 Subject: [PATCH 161/209] fix(secure_download_mode): Disable secure boot detection and print more info --- esptool/__init__.py | 4 ++++ esptool/cmds.py | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 556847b0c..252f34ace 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -906,6 +906,10 @@ def flash_xmc_startup(): flash_size = detect_flash_size(esp, args) elif args.flash_size == "keep": flash_size = detect_flash_size(esp, args=None) + if not esp.IS_STUB: + print( + "WARNING: In case of failure, please set a specific --flash_size." + ) else: flash_size = args.flash_size diff --git a/esptool/cmds.py b/esptool/cmds.py index b4bf46bb0..701dc3ea8 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -230,7 +230,7 @@ def detect_flash_size(esp, args=None): if flash_size is None: flash_size = "4MB" print( - "Warning: Could not auto-detect Flash size " + "WARNING: Could not auto-detect Flash size " f"(FlashID={flash_id:#x}, SizeID={size_id:#x}), defaulting to 4MB" ) else: @@ -568,11 +568,11 @@ def write_flash(esp, args): print("WARNING: File %s is empty" % argfile.name) continue - if not esp.get_secure_boot_enabled(): + if not esp.secure_download_mode and not esp.get_secure_boot_enabled(): image = _update_image_flash_params(esp, address, args, image) else: print( - "WARNING: Secure boot is enabled, so not changing any flash settings." + "WARNING: Security features enabled, so not changing any flash settings." ) calcmd5 = hashlib.md5(image).hexdigest() uncsize = len(image) From a561630c5ca0594346f8c87fd82094e75d8b4b4c Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 13 Mar 2024 14:28:13 +0100 Subject: [PATCH 162/209] feat: add UF2 IDs for ESP32-C5 and ESP32-C61 https://github.com/microsoft/uf2/pull/80 --- esptool/targets/esp32c5.py | 2 ++ esptool/targets/esp32c61.py | 2 ++ test/test_uf2_ids.py | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py index 802cc52ab..d4517af91 100644 --- a/esptool/targets/esp32c5.py +++ b/esptool/targets/esp32c5.py @@ -45,6 +45,8 @@ class ESP32C5ROM(ESP32C6ROM): [0x600FE000, 0x60100000, "MEM_INTERNAL2"], ] + UF2_FAMILY_ID = 0xF71C0343 + def get_chip_description(self): chip_name = { 0: "ESP32-C5", diff --git a/esptool/targets/esp32c61.py b/esptool/targets/esp32c61.py index 96f8ff93e..58867a433 100644 --- a/esptool/targets/esp32c61.py +++ b/esptool/targets/esp32c61.py @@ -58,6 +58,8 @@ class ESP32C61ROM(ESP32C6ROM): [0x600FE000, 0x60100000, "MEM_INTERNAL2"], ] + UF2_FAMILY_ID = 0x77D850C4 + def get_chip_description(self): chip_name = { 0: "ESP32-C61", diff --git a/test/test_uf2_ids.py b/test/test_uf2_ids.py index 1919013f7..8be38b91c 100644 --- a/test/test_uf2_ids.py +++ b/test/test_uf2_ids.py @@ -53,7 +53,7 @@ def test_check_uf2(uf2_json): out = [] # there was a difference between the chip support for chip in diff: - if chip in esptool_chips: + if chip not in esptool_chips: out.append( f"Missing chip definition for '{chip}' in esptool " "which was defined in Microsoft UF2 Github repo." From 353867e5833becddcd6b9110cb8ae6366ef0e5d3 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Thu, 29 Feb 2024 16:22:42 +0100 Subject: [PATCH 163/209] feat(esp32-p4): add spi-connection restriction to ROM class --- esptool/targets/esp32p4.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 7b4a35fbe..0d3c54793 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -173,7 +173,13 @@ def _post_connect(self): # self.disable_watchdogs() def check_spi_connection(self, spi_connection): - pass # TODO: Define GPIOs for --spi-connection + if not set(spi_connection).issubset(set(range(0, 55))): + raise FatalError("SPI Pin numbers must be in the range 0-54.") + if any([v for v in spi_connection if v in [24, 25]]): + print( + "WARNING: GPIO pins 24 and 25 are used by USB-Serial/JTAG, " + "consider using other pins for SPI flash connection." + ) class ESP32P4StubLoader(ESP32P4ROM): From 8e1c6a71db6d673c39e4549a7fb96360748160f3 Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Wed, 13 Mar 2024 11:13:52 +0100 Subject: [PATCH 164/209] ci: Add option to run tests with esp-flasher-stub --- .gitlab-ci.yml | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 967a157ee..0332c0447 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -34,6 +34,19 @@ cache: paths: - "$CI_PROJECT_DIR/.cache/pip" +.use_esp_flasher_stub: &use_esp_flasher_stub | + if [[ "$CI_USE_ESP_FLASHER_STUB" = "1" ]] + then + apt-get update && apt-get install -y jq + wget https://api.github.com/repos/esp-rs/esp-flasher-stub/releases/latest -O /tmp/esp_flasher_stub.json + echo "esp-flasher-stub version:"; cat /tmp/esp_flasher_stub.json | jq -r .tag_name + mkdir /tmp/assets + cat /tmp/esp_flasher_stub.json | jq -r .assets[].browser_download_url | while read -r url; do wget $url -P /tmp/assets; done + for f in /tmp/assets/*.json; do fname=$(basename $f); cp $f esptool/targets/stub_flasher/stub_flasher_${fname#esp}; done + echo "These are the changes in the repository:" + git diff --stat + fi + .test_template: &test_template stage: test image: python:3.7-bullseye @@ -59,6 +72,8 @@ version_check: .host_tests_template: &host_tests_template <<: *test_template + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" artifacts: when: always paths: @@ -125,6 +140,8 @@ host_tests_hsm: run_pre_commit_hooks: stage: test image: python:3.7-bullseye + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" tags: - host_test script: @@ -145,6 +162,8 @@ run_pre_commit_hooks: # Check all the scripts can run when installed, collect coverage check_install_coverage: <<: *test_template + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" artifacts: when: always paths: @@ -161,6 +180,8 @@ check_install_coverage: # Check all the scripts can run when installed check_install: <<: *test_template + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" before_script: - pip install . script: @@ -169,6 +190,8 @@ check_install: # Check all the scripts can run when installed in editable mode check_install_editable: <<: *test_template + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" before_script: - pip install -e . script: @@ -177,6 +200,8 @@ check_install_editable: # Check all the scripts can run when installed in Python user install directory check_install_system: <<: *test_template + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" before_script: - pip install --user . script: @@ -190,6 +215,8 @@ check_install_system: # Check all the scripts can run when installed in virtual environment check_install_venv: <<: *test_template + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" before_script: - python -m venv test_env - source test_env/bin/activate @@ -201,6 +228,8 @@ check_install_venv: # as the one embedded in esptool check_stub_build: <<: *test_template + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" artifacts: when: always paths: @@ -234,6 +263,7 @@ check_stub_build: - pip install -e .[dev] --prefer-binary # libffi (needed for espsecure) version keeps changing in python docker images. Add a symlink to the installed version on Raspberry Pi - if [ $(uname -m) = "armv7l" ]; then ln -sfn /usr/lib/arm-linux-gnueabihf/libffi.so.7.1.0 /usr/lib/arm-linux-gnueabihf/libffi.so.6; fi + - *use_esp_flasher_stub artifacts: reports: junit: test/report.xml @@ -393,6 +423,8 @@ target_esp32p4: PYTEST_ADDOPTS: "-sv --junitxml=test/report.xml --color=yes" PYTHONPATH: "$PYTHONPATH:${CI_PROJECT_DIR}/test" COVERAGE_PROCESS_START: "${CI_PROJECT_DIR}/test/.covconf" + rules: + - if: $CI_USE_ESP_FLASHER_STUB != "1" before_script: - pip install -e .[dev] --prefer-binary artifacts: @@ -458,6 +490,8 @@ build_docs: tags: - build_docs rules: + - if: $CI_PIPELINE_SOURCE == "schedule" && $CI_USE_ESP_FLASHER_STUB == "1" + when: never - changes: - "docs/**/*" - "CONTRIBUTING.rst" @@ -491,7 +525,7 @@ deploy_docs_preview: extends: - .deploy_docs_template rules: - - if: '$CI_COMMIT_REF_NAME == "master"' + - if: $CI_COMMIT_REF_NAME == "master" || ($CI_PIPELINE_SOURCE == "schedule" && $CI_USE_ESP_FLASHER_STUB == "1") when: never - changes: - "docs/**/*" From 92ca47ae1842ad0e2d8b7d8cf7a27e5566d9502f Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Fri, 15 Mar 2024 15:29:11 +0100 Subject: [PATCH 165/209] ci: Remove the deploy_docs_production job from the scheduled pipeline Fixes the "'deploy_docs_production' job needs 'build_docs' job, but 'build_docs' is not in any previous stage" issue. --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0332c0447..2ee9e2795 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -543,7 +543,7 @@ deploy_docs_production: extends: - .deploy_docs_template rules: - - if: '$CI_COMMIT_REF_NAME == "master"' + - if: $CI_COMMIT_REF_NAME == "master" && $CI_USE_ESP_FLASHER_STUB != "1" changes: - "docs/**/*" - "CONTRIBUTING.rst" From 26751c5c013216924d510ab5f2db38d022a046d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Tue, 19 Mar 2024 12:56:06 +0100 Subject: [PATCH 166/209] revert: clear boot control register on ESP32-S3 --- esptool/targets/esp32s3.py | 6 ------ 1 file changed, 6 deletions(-) diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index aa07e20f2..7531f4ae0 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -352,12 +352,6 @@ def hard_reset(self): if uses_usb_otg: self._check_if_can_reset() - # Clear force download boot mode to avoid the chip being stuck in download mode after reset - # workaround for issue: https://github.com/espressif/arduino-esp32/issues/6762 - self.write_reg( - self.RTC_CNTL_OPTION1_REG, 0, self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK - ) - print("Hard resetting via RTS pin...") HardReset(self._port, uses_usb_otg)() From d95ebdf17af36518be2cbda81b351ec94d0de743 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Wed, 20 Mar 2024 09:56:46 +0100 Subject: [PATCH 167/209] feat(esp32s3): clear boot control register on hard reset --- esptool/targets/esp32s3.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 7531f4ae0..04c3c0ef4 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -352,6 +352,16 @@ def hard_reset(self): if uses_usb_otg: self._check_if_can_reset() + try: + # Clear force download boot mode to avoid the chip being stuck in download mode after reset + # workaround for issue: https://github.com/espressif/arduino-esp32/issues/6762 + self.write_reg( + self.RTC_CNTL_OPTION1_REG, 0, self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK + ) + except Exception: + # Skip if response was not valid and proceed to reset; e.g. when monitoring while resetting + pass + print("Hard resetting via RTS pin...") HardReset(self._port, uses_usb_otg)() From 65ab3b8a7545d296032d7fa28eb8695012e0bb82 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Mon, 25 Mar 2024 10:27:06 +0200 Subject: [PATCH 168/209] feat(espefuse): Improves help for burn_efuse cmd Closes https://github.com/espressif/esp-idf/issues/13456 --- espefuse/efuse/base_operations.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/espefuse/efuse/base_operations.py b/espefuse/efuse/base_operations.py index d95b3095b..ccf7efe21 100644 --- a/espefuse/efuse/base_operations.py +++ b/espefuse/efuse/base_operations.py @@ -65,12 +65,11 @@ def check_efuse_name(efuse_name, efuse_list): ) burn.add_argument( "name_value_pairs", - help="Name of efuse register and New value pairs to burn", + help="Name of efuse field and new value pairs to burn. EFUSE_NAME: " + "[{}].".format(", ".join([e.name for e in efuses.efuses])), action=ActionEfuseValuePair, nargs="+", - metavar="[EFUSE_NAME VALUE] [{} VALUE".format( - " VALUE] [".join([e.name for e in efuses.efuses]) - ), + metavar="[EFUSE_NAME VALUE]", efuse_choices=[e.name for e in efuses.efuses] + [name for e in efuses.efuses for name in e.alt_names if name != ""], efuses=efuses, From 6c17499d57c1790cc65407b124ea759abcd9294f Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Fri, 29 Mar 2024 13:26:04 +0300 Subject: [PATCH 169/209] fix(espefuse): Fix burn_key for ECDSA_KEY, it can read pem file --- espefuse/efuse/esp32c5/operations.py | 11 +++++-- espefuse/efuse/esp32c5beta3/operations.py | 11 +++++-- espefuse/efuse/esp32c61/operations.py | 2 +- test/test_espefuse.py | 37 +++++++++++++++++------ 4 files changed, 47 insertions(+), 14 deletions(-) diff --git a/espefuse/efuse/esp32c5/operations.py b/espefuse/efuse/esp32c5/operations.py index 76ac62ef5..1fca6bcb6 100644 --- a/espefuse/efuse/esp32c5/operations.py +++ b/espefuse/efuse/esp32c5/operations.py @@ -236,14 +236,21 @@ def burn_key(esp, efuses, args, digest=None): block = efuses.blocks[block_num] if digest is None: - data = datafile.read() + if keypurpose == "ECDSA_KEY": + sk = espsecure.load_ecdsa_signing_key(datafile) + data = sk.to_string() + if len(data) == 24: + # the private key is 24 bytes long for NIST192p, and 8 bytes of padding + data = b"\x00" * 8 + data + else: + data = datafile.read() else: data = datafile print(" - %s" % (efuse.name), end=" ") revers_msg = None if efuses[block.key_purpose_name].need_reverse(keypurpose): - revers_msg = "\tReversing byte order for AES-XTS hardware peripheral" + revers_msg = f"\tReversing byte order for {keypurpose} hardware peripheral" data = data[::-1] print( "-> [{}]".format( diff --git a/espefuse/efuse/esp32c5beta3/operations.py b/espefuse/efuse/esp32c5beta3/operations.py index 2ee4c24b6..fbd721bd6 100644 --- a/espefuse/efuse/esp32c5beta3/operations.py +++ b/espefuse/efuse/esp32c5beta3/operations.py @@ -236,14 +236,21 @@ def burn_key(esp, efuses, args, digest=None): block = efuses.blocks[block_num] if digest is None: - data = datafile.read() + if keypurpose == "ECDSA_KEY": + sk = espsecure.load_ecdsa_signing_key(datafile) + data = sk.to_string() + if len(data) == 24: + # the private key is 24 bytes long for NIST192p, and 8 bytes of padding + data = b"\x00" * 8 + data + else: + data = datafile.read() else: data = datafile print(" - %s" % (efuse.name), end=" ") revers_msg = None if efuses[block.key_purpose_name].need_reverse(keypurpose): - revers_msg = "\tReversing byte order for AES-XTS hardware peripheral" + revers_msg = f"\tReversing byte order for {keypurpose} hardware peripheral" data = data[::-1] print( "-> [{}]".format( diff --git a/espefuse/efuse/esp32c61/operations.py b/espefuse/efuse/esp32c61/operations.py index b678c2ac8..230656555 100644 --- a/espefuse/efuse/esp32c61/operations.py +++ b/espefuse/efuse/esp32c61/operations.py @@ -304,7 +304,7 @@ def burn_key(esp, efuses, args, digest=None): if digest is None: if keypurpose == "ECDSA_KEY": - sk = espsecure._load_ecdsa_signing_key(datafile) + sk = espsecure.load_ecdsa_signing_key(datafile) data = sk.to_string() if len(data) == 24: # the private key is 24 bytes long for NIST192p, and 8 bytes of padding diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 5824ab56b..78ddffeef 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -902,6 +902,9 @@ def test_burn_key_one_key_block_with_fe_and_sb_keys(self): "esp32c6", "esp32h2", "esp32p4", + "esp32c5", + "esp32c5beta3", + "esp32c61", ], reason="Only chips with 6 keys", ) @@ -910,9 +913,13 @@ def test_burn_key_with_6_keys(self): BLOCK_KEY0 {IMAGES_DIR}/256bit XTS_AES_256_KEY_1 \ BLOCK_KEY1 {IMAGES_DIR}/256bit_1 XTS_AES_256_KEY_2 \ BLOCK_KEY2 {IMAGES_DIR}/256bit_2 XTS_AES_128_KEY" - if arg_chip in ["esp32c3", "esp32c6"] or arg_chip in [ + if arg_chip in [ + "esp32c3", + "esp32c6", "esp32h2", "esp32h2beta1", + "esp32c5", + "esp32c5beta3", ]: cmd = cmd.replace("XTS_AES_256_KEY_1", "XTS_AES_128_KEY") cmd = cmd.replace("XTS_AES_256_KEY_2", "XTS_AES_128_KEY") @@ -986,8 +993,8 @@ def test_burn_key_with_34_coding_scheme(self): self.check_data_block_in_log(output, f"{IMAGES_DIR}/192bit_2") @pytest.mark.skipif( - arg_chip not in ["esp32s2", "esp32s3", "esp32p4"], - reason="512 bit keys are only supported on ESP32-S2, S3, and P4", + arg_chip not in ["esp32s2", "esp32s3", "esp32p4", "esp32c61"], + reason="512 bit keys are only supported on ESP32-S2, S3, P4, C61", ) def test_burn_key_512bit(self): self.espefuse_py( @@ -1004,8 +1011,8 @@ def test_burn_key_512bit(self): ) @pytest.mark.skipif( - arg_chip not in ["esp32s2", "esp32s3", "esp32p4"], - reason="512 bit keys are only supported on ESP32-S2, S3, and P4", + arg_chip not in ["esp32s2", "esp32s3", "esp32p4", "esp32c61"], + reason="512 bit keys are only supported on ESP32-S2, S3, P4, C61", ) def test_burn_key_512bit_non_consecutive_blocks(self): # Burn efuses separately to test different kinds @@ -1047,8 +1054,8 @@ def test_burn_key_512bit_non_consecutive_blocks(self): ) in output @pytest.mark.skipif( - arg_chip not in ["esp32s2", "esp32s3", "esp32p4"], - reason="512 bit keys are only supported on ESP32-S2, S3, and P4", + arg_chip not in ["esp32s2", "esp32s3", "esp32p4", "esp32c61"], + reason="512 bit keys are only supported on ESP32-S2, S3, P4, C61", ) def test_burn_key_512bit_non_consecutive_blocks_loop_around(self): self.espefuse_py( @@ -1080,7 +1087,7 @@ def test_burn_key_512bit_non_consecutive_blocks_loop_around(self): ) in output @pytest.mark.skipif( - arg_chip not in ["esp32h2", "esp32p4"], + arg_chip not in ["esp32h2", "esp32c5", "esp32c5beta3", "esp32c61", "esp32p4"], reason="These chips support ECDSA_KEY", ) def test_burn_key_ecdsa_key(self): @@ -1106,7 +1113,7 @@ def test_burn_key_ecdsa_key(self): ) in output @pytest.mark.skipif( - arg_chip not in ["esp32h2", "esp32p4"], + arg_chip not in ["esp32h2", "esp32c5", "esp32c5beta3", "esp32c61", "esp32p4"], reason="These chips support ECDSA_KEY", ) def test_burn_key_ecdsa_key_check_byte_order(self): @@ -1211,6 +1218,9 @@ def test_burn_block_data_with_1_key_block(self): "esp32c6", "esp32h2", "esp32p4", + "esp32c5", + "esp32c5beta3", + "esp32c61", ], reason="Only chip with 6 keys", ) @@ -1349,6 +1359,9 @@ def test_burn_block_data_with_offset_1_key_block(self): "esp32c6", "esp32h2", "esp32p4", + "esp32c5", + "esp32c5beta3", + "esp32c61", ], reason="Only chips with 6 keys", ) @@ -1545,6 +1558,9 @@ def test_burn_key_from_digest2(self): "esp32c6", "esp32h2", "esp32p4", + "esp32c5", + "esp32c5beta3", + "esp32c61", ], reason="Supports 6 key blocks", ) @@ -1657,6 +1673,9 @@ def test_burn_bit_for_chips_with_1_key_block(self): "esp32c6", "esp32h2", "esp32p4", + "esp32c5", + "esp32c5beta3", + "esp32c61", ], reason="Only chip with 6 keys", ) From dcbfedcae029f357544d28e62191274915aaf817 Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Thu, 4 Apr 2024 16:20:39 +0200 Subject: [PATCH 170/209] ci: Test with latest Python --- .gitlab-ci.yml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2ee9e2795..bae1e5888 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -120,6 +120,19 @@ host_tests: # some .coverage files in sub-directories are not collected on some runners, move them first - find . -mindepth 2 -type f -name ".coverage*" -print -exec mv --backup=numbered {} . \; +host_tests_latest_python: + <<: *host_tests_template + image: python:3.12-bullseye + variables: + PYTEST_ADDOPTS: "-sv --junitxml=test/report.xml --color=yes" + script: + - pytest ${CI_PROJECT_DIR}/test/test_imagegen.py + - pytest ${CI_PROJECT_DIR}/test/test_espsecure.py + - pytest ${CI_PROJECT_DIR}/test/test_merge_bin.py + - pytest ${CI_PROJECT_DIR}/test/test_image_info.py + - pytest ${CI_PROJECT_DIR}/test/test_modules.py + - pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32 + # A new job "host_test_hsm" is created for the test "test_espsecure_hsm.py" which runs an ubuntu image, # because python-pkcs11 (v0.7.0) package is compiled using GLIBC_2.34 but docker image python:3.7-bullseye # support versions only upto GLIBC_2.31. From 5dc7914f361bd01cbfdb8b8d7082d5fdea9d1744 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 5 Apr 2024 09:40:22 +0200 Subject: [PATCH 171/209] ci: add mypy checks to pre-commit --- .mypy.ini | 13 +++++++++++++ .pre-commit-config.yaml | 7 +++++++ 2 files changed, 20 insertions(+) create mode 100644 .mypy.ini diff --git a/.mypy.ini b/.mypy.ini new file mode 100644 index 000000000..d836b95ac --- /dev/null +++ b/.mypy.ini @@ -0,0 +1,13 @@ +[mypy] + # Disallows defining functions with incomplete type annotations + disallow_incomplete_defs = false + # Disallows defining functions without type annotations or with incomplete type annotations + disallow_untyped_defs = false + # Suppress error messages about imports that cannot be resolved + ignore_missing_imports = true + # Specifies the Python version used to parse and check the target program + python_version = 3.9 + # Shows errors for missing return statements on some execution paths + warn_no_return = true + # Shows a warning when returning a value with type Any from a function declared with a non- Any return type + warn_return_any = true diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 464843542..d1286ad0a 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -11,6 +11,13 @@ repos: - id: sphinx-lint name: Lint RST files in docs folder using Sphinx Lint files: ^((docs/en)/.*\.(rst|inc))|CONTRIBUTING.rst$ + - repo: https://github.com/pre-commit/mirrors-mypy + rev: v1.4.1 # the last version running on py3.7 + hooks: + - id: mypy + additional_dependencies: [types-all] + # ignore wrapper scripts because of name colision with efuse/__init__.py etc. + exclude: test/|docs/|espefuse.py|espsecure.py|esptool.py - repo: https://github.com/codespell-project/codespell rev: v2.2.5 hooks: From 6f45b008ceb42771691bdac76eb270cdd76db88d Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 5 Apr 2024 09:41:12 +0200 Subject: [PATCH 172/209] fix: fix type annotation to comply with mypy --- espefuse/efuse/base_fields.py | 5 +++-- espefuse/efuse/esp32c61/mem_definition.py | 3 ++- espefuse/efuse/esp32h2beta1/mem_definition.py | 3 ++- espefuse/efuse/esp32p4/mem_definition.py | 3 ++- espefuse/efuse/mem_definition_base.py | 9 +++++---- esptool/bin_image.py | 4 ++-- esptool/loader.py | 6 +++++- esptool/targets/esp32h2beta1.py | 4 +++- 8 files changed, 24 insertions(+), 13 deletions(-) diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index 4cecd09d2..5dedd9f2b 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -12,6 +12,7 @@ import esptool from . import util +from typing import List class CheckArgValue(object): @@ -441,8 +442,8 @@ class EspEfusesBase(object): """ _esp = None - blocks = [] - efuses = [] + blocks: List[EfuseBlockBase] = [] + efuses: List = [] coding_scheme = None force_write_always = None batch_mode_cnt = 0 diff --git a/espefuse/efuse/esp32c61/mem_definition.py b/espefuse/efuse/esp32c61/mem_definition.py index be9279e3a..94b57b959 100644 --- a/espefuse/efuse/esp32c61/mem_definition.py +++ b/espefuse/efuse/esp32c61/mem_definition.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import os +from typing import List import yaml @@ -119,7 +120,7 @@ def __init__(self) -> None: # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 self.BLOCK2_CALIBRATION_EFUSES = [] - self.CALC = [] + self.CALC: List = [] dir_name = os.path.dirname(os.path.abspath(__file__)) dir_name, file_name = os.path.split(dir_name) diff --git a/espefuse/efuse/esp32h2beta1/mem_definition.py b/espefuse/efuse/esp32h2beta1/mem_definition.py index ee2f00697..8c694306e 100644 --- a/espefuse/efuse/esp32h2beta1/mem_definition.py +++ b/espefuse/efuse/esp32h2beta1/mem_definition.py @@ -9,6 +9,7 @@ import yaml from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase +from typing import List class EfuseDefineRegisters(EfuseRegistersBase): @@ -115,7 +116,7 @@ def __init__(self) -> None: # if BLK_VERSION_MAJOR is 1, these efuse fields are in BLOCK2 self.BLOCK2_CALIBRATION_EFUSES = [] - self.CALC = [] + self.CALC: List = [] dir_name = os.path.dirname(os.path.abspath(__file__)) dir_name, file_name = os.path.split(dir_name) diff --git a/espefuse/efuse/esp32p4/mem_definition.py b/espefuse/efuse/esp32p4/mem_definition.py index 73ab05e28..9d3d2a5b7 100644 --- a/espefuse/efuse/esp32p4/mem_definition.py +++ b/espefuse/efuse/esp32p4/mem_definition.py @@ -13,6 +13,7 @@ EfuseFieldsBase, EfuseRegistersBase, ) +from typing import List class EfuseDefineRegisters(EfuseRegistersBase): @@ -119,7 +120,7 @@ def __init__(self) -> None: # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 self.BLOCK2_CALIBRATION_EFUSES = [] - self.CALC = [] + self.CALC: List = [] dir_name = os.path.dirname(os.path.abspath(__file__)) dir_name, file_name = os.path.split(dir_name) diff --git a/espefuse/efuse/mem_definition_base.py b/espefuse/efuse/mem_definition_base.py index 21ae698b3..434b3a911 100644 --- a/espefuse/efuse/mem_definition_base.py +++ b/espefuse/efuse/mem_definition_base.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later from collections import namedtuple +from typing import Optional, List class EfuseRegistersBase(object): @@ -19,9 +20,9 @@ class EfuseRegistersBase(object): class EfuseBlocksBase(object): - BLOCKS = None + BLOCKS: Optional[List] = None NamedtupleBlock = namedtuple( - "Block", + "NamedtupleBlock", "name alias id rd_addr wr_addr write_disable_bit " "read_disable_bit len key_purpose", ) @@ -49,7 +50,7 @@ class Field: word = None pos = None bit_len = 0 - alt_names = [] + alt_names: List[str] = [] type = "" write_disable_bit = None read_disable_bit = None @@ -61,7 +62,7 @@ class Field: class EfuseFieldsBase(object): def __init__(self, e_desc) -> None: - self.ALL_EFUSES = [] + self.ALL_EFUSES: List = [] def set_category_and_class_type(efuse, name): def includes(name, names): diff --git a/esptool/bin_image.py b/esptool/bin_image.py index a54620200..2bef3b3d2 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -11,7 +11,7 @@ import re import struct import tempfile -from typing import BinaryIO, Optional +from typing import IO, Optional from intelhex import HexRecordError, IntelHex @@ -43,7 +43,7 @@ def align_file_position(f, size): f.seek(align, 1) -def intel_hex_to_bin(file: BinaryIO, start_addr: Optional[int] = None) -> BinaryIO: +def intel_hex_to_bin(file: IO[bytes], start_addr: Optional[int] = None) -> IO[bytes]: """Convert IntelHex file to temp binary file with padding from start_addr If hex file was detected return temp bin file object; input file otherwise""" INTEL_HEX_MAGIC = b":" diff --git a/esptool/loader.py b/esptool/loader.py index 55a941299..af4dc54af 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -13,6 +13,8 @@ import struct import sys import time +from typing import Optional + from .config import load_config_file from .reset import ( @@ -59,7 +61,7 @@ print( "The installed version (%s) of pyserial appears to be too old for esptool.py " "(Python interpreter %s). Check the README for installation instructions." - % (sys.VERSION, sys.executable) + % (serial.VERSION, sys.executable) ) raise except Exception: @@ -185,6 +187,8 @@ class ESPLoader(object): CHIP_NAME = "Espressif device" IS_STUB = False + STUB_CLASS: Optional[object] = None + BOOTLOADER_IMAGE: Optional[object] = None DEFAULT_PORT = "/dev/ttyUSB0" diff --git a/esptool/targets/esp32h2beta1.py b/esptool/targets/esp32h2beta1.py index 49e38e44a..117e5fb6b 100644 --- a/esptool/targets/esp32h2beta1.py +++ b/esptool/targets/esp32h2beta1.py @@ -8,6 +8,8 @@ from .esp32c3 import ESP32C3ROM from ..util import FatalError, NotImplementedInROMError +from typing import List + class ESP32H2BETA1ROM(ESP32C3ROM): CHIP_NAME = "ESP32-H2(beta1)" @@ -66,7 +68,7 @@ class ESP32H2BETA1ROM(ESP32C3ROM): FLASH_ENCRYPTED_WRITE_ALIGN = 16 - MEMORY_MAP = [] + MEMORY_MAP: List = [] FLASH_FREQUENCY = { "48m": 0xF, From 665b2edbf3185dcc565510525ba51ab51f3fc6c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Fri, 5 Apr 2024 14:05:10 +0200 Subject: [PATCH 173/209] ci: Add Secure Download Mode tests --- .gitlab-ci.yml | 7 ++++ CONTRIBUTING.rst | 2 ++ test/test_esptool.py | 6 ++-- test/test_esptool_sdm.py | 69 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 81 insertions(+), 3 deletions(-) create mode 100644 test/test_esptool_sdm.py diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index bae1e5888..3dcc5f068 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -377,6 +377,13 @@ target_esp32s3_jtag_serial: script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32S3_JTAG_SERIAL --preload-port /dev/serial_ports/ESP32S3_PRELOAD --chip esp32s3 --baud 115200 +target_esp32s3_sdm: + extends: .target_esptool_test + tags: + - esptool_esp32s3_sdm_target + script: + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool_sdm.py --port /dev/serial_ports/ESP32S3_SDM --chip esp32s3 --baud 115200 + # ESP32C2 target_esp32c2_40mhz: extends: .target_esptool_test diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index 11ec9aec4..de0ca91ed 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -151,6 +151,8 @@ The following tests are not run automatically by GitHub Actions, because they ne Some tests might fail at higher baud rates on some hardware. +* ``test_esptool_sdm.py`` contains integration tests for ``esptool.py`` with chips in secure download mode. It needs to be run against real Espressif hardware (with active SDM). The command line format is the same as for ``test_esptool.py``. + The following tests are not run automatically by GitHub Actions, but can be run locally in a command line: * ``test_espefuse.py`` tests ``espefuse.py`` functionality. To run it: diff --git a/test/test_esptool.py b/test/test_esptool.py index 5f7975760..438748bb6 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -204,7 +204,7 @@ def run_esptool_process(cmd): print(output) # for more complete stdout logs on failure return output - def run_esptool_error(self, args, baud=None): + def run_esptool_error(self, args, baud=None, chip=None): """ Run esptool.py similar to run_esptool, but expect an error. @@ -212,9 +212,9 @@ def run_esptool_error(self, args, baud=None): and returns the output from esptool.py as a string. """ with pytest.raises(subprocess.CalledProcessError) as fail: - self.run_esptool(args, baud) + self.run_esptool(args, baud, chip) failure = fail.value - assert failure.returncode == 2 # esptool.FatalError return code + assert failure.returncode in [1, 2] # UnsupportedCmdError and FatalError codes return failure.output.decode("utf-8") @classmethod diff --git a/test/test_esptool_sdm.py b/test/test_esptool_sdm.py new file mode 100644 index 000000000..eacf107d5 --- /dev/null +++ b/test/test_esptool_sdm.py @@ -0,0 +1,69 @@ +# Unit tests (really integration tests) for esptool.py using the pytest framework +# Uses a device in the Secure Download Mode connected to the serial port. +# +# RUNNING THIS WILL MESS UP THE DEVICE'S SPI FLASH CONTENTS +# +# How to use: +# +# Run with a physical connection to a chip: +# - `pytest test_esptool_sdm.py --chip esp32 --port /dev/ttyUSB0 --baud 115200` +# +# where - --port - a serial port for esptool.py operation +# - --chip - ESP chip name +# - --baud - baud rate +# - --with-trace - trace all interactions (True or False) + +from test_esptool import EsptoolTestCase, arg_chip, esptool, pytest + + +@pytest.mark.skipif( + arg_chip == "esp8266", reason="ESP8266 does not support Secure Download Mode" +) +class TestSecureDownloadMode(EsptoolTestCase): + expected_chip_name = esptool.util.expand_chip_name(arg_chip) + + def test_auto_detect(self): + output = self.run_esptool_error("flash_id", chip="auto") + + if arg_chip in ["esp32", "esp32s2"]: # no autodetection with get_security_info + assert "Secure Download Mode is enabled" in output + assert "Unsupported detection protocol" in output + else: + assert "Unsupported detection protocol" not in output + assert f"Detecting chip type... {self.expected_chip_name}" in output + assert "Stub loader is not supported in Secure Download Mode" in output + assert ( + f"Chip is {self.expected_chip_name} in Secure Download Mode" in output + ) + + # Commands not supported in SDM + def test_sdm_incompatible_commands(self): + output = self.run_esptool_error("flash_id") # flash_id + assert "This command (0xa) is not supported in Secure Download Mode" in output + + output = self.run_esptool_error("read_flash 0 10 out.bin") # read_flash + assert "This command (0xe) is not supported in Secure Download Mode" in output + + output = self.run_esptool_error("erase_flash") # erase_flash + assert ( + f"{self.expected_chip_name} ROM does not support function erase_flash" + in output + ) + + # Commands supported in SDM + def test_sdm_compatible_commands(self): + output = self.run_esptool("write_flash 0x0 images/one_kb.bin") # write_flash + assert "Security features enabled, so not changing any flash settings" in output + assert "Wrote 1024 bytes" in output + assert "Hash of data verified." not in output # Verification not supported + + output = self.run_esptool_error( + "write_flash --flash_size detect 0x0 images/one_kb.bin" + ) + assert ( + "Detecting flash size is not supported in secure download mode." in output + ) + + if arg_chip != "esp32": # esp32 does not support get_security_info + output = self.run_esptool("get_security_info") # get_security_info + assert "Security Information:" in output From 934d8afd88e54e3465fee1f9a314bef276631312 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Fri, 26 Jan 2024 20:32:09 +0200 Subject: [PATCH 174/209] feat(espefuse): Added check for correctness of written data --- espefuse/efuse/base_fields.py | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index 5dedd9f2b..f0bbbe02f 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -228,13 +228,14 @@ def get_offsets(self): return [self.parent.read_reg(offs) for offs in get_offsets(self)] - def read(self): + def read(self, print_info=True): words = self.get_words() data = BitArray() for word in reversed(words): data.append("uint:32=%d" % word) self.bitarray.overwrite(data, pos=0) - self.print_block(self.bitarray, "read_regs") + if print_info: + self.print_block(self.bitarray, "read_regs") def print_block(self, bit_string, comment, debug=False): if self.parent.debug or debug: @@ -386,6 +387,18 @@ def burn_words(self, words): ) break if not self.fail and self.num_errors == 0: + self.read(print_info=False) + if self.wr_bitarray & self.bitarray != self.wr_bitarray: + # if the required bits are not set then we need to re-burn it again. + if burns < 2: + print( + f"\nRepeat burning BLOCK{self.id} (#{burns + 2}) because not all bits were set" + ) + continue + else: + print( + f"\nAfter {burns + 1} attempts, the required data was not set to BLOCK{self.id}" + ) break def burn(self): From 97b17164c6c18641b1518d38741373b839483676 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Fri, 19 Apr 2024 09:18:29 +0300 Subject: [PATCH 175/209] fix(espefuse): Fix efuse base addr for esp32c5 MP --- espefuse/efuse/esp32c5/mem_definition.py | 2 +- esptool/targets/esp32c5.py | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/espefuse/efuse/esp32c5/mem_definition.py b/espefuse/efuse/esp32c5/mem_definition.py index bb31cad75..9a9212681 100644 --- a/espefuse/efuse/esp32c5/mem_definition.py +++ b/espefuse/efuse/esp32c5/mem_definition.py @@ -20,7 +20,7 @@ class EfuseDefineRegisters(EfuseRegistersBase): EFUSE_MEM_SIZE = 0x01FC + 4 # EFUSE registers & command/conf values - DR_REG_EFUSE_BASE = 0x600B0800 + DR_REG_EFUSE_BASE = 0x600B4800 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8 diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py index d4517af91..fc2db6c0d 100644 --- a/esptool/targets/esp32c5.py +++ b/esptool/targets/esp32c5.py @@ -13,6 +13,8 @@ class ESP32C5ROM(ESP32C6ROM): CHIP_NAME = "ESP32-C5" IMAGE_CHIP_ID = 23 + EFUSE_BASE = 0x600B4800 + IROM_MAP_START = 0x42000000 IROM_MAP_END = 0x42800000 DROM_MAP_START = 0x42800000 From 8c64674c57ec0511796b3c5c0a54d88a8d4ad715 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Mon, 22 Apr 2024 15:28:59 +0200 Subject: [PATCH 176/209] feat(esploader): Enable context manager for esp instances --- esptool/loader.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/esptool/loader.py b/esptool/loader.py index af4dc54af..2b2785db4 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -181,7 +181,8 @@ class ESPLoader(object): Don't instantiate this base class directly, either instantiate a subclass or call cmds.detect_chip() which will interrogate the chip and return the - appropriate subclass instance. + appropriate subclass instance. You can also use a context manager as + "with detect_chip() as esp:" to ensure the serial port is closed when done. """ @@ -281,7 +282,8 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): """Base constructor for ESPLoader bootloader interaction Don't call this constructor, either instantiate a specific - ROM class directly, or use cmds.detect_chip(). + ROM class directly, or use cmds.detect_chip(). You can use the with + statement to ensure the serial port is closed when done. This base class has all of the instance methods for bootloader functionality supported across various chips & stub @@ -365,6 +367,12 @@ def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): # need to set the property back to None or it will continue to fail self._port.write_timeout = None + def __enter__(self): + return self + + def __exit__(self, exc_type, exc_value, traceback): + self._port.close() + @property def serial_port(self): return self._port.port From 51501442be8b392e87a7302c19eca8566de9ed91 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Mon, 22 Apr 2024 14:43:50 +0200 Subject: [PATCH 177/209] feat(espefuse): Allow filtering efuses based on command line arguments --- docs/en/espefuse/summary-cmd.rst | 36 ++++++++++++++- espefuse/efuse/base_operations.py | 74 ++++++++++++++++++++----------- test/test_espefuse.py | 9 ++++ 3 files changed, 92 insertions(+), 27 deletions(-) diff --git a/docs/en/espefuse/summary-cmd.rst b/docs/en/espefuse/summary-cmd.rst index 5e5d46962..195083ebd 100644 --- a/docs/en/espefuse/summary-cmd.rst +++ b/docs/en/espefuse/summary-cmd.rst @@ -3,12 +3,16 @@ Summary ======= -The ``espefuse.py summary`` command reads all eFuses from the chip and outputs them in text or json format. It is also possible to save it to a file. +The ``espefuse.py summary`` command reads the eFuses from the chip and outputs them in text or json format. It is also possible to save it to a file. The command also supports eFuse filtering by name. Optional arguments: -- ``--format`` - Select the summary format: ``summary`` - text format (default option), ``json`` - json format. Usage ``--format json``. +- ``--format`` - Select the summary format: + - ``summary`` - text format (default option). + - ``json`` - json format. Usage ``--format json``. + - ``value_only`` - only the value of the eFuse specified as an argument will be displayed. For more information, refer to the :ref:`Filtering eFuses ` section. - ``--file`` - File to save the efuse summary. Usage ``--file efuses.json``. +- List of eFuses to filter. For more information, refer to the :ref:`Filtering eFuses ` section. Text Format Summary ------------------- @@ -112,3 +116,31 @@ Save Json Format Summary To File === Run "summary" command === Saving efuse values to efuses.json + +.. _filtering-eFuses: + +Filtering Efuses and Displaying Only the Value +---------------------------------------------- + +The ``espefuse.py summary`` command supports filtering eFuses by name. The eFuses to filter needs to be specified as positional arguments. If no eFuses are specified, complete summary will be displayed. Example: + +.. code-block:: none + + > espefuse.py summary ABS_DONE_0 BLOCK1 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Security fuses: + ABS_DONE_0 (BLOCK0) Secure boot V1 is enabled for bootloader image = False R/W (0b0) + BLOCK1 (BLOCK1) Flash encryption key + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + +If ``--format value_only`` is specified, only the value of the eFuse specified as an argument will be displayed. Only one eFuse can be specified as an argument for this format. Example: + +.. code-block:: none + + > espefuse.py summary --format value_only MAC + + === Run "summary" command === + 00:00:00:00:00:00 (CRC 0x00 OK) diff --git a/espefuse/efuse/base_operations.py b/espefuse/efuse/base_operations.py index ccf7efe21..8ee667810 100644 --- a/espefuse/efuse/base_operations.py +++ b/espefuse/efuse/base_operations.py @@ -182,7 +182,7 @@ def check_efuse_name(efuse_name, efuse_list): summary_cmd.add_argument( "--format", help="Select the summary format", - choices=["summary", "json"], + choices=["summary", "json", "value_only"], default="summary", ) summary_cmd.add_argument( @@ -191,6 +191,11 @@ def check_efuse_name(efuse_name, efuse_list): type=argparse.FileType("w"), default=sys.stdout, ) + summary_cmd.add_argument( + "efuses_to_show", + help="The efuses to show. If not provided, all efuses will be shown.", + nargs="*", + ) execute_scripts = subparsers.add_parser( "execute_scripts", help="Executes scripts to burn at one time." @@ -245,14 +250,21 @@ def add_show_sensitive_info_option(p): def summary(esp, efuses, args): - """Print a human-readable summary of efuse contents""" + """Print a human-readable or json summary of efuse contents""" ROW_FORMAT = "%-50s %-50s%s = %s %s %s" - human_output = args.format == "summary" + human_output = args.format in ["summary", "value_only"] + value_only = args.format == "value_only" + if value_only and len(args.efuses_to_show) != 1: + raise esptool.FatalError( + "The 'value_only' format can be used exactly for one efuse." + ) + do_filtering = bool(args.efuses_to_show) json_efuse = {} + summary_efuse = [] if args.file != sys.stdout: print("Saving efuse values to " + args.file.name) - if human_output: - print( + if human_output and not value_only: + summary_efuse.append( ROW_FORMAT.replace("-50", "-12") % ( "EFUSE_NAME (Block)", @@ -261,13 +273,12 @@ def summary(esp, efuses, args): "[Meaningful Value]", "[Readable/Writeable]", "(Hex Value)", - ), - file=args.file, + ) ) - print("-" * 88, file=args.file) + summary_efuse.append("-" * 88) for category in sorted(set(e.category for e in efuses), key=lambda c: c.title()): - if human_output: - print("%s fuses:" % category.title(), file=args.file) + if human_output and not value_only: + summary_efuse.append(f"{category.title()} fuses:") for e in (e for e in efuses if e.category == category): if e.efuse_type.startswith("bytes"): raw = "" @@ -296,8 +307,12 @@ def summary(esp, efuses, args): value = "".join(v) else: value = value.replace("0", "?") - if human_output: - print( + if ( + human_output + and (not do_filtering or e.name in args.efuses_to_show) + and not value_only + ): + summary_efuse.append( ROW_FORMAT % ( e.get_info(), @@ -306,18 +321,20 @@ def summary(esp, efuses, args): value, perms, raw, - ), - file=args.file, + ) ) desc_len = len(e.description[50:]) if desc_len: desc_len += 50 for i in range(50, desc_len, 50): - print( - "%-50s %-50s" % ("", e.description[i : (50 + i)]), - file=args.file, + summary_efuse.append( + f"{'':<50} {e.description[i : (50 + i)]:<50}" ) - if args.format == "json": + elif human_output and value_only and e.name in args.efuses_to_show: + summary_efuse.append(f"{value}") + elif args.format == "json" and ( + not do_filtering or e.name in args.efuses_to_show + ): json_efuse[e.name] = { "name": e.name, "value": base_value if readable else value, @@ -331,19 +348,26 @@ def summary(esp, efuses, args): "efuse_type": e.efuse_type, "bit_len": e.bit_len, } - if human_output: - print("", file=args.file) - if human_output: - print(efuses.summary(), file=args.file) + if human_output and not value_only: + # Remove empty category if efuses are filtered and there are none to show + if do_filtering and summary_efuse[-1] == f"{category.title()} fuses:": + summary_efuse.pop() + else: + summary_efuse.append("") + if human_output and not value_only: + summary_efuse.append(efuses.summary()) warnings = efuses.get_coding_scheme_warnings() if warnings: - print( - "WARNING: Coding scheme has encoding bit error warnings", file=args.file + summary_efuse.append( + "WARNING: Coding scheme has encoding bit error warnings" ) + if human_output: + for line in summary_efuse: + print(line, file=args.file) if args.file != sys.stdout: args.file.close() print("Done") - if args.format == "json": + elif args.format == "json": json.dump(json_efuse, args.file, sort_keys=True, indent=4) print("") diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 78ddffeef..2388dc94f 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -184,6 +184,15 @@ def test_summary(self): def test_summary_json(self): self.espefuse_py("summary --format json") + def test_summary_filter(self): + self.espefuse_py("summary MAC") + self.espefuse_py("summary --format value_only MAC") + self.espefuse_py( + "summary --format value_only MAC WR_DIS", + check_msg="The 'value_only' format can be used exactly for one efuse.", + ret_code=2, + ) + @pytest.mark.skipif( arg_chip == "esp32p4", reason="No Custom MAC Address defined yet" ) From 416dea2b597a44ab12bfbe77fbae1702fd077461 Mon Sep 17 00:00:00 2001 From: Green <77177015+GreenDiscord@users.noreply.github.com> Date: Fri, 26 Apr 2024 17:10:05 +0100 Subject: [PATCH 178/209] docs(flashing): Fixed a typo in /docs/en/esptool/flashing-firmware.rst Updated the text in this file to fix a typo which was decives, that is now devices. --- docs/en/esptool/flashing-firmware.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/en/esptool/flashing-firmware.rst b/docs/en/esptool/flashing-firmware.rst index 6c4276b05..78a6c575d 100644 --- a/docs/en/esptool/flashing-firmware.rst +++ b/docs/en/esptool/flashing-firmware.rst @@ -8,7 +8,7 @@ Flashing Firmware Esptool is used under the hood of many development frameworks for Espressif SoCs, such as `ESP-IDF `_, `Arduino `_, or `PlatformIO `_. After the resulting firmware binary files are compiled, esptool is used to flash these into the device. -Sometimes there might be a need to comfortably flash a bigger amount of decives with the same binaries or to share flashing instructions with a third party. +Sometimes there might be a need to comfortably flash a bigger amount of devices with the same binaries or to share flashing instructions with a third party. It is possible to compile the firmware just once and then repeatedly use esptool (manually or :ref:`in a custom script `) to flash the files. Sharing these instructions and below mentioned assets with a third party (for example a manufacturer) should suffice to allow reproducible and quick flashing of your application into an Espressif chip. From d690a33cfb1803d8602d58c181463b432fce30ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Mon, 29 Apr 2024 12:44:18 +0200 Subject: [PATCH 179/209] ci(hsm_tests): Run tests in a virtual env --- .gitlab-ci.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 3dcc5f068..c8d89690c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -144,8 +144,10 @@ host_tests_hsm: PYTEST_ADDOPTS: "-sv --junitxml=test/report.xml --color=yes" before_script: - apt-get update - - apt-get install -y python3 python3-pip softhsm2 + - apt-get install -y python3 python3-pip python3-venv softhsm2 - ./ci/setup_softhsm2.sh || exit 1 + - python3 -m venv esptoolenv + - source esptoolenv/bin/activate - pip3 install -e .[dev,hsm] --prefer-binary script: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espsecure_hsm.py From b23c15c41498b620aa5e2cf61e35343c7d54e74a Mon Sep 17 00:00:00 2001 From: BoryaGames Date: Fri, 3 May 2024 13:25:25 +0500 Subject: [PATCH 180/209] change(detect_chip): Fixed a spelling mistake Closes https://github.com/espressif/esptool/pull/977 --- esptool/cmds.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 701dc3ea8..7c770e42f 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -116,7 +116,7 @@ def detect_chip( else: err_msg = f"Unexpected chip ID value {chip_id}." except (UnsupportedCommandError, struct.error, FatalError) as e: - # UnsupportedCommmanddError: ESP8266/ESP32 ROM + # UnsupportedCommandError: ESP8266/ESP32 ROM # struct.error: ESP32-S2 # FatalError: ESP8266/ESP32 STUB print(" Unsupported detection protocol, switching and trying again...") From 0fd703a8ef98101c1ea34298673f747eb6823967 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Thu, 25 Apr 2024 10:54:48 +0200 Subject: [PATCH 181/209] feat(write_flash): retry flashing if chip disconnects --- esptool/cmds.py | 130 +++++++++++++++++++++++++++++----------------- esptool/loader.py | 3 ++ 2 files changed, 85 insertions(+), 48 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 7c770e42f..ddf28f9ed 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -13,6 +13,7 @@ import itertools from intelhex import IntelHex +from serial import SerialException from .bin_image import ELFFile, ImageSegment, LoadFirmwareImage from .bin_image import ( @@ -579,56 +580,89 @@ def write_flash(esp, args): if compress: uncimage = image image = zlib.compress(uncimage, 9) - # Decompress the compressed binary a block at a time, - # to dynamically calculate the timeout based on the real write size - decompress = zlib.decompressobj() - blocks = esp.flash_defl_begin(uncsize, len(image), address) - else: - blocks = esp.flash_begin(uncsize, address, begin_rom_encrypted=encrypted) - argfile.seek(0) # in case we need it again - seq = 0 - bytes_sent = 0 # bytes sent on wire - bytes_written = 0 # bytes written to flash - t = time.time() - - timeout = DEFAULT_TIMEOUT - - while len(image) > 0: - print_overwrite( - "Writing at 0x%08x... (%d %%)" - % (address + bytes_written, 100 * (seq + 1) // blocks) - ) - sys.stdout.flush() - block = image[0 : esp.FLASH_WRITE_SIZE] - if compress: - # feeding each compressed block into the decompressor lets us - # see block-by-block how much will be written - block_uncompressed = len(decompress.decompress(block)) - bytes_written += block_uncompressed - block_timeout = max( - DEFAULT_TIMEOUT, - timeout_per_mb(ERASE_WRITE_TIMEOUT_PER_MB, block_uncompressed), - ) - if not esp.IS_STUB: - timeout = ( - block_timeout # ROM code writes block to flash before ACKing + original_image = image # Save the whole image in case retry is needed + # Try again if reconnect was successful + for attempt in range(1, esp.WRITE_FLASH_ATTEMPTS + 1): + try: + if compress: + # Decompress the compressed binary a block at a time, + # to dynamically calculate the timeout based on the real write size + decompress = zlib.decompressobj() + blocks = esp.flash_defl_begin(uncsize, len(image), address) + else: + blocks = esp.flash_begin( + uncsize, address, begin_rom_encrypted=encrypted ) - esp.flash_defl_block(block, seq, timeout=timeout) - if esp.IS_STUB: - # Stub ACKs when block is received, - # then writes to flash while receiving the block after it - timeout = block_timeout - else: - # Pad the last block - block = block + b"\xff" * (esp.FLASH_WRITE_SIZE - len(block)) - if encrypted: - esp.flash_encrypt_block(block, seq) + argfile.seek(0) # in case we need it again + seq = 0 + bytes_sent = 0 # bytes sent on wire + bytes_written = 0 # bytes written to flash + t = time.time() + + timeout = DEFAULT_TIMEOUT + + while len(image) > 0: + print_overwrite( + "Writing at 0x%08x... (%d %%)" + % (address + bytes_written, 100 * (seq + 1) // blocks) + ) + sys.stdout.flush() + block = image[0 : esp.FLASH_WRITE_SIZE] + if compress: + # feeding each compressed block into the decompressor lets us + # see block-by-block how much will be written + block_uncompressed = len(decompress.decompress(block)) + bytes_written += block_uncompressed + block_timeout = max( + DEFAULT_TIMEOUT, + timeout_per_mb( + ERASE_WRITE_TIMEOUT_PER_MB, block_uncompressed + ), + ) + if not esp.IS_STUB: + timeout = block_timeout # ROM code writes block to flash before ACKing + esp.flash_defl_block(block, seq, timeout=timeout) + if esp.IS_STUB: + # Stub ACKs when block is received, + # then writes to flash while receiving the block after it + timeout = block_timeout + else: + # Pad the last block + block = block + b"\xff" * (esp.FLASH_WRITE_SIZE - len(block)) + if encrypted: + esp.flash_encrypt_block(block, seq) + else: + esp.flash_block(block, seq) + bytes_written += len(block) + bytes_sent += len(block) + image = image[esp.FLASH_WRITE_SIZE :] + seq += 1 + break + except SerialException: + if attempt == esp.WRITE_FLASH_ATTEMPTS or encrypted: + # Already retried once or encrypted mode is disabled because of security reasons + raise + print("\nLost connection, retrying...") + esp._port.close() + print("Waiting for the chip to reconnect", end="") + for _ in range(DEFAULT_CONNECT_ATTEMPTS): + try: + time.sleep(1) + esp._port.open() + print() # Print new line which was suppressed by print(".") + esp.connect() + if esp.IS_STUB: + # Hack to bypass the stub overwrite check + esp.IS_STUB = False + # Reflash stub because chip was reset + esp = esp.run_stub() + image = original_image + break + except SerialException: + print(".", end="") + sys.stdout.flush() else: - esp.flash_block(block, seq) - bytes_written += len(block) - bytes_sent += len(block) - image = image[esp.FLASH_WRITE_SIZE :] - seq += 1 + raise # Reconnect limit reached if esp.IS_STUB: # Stub only writes each block to flash after 'ack'ing the receive, diff --git a/esptool/loader.py b/esptool/loader.py index 2b2785db4..8cfc3a43e 100644 --- a/esptool/loader.py +++ b/esptool/loader.py @@ -278,6 +278,9 @@ class ESPLoader(object): # Chip IDs that are no longer supported by esptool UNSUPPORTED_CHIPS = {6: "ESP32-S3(beta 3)"} + # Number of attempts to write flash data + WRITE_FLASH_ATTEMPTS = 2 + def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False): """Base constructor for ESPLoader bootloader interaction From d4e3729fd3cdd6806ef422f4d775cd2997791575 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Fri, 17 May 2024 16:52:09 +0200 Subject: [PATCH 182/209] fix: sort segments if ram_only_header is used There are a few scenarios that segment sorting is required. This is (as for now) a zephyr-case scenario only, where flash section can be created during in-between ram linking. Without segment sorting, flash segments will overlap and ELF won't be created. Signed-off-by: Sylvio Alves --- esptool/bin_image.py | 5 +++++ esptool/cmds.py | 6 ++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 2bef3b3d2..98b8b365c 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -352,6 +352,11 @@ def get_non_irom_segments(self): irom_segment = self.get_irom_segment() return [s for s in self.segments if s != irom_segment] + def sort_segments(self): + if not self.segments: + return # nothing to sort + self.segments = sorted(self.segments, key=lambda s: s.addr) + def merge_adjacent_segments(self): if not self.segments: return # nothing to merge diff --git a/esptool/cmds.py b/esptool/cmds.py index ddf28f9ed..253a4fdb8 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -1039,8 +1039,6 @@ def elf2image(args): args.chip = "esp8266" print("Creating {} image...".format(args.chip)) - if args.ram_only_header: - print("ROM segments hidden - only RAM segments are visible to the ROM loader!") if args.chip != "esp8266": image = CHIP_DEFS[args.chip].BOOTLOADER_IMAGE() @@ -1076,6 +1074,10 @@ def elf2image(args): image.elf_sha256 = e.sha256() image.elf_sha256_offset = args.elf_sha256_offset + if args.ram_only_header: + print("ROM segments hidden - only RAM segments are visible to the ROM loader!") + image.sort_segments() + before = len(image.segments) image.merge_adjacent_segments() if len(image.segments) != before: From 7190ed5015cdb3d5a1ee34cdab583fca8f396d09 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Sun, 19 May 2024 12:36:56 +0200 Subject: [PATCH 183/209] fix: ram_only_header: pad flash segment to next boundary When flash segment does not fit minimum alignment requirement, pad it to next alignment boundary so that the flash placement fits properly. Otherwise ELF won't be created due to wrong alignment. Signed-off-by: Sylvio Alves --- esptool/bin_image.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 98b8b365c..082f4fb01 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -760,8 +760,10 @@ def get_alignment_data_needed(segment): self.ROM_LOADER.BOOTLOADER_FLASH_OFFSET - self.SEG_HEADER_LEN ) if pad_len < align_min: - print("Unable to align the segment!") - break + # in case pad_len does not fit minimum alignment, + # pad it to next aligned boundary + pad_len += self.IROM_ALIGN + pad_len -= self.ROM_LOADER.BOOTLOADER_FLASH_OFFSET pad_segment = ImageSegment(0, b"\x00" * pad_len, f.tell()) self.save_segment(f, pad_segment) From 7b226ed3de8799c7931309303cdb9d3871f310c8 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Mon, 20 May 2024 15:12:23 +0200 Subject: [PATCH 184/209] fix(elf2image): add ELF flags to merge condition Improve the condition upon the segments being merged in the elf2image command. Covering the cases when comparing adjacent segment addresses and types is not enough. Signed-off-by: Marek Matej --- esptool/bin_image.py | 30 ++++++++++++++++++------------ esptool/cmds.py | 4 ++-- test/test_imagegen.py | 4 ++-- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/esptool/bin_image.py b/esptool/bin_image.py index 082f4fb01..bb2d1f031 100644 --- a/esptool/bin_image.py +++ b/esptool/bin_image.py @@ -115,10 +115,11 @@ class ImageSegment(object): """Wrapper class for a segment in an ESP image (very similar to a section in an ELFImage also)""" - def __init__(self, addr, data, file_offs=None): + def __init__(self, addr, data, file_offs=None, flags=0): self.addr = addr self.data = data self.file_offs = file_offs + self.flags = flags self.include_in_checksum = True if self.addr != 0: self.pad_to_alignment( @@ -167,8 +168,8 @@ class ELFSection(ImageSegment): """Wrapper class for a section in an ELF image, has a section name as well as the common properties of an ImageSegment.""" - def __init__(self, name, addr, data): - super(ELFSection, self).__init__(addr, data) + def __init__(self, name, addr, data, flags): + super(ELFSection, self).__init__(addr, data, flags=flags) self.name = name.decode("utf-8") def __repr__(self): @@ -178,6 +179,9 @@ def __repr__(self): class BaseFirmwareImage(object): SEG_HEADER_LEN = 8 SHA256_DIGEST_LEN = 32 + ELF_FLAG_WRITE = 0x1 + ELF_FLAG_READ = 0x2 + ELF_FLAG_EXEC = 0x4 """ Base class with common firmware image functions """ @@ -373,6 +377,8 @@ def merge_adjacent_segments(self): elem.get_memory_type(self) == next_elem.get_memory_type(self), elem.include_in_checksum == next_elem.include_in_checksum, next_elem.addr == elem.addr + len(elem.data), + next_elem.flags & self.ELF_FLAG_EXEC + == elem.flags & self.ELF_FLAG_EXEC, ) ): # Merge any segment that ends where the next one starts, @@ -1276,7 +1282,7 @@ def read_section_header(offs): name_offs, sec_type, _flags, lma, sec_offs, size = struct.unpack_from( " 0 ] self.sections = prog_sections self.nobits_sections = [ - ELFSection(lookup_string(n_offs), lma, b"") - for (n_offs, _type, lma, size, offs) in nobits_secitons + ELFSection(lookup_string(n_offs), lma, b"", flags=_flags) + for (n_offs, _type, lma, size, offs, _flags) in nobits_secitons if lma != 0 and size > 0 ] @@ -1347,7 +1353,7 @@ def read_segment_header(offs): _flags, _align, ) = struct.unpack_from(" 0 ] self.segments = prog_segments diff --git a/esptool/cmds.py b/esptool/cmds.py index 253a4fdb8..b7b483894 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -697,7 +697,7 @@ def write_flash(esp, args): print("Flash md5: %s" % res) print( "MD5 of 0xFF is %s" - % (hashlib.md5(b"\xFF" * uncsize).hexdigest()) + % (hashlib.md5(b"\xff" * uncsize).hexdigest()) ) raise FatalError("MD5 of file does not match data in flash!") else: @@ -1383,7 +1383,7 @@ def merge_bin(args): def pad_to(flash_offs): # account for output file offset if there is any - of.write(b"\xFF" * (flash_offs - args.target_offset - of.tell())) + of.write(b"\xff" * (flash_offs - args.target_offset - of.tell())) for addr, argfile in input_files: pad_to(addr) diff --git a/test/test_imagegen.py b/test/test_imagegen.py index 9ca354260..5dfbce29c 100755 --- a/test/test_imagegen.py +++ b/test/test_imagegen.py @@ -326,8 +326,8 @@ def test_use_segments(self): # this ELF will produce 8 segments in the bin image = self._test_elf2image(ELF, BIN) # Adjacent sections are now merged, len(image.segments) should - # equal 4 (instead of 8). - assert len(image.segments) == 4 + # equal 5 (instead of 8). + assert len(image.segments) == 5 # --use_segments uses ELF segments(phdrs), produces just 2 segments in the bin image = self._test_elf2image(ELF, BIN, ["--use_segments"]) From 4451e2683fd1b6be5f8f4e1e1fb7e2ee688a70a6 Mon Sep 17 00:00:00 2001 From: Tiago Medicci Serrano Date: Tue, 28 May 2024 09:41:01 -0300 Subject: [PATCH 185/209] fix: Do not append SHA256 when `--ram-only-header` When called with `--ram-only-header`, the ROM segments are hidden. In this case, the end of the first two visible segments (in RAM) is not the end of the image and is not suitable for appending the SHA256 digest. --- esptool/__init__.py | 2 +- esptool/cmds.py | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 252f34ace..bc4d102c7 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -496,7 +496,7 @@ def add_spi_flash_subparsers( "quantity. This will make the other segments invisible to the ROM " "loader. Use this argument with care because the ROM loader will load " "only the RAM segments although the other segments being present in " - "the output.", + "the output. Implies --dont-append-digest", action="store_true", default=None, ) diff --git a/esptool/cmds.py b/esptool/cmds.py index b7b483894..4d9975ea4 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -1050,7 +1050,10 @@ def elf2image(args): image.min_rev_full = args.min_rev_full image.max_rev_full = args.max_rev_full image.ram_only_header = args.ram_only_header - image.append_digest = args.append_digest + if image.ram_only_header: + image.append_digest = False + else: + image.append_digest = args.append_digest elif args.version == "1": # ESP8266 image = ESP8266ROMFirmwareImage() elif args.version == "2": @@ -1075,7 +1078,10 @@ def elf2image(args): image.elf_sha256_offset = args.elf_sha256_offset if args.ram_only_header: - print("ROM segments hidden - only RAM segments are visible to the ROM loader!") + print( + "Image has only RAM segments visible. " + "ROM segments are hidden and SHA256 digest is not appended." + ) image.sort_segments() before = len(image.segments) From 40621e2720467a84d90d52b11d77f836fc864cb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Wed, 29 May 2024 15:20:34 +0200 Subject: [PATCH 186/209] docs(troubleshooting): Mention the ESP Hardware Design Guidelines docs --- .github/ISSUE_TEMPLATE/issue-with-hw.yml | 2 +- docs/en/troubleshooting.rst | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/issue-with-hw.yml b/.github/ISSUE_TEMPLATE/issue-with-hw.yml index a2ae0bd70..5fdfcd485 100644 --- a/.github/ISSUE_TEMPLATE/issue-with-hw.yml +++ b/.github/ISSUE_TEMPLATE/issue-with-hw.yml @@ -7,7 +7,7 @@ body: value: | * Most failures to connect, flash, etc. are problems with the hardware. * Please check any guide that came with your hardware, and also check [the esptool troubleshooting guide](https://docs.espressif.com/projects/esptool/en/latest/troubleshooting.html). - * If your board is a custom design, consider using our [free-of-charge schematic and PCB review service](https://www.espressif.com/en/contact-us/circuit-schematic-pcb-design-review). + * If your board is a custom design, check the [ESP Hardware Design Guidelines](https://docs.espressif.com/projects/esp-hardware-design-guidelines/) and consider using our [free-of-charge schematic and PCB review service](https://www.espressif.com/en/contact-us/circuit-schematic-pcb-design-review). * If still experiencing the issue, please provide as many details as possible below about your hardware and computer setup. - type: input id: os diff --git a/docs/en/troubleshooting.rst b/docs/en/troubleshooting.rst index 820bfa297..7db2337bc 100644 --- a/docs/en/troubleshooting.rst +++ b/docs/en/troubleshooting.rst @@ -5,7 +5,9 @@ Troubleshooting =============== -Flashing problems can be fiddly to troubleshoot. Try the suggestions here if you're having problems: +Flashing problems can be fiddly to troubleshoot. The underlying issue can be caused by the drivers, OS, hardware, or even a combination of these. If your board is a custom design, check the `ESP Hardware Design Guidelines `_ or consider using our `free-of-charge schematic and PCB review service `_. + +Try the following suggestions if your issues persist: Bootloader Won't Respond ------------------------ From e49137875a9147e9ecb2f00152486460d5dd8fc5 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Mon, 27 May 2024 11:36:04 +0530 Subject: [PATCH 187/209] feat(espsecure): Add support for secure boot v2 using ECDSA-P384 signatures --- espsecure/__init__.py | 217 ++++++++++++++++++++++++++++-------------- 1 file changed, 147 insertions(+), 70 deletions(-) diff --git a/espsecure/__init__.py b/espsecure/__init__.py index c6b44f941..fa0c258b6 100755 --- a/espsecure/__init__.py +++ b/espsecure/__init__.py @@ -31,9 +31,14 @@ SIG_BLOCK_VERSION_RSA = 0x02 SIG_BLOCK_VERSION_ECDSA = 0x03 +# SHA scheme used in Secure Boot V2 ECDSA signature blocks +ECDSA_SHA_256 = 0x0 +ECDSA_SHA_384 = 0x1 + # Curve IDs used in Secure Boot V2 ECDSA signature blocks CURVE_ID_P192 = 1 CURVE_ID_P256 = 2 +CURVE_ID_P384 = 3 SECTOR_SIZE = 4096 SIG_BLOCK_SIZE = ( @@ -182,23 +187,21 @@ def generate_signing_key(args): ) with open(args.keyfile, "wb") as f: f.write(private_key) - print("RSA 3072 private key in PEM format written to %s" % args.keyfile) + print(f"RSA 3072 private key in PEM format written to {args.keyfile}") elif args.scheme == "ecdsa192": """Generate a ECDSA 192 signing key for signing secure boot images""" _generate_ecdsa_signing_key(ecdsa.NIST192p, args.keyfile) - print( - "ECDSA NIST192p private key in PEM format written to %s" % args.keyfile - ) + print(f"ECDSA NIST192p private key in PEM format written to {args.keyfile}") elif args.scheme == "ecdsa256": """Generate a ECDSA 256 signing key for signing secure boot images""" _generate_ecdsa_signing_key(ecdsa.NIST256p, args.keyfile) - print( - "ECDSA NIST256p private key in PEM format written to %s" % args.keyfile - ) + print(f"ECDSA NIST256p private key in PEM format written to {args.keyfile}") + elif args.scheme == "ecdsa384": + """Generate a ECDSA 384 signing key for signing secure boot images""" + _generate_ecdsa_signing_key(ecdsa.NIST384p, args.keyfile) + print(f"ECDSA NIST384p private key in PEM format written to {args.keyfile}") else: - raise esptool.FatalError( - "ERROR: Unsupported signing scheme (%s)" % args.scheme - ) + raise esptool.FatalError("ERROR: Unsupported signing scheme {args.scheme}") def load_ecdsa_signing_key(keyfile): @@ -260,12 +263,10 @@ def _load_sbv2_signing_key(keydata): ) return sk if isinstance(sk, ec.EllipticCurvePrivateKey): - if not ( - isinstance(sk.curve, ec.SECP192R1) or isinstance(sk.curve, ec.SECP256R1) - ): + if not isinstance(sk.curve, (ec.SECP192R1, ec.SECP256R1, ec.SECP384R1)): raise esptool.FatalError( "Key file uses incorrect curve. Secure Boot V2 + ECDSA only supports " - "NIST192p, NIST256p (aka prime192v1, prime256v1)" + "NIST192p, NIST256p, NIST384p (aka prime192v1 / secp192r1, prime256v1 / secp256r1, secp384r1)" ) return sk @@ -285,12 +286,10 @@ def _load_sbv2_pub_key(keydata): ) return vk if isinstance(vk, ec.EllipticCurvePublicKey): - if not ( - isinstance(vk.curve, ec.SECP192R1) or isinstance(vk.curve, ec.SECP256R1) - ): + if not isinstance(vk.curve, (ec.SECP192R1, ec.SECP256R1, ec.SECP384R1)): raise esptool.FatalError( "Key file uses incorrect curve. Secure Boot V2 + ECDSA only supports " - "NIST192p, NIST256p (aka prime192v1, prime256v1)" + "NIST192p, NIST256p, NIST384p (aka prime192v1 / secp192r1, prime256v1 / secp256r1, secp384r1)" ) return vk @@ -338,7 +337,7 @@ def _microecc_format(a, b, curve_len): """ byte_len = int(curve_len / 8) ab = int_to_bytes(a, byte_len)[::-1] + int_to_bytes(b, byte_len)[::-1] - assert len(ab) == 48 or len(ab) == 64 + assert len(ab) in [48, 64, 96] return ab @@ -402,7 +401,7 @@ def sign_secure_boot_v1(args): def sign_secure_boot_v2(args): """ Sign a firmware app image with an RSA private key using RSA-PSS, - or ECDSA private key using P192 or P256. + or ECDSA private key using P192 or P256 or P384. Write output file with a Secure Boot V2 header appended. """ @@ -496,20 +495,16 @@ def sign_secure_boot_v2(args): ) print(f"{key_count} signing key(s) found.") - # Calculate digest of data file - digest = hashlib.sha256() - digest.update(contents) - digest = digest.digest() # Generate signature block using pre-calculated signatures if signature: signature_block = generate_signature_block_using_pre_calculated_signature( - signature, pub_key, digest + signature, pub_key, contents ) # Generate signature block by signing using private keys else: signature_block = generate_signature_block_using_private_key( - args.keyfile, digest + args.keyfile, contents ) if signature_block is None or len(signature_block) == 0: @@ -560,13 +555,17 @@ def generate_signature_using_hsm(config, contents): return [temp_signature_file] -def generate_signature_block_using_pre_calculated_signature(signature, pub_key, digest): +def generate_signature_block_using_pre_calculated_signature( + signature, pub_key, contents +): signature_blocks = b"" for sig, pk in zip(signature, pub_key): try: public_key = _get_sbv2_pub_key(pk) signature = sig.read() if isinstance(public_key, rsa.RSAPublicKey): + # Calculate digest of data file + digest = _sha256_digest(contents) # RSA signature rsa_primitives = _get_sbv2_rsa_primitives(public_key) # Verify the signature @@ -586,15 +585,24 @@ def generate_signature_block_using_pre_calculated_signature(signature, pub_key, if isinstance(numbers.curve, ec.SECP192R1): curve_len = 192 curve_id = CURVE_ID_P192 + hash_type = hashes.SHA256() + digest = _sha256_digest(contents) elif isinstance(numbers.curve, ec.SECP256R1): curve_len = 256 curve_id = CURVE_ID_P256 + hash_type = hashes.SHA256() + digest = _sha256_digest(contents) + elif isinstance(numbers.curve, ec.SECP384R1): + curve_len = 384 + curve_id = CURVE_ID_P384 + hash_type = hashes.SHA384() + digest = _sha384_digest(contents) else: raise esptool.FatalError("Invalid ECDSA curve instance.") # Verify the signature public_key.verify( - signature, digest, ec.ECDSA(utils.Prehashed(hashes.SHA256())) + signature, digest, ec.ECDSA(utils.Prehashed(hash_type)) ) pubkey_point = _microecc_format(numbers.x, numbers.y, curve_len) @@ -619,13 +627,14 @@ def generate_signature_block_using_pre_calculated_signature(signature, pub_key, return signature_blocks -def generate_signature_block_using_private_key(keyfiles, digest): +def generate_signature_block_using_private_key(keyfiles, contents): signature_blocks = b"" for keyfile in keyfiles: private_key = _load_sbv2_signing_key(keyfile.read()) # Sign if isinstance(private_key, rsa.RSAPrivateKey): + digest = _sha256_digest(contents) # RSA signature signature = private_key.sign( digest, @@ -640,21 +649,28 @@ def generate_signature_block_using_private_key(keyfiles, digest): digest, rsa_primitives, signature ) else: - # ECDSA signature - signature = private_key.sign( - digest, ec.ECDSA(utils.Prehashed(hashes.SHA256())) - ) - numbers = private_key.public_key().public_numbers() if isinstance(private_key.curve, ec.SECP192R1): curve_len = 192 curve_id = CURVE_ID_P192 + hash_type = hashes.SHA256() + digest = _sha256_digest(contents) elif isinstance(numbers.curve, ec.SECP256R1): curve_len = 256 curve_id = CURVE_ID_P256 + hash_type = hashes.SHA256() + digest = _sha256_digest(contents) + elif isinstance(numbers.curve, ec.SECP384R1): + curve_len = 384 + curve_id = CURVE_ID_P384 + hash_type = hashes.SHA384() + digest = _sha384_digest(contents) else: raise esptool.FatalError("Invalid ECDSA curve instance.") + # ECDSA signatures + signature = private_key.sign(digest, ec.ECDSA(utils.Prehashed(hash_type))) + pubkey_point = _microecc_format(numbers.x, numbers.y, curve_len) r, s = utils.decode_dss_signature(signature) @@ -703,15 +719,34 @@ def generate_ecdsa_signature_block(digest, curve_id, pubkey_point, signature_rs) # block is padded out to the much larger size # of the RSA version of this structure """ - signature_block = struct.pack( - " Date: Mon, 27 May 2024 11:36:57 +0530 Subject: [PATCH 188/209] ci(espsecure): Add tests for secure boot using ECDSA-P384 curve --- .../bootloader_signed_v2_ecdsa384.bin | Bin 0 -> 36864 bytes .../ecdsa384_secure_boot_signing_key.pem | 5 ++ .../ecdsa384_secure_boot_signing_key2.pem | 5 ++ .../ecdsa384_secure_boot_signing_pubkey.pem | 5 ++ .../ecdsa384_secure_boot_signing_pubkey2.pem | 5 ++ ...lculated_bootloader_signature_ecdsa384.bin | Bin 0 -> 104 bytes test/test_espsecure.py | 49 +++++++++++++++++- 7 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 test/secure_images/bootloader_signed_v2_ecdsa384.bin create mode 100644 test/secure_images/ecdsa384_secure_boot_signing_key.pem create mode 100644 test/secure_images/ecdsa384_secure_boot_signing_key2.pem create mode 100644 test/secure_images/ecdsa384_secure_boot_signing_pubkey.pem create mode 100644 test/secure_images/ecdsa384_secure_boot_signing_pubkey2.pem create mode 100644 test/secure_images/pre_calculated_bootloader_signature_ecdsa384.bin diff --git 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KEY----- +MIGkAgEBBDBIxytBXMNRUK/28IbGjtIOfZTLrcKU8nk0zT966n0c1kFa0VdK84k0/lxnX1ukymWg +BwYFK4EEACKhZANiAAQohLsM+b3/8g4A4q85TpbrVb7Z+CCkDOL90FzceloEFPY9Qt+IoIMmqxvx +0Uiz9t81CHE3+eVwoVLh7OepMJJ/lRX7leY6gLtnNYxPPpamrROAJ9BgakZ+VE9tYBlK3AY= +-----END EC PRIVATE KEY----- diff --git a/test/secure_images/ecdsa384_secure_boot_signing_key2.pem b/test/secure_images/ecdsa384_secure_boot_signing_key2.pem new file mode 100644 index 000000000..e16a09191 --- /dev/null +++ b/test/secure_images/ecdsa384_secure_boot_signing_key2.pem @@ -0,0 +1,5 @@ +-----BEGIN EC PRIVATE KEY----- +MIGkAgEBBDAi/QEI621c5gFBaHyZ3JyrCXQYy5umeENn7dfHXxyM6CIKLFXWXrHOJ+xPEAvKEnqg +BwYFK4EEACKhZANiAATQJep17Gl/ukPYPaoeau5WlspgrnT7pNqkq/TyJH5NYPZfuGFDzAxxaPl4 +PEbHAazkDNvziUUeI+CkF/M17chj7YyOFFdAJN+I+Qn38bS/yZiYVzOocGXeLWhZks3+wME= +-----END EC PRIVATE KEY----- diff --git a/test/secure_images/ecdsa384_secure_boot_signing_pubkey.pem b/test/secure_images/ecdsa384_secure_boot_signing_pubkey.pem new file mode 100644 index 000000000..6aa54bb79 --- /dev/null +++ b/test/secure_images/ecdsa384_secure_boot_signing_pubkey.pem @@ -0,0 +1,5 @@ +-----BEGIN PUBLIC KEY----- +MHYwEAYHKoZIzj0CAQYFK4EEACIDYgAEKIS7DPm9//IOAOKvOU6W61W+2fggpAzi +/dBc3HpaBBT2PULfiKCDJqsb8dFIs/bfNQhxN/nlcKFS4eznqTCSf5UV+5XmOoC7 +ZzWMTz6Wpq0TgCfQYGpGflRPbWAZStwG +-----END PUBLIC KEY----- diff --git a/test/secure_images/ecdsa384_secure_boot_signing_pubkey2.pem b/test/secure_images/ecdsa384_secure_boot_signing_pubkey2.pem new file mode 100644 index 000000000..5d1f86ed7 --- /dev/null +++ b/test/secure_images/ecdsa384_secure_boot_signing_pubkey2.pem @@ -0,0 +1,5 @@ +-----BEGIN PUBLIC KEY----- +MHYwEAYHKoZIzj0CAQYFK4EEACIDYgAE0CXqdexpf7pD2D2qHmruVpbKYK50+6Ta +pKv08iR+TWD2X7hhQ8wMcWj5eDxGxwGs5Azb84lFHiPgpBfzNe3IY+2MjhRXQCTf +iPkJ9/G0v8mYmFczqHBl3i1oWZLN/sDB +-----END PUBLIC KEY----- diff --git a/test/secure_images/pre_calculated_bootloader_signature_ecdsa384.bin b/test/secure_images/pre_calculated_bootloader_signature_ecdsa384.bin new file mode 100644 index 0000000000000000000000000000000000000000..268666c87017be45b65d15da03f85b7455b59f3c GIT binary patch literal 104 zcmV-u0GIzTW&$w)n@Mf1{ literal 0 HcmV?d00001 diff --git a/test/test_espsecure.py b/test/test_espsecure.py index 90045ff40..6fc2cb319 100755 --- a/test/test_espsecure.py +++ b/test/test_espsecure.py @@ -211,6 +211,7 @@ def test_sign_v2_data(self): "rsa_secure_boot_signing_key.pem", "ecdsa192_secure_boot_signing_key.pem", "ecdsa_secure_boot_signing_key.pem", + "ecdsa384_secure_boot_signing_key.pem", ] for key in signing_keys: try: @@ -411,11 +412,13 @@ def test_sign_v2_with_pre_calculated_signature(self): "rsa_secure_boot_signing_pubkey.pem", "ecdsa192_secure_boot_signing_pubkey.pem", "ecdsa_secure_boot_signing_pubkey.pem", + "ecdsa384_secure_boot_signing_pubkey.pem", ] pre_calculated_signatures = [ "pre_calculated_bootloader_signature_rsa.bin", "pre_calculated_bootloader_signature_ecdsa192.bin", "pre_calculated_bootloader_signature_ecdsa256.bin", + "pre_calculated_bootloader_signature_ecdsa384.bin", ] for pub_key, signature in zip(signing_keys, pre_calculated_signatures): try: @@ -497,6 +500,16 @@ def test_verify_signature_signing_key(self): ) espsecure.verify_signature(args) + # correct key v2 (ecdsa384) + args = self.VerifyArgs( + "2", + False, + None, + self._open("ecdsa384_secure_boot_signing_key.pem"), + self._open("bootloader_signed_v2_ecdsa384.bin"), + ) + espsecure.verify_signature(args) + # correct key v2 (ecdsa256) args = self.VerifyArgs( "2", @@ -553,6 +566,18 @@ def test_verify_signature_signing_key(self): espsecure.verify_signature(args) assert "Invalid datafile" in str(cm.value) + # wrong key v2 (ecdsa384) + args = self.VerifyArgs( + "2", + False, + None, + self._open("ecdsa384_secure_boot_signing_key2.pem"), + self._open("bootloader_signed_v2_ecdsa384.bin"), + ) + with pytest.raises(esptool.FatalError) as cm: + espsecure.verify_signature(args) + assert "Signature could not be verified with the provided key." in str(cm.value) + # wrong key v2 (ecdsa256) args = self.VerifyArgs( "2", @@ -610,6 +635,16 @@ def test_verify_signature_public_key(self): ) espsecure.verify_signature(args) + # correct key v2 (ecdsa384) + args = self.VerifyArgs( + "2", + False, + None, + self._open("ecdsa384_secure_boot_signing_pubkey.pem"), + self._open("bootloader_signed_v2_ecdsa384.bin"), + ) + espsecure.verify_signature(args) + # correct key v2 (ecdsa256) args = self.VerifyArgs( "2", @@ -654,6 +689,18 @@ def test_verify_signature_public_key(self): espsecure.verify_signature(args) assert "Signature could not be verified with the provided key." in str(cm.value) + # wrong key v2 (ecdsa384) + args = self.VerifyArgs( + "2", + False, + None, + self._open("ecdsa384_secure_boot_signing_pubkey2.pem"), + self._open("bootloader_signed_v2_ecdsa384.bin"), + ) + with pytest.raises(esptool.FatalError) as cm: + espsecure.verify_signature(args) + assert "Signature could not be verified with the provided key." in str(cm.value) + # wrong key v2 (ecdsa256) args = self.VerifyArgs( "2", @@ -728,7 +775,7 @@ def test_generate_and_extract_key_v2(self): # We need to manually delete the keyfile as we are iterating over # different schemes with the same keyfile so instead of using addCleanup, # we remove it using os.remove at the end of each pass - for scheme in ["rsa3072", "ecdsa192", "ecdsa256"]: + for scheme in ["rsa3072", "ecdsa192", "ecdsa256", "ecdsa384"]: args = self.GenerateKeyArgs("2", scheme, keyfile_name) espsecure.generate_signing_key(args) From 9bff02c313ddf192d65cba85f025e8613b21c76c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Wed, 5 Jun 2024 16:03:21 +0200 Subject: [PATCH 189/209] feat(esp32-p4): Add ECO1 magic number --- esptool/targets/esp32p4.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index 0d3c54793..fc5c9e4c8 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -21,7 +21,7 @@ class ESP32P4ROM(ESP32ROM): BOOTLOADER_FLASH_OFFSET = 0x2000 # First 2 sectors are reserved for FE purposes - CHIP_DETECT_MAGIC_VALUE = [0x0] + CHIP_DETECT_MAGIC_VALUE = [0x0, 0x0ADDBAD0] UART_DATE_REG_ADDR = 0x500CA000 + 0x8C From ea4c69e1efe6ee54cae12e42edca54d73141d023 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Thu, 6 Jun 2024 14:08:34 +0200 Subject: [PATCH 190/209] fix(espefuse): Use stub class if stub flasher is running Closes https://github.com/espressif/esptool/issues/982 --- espefuse/__init__.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/espefuse/__init__.py b/espefuse/__init__.py index 1bada3e7e..a2d4df0e4 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -94,6 +94,8 @@ def get_esp( ) if not skip_connect: esp.connect(connect_mode) + if esp.sync_stub_detected: + esp = esp.STUB_CLASS(esp) return esp From 2579e127f8ee2f84da01d0cf78dd2c1ee54ea083 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Thu, 23 May 2024 09:59:13 +1000 Subject: [PATCH 191/209] feat(reset): Automatically reconnect if port disconnects during reset Closes https://github.com/espressif/esptool/pull/980 --- esptool/reset.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/esptool/reset.py b/esptool/reset.py index 6223b5d98..dcfd2977e 100644 --- a/esptool/reset.py +++ b/esptool/reset.py @@ -26,6 +26,31 @@ DEFAULT_RESET_DELAY = 0.05 # default time to wait before releasing boot pin after reset +def reconnect(f): + def wrapper(*args): + """ + On targets with native USB, the reset process can cause the port to + disconnect / reconnect during reset. + This will retry reconnections for up to 10 seconds on ports that drop + out during the RTS/DTS reset process. + """ + self = args[0] + for retry in reversed(range(20)): + try: + if not self.port.isOpen(): + self.port.open() + ret = f(*args) + break + except OSError: + if not retry: + raise + self.port.close() + time.sleep(0.5) + return ret + + return wrapper + + class ResetStrategy(object): print_once = PrintOnce() @@ -51,9 +76,11 @@ def __call__(self): def reset(self): pass + @reconnect def _setDTR(self, state): self.port.setDTR(state) + @reconnect def _setRTS(self, state): self.port.setRTS(state) # Work-around for adapters on Windows using the usbser.sys driver: @@ -61,6 +88,7 @@ def _setRTS(self, state): # request is sent with the updated RTS state and the same DTR state self.port.setDTR(self.port.dtr) + @reconnect def _setDTRandRTS(self, dtr=False, rts=False): status = struct.unpack( "I", fcntl.ioctl(self.port.fileno(), TIOCMGET, struct.pack("I", 0)) From 69b8ffab7966052f7135252254c0147b6011cc2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Thu, 13 Jun 2024 14:09:00 +0200 Subject: [PATCH 192/209] feat(reset): Apply recconections to the whole reset sequence, not line transitions --- esptool/reset.py | 63 ++++++++++++++++++------------------------------ 1 file changed, 24 insertions(+), 39 deletions(-) diff --git a/esptool/reset.py b/esptool/reset.py index dcfd2977e..edf3b13b0 100644 --- a/esptool/reset.py +++ b/esptool/reset.py @@ -26,61 +26,47 @@ DEFAULT_RESET_DELAY = 0.05 # default time to wait before releasing boot pin after reset -def reconnect(f): - def wrapper(*args): +class ResetStrategy(object): + print_once = PrintOnce() + + def __init__(self, port, reset_delay=DEFAULT_RESET_DELAY): + self.port = port + self.reset_delay = reset_delay + + def __call__(self): """ - On targets with native USB, the reset process can cause the port to + On targets with USB modes, the reset process can cause the port to disconnect / reconnect during reset. - This will retry reconnections for up to 10 seconds on ports that drop - out during the RTS/DTS reset process. + This will retry reconnections on ports that + drop out during the reset sequence. """ - self = args[0] - for retry in reversed(range(20)): + for retry in reversed(range(3)): try: if not self.port.isOpen(): self.port.open() - ret = f(*args) + self.reset() break - except OSError: - if not retry: + except OSError as e: + # ENOTTY for TIOCMSET; EINVAL for TIOCMGET + if e.errno in [errno.ENOTTY, errno.EINVAL]: + self.print_once( + "WARNING: Chip was NOT reset. Setting RTS/DTR lines is not " + f"supported for port '{self.port.name}'. Set --before and --after " + "arguments to 'no_reset' and switch to bootloader manually to " + "avoid this warning." + ) + break + elif not retry: raise self.port.close() time.sleep(0.5) - return ret - - return wrapper - - -class ResetStrategy(object): - print_once = PrintOnce() - - def __init__(self, port, reset_delay=DEFAULT_RESET_DELAY): - self.port = port - self.reset_delay = reset_delay - - def __call__(self): - try: - self.reset() - except OSError as e: - # ENOTTY for TIOCMSET; EINVAL for TIOCMGET - if e.errno in [errno.ENOTTY, errno.EINVAL]: - self.print_once( - "WARNING: Chip was NOT reset. Setting RTS/DTR lines is not " - f"supported for port '{self.port.name}'. Set --before and --after " - "arguments to 'no_reset' and switch to bootloader manually to " - "avoid this warning." - ) - else: - raise def reset(self): pass - @reconnect def _setDTR(self, state): self.port.setDTR(state) - @reconnect def _setRTS(self, state): self.port.setRTS(state) # Work-around for adapters on Windows using the usbser.sys driver: @@ -88,7 +74,6 @@ def _setRTS(self, state): # request is sent with the updated RTS state and the same DTR state self.port.setDTR(self.port.dtr) - @reconnect def _setDTRandRTS(self, dtr=False, rts=False): status = struct.unpack( "I", fcntl.ioctl(self.port.fileno(), TIOCMGET, struct.pack("I", 0)) From 92e1b3a6541a56215f6858c753cda4eb98e6f363 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 7 Jun 2024 15:15:42 +0800 Subject: [PATCH 193/209] fix(esp32-c5): Use a longer reset delay with usb-serial/jtag to stabilize boot-up --- esptool/reset.py | 6 +++--- esptool/targets/esp32c5.py | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/esptool/reset.py b/esptool/reset.py index edf3b13b0..ef91e4bdc 100644 --- a/esptool/reset.py +++ b/esptool/reset.py @@ -148,13 +148,13 @@ class HardReset(ResetStrategy): Can be used to reset out of the bootloader or to restart a running app. """ - def __init__(self, port, uses_usb_otg=False): + def __init__(self, port, uses_usb=False): super().__init__(port) - self.uses_usb_otg = uses_usb_otg + self.uses_usb = uses_usb def reset(self): self._setRTS(True) # EN->LOW - if self.uses_usb_otg: + if self.uses_usb: # Give the chip some time to come out of reset, # to be able to handle further DTR/RTS transitions time.sleep(0.2) diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py index fc2db6c0d..51d52effd 100644 --- a/esptool/targets/esp32c5.py +++ b/esptool/targets/esp32c5.py @@ -7,6 +7,7 @@ from .esp32c6 import ESP32C6ROM from ..loader import ESPLoader +from ..reset import HardReset class ESP32C5ROM(ESP32C6ROM): @@ -24,6 +25,8 @@ class ESP32C5ROM(ESP32C6ROM): PCR_SYSCLK_XTAL_FREQ_V = 0x7F << 24 PCR_SYSCLK_XTAL_FREQ_S = 24 + UARTDEV_BUF_NO = 0x4085F51C # Variable in ROM .bss which indicates the port in use + # Magic value for ESP32C5 CHIP_DETECT_MAGIC_VALUE = [0x8082C5DC] @@ -67,6 +70,10 @@ def get_crystal_freq_rom_expect(self): self.read_reg(self.PCR_SYSCLK_CONF_REG) & self.PCR_SYSCLK_XTAL_FREQ_V ) >> self.PCR_SYSCLK_XTAL_FREQ_S + def hard_reset(self): + print("Hard resetting via RTS pin...") + HardReset(self._port, self.uses_usb_jtag_serial())() + def change_baud(self, baud): if not self.IS_STUB: crystal_freq_rom_expect = self.get_crystal_freq_rom_expect() From 3c2c60b1da272615bac382bcd03bb301ca44bbb6 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 13 Jun 2024 20:09:55 +0300 Subject: [PATCH 194/209] feat(espefuse): Adds incompatible eFuse settings check for S3 --- docs/en/espefuse/burn-efuse-cmd.rst | 4 ++++ espefuse/efuse/base_fields.py | 4 ++++ espefuse/efuse/base_operations.py | 13 +++++++++++++ espefuse/efuse/esp32s3/fields.py | 22 ++++++++++++++++++++++ espefuse/efuse/esp32s3beta2/fields.py | 22 ++++++++++++++++++++++ test/test_espefuse.py | 18 ++++++++++++++++++ 6 files changed, 83 insertions(+) diff --git a/docs/en/espefuse/burn-efuse-cmd.rst b/docs/en/espefuse/burn-efuse-cmd.rst index b5d974316..4d6446d9c 100644 --- a/docs/en/espefuse/burn-efuse-cmd.rst +++ b/docs/en/espefuse/burn-efuse-cmd.rst @@ -10,6 +10,10 @@ Positional arguments: - ``eFuse name`` - ``value`` +Optional arguments: + +* ``--force``. Suppress an error to burn eFuses. The tool checks for incompatible eFuse states to prevent them from burning and potentially **bricking the chip**. Use this flag only if you are sure. This will suppress the eFuse incompatibility error. + It can be list of eFuse names and values (like EFUSE_NAME1 1 EFUSE_NAME2 7 EFUSE_NAME3 10 etc.). New values can be a numeric value in decimal or hex (with "0x" prefix). eFuse bits can only be burned from 0 to 1, attempting to set any back to 0 will have no effect. Most eFuses have a limited bit width (many are only 1-bit flags). Longer eFuses (MAC addresses, keys) can be set with this command, but it's better to use a specific command (``burn_custom_mac``, ``burn_key``) for a specific field. diff --git a/espefuse/efuse/base_fields.py b/espefuse/efuse/base_fields.py index f0bbbe02f..654d0fd66 100644 --- a/espefuse/efuse/base_fields.py +++ b/espefuse/efuse/base_fields.py @@ -649,6 +649,10 @@ def get_block_errors(self, block_num): """Returns (error count, failure boolean flag)""" return self.blocks[block_num].num_errors, self.blocks[block_num].fail + def is_efuses_incompatible_for_burn(self): + # Overwrite this function for a specific target if you want to check if a certain eFuse(s) can be burned. + return False + class EfuseFieldBase(EfuseProtectBase): def __init__(self, parent, param): diff --git a/espefuse/efuse/base_operations.py b/espefuse/efuse/base_operations.py index 8ee667810..42a7c9abc 100644 --- a/espefuse/efuse/base_operations.py +++ b/espefuse/efuse/base_operations.py @@ -74,6 +74,11 @@ def check_efuse_name(efuse_name, efuse_list): + [name for e in efuses.efuses for name in e.alt_names if name != ""], efuses=efuses, ) + burn.add_argument( + "--force", + help="Suppress an error to burn eFuses", + action="store_true", + ) read_protect_efuse = subparsers.add_parser( "read_protect_efuse", @@ -480,6 +485,14 @@ def print_attention(blocked_efuses_after_burn): ) print(" espefuse/esptool will not work.") + if efuses.is_efuses_incompatible_for_burn(): + if args.force: + print("Ignore incompatible eFuse settings.") + else: + raise esptool.FatalError( + "Incompatible eFuse settings detected, abort. (use --force flag to skip it)." + ) + if not efuses.burn_all(check_batch_mode=True): return diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index 7cd8cd952..bbf08a37e 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -296,6 +296,28 @@ def summary(self): output = "Flash voltage (VDD_SPI) set to 3.3V by efuse." return output + def is_efuses_incompatible_for_burn(self): + # getting chip version: self._esp.get_chip_revision() + if ( + ( + self["DIS_USB_JTAG"].get() + and self["DIS_USB_SERIAL_JTAG"].get(from_read=False) + ) + or ( + self["DIS_USB_JTAG"].get(from_read=False) + and self["DIS_USB_SERIAL_JTAG"].get() + ) + or ( + self["DIS_USB_JTAG"].get(from_read=False) + and self["DIS_USB_SERIAL_JTAG"].get(from_read=False) + ) + ): + print( + "DIS_USB_JTAG and DIS_USB_SERIAL_JTAG cannot be set together due to a bug in the ROM bootloader!" + ) + return True + return False + class EfuseField(base_fields.EfuseFieldBase): @staticmethod diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 0622350b1..9bb774a2c 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -296,6 +296,28 @@ def summary(self): output = "Flash voltage (VDD_SPI) set to 3.3V by efuse." return output + def is_efuses_incompatible_for_burn(self): + # getting chip version: self._esp.get_chip_revision() + if ( + ( + self["DIS_USB_JTAG"].get(from_read=True) + and self["DIS_USB_SERIAL_JTAG"].get(from_read=False) + ) + or ( + self["DIS_USB_JTAG"].get(from_read=False) + and self["DIS_USB_SERIAL_JTAG"].get(from_read=True) + ) + or ( + self["DIS_USB_JTAG"].get(from_read=False) + and self["DIS_USB_SERIAL_JTAG"].get(from_read=False) + ) + ): + print( + "DIS_USB_JTAG and DIS_USB_SERIAL_JTAG cannot be set together due to a bug in the ROM bootloader" + ) + return True + return False + class EfuseField(base_fields.EfuseFieldBase): @staticmethod diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 2388dc94f..8b6638ee7 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -801,6 +801,24 @@ def test_burn_efuse_with_34_coding_scheme2(self): ADC2_TP_HIGH 45" ) + @pytest.mark.skipif( + arg_chip != "esp32s3", + reason="Currently S3 only has this efuse incompatibility check", + ) + def test_burn_efuse_incompatibility_check(self): + self.espefuse_py( + "burn_efuse DIS_USB_JTAG 1 DIS_USB_SERIAL_JTAG 1", + check_msg="Incompatible eFuse settings detected, abort", + ret_code=2, + ) + self.espefuse_py("burn_efuse DIS_USB_JTAG 1") + self.espefuse_py( + "burn_efuse DIS_USB_SERIAL_JTAG 1", + check_msg="Incompatible eFuse settings detected, abort", + ret_code=2, + ) + self.espefuse_py("burn_efuse DIS_USB_SERIAL_JTAG 1 --force") + class TestBurnKeyCommands(EfuseTestCase): @pytest.mark.skipif(arg_chip != "esp32", reason="ESP32-only") From 351d51db442c511d47629f12ecde1b135bc1876a Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Mon, 13 May 2024 18:15:15 +0300 Subject: [PATCH 195/209] feat(espefuse): Adds efuse dump formats: separated(default) and united(new) Added features: - read cmds can be run after burn cmds - the dump cmd can be used to create a united efuse file in --virt mode - the dump cmd can be used a few times without changing original data - updated the doc --- docs/en/espefuse/dump-cmd.rst | 17 ++++- espefuse/__init__.py | 24 +++++- espefuse/efuse/base_operations.py | 76 ++++++++++++++----- .../efuse/esp32/emulate_efuse_controller.py | 7 +- test/test_espefuse.py | 18 +++++ 5 files changed, 111 insertions(+), 31 deletions(-) diff --git a/docs/en/espefuse/dump-cmd.rst b/docs/en/espefuse/dump-cmd.rst index 01324529e..7e05727c6 100644 --- a/docs/en/espefuse/dump-cmd.rst +++ b/docs/en/espefuse/dump-cmd.rst @@ -10,7 +10,11 @@ The ``espefuse.py dump`` command allows: Optional arguments: -- ``--file_name`` - Saves dump for each block into separate file. Provide the common path name like /path/blk.bin, it will create: blk0.bin, blk1.bin ... blkN.bin. Then using ``burn_block_data`` command these dump files can be written to another chip. +- ``--format`` - Selects the dump format: + - ``default`` - Usual console eFuse dump; + - ``united`` - All eFuse blocks are stored in one file; + - ``separated`` - Each eFuse block is placed in a separate file. The tool will create multiple files based on the given the ``--file_name`` argument. Example: "--file_name /path/blk.bin", blk0.bin, blk1.bin ... blkN.bin. Use the ``burn_block_data`` cmd to write it back to another chip. +- ``--file_name`` - The path to the file in which to save the dump, if not specified, output to the console. Raw Values Of Efuse Registers ----------------------------- @@ -89,7 +93,7 @@ This command saves dump for each block into a separate file. You need to provide .. code-block:: none - > espefuse.py dump --file_name backup/chip1/blk.bin + > espefuse.py dump --format separated --file_name backup/chip1/blk.bin === Run "dump" command === backup/chip1/blk0.bin @@ -111,3 +115,12 @@ These dump files can be written to another chip: > espefuse.py burn_block_data BLOCK0 backup/chip1/blk0.bin \ BLOCK1 backup/chip1/blk1.bin \ BLOCK2 backup/chip1/blk2.bin + +To save all eFuse blocks in one file, use the following command: + +.. code-block:: none + + > espefuse.py dump --format united --file_name backup/chip1/efuses.bin + + === Run "dump" command === + backup/chip1/efuses.bin diff --git a/espefuse/__init__.py b/espefuse/__init__.py index a2d4df0e4..6158a3bf0 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -39,13 +39,15 @@ "execute_scripts", ] -SUPPORTED_COMMANDS = [ +SUPPORTED_READ_COMMANDS = [ "summary", "dump", "get_custom_mac", "adc_info", "check_error", -] + SUPPORTED_BURN_COMMANDS +] + +SUPPORTED_COMMANDS = SUPPORTED_READ_COMMANDS + SUPPORTED_BURN_COMMANDS SUPPORTED_CHIPS = { "esp32": DefChip("ESP32", esp32_efuse, esptool.targets.ESP32ROM), @@ -228,7 +230,7 @@ def main(custom_commandline=None, esp=None): ) common_args, remaining_args = init_parser.parse_known_args(custom_commandline) - debug_mode = common_args.debug or ("dump" in remaining_args) + debug_mode = common_args.debug just_print_help = [ True for arg in remaining_args if arg in ["--help", "-h"] ] or remaining_args == [] @@ -304,6 +306,22 @@ def main(custom_commandline=None, esp=None): if not efuses.burn_all(check_batch_mode=True): raise esptool.FatalError("BURN was not done") print("Successful") + + if ( + sum(cmd in SUPPORTED_BURN_COMMANDS for cmd in used_cmds) > 0 + and sum(cmd in SUPPORTED_READ_COMMANDS for cmd in used_cmds) > 0 + ): + # [burn_cmd1] [burn_cmd2] [read_cmd1] [burn_cmd3] [read_cmd2] + print("\n=== Run read commands after burn commands ===") + for rem_args in grouped_remaining_args: + args, unused_args = parser.parse_known_args( + rem_args, namespace=common_args + ) + current_cmd = args.operation + if current_cmd in SUPPORTED_READ_COMMANDS: + print(f"\n=== Run {args.operation} command ===") + operation_func = vars(efuse_operations)[current_cmd] + operation_func(esp, efuses, args) finally: if not external_esp and not common_args.virt and esp._port: esp._port.close() diff --git a/espefuse/efuse/base_operations.py b/espefuse/efuse/base_operations.py index 42a7c9abc..fb21bcd4d 100644 --- a/espefuse/efuse/base_operations.py +++ b/espefuse/efuse/base_operations.py @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import argparse +import os import json import sys @@ -173,12 +174,22 @@ def check_efuse_name(efuse_name, efuse_list): help="Display information about ADC calibration data stored in efuse.", ) - dump_cmd = subparsers.add_parser("dump", help="Dump raw hex values of all efuses") + dump_cmd = subparsers.add_parser("dump", help="Dump raw hex values of all eFuses") + dump_cmd.add_argument( + "--format", + help="Select the dump format: " + "default - usual console eFuse dump; " + "united - all eFuse blocks are stored in one file; " + "separated - each eFuse block is placed in a separate file. Tool will create multiple files based on " + "the given --file_name (/path/blk.bin): blk0.bin, blk1.bin ... blkN.bin. Use the burn_block_data cmd " + "to write it back to another chip.", + choices=["default", "separated", "united"], + default="default", + ) dump_cmd.add_argument( "--file_name", - help="Saves dump for each block into separate file. Provide the common " - "path name /path/blk.bin, it will create: blk0.bin, blk1.bin ... blkN.bin. " - "Use burn_block_data to write it back to another chip.", + help="The path to the file in which to save the dump, if not specified, output to the console.", + default=sys.stdout, ) summary_cmd = subparsers.add_parser( @@ -379,23 +390,48 @@ def summary(esp, efuses, args): def dump(esp, efuses, args): """Dump raw efuse data registers""" - # Using --debug option allows to print dump. - # Nothing to do here. The log will be printed - # during EspEfuses.__init__() in self.read_blocks() - if args.file_name: - # save dump to the file + dump_file = args.file_name + to_console = args.file_name == sys.stdout + + def output_block_to_file(block, f, to_console): + block_dump = BitStream(block.get_bitstring()) + block_dump.byteswap() + if to_console: + f.write(block_dump.hex + "\n") + else: + block_dump.tofile(f) + + if args.format == "default": + if to_console: + # for "espefuse.py dump" cmd + for block in efuses.blocks: + block.print_block(block.get_bitstring(), "dump", debug=True) + return + else: + # for back compatibility to support "espefuse.py dump --file_name dump.bin" + args.format = "separated" + + if args.format == "separated": + # each efuse block is placed in a separate file for block in efuses.blocks: - file_dump_name = args.file_name - place_for_index = file_dump_name.find(".bin") - file_dump_name = ( - file_dump_name[:place_for_index] - + str(block.id) - + file_dump_name[place_for_index:] - ) - print(file_dump_name) - with open(file_dump_name, "wb") as f: - block.get_bitstring().byteswap() - block.get_bitstring().tofile(f) + if not to_console: + file_dump_name = args.file_name + fname, fextension = os.path.splitext(file_dump_name) + file_dump_name = f"{fname}{block.id}{fextension}" + print(f"Dump efuse block{block.id} -> {file_dump_name}") + dump_file = open(file_dump_name, "wb") + output_block_to_file(block, dump_file, to_console) + if not to_console: + dump_file.close() + elif args.format == "united": + # all efuse blocks are stored in one file + if not to_console: + print(f"Dump efuse blocks -> {args.file_name}") + dump_file = open(args.file_name, "wb") + for block in efuses.blocks: + output_block_to_file(block, dump_file, to_console) + if not to_console: + dump_file.close() def burn_efuse(esp, efuses, args): diff --git a/espefuse/efuse/esp32/emulate_efuse_controller.py b/espefuse/efuse/esp32/emulate_efuse_controller.py index 5b5882f36..6771a0b39 100644 --- a/espefuse/efuse/esp32/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32/emulate_efuse_controller.py @@ -38,12 +38,7 @@ def read_reg(self, addr): if addr == self.REGS.APB_CTL_DATE_ADDR: return self.REGS.APB_CTL_DATE_V << self.REGS.APB_CTL_DATE_S else: - val = 0 - if addr == self.REGS.EFUSE_BLK0_RDATA3_REG: - val = self.REGS.EFUSE_RD_CHIP_VER_REV1 - if addr == self.REGS.EFUSE_BLK0_RDATA5_REG: - val = self.REGS.EFUSE_RD_CHIP_VER_REV2 - return val | super(EmulateEfuseController, self).read_reg(addr) + return super(EmulateEfuseController, self).read_reg(addr) """ << esptool method end """ diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 8b6638ee7..26daf8c49 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -73,6 +73,7 @@ def setup_method(self): f"{sys.executable} -m espefuse --chip {arg_chip} " f"--virt --path-efuse-file {self.efuse_file.name} -d" ) + self._set_target_wafer_version() else: self.base_cmd = ( f"{sys.executable} -m espefuse --chip {arg_chip} " @@ -117,6 +118,11 @@ def _set_34_coding_scheme(self): def _set_none_recovery_coding_scheme(self): self.espefuse_py("burn_efuse CODING_SCHEME 3") + def _set_target_wafer_version(self): + # ESP32 has to be ECO3 (v3.0) for tests + if arg_chip == "esp32": + self.espefuse_py("burn_efuse CHIP_VER_REV1 1 CHIP_VER_REV2 1") + def check_data_block_in_log( self, log, file_path, repeat=1, reverse_order=False, offset=0 ): @@ -177,6 +183,18 @@ def test_dump(self): self.espefuse_py("dump -h") self.espefuse_py("dump") + def test_dump_format_united(self): + tmp_file = tempfile.NamedTemporaryFile(delete=False) + self.espefuse_py(f"dump --format united --file_name {tmp_file.name}") + + def test_dump_separated_default(self): + tmp_file = tempfile.NamedTemporaryFile(delete=False) + self.espefuse_py(f"dump --file_name {tmp_file.name}") + + def test_dump_separated(self): + tmp_file = tempfile.NamedTemporaryFile(delete=False) + self.espefuse_py(f"dump --format separated --file_name {tmp_file.name}") + def test_summary(self): self.espefuse_py("summary -h") self.espefuse_py("summary") From 53393544a38a1f3f29baed4c9fe2a3fa9f90c833 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Sat, 6 Apr 2024 17:56:46 +0300 Subject: [PATCH 196/209] feat(espefuse): Adds support extend efuse table by user CSV file --- docs/en/espefuse/index.rst | 53 ++++ espefuse/__init__.py | 24 +- espefuse/efuse/csv_table_parser.py | 266 ++++++++++++++++++ .../efuse/esp32/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32/fields.py | 11 +- espefuse/efuse/esp32/mem_definition.py | 4 +- .../efuse/esp32c2/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32c2/fields.py | 11 +- espefuse/efuse/esp32c2/mem_definition.py | 4 +- .../efuse/esp32c3/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32c3/fields.py | 11 +- espefuse/efuse/esp32c3/mem_definition.py | 4 +- .../efuse/esp32c5/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32c5/fields.py | 11 +- espefuse/efuse/esp32c5/mem_definition.py | 4 +- .../esp32c5beta3/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32c5beta3/fields.py | 11 +- espefuse/efuse/esp32c5beta3/mem_definition.py | 4 +- .../efuse/esp32c6/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32c6/fields.py | 11 +- espefuse/efuse/esp32c6/mem_definition.py | 4 +- .../esp32c61/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32c61/fields.py | 11 +- espefuse/efuse/esp32c61/mem_definition.py | 4 +- .../efuse/esp32h2/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32h2/fields.py | 11 +- espefuse/efuse/esp32h2/mem_definition.py | 4 +- .../esp32h2beta1/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32h2beta1/fields.py | 11 +- espefuse/efuse/esp32h2beta1/mem_definition.py | 4 +- .../efuse/esp32p4/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32p4/fields.py | 11 +- espefuse/efuse/esp32p4/mem_definition.py | 4 +- .../efuse/esp32s2/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32s2/fields.py | 11 +- espefuse/efuse/esp32s2/mem_definition.py | 4 +- .../efuse/esp32s3/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32s3/fields.py | 11 +- espefuse/efuse/esp32s3/mem_definition.py | 4 +- .../esp32s3beta2/emulate_efuse_controller.py | 2 +- espefuse/efuse/esp32s3beta2/fields.py | 11 +- espefuse/efuse/esp32s3beta2/mem_definition.py | 4 +- espefuse/efuse/mem_definition_base.py | 64 ++++- test/images/efuse/esp_efuse_custom_table.csv | 13 + test/test_espefuse.py | 29 ++ 45 files changed, 600 insertions(+), 70 deletions(-) create mode 100644 espefuse/efuse/csv_table_parser.py create mode 100644 test/images/efuse/esp_efuse_custom_table.csv diff --git a/docs/en/espefuse/index.rst b/docs/en/espefuse/index.rst index ba5009123..26e19cb49 100644 --- a/docs/en/espefuse/index.rst +++ b/docs/en/espefuse/index.rst @@ -56,6 +56,7 @@ Optional General Arguments Of Commands - ``--virt`` - For host tests. The tool will work in the virtual mode (without connecting to a chip). - ``--path-efuse-file`` - For host tests. Use it together with ``--virt`` option. The tool will work in the virtual mode (without connecting to a chip) and save eFuse memory to a given file. If the file does not exists the tool creates it. To reset written eFuses just delete the file. Usage: ``--path-efuse-file efuse_memory.bin``. - ``--do-not-confirm`` - Do not pause for confirmation before permanently writing eFuses. Use with caution. If this option is not used, a manual confirmation step is required, you need to enter the word ``BURN`` to continue burning. +- ``--extend-efuse-table`` - CSV file from `ESP-IDF `_ (esp_efuse_custom_table.csv). Virtual mode ^^^^^^^^^^^^ @@ -113,6 +114,58 @@ The example below shows how to use the two commands ``burn_key_digest`` and ``bu burn_key_digest secure_images/ecdsa256_secure_boot_signing_key_v2.pem \ burn_key BLOCK_KEY0 images/efuse/128bit_key.bin XTS_AES_128_KEY_DERIVED_FROM_128_EFUSE_BITS +Extend Efuse Table +------------------ + +This tool supports the use of `CSV files `_ from the `ESP-IDF `_ (e.g., ``esp_efuse_custom_table.csv``) to add custom eFuse fields. You can use this argument with any supported commands to access these custom eFuses. + +.. code-block:: none + + > espefuse.py -c esp32 --extend-efuse-table path/esp_efuse_custom_table.csv summary + +Below is an example of an ``esp_efuse_custom_table.csv`` file. This example demonstrates how to define single eFuse fields, ``structured eFuse fields`` and ``non-sequential bit fields``: + +.. code-block:: none + + MODULE_VERSION, EFUSE_BLK3, 56, 8, Module version + DEVICE_ROLE, EFUSE_BLK3, 64, 3, Device role + SETTING_1, EFUSE_BLK3, 67, 6, [SETTING_1_ALT_NAME] Setting 1 + SETTING_2, EFUSE_BLK3, 73, 5, Setting 2 + ID_NUM, EFUSE_BLK3, 140, 8, [MY_ID_NUM] comment + , EFUSE_BLK3, 132, 8, [MY_ID_NUM] comment + , EFUSE_BLK3, 122, 8, [MY_ID_NUM] comment + CUSTOM_SECURE_VERSION, EFUSE_BLK3, 78, 16, Custom secure version + ID_NUMK, EFUSE_BLK3, 150, 8, [MY_ID_NUMK] comment + , EFUSE_BLK3, 182, 8, [MY_ID_NUMK] comment + MY_DATA, EFUSE_BLK3, 190, 10, My data + MY_DATA.FIELD1, EFUSE_BLK3, 190, 7, Field1 + +When you include this CSV file, the tool will generate a new section in the summary called ``User fuses``. + +.. code-block:: none + + User fuses: + MODULE_VERSION (BLOCK3) Module version (56-63) = 0 R/W (0x00) + DEVICE_ROLE (BLOCK3) Device role (64-66) = 0 R/W (0b000) + SETTING_1 (BLOCK3) [SETTING_1_ALT_NAME] Setting 1 (67-72) = 0 R/W (0b000000) + SETTING_2 (BLOCK3) Setting 2 (73-77) = 0 R/W (0b00000) + ID_NUM_0 (BLOCK3) [MY_ID_NUM] comment (140-147) = 0 R/W (0x00) + ID_NUM_1 (BLOCK3) [MY_ID_NUM] comment (132-139) = 0 R/W (0x00) + ID_NUM_2 (BLOCK3) [MY_ID_NUM] comment (122-129) = 0 R/W (0x00) + CUSTOM_SECURE_VERSION (BLOCK3) Custom secure version (78-93) = 0 R/W (0x0000) + ID_NUMK_0 (BLOCK3) [MY_ID_NUMK] comment (150-157) = 0 R/W (0x00) + ID_NUMK_1 (BLOCK3) [MY_ID_NUMK] comment (182-189) = 0 R/W (0x00) + MY_DATA (BLOCK3) My data (190-199) = 0 R/W (0b0000000000) + MY_DATA_FIELD1 (BLOCK3) Field1 (190-196) = 0 R/W (0b0000000) + +You can reference these fields using the names and aliases provided in the CSV file. For non-sequential bits, the names are modified slightly with the addition of _0 and _1 postfixes for every sub-field, to ensure safer handling. + +For the current example, you can reference the custom fields with the following names: MODULE_VERSION, DEVICE_ROLE, SETTING_1, SETTING_2, ID_NUM_0, ID_NUM_1, ID_NUM_2, CUSTOM_SECURE_VERSION, ID_NUMK_0, ID_NUMK_1, MY_DATA, MY_DATA_FIELD1; and alises: SETTING_1_ALT_NAME, MY_ID_NUM_0, MY_ID_NUM_1, MY_ID_NUM_2, MY_ID_NUMK_0, MY_ID_NUMK_1. + +For convenience, the espefuse summary command includes the used bit range of the field in a comment, such as ``(150-157)`` len = 8 bits. + +For more details on the structure and usage of the CSV file, refer to the `eFuse Manager `_ chapter in the ESP-IDF documentation. + Recommendations --------------- diff --git a/espefuse/__init__.py b/espefuse/__init__.py index 6158a3bf0..1ec0e2f23 100755 --- a/espefuse/__init__.py +++ b/espefuse/__init__.py @@ -101,12 +101,20 @@ def get_esp( return esp -def get_efuses(esp, skip_connect=False, debug_mode=False, do_not_confirm=False): +def get_efuses( + esp, + skip_connect=False, + debug_mode=False, + do_not_confirm=False, + extend_efuse_table=None, +): for name in SUPPORTED_CHIPS: if SUPPORTED_CHIPS[name].chip_name == esp.CHIP_NAME: efuse = SUPPORTED_CHIPS[name].efuse_lib return ( - efuse.EspEfuses(esp, skip_connect, debug_mode, do_not_confirm), + efuse.EspEfuses( + esp, skip_connect, debug_mode, do_not_confirm, extend_efuse_table + ), efuse.operations, ) else: @@ -228,6 +236,12 @@ def main(custom_commandline=None, esp=None): "(efuses which disable access to blocks or chip).", action="store_true", ) + init_parser.add_argument( + "--extend-efuse-table", + help="CSV file from ESP-IDF (esp_efuse_custom_table.csv)", + type=argparse.FileType("r"), + default=None, + ) common_args, remaining_args = init_parser.parse_known_args(custom_commandline) debug_mode = common_args.debug @@ -257,7 +271,11 @@ def main(custom_commandline=None, esp=None): # TODO: Require the --port argument in the next major release, ESPTOOL-490 efuses, efuse_operations = get_efuses( - esp, just_print_help, debug_mode, common_args.do_not_confirm + esp, + just_print_help, + debug_mode, + common_args.do_not_confirm, + common_args.extend_efuse_table, ) parser = argparse.ArgumentParser(parents=[init_parser]) diff --git a/espefuse/efuse/csv_table_parser.py b/espefuse/efuse/csv_table_parser.py new file mode 100644 index 000000000..4bebbb02a --- /dev/null +++ b/espefuse/efuse/csv_table_parser.py @@ -0,0 +1,266 @@ +# This file helps to parse CSV eFuse tables +# +# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os +import re +import sys + + +class CSVFuseTable(list): + @classmethod + def from_csv(cls, csv_contents): + res = CSVFuseTable() + lines = csv_contents.splitlines() + + def expand_vars(f): + f = os.path.expandvars(f) + m = re.match(r"(? 1) + for dname in duplicates: + i_count = 0 + for p in res: + if p.field_name != dname: + continue + if len(duplicates.intersection([p.field_name])) != 0: + p.field_name = f"{p.field_name}_{i_count}" + if p.alt_names: + p.alt_names = f"{p.alt_names}_{i_count}" + i_count += 1 + else: + i_count = 0 + + for p in res: + p.field_name = p.field_name.replace(".", "_") + if p.alt_names: + p.alt_names = p.alt_names.replace(".", "_") + res.verify_duplicate_name() + return res + + def verify_duplicate_name(self): + # check on duplicate name + names = [p.field_name for p in self] + names += [name.replace(".", "_") for name in names if "." in name] + duplicates = set(n for n in names if names.count(n) > 1) + + # print sorted duplicate partitions by name + if len(duplicates) != 0: + fl_error = False + for p in self: + field_name = p.field_name + p.group + if field_name != "" and len(duplicates.intersection([field_name])) != 0: + fl_error = True + print( + f"Field at {p.field_name}, {p.efuse_block}, " + f"{p.bit_start}, {p.bit_count} have duplicate field_name" + ) + if fl_error is True: + raise InputError("Field names must be unique") + + def check_struct_field_name(self): + # check that structured fields have a root field + for p in self: + if "." in p.field_name: + name = "" + for sub in p.field_name.split(".")[:-1]: + name = sub if name == "" else name + "." + sub + missed_name = True + for d in self: + if ( + p is not d + and p.efuse_block == d.efuse_block + and name == d.field_name + ): + missed_name = False + if missed_name: + raise InputError(f"{name} is not found") + + def verify(self, type_table=None): + def check(p, n): + left = n.bit_start + right = n.bit_start + n.bit_count - 1 + start = p.bit_start + end = p.bit_start + p.bit_count - 1 + if left <= start <= right: + if left <= end <= right: + return "included in" # [n [p...p] n] + return "intersected with" # [n [p..n]..p] + if left <= end <= right: + return "intersected with" # [p..[n..p] n] + if start <= left and right <= end: + return "wraps" # [p [n...n] p] + return "ok" # [p] [n] or [n] [p] + + def print_error(p, n, state): + raise InputError( + f"Field at {p.field_name}, {p.efuse_block}, {p.bit_start}, {p.bit_count} {state} {n.field_name}, {n.efuse_block}, {n.bit_start}, {n.bit_count}" + ) + + for p in self: + p.verify(type_table) + + self.verify_duplicate_name() + if type_table != "custom_table": + # check will be done for common and custom tables together + self.check_struct_field_name() + + # check for overlaps + for p in self: + for n in self: + if p is not n and p.efuse_block == n.efuse_block: + state = check(p, n) + if state != "ok": + if "." in p.field_name: + name = "" + for sub in p.field_name.split("."): + name = sub if name == "" else name + "." + sub + for d in self: + if ( + p is not d + and p.efuse_block == d.efuse_block + and name == d.field_name + ): + state = check(p, d) + if state == "included in": + break + elif state != "intersected with": + state = "out of range" + print_error(p, d, state) + continue + elif "." in n.field_name: + continue + print_error(p, n, state) + + +class FuseDefinition(object): + def __init__(self): + self.field_name = "" + self.group = "" + self.efuse_block = "" + self.bit_start = None + self.bit_count = None + self.define = None + self.comment = "" + self.alt_names = "" + self.MAX_BITS_OF_BLOCK = 256 + + @classmethod + def from_csv(cls, line): + """Parse a line from the CSV""" + line_w_defaults = line + ",,,," + fields = [f.strip() for f in line_w_defaults.split(",")] + + res = FuseDefinition() + res.field_name = fields[0] + res.efuse_block = res.parse_block(fields[1]) + res.bit_start = res.parse_num(fields[2]) + res.bit_count = res.parse_bit_count(fields[3]) + if res.bit_count is None or res.bit_count == 0: + raise InputError("Field bit_count can't be empty") + res.comment = fields[4].rstrip("\\").rstrip() + res.comment += f" ({res.bit_start}-{res.bit_start + res.bit_count - 1})" + res.alt_names = res.get_alt_names(res.comment) + return res + + def parse_num(self, strval): + if strval == "": + return None + return self.parse_int(strval) + + def parse_bit_count(self, strval): + if strval == "MAX_BLK_LEN": + self.define = strval + return self.MAX_BITS_OF_BLOCK + else: + return self.parse_num(strval) + + def parse_int(self, v): + try: + return int(v, 0) + except ValueError: + raise InputError(f"Invalid field value {v}") + + def parse_block(self, strval): + if strval == "": + raise InputError("Field 'efuse_block' can't be left empty.") + return self.parse_int(strval.lstrip("EFUSE_BLK")) + + def verify(self, type_table): + if self.efuse_block is None: + raise ValidationError(self, "efuse_block field is not set") + if self.bit_count is None: + raise ValidationError(self, "bit_count field is not set") + max_bits = self.MAX_BITS_OF_BLOCK + if self.bit_start + self.bit_count > max_bits: + raise ValidationError( + self, + f"The field is outside the boundaries(max_bits = {max_bits}) of the {self.efuse_block} block", + ) + + def get_bit_count(self, check_define=True): + if check_define is True and self.define is not None: + return self.define + else: + return self.bit_count + + def get_alt_names(self, comment): + result = re.search(r"^\[(.*?)\]", comment) + if result: + return result.group(1) + return "" + + +class InputError(RuntimeError): + def __init__(self, e): + super(InputError, self).__init__(e) + + +class ValidationError(InputError): + def __init__(self, p, message): + super(ValidationError, self).__init__( + f"Entry {p.field_name} invalid: {message}" + ) diff --git a/espefuse/efuse/esp32/emulate_efuse_controller.py b/espefuse/efuse/esp32/emulate_efuse_controller.py index 6771a0b39..03011fa59 100644 --- a/espefuse/efuse/esp32/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) diff --git a/espefuse/efuse/esp32/fields.py b/espefuse/efuse/esp32/fields.py index 7a9c9d46a..c1a625bcb 100644 --- a/espefuse/efuse/esp32/fields.py +++ b/espefuse/efuse/esp32/fields.py @@ -68,9 +68,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32/mem_definition.py b/espefuse/efuse/esp32/mem_definition.py index 7d29a010a..60f30935a 100644 --- a/espefuse/efuse/esp32/mem_definition.py +++ b/espefuse/efuse/esp32/mem_definition.py @@ -89,7 +89,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: self.EFUSES = [] # if MAC_VERSION is set "1", these efuse fields are in BLOCK3: self.CUSTOM_MAC = [] @@ -109,7 +109,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name == "BLOCK1" or efuse.name == "BLOCK2": diff --git a/espefuse/efuse/esp32c2/emulate_efuse_controller.py b/espefuse/efuse/esp32c2/emulate_efuse_controller.py index 26796dff8..a7d4693e4 100644 --- a/espefuse/efuse/esp32c2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c2/emulate_efuse_controller.py @@ -21,7 +21,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32c2/fields.py b/espefuse/efuse/esp32c2/fields.py index bfbcae632..a9fe33cce 100644 --- a/espefuse/efuse/esp32c2/fields.py +++ b/espefuse/efuse/esp32c2/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32c2/mem_definition.py b/espefuse/efuse/esp32c2/mem_definition.py index 7adb0111f..47cd18c04 100644 --- a/espefuse/efuse/esp32c2/mem_definition.py +++ b/espefuse/efuse/esp32c2/mem_definition.py @@ -94,7 +94,7 @@ def get_blocks_for_keys(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -110,7 +110,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in ["BLOCK_KEY0"]: diff --git a/espefuse/efuse/esp32c3/emulate_efuse_controller.py b/espefuse/efuse/esp32c3/emulate_efuse_controller.py index 2d812a10d..fca2f102b 100644 --- a/espefuse/efuse/esp32c3/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c3/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32c3/fields.py b/espefuse/efuse/esp32c3/fields.py index 05914e429..f367540a8 100644 --- a/espefuse/efuse/esp32c3/fields.py +++ b/espefuse/efuse/esp32c3/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32c3/mem_definition.py b/espefuse/efuse/esp32c3/mem_definition.py index 610d64e17..bd13bd773 100644 --- a/espefuse/efuse/esp32c3/mem_definition.py +++ b/espefuse/efuse/esp32c3/mem_definition.py @@ -127,7 +127,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -145,7 +145,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32c5/emulate_efuse_controller.py b/espefuse/efuse/esp32c5/emulate_efuse_controller.py index 40cc06fdc..f81caeb70 100644 --- a/espefuse/efuse/esp32c5/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c5/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32c5/fields.py b/espefuse/efuse/esp32c5/fields.py index c3d44649d..b61ba6077 100644 --- a/espefuse/efuse/esp32c5/fields.py +++ b/espefuse/efuse/esp32c5/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32c5/mem_definition.py b/espefuse/efuse/esp32c5/mem_definition.py index 9a9212681..0520328ba 100644 --- a/espefuse/efuse/esp32c5/mem_definition.py +++ b/espefuse/efuse/esp32c5/mem_definition.py @@ -111,7 +111,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -129,7 +129,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py b/espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py index 27816831a..3fdab6f81 100644 --- a/espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c5beta3/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32c5beta3/fields.py b/espefuse/efuse/esp32c5beta3/fields.py index fc345686e..351d73667 100644 --- a/espefuse/efuse/esp32c5beta3/fields.py +++ b/espefuse/efuse/esp32c5beta3/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32c5beta3/mem_definition.py b/espefuse/efuse/esp32c5beta3/mem_definition.py index f1b99495b..67ffff60e 100644 --- a/espefuse/efuse/esp32c5beta3/mem_definition.py +++ b/espefuse/efuse/esp32c5beta3/mem_definition.py @@ -111,7 +111,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -129,7 +129,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32c6/emulate_efuse_controller.py b/espefuse/efuse/esp32c6/emulate_efuse_controller.py index a9e7d4d4a..47c403ce8 100644 --- a/espefuse/efuse/esp32c6/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c6/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32c6/fields.py b/espefuse/efuse/esp32c6/fields.py index 5e0a449e5..70df55cec 100644 --- a/espefuse/efuse/esp32c6/fields.py +++ b/espefuse/efuse/esp32c6/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32c6/mem_definition.py b/espefuse/efuse/esp32c6/mem_definition.py index 25e4caf01..4574fdf63 100644 --- a/espefuse/efuse/esp32c6/mem_definition.py +++ b/espefuse/efuse/esp32c6/mem_definition.py @@ -111,7 +111,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -129,7 +129,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32c61/emulate_efuse_controller.py b/espefuse/efuse/esp32c61/emulate_efuse_controller.py index 22e4da277..1118daada 100644 --- a/espefuse/efuse/esp32c61/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32c61/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32c61/fields.py b/espefuse/efuse/esp32c61/fields.py index db00fb0eb..5f6fe7b8c 100644 --- a/espefuse/efuse/esp32c61/fields.py +++ b/espefuse/efuse/esp32c61/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32c61/mem_definition.py b/espefuse/efuse/esp32c61/mem_definition.py index 94b57b959..2f8f818a5 100644 --- a/espefuse/efuse/esp32c61/mem_definition.py +++ b/espefuse/efuse/esp32c61/mem_definition.py @@ -111,7 +111,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -129,7 +129,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32h2/emulate_efuse_controller.py b/espefuse/efuse/esp32h2/emulate_efuse_controller.py index c8d3cd91a..b482eab09 100644 --- a/espefuse/efuse/esp32h2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32h2/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py index 46182607b..91ef6c15c 100644 --- a/espefuse/efuse/esp32h2/fields.py +++ b/espefuse/efuse/esp32h2/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32h2/mem_definition.py b/espefuse/efuse/esp32h2/mem_definition.py index d08a71f0c..87663e95f 100644 --- a/espefuse/efuse/esp32h2/mem_definition.py +++ b/espefuse/efuse/esp32h2/mem_definition.py @@ -111,7 +111,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -129,7 +129,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py b/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py index b81e8e08f..1c336cbfe 100644 --- a/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32h2beta1/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32h2beta1/fields.py b/espefuse/efuse/esp32h2beta1/fields.py index 165734989..90fb72bb5 100644 --- a/espefuse/efuse/esp32h2beta1/fields.py +++ b/espefuse/efuse/esp32h2beta1/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32h2beta1/mem_definition.py b/espefuse/efuse/esp32h2beta1/mem_definition.py index 8c694306e..73bfb370e 100644 --- a/espefuse/efuse/esp32h2beta1/mem_definition.py +++ b/espefuse/efuse/esp32h2beta1/mem_definition.py @@ -107,7 +107,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -126,7 +126,7 @@ def __init__(self) -> None: efuse_file = efuse_file.replace("esp32h2beta1", "esp32h2") with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32p4/emulate_efuse_controller.py b/espefuse/efuse/esp32p4/emulate_efuse_controller.py index aa670aff7..adae384df 100644 --- a/espefuse/efuse/esp32p4/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32p4/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32p4/fields.py b/espefuse/efuse/esp32p4/fields.py index 415a6b33d..e28d788dc 100644 --- a/espefuse/efuse/esp32p4/fields.py +++ b/espefuse/efuse/esp32p4/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32p4/mem_definition.py b/espefuse/efuse/esp32p4/mem_definition.py index 9d3d2a5b7..c1427e516 100644 --- a/espefuse/efuse/esp32p4/mem_definition.py +++ b/espefuse/efuse/esp32p4/mem_definition.py @@ -111,7 +111,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -129,7 +129,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32s2/emulate_efuse_controller.py b/espefuse/efuse/esp32s2/emulate_efuse_controller.py index 497c91a5f..6c88ed54b 100644 --- a/espefuse/efuse/esp32s2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s2/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32s2/fields.py b/espefuse/efuse/esp32s2/fields.py index 15d927529..1339fdb14 100644 --- a/espefuse/efuse/esp32s2/fields.py +++ b/espefuse/efuse/esp32s2/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32s2/mem_definition.py b/espefuse/efuse/esp32s2/mem_definition.py index b83ea9139..4799751db 100644 --- a/espefuse/efuse/esp32s2/mem_definition.py +++ b/espefuse/efuse/esp32s2/mem_definition.py @@ -150,7 +150,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -168,7 +168,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32s3/emulate_efuse_controller.py b/espefuse/efuse/esp32s3/emulate_efuse_controller.py index 7e767b954..9446c6af3 100644 --- a/espefuse/efuse/esp32s3/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s3/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32s3/fields.py b/espefuse/efuse/esp32s3/fields.py index bbf08a37e..9bb4eeaf3 100644 --- a/espefuse/efuse/esp32s3/fields.py +++ b/espefuse/efuse/esp32s3/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32s3/mem_definition.py b/espefuse/efuse/esp32s3/mem_definition.py index 54c88712c..11aecfa65 100644 --- a/espefuse/efuse/esp32s3/mem_definition.py +++ b/espefuse/efuse/esp32s3/mem_definition.py @@ -112,7 +112,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -130,7 +130,7 @@ def __init__(self) -> None: efuse_file = os.path.join(dir_name, "efuse_defs", file_name) with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py b/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py index 0d81c0832..949fc562b 100644 --- a/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py +++ b/espefuse/efuse/esp32s3beta2/emulate_efuse_controller.py @@ -19,7 +19,7 @@ class EmulateEfuseController(EmulateEfuseControllerBase): def __init__(self, efuse_file=None, debug=False): self.Blocks = EfuseDefineBlocks - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(None) self.REGS = EfuseDefineRegisters super(EmulateEfuseController, self).__init__(efuse_file, debug) self.write_reg(self.REGS.EFUSE_CMD_REG, 0) diff --git a/espefuse/efuse/esp32s3beta2/fields.py b/espefuse/efuse/esp32s3beta2/fields.py index 9bb774a2c..28e03e9cf 100644 --- a/espefuse/efuse/esp32s3beta2/fields.py +++ b/espefuse/efuse/esp32s3beta2/fields.py @@ -58,9 +58,16 @@ class EspEfuses(base_fields.EspEfusesBase): debug = False do_not_confirm = False - def __init__(self, esp, skip_connect=False, debug=False, do_not_confirm=False): + def __init__( + self, + esp, + skip_connect=False, + debug=False, + do_not_confirm=False, + extend_efuse_table=None, + ): self.Blocks = EfuseDefineBlocks() - self.Fields = EfuseDefineFields() + self.Fields = EfuseDefineFields(extend_efuse_table) self.REGS = EfuseDefineRegisters self.BURN_BLOCK_DATA_NAMES = self.Blocks.get_burn_block_data_names() self.BLOCKS_FOR_KEYS = self.Blocks.get_blocks_for_keys() diff --git a/espefuse/efuse/esp32s3beta2/mem_definition.py b/espefuse/efuse/esp32s3beta2/mem_definition.py index eabf76781..0fb1ec8ba 100644 --- a/espefuse/efuse/esp32s3beta2/mem_definition.py +++ b/espefuse/efuse/esp32s3beta2/mem_definition.py @@ -112,7 +112,7 @@ def get_burn_block_data_names(self): class EfuseDefineFields(EfuseFieldsBase): - def __init__(self) -> None: + def __init__(self, extend_efuse_table) -> None: # List of efuse fields from TRM the chapter eFuse Controller. self.EFUSES = [] @@ -131,7 +131,7 @@ def __init__(self) -> None: efuse_file = efuse_file.replace("esp32s3beta2", "esp32s3") with open(f"{efuse_file}", "r") as r_file: e_desc = yaml.safe_load(r_file) - super().__init__(e_desc) + super().__init__(e_desc, extend_efuse_table) for i, efuse in enumerate(self.ALL_EFUSES): if efuse.name in [ diff --git a/espefuse/efuse/mem_definition_base.py b/espefuse/efuse/mem_definition_base.py index 434b3a911..f6e2bdc0b 100644 --- a/espefuse/efuse/mem_definition_base.py +++ b/espefuse/efuse/mem_definition_base.py @@ -4,9 +4,12 @@ # # SPDX-License-Identifier: GPL-2.0-or-later -from collections import namedtuple +from collections import Counter, namedtuple +import esptool from typing import Optional, List +from .csv_table_parser import CSVFuseTable + class EfuseRegistersBase(object): # Coding Scheme values @@ -61,7 +64,7 @@ class Field: class EfuseFieldsBase(object): - def __init__(self, e_desc) -> None: + def __init__(self, e_desc, extend_efuse_table_file) -> None: self.ALL_EFUSES: List = [] def set_category_and_class_type(efuse, name): @@ -170,3 +173,60 @@ def includes(name, names): ) set_category_and_class_type(d, e_name) self.ALL_EFUSES.append(d) + + if self.extend_efuses(extend_efuse_table_file): + self.check_name_duplicates() + + def check_name_duplicates(self): + names = [n.name for n in self.ALL_EFUSES] + for n in self.ALL_EFUSES: + if n.alt_names: + names.extend(n.alt_names) + + name_counts = Counter(names) + duplicates = {name for name, count in name_counts.items() if count > 1} + if duplicates: + print("Names that are not unique: " + ", ".join(duplicates)) + raise esptool.FatalError("Duplicate names found in eFuses") + + def extend_efuses(self, extend_efuse_table_file): + if extend_efuse_table_file: + table = CSVFuseTable.from_csv(extend_efuse_table_file.read()) + for p in table: + item = Field() + item.name = p.field_name + item.block = p.efuse_block + item.word = p.bit_start // 32 + item.pos = p.bit_start % 32 + item.bit_len = p.bit_count + if p.bit_count == 1: + str_type = "bool" + else: + if p.bit_count > 32 and p.bit_count % 8 == 0: + str_type = f"bytes:{p.bit_count // 8}" + else: + str_type = f"uint:{p.bit_count}" + item.type = str_type + item.write_disable_bit = None + item.read_disable_bit = None + if item.block != 0: + # look for an already configured field associated with this field + # to take the WR_DIS and RID_DIS bits + for field in self.ALL_EFUSES: + if field.block == item.block: + if field.write_disable_bit is not None: + item.write_disable_bit = field.write_disable_bit + if field.read_disable_bit is not None: + item.read_disable_bit = field.read_disable_bit + if ( + item.read_disable_bit is not None + and item.write_disable_bit is not None + ): + break + item.category = "User" + item.description = p.comment + item.alt_names = p.alt_names.split(" ") if p.alt_names else [] + item.dictionary = "" + self.ALL_EFUSES.append(item) + return True + return False diff --git a/test/images/efuse/esp_efuse_custom_table.csv b/test/images/efuse/esp_efuse_custom_table.csv new file mode 100644 index 000000000..bb784a998 --- /dev/null +++ b/test/images/efuse/esp_efuse_custom_table.csv @@ -0,0 +1,13 @@ +# field_name, | efuse_block, | bit_start, | bit_count, | comment +MODULE_VERSION, EFUSE_BLK3, 56, 8, Module version +DEVICE_ROLE, EFUSE_BLK3, 64, 3, Device role +SETTING_1, EFUSE_BLK3, 67, 6, [SETTING_1_ALT_NAME] Setting 1 +SETTING_2, EFUSE_BLK3, 73, 5, Setting 2 +ID_NUM, EFUSE_BLK3, 140, 8, [MY_ID_NUM] comment +, EFUSE_BLK3, 132, 8, [MY_ID_NUM] comment +, EFUSE_BLK3, 122, 8, [MY_ID_NUM] comment +CUSTOM_SECURE_VERSION, EFUSE_BLK3, 78, 16, Custom secure version +ID_NUMK, EFUSE_BLK3, 150, 8, [MY_ID_NUMK] comment +, EFUSE_BLK3, 182, 8, [MY_ID_NUMK] comment +MY_DATA, EFUSE_BLK3, 190, 10, My data +MY_DATA.FIELD1, EFUSE_BLK3, 190, 7, Field1 \ No newline at end of file diff --git a/test/test_espefuse.py b/test/test_espefuse.py index 26daf8c49..40adf0669 100755 --- a/test/test_espefuse.py +++ b/test/test_espefuse.py @@ -2101,3 +2101,32 @@ def test_postpone_efuses(self): assert "Burn postponed efuses from BLOCK0" in output assert "BURN BLOCK0 - OK" in output assert "Successful" in output + + +class TestCSVEfuseTable(EfuseTestCase): + def test_extend_efuse_table_with_csv_file(self): + csv_file = f"{IMAGES_DIR}/esp_efuse_custom_table.csv" + output = self.espefuse_py(f" --extend-efuse-table {csv_file} summary") + assert "MODULE_VERSION (BLOCK3)" in output + assert "DEVICE_ROLE (BLOCK3)" in output + assert "SETTING_2 (BLOCK3)" in output + assert "ID_NUM_0 (BLOCK3)" in output + assert "ID_NUM_1 (BLOCK3)" in output + assert "ID_NUM_2 (BLOCK3)" in output + assert "CUSTOM_SECURE_VERSION (BLOCK3)" in output + assert "ID_NUMK_0 (BLOCK3)" in output + assert "ID_NUMK_1 (BLOCK3)" in output + + self.espefuse_py( + f"--extend-efuse-table {csv_file} burn_efuse \ + MODULE_VERSION 1 \ + CUSTOM_SECURE_VERSION 4 \ + SETTING_1_ALT_NAME 7 \ + SETTING_2 1 \ + ID_NUM_0 1 \ + ID_NUM_1 1 \ + ID_NUM_2 1 \ + MY_ID_NUMK_0 1 \ + MY_ID_NUMK_1 1 \ + MY_DATA_FIELD1 1" + ) From d3651ac6732112eed027f7a78457f0d1539c391f Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 16 May 2024 09:50:55 +0300 Subject: [PATCH 197/209] feat(esptool): Print key_purpose name for get_security_info cmd --- esptool/cmds.py | 11 ++++++++++- esptool/targets/esp32.py | 4 +++- esptool/targets/esp32c2.py | 3 +++ esptool/targets/esp32c3.py | 25 ++++++++++++++++++++++--- esptool/targets/esp32c5.py | 18 ++++++++++++++++++ esptool/targets/esp32c5beta3.py | 18 ++++++++++++++++++ esptool/targets/esp32c6.py | 10 +++++++--- esptool/targets/esp32c61.py | 21 +++++++++++++++++++++ esptool/targets/esp32h2.py | 18 ++++++++++++++++++ esptool/targets/esp32h2beta1.py | 26 +++++++++++++++++++++++--- esptool/targets/esp32p4.py | 28 +++++++++++++++++++++++++--- esptool/targets/esp32s2.py | 27 ++++++++++++++++++++++++--- esptool/targets/esp32s3.py | 27 ++++++++++++++++++++++++--- test/test_esptool.py | 3 ++- 14 files changed, 218 insertions(+), 21 deletions(-) diff --git a/esptool/cmds.py b/esptool/cmds.py index 4d9975ea4..a76fdebb3 100644 --- a/esptool/cmds.py +++ b/esptool/cmds.py @@ -1284,7 +1284,16 @@ def get_security_info(esp, args): print(title) print("=" * len(title)) print("Flags: {:#010x} ({})".format(si["flags"], bin(si["flags"]))) - print("Key Purposes: {}".format(si["key_purposes"])) + if esp.KEY_PURPOSES: + print(f"Key Purposes: {si['key_purposes']}") + desc = "\n ".join( + [ + f"BLOCK_KEY{key_num} - {esp.KEY_PURPOSES.get(purpose, 'UNKNOWN')}" + for key_num, purpose in enumerate(si["key_purposes"]) + if key_num <= esp.EFUSE_MAX_KEY + ] + ) + print(f" {desc}") if si["chip_id"] is not None and si["api_version"] is not None: print("Chip ID: {}".format(si["chip_id"])) print("API Version: {}".format(si["api_version"])) diff --git a/esptool/targets/esp32.py b/esptool/targets/esp32.py index 2b2a2bbc4..a42e68dd5 100644 --- a/esptool/targets/esp32.py +++ b/esptool/targets/esp32.py @@ -5,7 +5,7 @@ import struct import time -from typing import Optional +from typing import Dict, Optional from ..loader import ESPLoader from ..util import FatalError, NotSupportedError @@ -125,6 +125,8 @@ class ESP32ROM(ESPLoader): UF2_FAMILY_ID = 0x1C5F21B0 + KEY_PURPOSES: Dict[int, str] = {} + """ Try to read the BLOCK1 (encryption key) and check if it is valid """ def is_flash_encryption_key_valid(self): diff --git a/esptool/targets/esp32c2.py b/esptool/targets/esp32c2.py index 3f59eb5d0..3ed9df8dc 100644 --- a/esptool/targets/esp32c2.py +++ b/esptool/targets/esp32c2.py @@ -5,6 +5,7 @@ import struct import time +from typing import Dict from .esp32c3 import ESP32C3ROM from ..loader import ESPLoader @@ -64,6 +65,8 @@ class ESP32C2ROM(ESP32C3ROM): UF2_FAMILY_ID = 0x2B88D29C + KEY_PURPOSES: Dict[int, str] = {} + def get_pkg_version(self): num_word = 1 return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 22) & 0x07 diff --git a/esptool/targets/esp32c3.py b/esptool/targets/esp32c3.py index 0ef0905c9..23364fb31 100644 --- a/esptool/targets/esp32c3.py +++ b/esptool/targets/esp32c3.py @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import struct +from typing import Dict from .esp32 import ESP32ROM from ..loader import ESPLoader @@ -99,6 +100,20 @@ class ESP32C3ROM(ESP32ROM): UF2_FAMILY_ID = 0xD42BA06C + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "RESERVED", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + } + def get_pkg_version(self): num_word = 3 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07 @@ -179,8 +194,10 @@ def get_secure_boot_enabled(self): ) def get_key_block_purpose(self, key_block): - if key_block < 0 or key_block > 5: - raise FatalError("Valid key block numbers must be in range 0-5") + if key_block < 0 or key_block > self.EFUSE_MAX_KEY: + raise FatalError( + f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}" + ) reg, shift = [ (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT), @@ -194,7 +211,9 @@ def get_key_block_purpose(self, key_block): def is_flash_encryption_key_valid(self): # Need to see an AES-128 key - purposes = [self.get_key_block_purpose(b) for b in range(6)] + purposes = [ + self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1) + ] return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes) diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py index 51d52effd..37f43bee8 100644 --- a/esptool/targets/esp32c5.py +++ b/esptool/targets/esp32c5.py @@ -4,6 +4,7 @@ import struct import time +from typing import Dict from .esp32c6 import ESP32C6ROM from ..loader import ESPLoader @@ -52,6 +53,23 @@ class ESP32C5ROM(ESP32C6ROM): UF2_FAMILY_ID = 0xF71C0343 + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "ECDSA_KEY", + 2: "XTS_AES_256_KEY_1", + 3: "XTS_AES_256_KEY_2", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + 12: "KM_INIT_KEY", + } + def get_chip_description(self): chip_name = { 0: "ESP32-C5", diff --git a/esptool/targets/esp32c5beta3.py b/esptool/targets/esp32c5beta3.py index 0eeedc710..fd7795b3c 100644 --- a/esptool/targets/esp32c5beta3.py +++ b/esptool/targets/esp32c5beta3.py @@ -4,6 +4,7 @@ import struct import time +from typing import Dict from .esp32c6 import ESP32C6ROM from ..loader import ESPLoader @@ -41,6 +42,23 @@ class ESP32C5BETA3ROM(ESP32C6ROM): [0x600FE000, 0x60100000, "MEM_INTERNAL2"], ] + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "ECDSA_KEY", + 2: "XTS_AES_256_KEY_1", + 3: "XTS_AES_256_KEY_2", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + 12: "KM_INIT_KEY", + } + def get_chip_description(self): chip_name = { 0: "ESP32-C5 beta3 (QFN40)", diff --git a/esptool/targets/esp32c6.py b/esptool/targets/esp32c6.py index 0004afeb4..c78e1f72a 100644 --- a/esptool/targets/esp32c6.py +++ b/esptool/targets/esp32c6.py @@ -161,8 +161,10 @@ def get_secure_boot_enabled(self): ) def get_key_block_purpose(self, key_block): - if key_block < 0 or key_block > 5: - raise FatalError("Valid key block numbers must be in range 0-5") + if key_block < 0 or key_block > self.EFUSE_MAX_KEY: + raise FatalError( + f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}" + ) reg, shift = [ (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT), @@ -176,7 +178,9 @@ def get_key_block_purpose(self, key_block): def is_flash_encryption_key_valid(self): # Need to see an AES-128 key - purposes = [self.get_key_block_purpose(b) for b in range(6)] + purposes = [ + self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1) + ] return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes) diff --git a/esptool/targets/esp32c61.py b/esptool/targets/esp32c61.py index 58867a433..dd7f09ef7 100644 --- a/esptool/targets/esp32c61.py +++ b/esptool/targets/esp32c61.py @@ -3,6 +3,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import struct +from typing import Dict from .esp32c6 import ESP32C6ROM @@ -60,6 +61,26 @@ class ESP32C61ROM(ESP32C6ROM): UF2_FAMILY_ID = 0x77D850C4 + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "ECDSA_KEY", + 2: "XTS_AES_256_KEY_1", + 3: "XTS_AES_256_KEY_2", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + 12: "KM_INIT_KEY", + 13: "XTS_AES_256_KEY_1_PSRAM", + 14: "XTS_AES_256_KEY_2_PSRAM", + 15: "XTS_AES_128_KEY_PSRAM", + } + def get_chip_description(self): chip_name = { 0: "ESP32-C61", diff --git a/esptool/targets/esp32h2.py b/esptool/targets/esp32h2.py index b042cd7a1..da7d34a58 100644 --- a/esptool/targets/esp32h2.py +++ b/esptool/targets/esp32h2.py @@ -3,6 +3,8 @@ # # SPDX-License-Identifier: GPL-2.0-or-later +from typing import Dict + from .esp32c6 import ESP32C6ROM from ..util import FatalError @@ -32,6 +34,22 @@ class ESP32H2ROM(ESP32C6ROM): UF2_FAMILY_ID = 0x332726F6 + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "ECDSA_KEY", + 2: "XTS_AES_256_KEY_1", + 3: "XTS_AES_256_KEY_2", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + } + def get_pkg_version(self): num_word = 4 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07 diff --git a/esptool/targets/esp32h2beta1.py b/esptool/targets/esp32h2beta1.py index 117e5fb6b..999a16e08 100644 --- a/esptool/targets/esp32h2beta1.py +++ b/esptool/targets/esp32h2beta1.py @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import struct +from typing import Dict from .esp32c3 import ESP32C3ROM from ..util import FatalError, NotImplementedInROMError @@ -77,6 +78,21 @@ class ESP32H2BETA1ROM(ESP32C3ROM): "12m": 0x2, } + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "ECDSA_KEY", + 2: "RESERVED", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + } + def get_pkg_version(self): num_word = 4 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07 @@ -121,8 +137,10 @@ def get_flash_crypt_config(self): return None # doesn't exist on ESP32-H2 def get_key_block_purpose(self, key_block): - if key_block < 0 or key_block > 5: - raise FatalError("Valid key block numbers must be in range 0-5") + if key_block < 0 or key_block > self.EFUSE_MAX_KEY: + raise FatalError( + f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}" + ) reg, shift = [ (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT), @@ -136,7 +154,9 @@ def get_key_block_purpose(self, key_block): def is_flash_encryption_key_valid(self): # Need to see an AES-128 key - purposes = [self.get_key_block_purpose(b) for b in range(6)] + purposes = [ + self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1) + ] return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes) diff --git a/esptool/targets/esp32p4.py b/esptool/targets/esp32p4.py index fc5c9e4c8..10b8c2e35 100644 --- a/esptool/targets/esp32p4.py +++ b/esptool/targets/esp32p4.py @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later import struct +from typing import Dict from .esp32 import ESP32ROM from ..loader import ESPLoader @@ -85,6 +86,23 @@ class ESP32P4ROM(ESP32ROM): UF2_FAMILY_ID = 0x3D308E94 + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "ECDSA_KEY", + 2: "XTS_AES_256_KEY_1", + 3: "XTS_AES_256_KEY_2", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + 12: "KM_INIT_KEY", + } + def get_pkg_version(self): num_word = 2 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 27) & 0x07 @@ -139,8 +157,10 @@ def get_secure_boot_enabled(self): ) def get_key_block_purpose(self, key_block): - if key_block < 0 or key_block > 5: - raise FatalError("Valid key block numbers must be in range 0-5") + if key_block < 0 or key_block > self.EFUSE_MAX_KEY: + raise FatalError( + f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}" + ) reg, shift = [ (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT), @@ -154,7 +174,9 @@ def get_key_block_purpose(self, key_block): def is_flash_encryption_key_valid(self): # Need to see either an AES-128 key or two AES-256 keys - purposes = [self.get_key_block_purpose(b) for b in range(6)] + purposes = [ + self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1) + ] if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes): return True diff --git a/esptool/targets/esp32s2.py b/esptool/targets/esp32s2.py index 5c7c6b7bb..6af2842f7 100644 --- a/esptool/targets/esp32s2.py +++ b/esptool/targets/esp32s2.py @@ -5,6 +5,7 @@ import os import struct +from typing import Dict from .esp32 import ESP32ROM from ..loader import ESPLoader @@ -107,6 +108,22 @@ class ESP32S2ROM(ESP32ROM): UF2_FAMILY_ID = 0xBFDD4EEE + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "RESERVED", + 2: "XTS_AES_256_KEY_1", + 3: "XTS_AES_256_KEY_2", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + } + def get_pkg_version(self): num_word = 4 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F @@ -224,8 +241,10 @@ def get_secure_boot_enabled(self): ) def get_key_block_purpose(self, key_block): - if key_block < 0 or key_block > 5: - raise FatalError("Valid key block numbers must be in range 0-5") + if key_block < 0 or key_block > self.EFUSE_MAX_KEY: + raise FatalError( + f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}" + ) reg, shift = [ (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT), @@ -239,7 +258,9 @@ def get_key_block_purpose(self, key_block): def is_flash_encryption_key_valid(self): # Need to see either an AES-128 key or two AES-256 keys - purposes = [self.get_key_block_purpose(b) for b in range(6)] + purposes = [ + self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1) + ] if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes): return True diff --git a/esptool/targets/esp32s3.py b/esptool/targets/esp32s3.py index 04c3c0ef4..06fb129eb 100644 --- a/esptool/targets/esp32s3.py +++ b/esptool/targets/esp32s3.py @@ -5,6 +5,7 @@ import os import struct +from typing import Dict from .esp32 import ESP32ROM from ..loader import ESPLoader @@ -123,6 +124,22 @@ class ESP32S3ROM(ESP32ROM): UF2_FAMILY_ID = 0xC47E5767 + EFUSE_MAX_KEY = 5 + KEY_PURPOSES: Dict[int, str] = { + 0: "USER/EMPTY", + 1: "RESERVED", + 2: "XTS_AES_256_KEY_1", + 3: "XTS_AES_256_KEY_2", + 4: "XTS_AES_128_KEY", + 5: "HMAC_DOWN_ALL", + 6: "HMAC_DOWN_JTAG", + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", + 8: "HMAC_UP", + 9: "SECURE_BOOT_DIGEST0", + 10: "SECURE_BOOT_DIGEST1", + 11: "SECURE_BOOT_DIGEST2", + } + def get_pkg_version(self): num_word = 3 return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07 @@ -227,8 +244,10 @@ def get_flash_crypt_config(self): return None # doesn't exist on ESP32-S3 def get_key_block_purpose(self, key_block): - if key_block < 0 or key_block > 5: - raise FatalError("Valid key block numbers must be in range 0-5") + if key_block < 0 or key_block > self.EFUSE_MAX_KEY: + raise FatalError( + f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}" + ) reg, shift = [ (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT), @@ -242,7 +261,9 @@ def get_key_block_purpose(self, key_block): def is_flash_encryption_key_valid(self): # Need to see either an AES-128 key or two AES-256 keys - purposes = [self.get_key_block_purpose(b) for b in range(6)] + purposes = [ + self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1) + ] if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes): return True diff --git a/test/test_esptool.py b/test/test_esptool.py index 438748bb6..46e93950d 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -670,7 +670,8 @@ def test_show_security_info(self): res = self.run_esptool("get_security_info") assert "Flags" in res assert "Crypt Count" in res - assert "Key Purposes" in res + if arg_chip != "esp32c2": + assert "Key Purposes" in res if arg_chip != "esp32s2": try: esp = esptool.get_default_connected_device( From b2af8da8feeddb4d5e2286faf9d8ae5419da6200 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 18 Jun 2024 10:51:10 +0200 Subject: [PATCH 198/209] change: use pyproject.toml instead of setup.py --- pyproject.toml | 71 +++++++++++++++++++++++++++++ setup.py | 120 +------------------------------------------------ 2 files changed, 73 insertions(+), 118 deletions(-) create mode 100644 pyproject.toml diff --git a/pyproject.toml b/pyproject.toml new file mode 100644 index 000000000..bf3c665e3 --- /dev/null +++ b/pyproject.toml @@ -0,0 +1,71 @@ +[build-system] + requires = ["setuptools>=64"] + build-backend = "setuptools.build_meta" + +[project] + name = "esptool" + authors = [ + {name = "Fredrik Ahlberg (themadinventor)"}, + {name = "Angus Gratton (projectgus)"}, + {name = "Espressif Systems"} + ] + readme = {file = "README.md", content-type = "text/markdown"} + license = {text = "GPLv2+"} + description = "A serial utility to communicate & flash code to Espressif chips." + classifiers = [ + "Development Status :: 5 - Production/Stable", + "Intended Audience :: Developers", + "Natural Language :: English", + "Operating System :: POSIX", + "Operating System :: Microsoft :: Windows", + "Operating System :: MacOS :: MacOS X", + "Topic :: Software Development :: Embedded Systems", + "Environment :: Console", + "License :: OSI Approved :: GNU General Public License v2 or later (GPLv2+)", + "Programming Language :: Python :: 3.7", + "Programming Language :: Python :: 3.8", + "Programming Language :: Python :: 3.9", + "Programming Language :: Python :: 3.10", + "Programming Language :: Python :: 3.11", + "Programming Language :: Python :: 3.12", + ] + requires-python = ">=3.7" + dynamic = ["version", "scripts"] + + dependencies = [ + "bitstring>=3.1.6", + "cryptography>=2.1.4", + "ecdsa>=0.16.0", + "pyserial>=3.3", + "reedsolo>=1.5.3,<1.8", + "PyYAML>=5.1", + "intelhex", + ] + +[project.urls] + Homepage = "https://github.com/espressif/esptool/" + Documentation = "https://docs.espressif.com/projects/esptool/" + Source = "https://github.com/espressif/esptool/" + Tracker = "https://github.com/espressif/esptool/issues/" + Changelog = "https://github.com/espressif/esptool/blob/master/CHANGELOG.md" + +[project.optional-dependencies] + dev = [ + "pyelftools", + "coverage~=6.0", + "pre-commit", + "pytest", + "pytest-rerunfailures", + "requests", + "commitizen", + ] + hsm = ["python-pkcs11"] + +[tool.setuptools] + include-package-data = true + +[tool.setuptools.package-data] + "*" = ["esptool/targets/stub_flasher/*.json"] + +[tool.setuptools.packages] + find = {exclude = ["ci", "flasher_stub", "test", "docs"]} diff --git a/setup.py b/setup.py index 2e5fa78e9..0655e3c19 100644 --- a/setup.py +++ b/setup.py @@ -1,41 +1,5 @@ -# SPDX-FileCopyrightText: 2014-2023 Fredrik Ahlberg, Angus Gratton, -# Espressif Systems (Shanghai) CO LTD, other contributors as noted. -# -# SPDX-License-Identifier: GPL-2.0-or-later - -import io import os -import re -import sys - -try: - from setuptools import find_packages, setup -except ImportError: - print( - "Package setuptools is missing from your Python installation. " - "Please see the installation section in the esptool documentation" - " for instructions on how to install it." - ) - sys.exit(1) - - -# Example code to pull version from esptool module with regex, taken from -# https://packaging.python.org/en/latest/guides/single-sourcing-package-version/ -def read(*names, **kwargs): - with io.open( - os.path.join(os.path.dirname(__file__), *names), - encoding=kwargs.get("encoding", "utf8"), - ) as fp: - return fp.read() - - -def find_version(*file_paths): - version_file = read(*file_paths) - version_match = re.search(r"^__version__ = ['\"]([^'\"]*)['\"]", version_file, re.M) - if version_match: - return version_match.group(1) - raise RuntimeError("Unable to find version string.") - +from setuptools import setup if os.name != "nt": scripts = ["esptool.py", "espefuse.py", "espsecure.py", "esp_rfc2217_server.py"] @@ -51,87 +15,7 @@ def find_version(*file_paths): ], } - -long_description = """ -========== -esptool.py -========== -A Python-based, open-source, platform-independent utility to communicate with \ -the ROM bootloader in Espressif chips. - -The esptool.py project is `hosted on github `_. - -Documentation -------------- -Visit online `esptool documentation `_ \ -or run ``esptool.py -h``. - -Contributing ------------- -Please see the `contributions guide \ -`_. -""" - setup( - name="esptool", - version=find_version("esptool/__init__.py"), - description="A serial utility to communicate & flash code to Espressif chips.", - long_description=long_description, - url="https://github.com/espressif/esptool/", - project_urls={ - "Documentation": "https://docs.espressif.com/projects/esptool/", - "Source": "https://github.com/espressif/esptool/", - "Tracker": "https://github.com/espressif/esptool/issues/", - }, - author="Fredrik Ahlberg (themadinventor) & Angus Gratton (projectgus) " - "& Espressif Systems", - author_email="", - license="GPLv2+", - classifiers=[ - "Development Status :: 5 - Production/Stable", - "Intended Audience :: Developers", - "Natural Language :: English", - "Operating System :: POSIX", - "Operating System :: Microsoft :: Windows", - "Operating System :: MacOS :: MacOS X", - "Topic :: Software Development :: Embedded Systems", - "Environment :: Console", - "License :: OSI Approved :: GNU General Public License v2 or later (GPLv2+)", - "Programming Language :: Python :: 3.7", - "Programming Language :: Python :: 3.8", - "Programming Language :: Python :: 3.9", - "Programming Language :: Python :: 3.10", - "Programming Language :: Python :: 3.11", - "Programming Language :: Python :: 3.12", - ], - python_requires=">=3.7", - setup_requires=(["wheel"] if "bdist_wheel" in sys.argv else []), - extras_require={ - "dev": [ - "pyelftools", - "coverage~=6.0", - "pre-commit", - "pytest", - "pytest-rerunfailures", - "requests", - "commitizen", - ], - "hsm": [ - "python-pkcs11", - ], - }, - install_requires=[ - "bitstring>=3.1.6", - "cryptography>=2.1.4", - "ecdsa>=0.16.0", - "pyserial>=3.3", - "reedsolo>=1.5.3,<1.8", - "PyYAML>=5.1", - "intelhex", - ], - packages=find_packages(), - include_package_data=True, - package_data={"": ["esptool/targets/stub_flasher/*.json"]}, - entry_points=entry_points, scripts=scripts, + entry_points=entry_points, ) From 8681f0da2f67746b20137ee8ad616bddf60a921d Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 18 Jun 2024 11:47:26 +0200 Subject: [PATCH 199/209] change: move tools configuration to pyproject.toml --- .codespellrc | 4 -- .cz.toml | 24 ----------- .mypy.ini | 13 ------ .pre-commit-config.yaml | 2 + .ruff.toml | 59 -------------------------- pyproject.toml | 94 +++++++++++++++++++++++++++++++++++++++++ 6 files changed, 96 insertions(+), 100 deletions(-) delete mode 100644 .codespellrc delete mode 100644 .cz.toml delete mode 100644 .mypy.ini delete mode 100644 .ruff.toml diff --git a/.codespellrc b/.codespellrc deleted file mode 100644 index 3f052e961..000000000 --- a/.codespellrc +++ /dev/null @@ -1,4 +0,0 @@ -[codespell] -skip = *.bin,test/images/efuse/*,docs/en/espefuse/inc/* -ignore-words-list = bloc,ser,dout,exten -write-changes = false diff --git a/.cz.toml b/.cz.toml deleted file mode 100644 index cca4ea574..000000000 --- a/.cz.toml +++ /dev/null @@ -1,24 +0,0 @@ -[tool.commitizen] -version = "4.7.0" -update_changelog_on_bump = true -tag_format = "v$version" -changelog_start_rev = "v4.2.1" -changelog_merge_prerelease = true -annotated_tag = true -bump_message = "change: Update version to $new_version" -version_files = [ - "esptool/__init__.py:__version__" -] -change_type_order = [ - "BREAKING CHANGE", - "New Features", - "Bug Fixes", - "Code Refactoring", - "Performance Improvements" -] - -[tool.commitizen.change_type_map] -feat = "New Features" -fix = "Bug Fixes" -refactor = "Code Refactoring" -perf = "Performance Improvements" \ No newline at end of file diff --git a/.mypy.ini b/.mypy.ini deleted file mode 100644 index d836b95ac..000000000 --- a/.mypy.ini +++ /dev/null @@ -1,13 +0,0 @@ -[mypy] - # Disallows defining functions with incomplete type annotations - disallow_incomplete_defs = false - # Disallows defining functions without type annotations or with incomplete type annotations - disallow_untyped_defs = false - # Suppress error messages about imports that cannot be resolved - ignore_missing_imports = true - # Specifies the Python version used to parse and check the target program - python_version = 3.9 - # Shows errors for missing return statements on some execution paths - warn_no_return = true - # Shows a warning when returning a value with type Any from a function declared with a non- Any return type - warn_return_any = true diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index d1286ad0a..9d48ead66 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -22,6 +22,8 @@ repos: rev: v2.2.5 hooks: - id: codespell + additional_dependencies: + - tomli - repo: https://github.com/espressif/conventional-precommit-linter rev: v1.4.0 hooks: diff --git a/.ruff.toml b/.ruff.toml deleted file mode 100644 index 1a1d17fda..000000000 --- a/.ruff.toml +++ /dev/null @@ -1,59 +0,0 @@ -# https://docs.astral.sh/ruff/settings/ -# Exclude a variety of commonly ignored directories. -exclude = [ - ".eggs", - ".git", - "__pycache__" -] - -line-length = 88 - -select = ['E', 'F', 'W'] -ignore = ["E203"] - -# Assume Python 3.7 -target-version = "py37" - -[per-file-ignores] - - -# tests often manipulate sys.path before importing the main tools, so ignore import order violations -"test/*.py" = ["E402"] - -# multiple spaces after ',' and long lines - used for visual layout of eFuse data -"espefuse/efuse/*/mem_definition.py" = ["E241", "E501"] -"espefuse/efuse/*/operations.py" = ["E241", "E501", "F401"] -"espefuse/efuse/*/fields.py" = ["E241", "E501"] - -# ignore long lines - used for RS encoding pairs -"test/test_modules.py" = ["E501"] - -# don't check for unused imports in __init__.py files -"__init__.py" = ["F401"] - -# allow definition from star imports in docs config -"docs/conf_common.py" = ["F405"] - - - -[lint] -# Enable Pyflakes (`F`) and a subset of the pycodestyle (`E`) codes by default. -# Unlike Flake8, Ruff doesn't enable pycodestyle warnings (`W`) or -# McCabe complexity (`C901`) by default. -select = ["E4", "E7", "E9", "F"] -ignore = [] - -# Allow fix for all enabled rules (when `--fix`) is provided. -fixable = ["ALL"] -unfixable = [] - -# Allow unused variables when underscore-prefixed. -dummy-variable-rgx = "^(_+|(_+[a-zA-Z0-9_]*[a-zA-Z0-9]+?))$" - - -# ruff-format hook configuration -[format] -quote-style = "double" -indent-style = "space" -docstring-code-format = true - diff --git a/pyproject.toml b/pyproject.toml index bf3c665e3..0bd52b19a 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -69,3 +69,97 @@ [tool.setuptools.packages] find = {exclude = ["ci", "flasher_stub", "test", "docs"]} + +[tool.setuptools.dynamic] + version = {attr = "esptool.__init__.__version__"} + +[tool.commitizen] + version = "4.7.0" + update_changelog_on_bump = true + tag_format = "v$version" + changelog_start_rev = "v4.2.1" + changelog_merge_prerelease = true + annotated_tag = true + bump_message = "change: Update version to $new_version" + version_files = [ + "esptool/__init__.py:__version__" + ] + change_type_order = [ + "BREAKING CHANGE", + "New Features", + "Bug Fixes", + "Code Refactoring", + "Performance Improvements" + ] + +[tool.commitizen.change_type_map] + feat = "New Features" + fix = "Bug Fixes" + refactor = "Code Refactoring" + perf = "Performance Improvements" + +[tool.codespell] + skip = '*.bin,*test/images/efuse/*,*docs/en/espefuse/inc/*' + ignore-words-list = 'bloc,ser,dout,exten' + write-changes = false + +[tool.mypy] + disallow_incomplete_defs = false # Disallows defining functions with incomplete type annotations + disallow_untyped_defs = false # Disallows defining functions without type annotations or with incomplete type annotations + ignore_missing_imports = true # Suppress error messages about imports that cannot be resolved + python_version = "3.7" # Specifies the Python version used to parse and check the target program + warn_no_return = true # Shows errors for missing return statements on some execution paths + warn_return_any = true # Shows a warning when returning a value with type Any from a function declared with a non- Any return type + +[tool.ruff] + # https://docs.astral.sh/ruff/settings/ + # Exclude a variety of commonly ignored directories. + exclude = [ + ".eggs", + ".git", + "__pycache__" + ] + + line-length = 88 + + select = ['E', 'F', 'W'] + ignore = ["E203"] + + target-version = "py37" + +[tool.ruff.lint] + # Enable Pyflakes (`F`) and a subset of the pycodestyle (`E`) codes by default. + # Unlike Flake8, Ruff doesn't enable pycodestyle warnings (`W`) or + # McCabe complexity (`C901`) by default. + select = ["E4", "E7", "E9", "F"] + ignore = [] + + # Allow fix for all enabled rules (when `--fix`) is provided. + fixable = ["ALL"] + unfixable = [] + + # Allow unused variables when underscore-prefixed. + dummy-variable-rgx = "^(_+|(_+[a-zA-Z0-9_]*[a-zA-Z0-9]+?))$" + +[tool.ruff.lint.per-file-ignores] + # tests often manipulate sys.path before importing the main tools, so ignore import order violations + "test/*.py" = ["E402"] + + # multiple spaces after ',' and long lines - used for visual layout of eFuse data + "espefuse/efuse/*/mem_definition.py" = ["E241", "E501"] + "espefuse/efuse/*/operations.py" = ["E241", "E501", "F401"] + "espefuse/efuse/*/fields.py" = ["E241", "E501"] + + # ignore long lines - used for RS encoding pairs + "test/test_modules.py" = ["E501"] + + # don't check for unused imports in __init__.py files + "__init__.py" = ["F401"] + + # allow definition from star imports in docs config + "docs/conf_common.py" = ["F405"] + +[tool.ruff.format] + quote-style = "double" + indent-style = "space" + docstring-code-format = true From 39768fb1c018d1a100e78795ba39d59deef4e60b Mon Sep 17 00:00:00 2001 From: Jakub Kocka Date: Thu, 20 Jun 2024 14:12:41 +0200 Subject: [PATCH 200/209] ci(host_tests): Split target jobs and run in parallel --- .gitlab-ci.yml | 40 +++++++++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c8d89690c..e247a38bf 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -104,19 +104,33 @@ host_tests: - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_merge_bin.py - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_image_info.py - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_modules.py - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c2 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c3 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32s2 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32s3 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32s3beta2 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2beta1 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c5 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c5beta3 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c6 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32c61 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32h2 - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip esp32p4 + # some .coverage files in sub-directories are not collected on some runners, move them firs + - find . -mindepth 2 -type f -name ".coverage*" -print -exec mv --backup=numbered {} . \; + +host_tests_espefuse: + <<: *host_tests_template + variables: + PYTHONPATH: "$PYTHONPATH:${CI_PROJECT_DIR}/test" + COVERAGE_PROCESS_START: "${CI_PROJECT_DIR}/test/.covconf" + PYTEST_ADDOPTS: "-sv --junitxml=test/report.xml --color=yes" + parallel: + matrix: + - TARGET: + - esp32 + - esp32c2 + - esp32c3 + - esp32c5 + - esp32c5beta3 + - esp32c6 + - esp32c61 + - esp32h2 + - esp32h2beta1 + - esp32p4 + - esp32s2 + - esp32s3 + - esp32s3beta2 + script: + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_espefuse.py --chip ${TARGET} # some .coverage files in sub-directories are not collected on some runners, move them first - find . -mindepth 2 -type f -name ".coverage*" -print -exec mv --backup=numbered {} . \; From a1afaa54a16f75d43eb796ecb8503eb420eb661a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Mon, 24 Jun 2024 15:44:43 +0200 Subject: [PATCH 201/209] change(port_detection): Filter out BT and WLAN debug serial ports on MacOS Related to https://github.com/espressif/esp-idf/issues/14058 --- esptool/__init__.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index bc4d102c7..b66a2f1b0 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -1006,7 +1006,14 @@ def get_port_list(): "Please try to specify the port when running esptool.py or update " "the pyserial package to the latest version" ) - return sorted(ports.device for ports in list_ports.comports()) + port_list = sorted(ports.device for ports in list_ports.comports()) + if sys.platform == "darwin": + port_list = [ + port + for port in port_list + if not port.endswith(("Bluetooth-Incoming-Port", "wlan-debug")) + ] + return port_list def expand_file_arguments(argv): From 7df0218aedc46854ffba77169e6755c72114bbc5 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Thu, 27 Jun 2024 10:53:48 +0200 Subject: [PATCH 202/209] ci: fix esptool_lint GitHub action --- .github/workflows/test_esptool.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/test_esptool.yml b/.github/workflows/test_esptool.yml index e464e9559..f398f650c 100644 --- a/.github/workflows/test_esptool.yml +++ b/.github/workflows/test_esptool.yml @@ -69,6 +69,11 @@ jobs: - name: Checkout uses: actions/checkout@master + - name: Set up Python 3.7 + uses: actions/setup-python@master + with: + python-version: 3.7 + - name: Run pre-commit hooks run: | pip install --extra-index-url https://dl.espressif.com/pypi -e .[dev] From 9388ff43550a5acab2a9f12a980036c1f753c0cf Mon Sep 17 00:00:00 2001 From: Jaroslav Burian Date: Wed, 26 Jun 2024 09:22:00 +0200 Subject: [PATCH 203/209] ci(pre-commit): Update version of commit-linter Update of conventional-commi-linter because of not working with Python version 3.12. UnicodeEncodeError: 'charmap' codec can't encode character '\u274c' in position 2: character maps to --- .pre-commit-config.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 9d48ead66..7ffcb4f38 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -25,7 +25,7 @@ repos: additional_dependencies: - tomli - repo: https://github.com/espressif/conventional-precommit-linter - rev: v1.4.0 + rev: v1.9.0 hooks: - id: conventional-precommit-linter stages: [commit-msg] From 4cc923f6ee8c8824d2885b44e8ff583899cea80c Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Fri, 19 Apr 2024 12:44:21 +0300 Subject: [PATCH 204/209] feat(esp32c5): Add UART stub support --- esptool/targets/esp32c5.py | 33 +- .../stub_flasher/stub_flasher_32c5.json | 8 + .../stub_flasher/stub_flasher_32c5beta3.json | 8 +- flasher_stub/Makefile | 6 + flasher_stub/compare_stubs.py | 3 +- flasher_stub/include/rom_functions.h | 4 +- flasher_stub/include/soc_support.h | 31 +- flasher_stub/ld/rom_32c5.ld | 483 ++++++++++++++++++ flasher_stub/ld/rom_32c5_beta_3.ld | 165 ++++++ flasher_stub/ld/stub_32c5.ld | 26 + flasher_stub/stub_flasher.c | 6 +- .../ram_helloworld/helloworld-esp32c5.bin | Bin 0 -> 128 bytes test/images/ram_helloworld/source/Makefile | 9 +- .../ram_helloworld/source/ld/app_32c5.ld | 26 + 14 files changed, 784 insertions(+), 24 deletions(-) create mode 100644 esptool/targets/stub_flasher/stub_flasher_32c5.json create mode 100755 flasher_stub/ld/rom_32c5.ld create mode 100644 flasher_stub/ld/stub_32c5.ld create mode 100644 test/images/ram_helloworld/helloworld-esp32c5.bin create mode 100644 test/images/ram_helloworld/source/ld/app_32c5.ld diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py index 37f43bee8..a07135e12 100644 --- a/esptool/targets/esp32c5.py +++ b/esptool/targets/esp32c5.py @@ -9,6 +9,7 @@ from .esp32c6 import ESP32C6ROM from ..loader import ESPLoader from ..reset import HardReset +from ..util import FatalError class ESP32C5ROM(ESP32C6ROM): @@ -29,7 +30,7 @@ class ESP32C5ROM(ESP32C6ROM): UARTDEV_BUF_NO = 0x4085F51C # Variable in ROM .bss which indicates the port in use # Magic value for ESP32C5 - CHIP_DETECT_MAGIC_VALUE = [0x8082C5DC] + CHIP_DETECT_MAGIC_VALUE = [0x1101406F] FLASH_FREQUENCY = { "80m": 0xF, @@ -119,5 +120,33 @@ def change_baud(self, baud): else: ESPLoader.change_baud(self, baud) + def check_spi_connection(self, spi_connection): + if not set(spi_connection).issubset(set(range(0, 29))): + raise FatalError("SPI Pin numbers must be in the range 0-28.") + if any([v for v in spi_connection if v in [13, 14]]): + print( + "WARNING: GPIO pins 13 and 14 are used by USB-Serial/JTAG, " + "consider using other pins for SPI flash connection." + ) + + +class ESP32C5StubLoader(ESP32C5ROM): + """Access class for ESP32C5 stub loader, runs on top of ROM. + + (Basically the same as ESP32StubLoader, but different base class. + Can possibly be made into a mixin.) + """ + + FLASH_WRITE_SIZE = 0x4000 # matches MAX_WRITE_BLOCK in stub_loader.c + STATUS_BYTES_LENGTH = 2 # same as ESP8266, different to ESP32 ROM + IS_STUB = True + + def __init__(self, rom_loader): + self.secure_download_mode = rom_loader.secure_download_mode + self._port = rom_loader._port + self._trace_enabled = rom_loader._trace_enabled + self.cache = rom_loader.cache + self.flush_input() # resets _slip_reader + -# TODO: [ESP32C5] ESPTOOL-825, IDF-8631 support stub flasher +ESP32C5ROM.STUB_CLASS = ESP32C5StubLoader diff --git a/esptool/targets/stub_flasher/stub_flasher_32c5.json b/esptool/targets/stub_flasher/stub_flasher_32c5.json new file mode 100644 index 000000000..ceda12bdd --- /dev/null +++ b/esptool/targets/stub_flasher/stub_flasher_32c5.json @@ -0,0 +1,8 @@ +{ + "entry": 1082131910, + "text": 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"ARG3BwBgTsaDqYcASsg3CYRAJspSxAbOIsy3BABgfVoTCQkAwEwTdPQ/DeDyQGJEI6g0AUJJ0kSySSJKBWGCgIhAgycJABN19Q+Cl30U4xlE/8m/EwcADJRBqodjGOUAhUeFxiOgBQB5VYKABUdjh+YACUZjjcYAfVWCgEIFEwewDUGFY5XnAolHnMH1t5MGwA1jFtUAmMETBQAMgoCTBtANfVVjldcAmMETBbANgoC3NYVAQRGThQW6BsZhP2NFBQa3N4VAk4eHsQOnBwgD1kcIE3X1D5MGFgDCBsGCI5LXCDKXIwCnAAPXRwiRZ5OHBwRjHvcCN7eEQBMHh7GhZ7qXA6YHCLf2hEC3N4VAk4eHsZOGhrVjH+YAI6bHCCOg1wgjkgcIIaD5V+MG9fyyQEEBgoAjptcII6DnCN23NzcAYHxLnYv1/zcnAGB8S52L9f+CgEERBsbdN7c3AGAjpgcCNwcACJjDmEN9/8hXskATRfX/BYlBAYKAQREGxtk/fd03BwBAtzcAYJjDNzcAYBxD/f+yQEEBgoBBESLEN4SEQJMHxABKwAOpBwEGxibCYwoJBEU3OcW9RxMExACBRGPWJwEERL2Ik7QUAH03hT8cRDcGgAATl8cAmeA3BgABt/b/AHWPtzYAYNjCkMKYQn3/QUeR4AVHMwnpQLqXIygkARzEskAiRJJEAklBAYKAQREGxhMHAAxjEOUCEwWwDZcAgP/ngIDjEwXADbJAQQEXA4D/ZwCD4hMHsA3jGOX+lwCA/+eAgOETBdANxbdBESLEJsIGxiqEswS1AGMXlACyQCJEkkRBAYKAA0UEAAUERTfttxMFAAwXA4D/ZwAD3jVxJstOx/1yhWn9dCLNSslSxVbDBs+ThIT6FpGThwkHppcYCLOE5wAqiSaFLoSXAID/54DgSJOHCQcYCAVqupezikdBMeQFZ311kwWF+pMHBwcTBYX5FAiqlzOF1wCTBwcHrpezhdcAKsaXAID/54CgRTJFwUWhPwFFhWIWkfpAakTaREpJukkqSppKDWGCgKKJY3OKAIVpTobWhUqFlwCA/+eA4OITdfUPAe1OhtaFJoWXAID/54DgQE6ZMwQ0QVG3EwUwBlW/MXH9ck7XUtVW017PBt8i3SbbStla0WLNZstqyW7HqokWkRMFAAIuirKKtosCypcAgP/ngKA7hWdj4FcThWR9dBMEhPqThwQHopcYCDOE5wAihZcAgP/ngCA6fXsTDDv5kwyL+ROHBAeThwQHFAhil+aXAUkzDNcAs4zXAFJNY3xNCWNxqQNBqFU1poUIAaU9cT0mhgwBIoWXAID/54AANqaZJpljdUkDswepQWPxdwOzBCpBY/OaANaEJoYMAU6FlwCA/+eAQNQTdfUPVd0CzIFEeV2NTaMJAQBihZcAgP/ngMDDffkDRTEB5oUFMWNPBQDj4p3+hWeThwcHppcYCLqX2pcjiqf4hQTxt+MVpf2RR+OF9PYFZ311kwcHB5MFhfoTBYX5FAiqlzOF1wCTBwcHrpezhdcAKsaXAID/54AgLO0zMkXBRX07zTMTBQAClwCA/+eAwCmFYhaR+lBqVNpUSlm6WSpamloKW/pLakzaTEpNuk0pYYKAAREGziLMnTk3BM4/bAATBUT/lwCA/+eAwMqqhwVFleeyR5P3ByA+xkE5NzcAYBxHtwZAABMFRP/VjxzHskWXAID/54BAyDM1oADyQGJEBWGCgEERt4eEQAbGk4fHAAVHI4DnABPXxQCYxwVnfRfMw8jH+Y06laqVsYGMyyOqBwBBNxnBEwVQDLJAQQGCgAERIsw3hIRAkwfEACbKxEdOxgbOSsiqiRMExABj85UAroSpwAMpRAAmmRNZyQAcSGNV8AAcRGNe+QLpNn3dSEAmhs6FlwCA/+eAQLsTdfUPAcWTB0AMXMhcQKaXXMBcRIWPXMTyQGJE0kRCSbJJBWGCgOE+bb+3V0FJGXGTh/eEAUU+zobeotym2srYztbS1NbS2tDezuLM5srqyO7GlwCA/+eAoK23B4RANzeFQJOHBwATB4e6Y+DnFK0xkUVoCD05jTG3t4RAk4eHsSFnPpcjIPcItwWAQLcHgEABRpOHBwuThQUANwmEQBVFIyD5AJcAgP/ngMAONwcAYFxHEwUAAreEhECT5xcQXMeXAID/54CADbcXCWCIX4FFtzmFQHGJYRUTNRUAlwCA/+eAQLbBZ/0XEwcAEIVmQWa3BQABAUWThMQAtwqEQA1qlwCA/+eAAKyTiYmxEwkJABOLygAmmoOnyQj134OryQiFRyOmCQgjAvECg8cbAAlHIxPhAqMC8QIC1E1HY4vnBlFHY4nnBilHY5/nAIPHOwADxysAogfZjxFHY5bnAIOniwCcQz7UjT6hRUgQmTaDxzsAA8crAKIH2Y8RZ0EHY373AhMFsA2XAID/54BgkxMFwA2XAID/54CgkhMF4A6XAID/54DgkQ0+vbcjoAcAkQdtvclHIxPxAn23A8cbANFGY+fmAoVGY+bmAAFMEwTwD52oeRcTd/cPyUbj6Ob+tzaFQAoHk4bGujaXGEMCh5MGBwOT9vYPEUbjadb8Ewf3AhN39w+NRmPu5gi3NoVACgeThoa/NpcYQwKHEwdAAmOa5xAC1B1EAUWXAID/54BAiQFFiTRVNE00oUVIEH0UlTx98AFMAUQTdfQPLTQTdfwPFTRZNOMRBOyDxxsASUdjZfcwCUfjeffq9ReT9/cPPUfjY/fqNzeFQIoHEweHwLqXnEOChwVEnetwEIFFAUWXAID/54BgiR3h0UVoEBk8AUQxqAVEge+XAID/54DgjTM0oAApoCFHY4XnAAVEAUxhtwOsiwADpMsAs2eMANIH9feZOWX1wWwinP0cfX0zBYxAXdyzd5UBlePBbDMFjEBj5owC/XwzBYxAXdAxgZcAgP/ngICKXflmlPW3MYGXAID/54CAiV3xapTRt0GBlwCA/+eAwIhZ+TMElEHBtyFH44rn8AFMEwQADDm3QUfNv0FHBUTjnef2g6XLAAOliwBZOrm/QUcFROOT5/YDpwsBkWdj6Oceg6VLAQOliwAxMYG3QUcFROOU5/SDpwsBEWdjafccA6fLAIOlSwEDpYsAM4TnAt02I6wEACMkirAJvwPHBABjAwcUA6eLAMEXEwQADGMT9wDASAFHkwbwDmNG9wKDx1sAA8dLAAFMogfZjwPHawBCB12Pg8d7AOIH2Y/jhPbmEwQQDIW1M4brAANGhgEFB7GO4beDxwQA/cfcRGOdBxTASCOABABVvWFHY5bnAoOnywEDp4sBg6ZLAQOmCwGDpcsAA6WLAJfwf//ngIB5KowzNKAAAb0BTAVEKbURRwVE453n5reXAGC0X2V3fRcFZvmO0Y4DpYsAtN+0V4FF+Y7RjrTX9F/5jtGO9N/0U3WPUY/405fwf//ngKB8BbUT9/cA4xcH6pPcRwAThIsAAUx9XeN3nNtIRJfwf//ngGBgGERUQBBA+Y5jB6cBHEITR/f/fY/ZjhTCBQxBBNm/EUe1tUFHBUTjmufeg6eLAAOnSwEjJPkAIyLpAMmzgyVJAMEXkeWJzwFMEwRgDKG7AyeJAGNm9wYT9zcA4xsH4gMoiQABRgFHMwXoQLOG5QBjafcA4wcG0iMkqQAjItkADbMzhusAEE4RB5DCBUbpvyFHBUTjlOfYAySJABnAEwSADCMkCQAjIgkAMzSAAL2zAUwTBCAMxbkBTBMEgAzlsQFMEwSQDMWxEwcgDWOD5wwTB0AN45HnugPEOwCDxysAIgRdjJfwf//ngIBfA6zEAEEUY3OEASKM4w8MtsBAYpQxgJxIY1XwAJxEY1r0Cu/wr+B13chAYoaThYsBl/B//+eAgFsBxZMHQAzcyNxA4pfcwNxEs4eHQdzEl/B//+eAYFoVvgllEwUFcQOsywADpIsAl/B//+eA4Eq3BwBg2Eu3BgABwRaTV0cBEgd1j72L2Y+zh4cDAUWz1YcCl/B//+eAQEwTBYA+l/B//+eAgEfdtIOmSwEDpgsBg6XLAAOliwDv8K/2wbyDxTsAg8crABOFiwGiBd2NwRWpOm287/AP2oG3A8Q7AIPHKwATjIsBIgRdjNxEQRTF45FHhUtj/ocIkweQDNzIebQDpw0AItAFSLOH7EA+1oMnirBjc/QADUhCxjrE7/CP1SJHMkg3hYRA4oV8EJOGygAQEBMFRQKX8H//54AASje3hECTCMcAglcDp4iwg6UNAB2MHY8+nLJXI6TosKqLvpUjoL0Ak4fKAJ2NAcWhZ2OW9QBahV04I6BtAQnE3ESZw+NAcPlj3wsAkwdwDIW/hUu3PYVAt4yEQJONjbqTjMwA6b/jlQue3ETjggeekweADLG3g6eLAOObB5wBRZfwf//ngCA5CWUTBQVxl/B//+eAwDSX8H//54DAOU26A6TLAOMGBJoBRZfwf//ngIA2EwWAPpfwf//ngEAyApRBuvZQZlTWVEZZtlkmWpZaBlv2S2ZM1kxGTbZNCWGCgAAA", "text_start": 1082130432, - "data": "FACEQGwKgEC8CoBAFAuAQOILgEBODIBA/AuAQDgJgECeC4BA3guAQCgLgEDoCIBAXAuAQOgIgEBGCoBAjAqAQLwKgEAUC4BAWAqAQJwJgEDMCYBAVAqAQKYOgEC8CoBAZg2AQF4OgEAoCIBAhg6AQCgIgEAoCIBAKAiAQCgIgEAoCIBAKAiAQCgIgEAoCIBAAg2AQCgIgECEDYBAXg6AQA==", - "data_start": 1082469296, + "data": "DACEQO4IgEA6CYBAkgmAQGAKgEDMCoBAegqAQLYHgEAcCoBAXAqAQKYJgEBmB4BA2gmAQGYHgEDICIBADAmAQDoJgECSCYBA2giAQCAIgEBQCIBA1giAQCQNgEA6CYBA5AuAQNgMgECyBoBAAg2AQLIGgECyBoBAsgaAQLIGgECyBoBAsgaAQLIGgECyBoBAgAuAQLIGgEAADIBA2AyAQA==", + "data_start": 1082469288, "bss_start": 1082392576 } \ No newline at end of file diff --git a/flasher_stub/Makefile b/flasher_stub/Makefile index 1d78f4d0c..b1ca91207 100644 --- a/flasher_stub/Makefile +++ b/flasher_stub/Makefile @@ -68,6 +68,7 @@ STUB_ELF_32H2_BETA_1 = $(BUILD_DIR)/$(STUB)_32h2beta1.elf STUB_ELF_32H2_BETA_2 = $(BUILD_DIR)/$(STUB)_32h2beta2.elf STUB_ELF_32C2 = $(BUILD_DIR)/$(STUB)_32c2.elf STUB_ELF_32C6 = $(BUILD_DIR)/$(STUB)_32c6.elf +STUB_ELF_32C5 = $(BUILD_DIR)/$(STUB)_32c5.elf STUB_ELF_32C5_BETA_3 = $(BUILD_DIR)/$(STUB)_32c5beta3.elf STUB_ELF_32H2 = $(BUILD_DIR)/$(STUB)_32h2.elf STUB_ELF_32P4 = $(BUILD_DIR)/$(STUB)_32p4.elf @@ -94,6 +95,7 @@ STUBS_ELF += \ $(STUB_ELF_32H2_BETA_2) \ $(STUB_ELF_32C2) \ $(STUB_ELF_32C6) \ + $(STUB_ELF_32C5) \ $(STUB_ELF_32C5_BETA_3) \ $(STUB_ELF_32H2) \ $(STUB_ELF_32P4) @@ -171,6 +173,10 @@ $(STUB_ELF_32C6): $(SRCS) $(BUILD_DIR) ld/stub_32c6.ld @echo " CC(32C6) $^ -> $@" $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C6=1 -Tstub_32c6.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) +$(STUB_ELF_32C5): $(SRCS) $(BUILD_DIR) ld/stub_32c5.ld + @echo " CC(32C5) $^ -> $@" + $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C5=1 -Tstub_32c5.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + $(STUB_ELF_32C5_BETA_3): $(SRCS) $(BUILD_DIR) ld/stub_32c5_beta_3.ld @echo " CC(32C5BETA3) $^ -> $@" $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C5BETA3=1 -Tstub_32c5_beta_3.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) diff --git a/flasher_stub/compare_stubs.py b/flasher_stub/compare_stubs.py index 74843f0fb..1d6c28964 100755 --- a/flasher_stub/compare_stubs.py +++ b/flasher_stub/compare_stubs.py @@ -68,9 +68,8 @@ def diff(path_to_new, path_to_old): same = True for chip in esptool.CHIP_LIST: print("Comparing {} stub: ".format(chip), end="") - # TODO: [ESP32C5] ESPTOOL-825 remove when supported stub flasher # TODO: [ESP32C61] IDF-9241 remove when supported stub flasher - if chip in ["esp32c5", "esp32c61"]: + if chip in ["esp32c61"]: print(f"{chip} has not supported stub yet, skipping...") continue diff --git a/flasher_stub/include/rom_functions.h b/flasher_stub/include/rom_functions.h index 5c7d5a8d8..a66a9b62c 100644 --- a/flasher_stub/include/rom_functions.h +++ b/flasher_stub/include/rom_functions.h @@ -18,11 +18,11 @@ int uart_rx_one_char(uint8_t *ch); uint8_t uart_rx_one_char_block(); int uart_tx_one_char(char ch); -#if ESP32C6 || ESP32H2 || ESP32C5BETA3 || ESP32P4 +#if ESP32C6 || ESP32H2 || ESP32C5 || ESP32C5BETA3 || ESP32P4 /* uart_tx_one_char doesn't send data to USB device serial, needs to be replaced */ int uart_tx_one_char2(char ch); #define uart_tx_one_char(ch) uart_tx_one_char2(ch) -#endif // ESP32C6 || ESP32H2 || ESP32C5BETA3 || ESP32P4 +#endif // ESP32C6 || ESP32H2 || ESP32C5 || ESP32C5BETA3 || ESP32P4 void uart_div_modify(uint32_t uart_no, uint32_t baud_div); diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index eed774bdc..0f2e390f8 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -46,8 +46,13 @@ #define WITH_USB_OTG 1 #endif // ESP32S3 +#ifdef ESP32C5 +#define WITH_USB_JTAG_SERIAL 0 // not implemented yet +#define IS_RISCV 1 +#endif // ESP32C5 + #ifdef ESP32C5BETA3 -#define WITH_USB_JTAG_SERIAL 1 +#define WITH_USB_JTAG_SERIAL 0 #define IS_RISCV 1 #endif // ESP32C5BETA3 @@ -173,7 +178,7 @@ #define DR_REG_IO_MUX_BASE 0x60009000 #endif -#if ESP32C6 || ESP32C5BETA3 +#if ESP32C6 || ESP32C5 || ESP32C5BETA3 #define UART_BASE_REG 0x60000000 /* UART0 */ #define SPI_BASE_REG 0x60003000 /* SPI peripheral 1, used for SPI flash */ #define SPI0_BASE_REG 0x60002000 /* SPI peripheral 0, inner state machine */ @@ -333,14 +338,14 @@ #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ #endif // ESP32S3 -#if ESP32C6 || ESP32C5BETA3 +#if ESP32C6 #define UART_USB_JTAG_SERIAL 3 #define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xC0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */ #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ -#endif // ESP32C6 || ESP32C5BETA3 +#endif // ESP32C6 #ifdef ESP32H2 #define UART_USB_JTAG_SERIAL 3 @@ -403,7 +408,7 @@ #define RTC_CNTL_SWD_AUTO_FEED_EN (1 << 31) #endif -#if ESP32C6 || ESP32C5BETA3 || ESP32P4 +#if ESP32C6 || ESP32C5 || ESP32C5BETA3 || ESP32P4 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG #define RTC_CNTL_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x001C) // LP_WDT_SWD_CONFIG_REG @@ -456,6 +461,14 @@ #define SYSTEM_SOC_CLK_MAX 1 #endif // ESP32S2 +#ifdef ESP32C5 +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) +#define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) +#define PCR_SOC_CLK_SEL_V 0x3 +#define PCR_SOC_CLK_SEL_S 16 +#define PCR_SOC_CLK_MAX 3 // CPU_CLK frequency is 240 MHz (source is PLL_F240_CLK) +#endif // ESP32C5 + #ifdef ESP32C5BETA3 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) #define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) @@ -501,9 +514,9 @@ #define ROM_SPIFLASH_LEGACY 0x3ffae270 #endif // ESP32 || ESP32S2 || ESP32S3 || ESP32S3BETA2 -#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5BETA3 +#if ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5 || ESP32C5BETA3 #define ROM_SPIFLASH_LEGACY 0x3fcdfff4 -#endif // ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 +#endif // ESP32C3 || ESP32C6BETA || ESP32C2 || ESP32C6 || ESP32C5 || ESP32C5BETA3 #if ESP32H2BETA1 || ESP32H2BETA2 #define ROM_SPIFLASH_LEGACY 0x3fcdfff0 @@ -567,13 +580,13 @@ #define FUNC_GPIO 1 #endif // ESP32C2 -#if ESP32C6 || ESP32C6BETA || ESP32C5BETA3 +#if ESP32C6 || ESP32C6BETA || ESP32C5 || ESP32C5BETA3 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x78) #define PERIPHS_IO_MUX_SPIQ_U (DR_REG_IO_MUX_BASE + 0x68) #define PERIPHS_IO_MUX_SPID_U (DR_REG_IO_MUX_BASE + 0x7c) #define PERIPHS_IO_MUX_SPICS0_U (DR_REG_IO_MUX_BASE + 0x64) #define FUNC_GPIO 1 -#endif // ESP32C6 || ESP32C6BETA +#endif // ESP32C6 || ESP32C6BETA || ESP32C5 || ESP32C5BETA3 #if ESP32H2 || ESP32H2BETA1 || ESP32H2BETA2 #define PERIPHS_IO_MUX_SPICLK_U (DR_REG_IO_MUX_BASE + 0x50) diff --git a/flasher_stub/ld/rom_32c5.ld b/flasher_stub/ld/rom_32c5.ld new file mode 100755 index 000000000..3ef16e1fe --- /dev/null +++ b/flasher_stub/ld/rom_32c5.ld @@ -0,0 +1,483 @@ +/* ROM function interface esp32c5.rom.ld for esp32c5 + * + * + * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum f5c146321f24f88ad1f27234da5aed11 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +PROVIDE ( SPIWrite = esp_rom_spiflash_write); +PROVIDE ( SPI_read_status_high = esp_rom_spiflash_read_statushigh); +PROVIDE ( SPI_write_status = esp_rom_spiflash_write_status); +PROVIDE ( SPIRead = esp_rom_spiflash_read); +PROVIDE ( SPIParamCfg = esp_rom_spiflash_config_param); +PROVIDE ( SPIEraseChip = esp_rom_spiflash_erase_chip); +PROVIDE ( SPIEraseSector = esp_rom_spiflash_erase_sector); +PROVIDE ( SPIEraseBlock = esp_rom_spiflash_erase_block); +PROVIDE ( SPI_Write_Encrypt_Enable = esp_rom_spiflash_write_encrypted_enable); +PROVIDE ( SPI_Write_Encrypt_Disable = esp_rom_spiflash_write_encrypted_disable); +PROVIDE ( SPI_Encrypt_Write = esp_rom_spiflash_write_encrypted); + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +rtc_get_wakeup_cause = 0x4000001c; +pmu_enable_unhold_pads = 0x40000020; +ets_printf = 0x40000024; +ets_install_putc1 = 0x40000028; +ets_install_putc2 = 0x4000002c; +ets_install_uart_printf = 0x40000030; +ets_install_usb_printf = 0x40000034; +ets_get_printf_channel = 0x40000038; +ets_delay_us = 0x4000003c; +ets_get_cpu_frequency = 0x40000040; +ets_update_cpu_frequency = 0x40000044; +ets_install_lock = 0x40000048; +UartRxString = 0x4000004c; +UartGetCmdLn = 0x40000050; +uart_tx_one_char = 0x40000054; +uart_tx_one_char2 = 0x40000058; +uart_tx_one_char3 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +uart_buff_switch = 0x40000088; +roundup2 = 0x4000008c; +multofup = 0x40000090; +software_reset = 0x40000094; +software_reset_cpu = 0x40000098; +ets_clk_assist_debug_clock_enable = 0x4000009c; +clear_super_wdt_reset_flag = 0x400000a0; +disable_default_watchdog = 0x400000a4; +esp_rom_set_rtc_wake_addr = 0x400000a8; +esp_rom_get_rtc_wake_addr = 0x400000ac; +send_packet = 0x400000b0; +recv_packet = 0x400000b4; +GetUartDevice = 0x400000b8; +UartDwnLdProc = 0x400000bc; +GetSecurityInfoProc = 0x400000c0; +Uart_Init = 0x400000c4; +ets_set_user_start = 0x400000c8; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4004fffc; +ets_ops_table_ptr = 0x4085fff8; +g_saved_pc = 0x4085fffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000cc; +mz_free = 0x400000d0; +tdefl_compress = 0x400000d4; +tdefl_compress_buffer = 0x400000d8; +tdefl_compress_mem_to_heap = 0x400000dc; +tdefl_compress_mem_to_mem = 0x400000e0; +tdefl_compress_mem_to_output = 0x400000e4; +tdefl_get_adler32 = 0x400000e8; +tdefl_get_prev_return_status = 0x400000ec; +tdefl_init = 0x400000f0; +tdefl_write_image_to_png_file_in_memory = 0x400000f4; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f8; +tinfl_decompress = 0x400000fc; +tinfl_decompress_mem_to_callback = 0x40000100; +tinfl_decompress_mem_to_heap = 0x40000104; +tinfl_decompress_mem_to_mem = 0x40000108; + + +/*************************************** + Group tjpgd + ***************************************/ + +/* Functions */ +jd_prepare = 0x4000010c; +jd_decomp = 0x40000110; + + +/*************************************** + Group spi_extmem_common + ***************************************/ + +/* Functions */ +esp_rom_spi_cmd_config = 0x40000114; +esp_rom_spi_cmd_start = 0x40000118; +esp_rom_spi_set_op_mode = 0x4000011c; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x40000120; +esp_rom_spiflash_write_encrypted = 0x40000124; +esp_rom_spiflash_write_encrypted_dest = 0x40000128; +esp_rom_spiflash_write_encrypted_enable = 0x4000012c; +esp_rom_spiflash_write_encrypted_disable = 0x40000130; +esp_rom_spiflash_erase_chip = 0x40000134; +_esp_rom_spiflash_erase_sector = 0x40000138; +_esp_rom_spiflash_erase_block = 0x4000013c; +_esp_rom_spiflash_write = 0x40000140; +_esp_rom_spiflash_read = 0x40000144; +_esp_rom_spiflash_unlock = 0x40000148; +_SPIEraseArea = 0x4000014c; +_SPI_write_enable = 0x40000150; +esp_rom_spiflash_erase_sector = 0x40000154; +esp_rom_spiflash_erase_block = 0x40000158; +esp_rom_spiflash_write = 0x4000015c; +esp_rom_spiflash_read = 0x40000160; +esp_rom_spiflash_unlock = 0x40000164; +SPIEraseArea = 0x40000168; +SPI_write_enable = 0x4000016c; +esp_rom_spiflash_config_param = 0x40000170; +esp_rom_spiflash_read_user_cmd = 0x40000174; +esp_rom_spiflash_select_qio_pins = 0x40000178; +esp_rom_spi_flash_auto_sus_res = 0x4000017c; +esp_rom_spi_flash_send_resume = 0x40000180; +esp_rom_spi_flash_update_id = 0x40000184; +esp_rom_spiflash_config_clk = 0x40000188; +esp_rom_spiflash_config_readmode = 0x4000018c; +esp_rom_spiflash_read_status = 0x40000190; +esp_rom_spiflash_read_statushigh = 0x40000194; +esp_rom_spiflash_write_status = 0x40000198; +esp_rom_spiflash_write_disable = 0x4000019c; +spi_cache_mode_switch = 0x400001a0; +spi_common_set_dummy_output = 0x400001a4; +spi_common_set_flash_cs_timing = 0x400001a8; +esp_rom_spi_set_address_bit_len = 0x400001ac; +SPILock = 0x400001b0; +SPIMasterReadModeCnfig = 0x400001b4; +SPI_Common_Command = 0x400001b8; +SPI_WakeUp = 0x400001bc; +SPI_block_erase = 0x400001c0; +SPI_chip_erase = 0x400001c4; +SPI_init = 0x400001c8; +SPI_page_program = 0x400001cc; +SPI_read_data = 0x400001d0; +SPI_sector_erase = 0x400001d4; +SelectSpiFunction = 0x400001d8; +SetSpiDrvs = 0x400001dc; +Wait_SPI_Idle = 0x400001e0; +spi_dummy_len_fix = 0x400001e4; +Disable_QMode = 0x400001e8; +Enable_QMode = 0x400001ec; +spi_flash_attach = 0x400001f0; +spi_flash_get_chip_size = 0x400001f4; +spi_flash_guard_set = 0x400001f8; +spi_flash_guard_get = 0x400001fc; +spi_flash_read_encrypted = 0x40000200; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4085fff0; +rom_spiflash_legacy_data = 0x4085ffec; +g_flash_guard_ops = 0x4085fff4; + + +/*************************************** + Group hal_wdt + ***************************************/ + +/* Functions */ +wdt_hal_init = 0x400003a4; +wdt_hal_deinit = 0x400003a8; +wdt_hal_config_stage = 0x400003ac; +wdt_hal_write_protect_disable = 0x400003b0; +wdt_hal_write_protect_enable = 0x400003b4; +wdt_hal_enable = 0x400003b8; +wdt_hal_disable = 0x400003bc; +wdt_hal_handle_intr = 0x400003c0; +wdt_hal_feed = 0x400003c4; +wdt_hal_set_flashboot_en = 0x400003c8; +wdt_hal_is_enabled = 0x400003cc; + + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +systimer_hal_init = 0x400003d0; +systimer_hal_deinit = 0x400003d4; +systimer_hal_set_tick_rate_ops = 0x400003d8; +systimer_hal_get_counter_value = 0x400003dc; +systimer_hal_get_time = 0x400003e0; +systimer_hal_set_alarm_target = 0x400003e4; +systimer_hal_set_alarm_period = 0x400003e8; +systimer_hal_get_alarm_value = 0x400003ec; +systimer_hal_enable_alarm_int = 0x400003f0; +systimer_hal_on_apb_freq_update = 0x400003f4; +systimer_hal_counter_value_advance = 0x400003f8; +systimer_hal_enable_counter = 0x400003fc; +systimer_hal_select_alarm_mode = 0x40000400; +systimer_hal_connect_alarm_counter = 0x40000404; +systimer_hal_counter_can_stall_by_cpu = 0x40000408; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_Line_Size = 0x40000638; +Cache_Get_Mode = 0x4000063c; +Cache_Address_Through_Cache = 0x40000640; +ROM_Boot_Cache_Init = 0x40000644; +Cache_Sync_Items = 0x40000648; +Cache_Op_Addr = 0x4000064c; +Cache_Invalidate_Addr = 0x40000650; +Cache_Clean_Addr = 0x40000654; +Cache_WriteBack_Addr = 0x40000658; +Cache_WriteBack_Invalidate_Addr = 0x4000065c; +Cache_Invalidate_All = 0x40000660; +Cache_Clean_All = 0x40000664; +Cache_WriteBack_All = 0x40000668; +Cache_WriteBack_Invalidate_All = 0x4000066c; +Cache_Mask_All = 0x40000670; +Cache_UnMask_Dram0 = 0x40000674; +Cache_Suspend_Autoload = 0x40000678; +Cache_Resume_Autoload = 0x4000067c; +Cache_Start_Preload = 0x40000680; +Cache_Preload_Done = 0x40000684; +Cache_End_Preload = 0x40000688; +Cache_Config_Autoload = 0x4000068c; +Cache_Enable_Autoload = 0x40000690; +Cache_Disable_Autoload = 0x40000694; +Cache_Enable_PreLock = 0x40000698; +Cache_Disable_PreLock = 0x4000069c; +Cache_Lock_Items = 0x400006a0; +Cache_Lock_Addr = 0x400006a4; +Cache_Unlock_Addr = 0x400006a8; +Cache_Disable_Cache = 0x400006ac; +Cache_Enable_Cache = 0x400006b0; +Cache_Suspend_Cache = 0x400006b4; +Cache_Resume_Cache = 0x400006b8; +Cache_Freeze_Enable = 0x400006bc; +Cache_Freeze_Disable = 0x400006c0; +Cache_Set_IDROM_MMU_Size = 0x400006c4; +Cache_Get_IROM_MMU_End = 0x400006c8; +Cache_Get_DROM_MMU_End = 0x400006cc; +Cache_MMU_Init = 0x400006d0; +Cache_MSPI_MMU_Set = 0x400006d4; +Cache_MSPI_MMU_Set_Secure = 0x400006d8; +Cache_Count_Flash_Pages = 0x400006dc; +Cache_Travel_Tag_Memory = 0x400006e0; +Cache_Get_Virtual_Addr = 0x400006e4; +flash2spiram_instruction_offset = 0x400006e8; +flash2spiram_rodata_offset = 0x400006ec; +flash_instr_rodata_start_page = 0x400006f0; +flash_instr_rodata_end_page = 0x400006f4; +Cache_Set_IDROM_MMU_Info = 0x400006f8; +Cache_Flash_To_SPIRAM_Copy = 0x400006fc; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4085ffcc; +rom_cache_internal_table_ptr = 0x4085ffc8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x40000700; +ets_clk_get_cpu_freq = 0x40000704; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_set_output_level = 0x40000708; +gpio_get_input_level = 0x4000070c; +gpio_matrix_in = 0x40000710; +gpio_matrix_out = 0x40000714; +gpio_bypass_matrix_in = 0x40000718; +gpio_output_disable = 0x4000071c; +gpio_output_enable = 0x40000720; +gpio_pad_input_disable = 0x40000724; +gpio_pad_input_enable = 0x40000728; +gpio_pad_pulldown = 0x4000072c; +gpio_pad_pullup = 0x40000730; +gpio_pad_select_gpio = 0x40000734; +gpio_pad_set_drv = 0x40000738; +gpio_pad_unhold = 0x4000073c; +gpio_pad_hold = 0x40000740; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x40000744; +esprv_intc_int_set_threshold = 0x40000748; +esprv_intc_int_enable = 0x4000074c; +esprv_intc_int_disable = 0x40000750; +esprv_intc_int_set_type = 0x40000754; +PROVIDE( intr_handler_set = 0x40000758 ); +intr_matrix_set = 0x4000075c; +ets_intr_register_ctx = 0x40000760; +ets_intr_lock = 0x40000764; +ets_intr_unlock = 0x40000768; +ets_isr_attach = 0x4000076c; +ets_isr_mask = 0x40000770; +ets_isr_unmask = 0x40000774; + + +/*************************************** + Group crc + ***************************************/ + +/* Functions */ +crc32_le = 0x40000778; +crc16_le = 0x4000077c; +crc8_le = 0x40000780; +crc32_be = 0x40000784; +crc16_be = 0x40000788; +crc8_be = 0x4000078c; +esp_crc8 = 0x40000790; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4004fff8; +crc16_le_table_ptr = 0x4004fff4; +crc8_le_table_ptr = 0x4004fff0; +crc32_be_table_ptr = 0x4004ffec; +crc16_be_table_ptr = 0x4004ffe8; +crc8_be_table_ptr = 0x4004ffe4; + + +/*************************************** + Group md5 + ***************************************/ + +/* Functions */ +md5_vector = 0x40000794; +MD5Init = 0x40000798; +MD5Update = 0x4000079c; +MD5Final = 0x400007a0; + + +/*************************************** + Group hwcrypto + ***************************************/ + +/* Functions */ +ets_sha_enable = 0x400007a4; +ets_sha_disable = 0x400007a8; +ets_sha_get_state = 0x400007ac; +ets_sha_init = 0x400007b0; +ets_sha_process = 0x400007b4; +ets_sha_starts = 0x400007b8; +ets_sha_update = 0x400007bc; +ets_sha_finish = 0x400007c0; +ets_sha_clone = 0x400007c4; +ets_hmac_enable = 0x400007c8; +ets_hmac_disable = 0x400007cc; +ets_hmac_calculate_message = 0x400007d0; +ets_hmac_calculate_downstream = 0x400007d4; +ets_hmac_invalidate_downstream = 0x400007d8; +ets_aes_enable = 0x400007dc; +ets_aes_disable = 0x400007e0; +ets_aes_setkey = 0x400007e4; +ets_aes_block = 0x400007e8; +ets_aes_setkey_dec = 0x400007ec; +ets_aes_setkey_enc = 0x400007f0; +ets_bigint_enable = 0x400007f4; +ets_bigint_disable = 0x400007f8; +ets_bigint_multiply = 0x400007fc; +ets_bigint_modmult = 0x40000800; +ets_bigint_modexp = 0x40000804; +ets_bigint_wait_finish = 0x40000808; +ets_bigint_getz = 0x4000080c; +ets_ds_enable = 0x40000810; +ets_ds_disable = 0x40000814; +ets_ds_start_sign = 0x40000818; +ets_ds_is_busy = 0x4000081c; +ets_ds_finish_sign = 0x40000820; +ets_ds_encrypt_params = 0x40000824; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x40000828; +ets_efuse_program = 0x4000082c; +ets_efuse_clear_program_registers = 0x40000830; +ets_efuse_write_key = 0x40000834; +ets_efuse_get_read_register_address = 0x40000838; +ets_efuse_get_key_purpose = 0x4000083c; +ets_efuse_key_block_unused = 0x40000840; +ets_efuse_find_unused_key_block = 0x40000844; +ets_efuse_rs_calculate = 0x40000848; +ets_efuse_count_unused_key_blocks = 0x4000084c; +ets_efuse_secure_boot_enabled = 0x40000850; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000854; +ets_efuse_cache_encryption_enabled = 0x40000858; +ets_efuse_download_modes_disabled = 0x4000085c; +ets_efuse_find_purpose = 0x40000860; +ets_efuse_force_send_resume = 0x40000864; +ets_efuse_get_flash_delay_us = 0x40000868; +ets_efuse_get_uart_print_control = 0x4000086c; +ets_efuse_direct_boot_mode_disabled = 0x40000870; +ets_efuse_security_download_modes_enabled = 0x40000874; +ets_efuse_jtag_disabled = 0x40000878; +ets_efuse_usb_print_is_disabled = 0x4000087c; +ets_efuse_usb_download_mode_disabled = 0x40000880; +ets_efuse_usb_device_disabled = 0x40000884; +ets_efuse_secure_boot_fast_wake_enabled = 0x40000888; +ets_jtag_enable_temporarily = 0x4000088c; + + +/*************************************** + Group key_mgr + ***************************************/ + +/* Functions */ +esp_rom_check_recover_key = 0x40000890; +esp_rom_km_huk_conf = 0x40000894; +esp_rom_km_huk_risk = 0x40000898; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x4000089c; +ets_rsa_pss_verify = 0x400008a0; +ets_ecdsa_verify = 0x400008a4; +ets_secure_boot_verify_bootloader_with_keys = 0x400008a8; +ets_secure_boot_verify_signature = 0x400008ac; +ets_secure_boot_read_key_digests = 0x400008b0; +ets_mgf1_sha256 = 0x400008b4; +ets_secure_boot_revoke_public_key_digest = 0x400008b8; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x40000ab8; +usb_serial_device_rx_one_char_block = 0x40000abc; +usb_serial_device_tx_flush = 0x40000ac0; +usb_serial_device_tx_one_char = 0x40000ac4; + diff --git a/flasher_stub/ld/rom_32c5_beta_3.ld b/flasher_stub/ld/rom_32c5_beta_3.ld index d9c3d3e5e..e009f2ac4 100755 --- a/flasher_stub/ld/rom_32c5_beta_3.ld +++ b/flasher_stub/ld/rom_32c5_beta_3.ld @@ -427,3 +427,168 @@ usb_serial_device_rx_one_char_block = 0x40000a70; usb_serial_device_tx_flush = 0x40000a74; usb_serial_device_tx_one_char = 0x40000a78; + +/*************************************** + Group usb_dwcotg_uart + ***************************************/ + +/* Functions */ +Uart_Init_USB = 0x40000a7c; +usb_serial_otg_rx_one_char = 0x40000a80; +usb_serial_otg_rx_one_char_block = 0x40000a84; +usb_serial_otg_tx_flush = 0x40000a88; +usb_serial_otg_tx_one_char = 0x40000a8c; +/* Data (.data, .bss, .rodata) */ +uart_acm_dev = 0x4087ffc4; + + +/*************************************** + Group usb_dwcotg_module + ***************************************/ + +/* Functions */ +cdc_acm_class_handle_req = 0x40000a90; +cdc_acm_init = 0x40000a94; +cdc_acm_fifo_fill = 0x40000a98; +cdc_acm_rx_fifo_cnt = 0x40000a9c; +cdc_acm_fifo_read = 0x40000aa0; +cdc_acm_irq_tx_enable = 0x40000aa4; +cdc_acm_irq_tx_disable = 0x40000aa8; +cdc_acm_irq_state_enable = 0x40000aac; +cdc_acm_irq_state_disable = 0x40000ab0; +cdc_acm_irq_tx_ready = 0x40000ab4; +cdc_acm_irq_rx_enable = 0x40000ab8; +cdc_acm_irq_rx_disable = 0x40000abc; +cdc_acm_irq_rx_ready = 0x40000ac0; +cdc_acm_irq_is_pending = 0x40000ac4; +cdc_acm_irq_callback_set = 0x40000ac8; +cdc_acm_line_ctrl_set = 0x40000acc; +cdc_acm_line_ctrl_get = 0x40000ad0; +cdc_acm_poll_out = 0x40000ad4; +chip_usb_dw_did_persist = 0x40000ad8; +chip_usb_dw_init = 0x40000adc; +chip_usb_detach = 0x40000ae0; +chip_usb_dw_prepare_persist = 0x40000ae4; +chip_usb_get_persist_flags = 0x40000ae8; +chip_usb_set_persist_flags = 0x40000aec; +cpio_start = 0x40000af0; +cpio_feed = 0x40000af4; +cpio_done = 0x40000af8; +cpio_destroy = 0x40000afc; +dfu_flash_init = 0x40000b00; +dfu_flash_erase = 0x40000b04; +dfu_flash_program = 0x40000b08; +dfu_flash_read = 0x40000b0c; +dfu_flash_attach = 0x40000b10; +dfu_cpio_callback = 0x40000b14; +dfu_updater_get_err = 0x40000b18; +dfu_updater_clear_err = 0x40000b1c; +dfu_updater_enable = 0x40000b20; +dfu_updater_begin = 0x40000b24; +dfu_updater_feed = 0x40000b28; +dfu_updater_end = 0x40000b2c; +dfu_updater_set_raw_addr = 0x40000b30; +dfu_updater_flash_read = 0x40000b34; +usb_dc_prepare_persist = 0x40000b38; +usb_dw_isr_handler = 0x40000b3c; +usb_dc_attach = 0x40000b40; +usb_dc_detach = 0x40000b44; +usb_dc_reset = 0x40000b48; +usb_dc_set_address = 0x40000b4c; +usb_dc_ep_check_cap = 0x40000b50; +usb_dc_ep_configure = 0x40000b54; +usb_dc_ep_set_stall = 0x40000b58; +usb_dc_ep_clear_stall = 0x40000b5c; +usb_dc_ep_halt = 0x40000b60; +usb_dc_ep_is_stalled = 0x40000b64; +usb_dc_ep_enable = 0x40000b68; +usb_dc_ep_disable = 0x40000b6c; +usb_dc_ep_flush = 0x40000b70; +usb_dc_ep_write_would_block = 0x40000b74; +usb_dc_ep_write = 0x40000b78; +usb_dc_ep_read_wait = 0x40000b7c; +usb_dc_ep_read_continue = 0x40000b80; +usb_dc_ep_read = 0x40000b84; +usb_dc_ep_set_callback = 0x40000b88; +usb_dc_set_status_callback = 0x40000b8c; +usb_dc_ep_mps = 0x40000b90; +usb_dc_check_poll_for_interrupts = 0x40000b94; +mac_addr_to_serial_str_desc = 0x40000b98; +usb_set_current_descriptor = 0x40000b9c; +usb_get_descriptor = 0x40000ba0; +usb_dev_resume = 0x40000ba4; +usb_dev_get_configuration = 0x40000ba8; +usb_set_config = 0x40000bac; +usb_deconfig = 0x40000bb0; +usb_enable = 0x40000bb4; +usb_disable = 0x40000bb8; +usb_write_would_block = 0x40000bbc; +usb_write = 0x40000bc0; +usb_read = 0x40000bc4; +usb_ep_set_stall = 0x40000bc8; +usb_ep_clear_stall = 0x40000bcc; +usb_ep_read_wait = 0x40000bd0; +usb_ep_read_continue = 0x40000bd4; +usb_transfer_ep_callback = 0x40000bd8; +usb_transfer = 0x40000bdc; +usb_cancel_transfer = 0x40000be0; +usb_transfer_sync = 0x40000be4; +usb_dfu_set_detach_cb = 0x40000be8; +dfu_class_handle_req = 0x40000bec; +dfu_status_cb = 0x40000bf0; +dfu_custom_handle_req = 0x40000bf4; +usb_dfu_init = 0x40000bf8; +usb_dfu_force_detach = 0x40000bfc; +usb_dev_deinit = 0x40000c00; +usb_dw_ctrl_deinit = 0x40000c04; +/* Data (.data, .bss, .rodata) */ +s_usb_osglue = 0x4087ffb8; + + +/*************************************** + Group lldesc + ***************************************/ + +/* Functions */ +lldesc_build_chain = 0x40000c08; + + +/*************************************** + Group sip + ***************************************/ + +/* Functions */ +sip_after_tx_complete = 0x40000c0c; +sip_alloc_to_host_evt = 0x40000c10; +sip_download_begin = 0x40000c14; +sip_get_ptr = 0x40000c18; +sip_get_state = 0x40000c1c; +sip_init_attach = 0x40000c20; +sip_install_rx_ctrl_cb = 0x40000c24; +sip_install_rx_data_cb = 0x40000c28; +sip_is_active = 0x40000c2c; +sip_post_init = 0x40000c30; +sip_reclaim_from_host_cmd = 0x40000c34; +sip_reclaim_tx_data_pkt = 0x40000c38; +sip_send = 0x40000c3c; +sip_to_host_chain_append = 0x40000c40; +sip_to_host_evt_send_done = 0x40000c44; + + +/*************************************** + Group slc + ***************************************/ + +/* Functions */ +slc_add_credits = 0x40000c48; +slc_enable = 0x40000c4c; +slc_from_host_chain_fetch = 0x40000c50; +slc_from_host_chain_recycle = 0x40000c54; +slc_has_pkt_to_host = 0x40000c58; +slc_init_attach = 0x40000c5c; +slc_init_credit = 0x40000c60; +slc_reattach = 0x40000c64; +slc_send_to_host_chain = 0x40000c68; +slc_set_host_io_max_window = 0x40000c6c; +slc_to_host_chain_recycle = 0x40000c70; + diff --git a/flasher_stub/ld/stub_32c5.ld b/flasher_stub/ld/stub_32c5.ld new file mode 100644 index 000000000..0ddc7cf96 --- /dev/null +++ b/flasher_stub/ld/stub_32c5.ld @@ -0,0 +1,26 @@ +MEMORY { + iram : org = 0x40800000, len = 0x4000 + dram : org = 0x40840000, len = 0x18000 +} + +ENTRY(stub_main) + +SECTIONS { + .text : ALIGN(4) { + *(.literal) + *(.text .text.*) + } > iram + + .bss : ALIGN(4) { + _bss_start = ABSOLUTE(.); + *(.bss) + _bss_end = ABSOLUTE(.); + } > dram + + .data : ALIGN(4) { + *(.data) + *(.rodata .rodata.*) + } > dram +} + +INCLUDE "rom_32c5.ld" diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c index 445e42567..19aa77f27 100644 --- a/flasher_stub/stub_flasher.c +++ b/flasher_stub/stub_flasher.c @@ -63,7 +63,7 @@ static bool can_use_max_cpu_freq() #endif } -#if ESP32C6 || ESP32H2 || ESP32C5BETA3 +#if ESP32C6 || ESP32H2 || ESP32C5 || ESP32C5BETA3 static uint32_t pcr_sysclk_conf_reg = 0; #else static uint32_t cpu_per_conf_reg = 0; @@ -75,7 +75,7 @@ static void set_max_cpu_freq() if (can_use_max_cpu_freq()) { /* Set CPU frequency to max. This also increases SPI speed. */ - #if ESP32C6 || ESP32H2 || ESP32C5BETA3 + #if ESP32C6 || ESP32H2 || ESP32C5 || ESP32C5BETA3 pcr_sysclk_conf_reg = READ_REG(PCR_SYSCLK_CONF_REG); WRITE_REG(PCR_SYSCLK_CONF_REG, (pcr_sysclk_conf_reg & ~PCR_SOC_CLK_SEL_M) | (PCR_SOC_CLK_MAX << PCR_SOC_CLK_SEL_S)); #else @@ -92,7 +92,7 @@ static void reset_cpu_freq() { /* Restore saved sysclk_conf and cpu_per_conf registers. Use only if set_max_cpu_freq() has been called. */ - #if ESP32C6 || ESP32H2 || ESP32C5BETA3 + #if ESP32C6 || ESP32H2 || ESP32C5 || ESP32C5BETA3 if (can_use_max_cpu_freq() && pcr_sysclk_conf_reg != 0) { WRITE_REG(PCR_SYSCLK_CONF_REG, (READ_REG(PCR_SYSCLK_CONF_REG) & ~PCR_SOC_CLK_SEL_M) | (pcr_sysclk_conf_reg & PCR_SOC_CLK_SEL_M)); diff --git a/test/images/ram_helloworld/helloworld-esp32c5.bin b/test/images/ram_helloworld/helloworld-esp32c5.bin new file mode 100644 index 0000000000000000000000000000000000000000..971ebec37f198dd23f7bd8b9162dbf03435884d4 GIT binary patch literal 128 zcmaFK#K7Rf+u-nyfq_9Bh#CI>2a${*F$o~UQBdg!+c9&I1_xnQmnYLd)c=3pprCto zzYAZ3g8)$8BQ+-{U!gp|C?`dc3#1bbT+{d}&HI;k8%y>jju{*0{wZhidZu6^ubO&% KlJ-2S(~ $@" $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32P4=1 -Tapp_32p4.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) +$(APP_ELF_32C5): $(SRCS) $(BUILD_DIR) ld/app_32c5.ld + @echo " CC(32C5) $^ -> $@" + $(Q) $(CROSS_ESPRISCV32)gcc $(CFLAGS_ESPRISCV32) -DESP32C5=1 -Tapp_32c5.ld -Wl,-Map=$(@:.elf=.map) -o $@ $(filter %.c, $^) $(LDLIBS) + clean: $(Q) rm -rf $(BUILD_DIR) diff --git a/test/images/ram_helloworld/source/ld/app_32c5.ld b/test/images/ram_helloworld/source/ld/app_32c5.ld new file mode 100644 index 000000000..ea84886c0 --- /dev/null +++ b/test/images/ram_helloworld/source/ld/app_32c5.ld @@ -0,0 +1,26 @@ +MEMORY { + iram : org = 0x40800d44, len = 0x100 + dram : org = 0x40800e44, len = 0x100 +} + +ENTRY(ram_main) + +SECTIONS { + .text : ALIGN(4) { + *(.literal) + *(.text .text.*) + } > iram + + .bss : ALIGN(4) { + _bss_start = ABSOLUTE(.); + *(.bss) + _bss_end = ABSOLUTE(.); + } > dram + + .data : ALIGN(4) { + *(.data) + *(.rodata .rodata.*) + } > dram +} + +INCLUDE "../../../../flasher_stub/ld/rom_32c5.ld" From bce33d8558021d1246b98e2b5f453cf25bb2ffc8 Mon Sep 17 00:00:00 2001 From: Jaroslav Burian Date: Fri, 28 Jun 2024 08:15:21 +0200 Subject: [PATCH 205/209] feat(esp32c5): Add USB-serial/JTAG stub support - Enables USB-serial/JTAG stub - Enables USE_MAX_CPU_FREQ --- .../targets/stub_flasher/stub_flasher_32c5.json | 8 ++++---- flasher_stub/include/soc_support.h | 12 +++++++++++- flasher_stub/stub_io.c | 2 +- .../ram_helloworld/helloworld-esp32c5.bin | Bin 128 -> 128 bytes .../images/ram_helloworld/source/ld/app_32c5.ld | 4 ++-- test/test_esptool.py | 9 ++++++++- 6 files changed, 26 insertions(+), 9 deletions(-) diff --git a/esptool/targets/stub_flasher/stub_flasher_32c5.json b/esptool/targets/stub_flasher/stub_flasher_32c5.json index ceda12bdd..871a95d5e 100644 --- a/esptool/targets/stub_flasher/stub_flasher_32c5.json +++ b/esptool/targets/stub_flasher/stub_flasher_32c5.json @@ -1,8 +1,8 @@ { - "entry": 1082131910, - "text": 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"text_start": 1082130432, - "data": "DACEQO4IgEA6CYBAkgmAQGAKgEDMCoBAegqAQLYHgEAcCoBAXAqAQKYJgEBmB4BA2gmAQGYHgEDICIBADAmAQDoJgECSCYBA2giAQCAIgEBQCIBA1giAQCQNgEA6CYBA5AuAQNgMgECyBoBAAg2AQLIGgECyBoBAsgaAQLIGgECyBoBAsgaAQLIGgECyBoBAgAuAQLIGgEAADIBA2AyAQA==", - "data_start": 1082469288, + "data": "FACEQG4KgEC+CoBAFguAQOQLgEBQDIBA/guAQDoJgECgC4BA4AuAQCoLgEDqCIBAXguAQOoIgEBICoBAjgqAQL4KgEAWC4BAWgqAQJ4JgEDOCYBAVgqAQKgOgEC+CoBAaA2AQGAOgEAqCIBAiA6AQCoIgEAqCIBAKgiAQCoIgEAqCIBAKgiAQCoIgEAqCIBABA2AQCoIgECGDYBAYA6AQA==", + "data_start": 1082469296, "bss_start": 1082392576 } \ No newline at end of file diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h index 0f2e390f8..1170ece7c 100644 --- a/flasher_stub/include/soc_support.h +++ b/flasher_stub/include/soc_support.h @@ -47,7 +47,7 @@ #endif // ESP32S3 #ifdef ESP32C5 -#define WITH_USB_JTAG_SERIAL 0 // not implemented yet +#define WITH_USB_JTAG_SERIAL 1 #define IS_RISCV 1 #endif // ESP32C5 @@ -347,6 +347,16 @@ #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ #endif // ESP32C6 +#if ESP32C5 +#define UART_USB_JTAG_SERIAL 3 + +#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xD0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */ + +#define CLIC_EXT_INTR_NUM_OFFSET 16 /* For CLIC first 16 interrupts are reserved as internal */ +#define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ +#endif // ESP32C5 + #ifdef ESP32H2 #define UART_USB_JTAG_SERIAL 3 diff --git a/flasher_stub/stub_io.c b/flasher_stub/stub_io.c index f86f67e7a..1331bc7a8 100644 --- a/flasher_stub/stub_io.c +++ b/flasher_stub/stub_io.c @@ -65,7 +65,7 @@ static void stub_configure_rx_uart(void) #if WITH_USB_JTAG_SERIAL if (stub_uses_usb_jtag_serial()) { #if IS_RISCV - #if ESP32P4 + #if ESP32P4 || ESP32C5 WRITE_REG(INTERRUPT_CORE0_USB_INTR_MAP_REG, ETS_USB_INUM + CLIC_EXT_INTR_NUM_OFFSET); #else WRITE_REG(INTERRUPT_CORE0_USB_INTR_MAP_REG, ETS_USB_INUM); // Route USB interrupt to CPU diff --git a/test/images/ram_helloworld/helloworld-esp32c5.bin b/test/images/ram_helloworld/helloworld-esp32c5.bin index 971ebec37f198dd23f7bd8b9162dbf03435884d4..eab9d52efa0797438f08e0b97acffc9dd449fab5 100644 GIT binary patch delta 101 zcmZo*Y+$s0$;7}A!{6xej)8$e9EchI{|AwbATbFb!%i!sk#);M{ipLl16qkOZP%3ZxrAH<1>Y-VaG`~EW!1+qOVfRt7quYKo0{{lU BCEox5 delta 101 zcmZo*Y+$s0$;80m!rS2Rj)8$e9EchI{|AwbATbFb!%50R+lH!Kh*z! z-k_j+b-xQ=!$fNpMTTn{U!{5f@@`|vzQi$O>xEMCtPOypHlk5AH`XLVW<0LN7! A)Bpeg diff --git a/test/images/ram_helloworld/source/ld/app_32c5.ld b/test/images/ram_helloworld/source/ld/app_32c5.ld index ea84886c0..9594e6880 100644 --- a/test/images/ram_helloworld/source/ld/app_32c5.ld +++ b/test/images/ram_helloworld/source/ld/app_32c5.ld @@ -1,6 +1,6 @@ MEMORY { - iram : org = 0x40800d44, len = 0x100 - dram : org = 0x40800e44, len = 0x100 + iram : org = 0x40810f5c, len = 0x100 + dram : org = 0x4081105c, len = 0x100 } ENTRY(ram_main) diff --git a/test/test_esptool.py b/test/test_esptool.py index 46e93950d..906013150 100755 --- a/test/test_esptool.py +++ b/test/test_esptool.py @@ -184,7 +184,14 @@ def run_esptool_process(cmd): preload and arg_preload_port and arg_chip - in ["esp32c3", "esp32s3", "esp32c6", "esp32h2", "esp32p4"] # With U-JS + in [ + "esp32c3", + "esp32s3", + "esp32c6", + "esp32h2", + "esp32p4", + "esp32c5", + ] # With U-JS ): port_index = base_cmd.index("--port") + 1 base_cmd[port_index] = arg_preload_port # Set the port to the preload one From 531c90ce39ba01a8b97126ec4492e24cd99f7456 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 16 Jul 2024 12:25:45 +0200 Subject: [PATCH 206/209] ci(dev-release): use commitizen for dev release --- .github/workflows/build_esptool.yml | 4 +- .../workflows/dev_release_esptool_pypi.yml | 41 ------------------- .github/workflows/release_esptool_pypi.yml | 2 +- ci/patch_dev_release.py | 40 ------------------ esptool/__init__.py | 2 +- pyproject.toml | 4 +- 6 files changed, 5 insertions(+), 88 deletions(-) delete mode 100644 .github/workflows/dev_release_esptool_pypi.yml delete mode 100644 ci/patch_dev_release.py diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index b5efd34db..c86a6c4c9 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -89,7 +89,7 @@ jobs: create_release: name: Create GitHub release - if: startsWith(github.ref, 'refs/tags/') && !(contains(github.ref_name, 'dev')) + if: startsWith(github.ref, 'refs/tags/') needs: build-esptool-binaries runs-on: ubuntu-latest permissions: @@ -127,5 +127,5 @@ jobs: body_path: changelog_body.md name: Version ${{ steps.get_version.outputs.VERSION }} draft: true - prerelease: false + prerelease: ${{ contains(github.ref_name, 'dev') }} files: esptool-v${{ steps.get_version.outputs.VERSION }}-*.zip diff --git a/.github/workflows/dev_release_esptool_pypi.yml b/.github/workflows/dev_release_esptool_pypi.yml deleted file mode 100644 index 61cd63038..000000000 --- a/.github/workflows/dev_release_esptool_pypi.yml +++ /dev/null @@ -1,41 +0,0 @@ -# This workflow will upload an esptool Python package when a dev release tag (e.g. "v4.7.dev2") is pushed - -name: PyPI dev release - -on: - push: - tags: - - v*.*.dev* - -jobs: - build_and_upload: - - runs-on: ubuntu-latest - - if: startsWith(github.ref, 'refs/tags/') && contains(github.ref_name, 'dev') - - steps: - - uses: actions/checkout@master - - name: Set up Python 3.8 - uses: actions/setup-python@master - with: - python-version: '3.8' - - name: Install dependencies - run: | - python -m pip install --upgrade pip - python -m pip install twine setuptools - - - name: Create development release ${{ github.ref_name }} - env: - TWINE_USERNAME: __token__ - TWINE_PASSWORD: ${{ secrets.PYPI_PASSWORD }} - TWINE_NON_INTERACTIVE: true - run: | - python ci/patch_dev_release.py --version ${{ github.ref_name }} esptool/__init__.py - git diff - python -m pip download esptool==$(python setup.py -V) && echo "Version ${{ github.ref_name }} already published, skipping..." && exit 1 - - echo "Packaging and publishing new esptool development release: ${{ github.ref_name }}" - python setup.py sdist - tar -ztvf dist/* - twine upload dist/* diff --git a/.github/workflows/release_esptool_pypi.yml b/.github/workflows/release_esptool_pypi.yml index cd0c01bb0..5e6fb0b8a 100644 --- a/.github/workflows/release_esptool_pypi.yml +++ b/.github/workflows/release_esptool_pypi.yml @@ -4,7 +4,7 @@ name: PyPI release on: release: - types: [released] + types: [released, prereleased] jobs: build_and_upload: diff --git a/ci/patch_dev_release.py b/ci/patch_dev_release.py deleted file mode 100644 index 9cd9feff7..000000000 --- a/ci/patch_dev_release.py +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD -# -# SPDX-License-Identifier: GPL-2.0-or-later - -import argparse -import re - -LINE_RE = re.compile(r"^__version__ = ['\"]([^'\"]*)['\"]") -NEW_LINE = '__version__ = "{}"\n' - - -def patch_file(path, new_version): - assert ".dev" in new_version - new_version = new_version.lstrip("v") - - with open(path, "r") as fin: - lines = fin.readlines() - - for i, line in enumerate(lines, start=0): - m = LINE_RE.search(line) - if m: - lines[i] = NEW_LINE.format(new_version) - break - - with open(path, "w") as fout: - fout.writelines(lines) - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument("file", help="Path to script with __version__") - parser.add_argument( - "--version", help="Development version specifier to patch the version to" - ) - args = parser.parse_args() - patch_file(args.file, args.version) - - -if __name__ == "__main__": - main() diff --git a/esptool/__init__.py b/esptool/__init__.py index b66a2f1b0..794f62e6e 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.7.0" +__version__ = "4.8.0.dev4" import argparse import inspect diff --git a/pyproject.toml b/pyproject.toml index 0bd52b19a..fa874118f 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -74,11 +74,9 @@ version = {attr = "esptool.__init__.__version__"} [tool.commitizen] - version = "4.7.0" - update_changelog_on_bump = true + version = "4.8.0.dev4" tag_format = "v$version" changelog_start_rev = "v4.2.1" - changelog_merge_prerelease = true annotated_tag = true bump_message = "change: Update version to $new_version" version_files = [ From ef96323864f8cfd4b4ae84388728ddb5ea45cc45 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 16 Jul 2024 12:44:59 +0200 Subject: [PATCH 207/209] change: remove failing part of action for test --- .github/workflows/build_esptool.yml | 44 ++++++++++++++--------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index c86a6c4c9..fd390ae6e 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -8,7 +8,7 @@ jobs: runs-on: ${{ matrix.RUN_ON }} strategy: matrix: - platform: [macos, windows, linux-amd64, linux-arm32, linux-arm64] + platform: [macos, windows, linux-amd64] include: - platform: macos TARGET: macos @@ -23,16 +23,16 @@ jobs: TARGET: linux-amd64 SEPARATOR: ':' RUN_ON: ubuntu-20.04 - - platform: linux-arm32 - CONTAINER: python:3.8-bullseye - TARGET: linux-arm32 - SEPARATOR: ':' - RUN_ON: [ARM, self-hosted, linux] - - platform: linux-arm64 - CONTAINER: python:3.8-bullseye - TARGET: linux-arm64 - SEPARATOR: ':' - RUN_ON: [ARM64, self-hosted, linux] + # - platform: linux-arm32 + # CONTAINER: python:3.8-bullseye + # TARGET: linux-arm32 + # SEPARATOR: ':' + # RUN_ON: [ARM, self-hosted, linux] + # - platform: linux-arm64 + # CONTAINER: python:3.8-bullseye + # TARGET: linux-arm64 + # SEPARATOR: ':' + # RUN_ON: [ARM64, self-hosted, linux] container: ${{ matrix.CONTAINER }} # use python container on ARM env: DISTPATH: esptool-${{ matrix.TARGET }} @@ -60,17 +60,17 @@ jobs: pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico --add-data="${{ env.EFUSE_DIR }}*.yaml${{ matrix.SEPARATOR }}${{ env.EFUSE_DIR }}" espefuse.py pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico espsecure.py pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=ci/espressif.ico esp_rfc2217_server.py - - name: Sign binaries - if: matrix.platform == 'windows' && github.event_name != 'pull_request' - env: - CERTIFICATE: ${{ secrets.CERTIFICATE }} - CERTIFICATE_PASSWORD: ${{ secrets.CERTIFICATE_PASSWORD }} - shell: pwsh - run: | - ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/esptool.exe - ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/espefuse.exe - ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/espsecure.exe - ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/esp_rfc2217_server.exe + # - name: Sign binaries + # if: matrix.platform == 'windows' && github.event_name != 'pull_request' + # env: + # CERTIFICATE: ${{ secrets.CERTIFICATE }} + # CERTIFICATE_PASSWORD: ${{ secrets.CERTIFICATE_PASSWORD }} + # shell: pwsh + # run: | + # ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/esptool.exe + # ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/espefuse.exe + # ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/espsecure.exe + # ./ci/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/esp_rfc2217_server.exe - name: Test binaries shell: bash run: | From e8efc1e94e2114a0cd8cc3621da26bc356caff2c Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 16 Jul 2024 13:44:06 +0200 Subject: [PATCH 208/209] change: Update version to 4.8.0.dev5 --- esptool/__init__.py | 2 +- pyproject.toml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/esptool/__init__.py b/esptool/__init__.py index 794f62e6e..8153c7bee 100644 --- a/esptool/__init__.py +++ b/esptool/__init__.py @@ -28,7 +28,7 @@ "write_mem", ] -__version__ = "4.8.0.dev4" +__version__ = "4.8.0.dev5" import argparse import inspect diff --git a/pyproject.toml b/pyproject.toml index fa874118f..006eb4b92 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -74,7 +74,7 @@ version = {attr = "esptool.__init__.__version__"} [tool.commitizen] - version = "4.8.0.dev4" + version = "4.8.0.dev5" tag_format = "v$version" changelog_start_rev = "v4.2.1" annotated_tag = true From 97d5224212986ccb59de0716cf75af48c345202e Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Tue, 16 Jul 2024 15:30:16 +0200 Subject: [PATCH 209/209] fix: this is fix for ci config to test release --- .github/workflows/build_esptool.yml | 8 +++++++- .github/workflows/release_esptool_pypi.yml | 2 +- .github/workflows/test_esptool.yml | 7 +++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build_esptool.yml b/.github/workflows/build_esptool.yml index fd390ae6e..c7b2cde89 100644 --- a/.github/workflows/build_esptool.yml +++ b/.github/workflows/build_esptool.yml @@ -99,6 +99,12 @@ jobs: id: get_version run: echo "VERSION=${GITHUB_REF#refs/tags/v}" >> $GITHUB_OUTPUT shell: bash + - name: Get previous version + id: get_previous_version + env: + FILTER: "${{ contains(github.ref_name, 'dev') && 'first' || 'map(select(.prerelease == false)) | first' }} | .tag_name" + run: echo "VERSION=$(curl https://api.github.com/repos/peterdragun/esptool/releases | jq -r '${{env.FILTER}}')" >> $GITHUB_OUTPUT + shell: bash - name: Checkout uses: actions/checkout@master with: @@ -109,7 +115,7 @@ jobs: pip install --user -e ".[dev]" - name: Generate changelog run: | - cz changelog ${{ steps.get_version.outputs.VERSION }} --template ci/gh_changelog_template.md.j2 --file-name changelog_body.md + cz changelog ${{ steps.get_previous_version.outputs.VERSION }}..${{ steps.get_version.outputs.VERSION }} --template ci/gh_changelog_template.md.j2 --file-name changelog_body.md cat changelog_body.md - name: Download built binaries uses: actions/download-artifact@master diff --git a/.github/workflows/release_esptool_pypi.yml b/.github/workflows/release_esptool_pypi.yml index 5e6fb0b8a..e9a3bbb05 100644 --- a/.github/workflows/release_esptool_pypi.yml +++ b/.github/workflows/release_esptool_pypi.yml @@ -4,7 +4,7 @@ name: PyPI release on: release: - types: [released, prereleased] + types: [published] jobs: build_and_upload: diff --git a/.github/workflows/test_esptool.yml b/.github/workflows/test_esptool.yml index f398f650c..7c2290f07 100644 --- a/.github/workflows/test_esptool.yml +++ b/.github/workflows/test_esptool.yml @@ -14,6 +14,13 @@ jobs: - name: Checkout ref commit uses: actions/checkout@master + - name: Get previous version + id: get_previous_version + env: + FILTER: "${{ contains(github.ref_name, 'dev') && 'first' || 'map(select(.prerelease == false)) | first' }} | .tag_name" + run: | + echo "VERSION=$(curl https://api.github.com/repos/peterdragun/esptool/releases | jq -r '${{env.FILTER}}')" + - name: Set up Python ${{ matrix.python-version }} uses: actions/setup-python@master with: