From 1b7eac43f76fa27d70ff2efe1416ecdafe9d9a99 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 18 Nov 2022 20:36:51 -0800 Subject: [PATCH 01/61] WIP metaclass name inference --- magma/circuit.py | 34 +- tests/gold/TopGen.json | 14 +- .../gold/test_assign_operator2_3_coreir.json | 6 +- tests/gold/test_assign_operator2_3_verilog.v | 4 +- .../test_assign_operator2_None_coreir.json | 6 +- .../gold/test_assign_operator2_None_verilog.v | 4 +- tests/gold/test_assign_operator_3_coreir.json | 8 +- tests/gold/test_assign_operator_3_verilog.v | 6 +- .../test_assign_operator_None_coreir.json | 8 +- .../gold/test_assign_operator_None_verilog.v | 6 +- .../test_compile_guard_anon_driver_driven.v | 14 +- ...st_compile_guard_anon_driver_nested_type.v | 299 ++++++++++++------ tests/gold/test_compile_guard_assert.json | 16 +- .../gold/test_compile_guard_drive_output.json | 12 +- tests/gold/test_when_memory_Bits8.mlir | 2 +- .../test_when_memory_Tuplex_Bit_y_Bits7.mlir | 2 +- tests/gold/test_when_non_port.mlir | 5 +- tests/gold/test_when_recursive_non_port.mlir | 17 +- tests/gold/test_when_reg_ce.mlir | 2 +- .../gold/test_when_reg_ce_already_wired.mlir | 2 +- .../gold/test_when_reg_ce_explicit_wire.mlir | 2 +- .../test_when_reg_ce_explicit_wire_twice.mlir | 2 +- ...hen_reg_ce_explicit_wire_with_default.mlir | 2 +- .../test_when_reg_ce_implicit_wire_twice.mlir | 2 +- tests/gold/test_when_reg_ce_multiple.mlir | 2 +- tests/gold/test_when_register_default.mlir | 2 +- tests/gold/test_when_register_no_default.mlir | 2 +- tests/gold/test_when_spurious_assign.mlir | 6 +- tests/gold/test_when_user_reg.mlir | 2 +- tests/gold/test_when_user_reg_enable.mlir | 2 +- tests/gold/uniquification_key_error_mux.json | 10 +- tests/gold/uniquify_equal.json | 6 +- tests/gold/uniquify_multiple_rename.json | 18 +- tests/gold/uniquify_unequal.json | 16 +- tests/test_backend/test_mlir/examples.py | 2 +- .../golds/complex_mixed_direction_ports2.mlir | 2 +- .../test_backend/test_mlir/golds/counter.mlir | 2 +- .../golds/simple_memory_wrapper.mlir | 2 +- .../golds/simple_module_params_instance.mlir | 2 +- .../test_mlir/golds/simple_redefinition.mlir | 4 +- .../test_mlir/golds/xmr_bind.mlir | 6 +- tests/test_circuit/gold/test_add8cin.json | 10 +- .../gold/test_anon_value_Array((2, Bit)).json | 13 +- .../gold/test_anon_value_Array((2, Bit)).v | 6 +- .../gold/test_anon_value_Bit.json | 12 +- tests/test_circuit/gold/test_anon_value_Bit.v | 6 +- .../gold/test_anon_value_Bits(2).json | 13 +- .../gold/test_anon_value_Bits(2).v | 6 +- .../test_anon_value_Tuple(x=Bit,y=Bit).json | 15 +- .../gold/test_anon_value_Tuple(x=Bit,y=Bit).v | 18 +- .../test_circuit/gold/test_for_loop_def.json | 8 +- tests/test_circuit/gold/test_for_loop_def.v | 8 +- .../gold/test_ignore_undriven_coreir.json | 14 +- .../test_ignore_unused_undriven_hierarchy.v | 16 +- tests/test_circuit/gold/test_unwired_output.v | 4 +- tests/test_circuit/test_define.py | 2 +- tests/test_circuit/test_inspect.py | 4 +- tests/test_circuit/test_new_style_syntax.py | 14 +- tests/test_circuit/test_reg_enable_call.py | 8 +- tests/test_compile/gold/test_header_footer.v | 8 +- tests/test_coreir/gold/linker_test0.json | 8 +- .../gold/test_auto_wire_tuple_clocks.v | 8 +- .../test_multi_direction_tuple_instance.json | 6 +- tests/test_coreir/gold/test_nesting.json | 18 +- .../test_ignore_unused_undriven_hierarchy.v | 16 +- tests/test_errors/test_tuple_errors.py | 4 +- tests/test_higher/test_braid.py | 2 +- tests/test_higher/test_curry.py | 8 +- tests/test_higher/test_join.py | 2 +- tests/test_ir/gold/declaretest.v | 6 +- tests/test_ir/test_ir.py | 16 +- tests/test_ir_pass.py | 6 +- tests/test_meta/gold/creg.v | 6 +- ...oreir_wires_arr_tuple_TuplexInBityOutBit.v | 10 +- ...insert_coreir_wires_instance_Array5Bits5.v | 22 +- .../gold/insert_coreir_wires_instance_Bit.v | 8 +- .../gold/insert_coreir_wires_instance_Bits5.v | 8 +- ...sert_coreir_wires_instance_TupleBits5Bit.v | 12 +- ...t_coreir_wires_temp_array_not_whole_anon.v | 8 +- ...rt_coreir_wires_tuple_TuplexInBityOutBit.v | 10 +- tests/test_primitives/gold/test_memory_arr.v | 2 +- .../gold/test_memory_basic.mlir | 64 ++-- .../gold/test_memory_product.v | 2 +- .../gold/test_memory_product_init.v | 2 +- .../gold/test_memory_read_latency_False.v | 8 +- .../gold/test_memory_read_latency_True.v | 8 +- .../gold/test_memory_read_only.v | 8 +- tests/test_symbol_table_generation.py | 13 +- .../gold/TestSequential2NestedLoopUnroll.v | 8 +- .../test_syntax/gold/test_inline_comb_basic.v | 15 +- .../test_syntax/gold/test_inline_comb_list.v | 14 +- .../test_syntax/gold/test_inline_comb_wire.v | 7 +- .../gold/test_renamed_args_wire.json | 6 +- .../gold/test_AsyncResetN[Out]_cast.v | 12 +- .../gold/test_AsyncReset[Out]_cast.v | 12 +- tests/test_type/gold/test_anon_bits.v | 25 +- .../gold/test_array2_nested_bits_temporary.v | 20 +- .../gold/test_ndarray_dynamic_getitem.v | 58 ++-- .../gold/test_ndarray_dynamic_getitem2.v | 106 +++---- .../gold/test_ndarray_dynamic_getitem3.v | 154 ++++----- tests/test_type/test_const_wire_golden.json | 4 +- .../test_coreir_wrap_golden_AsyncReset.json | 12 +- .../test_coreir_wrap_golden_Clock.json | 12 +- tests/test_verilog/gold/TestDisplay.v | 12 +- tests/test_verilog/gold/TestFDisplay.v | 12 +- tests/test_verilog/gold/TestFLog.v | 12 +- tests/test_verilog/gold/TestLog.v | 12 +- tests/test_verilog/gold/Top.v | 16 +- tests/test_verilog/gold/bind_test.v | 6 +- tests/test_verilog/gold/bind_uniq_test.v | 98 +++--- .../test_verilog/gold/test_inline_tuple.json | 46 +-- tests/test_verilog/gold/test_inline_tuple.sv | 14 +- ...test_inline_verilog_share_default_clocks.v | 11 +- .../test_inline_wire_insertion_bad_verilog.v | 16 +- tests/test_verilog/gold/test_pad.v | 22 +- tests/test_verilog/gold/test_rxmod_top.json | 10 +- .../gold/top-declare-coreir-verilog.v | 14 +- .../test_verilog/gold/top-declare-coreir.json | 20 +- tests/test_verilog/gold/top-declare-verilog.v | 10 +- .../gold/top-define-coreir-verilog.json | 20 +- .../gold/top-define-coreir-verilog.v | 14 +- .../test_verilog/gold/top-define-coreir.json | 20 +- tests/test_verilog/gold/top-define-verilog.v | 10 +- tests/test_wire/gold/arg1.v | 6 +- tests/test_wire/gold/arg2.v | 6 +- tests/test_wire/gold/array1.v | 6 +- tests/test_wire/gold/array2.v | 6 +- tests/test_wire/gold/array3.v | 6 +- tests/test_wire/gold/call1.v | 6 +- tests/test_wire/gold/call2.v | 6 +- tests/test_wire/gold/compose.v | 10 +- tests/test_wire/gold/const0.v | 12 +- tests/test_wire/gold/const1.v | 12 +- tests/test_wire/gold/const_bits_Bits_1.v | 8 +- tests/test_wire/gold/const_bits_Bits_2.v | 8 +- tests/test_wire/gold/const_bits_Bits_3.v | 8 +- tests/test_wire/gold/const_bits_SInt_1.v | 8 +- tests/test_wire/gold/const_bits_SInt_2.v | 8 +- tests/test_wire/gold/const_bits_SInt_3.v | 8 +- tests/test_wire/gold/const_bits_UInt_1.v | 8 +- tests/test_wire/gold/const_bits_UInt_2.v | 8 +- tests/test_wire/gold/const_bits_UInt_3.v | 8 +- tests/test_wire/gold/flip.v | 6 +- tests/test_wire/gold/named1.v | 6 +- tests/test_wire/gold/named2a.v | 6 +- tests/test_wire/gold/named2b.v | 6 +- tests/test_wire/gold/named2c.v | 6 +- tests/test_wire/gold/pos.v | 6 +- 148 files changed, 1139 insertions(+), 942 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index f9c97fcdf..93310d7db 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -37,8 +37,8 @@ ) from magma.find_unconnected_ports import find_and_log_unconnected_ports from magma.logging import root_logger, capture_logs -from magma.ref import TempNamedRef -from magma.t import In +from magma.ref import TempNamedRef, AnonRef +from magma.t import In, Type from magma.view import PortView from magma.wire_container import WiringLog, AggregateWireable @@ -204,6 +204,16 @@ def _get_intermediate_values(value): return values +def _infer_names(dct): + """Try to infer value/inst names from metaclass dct""" + for key, value in dct.items(): + if isinstance(value, Type): + if isinstance(value.name, AnonRef): + value.name = TempNamedRef(key, value) + if isinstance(type(value), CircuitKind) and not value.name: + value.name = key + + class CircuitKind(type): def __prepare__(name, bases, **kwargs): ctx = DefinitionContext(StagedPlacer(name)) @@ -256,9 +266,11 @@ def __new__(metacls, name, bases, dct): # Override staged context with '_context_' from namespace if # available. cls._context_ = dct.get("_context_", context) + _infer_names(dct) # do before place instances for default logic cls._context_.place_instances(cls) _setup_interface(cls) cls._context_.finalize(cls) + pop_definition_context(use_staged_logger=True) return cls @@ -392,12 +404,18 @@ def set_debug_info(self, debug_info): self.debug_info = debug_info def __str__(self): - if self.name: - return f"{self.name}<{type(self)}>" - name = f"AnonymousCircuitInst{id(self)}" - interface = ", ".join(f"{name}: {type(value)}" - for name, value in self.interface.ports.items()) - return f"{name}<{interface}>" + name = self.name + if not name: + name = f"AnonymousCircuitInst{id(self)}" + if type(self) is AnonymousCircuitType: + interface = ", ".join( + f"{name}: {type(value)}" + for name, value in self.interface.ports.items() + ) + name += f"<{interface}>" + else: + name += f"<{type(self)}>" + return name def __repr__(self): args = [] diff --git a/tests/gold/TopGen.json b/tests/gold/TopGen.json index fd9add260..13138fbce 100644 --- a/tests/gold/TopGen.json +++ b/tests/gold/TopGen.json @@ -17,20 +17,20 @@ ["z","Bit"] ]], "instances":{ - "MyMux1x2_inst0":{ - "modref":"global.MyMux1x2" - }, "const_0_1":{ "genref":"coreir.const", "genargs":{"width":["Int",1]}, "modargs":{"value":[["BitVector",1],"1'h0"]} + }, + "mux":{ + "modref":"global.MyMux1x2" } }, "connections":[ - ["self.x","MyMux1x2_inst0.I0.0"], - ["self.y","MyMux1x2_inst0.I1.0"], - ["self.z","MyMux1x2_inst0.O.0"], - ["const_0_1.out","MyMux1x2_inst0.S"] + ["mux.S","const_0_1.out"], + ["self.x","mux.I0.0"], + ["self.y","mux.I1.0"], + ["self.z","mux.O.0"] ] } } diff --git a/tests/gold/test_assign_operator2_3_coreir.json b/tests/gold/test_assign_operator2_3_coreir.json index 486b0f5a6..5b8901bd2 100644 --- a/tests/gold/test_assign_operator2_3_coreir.json +++ b/tests/gold/test_assign_operator2_3_coreir.json @@ -16,13 +16,13 @@ ["c",["Array",3,"Bit"]] ]], "instances":{ - "And3_inst0":{ + "and2":{ "modref":"global.And3" } }, "connections":[ - ["And3_inst0.O","And3_inst0.I0"], - ["self.a","And3_inst0.I1"], + ["and2.O","and2.I0"], + ["self.a","and2.I1"], ["self.c","self.b"] ] } diff --git a/tests/gold/test_assign_operator2_3_verilog.v b/tests/gold/test_assign_operator2_3_verilog.v index 235247117..d787afb1d 100644 --- a/tests/gold/test_assign_operator2_3_verilog.v +++ b/tests/gold/test_assign_operator2_3_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator2_3_verilog (input [2:0] a, input [2:0] b, output [2:0] c); -wire [2:0] And3_inst0_O; -And3 And3_inst0 (.I0(And3_inst0_O), .I1(a), .O(And3_inst0_O)); +wire [2:0] and2_O; +And3 and2 (.I0(and2_O), .I1(a), .O(and2_O)); assign c = b; endmodule diff --git a/tests/gold/test_assign_operator2_None_coreir.json b/tests/gold/test_assign_operator2_None_coreir.json index 6f2c2e82d..b349fb11f 100644 --- a/tests/gold/test_assign_operator2_None_coreir.json +++ b/tests/gold/test_assign_operator2_None_coreir.json @@ -16,13 +16,13 @@ ["c","Bit"] ]], "instances":{ - "AndNone_inst0":{ + "and2":{ "modref":"global.AndNone" } }, "connections":[ - ["AndNone_inst0.O","AndNone_inst0.I0"], - ["self.a","AndNone_inst0.I1"], + ["and2.O","and2.I0"], + ["self.a","and2.I1"], ["self.c","self.b"] ] } diff --git a/tests/gold/test_assign_operator2_None_verilog.v b/tests/gold/test_assign_operator2_None_verilog.v index 2429c453a..9508980b2 100644 --- a/tests/gold/test_assign_operator2_None_verilog.v +++ b/tests/gold/test_assign_operator2_None_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator2_None_verilog (input a, input b, output c); -wire AndNone_inst0_O; -AndNone AndNone_inst0 (.I0(AndNone_inst0_O), .I1(a), .O(AndNone_inst0_O)); +wire and2_O; +AndNone and2 (.I0(and2_O), .I1(a), .O(and2_O)); assign c = b; endmodule diff --git a/tests/gold/test_assign_operator_3_coreir.json b/tests/gold/test_assign_operator_3_coreir.json index 47a75dfed..850895368 100644 --- a/tests/gold/test_assign_operator_3_coreir.json +++ b/tests/gold/test_assign_operator_3_coreir.json @@ -16,14 +16,14 @@ ["c",["Array",3,"Bit"]] ]], "instances":{ - "And3_inst0":{ + "and2":{ "modref":"global.And3" } }, "connections":[ - ["self.a","And3_inst0.I0"], - ["self.b","And3_inst0.I1"], - ["self.c","And3_inst0.O"] + ["self.a","and2.I0"], + ["self.b","and2.I1"], + ["self.c","and2.O"] ] } } diff --git a/tests/gold/test_assign_operator_3_verilog.v b/tests/gold/test_assign_operator_3_verilog.v index b0aaf0f15..fdfd0e47b 100644 --- a/tests/gold/test_assign_operator_3_verilog.v +++ b/tests/gold/test_assign_operator_3_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator_3_verilog (input [2:0] a, input [2:0] b, output [2:0] c); -wire [2:0] And3_inst0_O; -And3 And3_inst0 (.I0(a), .I1(b), .O(And3_inst0_O)); -assign c = And3_inst0_O; +wire [2:0] and2_O; +And3 and2 (.I0(a), .I1(b), .O(and2_O)); +assign c = and2_O; endmodule diff --git a/tests/gold/test_assign_operator_None_coreir.json b/tests/gold/test_assign_operator_None_coreir.json index 63b6c2aa6..cc6f8cb75 100644 --- a/tests/gold/test_assign_operator_None_coreir.json +++ b/tests/gold/test_assign_operator_None_coreir.json @@ -16,14 +16,14 @@ ["c","Bit"] ]], "instances":{ - "AndNone_inst0":{ + "and2":{ "modref":"global.AndNone" } }, "connections":[ - ["self.a","AndNone_inst0.I0"], - ["self.b","AndNone_inst0.I1"], - ["self.c","AndNone_inst0.O"] + ["self.a","and2.I0"], + ["self.b","and2.I1"], + ["self.c","and2.O"] ] } } diff --git a/tests/gold/test_assign_operator_None_verilog.v b/tests/gold/test_assign_operator_None_verilog.v index f3015eab4..1311cfe38 100644 --- a/tests/gold/test_assign_operator_None_verilog.v +++ b/tests/gold/test_assign_operator_None_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator_None_verilog (input a, input b, output c); -wire AndNone_inst0_O; -AndNone AndNone_inst0 (.I0(a), .I1(b), .O(AndNone_inst0_O)); -assign c = AndNone_inst0_O; +wire and2_O; +AndNone and2 (.I0(a), .I1(b), .O(and2_O)); +assign c = and2_O; endmodule diff --git a/tests/gold/test_compile_guard_anon_driver_driven.v b/tests/gold/test_compile_guard_anon_driver_driven.v index bda3fab10..4f1a8a7b4 100644 --- a/tests/gold/test_compile_guard_anon_driver_driven.v +++ b/tests/gold/test_compile_guard_anon_driver_driven.v @@ -16,6 +16,13 @@ module coreir_reg #( assign out = outReg; endmodule +module corebit_wire ( + input in, + output out +); + assign out = in; +endmodule + module Register ( input I, output O, @@ -50,11 +57,16 @@ module _Top ( input I, input CLK ); +wire x_out; `ifdef COND A A ( - .port_0(I), + .port_0(x_out), .port_1(CLK) ); `endif +corebit_wire x ( + .in(I), + .out(x_out) +); endmodule diff --git a/tests/gold/test_compile_guard_anon_driver_nested_type.v b/tests/gold/test_compile_guard_anon_driver_nested_type.v index ba6f4d9a2..8420ec94e 100644 --- a/tests/gold/test_compile_guard_anon_driver_nested_type.v +++ b/tests/gold/test_compile_guard_anon_driver_nested_type.v @@ -1,3 +1,12 @@ +module coreir_wire #( + parameter width = 1 +) ( + input [width-1:0] in, + output [width-1:0] out +); + assign out = in; +endmodule + module coreir_reg #( parameter width = 1, parameter clk_posedge = 1, @@ -225,110 +234,200 @@ module _Top ( input I, input CLK ); +wire [9:0] x_0_x_out; +wire [9:0] x_1_x_out; +wire [9:0] x_2_x_out; +wire [9:0] x_3_x_out; +wire [9:0] x_4_x_out; +wire [9:0] x_5_x_out; +wire [9:0] x_6_x_out; +wire [9:0] x_7_x_out; +wire [9:0] x_8_x_out; +wire [9:0] x_9_x_out; `ifdef COND A A ( - .port_0(I), - .port_1(I), - .port_2(I), - .port_3(I), - .port_4(I), - .port_5(I), - .port_6(I), - .port_7(I), - .port_8(I), - .port_9(I), - .port_10(I), - .port_11(I), - .port_12(I), - .port_13(I), - .port_14(I), - .port_15(I), - .port_16(I), - .port_17(I), - .port_18(I), - .port_19(I), - .port_20(I), - .port_21(I), - .port_22(I), - .port_23(I), - .port_24(I), - .port_25(I), - .port_26(I), - .port_27(I), - .port_28(I), - .port_29(I), - .port_30(I), - .port_31(I), - .port_32(I), - .port_33(I), - .port_34(I), - .port_35(I), - .port_36(I), - .port_37(I), - .port_38(I), - .port_39(I), - .port_40(I), - .port_41(I), - .port_42(I), - .port_43(I), - .port_44(I), - .port_45(I), - .port_46(I), - .port_47(I), - .port_48(I), - .port_49(I), - .port_50(I), - .port_51(I), - .port_52(I), - .port_53(I), - .port_54(I), - .port_55(I), - .port_56(I), - .port_57(I), - .port_58(I), - .port_59(I), - .port_60(I), - .port_61(I), - .port_62(I), - .port_63(I), - .port_64(I), - .port_65(I), - .port_66(I), - .port_67(I), - .port_68(I), - .port_69(I), - .port_70(I), - .port_71(I), - .port_72(I), - .port_73(I), - .port_74(I), - .port_75(I), - .port_76(I), - .port_77(I), - .port_78(I), - .port_79(I), - .port_80(I), - .port_81(I), - .port_82(I), - .port_83(I), - .port_84(I), - .port_85(I), - .port_86(I), - .port_87(I), - .port_88(I), - .port_89(I), - .port_90(I), - .port_91(I), - .port_92(I), - .port_93(I), - .port_94(I), - .port_95(I), - .port_96(I), - .port_97(I), - .port_98(I), - .port_99(I), + .port_0(x_0_x_out[0]), + .port_1(x_0_x_out[1]), + .port_2(x_0_x_out[2]), + .port_3(x_0_x_out[3]), + .port_4(x_0_x_out[4]), + .port_5(x_0_x_out[5]), + .port_6(x_0_x_out[6]), + .port_7(x_0_x_out[7]), + .port_8(x_0_x_out[8]), + .port_9(x_0_x_out[9]), + .port_10(x_1_x_out[0]), + .port_11(x_1_x_out[1]), + .port_12(x_1_x_out[2]), + .port_13(x_1_x_out[3]), + .port_14(x_1_x_out[4]), + .port_15(x_1_x_out[5]), + .port_16(x_1_x_out[6]), + .port_17(x_1_x_out[7]), + .port_18(x_1_x_out[8]), + .port_19(x_1_x_out[9]), + .port_20(x_2_x_out[0]), + .port_21(x_2_x_out[1]), + .port_22(x_2_x_out[2]), + .port_23(x_2_x_out[3]), + .port_24(x_2_x_out[4]), + .port_25(x_2_x_out[5]), + .port_26(x_2_x_out[6]), + .port_27(x_2_x_out[7]), + .port_28(x_2_x_out[8]), + .port_29(x_2_x_out[9]), + .port_30(x_3_x_out[0]), + .port_31(x_3_x_out[1]), + .port_32(x_3_x_out[2]), + .port_33(x_3_x_out[3]), + .port_34(x_3_x_out[4]), + .port_35(x_3_x_out[5]), + .port_36(x_3_x_out[6]), + .port_37(x_3_x_out[7]), + .port_38(x_3_x_out[8]), + .port_39(x_3_x_out[9]), + .port_40(x_4_x_out[0]), + .port_41(x_4_x_out[1]), + .port_42(x_4_x_out[2]), + .port_43(x_4_x_out[3]), + .port_44(x_4_x_out[4]), + .port_45(x_4_x_out[5]), + .port_46(x_4_x_out[6]), + .port_47(x_4_x_out[7]), + .port_48(x_4_x_out[8]), + .port_49(x_4_x_out[9]), + .port_50(x_5_x_out[0]), + .port_51(x_5_x_out[1]), + .port_52(x_5_x_out[2]), + .port_53(x_5_x_out[3]), + .port_54(x_5_x_out[4]), + .port_55(x_5_x_out[5]), + .port_56(x_5_x_out[6]), + .port_57(x_5_x_out[7]), + .port_58(x_5_x_out[8]), + .port_59(x_5_x_out[9]), + .port_60(x_6_x_out[0]), + .port_61(x_6_x_out[1]), + .port_62(x_6_x_out[2]), + .port_63(x_6_x_out[3]), + .port_64(x_6_x_out[4]), + .port_65(x_6_x_out[5]), + .port_66(x_6_x_out[6]), + .port_67(x_6_x_out[7]), + .port_68(x_6_x_out[8]), + .port_69(x_6_x_out[9]), + .port_70(x_7_x_out[0]), + .port_71(x_7_x_out[1]), + .port_72(x_7_x_out[2]), + .port_73(x_7_x_out[3]), + .port_74(x_7_x_out[4]), + .port_75(x_7_x_out[5]), + .port_76(x_7_x_out[6]), + .port_77(x_7_x_out[7]), + .port_78(x_7_x_out[8]), + .port_79(x_7_x_out[9]), + .port_80(x_8_x_out[0]), + .port_81(x_8_x_out[1]), + .port_82(x_8_x_out[2]), + .port_83(x_8_x_out[3]), + .port_84(x_8_x_out[4]), + .port_85(x_8_x_out[5]), + .port_86(x_8_x_out[6]), + .port_87(x_8_x_out[7]), + .port_88(x_8_x_out[8]), + .port_89(x_8_x_out[9]), + .port_90(x_9_x_out[0]), + .port_91(x_9_x_out[1]), + .port_92(x_9_x_out[2]), + .port_93(x_9_x_out[3]), + .port_94(x_9_x_out[4]), + .port_95(x_9_x_out[5]), + .port_96(x_9_x_out[6]), + .port_97(x_9_x_out[7]), + .port_98(x_9_x_out[8]), + .port_99(x_9_x_out[9]), .port_100(CLK) ); `endif +wire [9:0] x_0_x_in; +assign x_0_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_0_x ( + .in(x_0_x_in), + .out(x_0_x_out) +); +wire [9:0] x_1_x_in; +assign x_1_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_1_x ( + .in(x_1_x_in), + .out(x_1_x_out) +); +wire [9:0] x_2_x_in; +assign x_2_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_2_x ( + .in(x_2_x_in), + .out(x_2_x_out) +); +wire [9:0] x_3_x_in; +assign x_3_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_3_x ( + .in(x_3_x_in), + .out(x_3_x_out) +); +wire [9:0] x_4_x_in; +assign x_4_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_4_x ( + .in(x_4_x_in), + .out(x_4_x_out) +); +wire [9:0] x_5_x_in; +assign x_5_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_5_x ( + .in(x_5_x_in), + .out(x_5_x_out) +); +wire [9:0] x_6_x_in; +assign x_6_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_6_x ( + .in(x_6_x_in), + .out(x_6_x_out) +); +wire [9:0] x_7_x_in; +assign x_7_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_7_x ( + .in(x_7_x_in), + .out(x_7_x_out) +); +wire [9:0] x_8_x_in; +assign x_8_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_8_x ( + .in(x_8_x_in), + .out(x_8_x_out) +); +wire [9:0] x_9_x_in; +assign x_9_x_in = {I,I,I,I,I,I,I,I,I,I}; +coreir_wire #( + .width(10) +) x_9_x ( + .in(x_9_x_in), + .out(x_9_x_out) +); endmodule diff --git a/tests/gold/test_compile_guard_assert.json b/tests/gold/test_compile_guard_assert.json index 4f81daa88..3e8ac0973 100644 --- a/tests/gold/test_compile_guard_assert.json +++ b/tests/gold/test_compile_guard_assert.json @@ -12,9 +12,6 @@ "ASSERT_ON_compile_guard_inline_verilog_inst_0":{ "modref":"global.ASSERT_ON_compile_guard_inline_verilog_0" }, - "Register_inst0":{ - "modref":"global.Register_unq1" - }, "_FAULT_ASSERT_WIRE_0":{ "modref":"corebit.wire" }, @@ -33,6 +30,9 @@ "genargs":{"width":["Int",4]}, "modargs":{"value":[["BitVector",4],"4'h3"]} }, + "count":{ + "modref":"global.Register_unq1" + }, "magma_Bit_not_inst0":{ "modref":"corebit.not" }, @@ -54,15 +54,15 @@ }, "connections":[ ["_FAULT_ASSERT_WIRE_0.out","ASSERT_ON_compile_guard_inline_verilog_inst_0.__magma_inline_value_0"], - ["self.port_0","Register_inst0.CE"], - ["self.port_1","Register_inst0.CLK"], - ["magma_UInt_2_add_inst0.out","Register_inst0.I"], - ["magma_UInt_2_add_inst0.in0","Register_inst0.O"], - ["magma_UInt_2_eq_inst0.in0","Register_inst0.O"], ["magma_Bit_or_inst0.out","_FAULT_ASSERT_WIRE_0.in"], ["magma_UInt_2_add_inst0.in1","const_1_2.out"], ["magma_UInt_2_eq_inst0.in1","const_3_2.out"], ["magma_Bits_4_eq_inst0.in1","const_3_4.out"], + ["self.port_0","count.CE"], + ["self.port_1","count.CLK"], + ["magma_UInt_2_add_inst0.out","count.I"], + ["magma_UInt_2_add_inst0.in0","count.O"], + ["magma_UInt_2_eq_inst0.in0","count.O"], ["magma_UInt_2_eq_inst0.out","magma_Bit_not_inst0.in"], ["magma_Bit_or_inst0.in0","magma_Bit_not_inst0.out"], ["magma_Bits_4_eq_inst0.out","magma_Bit_or_inst0.in1"], diff --git a/tests/gold/test_compile_guard_drive_output.json b/tests/gold/test_compile_guard_drive_output.json index bce3fec61..726e0c088 100644 --- a/tests/gold/test_compile_guard_drive_output.json +++ b/tests/gold/test_compile_guard_drive_output.json @@ -4,9 +4,9 @@ "modules":{ "CompileGuardCircuit_1":{ "type":["Record",[ + ["CLK",["Named","coreir.clkIn"]], ["port_0","Bit"], - ["port_1",["Named","coreir.clkIn"]], - ["port_2","BitIn"] + ["port_1","BitIn"] ]], "instances":{ "Register_inst0":{ @@ -21,11 +21,11 @@ } }, "connections":[ - ["self.port_1","Register_inst0.CLK"], + ["self.CLK","Register_inst0.CLK"], ["magma_Bit_xor_inst0.out","Register_inst0.I"], ["self.port_0","Register_inst0.O"], ["magma_Bit_xor_inst0.in1","bit_const_1_None.out"], - ["self.port_2","magma_Bit_xor_inst0.in0"] + ["self.port_1","magma_Bit_xor_inst0.in0"] ] }, "Register":{ @@ -60,9 +60,9 @@ } }, "connections":[ + ["self.CLK","CompileGuardCircuit_1.CLK"], ["self.O","CompileGuardCircuit_1.port_0"], - ["self.CLK","CompileGuardCircuit_1.port_1"], - ["self.I","CompileGuardCircuit_1.port_2"] + ["self.I","CompileGuardCircuit_1.port_1"] ] } } diff --git a/tests/gold/test_when_memory_Bits8.mlir b/tests/gold/test_when_memory_Bits8.mlir index 4fa715ba6..3d263e84b 100644 --- a/tests/gold/test_when_memory_Bits8.mlir +++ b/tests/gold/test_when_memory_Bits8.mlir @@ -13,7 +13,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } hw.module @test_when_memory_Bits8(%data0: i8, %addr0: i5, %en0: i1, %data1: i8, %addr1: i5, %en1: i1, %CLK: i1) -> (out: i8) { %0 = hw.constant 1 : i1 - %5 = hw.instance "Memory_inst0" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA: %3: i8, WE: %4: i1) -> (RDATA: i8) + %5 = hw.instance "mem" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA: %3: i8, WE: %4: i1) -> (RDATA: i8) %6 = hw.constant 255 : i8 %7 = hw.constant 0 : i5 %8 = hw.constant 0 : i8 diff --git a/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir b/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir index f4a09f84a..1dceb7140 100644 --- a/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir +++ b/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir @@ -30,7 +30,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } hw.module @test_when_memory_Tuplex_Bit_y_Bits7(%data0_x: i1, %data0_y: i7, %addr0: i5, %en0: i1, %data1_x: i1, %data1_y: i7, %addr1: i5, %en1: i1, %CLK: i1) -> (out_x: i1, out_y: i7) { %0 = hw.constant 1 : i1 - %6, %7 = hw.instance "Memory_inst0" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA_x: %3: i1, WDATA_y: %4: i7, WE: %5: i1) -> (RDATA_x: i1, RDATA_y: i7) + %6, %7 = hw.instance "mem" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA_x: %3: i1, WDATA_y: %4: i7, WE: %5: i1) -> (RDATA_x: i1, RDATA_y: i7) %8 = hw.constant 127 : i7 %9 = hw.constant 0 : i5 %10 = hw.constant 0 : i1 diff --git a/tests/gold/test_when_non_port.mlir b/tests/gold/test_when_non_port.mlir index 9ceb6d9dc..7b126c6e2 100644 --- a/tests/gold/test_when_non_port.mlir +++ b/tests/gold/test_when_non_port.mlir @@ -11,6 +11,9 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %3, %1 : i1 } } - hw.output %2 : i1 + %5 = sv.wire sym @test_non_port.x {name="x"} : !hw.inout + sv.assign %5, %2 : i1 + %4 = sv.read_inout %5 : !hw.inout + hw.output %4 : i1 } } diff --git a/tests/gold/test_when_recursive_non_port.mlir b/tests/gold/test_when_recursive_non_port.mlir index f5e6cc8df..ccbd6b058 100644 --- a/tests/gold/test_when_recursive_non_port.mlir +++ b/tests/gold/test_when_recursive_non_port.mlir @@ -2,19 +2,22 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @test_recursive_non_port(%I: i2, %S: i1) -> (O0: i1, O1: i1) { %0 = comb.extract %I from 0 : (i2) -> i1 %1 = comb.extract %I from 1 : (i2) -> i1 - %4 = sv.reg : !hw.inout - %2 = sv.read_inout %4 : !hw.inout %5 = sv.reg : !hw.inout %3 = sv.read_inout %5 : !hw.inout + %6 = sv.reg : !hw.inout + %4 = sv.read_inout %6 : !hw.inout sv.alwayscomb { sv.if %S { - sv.bpassign %4, %0 : i1 - sv.bpassign %5, %2 : i1 + sv.bpassign %5, %0 : i1 + sv.bpassign %6, %2 : i1 } else { - sv.bpassign %4, %1 : i1 - sv.bpassign %5, %2 : i1 + sv.bpassign %5, %1 : i1 + sv.bpassign %6, %2 : i1 } } - hw.output %2, %3 : i1, i1 + %7 = sv.wire sym @test_recursive_non_port.x {name="x"} : !hw.inout + sv.assign %7, %3 : i1 + %2 = sv.read_inout %7 : !hw.inout + hw.output %2, %4 : i1, i1 } } diff --git a/tests/gold/test_when_reg_ce.mlir b/tests/gold/test_when_reg_ce.mlir index 32cc3212a..d247857f8 100644 --- a/tests/gold/test_when_reg_ce.mlir +++ b/tests/gold/test_when_reg_ce.mlir @@ -14,7 +14,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %6, %0 : i1 } } - %7 = sv.reg {name = "Register_inst0"} : !hw.inout + %7 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %4 { sv.passign %7, %3 : i8 diff --git a/tests/gold/test_when_reg_ce_already_wired.mlir b/tests/gold/test_when_reg_ce_already_wired.mlir index 398aa3054..1e1723cd6 100644 --- a/tests/gold/test_when_reg_ce_already_wired.mlir +++ b/tests/gold/test_when_reg_ce_already_wired.mlir @@ -8,7 +8,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i8 } } - %3 = sv.reg {name = "Register_inst0"} : !hw.inout + %3 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %x { sv.passign %3, %1 : i8 diff --git a/tests/gold/test_when_reg_ce_explicit_wire.mlir b/tests/gold/test_when_reg_ce_explicit_wire.mlir index 1736e9a3b..1e104d48e 100644 --- a/tests/gold/test_when_reg_ce_explicit_wire.mlir +++ b/tests/gold/test_when_reg_ce_explicit_wire.mlir @@ -13,7 +13,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %5, %x : i1 } } - %6 = sv.reg {name = "Register_inst0"} : !hw.inout + %6 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %3 { sv.passign %6, %2 : i8 diff --git a/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir b/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir index ce52689b1..291193684 100644 --- a/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir +++ b/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir @@ -20,7 +20,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } %8 = hw.constant -1 : i1 %7 = comb.xor %8, %y : i1 - %9 = sv.reg {name = "Register_inst0"} : !hw.inout + %9 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %7 { sv.passign %9, %5 : i8 diff --git a/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir b/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir index 78fcc92c2..82761c5e3 100644 --- a/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir +++ b/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir @@ -13,7 +13,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %5, %x : i1 } } - %6 = sv.reg {name = "Register_inst0"} : !hw.inout + %6 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %3 { sv.passign %6, %2 : i8 diff --git a/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir b/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir index 1b5863794..2bf19a1a7 100644 --- a/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir +++ b/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir @@ -29,7 +29,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %13, %9 : i1 } } - %14 = sv.reg {name = "Register_inst0"} : !hw.inout + %14 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %11 { sv.passign %14, %10 : i8 diff --git a/tests/gold/test_when_reg_ce_multiple.mlir b/tests/gold/test_when_reg_ce_multiple.mlir index 4d956e703..bbe9e3f80 100644 --- a/tests/gold/test_when_reg_ce_multiple.mlir +++ b/tests/gold/test_when_reg_ce_multiple.mlir @@ -23,7 +23,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } } } - %11 = sv.reg {name = "Register_inst0"} : !hw.inout + %11 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %8 { sv.passign %11, %7 : i8 diff --git a/tests/gold/test_when_register_default.mlir b/tests/gold/test_when_register_default.mlir index e0174761a..6d4cf419d 100644 --- a/tests/gold/test_when_register_default.mlir +++ b/tests/gold/test_when_register_default.mlir @@ -8,7 +8,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i1 } } - %3 = sv.reg {name = "Register_inst0"} : !hw.inout + %3 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %3, %1 : i1 } diff --git a/tests/gold/test_when_register_no_default.mlir b/tests/gold/test_when_register_no_default.mlir index 6418454b3..f034b2dba 100644 --- a/tests/gold/test_when_register_no_default.mlir +++ b/tests/gold/test_when_register_no_default.mlir @@ -11,7 +11,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %3, %0 : i1 } } - %5 = sv.reg {name = "Register_inst0"} : !hw.inout + %5 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %5, %2 : i1 } diff --git a/tests/gold/test_when_spurious_assign.mlir b/tests/gold/test_when_spurious_assign.mlir index 27b1b4a80..5bd85186f 100644 --- a/tests/gold/test_when_spurious_assign.mlir +++ b/tests/gold/test_when_spurious_assign.mlir @@ -35,7 +35,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %15, %11 : i1 } } - %20 = sv.reg {name = "Register_inst0"} : !hw.inout + %20 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %0 { sv.passign %20, %x : i8 @@ -46,7 +46,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %20, %21 : i8 } %17 = sv.read_inout %20 : !hw.inout - %22 = sv.reg {name = "Register_inst0"} : !hw.inout + %22 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %0 { sv.passign %22, %6 : i8 @@ -57,7 +57,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %22, %23 : i8 } %18 = sv.read_inout %22 : !hw.inout - %24 = sv.reg {name = "Register_inst0"} : !hw.inout + %24 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %0 { sv.passign %24, %13 : i1 diff --git a/tests/gold/test_when_user_reg.mlir b/tests/gold/test_when_user_reg.mlir index 80544c0c4..b55833270 100644 --- a/tests/gold/test_when_user_reg.mlir +++ b/tests/gold/test_when_user_reg.mlir @@ -9,7 +9,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i8 } } - %0 = hw.instance "Register_inst0" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) + %0 = hw.instance "x" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) hw.output %0 : i8 } } diff --git a/tests/gold/test_when_user_reg_enable.mlir b/tests/gold/test_when_user_reg_enable.mlir index 7e3537e53..3d08213cc 100644 --- a/tests/gold/test_when_user_reg_enable.mlir +++ b/tests/gold/test_when_user_reg_enable.mlir @@ -84,7 +84,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } } %49 = comb.concat %38, %37, %36, %35, %34, %33, %32, %31 : i1, i1, i1, i1, i1, i1, i1, i1 - %21 = hw.instance "Register_inst0" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) + %21 = hw.instance "x" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) hw.output %21 : i8 } } diff --git a/tests/gold/uniquification_key_error_mux.json b/tests/gold/uniquification_key_error_mux.json index 99cf534b1..3379b5869 100644 --- a/tests/gold/uniquification_key_error_mux.json +++ b/tests/gold/uniquification_key_error_mux.json @@ -10,16 +10,16 @@ ["O",["Array",6,"Bit"]] ]], "instances":{ - "coreir_commonlib_mux2x6_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",6]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x6_inst0.in.data.0"], - ["self.I1","coreir_commonlib_mux2x6_inst0.in.data.1"], - ["self.S","coreir_commonlib_mux2x6_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x6_inst0.out"] + ["self.I0","mux.in.data.0"], + ["self.I1","mux.in.data.1"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out"] ] }, "MuxWithDefaultWrapper_2_6_19_0":{ diff --git a/tests/gold/uniquify_equal.json b/tests/gold/uniquify_equal.json index 125248f02..f9d39ae25 100644 --- a/tests/gold/uniquify_equal.json +++ b/tests/gold/uniquify_equal.json @@ -20,14 +20,14 @@ "foo_inst0":{ "modref":"global.foo" }, - "foo_inst1":{ + "inst":{ "modref":"global.foo" } }, "connections":[ ["self.I","foo_inst0.I"], - ["foo_inst1.I","foo_inst0.O"], - ["self.O","foo_inst1.O"] + ["inst.I","foo_inst0.O"], + ["self.O","inst.O"] ] } } diff --git a/tests/gold/uniquify_multiple_rename.json b/tests/gold/uniquify_multiple_rename.json index cae66fb58..96e152168 100644 --- a/tests/gold/uniquify_multiple_rename.json +++ b/tests/gold/uniquify_multiple_rename.json @@ -30,23 +30,23 @@ ["O2",["Array",3,"Bit"]] ]], "instances":{ - "Foo_inst0":{ + "foo0":{ "modref":"global.Foo" }, - "Foo_inst1":{ + "foo1":{ "modref":"global.Foo_unq1" }, - "Foo_inst2":{ + "foo2":{ "modref":"global.Foo_unq1" } }, "connections":[ - ["self.I0","Foo_inst0.I"], - ["self.O0","Foo_inst0.O"], - ["self.I1","Foo_inst1.I"], - ["self.O1","Foo_inst1.O"], - ["self.I2","Foo_inst2.I"], - ["self.O2","Foo_inst2.O"] + ["self.I0","foo0.I"], + ["self.O0","foo0.O"], + ["self.I1","foo1.I"], + ["self.O1","foo1.O"], + ["self.I2","foo2.I"], + ["self.O2","foo2.O"] ] } } diff --git a/tests/gold/uniquify_unequal.json b/tests/gold/uniquify_unequal.json index 6211b15bf..2c6aafe97 100644 --- a/tests/gold/uniquify_unequal.json +++ b/tests/gold/uniquify_unequal.json @@ -26,18 +26,18 @@ ["O","Bit"] ]], "instances":{ - "foo_inst0":{ - "modref":"global.foo" - }, - "foo_inst1":{ + "bar_inst":{ "modref":"global.foo_unq1" + }, + "foo_inst":{ + "modref":"global.foo" } }, "connections":[ - ["self.I","foo_inst0.I"], - ["foo_inst1.I.0","foo_inst0.O"], - ["foo_inst1.I.1","foo_inst0.O"], - ["self.O","foo_inst1.O.0"] + ["foo_inst.O","bar_inst.I.0"], + ["foo_inst.O","bar_inst.I.1"], + ["self.O","bar_inst.O.0"], + ["self.I","foo_inst.I"] ] } } diff --git a/tests/test_backend/test_mlir/examples.py b/tests/test_backend/test_mlir/examples.py index 4e9acdab8..398f6fe6c 100644 --- a/tests/test_backend/test_mlir/examples.py +++ b/tests/test_backend/test_mlir/examples.py @@ -442,7 +442,7 @@ class xmr_bind_asserts(m.Circuit): ProcessInlineVerilogPass(xmr_bind_asserts).run() -xmr_bind.bind(xmr_bind_asserts, xmr_bind.inst.xmr_bind_grandchild_inst0.y) +xmr_bind.bind(xmr_bind_asserts, xmr_bind.inst.inst.y) class simple_compile_guard(m.Circuit): diff --git a/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir b/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir index 6174c86fd..3cbcd79f6 100644 --- a/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir +++ b/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir @@ -3,7 +3,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %a_x : i8 } hw.module @complex_mixed_direction_ports2(%a_x: i8) -> (a_y: i8) { - %0 = hw.instance "simple_mixed_direction_ports_inst0" @simple_mixed_direction_ports(a_x: %a_x: i8) -> (a_y: i8) + %0 = hw.instance "simple" @simple_mixed_direction_ports(a_x: %a_x: i8) -> (a_y: i8) hw.output %0 : i8 } } diff --git a/tests/test_backend/test_mlir/golds/counter.mlir b/tests/test_backend/test_mlir/golds/counter.mlir index 0c5ad2480..8c430ad5b 100644 --- a/tests/test_backend/test_mlir/golds/counter.mlir +++ b/tests/test_backend/test_mlir/golds/counter.mlir @@ -2,7 +2,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @counter(%CLK: i1) -> (y: i16) { %0 = hw.constant 1 : i16 %2 = comb.add %1, %0 : i16 - %3 = sv.reg {name = "Register_inst0"} : !hw.inout + %3 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %3, %2 : i16 } diff --git a/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir b/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir index 9b9aedb61..5a7ccf9f8 100644 --- a/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir +++ b/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir @@ -12,7 +12,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %0 : i12 } hw.module @simple_memory_wrapper(%RADDR: i7, %CLK: i1, %WADDR: i7, %WDATA: i12, %WE: i1) -> (RDATA: i12) { - %0 = hw.instance "Memory_inst0" @Memory(RADDR: %RADDR: i7, CLK: %CLK: i1, WADDR: %WADDR: i7, WDATA: %WDATA: i12, WE: %WE: i1) -> (RDATA: i12) + %0 = hw.instance "mem" @Memory(RADDR: %RADDR: i7, CLK: %CLK: i1, WADDR: %WADDR: i7, WDATA: %WDATA: i12, WE: %WE: i1) -> (RDATA: i12) hw.output %0 : i12 } } diff --git a/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir b/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir index 3155b0c67..fc71bd207 100644 --- a/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir +++ b/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir @@ -3,7 +3,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %I : i1 } hw.module @simple_module_params_instance(%I: i1) -> (O: i1) { - %0 = hw.instance "simple_module_params_inst0" @simple_module_params(I: %I: i1) -> (O: i1) + %0 = hw.instance "inst" @simple_module_params(I: %I: i1) -> (O: i1) hw.output %0 : i1 } } diff --git a/tests/test_backend/test_mlir/golds/simple_redefinition.mlir b/tests/test_backend/test_mlir/golds/simple_redefinition.mlir index ca49c5e7c..33497e348 100644 --- a/tests/test_backend/test_mlir/golds/simple_redefinition.mlir +++ b/tests/test_backend/test_mlir/golds/simple_redefinition.mlir @@ -3,8 +3,8 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %a : i1 } hw.module @simple_redefinition(%a: i1) -> (y: i1) { - %0 = hw.instance "simple_redefinition_module_inst0" @simple_redefinition_module(a: %a: i1) -> (y: i1) - %1 = hw.instance "simple_redefinition_module_inst1" @simple_redefinition_module(a: %0: i1) -> (y: i1) + %0 = hw.instance "i0" @simple_redefinition_module(a: %a: i1) -> (y: i1) + %1 = hw.instance "i1" @simple_redefinition_module(a: %0: i1) -> (y: i1) hw.output %1 : i1 } } diff --git a/tests/test_backend/test_mlir/golds/xmr_bind.mlir b/tests/test_backend/test_mlir/golds/xmr_bind.mlir index d14f165af..dac6d7faa 100644 --- a/tests/test_backend/test_mlir/golds/xmr_bind.mlir +++ b/tests/test_backend/test_mlir/golds/xmr_bind.mlir @@ -3,7 +3,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %a : i16 } hw.module @xmr_bind_child(%a: i16) -> (y: i16) { - %0 = hw.instance "xmr_bind_grandchild_inst0" @xmr_bind_grandchild(a: %a: i16) -> (y: i16) + %0 = hw.instance "inst" @xmr_bind_grandchild(a: %a: i16) -> (y: i16) hw.output %0 : i16 } hw.module @xmr_bind_asserts(%a: i16, %y: i16, %other: i16) -> () { @@ -13,8 +13,8 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.verbatim "assert property ({{0}} == 0);" (%0) : i16 } hw.module @xmr_bind(%a: i16) -> (y: i16) { - %0 = hw.instance "xmr_bind_child_inst0" @xmr_bind_child(a: %a: i16) -> (y: i16) - %1 = sv.xmr "xmr_bind_child_inst0", "xmr_bind_grandchild_inst0", "y" : !hw.inout + %0 = hw.instance "inst" @xmr_bind_child(a: %a: i16) -> (y: i16) + %1 = sv.xmr "inst", "inst", "y" : !hw.inout %2 = sv.read_inout %1 : !hw.inout hw.instance "xmr_bind_asserts_inst" sym @xmr_bind.xmr_bind_asserts_inst @xmr_bind_asserts(a: %a: i16, y: %0: i16, other: %2: i16) -> () {doNotPrint = 1} hw.output %0 : i16 diff --git a/tests/test_circuit/gold/test_add8cin.json b/tests/test_circuit/gold/test_add8cin.json index f8626cd7b..d4f324384 100644 --- a/tests/test_circuit/gold/test_add8cin.json +++ b/tests/test_circuit/gold/test_add8cin.json @@ -46,15 +46,15 @@ ["O",["Array",8,"Bit"]] ]], "instances":{ - "Add8_cin_inst0":{ + "adder":{ "modref":"global.Add8_cin" } }, "connections":[ - ["self.CIN","Add8_cin_inst0.CIN"], - ["self.I0","Add8_cin_inst0.I0"], - ["self.I1","Add8_cin_inst0.I1"], - ["self.O","Add8_cin_inst0.O"] + ["self.CIN","adder.CIN"], + ["self.I0","adder.I0"], + ["self.I1","adder.I1"], + ["self.O","adder.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json index 48b134285..984717dab 100644 --- a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json +++ b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json @@ -16,14 +16,19 @@ ["O",["Array",2,"Bit"]] ]], "instances":{ - "And2_inst0":{ + "and2":{ "modref":"global.And2" + }, + "tmp":{ + "genref":"coreir.wire", + "genargs":{"width":["Int",2]} } }, "connections":[ - ["self.I0","And2_inst0.I0"], - ["self.I1","And2_inst0.I1"], - ["self.O","And2_inst0.O"] + ["self.I0","and2.I0"], + ["self.I1","and2.I1"], + ["tmp.in","and2.O"], + ["tmp.out","self.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v index 058f17080..8465af807 100644 --- a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v +++ b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v @@ -1,6 +1,6 @@ module main (input [1:0] I0, input [1:0] I1, output [1:0] O); -wire [1:0] And2_inst0_O; -And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire [1:0] and2_O; +And2 and2 (.I0(I0), .I1(I1), .O(and2_O)); +assign O = and2_O; endmodule diff --git a/tests/test_circuit/gold/test_anon_value_Bit.json b/tests/test_circuit/gold/test_anon_value_Bit.json index 1afbaed4d..44e36f2f5 100644 --- a/tests/test_circuit/gold/test_anon_value_Bit.json +++ b/tests/test_circuit/gold/test_anon_value_Bit.json @@ -16,14 +16,18 @@ ["O","Bit"] ]], "instances":{ - "And2_inst0":{ + "and2":{ "modref":"global.And2" + }, + "tmp":{ + "modref":"corebit.wire" } }, "connections":[ - ["self.I0","And2_inst0.I0"], - ["self.I1","And2_inst0.I1"], - ["self.O","And2_inst0.O"] + ["self.I0","and2.I0"], + ["self.I1","and2.I1"], + ["tmp.in","and2.O"], + ["tmp.out","self.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Bit.v b/tests/test_circuit/gold/test_anon_value_Bit.v index f0fc76a4f..d7b3e2500 100644 --- a/tests/test_circuit/gold/test_anon_value_Bit.v +++ b/tests/test_circuit/gold/test_anon_value_Bit.v @@ -1,6 +1,6 @@ module main (input I0, input I1, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire and2_O; +And2 and2 (.I0(I0), .I1(I1), .O(and2_O)); +assign O = and2_O; endmodule diff --git a/tests/test_circuit/gold/test_anon_value_Bits(2).json b/tests/test_circuit/gold/test_anon_value_Bits(2).json index 48b134285..984717dab 100644 --- a/tests/test_circuit/gold/test_anon_value_Bits(2).json +++ b/tests/test_circuit/gold/test_anon_value_Bits(2).json @@ -16,14 +16,19 @@ ["O",["Array",2,"Bit"]] ]], "instances":{ - "And2_inst0":{ + "and2":{ "modref":"global.And2" + }, + "tmp":{ + "genref":"coreir.wire", + "genargs":{"width":["Int",2]} } }, "connections":[ - ["self.I0","And2_inst0.I0"], - ["self.I1","And2_inst0.I1"], - ["self.O","And2_inst0.O"] + ["self.I0","and2.I0"], + ["self.I1","and2.I1"], + ["tmp.in","and2.O"], + ["tmp.out","self.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Bits(2).v b/tests/test_circuit/gold/test_anon_value_Bits(2).v index 058f17080..8465af807 100644 --- a/tests/test_circuit/gold/test_anon_value_Bits(2).v +++ b/tests/test_circuit/gold/test_anon_value_Bits(2).v @@ -1,6 +1,6 @@ module main (input [1:0] I0, input [1:0] I1, output [1:0] O); -wire [1:0] And2_inst0_O; -And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire [1:0] and2_O; +And2 and2 (.I0(I0), .I1(I1), .O(and2_O)); +assign O = and2_O; endmodule diff --git a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json index fe742125f..ed95d6b6a 100644 --- a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json +++ b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json @@ -16,14 +16,21 @@ ["O",["Record",[["x","Bit"],["y","Bit"]]]] ]], "instances":{ - "And2_inst0":{ + "and2":{ "modref":"global.And2" + }, + "tmp":{ + "genref":"coreir.wire", + "genargs":{"width":["Int",2]} } }, "connections":[ - ["self.I0","And2_inst0.I0"], - ["self.I1","And2_inst0.I1"], - ["self.O","And2_inst0.O"] + ["self.I0","and2.I0"], + ["self.I1","and2.I1"], + ["tmp.in.0","and2.O.x"], + ["tmp.in.1","and2.O.y"], + ["tmp.out.0","self.O.x"], + ["tmp.out.1","self.O.y"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v index f18f6c484..ebc227109 100644 --- a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v +++ b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v @@ -1,12 +1,12 @@ module main (input I0_x, input I0_y, input I1_x, input I1_y, output O_x, output O_y); -wire And2_inst0_I0_x; -wire And2_inst0_I0_y; -wire And2_inst0_I1_x; -wire And2_inst0_I1_y; -wire And2_inst0_O_x; -wire And2_inst0_O_y; -And2 And2_inst0 (.I0_x(I0_x), .I0_y(I0_y), .I1_x(I1_x), .I1_y(I1_y), .O_x(And2_inst0_O_x), .O_y(And2_inst0_O_y)); -assign O_x = And2_inst0_O_x; -assign O_y = And2_inst0_O_y; +wire and2_I0_x; +wire and2_I0_y; +wire and2_I1_x; +wire and2_I1_y; +wire and2_O_x; +wire and2_O_y; +And2 and2 (.I0_x(I0_x), .I0_y(I0_y), .I1_x(I1_x), .I1_y(I1_y), .O_x(and2_O_x), .O_y(and2_O_y)); +assign O_x = and2_O_x; +assign O_y = and2_O_y; endmodule diff --git a/tests/test_circuit/gold/test_for_loop_def.json b/tests/test_circuit/gold/test_for_loop_def.json index 23454ddd0..510b3618e 100644 --- a/tests/test_circuit/gold/test_for_loop_def.json +++ b/tests/test_circuit/gold/test_for_loop_def.json @@ -27,7 +27,7 @@ "modref":"global.And2", "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"} }, - "and2_3":{ + "and2_prev":{ "modref":"global.And2", "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"} } @@ -39,9 +39,9 @@ ["self.I.1","and2_1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], ["and2_2.I0","and2_1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}], ["self.I.1","and2_2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], - ["and2_3.I0","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}], - ["self.I.1","and2_3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], - ["self.O","and2_3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"70"}] + ["and2_prev.I0","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}], + ["self.I.1","and2_prev.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], + ["self.O","and2_prev.O",{"filename":"tests/test_circuit/test_define.py","lineno":"70"}] ], "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"} } diff --git a/tests/test_circuit/gold/test_for_loop_def.v b/tests/test_circuit/gold/test_for_loop_def.v index 8ad60292b..da18b2d56 100644 --- a/tests/test_circuit/gold/test_for_loop_def.v +++ b/tests/test_circuit/gold/test_for_loop_def.v @@ -3,7 +3,7 @@ module main (input [1:0] I, output O); wire and2_0_O; wire and2_1_O; wire and2_2_O; -wire and2_3_O; +wire and2_prev_O; // Instanced at tests/test_circuit/test_define.py:61 // Argument I0(I[0]) wired at tests/test_circuit/test_define.py:63 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:64 @@ -22,9 +22,9 @@ And2 and2_2 (.I0(and2_1_O), .I1(I[1]), .O(and2_2_O)); // Instanced at tests/test_circuit/test_define.py:61 // Argument I0(and2_2_O) wired at tests/test_circuit/test_define.py:66 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:67 -// Argument O(and2_3_O) wired at tests/test_circuit/test_define.py:70 -And2 and2_3 (.I0(and2_2_O), .I1(I[1]), .O(and2_3_O)); +// Argument O(and2_prev_O) wired at tests/test_circuit/test_define.py:70 +And2 and2_prev (.I0(and2_2_O), .I1(I[1]), .O(and2_prev_O)); // Wired at tests/test_circuit/test_define.py:70 -assign O = and2_3_O; +assign O = and2_prev_O; endmodule diff --git a/tests/test_circuit/gold/test_ignore_undriven_coreir.json b/tests/test_circuit/gold/test_ignore_undriven_coreir.json index ec762b740..a8557a5b9 100644 --- a/tests/test_circuit/gold/test_ignore_undriven_coreir.json +++ b/tests/test_circuit/gold/test_ignore_undriven_coreir.json @@ -37,26 +37,26 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "Foo_inst0":{ - "modref":"global.Foo" - }, "corebit_term_inst0":{ "modref":"corebit.term" }, "corebit_undriven_inst0":{ "modref":"corebit.undriven" }, + "foo":{ + "modref":"global.Foo" + }, "magma_Bits_2_eq_inst0":{ "genref":"coreir.eq", "genargs":{"width":["Int",2]} } }, "connections":[ - ["self.CLK","Foo_inst0.CLK"], - ["magma_Bits_2_eq_inst0.out","Foo_inst0.I0"], - ["self.O0","Foo_inst0.O0"], - ["corebit_term_inst0.in","Foo_inst0.O1"], + ["foo.O1","corebit_term_inst0.in"], ["self.O1","corebit_undriven_inst0.out"], + ["self.CLK","foo.CLK"], + ["magma_Bits_2_eq_inst0.out","foo.I0"], + ["self.O0","foo.O0"], ["self.I0","magma_Bits_2_eq_inst0.in0"], ["self.I1","magma_Bits_2_eq_inst0.in1"] ] diff --git a/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v b/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v index 226f50ed9..a9107ec0a 100644 --- a/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v +++ b/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v @@ -35,20 +35,14 @@ module Main ( output O2__1, output [1:0] O3 ); -wire Foo_inst0_O1; wire corebit_undriven_inst2_out; wire corebit_undriven_inst3_out; -Foo Foo_inst0 ( - .I0(I0), - .I1(corebit_undriven_inst3_out), - .O0(O0), - .O1(Foo_inst0_O1) -); +wire foo_O1; corebit_term corebit_term_inst0 ( .in(I1) ); corebit_term corebit_term_inst1 ( - .in(Foo_inst0_O1) + .in(foo_O1) ); corebit_undriven corebit_undriven_inst0 ( .out(O1) @@ -62,6 +56,12 @@ corebit_undriven corebit_undriven_inst2 ( corebit_undriven corebit_undriven_inst3 ( .out(corebit_undriven_inst3_out) ); +Foo foo ( + .I0(I0), + .I1(corebit_undriven_inst3_out), + .O0(O0), + .O1(foo_O1) +); assign O2__0 = 1'b1; assign O3 = {corebit_undriven_inst2_out,1'b1}; endmodule diff --git a/tests/test_circuit/gold/test_unwired_output.v b/tests/test_circuit/gold/test_unwired_output.v index 510420101..51961ec48 100644 --- a/tests/test_circuit/gold/test_unwired_output.v +++ b/tests/test_circuit/gold/test_unwired_output.v @@ -1,5 +1,5 @@ module main (input [1:0] I, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I1(I[1]), .O(And2_inst0_O)); +wire and2_O; +And2 and2 (.I1(I[1]), .O(and2_O)); endmodule diff --git a/tests/test_circuit/test_define.py b/tests/test_circuit/test_define.py index 3af6e1c0c..52ab36395 100644 --- a/tests/test_circuit/test_define.py +++ b/tests/test_circuit/test_define.py @@ -121,7 +121,7 @@ class main(m.Circuit): m.compile("build/test_unwired_output", main, "verilog") assert check_files_equal(__file__, f"build/test_unwired_output.v", f"gold/test_unwired_output.v") - assert caplog.records[-2].msg == "main.And2_inst0.I0 not connected" + assert caplog.records[-2].msg == "main.and2.I0 not connected" assert caplog.records[-1].msg == "main.O is unwired" diff --git a/tests/test_circuit/test_inspect.py b/tests/test_circuit/test_inspect.py index 6b6bc0aeb..d44110e62 100644 --- a/tests/test_circuit/test_inspect.py +++ b/tests/test_circuit/test_inspect.py @@ -62,6 +62,6 @@ class circ(m.Circuit): m.wire(io.O, anon.O) string = str(circ.anon) - assert string[:len("AnonymousCircuitInst")] == "AnonymousCircuitInst" + assert string[:len("anon")] == "anon" assert string[-len(""):] == "" - assert repr(circ.anon) == 'AnonymousCircuitType("I0", array([And2_inst0.I0, And2_inst1.I0, And2_inst2.I0]), "I1", array([And2_inst0.I1, And2_inst1.I1, And2_inst2.I1]), "O", array([And2_inst0.O, And2_inst1.O, And2_inst2.O]))' + assert repr(circ.anon) == 'anon = AnonymousCircuitType("I0", array([And2_inst0.I0, And2_inst1.I0, And2_inst2.I0]), "I1", array([And2_inst0.I1, And2_inst1.I1, And2_inst2.I1]), "O", array([And2_inst0.O, And2_inst1.O, And2_inst2.O]))' diff --git a/tests/test_circuit/test_new_style_syntax.py b/tests/test_circuit/test_new_style_syntax.py index a365e1b48..8b5c51be2 100644 --- a/tests/test_circuit/test_new_style_syntax.py +++ b/tests/test_circuit/test_new_style_syntax.py @@ -125,14 +125,14 @@ class _Foo(m.Circuit): assert has_error( caplog, - "Cannot wire _Foo.I (Out(Bit)) to _Foo._Bar_inst0.I (In(Bits[1]))") + "Cannot wire _Foo.I (Out(Bit)) to _Foo.bar.I (In(Bits[1]))") assert has_error( caplog, - "Cannot wire _Foo._Bar_inst0.O (Out(Bits[1])) to _Foo.O (In(Bit))") + "Cannot wire _Foo.bar.O (Out(Bits[1])) to _Foo.O (In(Bit))") assert has_error(caplog, "_Foo.O not driven") assert has_error(caplog, "_Foo.O: Unconnected") - assert has_error(caplog, "_Foo._Bar_inst0.I not driven") - assert has_error(caplog, "_Foo._Bar_inst0.I: Unconnected") + assert has_error(caplog, "_Foo.bar.I not driven") + assert has_error(caplog, "_Foo.bar.I: Unconnected") def test_nested_definition(): @@ -149,9 +149,9 @@ class _Bar(m.Circuit): m.wire(bar.O, io.O) assert repr(_Foo) == """_Foo = DefineCircuit("_Foo", "I", In(Bit), "O", Out(Bit)) -_Bar_inst0 = _Bar() -wire(_Foo.I, _Bar_inst0.I) -wire(_Bar_inst0.O, _Foo.O) +bar = _Bar() +wire(_Foo.I, bar.I) +wire(bar.O, _Foo.O) EndCircuit()""" assert repr(_Foo._Bar) == """_Bar = DefineCircuit("_Bar", "I", In(Bit), "O", Out(Bit)) wire(_Bar.I, _Bar.O) diff --git a/tests/test_circuit/test_reg_enable_call.py b/tests/test_circuit/test_reg_enable_call.py index 261c1a8d1..eeee955fe 100644 --- a/tests/test_circuit/test_reg_enable_call.py +++ b/tests/test_circuit/test_reg_enable_call.py @@ -13,12 +13,12 @@ class test_reg_enable_call(m.Circuit): assert repr(test_reg_enable_call) == """\ test_reg_enable_call = DefineCircuit("test_reg_enable_call", "I", In(Bits[5]), \ "O", Out(Bits[5]), "nen", In(Bit), "CLK", In(Clock)) -Register_inst0 = Register() magma_Bit_not_inst0 = magma_Bit_not() -wire(test_reg_enable_call.I, Register_inst0.I) -wire(magma_Bit_not_inst0.out, Register_inst0.en) +reg = Register() wire(test_reg_enable_call.nen, magma_Bit_not_inst0.in) -wire(Register_inst0.O, test_reg_enable_call.O) +wire(test_reg_enable_call.I, reg.I) +wire(magma_Bit_not_inst0.out, reg.en) +wire(reg.O, test_reg_enable_call.O) EndCircuit()\ """ m.compile("build/test_reg_enable_call", test_reg_enable_call) diff --git a/tests/test_compile/gold/test_header_footer.v b/tests/test_compile/gold/test_header_footer.v index 7f117b8cc..a43723204 100644 --- a/tests/test_compile/gold/test_header_footer.v +++ b/tests/test_compile/gold/test_header_footer.v @@ -9,12 +9,12 @@ module Main ( input I, output O ); -wire Foo_inst0_y; -Foo Foo_inst0 ( +wire foo_y; +Foo foo ( .x(I), - .y(Foo_inst0_y) + .y(foo_y) ); -assign O = Foo_inst0_y; +assign O = foo_y; endmodule diff --git a/tests/test_coreir/gold/linker_test0.json b/tests/test_coreir/gold/linker_test0.json index aa3946362..07e9899f7 100644 --- a/tests/test_coreir/gold/linker_test0.json +++ b/tests/test_coreir/gold/linker_test0.json @@ -9,15 +9,15 @@ ["O",["Array",16,"Bit"]] ]], "instances":{ - "commonlib_smax_width_16_inst0":{ + "smax":{ "genref":"commonlib.smax", "genargs":{"width":["Int",16]} } }, "connections":[ - ["self.I0","commonlib_smax_width_16_inst0.in0"], - ["self.I1","commonlib_smax_width_16_inst0.in1"], - ["self.O","commonlib_smax_width_16_inst0.out"] + ["smax.in0","self.I0"], + ["smax.in1","self.I1"], + ["smax.out","self.O"] ] }, "commonlib_smax_width_16":{ diff --git a/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v b/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v index c0d080b5c..14c11b649 100644 --- a/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v +++ b/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v @@ -5,13 +5,13 @@ module Main ( input clocks_clk, input clocks_rst ); -wire Foo_inst0_O; -Foo Foo_inst0 ( +wire foo_O; +Foo foo ( .I(I), - .O(Foo_inst0_O), + .O(foo_O), .clocks_clk(clocks_clk), .clocks_rst(clocks_rst) ); -assign O = Foo_inst0_O; +assign O = foo_O; endmodule diff --git a/tests/test_coreir/gold/test_multi_direction_tuple_instance.json b/tests/test_coreir/gold/test_multi_direction_tuple_instance.json index d01098506..377a53288 100644 --- a/tests/test_coreir/gold/test_multi_direction_tuple_instance.json +++ b/tests/test_coreir/gold/test_multi_direction_tuple_instance.json @@ -15,13 +15,13 @@ ["ifc",["Record",[["I","BitIn"],["O","Bit"]]]] ]], "instances":{ - "Foo_inst0":{ + "foo_inst":{ "modref":"global.Foo" } }, "connections":[ - ["self.ifc.I","Foo_inst0.ifc.I"], - ["self.ifc.O","Foo_inst0.ifc.O"] + ["self.ifc.I","foo_inst.ifc.I"], + ["self.ifc.O","foo_inst.ifc.O"] ] } } diff --git a/tests/test_coreir/gold/test_nesting.json b/tests/test_coreir/gold/test_nesting.json index 135697c48..5edf0b032 100644 --- a/tests/test_coreir/gold/test_nesting.json +++ b/tests/test_coreir/gold/test_nesting.json @@ -15,23 +15,23 @@ ["I",["Record",[["x",["Record",[["a","BitIn"],["b","BitIn"]]]],["y",["Record",[["a","Bit"],["b","Bit"]]]],["z",["Record",[["a","BitIn"],["b","Bit"]]]]]]] ]], "instances":{ - "Foo_inst0":{ + "foo_inst0":{ "modref":"global.Foo" }, - "Foo_inst1":{ + "foo_inst1":{ "modref":"global.Foo" }, - "Foo_inst2":{ + "foo_inst2":{ "modref":"global.Foo" } }, "connections":[ - ["self.I.x.a","Foo_inst0.ifc.I"], - ["self.I.y.a","Foo_inst0.ifc.O"], - ["self.I.x.b","Foo_inst1.ifc.I"], - ["self.I.y.b","Foo_inst1.ifc.O"], - ["self.I.z.a","Foo_inst2.ifc.I"], - ["self.I.z.b","Foo_inst2.ifc.O"] + ["self.I.x.a","foo_inst0.ifc.I"], + ["self.I.y.a","foo_inst0.ifc.O"], + ["self.I.x.b","foo_inst1.ifc.I"], + ["self.I.y.b","foo_inst1.ifc.O"], + ["self.I.z.a","foo_inst2.ifc.I"], + ["self.I.z.b","foo_inst2.ifc.O"] ] } } diff --git a/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v b/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v index 54a3a5eb6..35ea3d1cc 100644 --- a/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v +++ b/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v @@ -31,19 +31,13 @@ module Main ( output O0, output O1 ); -wire Foo_inst0_O1; wire corebit_undriven_inst1_out; -Foo Foo_inst0 ( - .I0(I0), - .I1(corebit_undriven_inst1_out), - .O0(O0), - .O1(Foo_inst0_O1) -); +wire foo_O1; corebit_term corebit_term_inst0 ( .in(I1) ); corebit_term corebit_term_inst1 ( - .in(Foo_inst0_O1) + .in(foo_O1) ); corebit_undriven corebit_undriven_inst0 ( .out(O1) @@ -51,5 +45,11 @@ corebit_undriven corebit_undriven_inst0 ( corebit_undriven corebit_undriven_inst1 ( .out(corebit_undriven_inst1_out) ); +Foo foo ( + .I0(I0), + .I1(corebit_undriven_inst1_out), + .O0(O0), + .O1(foo_O1) +); endmodule diff --git a/tests/test_errors/test_tuple_errors.py b/tests/test_errors/test_tuple_errors.py index 2b869f1b1..c8d14cfcb 100644 --- a/tests/test_errors/test_tuple_errors.py +++ b/tests/test_errors/test_tuple_errors.py @@ -188,5 +188,5 @@ class Bar(m.Circuit): assert caplog.messages[0] == "Bar.z.x not driven" assert caplog.messages[1] == "Bar.z.x: Unconnected" - assert caplog.messages[2] == "Foo_inst0.z.y not driven" - assert caplog.messages[3] == "Foo_inst0.z.y: Unconnected" + assert caplog.messages[2] == "foo.z.y not driven" + assert caplog.messages[3] == "foo.z.y: Unconnected" diff --git a/tests/test_higher/test_braid.py b/tests/test_higher/test_braid.py index fb0adb3de..c84fdc953 100644 --- a/tests/test_higher/test_braid.py +++ b/tests/test_higher/test_braid.py @@ -37,6 +37,6 @@ class _Top(Circuit): assert repr(lut1) == 'lut1 = Buf(name="lut1")' assert repr(lut2) == 'lut2 = Buf(name="lut2")' - assert repr(lut3) == 'AnonymousCircuitType("I", lut2.I, "O", lut1.O)' + assert repr(lut3) == 'lut3 = AnonymousCircuitType("I", lut2.I, "O", lut1.O)' diff --git a/tests/test_higher/test_curry.py b/tests/test_higher/test_curry.py index 91d2fc078..e3199f7d6 100644 --- a/tests/test_higher/test_curry.py +++ b/tests/test_higher/test_curry.py @@ -16,8 +16,8 @@ class _Top(Circuit): lut3 = _Top.lut3 assert repr(lut1) == 'lut1 = LUT2(name="lut1")' - assert repr(lut2) == 'AnonymousCircuitType("I", array([lut1.I0, lut1.I1]), "O", lut1.O)' - assert repr(lut3) == 'AnonymousCircuitType("I0", lut1.I0, "I1", lut1.I1, "O", lut1.O)' + assert repr(lut2) == 'lut2 = AnonymousCircuitType("I", array([lut1.I0, lut1.I1]), "O", lut1.O)' + assert repr(lut3) == 'lut3 = AnonymousCircuitType("I0", lut1.I0, "I1", lut1.I1, "O", lut1.O)' def test_rom(): class ROM2(Circuit): @@ -35,7 +35,7 @@ class _Top(Circuit): rom3 = _Top.rom3 assert repr(rom1) == 'rom1 = ROM2(name="rom1")' - assert repr(rom2) == 'AnonymousCircuitType("I0", rom1.I[0], "I1", rom1.I[1], "O", rom1.O)' - assert repr(rom3) == 'AnonymousCircuitType("I", array([rom1.I[0], rom1.I[1]]), "O", rom1.O)' + assert repr(rom2) == 'rom2 = AnonymousCircuitType("I0", rom1.I[0], "I1", rom1.I[1], "O", rom1.O)' + assert repr(rom3) == 'rom3 = AnonymousCircuitType("I", array([rom1.I[0], rom1.I[1]]), "O", rom1.O)' diff --git a/tests/test_higher/test_join.py b/tests/test_higher/test_join.py index 8d1ff9cdf..1dbfe6ab0 100644 --- a/tests/test_higher/test_join.py +++ b/tests/test_higher/test_join.py @@ -10,4 +10,4 @@ class _Top(m.Circuit): and1 = And2(name='and1') a = m.join(and0, and1) - assert repr(_Top.a) == 'AnonymousCircuitType("I0", array([and0.I0, and1.I0]), "I1", array([and0.I1, and1.I1]), "O", array([and0.O, and1.O]))' + assert repr(_Top.a) == 'a = AnonymousCircuitType("I0", array([and0.I0, and1.I0]), "I1", array([and0.I1, and1.I1]), "O", array([and0.O, and1.O]))' diff --git a/tests/test_ir/gold/declaretest.v b/tests/test_ir/gold/declaretest.v index f0fc76a4f..2534dfb8a 100644 --- a/tests/test_ir/gold/declaretest.v +++ b/tests/test_ir/gold/declaretest.v @@ -1,6 +1,6 @@ module main (input I0, input I1, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire inst0_O; +And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O)); +assign O = inst0_O; endmodule diff --git a/tests/test_ir/test_ir.py b/tests/test_ir/test_ir.py index 16f54ef32..7afd00c47 100644 --- a/tests/test_ir/test_ir.py +++ b/tests/test_ir/test_ir.py @@ -26,15 +26,15 @@ class main(Circuit): #print(result) assert result == """\ AndN2 = DefineCircuit("AndN2", "I", Array[(2, In(Bit))], "O", Out(Bit)) -And2_inst0 = And2() -wire(AndN2.I[0], And2_inst0.I0) -wire(AndN2.I[1], And2_inst0.I1) -wire(And2_inst0.O, AndN2.O) +and2 = And2() +wire(AndN2.I[0], and2.I0) +wire(AndN2.I[1], and2.I1) +wire(and2.O, AndN2.O) EndCircuit() main = DefineCircuit("main", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) -AndN2_inst0 = AndN2() -wire(main.I0, AndN2_inst0.I[0]) -wire(main.I1, AndN2_inst0.I[1]) -wire(AndN2_inst0.O, main.O) +and2 = AndN2() +wire(main.I0, and2.I[0]) +wire(main.I1, and2.I[1]) +wire(and2.O, main.O) EndCircuit() """ diff --git a/tests/test_ir_pass.py b/tests/test_ir_pass.py index a28c1f795..ed8505c2c 100644 --- a/tests/test_ir_pass.py +++ b/tests/test_ir_pass.py @@ -31,13 +31,13 @@ def test_basic(): _Cell_inst1 = _Cell() _Cell_inst2 = _Cell() _Cell_inst3 = _Cell() -_Cell_inst4 = _Cell() +cell = _Cell() wire(_Top.I, _Cell_inst0.I) wire(_Cell_inst0.O, _Cell_inst1.I) wire(_Cell_inst1.O, _Cell_inst2.I) wire(_Cell_inst2.O, _Cell_inst3.I) -wire(_Cell_inst3.O, _Cell_inst4.I) -wire(_Cell_inst4.O, _Top.O) +wire(_Cell_inst3.O, cell.I) +wire(cell.O, _Top.O) EndCircuit() """ diff --git a/tests/test_meta/gold/creg.v b/tests/test_meta/gold/creg.v index 2b0c803e1..b027aaf5a 100644 --- a/tests/test_meta/gold/creg.v +++ b/tests/test_meta/gold/creg.v @@ -7,8 +7,8 @@ assign O = {DFF_inst1_O,DFF_inst0_O}; endmodule module main (input CLK, input [1:0] I, output [1:0] O); -wire [1:0] Register2_inst0_O; -Register2 Register2_inst0 (.I(I), .O(Register2_inst0_O), .CLK(CLK)); -assign O = Register2_inst0_O; +wire [1:0] reg_O; +Register2 reg (.I(I), .O(reg_O), .CLK(CLK)); +assign O = reg_O; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v b/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v index e8f80c4b3..0d47e23a2 100644 --- a/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v +++ b/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v @@ -5,17 +5,17 @@ module Main ( input z_1_x, output z_1_y ); -wire Foo_inst0_z_0_y; wire a_x; wire a_y; -Foo Foo_inst0 ( +wire foo_z_0_y; +assign a_x = foo_z_0_y; +assign a_y = z_0_x; +Foo foo ( .z_0_x(a_y), - .z_0_y(Foo_inst0_z_0_y), + .z_0_y(foo_z_0_y), .z_1_x(z_0_x), .z_1_y(z_1_y) ); -assign a_x = Foo_inst0_z_0_y; -assign a_y = z_0_x; assign z_0_y = a_x; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v b/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v index 17ee499f1..4b06bac37 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v @@ -3,19 +3,19 @@ module Main ( input [4:0] I [4:0], output [4:0] O [4:0] ); -wire [4:0] Foo_inst0_O [4:0]; +wire [4:0] foo_O [4:0]; wire [24:0] x; -wire [4:0] Foo_inst0_I [4:0]; -assign Foo_inst0_I[4] = I[4]; -assign Foo_inst0_I[3] = I[3]; -assign Foo_inst0_I[2] = I[2]; -assign Foo_inst0_I[1] = I[1]; -assign Foo_inst0_I[0] = I[0]; -Foo Foo_inst0 ( - .I(Foo_inst0_I), - .O(Foo_inst0_O) +wire [4:0] foo_I [4:0]; +assign foo_I[4] = I[4]; +assign foo_I[3] = I[3]; +assign foo_I[2] = I[2]; +assign foo_I[1] = I[1]; +assign foo_I[0] = I[0]; +Foo foo ( + .I(foo_I), + .O(foo_O) ); -assign x = {Foo_inst0_O[4],Foo_inst0_O[3],Foo_inst0_O[2],Foo_inst0_O[1],Foo_inst0_O[0]}; +assign x = {foo_O[4],foo_O[3],foo_O[2],foo_O[1],foo_O[0]}; assign O[4] = {x[24],x[23],x[22],x[21],x[20]}; assign O[3] = {x[19],x[18],x[17],x[16],x[15]}; assign O[2] = {x[14],x[13],x[12],x[11],x[10]}; diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v b/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v index 924b0e9f6..7474efa07 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v @@ -3,13 +3,13 @@ module Main ( input I, output O ); -wire Foo_inst0_O; +wire foo_O; wire x; -Foo Foo_inst0 ( +Foo foo ( .I(I), - .O(Foo_inst0_O) + .O(foo_O) ); -assign x = Foo_inst0_O; +assign x = foo_O; assign O = x; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v b/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v index d7d5a5b1c..ea155721d 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v @@ -3,13 +3,13 @@ module Main ( input [4:0] I, output [4:0] O ); -wire [4:0] Foo_inst0_O; +wire [4:0] foo_O; wire [4:0] x; -Foo Foo_inst0 ( +Foo foo ( .I(I), - .O(Foo_inst0_O) + .O(foo_O) ); -assign x = Foo_inst0_O; +assign x = foo_O; assign O = x; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v b/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v index f90b70a5b..13dfba1f2 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v @@ -5,16 +5,16 @@ module Main ( output [4:0] O__0, output O__1 ); -wire [4:0] Foo_inst0_O__0; -wire Foo_inst0_O__1; +wire [4:0] foo_O__0; +wire foo_O__1; wire [5:0] x; -Foo Foo_inst0 ( +Foo foo ( .I__0(I__0), .I__1(I__1), - .O__0(Foo_inst0_O__0), - .O__1(Foo_inst0_O__1) + .O__0(foo_O__0), + .O__1(foo_O__1) ); -assign x = {Foo_inst0_O__1,Foo_inst0_O__0}; +assign x = {foo_O__1,foo_O__0}; assign O__0 = {x[4],x[3],x[2],x[1],x[0]}; assign O__1 = x[5]; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v b/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v index c93a32a7e..fa6ac905b 100644 --- a/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v +++ b/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v @@ -3,11 +3,15 @@ module Main ( output [1:0] O0, output [1:0] O1 ); +wire [1:0] x_0; +wire [1:0] x_1; wire y; wire z; +assign x_0 = {z,y}; +assign x_1 = {y,z}; assign y = I[1]; assign z = I[0]; -assign O0 = {z,y}; -assign O1 = {z,y}; +assign O0 = {x_1[0],x_0[0]}; +assign O1 = {x_0[1],x_1[1]}; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v b/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v index 769644c3b..84b8c5b1a 100644 --- a/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v +++ b/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v @@ -3,15 +3,15 @@ module Main ( input z_x, output z_y ); -wire Foo_inst0_z_y; wire a_x; wire a_y; -Foo Foo_inst0 ( +wire foo_z_y; +assign a_x = foo_z_y; +assign a_y = z_x; +Foo foo ( .z_x(a_y), - .z_y(Foo_inst0_z_y) + .z_y(foo_z_y) ); -assign a_x = Foo_inst0_z_y; -assign a_y = z_x; assign z_y = a_x; endmodule diff --git a/tests/test_primitives/gold/test_memory_arr.v b/tests/test_primitives/gold/test_memory_arr.v index 59bad0e8f..26604c101 100644 --- a/tests/test_primitives/gold/test_memory_arr.v +++ b/tests/test_primitives/gold/test_memory_arr.v @@ -90,7 +90,7 @@ module test_memory_arr ( input [4:0] wdata_1_Y, input wen ); -Memory Memory_inst0 ( +Memory Mem4xT ( .CLK(clk), .RADDR(raddr), .RDATA_0_X(rdata_0_X), diff --git a/tests/test_primitives/gold/test_memory_basic.mlir b/tests/test_primitives/gold/test_memory_basic.mlir index f456b0007..a5e5b9ce2 100644 --- a/tests/test_primitives/gold/test_memory_basic.mlir +++ b/tests/test_primitives/gold/test_memory_basic.mlir @@ -1,36 +1,38 @@ -hw.module @Memory(%RADDR: i2, %CLK: i1, %WADDR: i2, %WDATA: i5, %WE: i1) -> (RDATA: i5) { - %1 = sv.reg {name = "coreir_mem4x5_inst0"} : !hw.inout> - %2 = sv.array_index_inout %1[%RADDR] : !hw.inout>, i2 - %0 = sv.read_inout %2 : !hw.inout - %3 = sv.array_index_inout %1[%WADDR] : !hw.inout>, i2 - sv.alwaysff(posedge %CLK) { - sv.if %WE { - sv.passign %3, %WDATA : i5 +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module @Memory(%RADDR: i2, %CLK: i1, %WADDR: i2, %WDATA: i5, %WE: i1) -> (RDATA: i5) { + %1 = sv.reg {name = "coreir_mem4x5_inst0"} : !hw.inout> + %2 = sv.array_index_inout %1[%RADDR] : !hw.inout>, i2 + %0 = sv.read_inout %2 : !hw.inout + %3 = sv.array_index_inout %1[%WADDR] : !hw.inout>, i2 + sv.alwaysff(posedge %CLK) { + sv.if %WE { + sv.passign %3, %WDATA : i5 + } } + hw.output %0 : i5 } - hw.output %0 : i5 -} -hw.module @test_memory_basic(%raddr: i2, %waddr: i2, %wdata: i5, %clk: i1, %wen: i1) -> (rdata: i5) { - %0 = hw.constant 1 : i1 - %1 = hw.constant 0 : i2 - %2 = hw.constant 0 : i5 - %3 = hw.constant 0 : i1 - %7 = sv.reg : !hw.inout - %4 = sv.read_inout %7 : !hw.inout - %8 = sv.reg : !hw.inout - %5 = sv.read_inout %8 : !hw.inout - %9 = sv.reg : !hw.inout - %6 = sv.read_inout %9 : !hw.inout - sv.alwayscomb { - sv.bpassign %7, %1 : i2 - sv.bpassign %8, %2 : i5 - sv.bpassign %9, %3 : i1 - sv.if %wen { - sv.bpassign %7, %waddr : i2 - sv.bpassign %8, %wdata : i5 - sv.bpassign %9, %0 : i1 + hw.module @test_memory_basic(%raddr: i2, %waddr: i2, %wdata: i5, %clk: i1, %wen: i1) -> (rdata: i5) { + %0 = hw.constant 1 : i1 + %1 = hw.constant 0 : i2 + %2 = hw.constant 0 : i5 + %3 = hw.constant 0 : i1 + %7 = sv.reg : !hw.inout + %4 = sv.read_inout %7 : !hw.inout + %8 = sv.reg : !hw.inout + %5 = sv.read_inout %8 : !hw.inout + %9 = sv.reg : !hw.inout + %6 = sv.read_inout %9 : !hw.inout + sv.alwayscomb { + sv.bpassign %7, %1 : i2 + sv.bpassign %8, %2 : i5 + sv.bpassign %9, %3 : i1 + sv.if %wen { + sv.bpassign %7, %waddr : i2 + sv.bpassign %8, %wdata : i5 + sv.bpassign %9, %0 : i1 + } } + %10 = hw.instance "Mem4x5" @Memory(RADDR: %raddr: i2, CLK: %clk: i1, WADDR: %4: i2, WDATA: %5: i5, WE: %6: i1) -> (RDATA: i5) + hw.output %10 : i5 } - %10 = hw.instance "Memory_inst0" @Memory(RADDR: %raddr: i2, CLK: %clk: i1, WADDR: %4: i2, WDATA: %5: i5, WE: %6: i1) -> (RDATA: i5) - hw.output %10 : i5 } diff --git a/tests/test_primitives/gold/test_memory_product.v b/tests/test_primitives/gold/test_memory_product.v index b2e75f196..3a3f3dc20 100644 --- a/tests/test_primitives/gold/test_memory_product.v +++ b/tests/test_primitives/gold/test_memory_product.v @@ -80,7 +80,7 @@ module test_memory_product ( input [4:0] wdata_Y, input wen ); -Memory Memory_inst0 ( +Memory Mem4xT ( .CLK(clk), .RADDR(raddr), .RDATA_X(rdata_X), diff --git a/tests/test_primitives/gold/test_memory_product_init.v b/tests/test_primitives/gold/test_memory_product_init.v index 0b38a0055..5bad4a38e 100644 --- a/tests/test_primitives/gold/test_memory_product_init.v +++ b/tests/test_primitives/gold/test_memory_product_init.v @@ -71,7 +71,7 @@ module test_memory_product_init ( output [7:0] rdata_X, output [7:0] rdata_Y ); -Memory Memory_inst0 ( +Memory Mem4xT ( .CLK(clk), .RADDR(raddr), .RDATA_X(rdata_X), diff --git a/tests/test_primitives/gold/test_memory_read_latency_False.v b/tests/test_primitives/gold/test_memory_read_latency_False.v index 7b066466c..59c76ca83 100644 --- a/tests/test_primitives/gold/test_memory_read_latency_False.v +++ b/tests/test_primitives/gold/test_memory_read_latency_False.v @@ -179,15 +179,15 @@ module test_memory_read_latency_False ( input clk, input wen ); -wire [4:0] Memory_inst0_RDATA; -Memory Memory_inst0 ( +wire [4:0] Mem4x5_RDATA; +Memory Mem4x5 ( .RADDR(raddr), - .RDATA(Memory_inst0_RDATA), + .RDATA(Mem4x5_RDATA), .CLK(clk), .WADDR(waddr), .WDATA(wdata), .WE(wen) ); -assign rdata = Memory_inst0_RDATA; +assign rdata = Mem4x5_RDATA; endmodule diff --git a/tests/test_primitives/gold/test_memory_read_latency_True.v b/tests/test_primitives/gold/test_memory_read_latency_True.v index 3b91cd527..e61ce1bbf 100644 --- a/tests/test_primitives/gold/test_memory_read_latency_True.v +++ b/tests/test_primitives/gold/test_memory_read_latency_True.v @@ -167,16 +167,16 @@ module test_memory_read_latency_True ( input wen, input ren ); -wire [4:0] Memory_inst0_RDATA; -Memory Memory_inst0 ( +wire [4:0] Mem4x5_RDATA; +Memory Mem4x5 ( .RADDR(raddr), - .RDATA(Memory_inst0_RDATA), + .RDATA(Mem4x5_RDATA), .CLK(clk), .RE(ren), .WADDR(waddr), .WDATA(wdata), .WE(wen) ); -assign rdata = Memory_inst0_RDATA; +assign rdata = Mem4x5_RDATA; endmodule diff --git a/tests/test_primitives/gold/test_memory_read_only.v b/tests/test_primitives/gold/test_memory_read_only.v index 6010ab1f6..8a76c364b 100644 --- a/tests/test_primitives/gold/test_memory_read_only.v +++ b/tests/test_primitives/gold/test_memory_read_only.v @@ -105,12 +105,12 @@ module test_memory_read_only ( output [4:0] rdata, input clk ); -wire [4:0] Memory_inst0_RDATA; -Memory Memory_inst0 ( +wire [4:0] Mem4x5_RDATA; +Memory Mem4x5 ( .RADDR(raddr), - .RDATA(Memory_inst0_RDATA), + .RDATA(Mem4x5_RDATA), .CLK(clk) ); -assign rdata = Memory_inst0_RDATA; +assign rdata = Mem4x5_RDATA; endmodule diff --git a/tests/test_symbol_table_generation.py b/tests/test_symbol_table_generation.py index b531b5e9b..09a7eff1b 100644 --- a/tests/test_symbol_table_generation.py +++ b/tests/test_symbol_table_generation.py @@ -26,12 +26,12 @@ class DFFInit1(m.Circuit): symbol_table = _compile("build/DFFInit1", DFFInit1) assert symbol_table.get_module_name("DFFInit1") == "DFFInit1" - assert (symbol_table.get_instance_name("DFFInit1", "SB_DFF_inst0") == - (SYMBOL_TABLE_EMPTY, "SB_DFF_inst0")) + assert (symbol_table.get_instance_name("DFFInit1", "dff_inst") == + (SYMBOL_TABLE_EMPTY, "dff_inst")) assert symbol_table.get_port_name("DFFInit1", "D") == "D" assert symbol_table.get_port_name("DFFInit1", "Q") == "Q" assert symbol_table.get_port_name("DFFInit1", "C") == "C" - instance_type = symbol_table.get_instance_type("DFFInit1", "SB_DFF_inst0") + instance_type = symbol_table.get_instance_type("DFFInit1", "dff_inst") assert instance_type == "SB_DFF" @@ -50,10 +50,11 @@ class DFFList(m.Circuit): symbol_table = _compile("build/DFFList", DFFList) for i in range(10): - name = symbol_table.get_instance_name("DFFList", f"SB_DFF_inst{i}") - assert name == (SYMBOL_TABLE_EMPTY, f"SB_DFF_inst{i}") + inst_name = f"SB_DFF_inst{i}" if i < 9 else "dff" + name = symbol_table.get_instance_name("DFFList", inst_name) + assert name == (SYMBOL_TABLE_EMPTY, inst_name) instance_type = symbol_table.get_instance_type( - "DFFList", f"SB_DFF_inst{i}") + "DFFList", inst_name) assert instance_type == "SB_DFF" diff --git a/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v b/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v index 4e96c41e3..442d81df0 100644 --- a/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v +++ b/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v @@ -44,7 +44,7 @@ wire [3:0] Register_inst1_O; wire [3:0] Register_inst2_O; wire [3:0] Register_inst3_O; wire [3:0] Register_inst4_O; -wire [3:0] Register_inst5_O; +wire [3:0] call_result_O; Register Register_inst0 ( .I(I), .O(Register_inst0_O), @@ -70,11 +70,11 @@ Register Register_inst4 ( .O(Register_inst4_O), .CLK(CLK) ); -Register Register_inst5 ( +Register call_result ( .I(Register_inst4_O), - .O(Register_inst5_O), + .O(call_result_O), .CLK(CLK) ); -assign O = Register_inst5_O; +assign O = call_result_O; endmodule diff --git a/tests/test_syntax/gold/test_inline_comb_basic.v b/tests/test_syntax/gold/test_inline_comb_basic.v index 6cf079e39..ecbc3dadb 100644 --- a/tests/test_syntax/gold/test_inline_comb_basic.v +++ b/tests/test_syntax/gold/test_inline_comb_basic.v @@ -59,8 +59,11 @@ module Main ( input CLK ); wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire O1; wire magma_Bit_not_inst0_out; wire magma_Bit_not_inst1_out; +wire reg_O; Mux2xBit Mux2xBit_inst0 ( .I0(O0), .I1(magma_Bit_not_inst0_out), @@ -71,14 +74,16 @@ Mux2xBit Mux2xBit_inst1 ( .I0(O0), .I1(magma_Bit_not_inst1_out), .S(invert), - .O(O1) + .O(Mux2xBit_inst1_O) ); -Register Register_inst0 ( +assign O1 = Mux2xBit_inst1_O; +assign magma_Bit_not_inst0_out = ~ O0; +assign magma_Bit_not_inst1_out = ~ O0; +Register reg ( .I(Mux2xBit_inst0_O), - .O(O0), + .O(reg_O), .CLK(CLK) ); -assign magma_Bit_not_inst0_out = ~ O0; -assign magma_Bit_not_inst1_out = ~ O0; +assign O1 = O1; endmodule diff --git a/tests/test_syntax/gold/test_inline_comb_list.v b/tests/test_syntax/gold/test_inline_comb_list.v index 3d5181469..29fee170f 100644 --- a/tests/test_syntax/gold/test_inline_comb_list.v +++ b/tests/test_syntax/gold/test_inline_comb_list.v @@ -58,27 +58,27 @@ module Main ( output O1, input CLK ); -wire Register_inst0_O; wire magma_Bit_not_inst0_out; wire magma_Bit_not_inst1_out; +wire reg_O; Mux2xBit Mux2xBit_inst0 ( - .I0(Register_inst0_O), + .I0(\reg _O), .I1(magma_Bit_not_inst0_out), .S(s), .O(O0) ); Mux2xBit Mux2xBit_inst1 ( .I0(magma_Bit_not_inst1_out), - .I1(Register_inst0_O), + .I1(\reg _O), .S(s), .O(O1) ); -Register Register_inst0 ( +assign magma_Bit_not_inst0_out = ~ \reg _O; +assign magma_Bit_not_inst1_out = ~ \reg _O; +Register reg ( .I(O0), - .O(Register_inst0_O), + .O(reg_O), .CLK(CLK) ); -assign magma_Bit_not_inst0_out = ~ Register_inst0_O; -assign magma_Bit_not_inst1_out = ~ Register_inst0_O; endmodule diff --git a/tests/test_syntax/gold/test_inline_comb_wire.v b/tests/test_syntax/gold/test_inline_comb_wire.v index d71a60a7c..3179ac828 100644 --- a/tests/test_syntax/gold/test_inline_comb_wire.v +++ b/tests/test_syntax/gold/test_inline_comb_wire.v @@ -59,17 +59,18 @@ module Main ( ); wire Mux2xBit_inst0_O; wire magma_Bit_not_inst0_out; +wire reg_O; Mux2xBit Mux2xBit_inst0 ( .I0(O), .I1(magma_Bit_not_inst0_out), .S(invert), .O(Mux2xBit_inst0_O) ); -Register Register_inst0 ( +assign magma_Bit_not_inst0_out = ~ O; +Register reg ( .I(Mux2xBit_inst0_O), - .O(O), + .O(reg_O), .CLK(CLK) ); -assign magma_Bit_not_inst0_out = ~ O; endmodule diff --git a/tests/test_syntax/gold/test_renamed_args_wire.json b/tests/test_syntax/gold/test_renamed_args_wire.json index 8d8ff1d8f..096cba389 100644 --- a/tests/test_syntax/gold/test_renamed_args_wire.json +++ b/tests/test_syntax/gold/test_renamed_args_wire.json @@ -8,13 +8,13 @@ ["O","Bit"] ]], "instances":{ - "invert_inst0":{ + "inv":{ "modref":"global.invert" } }, "connections":[ - ["self.O","invert_inst0.O"], - ["self.I","invert_inst0.a"] + ["self.O","inv.O"], + ["self.I","inv.a"] ] }, "Not":{ diff --git a/tests/test_type/gold/test_AsyncResetN[Out]_cast.v b/tests/test_type/gold/test_AsyncResetN[Out]_cast.v index a9a725671..65d32cf48 100644 --- a/tests/test_type/gold/test_AsyncResetN[Out]_cast.v +++ b/tests/test_type/gold/test_AsyncResetN[Out]_cast.v @@ -19,7 +19,6 @@ module AsyncResetTest ( input T_Tuple_in_T, input T_in ); -wire Inst_inst0_O; wire coreir_wrapInAsyncResetN_inst0_out; wire coreir_wrapInAsyncResetN_inst1_out; wire coreir_wrapInAsyncResetN_inst2_out; @@ -31,10 +30,7 @@ wire coreir_wrapOutAsyncResetN_inst1_out; wire coreir_wrapOutAsyncResetN_inst2_out; wire coreir_wrapOutAsyncResetN_inst3_out; wire coreir_wrapOutAsyncResetN_inst4_out; -Inst Inst_inst0 ( - .O(Inst_inst0_O), - .I(coreir_wrapOutAsyncResetN_inst0_out) -); +wire inst_O; coreir_wrap coreir_wrapInAsyncResetN_inst0 ( .in(T_Tuple_in_T), .out(coreir_wrapInAsyncResetN_inst0_out) @@ -56,7 +52,7 @@ coreir_wrap coreir_wrapInAsyncResetN_inst4 ( .out(coreir_wrapInAsyncResetN_inst4_out) ); coreir_wrap coreir_wrapInAsyncResetN_inst5 ( - .in(Inst_inst0_O), + .in(inst_O), .out(coreir_wrapInAsyncResetN_inst5_out) ); coreir_wrap coreir_wrapOutAsyncResetN_inst0 ( @@ -79,6 +75,10 @@ coreir_wrap coreir_wrapOutAsyncResetN_inst4 ( .in(I_Arr[2]), .out(coreir_wrapOutAsyncResetN_inst4_out) ); +Inst inst ( + .O(inst_O), + .I(coreir_wrapOutAsyncResetN_inst0_out) +); assign Bit_Arr_out = {coreir_wrapInAsyncResetN_inst5_out,coreir_wrapInAsyncResetN_inst4_out,coreir_wrapInAsyncResetN_inst3_out,coreir_wrapInAsyncResetN_inst2_out}; assign Bit_out = coreir_wrapInAsyncResetN_inst1_out; assign O = coreir_wrapOutAsyncResetN_inst1_out; diff --git a/tests/test_type/gold/test_AsyncReset[Out]_cast.v b/tests/test_type/gold/test_AsyncReset[Out]_cast.v index 62a52ccd1..08545543c 100644 --- a/tests/test_type/gold/test_AsyncReset[Out]_cast.v +++ b/tests/test_type/gold/test_AsyncReset[Out]_cast.v @@ -19,7 +19,6 @@ module AsyncResetTest ( input T_Tuple_in_T, input T_in ); -wire Inst_inst0_O; wire coreir_wrapInAsyncReset_inst0_out; wire coreir_wrapInAsyncReset_inst1_out; wire coreir_wrapInAsyncReset_inst2_out; @@ -31,10 +30,7 @@ wire coreir_wrapOutAsyncReset_inst1_out; wire coreir_wrapOutAsyncReset_inst2_out; wire coreir_wrapOutAsyncReset_inst3_out; wire coreir_wrapOutAsyncReset_inst4_out; -Inst Inst_inst0 ( - .O(Inst_inst0_O), - .I(coreir_wrapOutAsyncReset_inst0_out) -); +wire inst_O; coreir_wrap coreir_wrapInAsyncReset_inst0 ( .in(T_Tuple_in_T), .out(coreir_wrapInAsyncReset_inst0_out) @@ -56,7 +52,7 @@ coreir_wrap coreir_wrapInAsyncReset_inst4 ( .out(coreir_wrapInAsyncReset_inst4_out) ); coreir_wrap coreir_wrapInAsyncReset_inst5 ( - .in(Inst_inst0_O), + .in(inst_O), .out(coreir_wrapInAsyncReset_inst5_out) ); coreir_wrap coreir_wrapOutAsyncReset_inst0 ( @@ -79,6 +75,10 @@ coreir_wrap coreir_wrapOutAsyncReset_inst4 ( .in(I_Arr[2]), .out(coreir_wrapOutAsyncReset_inst4_out) ); +Inst inst ( + .O(inst_O), + .I(coreir_wrapOutAsyncReset_inst0_out) +); assign Bit_Arr_out = {coreir_wrapInAsyncReset_inst5_out,coreir_wrapInAsyncReset_inst4_out,coreir_wrapInAsyncReset_inst3_out,coreir_wrapInAsyncReset_inst2_out}; assign Bit_out = coreir_wrapInAsyncReset_inst1_out; assign O = coreir_wrapOutAsyncReset_inst1_out; diff --git a/tests/test_type/gold/test_anon_bits.v b/tests/test_type/gold/test_anon_bits.v index 1df2f4f51..7d027caba 100644 --- a/tests/test_type/gold/test_anon_bits.v +++ b/tests/test_type/gold/test_anon_bits.v @@ -1,7 +1,30 @@ +module coreir_wire #( + parameter width = 1 +) ( + input [width-1:0] in, + output [width-1:0] out +); + assign out = in; +endmodule + module Test ( input [4:0] I, output [4:0] O ); -assign O = I; +wire [4:0] x_out; +wire [4:0] y_out; +coreir_wire #( + .width(5) +) x ( + .in(y_out), + .out(x_out) +); +coreir_wire #( + .width(5) +) y ( + .in(I), + .out(y_out) +); +assign O = x_out; endmodule diff --git a/tests/test_type/gold/test_array2_nested_bits_temporary.v b/tests/test_type/gold/test_array2_nested_bits_temporary.v index 157c2573b..531da0382 100644 --- a/tests/test_type/gold/test_array2_nested_bits_temporary.v +++ b/tests/test_type/gold/test_array2_nested_bits_temporary.v @@ -37,7 +37,6 @@ module Foo ( output [7:0] O [3:0], input CLK ); -wire [7:0] Register_inst0_O; wire magma_Bit_and_inst0_out; wire magma_Bit_and_inst1_out; wire magma_Bit_and_inst2_out; @@ -51,24 +50,25 @@ wire [7:0] pointer_0; wire [7:0] pointer_1; wire [7:0] pointer_2; wire [7:0] pointer_3; -Register Register_inst0 ( - .I(write_pointer), - .O(Register_inst0_O), - .CLK(CLK) -); +wire [7:0] reg_O; assign magma_Bit_and_inst0_out = pointer_0[7] & 1'b1; assign magma_Bit_and_inst1_out = pointer_1[7] & 1'b1; assign magma_Bit_and_inst2_out = pointer_2[7] & 1'b1; assign magma_Bit_and_inst3_out = pointer_3[7] & 1'b1; -assign magma_UInt_8_add_inst0_out = 8'(Register_inst0_O + 8'h00); -assign magma_UInt_8_add_inst1_out = 8'(Register_inst0_O + 8'h01); -assign magma_UInt_8_add_inst2_out = 8'(Register_inst0_O + 8'h02); -assign magma_UInt_8_add_inst3_out = 8'(Register_inst0_O + 8'h03); +assign magma_UInt_8_add_inst0_out = 8'(\reg _O + 8'h00); +assign magma_UInt_8_add_inst1_out = 8'(\reg _O + 8'h01); +assign magma_UInt_8_add_inst2_out = 8'(\reg _O + 8'h02); +assign magma_UInt_8_add_inst3_out = 8'(\reg _O + 8'h03); assign pointer = {magma_UInt_8_add_inst3_out,magma_UInt_8_add_inst2_out,magma_UInt_8_add_inst1_out,magma_UInt_8_add_inst0_out}; assign pointer_0 = magma_UInt_8_add_inst0_out; assign pointer_1 = magma_UInt_8_add_inst1_out; assign pointer_2 = magma_UInt_8_add_inst2_out; assign pointer_3 = magma_UInt_8_add_inst3_out; +Register reg ( + .I(write_pointer), + .O(reg_O), + .CLK(CLK) +); assign O[3] = {pointer[31],pointer[30],pointer[29],pointer[28],pointer[27],pointer[26],pointer[25],pointer[24]}; assign O[2] = {pointer[23],pointer[22],pointer[21],pointer[20],pointer[19],pointer[18],pointer[17],pointer[16]}; assign O[1] = {pointer[15],pointer[14],pointer[13],pointer[12],pointer[11],pointer[10],pointer[9],pointer[8]}; diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem.v b/tests/test_type/gold/test_ndarray_dynamic_getitem.v index ec5ac0f46..4112dc904 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem.v @@ -79,23 +79,23 @@ module Main ( input CLK ); wire [1:0] Mux4xArray3_Array2_Bit_inst0_O [2:0]; -wire [1:0] Register_inst0_O [3:0][2:0]; +wire [1:0] mem_O [3:0][2:0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I0 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I0[2] = Register_inst0_O[0][2]; -assign Mux4xArray3_Array2_Bit_inst0_I0[1] = Register_inst0_O[0][1]; -assign Mux4xArray3_Array2_Bit_inst0_I0[0] = Register_inst0_O[0][0]; +assign Mux4xArray3_Array2_Bit_inst0_I0[2] = mem_O[0][2]; +assign Mux4xArray3_Array2_Bit_inst0_I0[1] = mem_O[0][1]; +assign Mux4xArray3_Array2_Bit_inst0_I0[0] = mem_O[0][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I1 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I1[2] = Register_inst0_O[1][2]; -assign Mux4xArray3_Array2_Bit_inst0_I1[1] = Register_inst0_O[1][1]; -assign Mux4xArray3_Array2_Bit_inst0_I1[0] = Register_inst0_O[1][0]; +assign Mux4xArray3_Array2_Bit_inst0_I1[2] = mem_O[1][2]; +assign Mux4xArray3_Array2_Bit_inst0_I1[1] = mem_O[1][1]; +assign Mux4xArray3_Array2_Bit_inst0_I1[0] = mem_O[1][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I2 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I2[2] = Register_inst0_O[2][2]; -assign Mux4xArray3_Array2_Bit_inst0_I2[1] = Register_inst0_O[2][1]; -assign Mux4xArray3_Array2_Bit_inst0_I2[0] = Register_inst0_O[2][0]; +assign Mux4xArray3_Array2_Bit_inst0_I2[2] = mem_O[2][2]; +assign Mux4xArray3_Array2_Bit_inst0_I2[1] = mem_O[2][1]; +assign Mux4xArray3_Array2_Bit_inst0_I2[0] = mem_O[2][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I3 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I3[2] = Register_inst0_O[3][2]; -assign Mux4xArray3_Array2_Bit_inst0_I3[1] = Register_inst0_O[3][1]; -assign Mux4xArray3_Array2_Bit_inst0_I3[0] = Register_inst0_O[3][0]; +assign Mux4xArray3_Array2_Bit_inst0_I3[2] = mem_O[3][2]; +assign Mux4xArray3_Array2_Bit_inst0_I3[1] = mem_O[3][1]; +assign Mux4xArray3_Array2_Bit_inst0_I3[0] = mem_O[3][0]; Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .I0(Mux4xArray3_Array2_Bit_inst0_I0), .I1(Mux4xArray3_Array2_Bit_inst0_I1), @@ -104,22 +104,22 @@ Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .S(raddr), .O(Mux4xArray3_Array2_Bit_inst0_O) ); -wire [1:0] Register_inst0_I [3:0][2:0]; -assign Register_inst0_I[3][2] = Register_inst0_O[3][2]; -assign Register_inst0_I[3][1] = Register_inst0_O[3][1]; -assign Register_inst0_I[3][0] = Register_inst0_O[3][0]; -assign Register_inst0_I[2][2] = Register_inst0_O[2][2]; -assign Register_inst0_I[2][1] = Register_inst0_O[2][1]; -assign Register_inst0_I[2][0] = Register_inst0_O[2][0]; -assign Register_inst0_I[1][2] = Register_inst0_O[1][2]; -assign Register_inst0_I[1][1] = Register_inst0_O[1][1]; -assign Register_inst0_I[1][0] = Register_inst0_O[1][0]; -assign Register_inst0_I[0][2] = Register_inst0_O[0][2]; -assign Register_inst0_I[0][1] = Register_inst0_O[0][1]; -assign Register_inst0_I[0][0] = Register_inst0_O[0][0]; -Register Register_inst0 ( - .I(Register_inst0_I), - .O(Register_inst0_O), +wire [1:0] mem_I [3:0][2:0]; +assign mem_I[3][2] = mem_O[3][2]; +assign mem_I[3][1] = mem_O[3][1]; +assign mem_I[3][0] = mem_O[3][0]; +assign mem_I[2][2] = mem_O[2][2]; +assign mem_I[2][1] = mem_O[2][1]; +assign mem_I[2][0] = mem_O[2][0]; +assign mem_I[1][2] = mem_O[1][2]; +assign mem_I[1][1] = mem_O[1][1]; +assign mem_I[1][0] = mem_O[1][0]; +assign mem_I[0][2] = mem_O[0][2]; +assign mem_I[0][1] = mem_O[0][1]; +assign mem_I[0][0] = mem_O[0][0]; +Register mem ( + .I(mem_I), + .O(mem_O), .CLK(CLK) ); assign rdata[2] = Mux4xArray3_Array2_Bit_inst0_O[2]; diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v index 9b85af60d..95bf263cf 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v @@ -94,23 +94,23 @@ module Main ( ); wire [1:0] Mux4xArray3_Array2_Bit_inst0_O [2:0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_O [2:0]; -wire [1:0] Register_inst0_O [1:0][3:0][2:0]; +wire [1:0] mem_O [1:0][3:0][2:0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I0 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I0[2] = Register_inst0_O[0][0][2]; -assign Mux4xArray3_Array2_Bit_inst0_I0[1] = Register_inst0_O[0][0][1]; -assign Mux4xArray3_Array2_Bit_inst0_I0[0] = Register_inst0_O[0][0][0]; +assign Mux4xArray3_Array2_Bit_inst0_I0[2] = mem_O[0][0][2]; +assign Mux4xArray3_Array2_Bit_inst0_I0[1] = mem_O[0][0][1]; +assign Mux4xArray3_Array2_Bit_inst0_I0[0] = mem_O[0][0][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I1 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I1[2] = Register_inst0_O[0][1][2]; -assign Mux4xArray3_Array2_Bit_inst0_I1[1] = Register_inst0_O[0][1][1]; -assign Mux4xArray3_Array2_Bit_inst0_I1[0] = Register_inst0_O[0][1][0]; +assign Mux4xArray3_Array2_Bit_inst0_I1[2] = mem_O[0][1][2]; +assign Mux4xArray3_Array2_Bit_inst0_I1[1] = mem_O[0][1][1]; +assign Mux4xArray3_Array2_Bit_inst0_I1[0] = mem_O[0][1][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I2 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I2[2] = Register_inst0_O[0][2][2]; -assign Mux4xArray3_Array2_Bit_inst0_I2[1] = Register_inst0_O[0][2][1]; -assign Mux4xArray3_Array2_Bit_inst0_I2[0] = Register_inst0_O[0][2][0]; +assign Mux4xArray3_Array2_Bit_inst0_I2[2] = mem_O[0][2][2]; +assign Mux4xArray3_Array2_Bit_inst0_I2[1] = mem_O[0][2][1]; +assign Mux4xArray3_Array2_Bit_inst0_I2[0] = mem_O[0][2][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I3 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I3[2] = Register_inst0_O[0][3][2]; -assign Mux4xArray3_Array2_Bit_inst0_I3[1] = Register_inst0_O[0][3][1]; -assign Mux4xArray3_Array2_Bit_inst0_I3[0] = Register_inst0_O[0][3][0]; +assign Mux4xArray3_Array2_Bit_inst0_I3[2] = mem_O[0][3][2]; +assign Mux4xArray3_Array2_Bit_inst0_I3[1] = mem_O[0][3][1]; +assign Mux4xArray3_Array2_Bit_inst0_I3[0] = mem_O[0][3][0]; Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .I0(Mux4xArray3_Array2_Bit_inst0_I0), .I1(Mux4xArray3_Array2_Bit_inst0_I1), @@ -120,21 +120,21 @@ Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .O(Mux4xArray3_Array2_Bit_inst0_O) ); wire [1:0] Mux4xArray3_Array2_Bit_inst1_I0 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I0[2] = Register_inst0_O[1][0][2]; -assign Mux4xArray3_Array2_Bit_inst1_I0[1] = Register_inst0_O[1][0][1]; -assign Mux4xArray3_Array2_Bit_inst1_I0[0] = Register_inst0_O[1][0][0]; +assign Mux4xArray3_Array2_Bit_inst1_I0[2] = mem_O[1][0][2]; +assign Mux4xArray3_Array2_Bit_inst1_I0[1] = mem_O[1][0][1]; +assign Mux4xArray3_Array2_Bit_inst1_I0[0] = mem_O[1][0][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_I1 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I1[2] = Register_inst0_O[1][1][2]; -assign Mux4xArray3_Array2_Bit_inst1_I1[1] = Register_inst0_O[1][1][1]; -assign Mux4xArray3_Array2_Bit_inst1_I1[0] = Register_inst0_O[1][1][0]; +assign Mux4xArray3_Array2_Bit_inst1_I1[2] = mem_O[1][1][2]; +assign Mux4xArray3_Array2_Bit_inst1_I1[1] = mem_O[1][1][1]; +assign Mux4xArray3_Array2_Bit_inst1_I1[0] = mem_O[1][1][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_I2 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I2[2] = Register_inst0_O[1][2][2]; -assign Mux4xArray3_Array2_Bit_inst1_I2[1] = Register_inst0_O[1][2][1]; -assign Mux4xArray3_Array2_Bit_inst1_I2[0] = Register_inst0_O[1][2][0]; +assign Mux4xArray3_Array2_Bit_inst1_I2[2] = mem_O[1][2][2]; +assign Mux4xArray3_Array2_Bit_inst1_I2[1] = mem_O[1][2][1]; +assign Mux4xArray3_Array2_Bit_inst1_I2[0] = mem_O[1][2][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_I3 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I3[2] = Register_inst0_O[1][3][2]; -assign Mux4xArray3_Array2_Bit_inst1_I3[1] = Register_inst0_O[1][3][1]; -assign Mux4xArray3_Array2_Bit_inst1_I3[0] = Register_inst0_O[1][3][0]; +assign Mux4xArray3_Array2_Bit_inst1_I3[2] = mem_O[1][3][2]; +assign Mux4xArray3_Array2_Bit_inst1_I3[1] = mem_O[1][3][1]; +assign Mux4xArray3_Array2_Bit_inst1_I3[0] = mem_O[1][3][0]; Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst1 ( .I0(Mux4xArray3_Array2_Bit_inst1_I0), .I1(Mux4xArray3_Array2_Bit_inst1_I1), @@ -143,34 +143,34 @@ Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst1 ( .S(raddr1), .O(Mux4xArray3_Array2_Bit_inst1_O) ); -wire [1:0] Register_inst0_I [1:0][3:0][2:0]; -assign Register_inst0_I[1][3][2] = Register_inst0_O[1][3][2]; -assign Register_inst0_I[1][3][1] = Register_inst0_O[1][3][1]; -assign Register_inst0_I[1][3][0] = Register_inst0_O[1][3][0]; -assign Register_inst0_I[1][2][2] = Register_inst0_O[1][2][2]; -assign Register_inst0_I[1][2][1] = Register_inst0_O[1][2][1]; -assign Register_inst0_I[1][2][0] = Register_inst0_O[1][2][0]; -assign Register_inst0_I[1][1][2] = Register_inst0_O[1][1][2]; -assign Register_inst0_I[1][1][1] = Register_inst0_O[1][1][1]; -assign Register_inst0_I[1][1][0] = Register_inst0_O[1][1][0]; -assign Register_inst0_I[1][0][2] = Register_inst0_O[1][0][2]; -assign Register_inst0_I[1][0][1] = Register_inst0_O[1][0][1]; -assign Register_inst0_I[1][0][0] = Register_inst0_O[1][0][0]; -assign Register_inst0_I[0][3][2] = Register_inst0_O[0][3][2]; -assign Register_inst0_I[0][3][1] = Register_inst0_O[0][3][1]; -assign Register_inst0_I[0][3][0] = Register_inst0_O[0][3][0]; -assign Register_inst0_I[0][2][2] = Register_inst0_O[0][2][2]; -assign Register_inst0_I[0][2][1] = Register_inst0_O[0][2][1]; -assign Register_inst0_I[0][2][0] = Register_inst0_O[0][2][0]; -assign Register_inst0_I[0][1][2] = Register_inst0_O[0][1][2]; -assign Register_inst0_I[0][1][1] = Register_inst0_O[0][1][1]; -assign Register_inst0_I[0][1][0] = Register_inst0_O[0][1][0]; -assign Register_inst0_I[0][0][2] = Register_inst0_O[0][0][2]; -assign Register_inst0_I[0][0][1] = Register_inst0_O[0][0][1]; -assign Register_inst0_I[0][0][0] = Register_inst0_O[0][0][0]; -Register Register_inst0 ( - .I(Register_inst0_I), - .O(Register_inst0_O), +wire [1:0] mem_I [1:0][3:0][2:0]; +assign mem_I[1][3][2] = mem_O[1][3][2]; +assign mem_I[1][3][1] = mem_O[1][3][1]; +assign mem_I[1][3][0] = mem_O[1][3][0]; +assign mem_I[1][2][2] = mem_O[1][2][2]; +assign mem_I[1][2][1] = mem_O[1][2][1]; +assign mem_I[1][2][0] = mem_O[1][2][0]; +assign mem_I[1][1][2] = mem_O[1][1][2]; +assign mem_I[1][1][1] = mem_O[1][1][1]; +assign mem_I[1][1][0] = mem_O[1][1][0]; +assign mem_I[1][0][2] = mem_O[1][0][2]; +assign mem_I[1][0][1] = mem_O[1][0][1]; +assign mem_I[1][0][0] = mem_O[1][0][0]; +assign mem_I[0][3][2] = mem_O[0][3][2]; +assign mem_I[0][3][1] = mem_O[0][3][1]; +assign mem_I[0][3][0] = mem_O[0][3][0]; +assign mem_I[0][2][2] = mem_O[0][2][2]; +assign mem_I[0][2][1] = mem_O[0][2][1]; +assign mem_I[0][2][0] = mem_O[0][2][0]; +assign mem_I[0][1][2] = mem_O[0][1][2]; +assign mem_I[0][1][1] = mem_O[0][1][1]; +assign mem_I[0][1][0] = mem_O[0][1][0]; +assign mem_I[0][0][2] = mem_O[0][0][2]; +assign mem_I[0][0][1] = mem_O[0][0][1]; +assign mem_I[0][0][0] = mem_O[0][0][0]; +Register mem ( + .I(mem_I), + .O(mem_O), .CLK(CLK) ); assign rdata0[2] = Mux4xArray3_Array2_Bit_inst0_O[2]; diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v index 0e635aa46..7218d857b 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v @@ -97,35 +97,35 @@ module Main ( ); wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_O [1:0][2:0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_O [1:0][2:0]; -wire [1:0] Register_inst0_O [3:0][1:0][2:0]; +wire [1:0] mem_O [3:0][1:0][2:0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I0 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][2] = Register_inst0_O[0][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][1] = Register_inst0_O[0][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][0] = Register_inst0_O[0][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][2] = Register_inst0_O[0][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][1] = Register_inst0_O[0][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][0] = Register_inst0_O[0][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][2] = mem_O[0][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][1] = mem_O[0][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][0] = mem_O[0][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][2] = mem_O[0][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][1] = mem_O[0][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][0] = mem_O[0][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I1 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][2] = Register_inst0_O[1][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][1] = Register_inst0_O[1][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][0] = Register_inst0_O[1][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][2] = Register_inst0_O[1][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][1] = Register_inst0_O[1][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][0] = Register_inst0_O[1][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][2] = mem_O[1][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][1] = mem_O[1][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][0] = mem_O[1][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][2] = mem_O[1][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][1] = mem_O[1][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][0] = mem_O[1][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I2 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][2] = Register_inst0_O[2][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][1] = Register_inst0_O[2][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][0] = Register_inst0_O[2][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][2] = Register_inst0_O[2][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][1] = Register_inst0_O[2][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][0] = Register_inst0_O[2][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][2] = mem_O[2][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][1] = mem_O[2][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][0] = mem_O[2][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][2] = mem_O[2][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][1] = mem_O[2][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][0] = mem_O[2][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I3 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][2] = Register_inst0_O[3][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][1] = Register_inst0_O[3][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][0] = Register_inst0_O[3][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][2] = Register_inst0_O[3][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][1] = Register_inst0_O[3][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][0] = Register_inst0_O[3][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][2] = mem_O[3][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][1] = mem_O[3][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][0] = mem_O[3][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][2] = mem_O[3][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][1] = mem_O[3][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][0] = mem_O[3][0][0]; Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst0 ( .I0(Mux4xArray2_Array3_Array2_Bit_inst0_I0), .I1(Mux4xArray2_Array3_Array2_Bit_inst0_I1), @@ -135,33 +135,33 @@ Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst0 ( .O(Mux4xArray2_Array3_Array2_Bit_inst0_O) ); wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I0 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][2] = Register_inst0_O[0][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][1] = Register_inst0_O[0][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][0] = Register_inst0_O[0][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][2] = Register_inst0_O[0][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][1] = Register_inst0_O[0][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][0] = Register_inst0_O[0][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][2] = mem_O[0][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][1] = mem_O[0][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][0] = mem_O[0][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][2] = mem_O[0][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][1] = mem_O[0][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][0] = mem_O[0][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I1 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][2] = Register_inst0_O[1][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][1] = Register_inst0_O[1][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][0] = Register_inst0_O[1][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][2] = Register_inst0_O[1][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][1] = Register_inst0_O[1][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][0] = Register_inst0_O[1][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][2] = mem_O[1][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][1] = mem_O[1][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][0] = mem_O[1][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][2] = mem_O[1][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][1] = mem_O[1][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][0] = mem_O[1][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I2 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][2] = Register_inst0_O[2][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][1] = Register_inst0_O[2][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][0] = Register_inst0_O[2][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][2] = Register_inst0_O[2][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][1] = Register_inst0_O[2][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][0] = Register_inst0_O[2][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][2] = mem_O[2][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][1] = mem_O[2][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][0] = mem_O[2][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][2] = mem_O[2][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][1] = mem_O[2][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][0] = mem_O[2][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I3 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][2] = Register_inst0_O[3][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][1] = Register_inst0_O[3][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][0] = Register_inst0_O[3][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][2] = Register_inst0_O[3][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][1] = Register_inst0_O[3][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][0] = Register_inst0_O[3][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][2] = mem_O[3][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][1] = mem_O[3][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][0] = mem_O[3][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][2] = mem_O[3][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][1] = mem_O[3][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][0] = mem_O[3][0][0]; Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst1 ( .I0(Mux4xArray2_Array3_Array2_Bit_inst1_I0), .I1(Mux4xArray2_Array3_Array2_Bit_inst1_I1), @@ -170,34 +170,34 @@ Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst1 ( .S(raddr1), .O(Mux4xArray2_Array3_Array2_Bit_inst1_O) ); -wire [1:0] Register_inst0_I [3:0][1:0][2:0]; -assign Register_inst0_I[3][1][2] = Register_inst0_O[3][1][2]; -assign Register_inst0_I[3][1][1] = Register_inst0_O[3][1][1]; -assign Register_inst0_I[3][1][0] = Register_inst0_O[3][1][0]; -assign Register_inst0_I[3][0][2] = Register_inst0_O[3][0][2]; -assign Register_inst0_I[3][0][1] = Register_inst0_O[3][0][1]; -assign Register_inst0_I[3][0][0] = Register_inst0_O[3][0][0]; -assign Register_inst0_I[2][1][2] = Register_inst0_O[2][1][2]; -assign Register_inst0_I[2][1][1] = Register_inst0_O[2][1][1]; -assign Register_inst0_I[2][1][0] = Register_inst0_O[2][1][0]; -assign Register_inst0_I[2][0][2] = Register_inst0_O[2][0][2]; -assign Register_inst0_I[2][0][1] = Register_inst0_O[2][0][1]; -assign Register_inst0_I[2][0][0] = Register_inst0_O[2][0][0]; -assign Register_inst0_I[1][1][2] = Register_inst0_O[1][1][2]; -assign Register_inst0_I[1][1][1] = Register_inst0_O[1][1][1]; -assign Register_inst0_I[1][1][0] = Register_inst0_O[1][1][0]; -assign Register_inst0_I[1][0][2] = Register_inst0_O[1][0][2]; -assign Register_inst0_I[1][0][1] = Register_inst0_O[1][0][1]; -assign Register_inst0_I[1][0][0] = Register_inst0_O[1][0][0]; -assign Register_inst0_I[0][1][2] = Register_inst0_O[0][1][2]; -assign Register_inst0_I[0][1][1] = Register_inst0_O[0][1][1]; -assign Register_inst0_I[0][1][0] = Register_inst0_O[0][1][0]; -assign Register_inst0_I[0][0][2] = Register_inst0_O[0][0][2]; -assign Register_inst0_I[0][0][1] = Register_inst0_O[0][0][1]; -assign Register_inst0_I[0][0][0] = Register_inst0_O[0][0][0]; -Register Register_inst0 ( - .I(Register_inst0_I), - .O(Register_inst0_O), +wire [1:0] mem_I [3:0][1:0][2:0]; +assign mem_I[3][1][2] = mem_O[3][1][2]; +assign mem_I[3][1][1] = mem_O[3][1][1]; +assign mem_I[3][1][0] = mem_O[3][1][0]; +assign mem_I[3][0][2] = mem_O[3][0][2]; +assign mem_I[3][0][1] = mem_O[3][0][1]; +assign mem_I[3][0][0] = mem_O[3][0][0]; +assign mem_I[2][1][2] = mem_O[2][1][2]; +assign mem_I[2][1][1] = mem_O[2][1][1]; +assign mem_I[2][1][0] = mem_O[2][1][0]; +assign mem_I[2][0][2] = mem_O[2][0][2]; +assign mem_I[2][0][1] = mem_O[2][0][1]; +assign mem_I[2][0][0] = mem_O[2][0][0]; +assign mem_I[1][1][2] = mem_O[1][1][2]; +assign mem_I[1][1][1] = mem_O[1][1][1]; +assign mem_I[1][1][0] = mem_O[1][1][0]; +assign mem_I[1][0][2] = mem_O[1][0][2]; +assign mem_I[1][0][1] = mem_O[1][0][1]; +assign mem_I[1][0][0] = mem_O[1][0][0]; +assign mem_I[0][1][2] = mem_O[0][1][2]; +assign mem_I[0][1][1] = mem_O[0][1][1]; +assign mem_I[0][1][0] = mem_O[0][1][0]; +assign mem_I[0][0][2] = mem_O[0][0][2]; +assign mem_I[0][0][1] = mem_O[0][0][1]; +assign mem_I[0][0][0] = mem_O[0][0][0]; +Register mem ( + .I(mem_I), + .O(mem_O), .CLK(CLK) ); assign rdata0[2] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][2]; diff --git a/tests/test_type/test_const_wire_golden.json b/tests/test_type/test_const_wire_golden.json index 22f4874df..00304f8ff 100644 --- a/tests/test_type/test_const_wire_golden.json +++ b/tests/test_type/test_const_wire_golden.json @@ -16,12 +16,12 @@ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "foo_inst0":{ + "foo_inst":{ "modref":"global.foo" } }, "connections":[ - ["foo_inst0.I","bit_const_0_None.out"], + ["foo_inst.I","bit_const_0_None.out"], ["self.O","bit_const_0_None.out"] ] } diff --git a/tests/test_type/test_coreir_wrap_golden_AsyncReset.json b/tests/test_type/test_coreir_wrap_golden_AsyncReset.json index fc5a4cdaa..16becb9ab 100644 --- a/tests/test_type/test_coreir_wrap_golden_AsyncReset.json +++ b/tests/test_type/test_coreir_wrap_golden_AsyncReset.json @@ -17,18 +17,18 @@ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "coreir_wrapBit_inst0":{ + "foo_inst":{ + "modref":"global.foo" + }, + "wrap":{ "genref":"coreir.wrap", "genargs":{"type":["CoreIRType",["Named","coreir.arst"]]} - }, - "foo_inst0":{ - "modref":"global.foo" } }, "connections":[ - ["coreir_wrapBit_inst0.in","bit_const_0_None.out"], ["self.O","bit_const_0_None.out"], - ["foo_inst0.r","coreir_wrapBit_inst0.out"] + ["wrap.in","bit_const_0_None.out"], + ["wrap.out","foo_inst.r"] ] } } diff --git a/tests/test_type/test_coreir_wrap_golden_Clock.json b/tests/test_type/test_coreir_wrap_golden_Clock.json index e626a5582..127fb1a01 100644 --- a/tests/test_type/test_coreir_wrap_golden_Clock.json +++ b/tests/test_type/test_coreir_wrap_golden_Clock.json @@ -17,18 +17,18 @@ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "coreir_wrapBit_inst0":{ + "foo_inst":{ + "modref":"global.foo" + }, + "wrap":{ "genref":"coreir.wrap", "genargs":{"type":["CoreIRType",["Named","coreir.clk"]]} - }, - "foo_inst0":{ - "modref":"global.foo" } }, "connections":[ - ["coreir_wrapBit_inst0.in","bit_const_0_None.out"], ["self.O","bit_const_0_None.out"], - ["foo_inst0.r","coreir_wrapBit_inst0.out"] + ["wrap.in","bit_const_0_None.out"], + ["wrap.out","foo_inst.r"] ] } } diff --git a/tests/test_verilog/gold/TestDisplay.v b/tests/test_verilog/gold/TestDisplay.v index 7d2b6085e..fed6d69b5 100644 --- a/tests/test_verilog/gold/TestDisplay.v +++ b/tests/test_verilog/gold/TestDisplay.v @@ -43,12 +43,6 @@ wire _magma_inline_wire0; wire _magma_inline_wire1; wire _magma_inline_wire2_O; wire _magma_inline_wire3; -FF FF_inst0 ( - .I(I), - .O(O), - .CLK(CLK), - .CE(CE) -); assign _magma_inline_wire0 = O; assign _magma_inline_wire1 = I; WireClock _magma_inline_wire2 ( @@ -56,6 +50,12 @@ WireClock _magma_inline_wire2 ( .O(_magma_inline_wire2_O) ); assign _magma_inline_wire3 = CE; +FF ff ( + .I(I), + .O(O), + .CLK(CLK), + .CE(CE) +); always @(posedge _magma_inline_wire2_O) begin if (_magma_inline_wire3) $display("%0t: ff.O=%d, ff.I=%d", $time, _magma_inline_wire0, _magma_inline_wire1); end diff --git a/tests/test_verilog/gold/TestFDisplay.v b/tests/test_verilog/gold/TestFDisplay.v index 3c693f143..b77d16f76 100644 --- a/tests/test_verilog/gold/TestFDisplay.v +++ b/tests/test_verilog/gold/TestFDisplay.v @@ -43,12 +43,6 @@ wire _magma_inline_wire0; wire _magma_inline_wire1; wire _magma_inline_wire2_O; wire _magma_inline_wire3; -FF FF_inst0 ( - .I(I), - .O(O), - .CLK(CLK), - .CE(CE) -); assign _magma_inline_wire0 = O; assign _magma_inline_wire1 = I; WireClock _magma_inline_wire2 ( @@ -56,6 +50,12 @@ WireClock _magma_inline_wire2 ( .O(_magma_inline_wire2_O) ); assign _magma_inline_wire3 = CE; +FF ff ( + .I(I), + .O(O), + .CLK(CLK), + .CE(CE) +); integer \_file_test_fdisplay.log ; initial \_file_test_fdisplay.log = $fopen("test_fdisplay.log", "a"); diff --git a/tests/test_verilog/gold/TestFLog.v b/tests/test_verilog/gold/TestFLog.v index 8191e4ae1..7fb5d740f 100644 --- a/tests/test_verilog/gold/TestFLog.v +++ b/tests/test_verilog/gold/TestFLog.v @@ -43,12 +43,6 @@ wire _magma_inline_wire0; wire _magma_inline_wire1; wire _magma_inline_wire2_O; wire _magma_inline_wire3; -FF FF_inst0 ( - .I(I), - .O(O), - .CLK(CLK), - .CE(CE) -); assign _magma_inline_wire0 = O; assign _magma_inline_wire1 = I; WireClock _magma_inline_wire2 ( @@ -56,6 +50,12 @@ WireClock _magma_inline_wire2 ( .O(_magma_inline_wire2_O) ); assign _magma_inline_wire3 = CE; +FF ff ( + .I(I), + .O(O), + .CLK(CLK), + .CE(CE) +); `ifndef MAGMA_LOG_LEVEL `define MAGMA_LOG_LEVEL 1 diff --git a/tests/test_verilog/gold/TestLog.v b/tests/test_verilog/gold/TestLog.v index 013c65663..b9a193fd3 100644 --- a/tests/test_verilog/gold/TestLog.v +++ b/tests/test_verilog/gold/TestLog.v @@ -43,12 +43,6 @@ wire _magma_inline_wire0; wire _magma_inline_wire1; wire _magma_inline_wire2_O; wire _magma_inline_wire3; -FF FF_inst0 ( - .I(I), - .O(O), - .CLK(CLK), - .CE(CE) -); assign _magma_inline_wire0 = O; assign _magma_inline_wire1 = I; WireClock _magma_inline_wire2 ( @@ -56,6 +50,12 @@ WireClock _magma_inline_wire2 ( .O(_magma_inline_wire2_O) ); assign _magma_inline_wire3 = CE; +FF ff ( + .I(I), + .O(O), + .CLK(CLK), + .CE(CE) +); `ifndef MAGMA_LOG_LEVEL `define MAGMA_LOG_LEVEL 1 diff --git a/tests/test_verilog/gold/Top.v b/tests/test_verilog/gold/Top.v index 75ac24de1..b4577f6c4 100644 --- a/tests/test_verilog/gold/Top.v +++ b/tests/test_verilog/gold/Top.v @@ -4,22 +4,22 @@ module Top ( output O, input CLK ); -wire FF_inst0_O; -wire FF_inst1_O; +wire ff0_O; +wire ff1_O; FF #( .init(0) -) FF_inst0 ( +) ff0 ( .I(I), - .O(FF_inst0_O), + .O(ff0_O), .CLK(CLK) ); FF #( .init(1) -) FF_inst1 ( - .I(FF_inst0_O), - .O(FF_inst1_O), +) ff1 ( + .I(ff0_O), + .O(ff1_O), .CLK(CLK) ); -assign O = FF_inst1_O; +assign O = ff1_O; endmodule diff --git a/tests/test_verilog/gold/bind_test.v b/tests/test_verilog/gold/bind_test.v index 262cfaee8..0bdda1a16 100644 --- a/tests/test_verilog/gold/bind_test.v +++ b/tests/test_verilog/gold/bind_test.v @@ -77,9 +77,6 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; -bar_foo_SomeCircuit SomeCircuit_inst0 ( - .I(magma_Bits_4_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -143,6 +140,9 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); +bar_foo_SomeCircuit some_circ ( + .I(magma_Bits_4_xor_inst0_out) +); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; diff --git a/tests/test_verilog/gold/bind_uniq_test.v b/tests/test_verilog/gold/bind_uniq_test.v index e43b6d3d8..27b61373c 100644 --- a/tests/test_verilog/gold/bind_uniq_test.v +++ b/tests/test_verilog/gold/bind_uniq_test.v @@ -115,9 +115,6 @@ wire [4:0] magma_Bits_5_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_5_inst0_O; wire temp3; -bar_foo_SomeCircuit_unq1 SomeCircuit_inst0 ( - .I(magma_Bits_5_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_5_inst0_O; assign _magma_bind_wire_1 = andr_5_inst0_O; assign _magma_bind_wire_2_0 = orr_5_inst0_O; @@ -188,6 +185,9 @@ orr_5 orr_5_inst0 ( .I(in1), .O(orr_5_inst0_O) ); +bar_foo_SomeCircuit_unq1 some_circ ( + .I(magma_Bits_5_xor_inst0_out) +); assign temp3 = andr_5_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -243,9 +243,6 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; -bar_foo_SomeCircuit SomeCircuit_inst0 ( - .I(magma_Bits_4_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -316,6 +313,9 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); +bar_foo_SomeCircuit some_circ ( + .I(magma_Bits_4_xor_inst0_out) +); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -343,16 +343,16 @@ endmodule module bar_foo_Main ( input CLK ); -wire RTL_inst0_handshake_arr_0_valid; -wire RTL_inst0_handshake_arr_1_valid; -wire RTL_inst0_handshake_arr_2_valid; -wire RTL_inst0_handshake_valid; -wire RTL_inst0_out; -wire RTL_inst1_handshake_arr_0_valid; -wire RTL_inst1_handshake_arr_1_valid; -wire RTL_inst1_handshake_arr_2_valid; -wire RTL_inst1_handshake_valid; -wire RTL_inst1_out; +wire RTL4_handshake_arr_0_valid; +wire RTL4_handshake_arr_1_valid; +wire RTL4_handshake_arr_2_valid; +wire RTL4_handshake_valid; +wire RTL4_out; +wire RTL5_handshake_arr_0_valid; +wire RTL5_handshake_arr_1_valid; +wire RTL5_handshake_arr_2_valid; +wire RTL5_handshake_valid; +wire RTL5_out; wire corebit_undriven_inst0_out; wire corebit_undriven_inst1_out; wire corebit_undriven_inst10_out; @@ -377,73 +377,73 @@ wire [3:0] undriven_inst0_out; wire [3:0] undriven_inst1_out; wire [4:0] undriven_inst2_out; wire [4:0] undriven_inst3_out; -wire [1:0] RTL_inst0_ndarr [2:0]; -assign RTL_inst0_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; -assign RTL_inst0_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; -assign RTL_inst0_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; -bar_foo_RTL RTL_inst0 ( +wire [1:0] RTL4_ndarr [2:0]; +assign RTL4_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; +assign RTL4_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; +assign RTL4_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; +bar_foo_RTL RTL4 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst1_out), - .handshake_arr_0_valid(RTL_inst0_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL4_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst2_out), - .handshake_arr_1_valid(RTL_inst0_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL4_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst3_out), - .handshake_arr_2_valid(RTL_inst0_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL4_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst0_out), - .handshake_valid(RTL_inst0_handshake_valid), + .handshake_valid(RTL4_handshake_valid), .in1(undriven_inst0_out), .in2(undriven_inst1_out), - .ndarr(RTL_inst0_ndarr), - .out(RTL_inst0_out) -); -wire [1:0] RTL_inst1_ndarr [2:0]; -assign RTL_inst1_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; -assign RTL_inst1_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; -assign RTL_inst1_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; -bar_foo_RTL_unq1 RTL_inst1 ( + .ndarr(RTL4_ndarr), + .out(RTL4_out) +); +wire [1:0] RTL5_ndarr [2:0]; +assign RTL5_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; +assign RTL5_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; +assign RTL5_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; +bar_foo_RTL_unq1 RTL5 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst11_out), - .handshake_arr_0_valid(RTL_inst1_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL5_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst12_out), - .handshake_arr_1_valid(RTL_inst1_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL5_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst13_out), - .handshake_arr_2_valid(RTL_inst1_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL5_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst10_out), - .handshake_valid(RTL_inst1_handshake_valid), + .handshake_valid(RTL5_handshake_valid), .in1(undriven_inst2_out), .in2(undriven_inst3_out), - .ndarr(RTL_inst1_ndarr), - .out(RTL_inst1_out) + .ndarr(RTL5_ndarr), + .out(RTL5_out) ); bar_corebit_term corebit_term_inst0 ( - .in(RTL_inst0_out) + .in(RTL4_out) ); bar_corebit_term corebit_term_inst1 ( - .in(RTL_inst0_handshake_valid) + .in(RTL4_handshake_valid) ); bar_corebit_term corebit_term_inst2 ( - .in(RTL_inst0_handshake_arr_0_valid) + .in(RTL4_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst3 ( - .in(RTL_inst0_handshake_arr_1_valid) + .in(RTL4_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst4 ( - .in(RTL_inst0_handshake_arr_2_valid) + .in(RTL4_handshake_arr_2_valid) ); bar_corebit_term corebit_term_inst5 ( - .in(RTL_inst1_out) + .in(RTL5_out) ); bar_corebit_term corebit_term_inst6 ( - .in(RTL_inst1_handshake_valid) + .in(RTL5_handshake_valid) ); bar_corebit_term corebit_term_inst7 ( - .in(RTL_inst1_handshake_arr_0_valid) + .in(RTL5_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst8 ( - .in(RTL_inst1_handshake_arr_1_valid) + .in(RTL5_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst9 ( - .in(RTL_inst1_handshake_arr_2_valid) + .in(RTL5_handshake_arr_2_valid) ); bar_corebit_undriven corebit_undriven_inst0 ( .out(corebit_undriven_inst0_out) diff --git a/tests/test_verilog/gold/test_inline_tuple.json b/tests/test_verilog/gold/test_inline_tuple.json index b258f9a15..cd73459be 100644 --- a/tests/test_verilog/gold/test_inline_tuple.json +++ b/tests/test_verilog/gold/test_inline_tuple.json @@ -84,9 +84,6 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "DelayUnit_inst0":{ - "modref":"global.DelayUnit" - }, "Main_inline_verilog_inst_0":{ "modref":"global.Main_inline_verilog_0" }, @@ -110,34 +107,37 @@ }, "_magma_inline_wire3":{ "modref":"corebit.wire" + }, + "delay":{ + "modref":"global.DelayUnit" } }, "connections":[ - ["Main_inline_verilog_inst_2.__magma_inline_value_0","DelayUnit_inst0;_magma_inline_wire4.out"], - ["Main_inline_verilog_inst_2.__magma_inline_value_1","DelayUnit_inst0;_magma_inline_wire5.out"], - ["Main_inline_verilog_inst_3.__magma_inline_value_0","DelayUnit_inst0;inner_delay;_magma_inline_wire6.out"], - ["Main_inline_verilog_inst_3.__magma_inline_value_1","DelayUnit_inst0;inner_delay;_magma_inline_wire7.out"], - ["self.CLK","DelayUnit_inst0.CLK"], - ["self.I.1.data","DelayUnit_inst0.INPUT.0.data"], - ["_magma_inline_wire3.in","DelayUnit_inst0.INPUT.0.ready"], - ["self.I.1.ready","DelayUnit_inst0.INPUT.0.ready"], - ["self.I.1.valid","DelayUnit_inst0.INPUT.0.valid"], - ["self.I.0.data","DelayUnit_inst0.INPUT.1.data"], - ["self.I.0.ready","DelayUnit_inst0.INPUT.1.ready"], - ["self.I.0.valid","DelayUnit_inst0.INPUT.1.valid"], - ["self.O.1.data","DelayUnit_inst0.OUTPUT.0.data"], - ["self.O.1.ready","DelayUnit_inst0.OUTPUT.0.ready"], - ["self.O.1.valid","DelayUnit_inst0.OUTPUT.0.valid"], - ["self.O.0.data","DelayUnit_inst0.OUTPUT.1.data"], - ["self.O.0.ready","DelayUnit_inst0.OUTPUT.1.ready"], - ["_magma_inline_wire2.in","DelayUnit_inst0.OUTPUT.1.valid"], - ["self.O.0.valid","DelayUnit_inst0.OUTPUT.1.valid"], ["_magma_inline_wire0.out","Main_inline_verilog_inst_0.__magma_inline_value_0"], ["_magma_inline_wire1.out","Main_inline_verilog_inst_0.__magma_inline_value_1"], ["_magma_inline_wire2.out","Main_inline_verilog_inst_1.__magma_inline_value_0"], ["_magma_inline_wire3.out","Main_inline_verilog_inst_1.__magma_inline_value_1"], + ["delay;_magma_inline_wire4.out","Main_inline_verilog_inst_2.__magma_inline_value_0"], + ["delay;_magma_inline_wire5.out","Main_inline_verilog_inst_2.__magma_inline_value_1"], + ["delay;inner_delay;_magma_inline_wire6.out","Main_inline_verilog_inst_3.__magma_inline_value_0"], + ["delay;inner_delay;_magma_inline_wire7.out","Main_inline_verilog_inst_3.__magma_inline_value_1"], ["self.I.0.valid","_magma_inline_wire0.in"], - ["self.O.1.ready","_magma_inline_wire1.in"] + ["self.O.1.ready","_magma_inline_wire1.in"], + ["delay.OUTPUT.1.valid","_magma_inline_wire2.in"], + ["delay.INPUT.0.ready","_magma_inline_wire3.in"], + ["self.CLK","delay.CLK"], + ["self.I.1.data","delay.INPUT.0.data"], + ["self.I.1.ready","delay.INPUT.0.ready"], + ["self.I.1.valid","delay.INPUT.0.valid"], + ["self.I.0.data","delay.INPUT.1.data"], + ["self.I.0.ready","delay.INPUT.1.ready"], + ["self.I.0.valid","delay.INPUT.1.valid"], + ["self.O.1.data","delay.OUTPUT.0.data"], + ["self.O.1.ready","delay.OUTPUT.0.ready"], + ["self.O.1.valid","delay.OUTPUT.0.valid"], + ["self.O.0.data","delay.OUTPUT.1.data"], + ["self.O.0.ready","delay.OUTPUT.1.ready"], + ["self.O.0.valid","delay.OUTPUT.1.valid"] ] }, "Main_inline_verilog_0":{ diff --git a/tests/test_verilog/gold/test_inline_tuple.sv b/tests/test_verilog/gold/test_inline_tuple.sv index a32668959..f73dfabdb 100644 --- a/tests/test_verilog/gold/test_inline_tuple.sv +++ b/tests/test_verilog/gold/test_inline_tuple.sv @@ -95,7 +95,11 @@ wire _magma_inline_wire0; wire _magma_inline_wire1; wire _magma_inline_wire2; wire _magma_inline_wire3; -DelayUnit DelayUnit_inst0 ( +assign _magma_inline_wire0 = I_0_valid; +assign _magma_inline_wire1 = O_1_ready; +assign _magma_inline_wire2 = O_0_valid; +assign _magma_inline_wire3 = I_1_ready; +DelayUnit delay ( .CLK(CLK), .INPUT_0_data(I_1_data), .INPUT_0_ready(I_1_ready), @@ -110,13 +114,9 @@ DelayUnit DelayUnit_inst0 ( .OUTPUT_1_ready(O_0_ready), .OUTPUT_1_valid(O_0_valid) ); -assign _magma_inline_wire0 = I_0_valid; -assign _magma_inline_wire1 = O_1_ready; -assign _magma_inline_wire2 = O_0_valid; -assign _magma_inline_wire3 = I_1_ready; assert property (@(posedge CLK) _magma_inline_wire0 |-> ##3 _magma_inline_wire1); assert property (@(posedge CLK) _magma_inline_wire2 |-> ##3 _magma_inline_wire3); -assert property (@(posedge CLK) DelayUnit_inst0._magma_inline_wire4.out |-> ##3 DelayUnit_inst0._magma_inline_wire5.out); -assert property (@(posedge CLK) DelayUnit_inst0.inner_delay._magma_inline_wire6.out |-> ##3 DelayUnit_inst0.inner_delay._magma_inline_wire7.out); +assert property (@(posedge CLK) delay._magma_inline_wire4.out |-> ##3 delay._magma_inline_wire5.out); +assert property (@(posedge CLK) delay.inner_delay._magma_inline_wire6.out |-> ##3 delay.inner_delay._magma_inline_wire7.out); endmodule diff --git a/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v b/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v index 39beba646..2fa08aa31 100644 --- a/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v +++ b/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v @@ -38,13 +38,20 @@ wire _magma_inline_wire0_O; wire _magma_inline_wire1; wire _magma_inline_wire2; wire _magma_inline_wire3; +wire clk_O; +wire rst; WireClock _magma_inline_wire0 ( - .I(CLK), + .I(clk_O), .O(_magma_inline_wire0_O) ); -assign _magma_inline_wire1 = RESET; +assign _magma_inline_wire1 = rst; assign _magma_inline_wire2 = x; assign _magma_inline_wire3 = y; +WireClock clk ( + .I(CLK), + .O(clk_O) +); +assign rst = RESET; assert property (@(posedge _magma_inline_wire0_O) disable iff (! _magma_inline_wire1) _magma_inline_wire2 |-> ##1 _magma_inline_wire3); diff --git a/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v b/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v index 65422a036..450ad6be3 100644 --- a/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v +++ b/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v @@ -1,14 +1,12 @@ -module test_wire_insertion_bad_verilog( // :1:1 +// Generated by CIRCT unknown git version +module test_wire_insertion_bad_verilog( input [31:0] I, output O); - wire _magma_inline_wire0; // :5:10 - - wire _I_0 = I[0]; // :2:10 - `ifdef LOGGING_ON // :4:5 - assign _magma_inline_wire0 = _I_0; // :6:5 - $display("%x", _magma_inline_wire0); // :7:10, :8:5 - `endif LOGGING_ON // :10:5 - assign O = _I_0; // :11:5 + `ifdef LOGGING_ON + wire _magma_inline_wire0 = I[0]; + $display("%x", _magma_inline_wire0); + `endif LOGGING_ON + assign O = _magma_inline_wire0; endmodule diff --git a/tests/test_verilog/gold/test_pad.v b/tests/test_verilog/gold/test_pad.v index e4f6a402e..b66da2f13 100644 --- a/tests/test_verilog/gold/test_pad.v +++ b/tests/test_verilog/gold/test_pad.v @@ -10,29 +10,29 @@ endmodule module Top ( inout pad ); -wire PRWDWUWSWCDGH_V_inst0_C; -wire PRWDWUWSWCDGH_V_inst0_PAD; wire bit_const_0_None_out; -PRWDWUWSWCDGH_V PRWDWUWSWCDGH_V_inst0 ( - .C(PRWDWUWSWCDGH_V_inst0_C), +wire pad_C; +wire pad_PAD; +corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +PRWDWUWSWCDGH_V pad ( + .C(pad_C), .DS0(bit_const_0_None_out), .DS1(bit_const_0_None_out), .DS2(bit_const_0_None_out), .I(bit_const_0_None_out), .IE(bit_const_0_None_out), .OEN(bit_const_0_None_out), - .PAD(PRWDWUWSWCDGH_V_inst0_PAD), + .PAD(pad_PAD), .PU(bit_const_0_None_out), .PD(bit_const_0_None_out), .ST(bit_const_0_None_out), .SL(bit_const_0_None_out), .RTE(bit_const_0_None_out) ); -corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -assign PRWDWUWSWCDGH_V_inst0_PAD = pad; +assign pad_PAD = pad; endmodule diff --git a/tests/test_verilog/gold/test_rxmod_top.json b/tests/test_verilog/gold/test_rxmod_top.json index 50696bd03..ca813d76b 100644 --- a/tests/test_verilog/gold/test_rxmod_top.json +++ b/tests/test_verilog/gold/test_rxmod_top.json @@ -19,15 +19,15 @@ ["valid","Bit"] ]], "instances":{ - "RXMOD_inst0":{ + "RXMOD_inst":{ "modref":"global.RXMOD" } }, "connections":[ - ["self.CLK","RXMOD_inst0.CLK"], - ["self.RX","RXMOD_inst0.RX"], - ["self.data","RXMOD_inst0.data"], - ["self.valid","RXMOD_inst0.valid"] + ["self.CLK","RXMOD_inst.CLK"], + ["self.RX","RXMOD_inst.RX"], + ["self.data","RXMOD_inst.data"], + ["self.valid","RXMOD_inst.valid"] ] } } diff --git a/tests/test_verilog/gold/top-declare-coreir-verilog.v b/tests/test_verilog/gold/top-declare-coreir-verilog.v index 58780ec4f..829e1366d 100644 --- a/tests/test_verilog/gold/top-declare-coreir-verilog.v +++ b/tests/test_verilog/gold/top-declare-coreir-verilog.v @@ -5,24 +5,24 @@ module Top ( input CLK, input ASYNCRESET ); -wire FF_inst0_q; -wire FF_inst1_q; +wire ff0_q; +wire ff1_q; FF #( .init(0) -) FF_inst0 ( +) ff0 ( .clk(CLK), .rst(ASYNCRESET), .d(I[0]), - .q(FF_inst0_q) + .q(ff0_q) ); FF #( .init(1) -) FF_inst1 ( +) ff1 ( .clk(CLK), .rst(ASYNCRESET), .d(I[1]), - .q(FF_inst1_q) + .q(ff1_q) ); -assign O = {FF_inst1_q,FF_inst0_q}; +assign O = {ff1_q,ff0_q}; endmodule diff --git a/tests/test_verilog/gold/top-declare-coreir.json b/tests/test_verilog/gold/top-declare-coreir.json index 60cf73d8c..37349e172 100644 --- a/tests/test_verilog/gold/top-declare-coreir.json +++ b/tests/test_verilog/gold/top-declare-coreir.json @@ -19,24 +19,24 @@ ["ASYNCRESET",["Named","coreir.arstIn"]] ]], "instances":{ - "FF_inst0":{ + "ff0":{ "modref":"global.FF", "modargs":{"init":["Int",0]} }, - "FF_inst1":{ + "ff1":{ "modref":"global.FF", "modargs":{"init":["Int",1]} } }, "connections":[ - ["self.CLK","FF_inst0.clk"], - ["self.I.0","FF_inst0.d"], - ["self.O.0","FF_inst0.q"], - ["self.ASYNCRESET","FF_inst0.rst"], - ["self.CLK","FF_inst1.clk"], - ["self.I.1","FF_inst1.d"], - ["self.O.1","FF_inst1.q"], - ["self.ASYNCRESET","FF_inst1.rst"] + ["self.CLK","ff0.clk"], + ["self.I.0","ff0.d"], + ["self.O.0","ff0.q"], + ["self.ASYNCRESET","ff0.rst"], + ["self.CLK","ff1.clk"], + ["self.I.1","ff1.d"], + ["self.O.1","ff1.q"], + ["self.ASYNCRESET","ff1.rst"] ] } } diff --git a/tests/test_verilog/gold/top-declare-verilog.v b/tests/test_verilog/gold/top-declare-verilog.v index a1a45f2d4..b3fd203cb 100644 --- a/tests/test_verilog/gold/top-declare-verilog.v +++ b/tests/test_verilog/gold/top-declare-verilog.v @@ -1,8 +1,8 @@ module Top (input [1:0] I, output [1:0] O, input CLK, input ASYNCRESET); -wire FF_inst0_q; -wire FF_inst1_q; -FF #(.init(0)) FF_inst0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(FF_inst0_q)); -FF #(.init(1)) FF_inst1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(FF_inst1_q)); -assign O = {FF_inst1_q,FF_inst0_q}; +wire ff0_q; +wire ff1_q; +FF #(.init(0)) ff0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(ff0_q)); +FF #(.init(1)) ff1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(ff1_q)); +assign O = {ff1_q,ff0_q}; endmodule diff --git a/tests/test_verilog/gold/top-define-coreir-verilog.json b/tests/test_verilog/gold/top-define-coreir-verilog.json index 666561022..82f5596a0 100644 --- a/tests/test_verilog/gold/top-define-coreir-verilog.json +++ b/tests/test_verilog/gold/top-define-coreir-verilog.json @@ -20,24 +20,24 @@ ["ASYNCRESET",["Named","coreir.arstIn"]] ]], "instances":{ - "FF_inst0":{ + "ff0":{ "modref":"global.FF", "modargs":{"init":["Int",0]} }, - "FF_inst1":{ + "ff1":{ "modref":"global.FF", "modargs":{"init":["Int",1]} } }, "connections":[ - ["self.CLK","FF_inst0.clk"], - ["self.I.0","FF_inst0.d"], - ["self.O.0","FF_inst0.q"], - ["self.ASYNCRESET","FF_inst0.rst"], - ["self.CLK","FF_inst1.clk"], - ["self.I.1","FF_inst1.d"], - ["self.O.1","FF_inst1.q"], - ["self.ASYNCRESET","FF_inst1.rst"] + ["self.CLK","ff0.clk"], + ["self.I.0","ff0.d"], + ["self.O.0","ff0.q"], + ["self.ASYNCRESET","ff0.rst"], + ["self.CLK","ff1.clk"], + ["self.I.1","ff1.d"], + ["self.O.1","ff1.q"], + ["self.ASYNCRESET","ff1.rst"] ] } } diff --git a/tests/test_verilog/gold/top-define-coreir-verilog.v b/tests/test_verilog/gold/top-define-coreir-verilog.v index 8ec930410..9927f702e 100644 --- a/tests/test_verilog/gold/top-define-coreir-verilog.v +++ b/tests/test_verilog/gold/top-define-coreir-verilog.v @@ -18,24 +18,24 @@ module Top ( input CLK, input ASYNCRESET ); -wire FF_inst0_q; -wire FF_inst1_q; +wire ff0_q; +wire ff1_q; FF #( .init(0) -) FF_inst0 ( +) ff0 ( .clk(CLK), .rst(ASYNCRESET), .d(I[0]), - .q(FF_inst0_q) + .q(ff0_q) ); FF #( .init(1) -) FF_inst1 ( +) ff1 ( .clk(CLK), .rst(ASYNCRESET), .d(I[1]), - .q(FF_inst1_q) + .q(ff1_q) ); -assign O = {FF_inst1_q,FF_inst0_q}; +assign O = {ff1_q,ff0_q}; endmodule diff --git a/tests/test_verilog/gold/top-define-coreir.json b/tests/test_verilog/gold/top-define-coreir.json index 666561022..82f5596a0 100644 --- a/tests/test_verilog/gold/top-define-coreir.json +++ b/tests/test_verilog/gold/top-define-coreir.json @@ -20,24 +20,24 @@ ["ASYNCRESET",["Named","coreir.arstIn"]] ]], "instances":{ - "FF_inst0":{ + "ff0":{ "modref":"global.FF", "modargs":{"init":["Int",0]} }, - "FF_inst1":{ + "ff1":{ "modref":"global.FF", "modargs":{"init":["Int",1]} } }, "connections":[ - ["self.CLK","FF_inst0.clk"], - ["self.I.0","FF_inst0.d"], - ["self.O.0","FF_inst0.q"], - ["self.ASYNCRESET","FF_inst0.rst"], - ["self.CLK","FF_inst1.clk"], - ["self.I.1","FF_inst1.d"], - ["self.O.1","FF_inst1.q"], - ["self.ASYNCRESET","FF_inst1.rst"] + ["self.CLK","ff0.clk"], + ["self.I.0","ff0.d"], + ["self.O.0","ff0.q"], + ["self.ASYNCRESET","ff0.rst"], + ["self.CLK","ff1.clk"], + ["self.I.1","ff1.d"], + ["self.O.1","ff1.q"], + ["self.ASYNCRESET","ff1.rst"] ] } } diff --git a/tests/test_verilog/gold/top-define-verilog.v b/tests/test_verilog/gold/top-define-verilog.v index 6f149ccf2..7711cc225 100644 --- a/tests/test_verilog/gold/top-define-verilog.v +++ b/tests/test_verilog/gold/top-define-verilog.v @@ -13,10 +13,10 @@ end assign q = ff; endmodule module Top (input [1:0] I, output [1:0] O, input CLK, input ASYNCRESET); -wire FF_inst0_q; -wire FF_inst1_q; -FF #(.init(0)) FF_inst0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(FF_inst0_q)); -FF #(.init(1)) FF_inst1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(FF_inst1_q)); -assign O = {FF_inst1_q,FF_inst0_q}; +wire ff0_q; +wire ff1_q; +FF #(.init(0)) ff0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(ff0_q)); +FF #(.init(1)) ff1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(ff1_q)); +assign O = {ff1_q,ff0_q}; endmodule diff --git a/tests/test_wire/gold/arg1.v b/tests/test_wire/gold/arg1.v index 6e284cc40..e822d65af 100644 --- a/tests/test_wire/gold/arg1.v +++ b/tests/test_wire/gold/arg1.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire Buf_inst0_O; -Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); -assign O = Buf_inst0_O; +wire buf_O; +Buf buf (.I(I), .O(buf_O)); +assign O = buf_O; endmodule diff --git a/tests/test_wire/gold/arg2.v b/tests/test_wire/gold/arg2.v index 313319687..d60c51b3d 100644 --- a/tests/test_wire/gold/arg2.v +++ b/tests/test_wire/gold/arg2.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire a_O; +And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/array1.v b/tests/test_wire/gold/array1.v index 3d7d9c6e9..a70b46989 100644 --- a/tests/test_wire/gold/array1.v +++ b/tests/test_wire/gold/array1.v @@ -1,6 +1,6 @@ module main (output O); -wire AndN2_inst0_O; -AndN2 AndN2_inst0 (.I(2'd2'), .O(AndN2_inst0_O)); -assign O = AndN2_inst0_O; +wire a_O; +AndN2 a (.I(2'd2'), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/array2.v b/tests/test_wire/gold/array2.v index c5c2c43e3..580c8faab 100644 --- a/tests/test_wire/gold/array2.v +++ b/tests/test_wire/gold/array2.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire AndN2_inst0_O; -AndN2 AndN2_inst0 (.I({1'b1,I}), .O(AndN2_inst0_O)); -assign O = AndN2_inst0_O; +wire a_O; +AndN2 a (.I({1'b1,I}), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/array3.v b/tests/test_wire/gold/array3.v index 39561f7c1..883a26712 100644 --- a/tests/test_wire/gold/array3.v +++ b/tests/test_wire/gold/array3.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire AndN2_inst0_O; -AndN2 AndN2_inst0 (.I(I), .O(AndN2_inst0_O)); -assign O = AndN2_inst0_O; +wire a_O; +AndN2 a (.I(I), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/call1.v b/tests/test_wire/gold/call1.v index f0fc76a4f..1d3827732 100644 --- a/tests/test_wire/gold/call1.v +++ b/tests/test_wire/gold/call1.v @@ -1,6 +1,6 @@ module main (input I0, input I1, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire a_O; +And2 a (.I0(I0), .I1(I1), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/call2.v b/tests/test_wire/gold/call2.v index 39561f7c1..883a26712 100644 --- a/tests/test_wire/gold/call2.v +++ b/tests/test_wire/gold/call2.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire AndN2_inst0_O; -AndN2 AndN2_inst0 (.I(I), .O(AndN2_inst0_O)); -assign O = AndN2_inst0_O; +wire a_O; +AndN2 a (.I(I), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/compose.v b/tests/test_wire/gold/compose.v index f7ea820c8..55e337026 100644 --- a/tests/test_wire/gold/compose.v +++ b/tests/test_wire/gold/compose.v @@ -1,8 +1,8 @@ module main (input I, output O); -wire Buf_inst0_O; -wire Buf_inst1_O; -Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); -Buf Buf_inst1 (.I(Buf_inst0_O), .O(Buf_inst1_O)); -assign O = Buf_inst1_O; +wire buf1_O; +wire buf2_O; +Buf buf1 (.I(I), .O(buf1_O)); +Buf buf2 (.I(buf1_O), .O(buf2_O)); +assign O = buf2_O; endmodule diff --git a/tests/test_wire/gold/const0.v b/tests/test_wire/gold/const0.v index 2cee40ff4..5fc945e12 100644 --- a/tests/test_wire/gold/const0.v +++ b/tests/test_wire/gold/const0.v @@ -10,17 +10,17 @@ endmodule module main ( output O ); -wire Buf_inst0_O; wire bit_const_0_None_out; -Buf Buf_inst0 ( - .I(bit_const_0_None_out), - .O(Buf_inst0_O) -); +wire buf_O; corebit_const #( .value(1'b0) ) bit_const_0_None ( .out(bit_const_0_None_out) ); -assign O = Buf_inst0_O; +Buf buf ( + .I(bit_const_0_None_out), + .O(buf_O) +); +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const1.v b/tests/test_wire/gold/const1.v index e2620020e..684e4acb8 100644 --- a/tests/test_wire/gold/const1.v +++ b/tests/test_wire/gold/const1.v @@ -10,17 +10,17 @@ endmodule module main ( output O ); -wire Buf_inst0_O; wire bit_const_1_None_out; -Buf Buf_inst0 ( - .I(bit_const_1_None_out), - .O(Buf_inst0_O) -); +wire buf_O; corebit_const #( .value(1'b1) ) bit_const_1_None ( .out(bit_const_1_None_out) ); -assign O = Buf_inst0_O; +Buf buf ( + .I(bit_const_1_None_out), + .O(buf_O) +); +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_Bits_1.v b/tests/test_wire/gold/const_bits_Bits_1.v index 43529ec03..834a0d74b 100644 --- a/tests/test_wire/gold/const_bits_Bits_1.v +++ b/tests/test_wire/gold/const_bits_Bits_1.v @@ -11,11 +11,11 @@ endmodule module main ( output [0:0] O ); -wire [0:0] Buf_inst0_O; +wire [0:0] buf_O; wire [0:0] const_1_1_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_1_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(1'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_1 ( .out(const_1_1_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_Bits_2.v b/tests/test_wire/gold/const_bits_Bits_2.v index 3d20c257d..2a674cbbc 100644 --- a/tests/test_wire/gold/const_bits_Bits_2.v +++ b/tests/test_wire/gold/const_bits_Bits_2.v @@ -11,11 +11,11 @@ endmodule module main ( output [1:0] O ); -wire [1:0] Buf_inst0_O; +wire [1:0] buf_O; wire [1:0] const_1_2_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_2_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(2'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_2 ( .out(const_1_2_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_Bits_3.v b/tests/test_wire/gold/const_bits_Bits_3.v index 58d89acdc..553febf62 100644 --- a/tests/test_wire/gold/const_bits_Bits_3.v +++ b/tests/test_wire/gold/const_bits_Bits_3.v @@ -11,11 +11,11 @@ endmodule module main ( output [2:0] O ); -wire [2:0] Buf_inst0_O; +wire [2:0] buf_O; wire [2:0] const_1_3_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_3_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(3'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_3 ( .out(const_1_3_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_SInt_1.v b/tests/test_wire/gold/const_bits_SInt_1.v index 43529ec03..834a0d74b 100644 --- a/tests/test_wire/gold/const_bits_SInt_1.v +++ b/tests/test_wire/gold/const_bits_SInt_1.v @@ -11,11 +11,11 @@ endmodule module main ( output [0:0] O ); -wire [0:0] Buf_inst0_O; +wire [0:0] buf_O; wire [0:0] const_1_1_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_1_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(1'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_1 ( .out(const_1_1_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_SInt_2.v b/tests/test_wire/gold/const_bits_SInt_2.v index 3d20c257d..2a674cbbc 100644 --- a/tests/test_wire/gold/const_bits_SInt_2.v +++ b/tests/test_wire/gold/const_bits_SInt_2.v @@ -11,11 +11,11 @@ endmodule module main ( output [1:0] O ); -wire [1:0] Buf_inst0_O; +wire [1:0] buf_O; wire [1:0] const_1_2_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_2_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(2'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_2 ( .out(const_1_2_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_SInt_3.v b/tests/test_wire/gold/const_bits_SInt_3.v index 58d89acdc..553febf62 100644 --- a/tests/test_wire/gold/const_bits_SInt_3.v +++ b/tests/test_wire/gold/const_bits_SInt_3.v @@ -11,11 +11,11 @@ endmodule module main ( output [2:0] O ); -wire [2:0] Buf_inst0_O; +wire [2:0] buf_O; wire [2:0] const_1_3_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_3_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(3'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_3 ( .out(const_1_3_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_UInt_1.v b/tests/test_wire/gold/const_bits_UInt_1.v index 43529ec03..834a0d74b 100644 --- a/tests/test_wire/gold/const_bits_UInt_1.v +++ b/tests/test_wire/gold/const_bits_UInt_1.v @@ -11,11 +11,11 @@ endmodule module main ( output [0:0] O ); -wire [0:0] Buf_inst0_O; +wire [0:0] buf_O; wire [0:0] const_1_1_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_1_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(1'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_1 ( .out(const_1_1_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_UInt_2.v b/tests/test_wire/gold/const_bits_UInt_2.v index 3d20c257d..2a674cbbc 100644 --- a/tests/test_wire/gold/const_bits_UInt_2.v +++ b/tests/test_wire/gold/const_bits_UInt_2.v @@ -11,11 +11,11 @@ endmodule module main ( output [1:0] O ); -wire [1:0] Buf_inst0_O; +wire [1:0] buf_O; wire [1:0] const_1_2_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_2_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(2'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_2 ( .out(const_1_2_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/const_bits_UInt_3.v b/tests/test_wire/gold/const_bits_UInt_3.v index 58d89acdc..553febf62 100644 --- a/tests/test_wire/gold/const_bits_UInt_3.v +++ b/tests/test_wire/gold/const_bits_UInt_3.v @@ -11,11 +11,11 @@ endmodule module main ( output [2:0] O ); -wire [2:0] Buf_inst0_O; +wire [2:0] buf_O; wire [2:0] const_1_3_out; -Buf Buf_inst0 ( +Buf buf ( .I(const_1_3_out), - .O(Buf_inst0_O) + .O(buf_O) ); coreir_const #( .value(3'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_3 ( .out(const_1_3_out) ); -assign O = Buf_inst0_O; +assign O = \buf _O; endmodule diff --git a/tests/test_wire/gold/flip.v b/tests/test_wire/gold/flip.v index d6d13c39b..d3656aafc 100644 --- a/tests/test_wire/gold/flip.v +++ b/tests/test_wire/gold/flip.v @@ -1,6 +1,6 @@ module main (output O); -wire Buf_inst0_O; -Buf Buf_inst0 (.I(1'b1), .O(Buf_inst0_O)); -assign O = Buf_inst0_O; +wire buf_O; +Buf buf (.I(1'b1), .O(buf_O)); +assign O = buf_O; endmodule diff --git a/tests/test_wire/gold/named1.v b/tests/test_wire/gold/named1.v index 6e284cc40..e822d65af 100644 --- a/tests/test_wire/gold/named1.v +++ b/tests/test_wire/gold/named1.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire Buf_inst0_O; -Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); -assign O = Buf_inst0_O; +wire buf_O; +Buf buf (.I(I), .O(buf_O)); +assign O = buf_O; endmodule diff --git a/tests/test_wire/gold/named2a.v b/tests/test_wire/gold/named2a.v index 313319687..d60c51b3d 100644 --- a/tests/test_wire/gold/named2a.v +++ b/tests/test_wire/gold/named2a.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire a_O; +And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/named2b.v b/tests/test_wire/gold/named2b.v index 313319687..d60c51b3d 100644 --- a/tests/test_wire/gold/named2b.v +++ b/tests/test_wire/gold/named2b.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire a_O; +And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/named2c.v b/tests/test_wire/gold/named2c.v index 313319687..d60c51b3d 100644 --- a/tests/test_wire/gold/named2c.v +++ b/tests/test_wire/gold/named2c.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire And2_inst0_O; -And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); -assign O = And2_inst0_O; +wire a_O; +And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); +assign O = a_O; endmodule diff --git a/tests/test_wire/gold/pos.v b/tests/test_wire/gold/pos.v index 6e284cc40..e822d65af 100644 --- a/tests/test_wire/gold/pos.v +++ b/tests/test_wire/gold/pos.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire Buf_inst0_O; -Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); -assign O = Buf_inst0_O; +wire buf_O; +Buf buf (.I(I), .O(buf_O)); +assign O = buf_O; endmodule From 6f859d1b98a3df085c43370714837b9297a52d5c Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 18 Nov 2022 20:38:16 -0800 Subject: [PATCH 02/61] Remove extra line --- magma/circuit.py | 1 - 1 file changed, 1 deletion(-) diff --git a/magma/circuit.py b/magma/circuit.py index 93310d7db..069e4450d 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -270,7 +270,6 @@ def __new__(metacls, name, bases, dct): cls._context_.place_instances(cls) _setup_interface(cls) cls._context_.finalize(cls) - pop_definition_context(use_staged_logger=True) return cls From 8ecac9ee2fdf88741a86832cd55d4f57a6aa0d04 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 21 Nov 2022 14:08:48 -0800 Subject: [PATCH 03/61] Update smart bits tests --- magma/circuit.py | 6 ++- magma/interface.py | 14 ++---- magma/smart/eval.py | 4 +- magma/smart/smart_bits.py | 17 +++++++ tests/test_smart/test_smart_bits.py | 78 ++++++++++++++++------------- 5 files changed, 73 insertions(+), 46 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 069e4450d..24aac5d13 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -37,6 +37,7 @@ ) from magma.find_unconnected_ports import find_and_log_unconnected_ports from magma.logging import root_logger, capture_logs +from magma.protocol_type import MagmaProtocol from magma.ref import TempNamedRef, AnonRef from magma.t import In, Type from magma.view import PortView @@ -207,10 +208,13 @@ def _get_intermediate_values(value): def _infer_names(dct): """Try to infer value/inst names from metaclass dct""" for key, value in dct.items(): + if isinstance(value, MagmaProtocol): + print(key, value) + value = value._get_magma_value_() if isinstance(value, Type): if isinstance(value.name, AnonRef): value.name = TempNamedRef(key, value) - if isinstance(type(value), CircuitKind) and not value.name: + elif isinstance(type(value), CircuitKind) and not value.name: value.name = key diff --git a/magma/interface.py b/magma/interface.py index 0c7abf8cb..d14bc8f0f 100644 --- a/magma/interface.py +++ b/magma/interface.py @@ -114,6 +114,8 @@ def _make_wires(value, wired): return "".join(_make_wires(v, wired) for v, _ in value.connection_iter()) driver = value.value() + if (driver, value) in wired: + return "" while driver is not None and driver.is_driven_anon_temporary(): driver = driver.value() if driver is None: @@ -121,15 +123,9 @@ def _make_wires(value, wired): if driver.has_children() and driver.name.anon(): return "".join(_make_wires(v, wired) for v, _ in value.connection_iter()) - s = "" - while driver is not None: - if (driver, value) in wired: - break - s += _make_wire_str(driver, value, wired) - if not driver.driven(): - break - value = driver - driver = driver.value() + s = _make_wire_str(driver, value, wired) + if driver.driven(): + s += _make_wires(driver, wired) return s diff --git a/magma/smart/eval.py b/magma/smart/eval.py index 64ad6abaa..11d82882d 100644 --- a/magma/smart/eval.py +++ b/magma/smart/eval.py @@ -404,4 +404,6 @@ def evaluate_assignment(lhs: SmartBits, rhs: SmartExpr) -> SmartBits: root = _insert_signednesses(root, widths, signednesses) root = _push_down_extensions(root, widths, signednesses) result = SmartBits.from_bits(_evaluate(root)) - return _force_width(result, len(lhs)) + result = _force_width(result, len(lhs)) + rhs.magma_value = result + return result diff --git a/magma/smart/smart_bits.py b/magma/smart/smart_bits.py index 1217c6cdd..bcecfc13b 100644 --- a/magma/smart/smart_bits.py +++ b/magma/smart/smart_bits.py @@ -19,6 +19,22 @@ class SmartExprMeta(MagmaProtocolMeta): class SmartExpr(MagmaProtocol, metaclass=SmartExprMeta): __hash__ = object.__hash__ + def __init__(self): + self._magma_value = None + + def _get_magma_value_(self): + if not self._magma_value: + raise Exception("Must evaluate SmartExpr to get magma value") + return self._magma_value + + @property + def magma_value(self): + return self._magma_value + + @magma_value.setter + def magma_value(self, x): + self._magma_value = x + @property @abc.abstractmethod def args(self): @@ -143,6 +159,7 @@ def sext(self, width) -> 'SmartExtendOp': class SmartOp(SmartExpr, metaclass=SmartExprMeta): def __init__(self, op, *args): + super().__init__() self._op = op self._args = args diff --git a/tests/test_smart/test_smart_bits.py b/tests/test_smart/test_smart_bits.py index e7a7ce044..a603191d5 100644 --- a/tests/test_smart/test_smart_bits.py +++ b/tests/test_smart/test_smart_bits.py @@ -59,10 +59,9 @@ class _Test(m.Circuit): O1=m.Out(m.smart.SmartBits[8]), O2=m.Out(m.smart.SmartBits[12]), O3=m.Out(m.smart.SmartBits[16])) - val = op(io.I0, io.I1) - io.O1 @= val - io.O2 @= val - io.O3 @= val + io.O1 @= op(io.I0, io.I1) + io.O2 @= op(io.I0, io.I1) + io.O3 @= op(io.I0, io.I1) class _Gold(m.Circuit): name = "test_binop" @@ -73,9 +72,8 @@ class _Gold(m.Circuit): O2=m.Out(m.UInt[12]), O3=m.Out(m.UInt[16])) O1 = m.UInt[8]() - O1 @= op(m.zext_to(io.I0, 12), io.I1)[:8] - O1[0] # force elaboration for repr test - io.O1 @= O1 + io.O1 @= op(m.zext_to(io.I0, 12), io.I1)[:8] + io.O1._resolve_bulk_wire() # force elaboration for repr test io.O2 @= op(m.zext_to(io.I0, 12), io.I1) io.O3 @= op(m.zext_to(io.I0, 16), m.zext_to(io.I1, 16)) @@ -121,9 +119,10 @@ class _Test(m.Circuit): I1=m.In(m.smart.SmartBits[4]), O1=m.Out(m.smart.SmartBits[8]), O2=m.Out(m.smart.SmartBits[16])) - val = io.I0 << io.I1 - io.O1 @= val - io.O2 @= val + io.O1 @= io.I0 << io.I1 + O2 = m.smart.SmartBits[16]() + O2 @= io.I0 << io.I1 + io.O2 @= O2 class _Gold(m.Circuit): name = "test_lshift" @@ -133,7 +132,7 @@ class _Gold(m.Circuit): O1=m.Out(m.UInt[8]), O2=m.Out(m.UInt[16])) io.O1 @= io.I0 << m.zext_to(io.I1, 8) - O2 = m.UInt[16]() + O2 = m.Bits[16]() O2 @= m.zext_to(io.I0 << m.zext_to(io.I1, 8), 16) io.O2 @= O2 @@ -151,10 +150,13 @@ class _Test(m.Circuit): O1=m.Out(m.smart.SmartBits[4]), O2=m.Out(m.smart.SmartBits[8]), O3=m.Out(m.smart.SmartBits[16])) - val = io.I0 >> io.I1 - io.O1 @= val - io.O2 @= val - io.O3 @= val + O1 = m.smart.SmartBits[4]() + O1 @= io.I0 >> io.I1 + io.O1 @= O1 + io.O2 @= io.I0 >> io.I1 + O3 = m.smart.SmartBits[16]() + O3 @= io.I0 >> io.I1 + io.O3 @= O3 class _Gold(m.Circuit): name = "test_rshift" @@ -164,12 +166,12 @@ class _Gold(m.Circuit): O1=m.Out(m.UInt[4]), O2=m.Out(m.UInt[8]), O3=m.Out(m.UInt[16])) - O1 = m.UInt[4]() + O1 = m.Bits[4]() O1 @= (io.I0 >> m.zext_to(io.I1, 8))[:4] O1[0] # force elaboration for repr test io.O1 @= O1 io.O2 @= m.zext_to(io.I0 >> m.zext_to(io.I1, 8), 8) - O3 = m.UInt[16]() + O3 = m.Bits[16]() O3 @= m.zext_to(io.I0 >> m.zext_to(io.I1, 8), 16) io.O3 @= O3 @@ -187,9 +189,12 @@ class _Test(m.Circuit): I2=m.In(m.smart.SmartBits[10]), O1=m.Out(m.smart.SmartBits[4]), O2=m.Out(m.smart.SmartBits[16])) - val = m.smart.concat(io.I0 + io.I1, io.I2) - io.O1 @= val - io.O2 @= val + O1 = m.smart.SmartBits[4]() + O1 @= m.smart.concat(io.I0 + io.I1, io.I2) + io.O1 @= O1 + O2 = m.smart.SmartBits[16]() + O2 @= m.smart.concat(io.I0 + io.I1, io.I2) + io.O2 @= O2 class _Gold(m.Circuit): name = "test_concat" @@ -199,10 +204,10 @@ class _Gold(m.Circuit): I2=m.In(m.UInt[10]), O1=m.Out(m.UInt[4]), O2=m.Out(m.UInt[16])) - O1 = m.UInt[4]() + O1 = m.Bits[4]() O1 @= m.concat(io.I0 + m.zext_to(io.I1, 8), io.I2)[:4] io.O1 @= O1 - O2 = m.UInt[16]() + O2 = m.Bits[16]() O2 @= m.concat(io.I0 + m.zext_to(io.I1, 8), io.I2)[:16] io.O2 @= O2 @@ -220,8 +225,12 @@ class _Test(m.Circuit): O1=m.Out(m.smart.SmartBits[24]), O2=m.Out(m.smart.SmartBits[6]), ) - io.O1 @= m.smart.repeat(io.I0, 3) - io.O2 @= m.smart.repeat(io.I1[0], 6) + O1 = m.smart.SmartBits[24]() + O1 @= m.smart.repeat(io.I0, 3) + io.O1 @= O1 + O2 = m.smart.SmartBits[6]() + O2 @= m.smart.repeat(io.I1[0], 6) + io.O2 @= O2 class _Gold(m.Circuit): name = "test_repeat" @@ -231,9 +240,9 @@ class _Gold(m.Circuit): O1=m.Out(m.UInt[24]), O2=m.Out(m.UInt[6]), ) - O1 = m.UInt[24]() # force elaboration for repr test + O1 = m.Bits[24]() # force elaboration for repr test O1 @= m.as_bits(m.repeat(io.I0, 3)) - O2 = m.UInt[6]() # force elaboration for repr test + O2 = m.Bits[6]() # force elaboration for repr test O2 @= m.repeat(io.I1[0], 6) io.O1 @= O1 io.O2 @= O2 @@ -252,9 +261,8 @@ class _Test(m.Circuit): I0=m.In(m.smart.SmartBits[8]), O1=m.Out(m.smart.SmartBits[4]), O2=m.Out(m.smart.SmartBits[16])) - val = op(io.I0) - io.O1 @= val - io.O2 @= val + io.O1 @= op(io.I0) + io.O2 @= op(io.I0) class _Gold(m.Circuit): name = "test_unary" @@ -262,10 +270,8 @@ class _Gold(m.Circuit): I0=m.In(m.UInt[8]), O1=m.Out(m.UInt[4]), O2=m.Out(m.UInt[16])) - O1 = m.UInt[4]() - O1 @= op(io.I0)[:4] - O1[0] # force elaboration for repr test - io.O1 @= O1 + io.O1 @= op(io.I0)[:4] + io.O1[0] # force elaboration for repr test io.O2 @= op(m.zext_to(io.I0, 16)) return _Test, _Gold @@ -533,7 +539,9 @@ class _Test(m.Circuit): S=m.In(m.smart.SmartBits[8]), O0=m.Out(m.smart.SmartBits[16]), ) - io.O0 @= m.smart.mux([io.I0, io.I1], io.S) + O0 = m.smart.SmartBits[16]() + O0 @= m.smart.mux([io.I0, io.I1], io.S) + io.O0 @= O0 class _Gold(m.Circuit): name = "test_mux" @@ -543,7 +551,7 @@ class _Gold(m.Circuit): S=m.In(m.UInt[8]), O0=m.Out(m.UInt[16]), ) - O0 = m.UInt[16]() # force elaboration for repr test + O0 = m.Bits[16]() # force elaboration for repr test O0 @= m.zext_to(m.mux([m.zext_to(io.I0, 12), io.I1], io.S[0]), 16) io.O0 @= O0 From a561b98fe48ed5f4ab8725c5ee86f90e222ae73c Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 21 Nov 2022 14:51:08 -0800 Subject: [PATCH 04/61] Update tests --- magma/backend/coreir/insert_coreir_wires.py | 7 ++-- tests/test_type/gold/test_array2_2d_tuple.v | 34 ++++++++++++++----- .../gold/test_insert_wrap_casts_temporary.v | 27 +++++++++++---- tests/test_type/test_array2.py | 18 +++++----- tests/test_type/test_clock.py | 2 +- tests/test_wire/test_check_wiring_context.py | 12 +++---- 6 files changed, 69 insertions(+), 31 deletions(-) diff --git a/magma/backend/coreir/insert_coreir_wires.py b/magma/backend/coreir/insert_coreir_wires.py index 641532808..bd075f8ce 100644 --- a/magma/backend/coreir/insert_coreir_wires.py +++ b/magma/backend/coreir/insert_coreir_wires.py @@ -62,8 +62,11 @@ def _make_wire(self, driver, value, definition): # Could be already wired for fanout cases if not wire_input.driven(): wire_input @= driver - if (isinstance(value, _ClockType) and - not isinstance(wire_output, type(value))): + if ( + not isinstance(wire_output, type(value)) and + isinstance(value, _ClockType) or + isinstance(wire_output, _ClockType) + ): # This mean it was cast by the user (e.g. m.clock(value)), so we # need to "recast" the wire output wire_output = convertbit(wire_output, type(value)) diff --git a/tests/test_type/gold/test_array2_2d_tuple.v b/tests/test_type/gold/test_array2_2d_tuple.v index 9dbbad017..4bc66b2ad 100644 --- a/tests/test_type/gold/test_array2_2d_tuple.v +++ b/tests/test_type/gold/test_array2_2d_tuple.v @@ -1,16 +1,34 @@ +module coreir_wire #( + parameter width = 1 +) ( + input [width-1:0] in, + output [width-1:0] out +); + assign out = in; +endmodule + module Foo ( input [3:0] I_c_0_a [3:0], input [3:0] I_c_1_a [3:0], output [3:0] O_c_0_a [3:0], output [3:0] O_c_1_a [3:0] ); -assign O_c_0_a[3] = I_c_1_a[0]; -assign O_c_0_a[2] = I_c_1_a[1]; -assign O_c_0_a[1] = I_c_1_a[2]; -assign O_c_0_a[0] = I_c_1_a[3]; -assign O_c_1_a[3] = I_c_0_a[0]; -assign O_c_1_a[2] = I_c_0_a[1]; -assign O_c_1_a[1] = I_c_0_a[2]; -assign O_c_1_a[0] = I_c_0_a[3]; +wire [31:0] temp_out; +wire [31:0] temp_in; +assign temp_in = {I_c_0_a[0],I_c_0_a[1],I_c_0_a[2],I_c_0_a[3],I_c_1_a[0],I_c_1_a[1],I_c_1_a[2],I_c_1_a[3]}; +coreir_wire #( + .width(32) +) temp ( + .in(temp_in), + .out(temp_out) +); +assign O_c_0_a[3] = {temp_out[15],temp_out[14],temp_out[13],temp_out[12]}; +assign O_c_0_a[2] = {temp_out[11],temp_out[10],temp_out[9],temp_out[8]}; +assign O_c_0_a[1] = {temp_out[7],temp_out[6],temp_out[5],temp_out[4]}; +assign O_c_0_a[0] = {temp_out[3],temp_out[2],temp_out[1],temp_out[0]}; +assign O_c_1_a[3] = {temp_out[31],temp_out[30],temp_out[29],temp_out[28]}; +assign O_c_1_a[2] = {temp_out[27],temp_out[26],temp_out[25],temp_out[24]}; +assign O_c_1_a[1] = {temp_out[23],temp_out[22],temp_out[21],temp_out[20]}; +assign O_c_1_a[0] = {temp_out[19],temp_out[18],temp_out[17],temp_out[16]}; endmodule diff --git a/tests/test_type/gold/test_insert_wrap_casts_temporary.v b/tests/test_type/gold/test_insert_wrap_casts_temporary.v index d9a526467..1b18a183f 100644 --- a/tests/test_type/gold/test_insert_wrap_casts_temporary.v +++ b/tests/test_type/gold/test_insert_wrap_casts_temporary.v @@ -49,30 +49,45 @@ wire _magma_inline_wire0_O; wire _magma_inline_wire1_out; wire coreir_wrapInClock_inst0_out; wire coreir_wrapOutClock_inst0_out; +wire temp0_O; wire temp1_out; -Foo Foo_inst0 ( - .CLK(coreir_wrapOutClock_inst0_out) -); +wire temp2_O; +wire temp3_out; WireClock _magma_inline_wire0 ( - .I(CLK), + .I(temp2_O), .O(_magma_inline_wire0_O) ); corebit_wire _magma_inline_wire1 ( - .in(RESETN), + .in(temp3_out), .out(_magma_inline_wire1_out) ); coreir_wrap coreir_wrapInClock_inst0 ( - .in(CLK), + .in(temp0_O), .out(coreir_wrapInClock_inst0_out) ); coreir_wrap coreir_wrapOutClock_inst0 ( .in(temp1_out), .out(coreir_wrapOutClock_inst0_out) ); +Foo foo0 ( + .CLK(coreir_wrapOutClock_inst0_out) +); +WireClock temp0 ( + .I(CLK), + .O(temp0_O) +); corebit_wire temp1 ( .in(coreir_wrapInClock_inst0_out), .out(temp1_out) ); +WireClock temp2 ( + .I(CLK), + .O(temp2_O) +); +corebit_wire temp3 ( + .in(RESETN), + .out(temp3_out) +); always @(posedge _magma_inline_wire0_O) disable iff (! _magma_inline_wire1_out) $display("Hello"); endmodule diff --git a/tests/test_type/test_array2.py b/tests/test_type/test_array2.py index d004ad4b3..61b478d5d 100644 --- a/tests/test_type/test_array2.py +++ b/tests/test_type/test_array2.py @@ -485,14 +485,16 @@ class Foo(m.Circuit): expected = """\ Foo = DefineCircuit("Foo", "I", Tuple(c=Array[(2, X)]), "O", Tuple(c=Array[(2, X)])) -wire(Foo.I.c[1].a[3], Foo.O.c[0].a[0]) -wire(Foo.I.c[1].a[2], Foo.O.c[0].a[1]) -wire(Foo.I.c[1].a[1], Foo.O.c[0].a[2]) -wire(Foo.I.c[1].a[0], Foo.O.c[0].a[3]) -wire(Foo.I.c[0].a[3], Foo.O.c[1].a[0]) -wire(Foo.I.c[0].a[2], Foo.O.c[1].a[1]) -wire(Foo.I.c[0].a[1], Foo.O.c[1].a[2]) -wire(Foo.I.c[0].a[0], Foo.O.c[1].a[3]) +temp = Tuple(c=Array[(2, X)])(name="temp") +wire(temp, Foo.O) +wire(Foo.I.c[1].a[3], temp.c[0].a[0]) +wire(Foo.I.c[1].a[2], temp.c[0].a[1]) +wire(Foo.I.c[1].a[1], temp.c[0].a[2]) +wire(Foo.I.c[1].a[0], temp.c[0].a[3]) +wire(Foo.I.c[0].a[3], temp.c[1].a[0]) +wire(Foo.I.c[0].a[2], temp.c[1].a[1]) +wire(Foo.I.c[0].a[1], temp.c[1].a[2]) +wire(Foo.I.c[0].a[0], temp.c[1].a[3]) EndCircuit()\ """ assert repr(Foo) == expected, repr(Foo) diff --git a/tests/test_type/test_clock.py b/tests/test_type/test_clock.py index c3ef07bf2..13286632c 100644 --- a/tests/test_type/test_clock.py +++ b/tests/test_type/test_clock.py @@ -490,4 +490,4 @@ class Bar(m.Circuit): m.compile("build/Bar", Bar) - assert caplog.messages[0] == "Foo_inst0.y.clk not driven, will attempt to automatically wire" + assert caplog.messages[0] == "foo.y.clk not driven, will attempt to automatically wire" diff --git a/tests/test_wire/test_check_wiring_context.py b/tests/test_wire/test_check_wiring_context.py index db29e7893..20dadcc21 100644 --- a/tests/test_wire/test_check_wiring_context.py +++ b/tests/test_wire/test_check_wiring_context.py @@ -43,8 +43,8 @@ class Bar(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Bar", Bar) - assert str(e.value) == ("Cannot wire Foo.x to Bar.y because they are not " - "from the same definition context") + assert str(e.value) == ("Cannot wire Foo.x to Bar._z.in because they are " + "not from the same definition context") def test_bad_temp2(caplog): @@ -61,8 +61,8 @@ class Bar(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Foo", Foo) - assert str(e.value) == ("Cannot wire Bar.x to Foo.y because they are not " - "from the same definition context") + assert str(e.value) == ("Cannot wire Bar.x to Foo.z.in because they are " + "not from the same definition context") def test_bad_portview(caplog): @@ -87,7 +87,7 @@ class Biz(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Foo", Biz) - assert str(e.value) == ("Cannot wire Bar.Foo_inst0.y to Biz.y because they " + assert str(e.value) == ("Cannot wire Bar.foo.y to Biz.y because they " "are not from the same definition context") @@ -109,7 +109,7 @@ class Baz(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Bar", Bar) - assert str(e.value) == ("Cannot wire Baz.Bar_inst0.y to Bar.Foo_inst0.x " + assert str(e.value) == ("Cannot wire Baz.bar.y to Bar.foo.x " "because they are not from the same definition " "context") From d9f3db1052457016186ac5dd833817803a99766d Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 22 Nov 2022 12:34:51 -0800 Subject: [PATCH 05/61] Improve port view logic --- magma/backend/check_wiring_context.py | 5 +++-- magma/t.py | 6 +++++- tests/test_wire/test_check_wiring_context.py | 2 +- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/magma/backend/check_wiring_context.py b/magma/backend/check_wiring_context.py index 0aa6c9b20..ec435d02a 100644 --- a/magma/backend/check_wiring_context.py +++ b/magma/backend/check_wiring_context.py @@ -21,6 +21,7 @@ def check_wiring_context(i, o): """ Ensures that i and o come from the same definition context """ + orig_i, orig_o = i, o if isinstance(o, Slice): o = o.value if isinstance(i, Slice): @@ -53,5 +54,5 @@ def check_wiring_context(i, o): o_inst.defn is i_inst.defn): return raise MagmaCompileException( - f"Cannot wire {o.debug_name} to {i.debug_name} because they are" - " not from the same definition context") + f"Cannot wire {orig_o.debug_name} to {orig_i.debug_name} because they " + "are not from the same definition context") diff --git a/magma/t.py b/magma/t.py index bf439512c..54f564f5d 100644 --- a/magma/t.py +++ b/magma/t.py @@ -3,7 +3,9 @@ from functools import lru_cache from magma.common import deprecated from magma.compatibility import IntegerTypes, StringTypes -from magma.ref import AnonRef, NamedRef, TempNamedRef, DefnRef, InstRef +from magma.ref import ( + AnonRef, NamedRef, TempNamedRef, DefnRef, InstRef, PortViewRef +) from magma.protocol_type import magma_value from magma.wire import wire @@ -98,6 +100,8 @@ def debug_name(self): elif isinstance(self.name, InstRef): inst_str = str(self.name.inst.name) + "." defn_str = str(self.name.inst.defn.name) + "." + elif isinstance(self.name, PortViewRef): + return ".".join(self.name.view.path()) return f"{defn_str}{inst_str}{str(self)}" def __le__(self, other): diff --git a/tests/test_wire/test_check_wiring_context.py b/tests/test_wire/test_check_wiring_context.py index 20dadcc21..244c6e9ee 100644 --- a/tests/test_wire/test_check_wiring_context.py +++ b/tests/test_wire/test_check_wiring_context.py @@ -87,7 +87,7 @@ class Biz(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Foo", Biz) - assert str(e.value) == ("Cannot wire Bar.foo.y to Biz.y because they " + assert str(e.value) == ("Cannot wire bar.foo.y to Biz.y because they " "are not from the same definition context") From 1cbea3a512cdf89605c48a17addd2508399d9a7e Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 22 Nov 2022 12:47:59 -0800 Subject: [PATCH 06/61] Remove debug print --- magma/circuit.py | 1 - 1 file changed, 1 deletion(-) diff --git a/magma/circuit.py b/magma/circuit.py index 24aac5d13..0ef116f9f 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -209,7 +209,6 @@ def _infer_names(dct): """Try to infer value/inst names from metaclass dct""" for key, value in dct.items(): if isinstance(value, MagmaProtocol): - print(key, value) value = value._get_magma_value_() if isinstance(value, Type): if isinstance(value.name, AnonRef): From 0ac14cec00170183e31b6c1126faf3b64c633fec Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 22 Nov 2022 16:13:05 -0800 Subject: [PATCH 07/61] WIP namer dict --- magma/circuit.py | 51 +++++++++++++++---- magma/generator.py | 4 +- magma/smart/eval.py | 6 +-- magma/smart/smart_bits.py | 39 ++++++++------ tests/gold/uniquify_equal.json | 10 ++-- .../test_circuit/gold/test_for_loop_def.json | 8 +-- tests/test_circuit/gold/test_for_loop_def.v | 8 +-- tests/test_higher/test_braid.py | 6 +-- tests/test_ir_pass.py | 22 ++++---- tests/test_symbol_table_generation.py | 2 +- 10 files changed, 95 insertions(+), 61 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 0ef116f9f..4ee7335ff 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -6,7 +6,7 @@ from functools import wraps import functools import operator -from collections import namedtuple +from collections import namedtuple, Counter import os from typing import Callable, Dict, List @@ -37,7 +37,7 @@ ) from magma.find_unconnected_ports import find_and_log_unconnected_ports from magma.logging import root_logger, capture_logs -from magma.protocol_type import MagmaProtocol +from magma.protocol_type import magma_value from magma.ref import TempNamedRef, AnonRef from magma.t import In, Type from magma.view import PortView @@ -205,23 +205,53 @@ def _get_intermediate_values(value): return values -def _infer_names(dct): - """Try to infer value/inst names from metaclass dct""" - for key, value in dct.items(): - if isinstance(value, MagmaProtocol): - value = value._get_magma_value_() +class LazyNamedValue: + pass + + +class NamerDict(dict): + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + self._inferred_name_counter = Counter() + + def _set_name(self, key, value, force=False): + if isinstance(value, LazyNamedValue): + if not magma_value(value): + if not value.name or force: + value.name = key + else: + value = magma_value(value) if isinstance(value, Type): - if isinstance(value.name, AnonRef): + if ( + isinstance(value.name, AnonRef) or + isinstance(value.name, TempNamedRef) and force + ): value.name = TempNamedRef(key, value) - elif isinstance(type(value), CircuitKind) and not value.name: + elif isinstance(type(value), CircuitKind) and ( + not value.name or force + ): value.name = key + def __setitem__(self, key, value): + if key in self and self[key] is not value: + if self._inferred_name_counter[key] == 1: + self._set_name(f"{key}_0", self[key], True) + self._set_name(f"{key}_{self._inferred_name_counter[key]}", value) + self._inferred_name_counter[key] += 1 + else: + self._set_name(key, value) + self._inferred_name_counter[key] += 1 + super().__setitem__(key, value) + + def __hash__(self): + return hash(tuple(sorted(self.items()))) + class CircuitKind(type): def __prepare__(name, bases, **kwargs): ctx = DefinitionContext(StagedPlacer(name)) push_definition_context(ctx, use_staged_logger=True) - return type.__prepare__(name, bases, **kwargs) + return NamerDict() """Metaclass for creating circuits.""" def __new__(metacls, name, bases, dct): @@ -269,7 +299,6 @@ def __new__(metacls, name, bases, dct): # Override staged context with '_context_' from namespace if # available. cls._context_ = dct.get("_context_", context) - _infer_names(dct) # do before place instances for default logic cls._context_.place_instances(cls) _setup_interface(cls) cls._context_.finalize(cls) diff --git a/magma/generator.py b/magma/generator.py index 1c7640c2b..cf4baccb5 100644 --- a/magma/generator.py +++ b/magma/generator.py @@ -3,7 +3,7 @@ import functools import weakref from .circuit import (DefineCircuitKind, Circuit, DebugCircuit, - DebugDefineCircuitKind) + DebugDefineCircuitKind, NamerDict) from . import cache_definition from magma.common import ParamDict from hwtypes import BitVector @@ -110,7 +110,7 @@ def __call__(cls, *args, **kwargs): len(args) == 3 and type(args[0]) is str and type(args[1]) is tuple - and type(args[2]) is dict + and (type(args[2]) is dict or type(args[2]) is NamerDict) and "__module__" in args[2] ) if is_base_cls: diff --git a/magma/smart/eval.py b/magma/smart/eval.py index 11d82882d..0dea98b71 100644 --- a/magma/smart/eval.py +++ b/magma/smart/eval.py @@ -403,7 +403,5 @@ def evaluate_assignment(lhs: SmartBits, rhs: SmartExpr) -> SmartBits: signednesses = _determine_result_signednesses(root) root = _insert_signednesses(root, widths, signednesses) root = _push_down_extensions(root, widths, signednesses) - result = SmartBits.from_bits(_evaluate(root)) - result = _force_width(result, len(lhs)) - rhs.magma_value = result - return result + result = SmartBits.from_bits(_evaluate(root), rhs.name) + return _force_width(result, len(lhs)) diff --git a/magma/smart/smart_bits.py b/magma/smart/smart_bits.py index bcecfc13b..06d21613b 100644 --- a/magma/smart/smart_bits.py +++ b/magma/smart/smart_bits.py @@ -6,6 +6,7 @@ from magma.bit import Bit from magma.bits import Bits, BitsMeta, SInt, reduce as bits_reduce +from magma.circuit import LazyNamedValue from magma.conversions import uint, bits, sint from magma.conversions import concat as bits_concat from magma.debug import debug_wire @@ -16,24 +17,22 @@ class SmartExprMeta(MagmaProtocolMeta): pass -class SmartExpr(MagmaProtocol, metaclass=SmartExprMeta): +class SmartExpr(MagmaProtocol, LazyNamedValue, metaclass=SmartExprMeta): __hash__ = object.__hash__ def __init__(self): - self._magma_value = None - - def _get_magma_value_(self): - if not self._magma_value: - raise Exception("Must evaluate SmartExpr to get magma value") - return self._magma_value + self._name = None @property - def magma_value(self): - return self._magma_value + def name(self): + return self._name - @magma_value.setter - def magma_value(self, x): - self._magma_value = x + @name.setter + def name(self, value): + self._name = value + + def _get_magma_value_(self): + return None @property @abc.abstractmethod @@ -412,10 +411,10 @@ def __repr__(cls): class SmartBits(SmartBitsExpr, metaclass=SmartBitsMeta): - def __init__(self, value=None): + def __init__(self, value=None, name=None): super().__init__(self) if value is None: - value = type(self)._to_magma_()() + value = type(self)._to_magma_()(name=name) self._value = value def __len__(self): @@ -454,13 +453,13 @@ def wire(self, other, debug_info): MagmaProtocol.wire(self, other, debug_info) @staticmethod - def from_bits(value): + def from_bits(value, name=None): if isinstance(value, Bit): value = bits(value) if not isinstance(value, Bits): raise TypeError(value) signed = isinstance(value, SInt) - return SmartBits[len(value), signed](value) + return SmartBits[len(value), signed](value, name=name) def __str__(self): signed = type(self)._signed_ @@ -469,6 +468,14 @@ def __str__(self): def connection_iter(self): yield from zip(self, self.trace()) + @property + def name(self): + return self._get_magma_value_().name + + @name.setter + def name(self, value): + self._get_magma_value_().name = value + SmartBit = SmartBits[1] diff --git a/tests/gold/uniquify_equal.json b/tests/gold/uniquify_equal.json index f9d39ae25..23d36ea43 100644 --- a/tests/gold/uniquify_equal.json +++ b/tests/gold/uniquify_equal.json @@ -17,17 +17,17 @@ ["O","Bit"] ]], "instances":{ - "foo_inst0":{ + "inst_0":{ "modref":"global.foo" }, - "inst":{ + "inst_1":{ "modref":"global.foo" } }, "connections":[ - ["self.I","foo_inst0.I"], - ["inst.I","foo_inst0.O"], - ["self.O","inst.O"] + ["self.I","inst_0.I"], + ["inst_1.I","inst_0.O"], + ["self.O","inst_1.O"] ] } } diff --git a/tests/test_circuit/gold/test_for_loop_def.json b/tests/test_circuit/gold/test_for_loop_def.json index 510b3618e..23454ddd0 100644 --- a/tests/test_circuit/gold/test_for_loop_def.json +++ b/tests/test_circuit/gold/test_for_loop_def.json @@ -27,7 +27,7 @@ "modref":"global.And2", "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"} }, - "and2_prev":{ + "and2_3":{ "modref":"global.And2", "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"61"} } @@ -39,9 +39,9 @@ ["self.I.1","and2_1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], ["and2_2.I0","and2_1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}], ["self.I.1","and2_2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], - ["and2_prev.I0","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}], - ["self.I.1","and2_prev.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], - ["self.O","and2_prev.O",{"filename":"tests/test_circuit/test_define.py","lineno":"70"}] + ["and2_3.I0","and2_2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"66"}], + ["self.I.1","and2_3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"67"}], + ["self.O","and2_3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"70"}] ], "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"} } diff --git a/tests/test_circuit/gold/test_for_loop_def.v b/tests/test_circuit/gold/test_for_loop_def.v index da18b2d56..8ad60292b 100644 --- a/tests/test_circuit/gold/test_for_loop_def.v +++ b/tests/test_circuit/gold/test_for_loop_def.v @@ -3,7 +3,7 @@ module main (input [1:0] I, output O); wire and2_0_O; wire and2_1_O; wire and2_2_O; -wire and2_prev_O; +wire and2_3_O; // Instanced at tests/test_circuit/test_define.py:61 // Argument I0(I[0]) wired at tests/test_circuit/test_define.py:63 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:64 @@ -22,9 +22,9 @@ And2 and2_2 (.I0(and2_1_O), .I1(I[1]), .O(and2_2_O)); // Instanced at tests/test_circuit/test_define.py:61 // Argument I0(and2_2_O) wired at tests/test_circuit/test_define.py:66 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:67 -// Argument O(and2_prev_O) wired at tests/test_circuit/test_define.py:70 -And2 and2_prev (.I0(and2_2_O), .I1(I[1]), .O(and2_prev_O)); +// Argument O(and2_3_O) wired at tests/test_circuit/test_define.py:70 +And2 and2_3 (.I0(and2_2_O), .I1(I[1]), .O(and2_3_O)); // Wired at tests/test_circuit/test_define.py:70 -assign O = and2_prev_O; +assign O = and2_3_O; endmodule diff --git a/tests/test_higher/test_braid.py b/tests/test_higher/test_braid.py index c84fdc953..7f43a7ed4 100644 --- a/tests/test_higher/test_braid.py +++ b/tests/test_higher/test_braid.py @@ -11,13 +11,13 @@ class _Top(Circuit): lut1 = And2(name='lut1') lut = braid([lut0,lut1]) - assert repr(lut) == 'AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", array([lut0.I1, lut1.I1]), "O", array([lut0.O, lut1.O]))' + assert repr(lut) == 'lut = AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", array([lut0.I1, lut1.I1]), "O", array([lut0.O, lut1.O]))' lut = braid([lut0,lut1], foldargs={'I1':'O'}) - assert repr(lut) == 'AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", lut1.O)' + assert repr(lut) == 'lut_1 = AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", lut1.O)' lut = braid([lut0,lut1], scanargs={'I1':'O'}) - assert repr(lut) == 'AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", array([lut0.O, lut1.O]))' + assert repr(lut) == 'lut_2 = AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", array([lut0.O, lut1.O]))' def test_compose(): diff --git a/tests/test_ir_pass.py b/tests/test_ir_pass.py index ed8505c2c..6087d78fd 100644 --- a/tests/test_ir_pass.py +++ b/tests/test_ir_pass.py @@ -27,17 +27,17 @@ def test_basic(): EndCircuit() _Top = DefineCircuit("_Top", "I", In(Bit), "O", Out(Bit)) -_Cell_inst0 = _Cell() -_Cell_inst1 = _Cell() -_Cell_inst2 = _Cell() -_Cell_inst3 = _Cell() -cell = _Cell() -wire(_Top.I, _Cell_inst0.I) -wire(_Cell_inst0.O, _Cell_inst1.I) -wire(_Cell_inst1.O, _Cell_inst2.I) -wire(_Cell_inst2.O, _Cell_inst3.I) -wire(_Cell_inst3.O, cell.I) -wire(cell.O, _Top.O) +cell_0 = _Cell() +cell_1 = _Cell() +cell_2 = _Cell() +cell_3 = _Cell() +cell_4 = _Cell() +wire(_Top.I, cell_0.I) +wire(cell_0.O, cell_1.I) +wire(cell_1.O, cell_2.I) +wire(cell_2.O, cell_3.I) +wire(cell_3.O, cell_4.I) +wire(cell_4.O, _Top.O) EndCircuit() """ diff --git a/tests/test_symbol_table_generation.py b/tests/test_symbol_table_generation.py index 09a7eff1b..e83d30160 100644 --- a/tests/test_symbol_table_generation.py +++ b/tests/test_symbol_table_generation.py @@ -50,7 +50,7 @@ class DFFList(m.Circuit): symbol_table = _compile("build/DFFList", DFFList) for i in range(10): - inst_name = f"SB_DFF_inst{i}" if i < 9 else "dff" + inst_name = f"dff_{i}" name = symbol_table.get_instance_name("DFFList", inst_name) assert name == (SYMBOL_TABLE_EMPTY, inst_name) instance_type = symbol_table.get_instance_type( From b226492eee227d2e21ca2c03de3615930268d88f Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 23 Nov 2022 17:46:42 -0800 Subject: [PATCH 08/61] Finish NamerDict patterng --- magma/circuit.py | 62 ++++++++++++------------ magma/smart/smart_bits.py | 3 -- tests/test_verilog/gold/bind_test.v | 6 +-- tests/test_verilog/gold/bind_uniq_test.v | 12 ++--- 4 files changed, 41 insertions(+), 42 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 4ee7335ff..61f863c26 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -10,7 +10,6 @@ import os from typing import Callable, Dict, List -import six from . import cache_definition from .common import deprecated, setattrs, OrderedIdentitySet from .interface import * @@ -212,36 +211,39 @@ class LazyNamedValue: class NamerDict(dict): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - self._inferred_name_counter = Counter() + self._inferred_names = {} - def _set_name(self, key, value, force=False): + def _set_name(self, key, value): + if isinstance(value, Type): + key = TempNamedRef(key, value) + value.name = key + + def __setitem__(self, key, value): + orig_value = value if isinstance(value, LazyNamedValue): - if not magma_value(value): - if not value.name or force: - value.name = key - else: + try: value = magma_value(value) - if isinstance(value, Type): - if ( - isinstance(value.name, AnonRef) or - isinstance(value.name, TempNamedRef) and force - ): - value.name = TempNamedRef(key, value) - elif isinstance(type(value), CircuitKind) and ( - not value.name or force + except NotImplementedError: + # SmartExpr doesn't have a magma_value + # TODO: This probably shouldn't be a protocol type then + pass + if ( + (isinstance(value, Type) and isinstance(value.name, AnonRef)) or + (isinstance(value, LazyNamedValue) and not value.name) or + (isinstance(type(value), CircuitKind) and not value.name) ): - value.name = key + values = self._inferred_names.setdefault(key, []) + if len(values) == 0: + self._set_name(key, value) + else: + if len(values) == 1: + self._set_name(f"{key}_0", values[0]) + self._set_name(f"{key}_{len(values)}", value) + values.append(value) + # TODO: Should we handle name collisions between explicitly named values + # and inferred names? - def __setitem__(self, key, value): - if key in self and self[key] is not value: - if self._inferred_name_counter[key] == 1: - self._set_name(f"{key}_0", self[key], True) - self._set_name(f"{key}_{self._inferred_name_counter[key]}", value) - self._inferred_name_counter[key] += 1 - else: - self._set_name(key, value) - self._inferred_name_counter[key] += 1 - super().__setitem__(key, value) + super().__setitem__(key, orig_value) def __hash__(self): return hash(tuple(sorted(self.items()))) @@ -255,6 +257,8 @@ def __prepare__(name, bases, **kwargs): """Metaclass for creating circuits.""" def __new__(metacls, name, bases, dct): + if isinstance(dct, NamerDict): + dct = dict(dct) # resolve to dict, no longer need name logic # Override class name if supplied (and save class name). cls_name = dct.get("_cls_name_", name) name = dct.setdefault('name', name) @@ -404,8 +408,7 @@ def inline_verilog(cls, inline_str, **kwargs): m_inline_verilog(inline_str, **kwargs) -@six.add_metaclass(CircuitKind) -class AnonymousCircuitType(object): +class AnonymousCircuitType(object, metaclass=CircuitKind): """Abstract base class for circuits""" _circuit_base_ = True @@ -740,8 +743,7 @@ def bind(cls, monitor, *args, compile_guard=None): cls.bind_modules[monitor] = (args, compile_guard) -@six.add_metaclass(DefineCircuitKind) -class Circuit(CircuitType): +class Circuit(CircuitType, metaclass=DefineCircuitKind): _circuit_base_ = True diff --git a/magma/smart/smart_bits.py b/magma/smart/smart_bits.py index 06d21613b..43819d9c7 100644 --- a/magma/smart/smart_bits.py +++ b/magma/smart/smart_bits.py @@ -31,9 +31,6 @@ def name(self): def name(self, value): self._name = value - def _get_magma_value_(self): - return None - @property @abc.abstractmethod def args(self): diff --git a/tests/test_verilog/gold/bind_test.v b/tests/test_verilog/gold/bind_test.v index 0bdda1a16..262cfaee8 100644 --- a/tests/test_verilog/gold/bind_test.v +++ b/tests/test_verilog/gold/bind_test.v @@ -77,6 +77,9 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; +bar_foo_SomeCircuit SomeCircuit_inst0 ( + .I(magma_Bits_4_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -140,9 +143,6 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); -bar_foo_SomeCircuit some_circ ( - .I(magma_Bits_4_xor_inst0_out) -); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; diff --git a/tests/test_verilog/gold/bind_uniq_test.v b/tests/test_verilog/gold/bind_uniq_test.v index 27b61373c..6da29a6d8 100644 --- a/tests/test_verilog/gold/bind_uniq_test.v +++ b/tests/test_verilog/gold/bind_uniq_test.v @@ -115,6 +115,9 @@ wire [4:0] magma_Bits_5_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_5_inst0_O; wire temp3; +bar_foo_SomeCircuit_unq1 SomeCircuit_inst0 ( + .I(magma_Bits_5_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_5_inst0_O; assign _magma_bind_wire_1 = andr_5_inst0_O; assign _magma_bind_wire_2_0 = orr_5_inst0_O; @@ -185,9 +188,6 @@ orr_5 orr_5_inst0 ( .I(in1), .O(orr_5_inst0_O) ); -bar_foo_SomeCircuit_unq1 some_circ ( - .I(magma_Bits_5_xor_inst0_out) -); assign temp3 = andr_5_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -243,6 +243,9 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; +bar_foo_SomeCircuit SomeCircuit_inst0 ( + .I(magma_Bits_4_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -313,9 +316,6 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); -bar_foo_SomeCircuit some_circ ( - .I(magma_Bits_4_xor_inst0_out) -); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; From 6c0e8c9b854242051ecd4e621a136641a004340e Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 28 Nov 2022 11:35:51 -0800 Subject: [PATCH 09/61] Add self namer logic to Generator2 --- magma/circuit.py | 3 ++- magma/generator.py | 8 +++++++- tests/test_verilog/gold/bind_test.v | 6 +++--- tests/test_verilog/gold/bind_uniq_test.v | 12 ++++++------ 4 files changed, 18 insertions(+), 11 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 61f863c26..e94f4a384 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -228,7 +228,8 @@ def __setitem__(self, key, value): # TODO: This probably shouldn't be a protocol type then pass if ( - (isinstance(value, Type) and isinstance(value.name, AnonRef)) or + (isinstance(value, Type) and hasattr(value, "name") and + isinstance(value.name, AnonRef)) or (isinstance(value, LazyNamedValue) and not value.name) or (isinstance(type(value), CircuitKind) and not value.name) ): diff --git a/magma/generator.py b/magma/generator.py index cf4baccb5..b56f6ff7e 100644 --- a/magma/generator.py +++ b/magma/generator.py @@ -70,7 +70,9 @@ def _make_key(cls, *args, **kwargs): def _make_type(cls, *args, **kwargs): - dummy = type.__new__(cls, "", (), {}) + dummy = type.__new__(cls, "", (), { + "_namer_dict": NamerDict() + }) name = cls.__name__ bases = (cls._base_cls_,) dct = cls._base_metacls_.__prepare__(name, bases) @@ -141,6 +143,10 @@ def __call__(cls, *args, **kwargs): def bind(cls, monitor): cls.bind_generators.append(monitor) + def __setattr__(cls, key, value): + cls._namer_dict[key] = value + super().__setattr__(key, value) + class _DebugGeneratorMeta(_Generator2Meta): _base_cls_ = DebugCircuit diff --git a/tests/test_verilog/gold/bind_test.v b/tests/test_verilog/gold/bind_test.v index 262cfaee8..0bdda1a16 100644 --- a/tests/test_verilog/gold/bind_test.v +++ b/tests/test_verilog/gold/bind_test.v @@ -77,9 +77,6 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; -bar_foo_SomeCircuit SomeCircuit_inst0 ( - .I(magma_Bits_4_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -143,6 +140,9 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); +bar_foo_SomeCircuit some_circ ( + .I(magma_Bits_4_xor_inst0_out) +); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; diff --git a/tests/test_verilog/gold/bind_uniq_test.v b/tests/test_verilog/gold/bind_uniq_test.v index 6da29a6d8..27b61373c 100644 --- a/tests/test_verilog/gold/bind_uniq_test.v +++ b/tests/test_verilog/gold/bind_uniq_test.v @@ -115,9 +115,6 @@ wire [4:0] magma_Bits_5_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_5_inst0_O; wire temp3; -bar_foo_SomeCircuit_unq1 SomeCircuit_inst0 ( - .I(magma_Bits_5_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_5_inst0_O; assign _magma_bind_wire_1 = andr_5_inst0_O; assign _magma_bind_wire_2_0 = orr_5_inst0_O; @@ -188,6 +185,9 @@ orr_5 orr_5_inst0 ( .I(in1), .O(orr_5_inst0_O) ); +bar_foo_SomeCircuit_unq1 some_circ ( + .I(magma_Bits_5_xor_inst0_out) +); assign temp3 = andr_5_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -243,9 +243,6 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; -bar_foo_SomeCircuit SomeCircuit_inst0 ( - .I(magma_Bits_4_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -316,6 +313,9 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); +bar_foo_SomeCircuit some_circ ( + .I(magma_Bits_4_xor_inst0_out) +); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; From 3d3ec5785e1ca74c5ebdea41b2764869ba110921 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 5 Dec 2022 19:47:42 -0800 Subject: [PATCH 10/61] Update gold --- tests/test_verilog/gold/test_inline_tuple.mlir | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/test_verilog/gold/test_inline_tuple.mlir b/tests/test_verilog/gold/test_inline_tuple.mlir index bd0957331..114215f00 100644 --- a/tests/test_verilog/gold/test_inline_tuple.mlir +++ b/tests/test_verilog/gold/test_inline_tuple.mlir @@ -9,17 +9,17 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %1, %0, %4, %5, %2, %3 : i1, i1, i5, i1, i5, i1 } hw.module @Main(%I_0_data: i5, %I_0_valid: i1, %I_1_data: i5, %I_1_valid: i1, %O_0_ready: i1, %O_1_ready: i1, %CLK: i1) -> (I_0_ready: i1, I_1_ready: i1, O_0_data: i5, O_0_valid: i1, O_1_data: i5, O_1_valid: i1) { - %0, %1, %2, %3, %4, %5 = hw.instance "DelayUnit_inst0" @DelayUnit(INPUT_0_data: %I_1_data: i5, INPUT_0_valid: %I_1_valid: i1, INPUT_1_data: %I_0_data: i5, INPUT_1_valid: %I_0_valid: i1, OUTPUT_0_ready: %O_1_ready: i1, OUTPUT_1_ready: %O_0_ready: i1, CLK: %CLK: i1) -> (INPUT_0_ready: i1, INPUT_1_ready: i1, OUTPUT_0_data: i5, OUTPUT_0_valid: i1, OUTPUT_1_data: i5, OUTPUT_1_valid: i1) + %0, %1, %2, %3, %4, %5 = hw.instance "delay" @DelayUnit(INPUT_0_data: %I_1_data: i5, INPUT_0_valid: %I_1_valid: i1, INPUT_1_data: %I_0_data: i5, INPUT_1_valid: %I_0_valid: i1, OUTPUT_0_ready: %O_1_ready: i1, OUTPUT_1_ready: %O_0_ready: i1, CLK: %CLK: i1) -> (INPUT_0_ready: i1, INPUT_1_ready: i1, OUTPUT_0_data: i5, OUTPUT_0_valid: i1, OUTPUT_1_data: i5, OUTPUT_1_valid: i1) sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%I_0_valid, %O_1_ready) : i1, i1 sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%5, %0) : i1, i1 - %7 = sv.xmr "DelayUnit_inst0", "inner_delay", "OUTPUT_0_valid" : !hw.inout + %7 = sv.xmr "delay", "inner_delay", "OUTPUT_0_valid" : !hw.inout %6 = sv.read_inout %7 : !hw.inout - %9 = sv.xmr "DelayUnit_inst0", "inner_delay", "INPUT_1_ready" : !hw.inout + %9 = sv.xmr "delay", "inner_delay", "INPUT_1_ready" : !hw.inout %8 = sv.read_inout %9 : !hw.inout sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%6, %8) : i1, i1 - %11 = sv.xmr "DelayUnit_inst0", "inner_delay", "inner_inner_delay", "OUTPUT_0_valid" : !hw.inout + %11 = sv.xmr "delay", "inner_delay", "inner_inner_delay", "OUTPUT_0_valid" : !hw.inout %10 = sv.read_inout %11 : !hw.inout - %13 = sv.xmr "DelayUnit_inst0", "inner_delay", "inner_inner_delay", "INPUT_1_ready" : !hw.inout + %13 = sv.xmr "delay", "inner_delay", "inner_inner_delay", "INPUT_1_ready" : !hw.inout %12 = sv.read_inout %13 : !hw.inout sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%10, %12) : i1, i1 hw.output %1, %0, %4, %5, %2, %3 : i1, i1, i5, i1, i5, i1 From 43059e0b5f8c45db053afd4a380a37516a3eb746 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 4 Apr 2022 11:54:10 -0700 Subject: [PATCH 11/61] Prototype debug transformer --- magma/__init__.py | 1 + magma/debug.py | 1 - magma/debug_rewriter.py | 57 +++++++++++++++++++ tests/test_debug/build/.gitignore | 2 + .../gold/test_debug_generator_basic.v | 55 ++++++++++++++++++ tests/test_debug/test_debug_generator.py | 17 ++++++ 6 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 magma/debug_rewriter.py create mode 100644 tests/test_debug/build/.gitignore create mode 100644 tests/test_debug/gold/test_debug_generator_basic.v create mode 100644 tests/test_debug/test_debug_generator.py diff --git a/magma/__init__.py b/magma/__init__.py index e0578d4ec..58ad6f387 100644 --- a/magma/__init__.py +++ b/magma/__init__.py @@ -125,6 +125,7 @@ def set_mantle_target(t): from magma.when import when, elsewhen, otherwise from magma.value_utils import fill from magma.bind2 import bind2, make_bind_ports +from magma.debug_rewriter import debug ################################################################################ # BEGIN ALIASES diff --git a/magma/debug.py b/magma/debug.py index 388e328fa..2deb3ca72 100644 --- a/magma/debug.py +++ b/magma/debug.py @@ -1,6 +1,5 @@ import inspect import collections -import magma from magma.config import get_debug_mode diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py new file mode 100644 index 000000000..540e1ad3d --- /dev/null +++ b/magma/debug_rewriter.py @@ -0,0 +1,57 @@ +import ast +import astor +import inspect + +from magma.ast_utils import get_ast, compile_function_to_file +from magma.t import Type +from magma.ref import AnonRef, NamedRef + + +class DebugTransformer(ast.NodeTransformer): + def __init__(self, filename): + self.filename = filename + + def visit_Assign(self, node): + if len(node.targets) > 1: + raise NotImplementedError() + + assert len(node.targets) == 1 + if not isinstance(node.targets[0], ast.Name): + return node + node.value = ast.Call( + ast.Attribute(ast.Attribute(ast.Name("m"), "debug_rewriter", + ast.Load()), "set_name", ast.Load()), + [node.value, ast.Str(node.targets[0].id), ast.Str(self.filename), + ast.Num(node.lineno)], + [] + ) + return node + + +def get_filename(fn): + frame = inspect.stack()[1] + module = inspect.getmodule(frame[0]) + return module.__file__ + + +def debug(fn): + filename = get_filename(fn) + tree = get_ast(fn) + assert len(tree.body[0].decorator_list) == 1 + tree.body[0].decorator_list = [] + tree = DebugTransformer(filename).visit(tree) + # TODO(leonardt): gen_free_name for magma ref + tree.body.insert(0, ast.parse("import magma as m").body[0]) + return compile_function_to_file(tree, fn.__name__) + return fn + + +def set_name(value, name, filename, lineno): + if not isinstance(value, Type): + return + if not isinstance(value.name, AnonRef): + return + value.name = NamedRef(name) + value.filename = filename + value.lineno = lineno + return value diff --git a/tests/test_debug/build/.gitignore b/tests/test_debug/build/.gitignore new file mode 100644 index 000000000..d6b7ef32c --- /dev/null +++ b/tests/test_debug/build/.gitignore @@ -0,0 +1,2 @@ +* +!.gitignore diff --git a/tests/test_debug/gold/test_debug_generator_basic.v b/tests/test_debug/gold/test_debug_generator_basic.v new file mode 100644 index 000000000..0e32d1fb0 --- /dev/null +++ b/tests/test_debug/gold/test_debug_generator_basic.v @@ -0,0 +1,55 @@ +module coreir_xorr #( + parameter width = 1 +) ( + input [width-1:0] in, + output out +); + assign out = ^in; +endmodule + +module coreir_wire #( + parameter width = 1 +) ( + input [width-1:0] in, + output [width-1:0] out +); + assign out = in; +endmodule + +module coreir_not #( + parameter width = 1 +) ( + input [width-1:0] in, + output [width-1:0] out +); + assign out = ~in; +endmodule + +module Foo ( + input [3:0] I, + output O +); +wire coreir_xorr_4_inst0_out; +wire [3:0] magma_Bits_4_not_inst0_out; +wire [3:0] x_out; +coreir_xorr #( + .width(4) +) coreir_xorr_4_inst0 ( + .in(x_out), + .out(coreir_xorr_4_inst0_out) +); +coreir_not #( + .width(4) +) magma_Bits_4_not_inst0 ( + .in(I), + .out(magma_Bits_4_not_inst0_out) +); +coreir_wire #( + .width(4) +) x ( + .in(magma_Bits_4_not_inst0_out), + .out(x_out) +); +assign O = coreir_xorr_4_inst0_out; +endmodule + diff --git a/tests/test_debug/test_debug_generator.py b/tests/test_debug/test_debug_generator.py new file mode 100644 index 000000000..c930c0b91 --- /dev/null +++ b/tests/test_debug/test_debug_generator.py @@ -0,0 +1,17 @@ +import magma as m +from magma.testing import check_files_equal + + +def test_debug_generator_basic(): + class Foo(m.Generator2): + @m.debug + def __init__(self, n): + self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) + x = m.Bits[n]() + x @= ~self.io.I + self.io.O @= x.reduce_xor() + + m.compile("build/test_debug_generator_basic", Foo(4)) + assert check_files_equal(__file__, + "build/test_debug_generator_basic.v", + "gold/test_debug_generator_basic.v") From 6289d9c586d1873d9bd74411ca0dcc2beededc96 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 4 Apr 2022 11:54:47 -0700 Subject: [PATCH 12/61] Use inline True --- .../gold/test_debug_generator_basic.v | 52 ++----------------- tests/test_debug/test_debug_generator.py | 2 +- 2 files changed, 4 insertions(+), 50 deletions(-) diff --git a/tests/test_debug/gold/test_debug_generator_basic.v b/tests/test_debug/gold/test_debug_generator_basic.v index 0e32d1fb0..5241cf8c5 100644 --- a/tests/test_debug/gold/test_debug_generator_basic.v +++ b/tests/test_debug/gold/test_debug_generator_basic.v @@ -1,55 +1,9 @@ -module coreir_xorr #( - parameter width = 1 -) ( - input [width-1:0] in, - output out -); - assign out = ^in; -endmodule - -module coreir_wire #( - parameter width = 1 -) ( - input [width-1:0] in, - output [width-1:0] out -); - assign out = in; -endmodule - -module coreir_not #( - parameter width = 1 -) ( - input [width-1:0] in, - output [width-1:0] out -); - assign out = ~in; -endmodule - module Foo ( input [3:0] I, output O ); -wire coreir_xorr_4_inst0_out; -wire [3:0] magma_Bits_4_not_inst0_out; -wire [3:0] x_out; -coreir_xorr #( - .width(4) -) coreir_xorr_4_inst0 ( - .in(x_out), - .out(coreir_xorr_4_inst0_out) -); -coreir_not #( - .width(4) -) magma_Bits_4_not_inst0 ( - .in(I), - .out(magma_Bits_4_not_inst0_out) -); -coreir_wire #( - .width(4) -) x ( - .in(magma_Bits_4_not_inst0_out), - .out(x_out) -); -assign O = coreir_xorr_4_inst0_out; +wire [3:0] x; +assign x = ~ I; +assign O = ^ x; endmodule diff --git a/tests/test_debug/test_debug_generator.py b/tests/test_debug/test_debug_generator.py index c930c0b91..fb5f4758d 100644 --- a/tests/test_debug/test_debug_generator.py +++ b/tests/test_debug/test_debug_generator.py @@ -11,7 +11,7 @@ def __init__(self, n): x @= ~self.io.I self.io.O @= x.reduce_xor() - m.compile("build/test_debug_generator_basic", Foo(4)) + m.compile("build/test_debug_generator_basic", Foo(4), inline=True) assert check_files_equal(__file__, "build/test_debug_generator_basic.v", "gold/test_debug_generator_basic.v") From eb0a37d07a78bd4272f78e2e2284ea3b22e819af Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 21 Apr 2022 16:24:25 -0700 Subject: [PATCH 13/61] Add preliminary bench --- benchmarks/debug.py | 42 ++++++++++++++++++++++++++++++++++++++++++ benchmarks/debug.svg | 4 ++++ 2 files changed, 46 insertions(+) create mode 100644 benchmarks/debug.py create mode 100644 benchmarks/debug.svg diff --git a/benchmarks/debug.py b/benchmarks/debug.py new file mode 100644 index 000000000..4c58b58ff --- /dev/null +++ b/benchmarks/debug.py @@ -0,0 +1,42 @@ +import pygal +import timeit +import magma as m + + +def gen_circuit(debug_mode, n=8): + class Foo(m.Generator2): + if debug_mode == 2: + @m.debug + def __init__(self, n): + self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) + x = m.Bits[n]() + x @= ~self.io.I + self.io.O @= x.reduce_xor() + elif debug_mode == 1: + def __init__(self, n): + m.config.set_debug_mode(True) + self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) + x = m.Bits[n]() + x @= ~self.io.I + self.io.O @= x.reduce_xor() + m.config.set_debug_mode(False) + else: + def __init__(self, n): + self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) + x = m.Bits[n]() + x @= ~self.io.I + self.io.O @= x.reduce_xor() + Foo(n) + + +data = {} + +for debug_mode in [0, 1, 2]: + data[debug_mode] = timeit.Timer(lambda: + gen_circuit(debug_mode)).timeit(number=10) + +bar = pygal.Bar() +bar.add('Off', data[0]) +bar.add('Old', data[1]) +bar.add('New', data[2]) +bar.render_to_file("debug.svg") diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg new file mode 100644 index 000000000..304e48acf --- /dev/null +++ b/benchmarks/debug.svg @@ -0,0 +1,4 @@ + +Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.005015535147.9435897435897541.03589291239430.164778124339.4280.000000000000060.048812987530.8564102564102469.4752912617305OffOldNew \ No newline at end of file From 120b33b66664c2d812e069c7bdffc5635c83d303 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 21 Apr 2022 16:27:01 -0700 Subject: [PATCH 14/61] use inspect.getfile --- benchmarks/debug.svg | 6 +++--- magma/debug_rewriter.py | 9 +-------- 2 files changed, 4 insertions(+), 11 deletions(-) diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg index 304e48acf..c838cfbe7 100644 --- a/benchmarks/debug.svg +++ b/benchmarks/debug.svg @@ -1,4 +1,4 @@ -Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.005015535147.9435897435897541.03589291239430.164778124339.4280.000000000000060.048812987530.8564102564102469.4752912617305OffOldNew \ No newline at end of file +Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.005428781147.9435897435897540.86884629198640.174791719339.4280.000000000000060.021797453530.8564102564102515.6562665481706OffOldNew \ No newline at end of file diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 540e1ad3d..d84949493 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -28,14 +28,8 @@ def visit_Assign(self, node): return node -def get_filename(fn): - frame = inspect.stack()[1] - module = inspect.getmodule(frame[0]) - return module.__file__ - - def debug(fn): - filename = get_filename(fn) + filename = inspect.getfile(fn) tree = get_ast(fn) assert len(tree.body[0].decorator_list) == 1 tree.body[0].decorator_list = [] @@ -43,7 +37,6 @@ def debug(fn): # TODO(leonardt): gen_free_name for magma ref tree.body.insert(0, ast.parse("import magma as m").body[0]) return compile_function_to_file(tree, fn.__name__) - return fn def set_name(value, name, filename, lineno): From e2cb6c82fa103c91e318bdc0f3adc7ebf413b32d Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 21 Apr 2022 16:34:33 -0700 Subject: [PATCH 15/61] Use exec/compile pattern --- benchmarks/debug.svg | 6 +++--- magma/debug_rewriter.py | 16 +++++++++++++--- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg index c838cfbe7..2e74264ac 100644 --- a/benchmarks/debug.svg +++ b/benchmarks/debug.svg @@ -1,4 +1,4 @@ -Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.005428781147.9435897435897540.86884629198640.174791719339.4280.000000000000060.021797453530.8564102564102515.6562665481706OffOldNew \ No newline at end of file +Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.20.20.220.220.005204506147.9435897435897543.32518451711210.237269165339.4280.00.014540692530.8564102564102532.7313572978802OffOldNew \ No newline at end of file diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index d84949493..b2b35a1da 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -19,12 +19,18 @@ def visit_Assign(self, node): if not isinstance(node.targets[0], ast.Name): return node node.value = ast.Call( - ast.Attribute(ast.Attribute(ast.Name("m"), "debug_rewriter", - ast.Load()), "set_name", ast.Load()), + ast.Attribute(ast.Attribute(ast.Name("m", ast.Load()), + "debug_rewriter", + ast.Load()), + "set_name", + ast.Load()), [node.value, ast.Str(node.targets[0].id), ast.Str(self.filename), ast.Num(node.lineno)], - [] + [], + lineno=node.lineno, + col_offset=node.col_offset ) + node = ast.fix_missing_locations(node) return node @@ -36,6 +42,10 @@ def debug(fn): tree = DebugTransformer(filename).visit(tree) # TODO(leonardt): gen_free_name for magma ref tree.body.insert(0, ast.parse("import magma as m").body[0]) + + namespace = {} + exec(compile(tree, filename, 'exec'), namespace) + return namespace[fn.__name__] return compile_function_to_file(tree, fn.__name__) From 1b9372f968ce62e5d477780d46de8b7bff54fb87 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 21 Apr 2022 16:36:15 -0700 Subject: [PATCH 16/61] Run pass later --- benchmarks/debug.svg | 6 +++--- magma/debug_rewriter.py | 3 +-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg index 2e74264ac..11f4dbaeb 100644 --- a/benchmarks/debug.svg +++ b/benchmarks/debug.svg @@ -1,4 +1,4 @@ -Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.20.20.220.220.005204506147.9435897435897543.32518451711210.237269165339.4280.00.014540692530.8564102564102532.7313572978802OffOldNew \ No newline at end of file +Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.005230691147.9435897435897542.09872205226220.197455643339.4280.000000000000060.013500457530.8564102564102530.8228961112513OffOldNew \ No newline at end of file diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index b2b35a1da..634959517 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -30,7 +30,6 @@ def visit_Assign(self, node): lineno=node.lineno, col_offset=node.col_offset ) - node = ast.fix_missing_locations(node) return node @@ -42,11 +41,11 @@ def debug(fn): tree = DebugTransformer(filename).visit(tree) # TODO(leonardt): gen_free_name for magma ref tree.body.insert(0, ast.parse("import magma as m").body[0]) + tree = ast.fix_missing_locations(tree) namespace = {} exec(compile(tree, filename, 'exec'), namespace) return namespace[fn.__name__] - return compile_function_to_file(tree, fn.__name__) def set_name(value, name, filename, lineno): From 6bb660b73bdb73da27d90f5044fa6af8b6aacdcb Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 21 Apr 2022 16:36:35 -0700 Subject: [PATCH 17/61] Rename helper --- magma/debug_rewriter.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 634959517..53e13f669 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -22,7 +22,7 @@ def visit_Assign(self, node): ast.Attribute(ast.Attribute(ast.Name("m", ast.Load()), "debug_rewriter", ast.Load()), - "set_name", + "set_debug_info", ast.Load()), [node.value, ast.Str(node.targets[0].id), ast.Str(self.filename), ast.Num(node.lineno)], @@ -48,7 +48,7 @@ def debug(fn): return namespace[fn.__name__] -def set_name(value, name, filename, lineno): +def set_debug_info(value, name, filename, lineno): if not isinstance(value, Type): return if not isinstance(value.name, AnonRef): From 76a11b3da37ff026d482da51d8d7fabe505245b8 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 21 Apr 2022 16:37:18 -0700 Subject: [PATCH 18/61] Include col_offset --- benchmarks/debug.svg | 6 +++--- magma/debug_rewriter.py | 5 +++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg index 11f4dbaeb..c3d3a72b1 100644 --- a/benchmarks/debug.svg +++ b/benchmarks/debug.svg @@ -1,4 +1,4 @@ -Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.005230691147.9435897435897542.09872205226220.197455643339.4280.000000000000060.013500457530.8564102564102530.8228961112513OffOldNew \ No newline at end of file +Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.20.20.220.220.240.240.006899876147.9435897435897541.58836445868280.243072564339.4280.000000000000060.014197638530.8564102564102533.5052552644952OffOldNew \ No newline at end of file diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 53e13f669..58d9e6bf1 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -25,7 +25,7 @@ def visit_Assign(self, node): "set_debug_info", ast.Load()), [node.value, ast.Str(node.targets[0].id), ast.Str(self.filename), - ast.Num(node.lineno)], + ast.Num(node.lineno), ast.Num(node.col_offset)], [], lineno=node.lineno, col_offset=node.col_offset @@ -48,7 +48,7 @@ def debug(fn): return namespace[fn.__name__] -def set_debug_info(value, name, filename, lineno): +def set_debug_info(value, name, filename, lineno, col_offset): if not isinstance(value, Type): return if not isinstance(value.name, AnonRef): @@ -56,4 +56,5 @@ def set_debug_info(value, name, filename, lineno): value.name = NamedRef(name) value.filename = filename value.lineno = lineno + value.col_offset = col_offset return value From 7266f625a09a5bb746c68e0c114bbbc8fc051ee7 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 5 Oct 2022 19:07:09 -0700 Subject: [PATCH 19/61] Migrate to libcst --- magma/debug_rewriter.py | 69 +++++++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 31 deletions(-) diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 58d9e6bf1..6e4f0be2f 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -1,50 +1,57 @@ -import ast -import astor import inspect +import textwrap -from magma.ast_utils import get_ast, compile_function_to_file +import libcst as cst from magma.t import Type from magma.ref import AnonRef, NamedRef -class DebugTransformer(ast.NodeTransformer): +class Transformer(cst.CSTTransformer): + METADATA_DEPENDENCIES = (cst.metadata.PositionProvider,) + def __init__(self, filename): + super().__init__() self.filename = filename - def visit_Assign(self, node): - if len(node.targets) > 1: - raise NotImplementedError() - - assert len(node.targets) == 1 - if not isinstance(node.targets[0], ast.Name): - return node - node.value = ast.Call( - ast.Attribute(ast.Attribute(ast.Name("m", ast.Load()), - "debug_rewriter", - ast.Load()), - "set_debug_info", - ast.Load()), - [node.value, ast.Str(node.targets[0].id), ast.Str(self.filename), - ast.Num(node.lineno), ast.Num(node.col_offset)], - [], - lineno=node.lineno, - col_offset=node.col_offset + def leave_Assign( + self, original_node: cst.FunctionDef, updated_node: cst.FunctionDef + ) -> cst.CSTNode: + assert len(updated_node.targets) == 1 + assert isinstance(updated_node.targets[0], cst.AssignTarget) + if not isinstance(updated_node.targets[0].target, cst.Name): + return updated_node + + pos = self.get_metadata(cst.metadata.PositionProvider, + original_node).start + value_str = cst.Module((cst.Expr(updated_node.value), )).code + name = updated_node.targets[0].target.value + tree = cst.parse_expression( + f"m.debug_rewriter.set_debug_info({value_str}, \"{name}\", " + f"\"{self.filename}\", {pos.line}, {pos.column})" ) - return node + return updated_node.with_changes(value=tree) + + def visit_FunctionDef(self, node: cst.FunctionDef) -> bool: + return True + + def leave_FunctionDef( + self, original_node: cst.FunctionDef, updated_node: cst.FunctionDef + ) -> cst.CSTNode: + return updated_node.with_changes(decorators=[]) def debug(fn): filename = inspect.getfile(fn) - tree = get_ast(fn) - assert len(tree.body[0].decorator_list) == 1 - tree.body[0].decorator_list = [] - tree = DebugTransformer(filename).visit(tree) - # TODO(leonardt): gen_free_name for magma ref - tree.body.insert(0, ast.parse("import magma as m").body[0]) - tree = ast.fix_missing_locations(tree) + indented_program_txt = inspect.getsource(fn) + program_txt = textwrap.dedent(indented_program_txt) + tree = cst.parse_module(program_txt) + wrapper = cst.metadata.MetadataWrapper(tree) + tree = wrapper.visit(Transformer(filename)) + code = "import magma as m\n" + tree.code + print(code) namespace = {} - exec(compile(tree, filename, 'exec'), namespace) + exec(code, namespace) return namespace[fn.__name__] From dd6242eb7e5246f38a264691c2b8c8dc670acb92 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 1 Nov 2022 13:14:41 -0700 Subject: [PATCH 20/61] Simple default logic --- magma/debug_rewriter.py | 10 ++++++++-- magma/generator.py | 2 ++ tests/test_debug/test_debug_generator.py | 1 - 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 6e4f0be2f..14695ad49 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -48,11 +48,17 @@ def debug(fn): wrapper = cst.metadata.MetadataWrapper(tree) tree = wrapper.visit(Transformer(filename)) code = "import magma as m\n" + tree.code - print(code) namespace = {} exec(code, namespace) - return namespace[fn.__name__] + debug_fn = namespace[fn.__name__] + + def wrapper(*args, **kwargs): + try: + return debug_fn(*args, **kwargs) + except Exception: + return fn(*args, **kwargs) + return wrapper def set_debug_info(value, name, filename, lineno, col_offset): diff --git a/magma/generator.py b/magma/generator.py index b56f6ff7e..0cab58854 100644 --- a/magma/generator.py +++ b/magma/generator.py @@ -6,6 +6,7 @@ DebugDefineCircuitKind, NamerDict) from . import cache_definition from magma.common import ParamDict +from magma.debug_rewriter import debug from hwtypes import BitVector @@ -76,6 +77,7 @@ def _make_type(cls, *args, **kwargs): name = cls.__name__ bases = (cls._base_cls_,) dct = cls._base_metacls_.__prepare__(name, bases) + cls.__init__ = debug(cls.__init__) cls.__init__(dummy, *args, **kwargs) dct.update(dict(dummy.__dict__)) # NOTE(leonardt): We need to override the Generator2 classmethod bind with diff --git a/tests/test_debug/test_debug_generator.py b/tests/test_debug/test_debug_generator.py index fb5f4758d..7e4e120e6 100644 --- a/tests/test_debug/test_debug_generator.py +++ b/tests/test_debug/test_debug_generator.py @@ -4,7 +4,6 @@ def test_debug_generator_basic(): class Foo(m.Generator2): - @m.debug def __init__(self, n): self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) x = m.Bits[n]() From 0b64609c311e38f56a3537d5e7133ac85922eec9 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 5 Dec 2022 19:23:34 -0800 Subject: [PATCH 21/61] Remove file/line logic --- magma/debug_rewriter.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 14695ad49..209ac98ae 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -26,8 +26,7 @@ def leave_Assign( value_str = cst.Module((cst.Expr(updated_node.value), )).code name = updated_node.targets[0].target.value tree = cst.parse_expression( - f"m.debug_rewriter.set_debug_info({value_str}, \"{name}\", " - f"\"{self.filename}\", {pos.line}, {pos.column})" + f"m.debug_rewriter.set_debug_info({value_str}, \"{name}\")" ) return updated_node.with_changes(value=tree) @@ -61,13 +60,10 @@ def wrapper(*args, **kwargs): return wrapper -def set_debug_info(value, name, filename, lineno, col_offset): +def set_debug_info(value, name): if not isinstance(value, Type): return if not isinstance(value.name, AnonRef): return value.name = NamedRef(name) - value.filename = filename - value.lineno = lineno - value.col_offset = col_offset return value From a3541f035e4cf3eb58f36cc83f6ab3ab9529a0b0 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 5 Dec 2022 19:41:30 -0800 Subject: [PATCH 22/61] Use namer-dict pattern --- magma/debug_rewriter.py | 29 +++++-------------- .../gold/test_debug_generator_basic.mlir | 11 +++++++ .../gold/test_debug_generator_basic.v | 9 ------ tests/test_debug/test_debug_generator.py | 6 ++-- 4 files changed, 22 insertions(+), 33 deletions(-) create mode 100644 tests/test_debug/gold/test_debug_generator_basic.mlir delete mode 100644 tests/test_debug/gold/test_debug_generator_basic.v diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 209ac98ae..930aa43fb 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -9,10 +9,6 @@ class Transformer(cst.CSTTransformer): METADATA_DEPENDENCIES = (cst.metadata.PositionProvider,) - def __init__(self, filename): - super().__init__() - self.filename = filename - def leave_Assign( self, original_node: cst.FunctionDef, updated_node: cst.FunctionDef ) -> cst.CSTNode: @@ -25,10 +21,10 @@ def leave_Assign( original_node).start value_str = cst.Module((cst.Expr(updated_node.value), )).code name = updated_node.targets[0].target.value - tree = cst.parse_expression( - f"m.debug_rewriter.set_debug_info({value_str}, \"{name}\")" + targets = updated_node.targets + ( + cst.AssignTarget(cst.parse_expression(f"self.{name}")), ) - return updated_node.with_changes(value=tree) + return updated_node.with_changes(targets=targets) def visit_FunctionDef(self, node: cst.FunctionDef) -> bool: return True @@ -40,30 +36,21 @@ def leave_FunctionDef( def debug(fn): - filename = inspect.getfile(fn) indented_program_txt = inspect.getsource(fn) program_txt = textwrap.dedent(indented_program_txt) tree = cst.parse_module(program_txt) wrapper = cst.metadata.MetadataWrapper(tree) - tree = wrapper.visit(Transformer(filename)) - code = "import magma as m\n" + tree.code + tree = wrapper.visit(Transformer()) - namespace = {} - exec(code, namespace) + namespace = dict(**fn.__globals__) + print(tree.code) + exec(tree.code, namespace) debug_fn = namespace[fn.__name__] def wrapper(*args, **kwargs): try: return debug_fn(*args, **kwargs) except Exception: + # TODO: Namespace issues, need to inherite fn closure return fn(*args, **kwargs) return wrapper - - -def set_debug_info(value, name): - if not isinstance(value, Type): - return - if not isinstance(value.name, AnonRef): - return - value.name = NamedRef(name) - return value diff --git a/tests/test_debug/gold/test_debug_generator_basic.mlir b/tests/test_debug/gold/test_debug_generator_basic.mlir new file mode 100644 index 000000000..b5398c1f5 --- /dev/null +++ b/tests/test_debug/gold/test_debug_generator_basic.mlir @@ -0,0 +1,11 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module @Foo(%I: i4) -> (O: i1) { + %1 = hw.constant -1 : i4 + %0 = comb.xor %1, %I : i4 + %3 = sv.wire sym @Foo.x {name="x"} : !hw.inout + sv.assign %3, %0 : i4 + %2 = sv.read_inout %3 : !hw.inout + %4 = comb.parity %2 : i4 + hw.output %4 : i1 + } +} diff --git a/tests/test_debug/gold/test_debug_generator_basic.v b/tests/test_debug/gold/test_debug_generator_basic.v deleted file mode 100644 index 5241cf8c5..000000000 --- a/tests/test_debug/gold/test_debug_generator_basic.v +++ /dev/null @@ -1,9 +0,0 @@ -module Foo ( - input [3:0] I, - output O -); -wire [3:0] x; -assign x = ~ I; -assign O = ^ x; -endmodule - diff --git a/tests/test_debug/test_debug_generator.py b/tests/test_debug/test_debug_generator.py index 7e4e120e6..0c2c6f7b6 100644 --- a/tests/test_debug/test_debug_generator.py +++ b/tests/test_debug/test_debug_generator.py @@ -10,7 +10,7 @@ def __init__(self, n): x @= ~self.io.I self.io.O @= x.reduce_xor() - m.compile("build/test_debug_generator_basic", Foo(4), inline=True) + m.compile("build/test_debug_generator_basic", Foo(4), output="mlir") assert check_files_equal(__file__, - "build/test_debug_generator_basic.v", - "gold/test_debug_generator_basic.v") + "build/test_debug_generator_basic.mlir", + "gold/test_debug_generator_basic.mlir") From 9d06e7a456dde4eb786498a4c3799f5cf70b3d81 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 5 Dec 2022 19:42:23 -0800 Subject: [PATCH 23/61] Remove debug print --- benchmarks/debug.svg | 6 +++--- magma/debug_rewriter.py | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg index c3d3a72b1..f5e4a888a 100644 --- a/benchmarks/debug.svg +++ b/benchmarks/debug.svg @@ -1,4 +1,4 @@ -Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.20.20.220.220.240.240.006899876147.9435897435897541.58836445868280.243072564339.4280.000000000000060.014197638530.8564102564102533.5052552644952OffOldNew \ No newline at end of file +Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.20.20.220.220.240.240.099069942147.9435897435897446.507246155224150.259655003339.4280.00.096152385530.8564102564102449.5323991726975OffOldNew \ No newline at end of file diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 930aa43fb..14261cd8b 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -43,7 +43,6 @@ def debug(fn): tree = wrapper.visit(Transformer()) namespace = dict(**fn.__globals__) - print(tree.code) exec(tree.code, namespace) debug_fn = namespace[fn.__name__] From 31b0df4b1f9ef000030a12b3450e35ca109add0c Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 5 Dec 2022 19:44:52 -0800 Subject: [PATCH 24/61] Update bench --- benchmarks/debug.py | 3 ++- magma/generator.py | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/benchmarks/debug.py b/benchmarks/debug.py index 4c58b58ff..46d20610f 100644 --- a/benchmarks/debug.py +++ b/benchmarks/debug.py @@ -6,7 +6,6 @@ def gen_circuit(debug_mode, n=8): class Foo(m.Generator2): if debug_mode == 2: - @m.debug def __init__(self, n): self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) x = m.Bits[n]() @@ -21,6 +20,8 @@ def __init__(self, n): self.io.O @= x.reduce_xor() m.config.set_debug_mode(False) else: + _disable_debug_ = True + def __init__(self, n): self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) x = m.Bits[n]() diff --git a/magma/generator.py b/magma/generator.py index 0cab58854..7ca9fe29d 100644 --- a/magma/generator.py +++ b/magma/generator.py @@ -77,7 +77,9 @@ def _make_type(cls, *args, **kwargs): name = cls.__name__ bases = (cls._base_cls_,) dct = cls._base_metacls_.__prepare__(name, bases) - cls.__init__ = debug(cls.__init__) + if not getattr(cls, "_disable__debug_", False): + # TODO: temp flag for debug bench, do not need + cls.__init__ = debug(cls.__init__) cls.__init__(dummy, *args, **kwargs) dct.update(dict(dummy.__dict__)) # NOTE(leonardt): We need to override the Generator2 classmethod bind with From 100e4e4bf3766b1368319dd359eb6e231316dabc Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 5 Dec 2022 19:46:06 -0800 Subject: [PATCH 25/61] Fix flag --- magma/generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/magma/generator.py b/magma/generator.py index 7ca9fe29d..95d16d964 100644 --- a/magma/generator.py +++ b/magma/generator.py @@ -77,7 +77,7 @@ def _make_type(cls, *args, **kwargs): name = cls.__name__ bases = (cls._base_cls_,) dct = cls._base_metacls_.__prepare__(name, bases) - if not getattr(cls, "_disable__debug_", False): + if not getattr(cls, "_disable_debug_", False): # TODO: temp flag for debug bench, do not need cls.__init__ = debug(cls.__init__) cls.__init__(dummy, *args, **kwargs) From 8b9649347f45e5913afc3a997f2613fa6bd8a2ba Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 6 Dec 2022 13:35:27 -0800 Subject: [PATCH 26/61] Fix regression, update golds --- magma/debug_rewriter.py | 8 ++++++-- ...lex_register_wrapper_elaborate_magma_registers.mlir | 2 +- .../test_mlir/golds/simple_memory_wrapper.mlir | 2 +- ...ple_register_wrapper_elaborate_magma_registers.mlir | 2 +- tests/test_syntax/gold/basic_function_call.json | 10 +++++----- tests/test_syntax/gold/custom_env0.json | 10 +++++----- tests/test_syntax/gold/custom_env1.json | 10 +++++----- tests/test_syntax/gold/if_statement_basic.json | 10 +++++----- tests/test_syntax/gold/multiple_assign.json | 10 +++++----- tests/test_syntax/gold/optional_assignment.json | 10 +++++----- tests/test_syntax/gold/simple_circuit_1.json | 10 +++++----- tests/test_syntax/gold/ternary.json | 10 +++++----- tests/test_syntax/gold/ternary_nested.json | 10 +++++----- tests/test_syntax/gold/ternary_nested2.json | 10 +++++----- 14 files changed, 59 insertions(+), 55 deletions(-) diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 14261cd8b..5ef74dad2 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -12,8 +12,12 @@ class Transformer(cst.CSTTransformer): def leave_Assign( self, original_node: cst.FunctionDef, updated_node: cst.FunctionDef ) -> cst.CSTNode: - assert len(updated_node.targets) == 1 - assert isinstance(updated_node.targets[0], cst.AssignTarget) + if len(updated_node.targets) != 1: + # TODO: handle chained assigns + return updated_node + if not isinstance(updated_node.targets[0], cst.AssignTarget): + # TODO: Handle this case + return updated_node if not isinstance(updated_node.targets[0].target, cst.Name): return updated_node diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir b/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir index ec8eaa5bb..2833c8b00 100644 --- a/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir +++ b/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir @@ -23,7 +23,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { %22 = comb.extract %14 from 7 : (i8) -> i1 %23 = hw.struct_extract %12["y"] : !hw.struct %24 = comb.concat %23, %22, %21, %20, %19, %18, %17, %16, %15 : i1, i1, i1, i1, i1, i1, i1, i1, i1 - %25 = sv.reg {name = "reg_PR9_inst0"} : !hw.inout + %25 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %25, %24 : i9 } (asyncreset : posedge %ASYNCRESET) { diff --git a/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir b/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir index 5a7ccf9f8..add75af5a 100644 --- a/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir +++ b/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir @@ -1,6 +1,6 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @Memory(%RADDR: i7, %CLK: i1, %WADDR: i7, %WDATA: i12, %WE: i1) -> (RDATA: i12) { - %1 = sv.reg {name = "coreir_mem128x12_inst0"} : !hw.inout> + %1 = sv.reg {name = "coreir_mem"} : !hw.inout> %2 = sv.array_index_inout %1[%RADDR] : !hw.inout>, i7 %0 = sv.read_inout %2 : !hw.inout %3 = sv.array_index_inout %1[%WADDR] : !hw.inout>, i7 diff --git a/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir b/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir index 1daffdf80..c85d471f2 100644 --- a/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir +++ b/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir @@ -1,6 +1,6 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @Register(%I: i8, %CLK: i1) -> (O: i8) { - %1 = sv.reg {name = "reg_P8_inst0"} : !hw.inout + %1 = sv.reg {name = "reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %1, %I : i8 } diff --git a/tests/test_syntax/gold/basic_function_call.json b/tests/test_syntax/gold/basic_function_call.json index 8b9d1a620..0795083c3 100644 --- a/tests/test_syntax/gold/basic_function_call.json +++ b/tests/test_syntax/gold/basic_function_call.json @@ -10,16 +10,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "basic_func":{ diff --git a/tests/test_syntax/gold/custom_env0.json b/tests/test_syntax/gold/custom_env0.json index 2446c3fce..542db6d26 100644 --- a/tests/test_syntax/gold/custom_env0.json +++ b/tests/test_syntax/gold/custom_env0.json @@ -10,16 +10,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "basic_fun":{ diff --git a/tests/test_syntax/gold/custom_env1.json b/tests/test_syntax/gold/custom_env1.json index 81470869e..f16a063cc 100644 --- a/tests/test_syntax/gold/custom_env1.json +++ b/tests/test_syntax/gold/custom_env1.json @@ -10,16 +10,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "basic_fun":{ diff --git a/tests/test_syntax/gold/if_statement_basic.json b/tests/test_syntax/gold/if_statement_basic.json index ebd24bd74..ca97c33f2 100644 --- a/tests/test_syntax/gold/if_statement_basic.json +++ b/tests/test_syntax/gold/if_statement_basic.json @@ -10,16 +10,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "basic_if":{ diff --git a/tests/test_syntax/gold/multiple_assign.json b/tests/test_syntax/gold/multiple_assign.json index e42731c74..95ddf91fa 100644 --- a/tests/test_syntax/gold/multiple_assign.json +++ b/tests/test_syntax/gold/multiple_assign.json @@ -25,16 +25,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "eq":{ diff --git a/tests/test_syntax/gold/optional_assignment.json b/tests/test_syntax/gold/optional_assignment.json index 865e0d6b5..a908f68af 100644 --- a/tests/test_syntax/gold/optional_assignment.json +++ b/tests/test_syntax/gold/optional_assignment.json @@ -27,16 +27,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "eq":{ diff --git a/tests/test_syntax/gold/simple_circuit_1.json b/tests/test_syntax/gold/simple_circuit_1.json index 2efd5e325..283eb4bcf 100644 --- a/tests/test_syntax/gold/simple_circuit_1.json +++ b/tests/test_syntax/gold/simple_circuit_1.json @@ -25,16 +25,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "eq":{ diff --git a/tests/test_syntax/gold/ternary.json b/tests/test_syntax/gold/ternary.json index e3fcc03ac..d058da68e 100644 --- a/tests/test_syntax/gold/ternary.json +++ b/tests/test_syntax/gold/ternary.json @@ -10,16 +10,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "ternary":{ diff --git a/tests/test_syntax/gold/ternary_nested.json b/tests/test_syntax/gold/ternary_nested.json index df2478451..6e011b5c4 100644 --- a/tests/test_syntax/gold/ternary_nested.json +++ b/tests/test_syntax/gold/ternary_nested.json @@ -10,16 +10,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "ternary_nested":{ diff --git a/tests/test_syntax/gold/ternary_nested2.json b/tests/test_syntax/gold/ternary_nested2.json index c7de4b123..741c621e7 100644 --- a/tests/test_syntax/gold/ternary_nested2.json +++ b/tests/test_syntax/gold/ternary_nested2.json @@ -10,16 +10,16 @@ ["O","Bit"] ]], "instances":{ - "coreir_commonlib_mux2x1_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",1]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], - ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], - ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ["self.I0","mux.in.data.0.0"], + ["self.I1","mux.in.data.1.0"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out.0"] ] }, "ternary_nested2":{ From aa277aa612239d74ecba42f36b8e9e016f80a920 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 7 Dec 2022 15:38:16 -0800 Subject: [PATCH 27/61] Update golds --- magma/primitives/register.py | 10 +- .../test_compile_guard_anon_driver_driven.v | 8 +- ...st_compile_guard_anon_driver_nested_type.v | 32 ++--- tests/gold/test_compile_guard_array.json | 8 +- tests/gold/test_compile_guard_assert.json | 36 ++--- tests/gold/test_compile_guard_basic.json | 8 +- .../test_compile_guard_basic_undefined.json | 8 +- tests/gold/test_compile_guard_basic_vcc.json | 8 +- ...t_compile_guard_contained_inline_verilog.v | 8 +- .../test_compile_guard_multiple_array.json | 8 +- .../gold/test_compile_guard_nested_type.json | 8 +- tests/gold/test_when_memory_Bits8.mlir | 2 +- .../test_when_memory_Tuplex_Bit_y_Bits7.mlir | 2 +- tests/gold/test_when_user_reg.mlir | 2 +- tests/gold/test_when_user_reg_enable.mlir | 2 +- .../gold/test_circuit_add_default_clock.v | 8 +- .../test_issues/gold/test_708_inline_False.v | 8 +- tests/test_issues/gold/test_708_inline_True.v | 8 +- tests/test_operators/gold/TestSetSlice.v | 8 +- tests/test_operators/gold/TestSlice.v | 20 +-- tests/test_primitives/gold/test_basic_mux.v | 16 +-- .../test_primitives/gold/test_basic_mux_arr.v | 10 +- .../gold/test_basic_mux_bits.v | 16 +-- .../gold/test_basic_mux_product.v | 10 +- .../gold/test_basic_mux_tuple.v | 10 +- .../test_basic_reg_AbstractBitVectorMeta.v | 36 ++--- .../gold/test_basic_reg_BitsMeta.v | 36 ++--- .../gold/test_basic_reg_function.v | 36 ++--- tests/test_primitives/gold/test_enable_reg.v | 40 +++--- tests/test_primitives/gold/test_memory_arr.v | 20 +-- .../gold/test_memory_basic.mlir | 2 +- .../gold/test_memory_product.v | 16 +-- .../gold/test_memory_product_init.v | 10 +- .../gold/test_memory_read_latency_False.v | 44 +++--- .../gold/test_memory_read_latency_True.v | 44 +++--- .../gold/test_memory_read_only.v | 8 +- .../test_primitives/gold/test_mux_operator.v | 16 +-- .../gold/test_mux_operator_int.v | 16 +-- .../gold/test_reg_async_resetn.v | 8 +- .../gold/test_reg_of_nested_array.v | 30 ++--- .../gold/test_reg_of_product.v | 26 ++-- .../gold/test_reg_of_product_zero_init.v | 26 ++-- .../gold/TestSequential2ArrOfBits.v | 42 +++--- .../test_syntax/gold/TestSequential2Assign.v | 8 +- tests/test_syntax/gold/TestSequential2Basic.v | 8 +- .../test_syntax/gold/TestSequential2Counter.v | 2 +- .../gold/TestSequential2CounterIf.v | 10 +- .../gold/TestSequential2CustomAnnotations.v | 2 +- .../test_syntax/gold/TestSequential2GetItem.v | 50 +++---- .../gold/TestSequential2Hierarchy.v | 8 +- .../gold/TestSequential2IteArray.v | 24 ++-- .../gold/TestSequential2IteArray2.v | 24 ++-- .../test_syntax/gold/TestSequential2IteBits.v | 18 +-- .../gold/TestSequential2IteBits2.v | 18 +-- .../gold/TestSequential2IteBits3.v | 24 ++-- .../gold/TestSequential2IteComplex.v | 36 ++--- .../gold/TestSequential2IteComplexRegister.v | 26 ++-- .../gold/TestSequential2IteComplexRegister2.v | 26 ++-- .../gold/TestSequential2IteNested.v | 26 ++-- .../gold/TestSequential2IteProduct.v | 24 ++-- .../gold/TestSequential2IteProduct2.v | 24 ++-- .../gold/TestSequential2IteTuple.v | 24 ++-- .../gold/TestSequential2IteTuple2.v | 24 ++-- .../gold/TestSequential2NestedLoopUnroll.v | 8 +- tests/test_syntax/gold/TestSequential2Prev.v | 2 +- .../test_syntax/gold/TestSequential2Product.v | 8 +- tests/test_syntax/gold/TestSequential2Reset.v | 22 +-- .../gold/TestSequential2ReturnTuple.v | 18 +-- tests/test_syntax/gold/TestSequential2Slice.v | 126 +++++++++--------- tests/test_syntax/gold/test_562.v | 16 +-- .../gold/test_combinational2_basic_if.v | 8 +- .../test_combinational2_pre_post_passes.v | 8 +- .../test_syntax/gold/test_inline_comb_basic.v | 16 +-- .../gold/test_inline_comb_bv_bit_bool.v | 16 +-- .../test_syntax/gold/test_inline_comb_list.v | 16 +-- .../test_syntax/gold/test_inline_comb_wire.v | 16 +-- tests/test_type/gold/TestBitite.v | 16 +-- .../test_type/gold/TestReadyValidNoDeqWhen.v | 8 +- .../test_type/gold/TestReadyValidNoEnqWhen.v | 16 +-- tests/test_type/gold/TestReadyValidWhen.v | 8 +- .../gold/test_array2_nested_bits_temporary.v | 2 +- .../test_type/gold/test_foo_magma_protocol.v | 8 +- .../gold/test_ndarray_dynamic_getitem.v | 52 ++++---- .../gold/test_ndarray_dynamic_getitem2.v | 76 +++++------ .../gold/test_ndarray_dynamic_getitem3.v | 82 ++++++------ tests/test_type/gold/test_ndarray_get_slice.v | 22 +-- tests/test_type/gold/test_ndarray_set_slice.v | 12 +- tests/test_verilog/gold/TestDisplay.v | 2 +- tests/test_verilog/gold/TestFDisplay.v | 6 +- tests/test_verilog/gold/TestFLog.v | 8 +- tests/test_verilog/gold/TestLog.v | 4 +- tests/test_verilog/gold/bind_test.v | 6 +- tests/test_verilog/gold/bind_uniq_test.v | 98 +++++++------- .../test_inline_wire_insertion_bad_verilog.v | 2 +- 94 files changed, 917 insertions(+), 917 deletions(-) diff --git a/magma/primitives/register.py b/magma/primitives/register.py index 96cc6386f..e9bc8bc96 100644 --- a/magma/primitives/register.py +++ b/magma/primitives/register.py @@ -209,10 +209,10 @@ def __init__(self, T: Kind = None, coreir_init = as_bits(init) coreir_init = int(coreir_init) - reg = _CoreIRRegister(T.flat_length(), init=coreir_init, - has_async_reset=has_async_reset, - has_async_resetn=has_async_resetn)() - O = from_bits(T, reg.O) + _reg = _CoreIRRegister(T.flat_length(), init=coreir_init, + has_async_reset=has_async_reset, + has_async_resetn=has_async_resetn)() + O = from_bits(T, _reg.O) wire(O, getattr(self.io, O_name)) I = getattr(self.io, I_name) @@ -233,7 +233,7 @@ def __init__(self, T: Kind = None, I = Mux(2, T)(name="enable_mux")(O, I, enable) elif (has_reset or has_resetn): I = Mux(2, T)()(I, init, reset_select) - reg.I @= as_bits(I) + _reg.I @= as_bits(I) def get_enable(self, inst): return getattr(inst, self.CE_name, None) diff --git a/tests/gold/test_compile_guard_anon_driver_driven.v b/tests/gold/test_compile_guard_anon_driver_driven.v index 4f1a8a7b4..28a3fa303 100644 --- a/tests/gold/test_compile_guard_anon_driver_driven.v +++ b/tests/gold/test_compile_guard_anon_driver_driven.v @@ -28,17 +28,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module A ( diff --git a/tests/gold/test_compile_guard_anon_driver_nested_type.v b/tests/gold/test_compile_guard_anon_driver_nested_type.v index 8420ec94e..d2b199018 100644 --- a/tests/gold/test_compile_guard_anon_driver_nested_type.v +++ b/tests/gold/test_compile_guard_anon_driver_nested_type.v @@ -48,28 +48,28 @@ module Register ( output [9:0] O_8_x, output [9:0] O_9_x ); -wire [99:0] reg_P100_inst0_out; -wire [99:0] reg_P100_inst0_in; -assign reg_P100_inst0_in = {I_9_x,I_8_x,I_7_x,I_6_x,I_5_x,I_4_x,I_3_x,I_2_x,I_1_x,I_0_x}; +wire [99:0] _reg_out; +wire [99:0] _reg_in; +assign _reg_in = {I_9_x,I_8_x,I_7_x,I_6_x,I_5_x,I_4_x,I_3_x,I_2_x,I_1_x,I_0_x}; coreir_reg #( .clk_posedge(1'b1), .init(100'h0000000000000000000000000), .width(100) -) reg_P100_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P100_inst0_in), - .out(reg_P100_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O_0_x = {reg_P100_inst0_out[9],reg_P100_inst0_out[8],reg_P100_inst0_out[7],reg_P100_inst0_out[6],reg_P100_inst0_out[5],reg_P100_inst0_out[4],reg_P100_inst0_out[3],reg_P100_inst0_out[2],reg_P100_inst0_out[1],reg_P100_inst0_out[0]}; -assign O_1_x = {reg_P100_inst0_out[19],reg_P100_inst0_out[18],reg_P100_inst0_out[17],reg_P100_inst0_out[16],reg_P100_inst0_out[15],reg_P100_inst0_out[14],reg_P100_inst0_out[13],reg_P100_inst0_out[12],reg_P100_inst0_out[11],reg_P100_inst0_out[10]}; -assign O_2_x = {reg_P100_inst0_out[29],reg_P100_inst0_out[28],reg_P100_inst0_out[27],reg_P100_inst0_out[26],reg_P100_inst0_out[25],reg_P100_inst0_out[24],reg_P100_inst0_out[23],reg_P100_inst0_out[22],reg_P100_inst0_out[21],reg_P100_inst0_out[20]}; -assign O_3_x = {reg_P100_inst0_out[39],reg_P100_inst0_out[38],reg_P100_inst0_out[37],reg_P100_inst0_out[36],reg_P100_inst0_out[35],reg_P100_inst0_out[34],reg_P100_inst0_out[33],reg_P100_inst0_out[32],reg_P100_inst0_out[31],reg_P100_inst0_out[30]}; -assign O_4_x = {reg_P100_inst0_out[49],reg_P100_inst0_out[48],reg_P100_inst0_out[47],reg_P100_inst0_out[46],reg_P100_inst0_out[45],reg_P100_inst0_out[44],reg_P100_inst0_out[43],reg_P100_inst0_out[42],reg_P100_inst0_out[41],reg_P100_inst0_out[40]}; -assign O_5_x = {reg_P100_inst0_out[59],reg_P100_inst0_out[58],reg_P100_inst0_out[57],reg_P100_inst0_out[56],reg_P100_inst0_out[55],reg_P100_inst0_out[54],reg_P100_inst0_out[53],reg_P100_inst0_out[52],reg_P100_inst0_out[51],reg_P100_inst0_out[50]}; -assign O_6_x = {reg_P100_inst0_out[69],reg_P100_inst0_out[68],reg_P100_inst0_out[67],reg_P100_inst0_out[66],reg_P100_inst0_out[65],reg_P100_inst0_out[64],reg_P100_inst0_out[63],reg_P100_inst0_out[62],reg_P100_inst0_out[61],reg_P100_inst0_out[60]}; -assign O_7_x = {reg_P100_inst0_out[79],reg_P100_inst0_out[78],reg_P100_inst0_out[77],reg_P100_inst0_out[76],reg_P100_inst0_out[75],reg_P100_inst0_out[74],reg_P100_inst0_out[73],reg_P100_inst0_out[72],reg_P100_inst0_out[71],reg_P100_inst0_out[70]}; -assign O_8_x = {reg_P100_inst0_out[89],reg_P100_inst0_out[88],reg_P100_inst0_out[87],reg_P100_inst0_out[86],reg_P100_inst0_out[85],reg_P100_inst0_out[84],reg_P100_inst0_out[83],reg_P100_inst0_out[82],reg_P100_inst0_out[81],reg_P100_inst0_out[80]}; -assign O_9_x = {reg_P100_inst0_out[99],reg_P100_inst0_out[98],reg_P100_inst0_out[97],reg_P100_inst0_out[96],reg_P100_inst0_out[95],reg_P100_inst0_out[94],reg_P100_inst0_out[93],reg_P100_inst0_out[92],reg_P100_inst0_out[91],reg_P100_inst0_out[90]}; +assign O_0_x = {_reg_out[9],_reg_out[8],_reg_out[7],_reg_out[6],_reg_out[5],_reg_out[4],_reg_out[3],_reg_out[2],_reg_out[1],_reg_out[0]}; +assign O_1_x = {_reg_out[19],_reg_out[18],_reg_out[17],_reg_out[16],_reg_out[15],_reg_out[14],_reg_out[13],_reg_out[12],_reg_out[11],_reg_out[10]}; +assign O_2_x = {_reg_out[29],_reg_out[28],_reg_out[27],_reg_out[26],_reg_out[25],_reg_out[24],_reg_out[23],_reg_out[22],_reg_out[21],_reg_out[20]}; +assign O_3_x = {_reg_out[39],_reg_out[38],_reg_out[37],_reg_out[36],_reg_out[35],_reg_out[34],_reg_out[33],_reg_out[32],_reg_out[31],_reg_out[30]}; +assign O_4_x = {_reg_out[49],_reg_out[48],_reg_out[47],_reg_out[46],_reg_out[45],_reg_out[44],_reg_out[43],_reg_out[42],_reg_out[41],_reg_out[40]}; +assign O_5_x = {_reg_out[59],_reg_out[58],_reg_out[57],_reg_out[56],_reg_out[55],_reg_out[54],_reg_out[53],_reg_out[52],_reg_out[51],_reg_out[50]}; +assign O_6_x = {_reg_out[69],_reg_out[68],_reg_out[67],_reg_out[66],_reg_out[65],_reg_out[64],_reg_out[63],_reg_out[62],_reg_out[61],_reg_out[60]}; +assign O_7_x = {_reg_out[79],_reg_out[78],_reg_out[77],_reg_out[76],_reg_out[75],_reg_out[74],_reg_out[73],_reg_out[72],_reg_out[71],_reg_out[70]}; +assign O_8_x = {_reg_out[89],_reg_out[88],_reg_out[87],_reg_out[86],_reg_out[85],_reg_out[84],_reg_out[83],_reg_out[82],_reg_out[81],_reg_out[80]}; +assign O_9_x = {_reg_out[99],_reg_out[98],_reg_out[97],_reg_out[96],_reg_out[95],_reg_out[94],_reg_out[93],_reg_out[92],_reg_out[91],_reg_out[90]}; endmodule module A ( diff --git a/tests/gold/test_compile_guard_array.json b/tests/gold/test_compile_guard_array.json index bcfeae1b4..843e50535 100644 --- a/tests/gold/test_compile_guard_array.json +++ b/tests/gold/test_compile_guard_array.json @@ -24,16 +24,16 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "reg_P1_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",1]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",1],"1'h0"]} } }, "connections":[ - ["self.CLK","reg_P1_inst0.clk"], - ["self.I","reg_P1_inst0.in.0"], - ["self.O","reg_P1_inst0.out.0"] + ["self.CLK","_reg.clk"], + ["self.I","_reg.in.0"], + ["self.O","_reg.out.0"] ] }, "_Top":{ diff --git a/tests/gold/test_compile_guard_assert.json b/tests/gold/test_compile_guard_assert.json index c420ca557..82184c771 100644 --- a/tests/gold/test_compile_guard_assert.json +++ b/tests/gold/test_compile_guard_assert.json @@ -87,16 +87,16 @@ ["O",["Array",2,"Bit"]] ]], "instances":{ - "coreir_commonlib_mux2x2_inst0":{ + "mux":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",2]} } }, "connections":[ - ["self.I0","coreir_commonlib_mux2x2_inst0.in.data.0"], - ["self.I1","coreir_commonlib_mux2x2_inst0.in.data.1"], - ["self.S","coreir_commonlib_mux2x2_inst0.in.sel.0"], - ["self.O","coreir_commonlib_mux2x2_inst0.out"] + ["self.I0","mux.in.data.0"], + ["self.I1","mux.in.data.1"], + ["self.S","mux.in.sel.0"], + ["self.O","mux.out"] ] }, "Register":{ @@ -106,16 +106,16 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "reg_P4_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",4]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",4],"4'h0"]} } }, "connections":[ - ["self.CLK","reg_P4_inst0.clk"], - ["self.I","reg_P4_inst0.in"], - ["self.O","reg_P4_inst0.out"] + ["self.CLK","_reg.clk"], + ["self.I","_reg.in"], + ["self.O","_reg.out"] ] }, "Register_unq1":{ @@ -126,22 +126,22 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "enable_mux":{ - "modref":"global.Mux2xUInt2" - }, - "reg_P2_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",2]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",2],"2'h0"]} + }, + "enable_mux":{ + "modref":"global.Mux2xUInt2" } }, "connections":[ - ["reg_P2_inst0.out","enable_mux.I0"], + ["self.CLK","_reg.clk"], + ["enable_mux.O","_reg.in"], + ["enable_mux.I0","_reg.out"], + ["self.O","_reg.out"], ["self.I","enable_mux.I1"], - ["reg_P2_inst0.in","enable_mux.O"], - ["self.CE","enable_mux.S"], - ["self.CLK","reg_P2_inst0.clk"], - ["self.O","reg_P2_inst0.out"] + ["self.CE","enable_mux.S"] ] }, "_Top":{ diff --git a/tests/gold/test_compile_guard_basic.json b/tests/gold/test_compile_guard_basic.json index dbc104962..07119ba82 100644 --- a/tests/gold/test_compile_guard_basic.json +++ b/tests/gold/test_compile_guard_basic.json @@ -24,16 +24,16 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "reg_P1_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",1]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",1],"1'h0"]} } }, "connections":[ - ["self.CLK","reg_P1_inst0.clk"], - ["self.I","reg_P1_inst0.in.0"], - ["self.O","reg_P1_inst0.out.0"] + ["self.CLK","_reg.clk"], + ["self.I","_reg.in.0"], + ["self.O","_reg.out.0"] ] }, "_Top":{ diff --git a/tests/gold/test_compile_guard_basic_undefined.json b/tests/gold/test_compile_guard_basic_undefined.json index e8d4168a6..b7b6356a7 100644 --- a/tests/gold/test_compile_guard_basic_undefined.json +++ b/tests/gold/test_compile_guard_basic_undefined.json @@ -24,16 +24,16 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "reg_P1_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",1]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",1],"1'h0"]} } }, "connections":[ - ["self.CLK","reg_P1_inst0.clk"], - ["self.I","reg_P1_inst0.in.0"], - ["self.O","reg_P1_inst0.out.0"] + ["self.CLK","_reg.clk"], + ["self.I","_reg.in.0"], + ["self.O","_reg.out.0"] ] }, "_Top":{ diff --git a/tests/gold/test_compile_guard_basic_vcc.json b/tests/gold/test_compile_guard_basic_vcc.json index 7021b5f16..0cdff4d52 100644 --- a/tests/gold/test_compile_guard_basic_vcc.json +++ b/tests/gold/test_compile_guard_basic_vcc.json @@ -33,16 +33,16 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "reg_P1_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",1]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",1],"1'h0"]} } }, "connections":[ - ["self.CLK","reg_P1_inst0.clk"], - ["self.I","reg_P1_inst0.in.0"], - ["self.O","reg_P1_inst0.out.0"] + ["self.CLK","_reg.clk"], + ["self.I","_reg.in.0"], + ["self.O","_reg.out.0"] ] }, "_Top":{ diff --git a/tests/gold/test_compile_guard_contained_inline_verilog.v b/tests/gold/test_compile_guard_contained_inline_verilog.v index 8798fe5ae..6d3f5d750 100644 --- a/tests/gold/test_compile_guard_contained_inline_verilog.v +++ b/tests/gold/test_compile_guard_contained_inline_verilog.v @@ -35,17 +35,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module DebugModule ( diff --git a/tests/gold/test_compile_guard_multiple_array.json b/tests/gold/test_compile_guard_multiple_array.json index 3ace84f45..994041dff 100644 --- a/tests/gold/test_compile_guard_multiple_array.json +++ b/tests/gold/test_compile_guard_multiple_array.json @@ -30,16 +30,16 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "reg_P1_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",1]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",1],"1'h0"]} } }, "connections":[ - ["self.CLK","reg_P1_inst0.clk"], - ["self.I","reg_P1_inst0.in.0"], - ["self.O","reg_P1_inst0.out.0"] + ["self.CLK","_reg.clk"], + ["self.I","_reg.in.0"], + ["self.O","_reg.out.0"] ] }, "_Top":{ diff --git a/tests/gold/test_compile_guard_nested_type.json b/tests/gold/test_compile_guard_nested_type.json index 517eec4cf..891cd9fef 100644 --- a/tests/gold/test_compile_guard_nested_type.json +++ b/tests/gold/test_compile_guard_nested_type.json @@ -30,16 +30,16 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ - "reg_P1_inst0":{ + "_reg":{ "genref":"coreir.reg", "genargs":{"width":["Int",1]}, "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",1],"1'h0"]} } }, "connections":[ - ["self.CLK","reg_P1_inst0.clk"], - ["self.I","reg_P1_inst0.in.0"], - ["self.O","reg_P1_inst0.out.0"] + ["self.CLK","_reg.clk"], + ["self.I","_reg.in.0"], + ["self.O","_reg.out.0"] ] }, "_Top":{ diff --git a/tests/gold/test_when_memory_Bits8.mlir b/tests/gold/test_when_memory_Bits8.mlir index 3d263e84b..67cd7d1b4 100644 --- a/tests/gold/test_when_memory_Bits8.mlir +++ b/tests/gold/test_when_memory_Bits8.mlir @@ -1,6 +1,6 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @Memory(%RADDR: i5, %CLK: i1, %WADDR: i5, %WDATA: i8, %WE: i1) -> (RDATA: i8) { - %1 = sv.reg {name = "coreir_mem32x8_inst0"} : !hw.inout> + %1 = sv.reg {name = "coreir_mem"} : !hw.inout> %2 = sv.array_index_inout %1[%RADDR] : !hw.inout>, i5 %0 = sv.read_inout %2 : !hw.inout %3 = sv.array_index_inout %1[%WADDR] : !hw.inout>, i5 diff --git a/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir b/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir index 1dceb7140..81dd16e5b 100644 --- a/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir +++ b/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir @@ -8,7 +8,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { %5 = comb.extract %WDATA_y from 5 : (i7) -> i1 %6 = comb.extract %WDATA_y from 6 : (i7) -> i1 %7 = comb.concat %6, %5, %4, %3, %2, %1, %0, %WDATA_x : i1, i1, i1, i1, i1, i1, i1, i1 - %9 = sv.reg {name = "coreir_mem32x8_inst0"} : !hw.inout> + %9 = sv.reg {name = "coreir_mem"} : !hw.inout> %10 = sv.array_index_inout %9[%RADDR] : !hw.inout>, i5 %8 = sv.read_inout %10 : !hw.inout %11 = sv.array_index_inout %9[%WADDR] : !hw.inout>, i5 diff --git a/tests/gold/test_when_user_reg.mlir b/tests/gold/test_when_user_reg.mlir index b55833270..80544c0c4 100644 --- a/tests/gold/test_when_user_reg.mlir +++ b/tests/gold/test_when_user_reg.mlir @@ -9,7 +9,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i8 } } - %0 = hw.instance "x" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) + %0 = hw.instance "Register_inst0" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) hw.output %0 : i8 } } diff --git a/tests/gold/test_when_user_reg_enable.mlir b/tests/gold/test_when_user_reg_enable.mlir index 3d08213cc..7e3537e53 100644 --- a/tests/gold/test_when_user_reg_enable.mlir +++ b/tests/gold/test_when_user_reg_enable.mlir @@ -84,7 +84,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } } %49 = comb.concat %38, %37, %36, %35, %34, %33, %32, %31 : i1, i1, i1, i1, i1, i1, i1, i1 - %21 = hw.instance "x" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) + %21 = hw.instance "Register_inst0" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) hw.output %21 : i8 } } diff --git a/tests/test_circuit/gold/test_circuit_add_default_clock.v b/tests/test_circuit/gold/test_circuit_add_default_clock.v index cb1c94d60..abaa77849 100644 --- a/tests/test_circuit/gold/test_circuit_add_default_clock.v +++ b/tests/test_circuit/gold/test_circuit_add_default_clock.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Foo ( diff --git a/tests/test_issues/gold/test_708_inline_False.v b/tests/test_issues/gold/test_708_inline_False.v index 967dcb2e1..40aefd4ef 100644 --- a/tests/test_issues/gold/test_708_inline_False.v +++ b/tests/test_issues/gold/test_708_inline_False.v @@ -52,14 +52,14 @@ module Mux2xTuplex_UInt8 ( output [7:0] O_x, input S ); -wire [7:0] coreir_commonlib_mux2x8_inst0_out; -commonlib_muxn__N2__width8 coreir_commonlib_mux2x8_inst0 ( +wire [7:0] mux_out; +commonlib_muxn__N2__width8 mux ( .in_data_0(I0_x), .in_data_1(I1_x), .in_sel(S), - .out(coreir_commonlib_mux2x8_inst0_out) + .out(mux_out) ); -assign O_x = coreir_commonlib_mux2x8_inst0_out; +assign O_x = mux_out; endmodule module Test ( diff --git a/tests/test_issues/gold/test_708_inline_True.v b/tests/test_issues/gold/test_708_inline_True.v index 6e363a953..3f50c36fa 100644 --- a/tests/test_issues/gold/test_708_inline_True.v +++ b/tests/test_issues/gold/test_708_inline_True.v @@ -4,16 +4,16 @@ module Mux2xTuplex_UInt8 ( output [7:0] O_x, input S ); -reg [7:0] coreir_commonlib_mux2x8_inst0_out; +reg [7:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x8_inst0_out = I0_x; + mux_out = I0_x; end else begin - coreir_commonlib_mux2x8_inst0_out = I1_x; + mux_out = I1_x; end end -assign O_x = coreir_commonlib_mux2x8_inst0_out; +assign O_x = mux_out; endmodule module Test ( diff --git a/tests/test_operators/gold/TestSetSlice.v b/tests/test_operators/gold/TestSetSlice.v index 28f54a865..5cd0642ec 100644 --- a/tests/test_operators/gold/TestSetSlice.v +++ b/tests/test_operators/gold/TestSetSlice.v @@ -4,16 +4,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module TestSetSlice ( diff --git a/tests/test_operators/gold/TestSlice.v b/tests/test_operators/gold/TestSlice.v index b70d1b0dc..4d5de8bb0 100644 --- a/tests/test_operators/gold/TestSlice.v +++ b/tests/test_operators/gold/TestSlice.v @@ -98,18 +98,18 @@ module Mux4xBits6 ( input [1:0] S, output [5:0] O ); -wire [5:0] coreir_commonlib_mux4x6_inst0_out; -wire [5:0] coreir_commonlib_mux4x6_inst0_in_data [3:0]; -assign coreir_commonlib_mux4x6_inst0_in_data[3] = I3; -assign coreir_commonlib_mux4x6_inst0_in_data[2] = I2; -assign coreir_commonlib_mux4x6_inst0_in_data[1] = I1; -assign coreir_commonlib_mux4x6_inst0_in_data[0] = I0; -commonlib_muxn__N4__width6 coreir_commonlib_mux4x6_inst0 ( - .in_data(coreir_commonlib_mux4x6_inst0_in_data), +wire [5:0] mux_out; +wire [5:0] mux_in_data [3:0]; +assign mux_in_data[3] = I3; +assign mux_in_data[2] = I2; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N4__width6 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux4x6_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux4x6_inst0_out; +assign O = mux_out; endmodule module TestSlice ( diff --git a/tests/test_primitives/gold/test_basic_mux.v b/tests/test_primitives/gold/test_basic_mux.v index 37b361d12..03bcbec0d 100644 --- a/tests/test_primitives/gold/test_basic_mux.v +++ b/tests/test_primitives/gold/test_basic_mux.v @@ -32,16 +32,16 @@ module Mux2xBit ( input S, output O ); -wire [0:0] coreir_commonlib_mux2x1_inst0_out; -wire [0:0] coreir_commonlib_mux2x1_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0; -commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( - .in_data(coreir_commonlib_mux2x1_inst0_in_data), +wire [0:0] mux_out; +wire [0:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width1 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x1_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module test_basic_mux ( diff --git a/tests/test_primitives/gold/test_basic_mux_arr.v b/tests/test_primitives/gold/test_basic_mux_arr.v index 1abc944ef..0374b7ce0 100644 --- a/tests/test_primitives/gold/test_basic_mux_arr.v +++ b/tests/test_primitives/gold/test_basic_mux_arr.v @@ -4,17 +4,17 @@ module Mux2xArray2_Bits2 ( input S, output [1:0] O [1:0] ); -reg [3:0] coreir_commonlib_mux2x4_inst0_out; +reg [3:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x4_inst0_out = {I0[1],I0[0]}; + mux_out = {I0[1],I0[0]}; end else begin - coreir_commonlib_mux2x4_inst0_out = {I1[1],I1[0]}; + mux_out = {I1[1],I1[0]}; end end -assign O[1] = {coreir_commonlib_mux2x4_inst0_out[3],coreir_commonlib_mux2x4_inst0_out[2]}; -assign O[0] = {coreir_commonlib_mux2x4_inst0_out[1],coreir_commonlib_mux2x4_inst0_out[0]}; +assign O[1] = {mux_out[3],mux_out[2]}; +assign O[0] = {mux_out[1],mux_out[0]}; endmodule module test_basic_mux_arr ( diff --git a/tests/test_primitives/gold/test_basic_mux_bits.v b/tests/test_primitives/gold/test_basic_mux_bits.v index 1d2f068cc..6ba3a2a03 100644 --- a/tests/test_primitives/gold/test_basic_mux_bits.v +++ b/tests/test_primitives/gold/test_basic_mux_bits.v @@ -32,16 +32,16 @@ module Mux2xBits2 ( input S, output [1:0] O ); -wire [1:0] coreir_commonlib_mux2x2_inst0_out; -wire [1:0] coreir_commonlib_mux2x2_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x2_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x2_inst0_in_data[0] = I0; -commonlib_muxn__N2__width2 coreir_commonlib_mux2x2_inst0 ( - .in_data(coreir_commonlib_mux2x2_inst0_in_data), +wire [1:0] mux_out; +wire [1:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width2 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x2_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x2_inst0_out; +assign O = mux_out; endmodule module test_basic_mux_bits ( diff --git a/tests/test_primitives/gold/test_basic_mux_product.v b/tests/test_primitives/gold/test_basic_mux_product.v index 623489b06..d4013ec25 100644 --- a/tests/test_primitives/gold/test_basic_mux_product.v +++ b/tests/test_primitives/gold/test_basic_mux_product.v @@ -7,17 +7,17 @@ module Mux2xTupleX_Bits2_Y_Bits4 ( output [3:0] O_Y, input S ); -reg [5:0] coreir_commonlib_mux2x6_inst0_out; +reg [5:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x6_inst0_out = {I0_Y,I0_X}; + mux_out = {I0_Y,I0_X}; end else begin - coreir_commonlib_mux2x6_inst0_out = {I1_Y,I1_X}; + mux_out = {I1_Y,I1_X}; end end -assign O_X = {coreir_commonlib_mux2x6_inst0_out[1],coreir_commonlib_mux2x6_inst0_out[0]}; -assign O_Y = {coreir_commonlib_mux2x6_inst0_out[5],coreir_commonlib_mux2x6_inst0_out[4],coreir_commonlib_mux2x6_inst0_out[3],coreir_commonlib_mux2x6_inst0_out[2]}; +assign O_X = {mux_out[1],mux_out[0]}; +assign O_Y = {mux_out[5],mux_out[4],mux_out[3],mux_out[2]}; endmodule module test_basic_mux_product ( diff --git a/tests/test_primitives/gold/test_basic_mux_tuple.v b/tests/test_primitives/gold/test_basic_mux_tuple.v index 64668e707..3cca81d03 100644 --- a/tests/test_primitives/gold/test_basic_mux_tuple.v +++ b/tests/test_primitives/gold/test_basic_mux_tuple.v @@ -7,17 +7,17 @@ module Mux2xTupleBit_Bits2 ( output [1:0] O__1, input S ); -reg [2:0] coreir_commonlib_mux2x3_inst0_out; +reg [2:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x3_inst0_out = {I0__1,I0__0}; + mux_out = {I0__1,I0__0}; end else begin - coreir_commonlib_mux2x3_inst0_out = {I1__1,I1__0}; + mux_out = {I1__1,I1__0}; end end -assign O__0 = coreir_commonlib_mux2x3_inst0_out[0]; -assign O__1 = {coreir_commonlib_mux2x3_inst0_out[2],coreir_commonlib_mux2x3_inst0_out[1]}; +assign O__0 = mux_out[0]; +assign O__1 = {mux_out[2],mux_out[1]}; endmodule module test_basic_mux_tuple ( diff --git a/tests/test_primitives/gold/test_basic_reg_AbstractBitVectorMeta.v b/tests/test_primitives/gold/test_basic_reg_AbstractBitVectorMeta.v index 5341528a2..b5dc5b469 100644 --- a/tests/test_primitives/gold/test_basic_reg_AbstractBitVectorMeta.v +++ b/tests/test_primitives/gold/test_basic_reg_AbstractBitVectorMeta.v @@ -59,16 +59,16 @@ module Mux2xBits8 ( input S, output [7:0] O ); -wire [7:0] coreir_commonlib_mux2x8_inst0_out; -wire [7:0] coreir_commonlib_mux2x8_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x8_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x8_inst0_in_data[0] = I0; -commonlib_muxn__N2__width8 coreir_commonlib_mux2x8_inst0 ( - .in_data(coreir_commonlib_mux2x8_inst0_in_data), +wire [7:0] mux_out; +wire [7:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width8 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x8_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x8_inst0_out; +assign O = mux_out; endmodule module Register ( @@ -78,30 +78,30 @@ module Register ( input RESET ); wire [7:0] Mux2xBits8_inst0_O; +wire [7:0] _reg_out; wire [7:0] const_222_8_out; -wire [7:0] reg_P8_inst0_out; Mux2xBits8 Mux2xBits8_inst0 ( .I0(I), .I1(const_222_8_out), .S(RESET), .O(Mux2xBits8_inst0_O) ); -coreir_const #( - .value(8'hde), - .width(8) -) const_222_8 ( - .out(const_222_8_out) -); coreir_reg #( .clk_posedge(1'b1), .init(8'hde), .width(8) -) reg_P8_inst0 ( +) _reg ( .clk(CLK), .in(Mux2xBits8_inst0_O), - .out(reg_P8_inst0_out) + .out(_reg_out) +); +coreir_const #( + .value(8'hde), + .width(8) +) const_222_8 ( + .out(const_222_8_out) ); -assign O = reg_P8_inst0_out; +assign O = _reg_out; endmodule module test_basic_reg_AbstractBitVectorMeta ( diff --git a/tests/test_primitives/gold/test_basic_reg_BitsMeta.v b/tests/test_primitives/gold/test_basic_reg_BitsMeta.v index 9929f67c5..ab42f83c4 100644 --- a/tests/test_primitives/gold/test_basic_reg_BitsMeta.v +++ b/tests/test_primitives/gold/test_basic_reg_BitsMeta.v @@ -59,16 +59,16 @@ module Mux2xBits8 ( input S, output [7:0] O ); -wire [7:0] coreir_commonlib_mux2x8_inst0_out; -wire [7:0] coreir_commonlib_mux2x8_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x8_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x8_inst0_in_data[0] = I0; -commonlib_muxn__N2__width8 coreir_commonlib_mux2x8_inst0 ( - .in_data(coreir_commonlib_mux2x8_inst0_in_data), +wire [7:0] mux_out; +wire [7:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width8 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x8_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x8_inst0_out; +assign O = mux_out; endmodule module Register ( @@ -78,30 +78,30 @@ module Register ( input RESET ); wire [7:0] Mux2xBits8_inst0_O; +wire [7:0] _reg_out; wire [7:0] const_222_8_out; -wire [7:0] reg_P8_inst0_out; Mux2xBits8 Mux2xBits8_inst0 ( .I0(I), .I1(const_222_8_out), .S(RESET), .O(Mux2xBits8_inst0_O) ); -coreir_const #( - .value(8'hde), - .width(8) -) const_222_8 ( - .out(const_222_8_out) -); coreir_reg #( .clk_posedge(1'b1), .init(8'hde), .width(8) -) reg_P8_inst0 ( +) _reg ( .clk(CLK), .in(Mux2xBits8_inst0_O), - .out(reg_P8_inst0_out) + .out(_reg_out) +); +coreir_const #( + .value(8'hde), + .width(8) +) const_222_8 ( + .out(const_222_8_out) ); -assign O = reg_P8_inst0_out; +assign O = _reg_out; endmodule module test_basic_reg_BitsMeta ( diff --git a/tests/test_primitives/gold/test_basic_reg_function.v b/tests/test_primitives/gold/test_basic_reg_function.v index 761eaad23..59b9946ea 100644 --- a/tests/test_primitives/gold/test_basic_reg_function.v +++ b/tests/test_primitives/gold/test_basic_reg_function.v @@ -59,16 +59,16 @@ module Mux2xBits8 ( input S, output [7:0] O ); -wire [7:0] coreir_commonlib_mux2x8_inst0_out; -wire [7:0] coreir_commonlib_mux2x8_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x8_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x8_inst0_in_data[0] = I0; -commonlib_muxn__N2__width8 coreir_commonlib_mux2x8_inst0 ( - .in_data(coreir_commonlib_mux2x8_inst0_in_data), +wire [7:0] mux_out; +wire [7:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width8 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x8_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x8_inst0_out; +assign O = mux_out; endmodule module Register ( @@ -78,30 +78,30 @@ module Register ( input RESET ); wire [7:0] Mux2xBits8_inst0_O; +wire [7:0] _reg_out; wire [7:0] const_222_8_out; -wire [7:0] reg_P8_inst0_out; Mux2xBits8 Mux2xBits8_inst0 ( .I0(I), .I1(const_222_8_out), .S(RESET), .O(Mux2xBits8_inst0_O) ); -coreir_const #( - .value(8'hde), - .width(8) -) const_222_8 ( - .out(const_222_8_out) -); coreir_reg #( .clk_posedge(1'b1), .init(8'hde), .width(8) -) reg_P8_inst0 ( +) _reg ( .clk(CLK), .in(Mux2xBits8_inst0_O), - .out(reg_P8_inst0_out) + .out(_reg_out) +); +coreir_const #( + .value(8'hde), + .width(8) +) const_222_8 ( + .out(const_222_8_out) ); -assign O = reg_P8_inst0_out; +assign O = _reg_out; endmodule module test_basic_reg ( diff --git a/tests/test_primitives/gold/test_enable_reg.v b/tests/test_primitives/gold/test_enable_reg.v index e6aceeed4..1193a6bd2 100644 --- a/tests/test_primitives/gold/test_enable_reg.v +++ b/tests/test_primitives/gold/test_enable_reg.v @@ -59,16 +59,16 @@ module Mux2xBits8 ( input S, output [7:0] O ); -wire [7:0] coreir_commonlib_mux2x8_inst0_out; -wire [7:0] coreir_commonlib_mux2x8_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x8_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x8_inst0_in_data[0] = I0; -commonlib_muxn__N2__width8 coreir_commonlib_mux2x8_inst0 ( - .in_data(coreir_commonlib_mux2x8_inst0_in_data), +wire [7:0] mux_out; +wire [7:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width8 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x8_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x8_inst0_out; +assign O = mux_out; endmodule module Register ( @@ -79,15 +79,24 @@ module Register ( input RESET ); wire [7:0] Mux2xBits8_inst0_O; +wire [7:0] _reg_out; wire [7:0] const_222_8_out; wire [7:0] enable_mux_O; -wire [7:0] reg_P8_inst0_out; Mux2xBits8 Mux2xBits8_inst0 ( .I0(enable_mux_O), .I1(const_222_8_out), .S(RESET), .O(Mux2xBits8_inst0_O) ); +coreir_reg #( + .clk_posedge(1'b1), + .init(8'hde), + .width(8) +) _reg ( + .clk(CLK), + .in(Mux2xBits8_inst0_O), + .out(_reg_out) +); coreir_const #( .value(8'hde), .width(8) @@ -95,21 +104,12 @@ coreir_const #( .out(const_222_8_out) ); Mux2xBits8 enable_mux ( - .I0(reg_P8_inst0_out), + .I0(_reg_out), .I1(I), .S(CE), .O(enable_mux_O) ); -coreir_reg #( - .clk_posedge(1'b1), - .init(8'hde), - .width(8) -) reg_P8_inst0 ( - .clk(CLK), - .in(Mux2xBits8_inst0_O), - .out(reg_P8_inst0_out) -); -assign O = reg_P8_inst0_out; +assign O = _reg_out; endmodule module test_enable_reg ( diff --git a/tests/test_primitives/gold/test_memory_arr.v b/tests/test_primitives/gold/test_memory_arr.v index 26604c101..21b4400da 100644 --- a/tests/test_primitives/gold/test_memory_arr.v +++ b/tests/test_primitives/gold/test_memory_arr.v @@ -54,26 +54,26 @@ module Memory ( input [4:0] WDATA_1_Y, input WE ); -wire [11:0] coreir_mem4x12_inst0_rdata; -wire [11:0] coreir_mem4x12_inst0_wdata; -assign coreir_mem4x12_inst0_wdata = {WDATA_1_Y,WDATA_1_X,WDATA_0_Y,WDATA_0_X}; +wire [11:0] coreir_mem_rdata; +wire [11:0] coreir_mem_wdata; +assign coreir_mem_wdata = {WDATA_1_Y,WDATA_1_X,WDATA_0_Y,WDATA_0_X}; coreir_mem #( .depth(4), .has_init(1'b0), .sync_read(1'b0), .width(12) -) coreir_mem4x12_inst0 ( +) coreir_mem ( .clk(CLK), - .wdata(coreir_mem4x12_inst0_wdata), + .wdata(coreir_mem_wdata), .waddr(WADDR), .wen(WE), - .rdata(coreir_mem4x12_inst0_rdata), + .rdata(coreir_mem_rdata), .raddr(RADDR) ); -assign RDATA_0_X = coreir_mem4x12_inst0_rdata[0]; -assign RDATA_0_Y = {coreir_mem4x12_inst0_rdata[5],coreir_mem4x12_inst0_rdata[4],coreir_mem4x12_inst0_rdata[3],coreir_mem4x12_inst0_rdata[2],coreir_mem4x12_inst0_rdata[1]}; -assign RDATA_1_X = coreir_mem4x12_inst0_rdata[6]; -assign RDATA_1_Y = {coreir_mem4x12_inst0_rdata[11],coreir_mem4x12_inst0_rdata[10],coreir_mem4x12_inst0_rdata[9],coreir_mem4x12_inst0_rdata[8],coreir_mem4x12_inst0_rdata[7]}; +assign RDATA_0_X = coreir_mem_rdata[0]; +assign RDATA_0_Y = {coreir_mem_rdata[5],coreir_mem_rdata[4],coreir_mem_rdata[3],coreir_mem_rdata[2],coreir_mem_rdata[1]}; +assign RDATA_1_X = coreir_mem_rdata[6]; +assign RDATA_1_Y = {coreir_mem_rdata[11],coreir_mem_rdata[10],coreir_mem_rdata[9],coreir_mem_rdata[8],coreir_mem_rdata[7]}; endmodule module test_memory_arr ( diff --git a/tests/test_primitives/gold/test_memory_basic.mlir b/tests/test_primitives/gold/test_memory_basic.mlir index a5e5b9ce2..931b438f9 100644 --- a/tests/test_primitives/gold/test_memory_basic.mlir +++ b/tests/test_primitives/gold/test_memory_basic.mlir @@ -1,6 +1,6 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @Memory(%RADDR: i2, %CLK: i1, %WADDR: i2, %WDATA: i5, %WE: i1) -> (RDATA: i5) { - %1 = sv.reg {name = "coreir_mem4x5_inst0"} : !hw.inout> + %1 = sv.reg {name = "coreir_mem"} : !hw.inout> %2 = sv.array_index_inout %1[%RADDR] : !hw.inout>, i2 %0 = sv.read_inout %2 : !hw.inout %3 = sv.array_index_inout %1[%WADDR] : !hw.inout>, i2 diff --git a/tests/test_primitives/gold/test_memory_product.v b/tests/test_primitives/gold/test_memory_product.v index 3a3f3dc20..9e1a0a0b5 100644 --- a/tests/test_primitives/gold/test_memory_product.v +++ b/tests/test_primitives/gold/test_memory_product.v @@ -50,24 +50,24 @@ module Memory ( input [4:0] WDATA_Y, input WE ); -wire [5:0] coreir_mem4x6_inst0_rdata; -wire [5:0] coreir_mem4x6_inst0_wdata; -assign coreir_mem4x6_inst0_wdata = {WDATA_Y,WDATA_X}; +wire [5:0] coreir_mem_rdata; +wire [5:0] coreir_mem_wdata; +assign coreir_mem_wdata = {WDATA_Y,WDATA_X}; coreir_mem #( .depth(4), .has_init(1'b0), .sync_read(1'b0), .width(6) -) coreir_mem4x6_inst0 ( +) coreir_mem ( .clk(CLK), - .wdata(coreir_mem4x6_inst0_wdata), + .wdata(coreir_mem_wdata), .waddr(WADDR), .wen(WE), - .rdata(coreir_mem4x6_inst0_rdata), + .rdata(coreir_mem_rdata), .raddr(RADDR) ); -assign RDATA_X = coreir_mem4x6_inst0_rdata[0]; -assign RDATA_Y = {coreir_mem4x6_inst0_rdata[5],coreir_mem4x6_inst0_rdata[4],coreir_mem4x6_inst0_rdata[3],coreir_mem4x6_inst0_rdata[2],coreir_mem4x6_inst0_rdata[1]}; +assign RDATA_X = coreir_mem_rdata[0]; +assign RDATA_Y = {coreir_mem_rdata[5],coreir_mem_rdata[4],coreir_mem_rdata[3],coreir_mem_rdata[2],coreir_mem_rdata[1]}; endmodule module test_memory_product ( diff --git a/tests/test_primitives/gold/test_memory_product_init.v b/tests/test_primitives/gold/test_memory_product_init.v index 5bad4a38e..15ae49d83 100644 --- a/tests/test_primitives/gold/test_memory_product_init.v +++ b/tests/test_primitives/gold/test_memory_product_init.v @@ -46,23 +46,23 @@ module Memory ( output [7:0] RDATA_X, output [7:0] RDATA_Y ); -wire [15:0] coreir_mem4x16_inst0_rdata; +wire [15:0] coreir_mem_rdata; coreir_mem #( .init({16'd127,16'd65535,16'd32640,16'd32768}), .depth(4), .has_init(1'b1), .sync_read(1'b0), .width(16) -) coreir_mem4x16_inst0 ( +) coreir_mem ( .clk(CLK), .wdata(16'h0000), .waddr(2'h0), .wen(1'b0), - .rdata(coreir_mem4x16_inst0_rdata), + .rdata(coreir_mem_rdata), .raddr(RADDR) ); -assign RDATA_X = {coreir_mem4x16_inst0_rdata[7],coreir_mem4x16_inst0_rdata[6],coreir_mem4x16_inst0_rdata[5],coreir_mem4x16_inst0_rdata[4],coreir_mem4x16_inst0_rdata[3],coreir_mem4x16_inst0_rdata[2],coreir_mem4x16_inst0_rdata[1],coreir_mem4x16_inst0_rdata[0]}; -assign RDATA_Y = {coreir_mem4x16_inst0_rdata[15],coreir_mem4x16_inst0_rdata[14],coreir_mem4x16_inst0_rdata[13],coreir_mem4x16_inst0_rdata[12],coreir_mem4x16_inst0_rdata[11],coreir_mem4x16_inst0_rdata[10],coreir_mem4x16_inst0_rdata[9],coreir_mem4x16_inst0_rdata[8]}; +assign RDATA_X = {coreir_mem_rdata[7],coreir_mem_rdata[6],coreir_mem_rdata[5],coreir_mem_rdata[4],coreir_mem_rdata[3],coreir_mem_rdata[2],coreir_mem_rdata[1],coreir_mem_rdata[0]}; +assign RDATA_Y = {coreir_mem_rdata[15],coreir_mem_rdata[14],coreir_mem_rdata[13],coreir_mem_rdata[12],coreir_mem_rdata[11],coreir_mem_rdata[10],coreir_mem_rdata[9],coreir_mem_rdata[8]}; endmodule module test_memory_product_init ( diff --git a/tests/test_primitives/gold/test_memory_read_latency_False.v b/tests/test_primitives/gold/test_memory_read_latency_False.v index 59c76ca83..f4ed92922 100644 --- a/tests/test_primitives/gold/test_memory_read_latency_False.v +++ b/tests/test_primitives/gold/test_memory_read_latency_False.v @@ -95,16 +95,16 @@ module Mux2xBits5 ( input S, output [4:0] O ); -wire [4:0] coreir_commonlib_mux2x5_inst0_out; -wire [4:0] coreir_commonlib_mux2x5_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x5_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x5_inst0_in_data[0] = I0; -commonlib_muxn__N2__width5 coreir_commonlib_mux2x5_inst0 ( - .in_data(coreir_commonlib_mux2x5_inst0_in_data), +wire [4:0] mux_out; +wire [4:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width5 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x5_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x5_inst0_out; +assign O = mux_out; endmodule module Register ( @@ -113,24 +113,24 @@ module Register ( input CE, input CLK ); +wire [4:0] _reg_out; wire [4:0] enable_mux_O; -wire [4:0] reg_P5_inst0_out; -Mux2xBits5 enable_mux ( - .I0(reg_P5_inst0_out), - .I1(I), - .S(CE), - .O(enable_mux_O) -); coreir_reg #( .clk_posedge(1'b1), .init(5'h00), .width(5) -) reg_P5_inst0 ( +) _reg ( .clk(CLK), .in(enable_mux_O), - .out(reg_P5_inst0_out) + .out(_reg_out) +); +Mux2xBits5 enable_mux ( + .I0(_reg_out), + .I1(I), + .S(CE), + .O(enable_mux_O) ); -assign O = reg_P5_inst0_out; +assign O = _reg_out; endmodule module Memory ( @@ -143,9 +143,9 @@ module Memory ( ); wire [4:0] Register_inst0_O; wire bit_const_1_None_out; -wire [4:0] coreir_mem4x5_inst0_rdata; +wire [4:0] coreir_mem_rdata; Register Register_inst0 ( - .I(coreir_mem4x5_inst0_rdata), + .I(coreir_mem_rdata), .O(Register_inst0_O), .CE(bit_const_1_None_out), .CLK(CLK) @@ -159,12 +159,12 @@ coreir_sync_read_mem #( .depth(4), .has_init(1'b0), .width(5) -) coreir_mem4x5_inst0 ( +) coreir_mem ( .clk(CLK), .wdata(WDATA), .waddr(WADDR), .wen(WE), - .rdata(coreir_mem4x5_inst0_rdata), + .rdata(coreir_mem_rdata), .ren(bit_const_1_None_out), .raddr(RADDR) ); diff --git a/tests/test_primitives/gold/test_memory_read_latency_True.v b/tests/test_primitives/gold/test_memory_read_latency_True.v index e61ce1bbf..fa0ec723a 100644 --- a/tests/test_primitives/gold/test_memory_read_latency_True.v +++ b/tests/test_primitives/gold/test_memory_read_latency_True.v @@ -87,16 +87,16 @@ module Mux2xBits5 ( input S, output [4:0] O ); -wire [4:0] coreir_commonlib_mux2x5_inst0_out; -wire [4:0] coreir_commonlib_mux2x5_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x5_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x5_inst0_in_data[0] = I0; -commonlib_muxn__N2__width5 coreir_commonlib_mux2x5_inst0 ( - .in_data(coreir_commonlib_mux2x5_inst0_in_data), +wire [4:0] mux_out; +wire [4:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width5 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x5_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x5_inst0_out; +assign O = mux_out; endmodule module Register ( @@ -105,24 +105,24 @@ module Register ( input CE, input CLK ); +wire [4:0] _reg_out; wire [4:0] enable_mux_O; -wire [4:0] reg_P5_inst0_out; -Mux2xBits5 enable_mux ( - .I0(reg_P5_inst0_out), - .I1(I), - .S(CE), - .O(enable_mux_O) -); coreir_reg #( .clk_posedge(1'b1), .init(5'h00), .width(5) -) reg_P5_inst0 ( +) _reg ( .clk(CLK), .in(enable_mux_O), - .out(reg_P5_inst0_out) + .out(_reg_out) +); +Mux2xBits5 enable_mux ( + .I0(_reg_out), + .I1(I), + .S(CE), + .O(enable_mux_O) ); -assign O = reg_P5_inst0_out; +assign O = _reg_out; endmodule module Memory ( @@ -135,9 +135,9 @@ module Memory ( input WE ); wire [4:0] Register_inst0_O; -wire [4:0] coreir_mem4x5_inst0_rdata; +wire [4:0] coreir_mem_rdata; Register Register_inst0 ( - .I(coreir_mem4x5_inst0_rdata), + .I(coreir_mem_rdata), .O(Register_inst0_O), .CE(RE), .CLK(CLK) @@ -146,12 +146,12 @@ coreir_sync_read_mem #( .depth(4), .has_init(1'b0), .width(5) -) coreir_mem4x5_inst0 ( +) coreir_mem ( .clk(CLK), .wdata(WDATA), .waddr(WADDR), .wen(WE), - .rdata(coreir_mem4x5_inst0_rdata), + .rdata(coreir_mem_rdata), .ren(RE), .raddr(RADDR) ); diff --git a/tests/test_primitives/gold/test_memory_read_only.v b/tests/test_primitives/gold/test_memory_read_only.v index 8a76c364b..22b9e87db 100644 --- a/tests/test_primitives/gold/test_memory_read_only.v +++ b/tests/test_primitives/gold/test_memory_read_only.v @@ -65,7 +65,7 @@ module Memory ( wire bit_const_0_None_out; wire [1:0] const_0_2_out; wire [4:0] const_0_5_out; -wire [4:0] coreir_mem4x5_inst0_rdata; +wire [4:0] coreir_mem_rdata; corebit_const #( .value(1'b0) ) bit_const_0_None ( @@ -89,15 +89,15 @@ coreir_mem #( .has_init(1'b1), .sync_read(1'b0), .width(5) -) coreir_mem4x5_inst0 ( +) coreir_mem ( .clk(CLK), .wdata(const_0_5_out), .waddr(const_0_2_out), .wen(bit_const_0_None_out), - .rdata(coreir_mem4x5_inst0_rdata), + .rdata(coreir_mem_rdata), .raddr(RADDR) ); -assign RDATA = coreir_mem4x5_inst0_rdata; +assign RDATA = coreir_mem_rdata; endmodule module test_memory_read_only ( diff --git a/tests/test_primitives/gold/test_mux_operator.v b/tests/test_primitives/gold/test_mux_operator.v index 8b394937e..7935bd67a 100644 --- a/tests/test_primitives/gold/test_mux_operator.v +++ b/tests/test_primitives/gold/test_mux_operator.v @@ -32,16 +32,16 @@ module Mux2xBit ( input S, output O ); -wire [0:0] coreir_commonlib_mux2x1_inst0_out; -wire [0:0] coreir_commonlib_mux2x1_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0; -commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( - .in_data(coreir_commonlib_mux2x1_inst0_in_data), +wire [0:0] mux_out; +wire [0:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width1 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x1_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module test_mux_operator ( diff --git a/tests/test_primitives/gold/test_mux_operator_int.v b/tests/test_primitives/gold/test_mux_operator_int.v index ac8cc67df..4c15220cc 100644 --- a/tests/test_primitives/gold/test_mux_operator_int.v +++ b/tests/test_primitives/gold/test_mux_operator_int.v @@ -40,16 +40,16 @@ module Mux2xBit ( input S, output O ); -wire [0:0] coreir_commonlib_mux2x1_inst0_out; -wire [0:0] coreir_commonlib_mux2x1_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0; -commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( - .in_data(coreir_commonlib_mux2x1_inst0_in_data), +wire [0:0] mux_out; +wire [0:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width1 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x1_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module test_mux_operator_int ( diff --git a/tests/test_primitives/gold/test_reg_async_resetn.v b/tests/test_primitives/gold/test_reg_async_resetn.v index 395f75ceb..94570d8b1 100644 --- a/tests/test_primitives/gold/test_reg_async_resetn.v +++ b/tests/test_primitives/gold/test_reg_async_resetn.v @@ -27,19 +27,19 @@ module Register ( input CLK, input ASYNCRESETN ); -wire [7:0] reg_PRn8_inst0_out; +wire [7:0] _reg_out; coreir_reg_arst #( .arst_posedge(1'b0), .clk_posedge(1'b1), .init(8'hde), .width(8) -) reg_PRn8_inst0 ( +) _reg ( .clk(CLK), .arst(ASYNCRESETN), .in(I), - .out(reg_PRn8_inst0_out) + .out(_reg_out) ); -assign O = reg_PRn8_inst0_out; +assign O = _reg_out; endmodule module test_reg_async_resetn ( diff --git a/tests/test_primitives/gold/test_reg_of_nested_array.v b/tests/test_primitives/gold/test_reg_of_nested_array.v index 0ef42b068..db1dd6c1a 100644 --- a/tests/test_primitives/gold/test_reg_of_nested_array.v +++ b/tests/test_primitives/gold/test_reg_of_nested_array.v @@ -22,18 +22,18 @@ module Mux2xArray3_Bits8 ( input S, output [7:0] O [2:0] ); -reg [23:0] coreir_commonlib_mux2x24_inst0_out; +reg [23:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x24_inst0_out = {I0[2],I0[1],I0[0]}; + mux_out = {I0[2],I0[1],I0[0]}; end else begin - coreir_commonlib_mux2x24_inst0_out = {I1[2],I1[1],I1[0]}; + mux_out = {I1[2],I1[1],I1[0]}; end end -assign O[2] = {coreir_commonlib_mux2x24_inst0_out[23],coreir_commonlib_mux2x24_inst0_out[22],coreir_commonlib_mux2x24_inst0_out[21],coreir_commonlib_mux2x24_inst0_out[20],coreir_commonlib_mux2x24_inst0_out[19],coreir_commonlib_mux2x24_inst0_out[18],coreir_commonlib_mux2x24_inst0_out[17],coreir_commonlib_mux2x24_inst0_out[16]}; -assign O[1] = {coreir_commonlib_mux2x24_inst0_out[15],coreir_commonlib_mux2x24_inst0_out[14],coreir_commonlib_mux2x24_inst0_out[13],coreir_commonlib_mux2x24_inst0_out[12],coreir_commonlib_mux2x24_inst0_out[11],coreir_commonlib_mux2x24_inst0_out[10],coreir_commonlib_mux2x24_inst0_out[9],coreir_commonlib_mux2x24_inst0_out[8]}; -assign O[0] = {coreir_commonlib_mux2x24_inst0_out[7],coreir_commonlib_mux2x24_inst0_out[6],coreir_commonlib_mux2x24_inst0_out[5],coreir_commonlib_mux2x24_inst0_out[4],coreir_commonlib_mux2x24_inst0_out[3],coreir_commonlib_mux2x24_inst0_out[2],coreir_commonlib_mux2x24_inst0_out[1],coreir_commonlib_mux2x24_inst0_out[0]}; +assign O[2] = {mux_out[23],mux_out[22],mux_out[21],mux_out[20],mux_out[19],mux_out[18],mux_out[17],mux_out[16]}; +assign O[1] = {mux_out[15],mux_out[14],mux_out[13],mux_out[12],mux_out[11],mux_out[10],mux_out[9],mux_out[8]}; +assign O[0] = {mux_out[7],mux_out[6],mux_out[5],mux_out[4],mux_out[3],mux_out[2],mux_out[1],mux_out[0]}; endmodule module Register ( @@ -43,7 +43,7 @@ module Register ( input RESET ); wire [7:0] Mux2xArray3_Bits8_inst0_O [2:0]; -wire [23:0] reg_P24_inst0_out; +wire [23:0] _reg_out; wire [7:0] Mux2xArray3_Bits8_inst0_I0 [2:0]; assign Mux2xArray3_Bits8_inst0_I0[2] = I[2]; assign Mux2xArray3_Bits8_inst0_I0[1] = I[1]; @@ -58,20 +58,20 @@ Mux2xArray3_Bits8 Mux2xArray3_Bits8_inst0 ( .S(RESET), .O(Mux2xArray3_Bits8_inst0_O) ); -wire [23:0] reg_P24_inst0_in; -assign reg_P24_inst0_in = {Mux2xArray3_Bits8_inst0_O[2],Mux2xArray3_Bits8_inst0_O[1],Mux2xArray3_Bits8_inst0_O[0]}; +wire [23:0] _reg_in; +assign _reg_in = {Mux2xArray3_Bits8_inst0_O[2],Mux2xArray3_Bits8_inst0_O[1],Mux2xArray3_Bits8_inst0_O[0]}; coreir_reg #( .clk_posedge(1'b1), .init(24'hbeadde), .width(24) -) reg_P24_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P24_inst0_in), - .out(reg_P24_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O[2] = {reg_P24_inst0_out[23],reg_P24_inst0_out[22],reg_P24_inst0_out[21],reg_P24_inst0_out[20],reg_P24_inst0_out[19],reg_P24_inst0_out[18],reg_P24_inst0_out[17],reg_P24_inst0_out[16]}; -assign O[1] = {reg_P24_inst0_out[15],reg_P24_inst0_out[14],reg_P24_inst0_out[13],reg_P24_inst0_out[12],reg_P24_inst0_out[11],reg_P24_inst0_out[10],reg_P24_inst0_out[9],reg_P24_inst0_out[8]}; -assign O[0] = {reg_P24_inst0_out[7],reg_P24_inst0_out[6],reg_P24_inst0_out[5],reg_P24_inst0_out[4],reg_P24_inst0_out[3],reg_P24_inst0_out[2],reg_P24_inst0_out[1],reg_P24_inst0_out[0]}; +assign O[2] = {_reg_out[23],_reg_out[22],_reg_out[21],_reg_out[20],_reg_out[19],_reg_out[18],_reg_out[17],_reg_out[16]}; +assign O[1] = {_reg_out[15],_reg_out[14],_reg_out[13],_reg_out[12],_reg_out[11],_reg_out[10],_reg_out[9],_reg_out[8]}; +assign O[0] = {_reg_out[7],_reg_out[6],_reg_out[5],_reg_out[4],_reg_out[3],_reg_out[2],_reg_out[1],_reg_out[0]}; endmodule module test_reg_of_nested_array ( diff --git a/tests/test_primitives/gold/test_reg_of_product.v b/tests/test_primitives/gold/test_reg_of_product.v index 50002c51d..8707059cb 100644 --- a/tests/test_primitives/gold/test_reg_of_product.v +++ b/tests/test_primitives/gold/test_reg_of_product.v @@ -25,17 +25,17 @@ module Mux2xTuplex_Bits8_y_Bits4 ( output [3:0] O_y, input S ); -reg [11:0] coreir_commonlib_mux2x12_inst0_out; +reg [11:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x12_inst0_out = {I0_y,I0_x}; + mux_out = {I0_y,I0_x}; end else begin - coreir_commonlib_mux2x12_inst0_out = {I1_y,I1_x}; + mux_out = {I1_y,I1_x}; end end -assign O_x = {coreir_commonlib_mux2x12_inst0_out[7],coreir_commonlib_mux2x12_inst0_out[6],coreir_commonlib_mux2x12_inst0_out[5],coreir_commonlib_mux2x12_inst0_out[4],coreir_commonlib_mux2x12_inst0_out[3],coreir_commonlib_mux2x12_inst0_out[2],coreir_commonlib_mux2x12_inst0_out[1],coreir_commonlib_mux2x12_inst0_out[0]}; -assign O_y = {coreir_commonlib_mux2x12_inst0_out[11],coreir_commonlib_mux2x12_inst0_out[10],coreir_commonlib_mux2x12_inst0_out[9],coreir_commonlib_mux2x12_inst0_out[8]}; +assign O_x = {mux_out[7],mux_out[6],mux_out[5],mux_out[4],mux_out[3],mux_out[2],mux_out[1],mux_out[0]}; +assign O_y = {mux_out[11],mux_out[10],mux_out[9],mux_out[8]}; endmodule module Register ( @@ -48,7 +48,7 @@ module Register ( ); wire [7:0] Mux2xTuplex_Bits8_y_Bits4_inst0_O_x; wire [3:0] Mux2xTuplex_Bits8_y_Bits4_inst0_O_y; -wire [11:0] reg_P12_inst0_out; +wire [11:0] _reg_out; Mux2xTuplex_Bits8_y_Bits4 Mux2xTuplex_Bits8_y_Bits4_inst0 ( .I0_x(I_x), .I0_y(I_y), @@ -58,19 +58,19 @@ Mux2xTuplex_Bits8_y_Bits4 Mux2xTuplex_Bits8_y_Bits4_inst0 ( .O_y(Mux2xTuplex_Bits8_y_Bits4_inst0_O_y), .S(RESET) ); -wire [11:0] reg_P12_inst0_in; -assign reg_P12_inst0_in = {Mux2xTuplex_Bits8_y_Bits4_inst0_O_y,Mux2xTuplex_Bits8_y_Bits4_inst0_O_x}; +wire [11:0] _reg_in; +assign _reg_in = {Mux2xTuplex_Bits8_y_Bits4_inst0_O_y,Mux2xTuplex_Bits8_y_Bits4_inst0_O_x}; coreir_reg #( .clk_posedge(1'b1), .init(12'hade), .width(12) -) reg_P12_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P12_inst0_in), - .out(reg_P12_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O_x = {reg_P12_inst0_out[7],reg_P12_inst0_out[6],reg_P12_inst0_out[5],reg_P12_inst0_out[4],reg_P12_inst0_out[3],reg_P12_inst0_out[2],reg_P12_inst0_out[1],reg_P12_inst0_out[0]}; -assign O_y = {reg_P12_inst0_out[11],reg_P12_inst0_out[10],reg_P12_inst0_out[9],reg_P12_inst0_out[8]}; +assign O_x = {_reg_out[7],_reg_out[6],_reg_out[5],_reg_out[4],_reg_out[3],_reg_out[2],_reg_out[1],_reg_out[0]}; +assign O_y = {_reg_out[11],_reg_out[10],_reg_out[9],_reg_out[8]}; endmodule module test_reg_of_product ( diff --git a/tests/test_primitives/gold/test_reg_of_product_zero_init.v b/tests/test_primitives/gold/test_reg_of_product_zero_init.v index 739f323ec..00b6f85b4 100644 --- a/tests/test_primitives/gold/test_reg_of_product_zero_init.v +++ b/tests/test_primitives/gold/test_reg_of_product_zero_init.v @@ -25,17 +25,17 @@ module Mux2xTuplex_Bits8_y_Bits4 ( output [3:0] O_y, input S ); -reg [11:0] coreir_commonlib_mux2x12_inst0_out; +reg [11:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x12_inst0_out = {I0_y,I0_x}; + mux_out = {I0_y,I0_x}; end else begin - coreir_commonlib_mux2x12_inst0_out = {I1_y,I1_x}; + mux_out = {I1_y,I1_x}; end end -assign O_x = {coreir_commonlib_mux2x12_inst0_out[7],coreir_commonlib_mux2x12_inst0_out[6],coreir_commonlib_mux2x12_inst0_out[5],coreir_commonlib_mux2x12_inst0_out[4],coreir_commonlib_mux2x12_inst0_out[3],coreir_commonlib_mux2x12_inst0_out[2],coreir_commonlib_mux2x12_inst0_out[1],coreir_commonlib_mux2x12_inst0_out[0]}; -assign O_y = {coreir_commonlib_mux2x12_inst0_out[11],coreir_commonlib_mux2x12_inst0_out[10],coreir_commonlib_mux2x12_inst0_out[9],coreir_commonlib_mux2x12_inst0_out[8]}; +assign O_x = {mux_out[7],mux_out[6],mux_out[5],mux_out[4],mux_out[3],mux_out[2],mux_out[1],mux_out[0]}; +assign O_y = {mux_out[11],mux_out[10],mux_out[9],mux_out[8]}; endmodule module Register ( @@ -48,7 +48,7 @@ module Register ( ); wire [7:0] Mux2xTuplex_Bits8_y_Bits4_inst0_O_x; wire [3:0] Mux2xTuplex_Bits8_y_Bits4_inst0_O_y; -wire [11:0] reg_P12_inst0_out; +wire [11:0] _reg_out; Mux2xTuplex_Bits8_y_Bits4 Mux2xTuplex_Bits8_y_Bits4_inst0 ( .I0_x(I_x), .I0_y(I_y), @@ -58,19 +58,19 @@ Mux2xTuplex_Bits8_y_Bits4 Mux2xTuplex_Bits8_y_Bits4_inst0 ( .O_y(Mux2xTuplex_Bits8_y_Bits4_inst0_O_y), .S(RESET) ); -wire [11:0] reg_P12_inst0_in; -assign reg_P12_inst0_in = {Mux2xTuplex_Bits8_y_Bits4_inst0_O_y,Mux2xTuplex_Bits8_y_Bits4_inst0_O_x}; +wire [11:0] _reg_in; +assign _reg_in = {Mux2xTuplex_Bits8_y_Bits4_inst0_O_y,Mux2xTuplex_Bits8_y_Bits4_inst0_O_x}; coreir_reg #( .clk_posedge(1'b1), .init(12'h000), .width(12) -) reg_P12_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P12_inst0_in), - .out(reg_P12_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O_x = {reg_P12_inst0_out[7],reg_P12_inst0_out[6],reg_P12_inst0_out[5],reg_P12_inst0_out[4],reg_P12_inst0_out[3],reg_P12_inst0_out[2],reg_P12_inst0_out[1],reg_P12_inst0_out[0]}; -assign O_y = {reg_P12_inst0_out[11],reg_P12_inst0_out[10],reg_P12_inst0_out[9],reg_P12_inst0_out[8]}; +assign O_x = {_reg_out[7],_reg_out[6],_reg_out[5],_reg_out[4],_reg_out[3],_reg_out[2],_reg_out[1],_reg_out[0]}; +assign O_y = {_reg_out[11],_reg_out[10],_reg_out[9],_reg_out[8]}; endmodule module test_reg_of_product_zero_init ( diff --git a/tests/test_syntax/gold/TestSequential2ArrOfBits.v b/tests/test_syntax/gold/TestSequential2ArrOfBits.v index d98754b48..3b57898f3 100644 --- a/tests/test_syntax/gold/TestSequential2ArrOfBits.v +++ b/tests/test_syntax/gold/TestSequential2ArrOfBits.v @@ -21,33 +21,33 @@ module Register ( output [6:0] O [14:0], input CLK ); -wire [104:0] reg_P105_inst0_out; -wire [104:0] reg_P105_inst0_in; -assign reg_P105_inst0_in = {I[14],I[13],I[12],I[11],I[10],I[9],I[8],I[7],I[6],I[5],I[4],I[3],I[2],I[1],I[0]}; +wire [104:0] _reg_out; +wire [104:0] _reg_in; +assign _reg_in = {I[14],I[13],I[12],I[11],I[10],I[9],I[8],I[7],I[6],I[5],I[4],I[3],I[2],I[1],I[0]}; coreir_reg #( .clk_posedge(1'b1), .init(105'h000000000000000000000000000), .width(105) -) reg_P105_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P105_inst0_in), - .out(reg_P105_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O[14] = {reg_P105_inst0_out[104],reg_P105_inst0_out[103],reg_P105_inst0_out[102],reg_P105_inst0_out[101],reg_P105_inst0_out[100],reg_P105_inst0_out[99],reg_P105_inst0_out[98]}; -assign O[13] = {reg_P105_inst0_out[97],reg_P105_inst0_out[96],reg_P105_inst0_out[95],reg_P105_inst0_out[94],reg_P105_inst0_out[93],reg_P105_inst0_out[92],reg_P105_inst0_out[91]}; -assign O[12] = {reg_P105_inst0_out[90],reg_P105_inst0_out[89],reg_P105_inst0_out[88],reg_P105_inst0_out[87],reg_P105_inst0_out[86],reg_P105_inst0_out[85],reg_P105_inst0_out[84]}; -assign O[11] = {reg_P105_inst0_out[83],reg_P105_inst0_out[82],reg_P105_inst0_out[81],reg_P105_inst0_out[80],reg_P105_inst0_out[79],reg_P105_inst0_out[78],reg_P105_inst0_out[77]}; -assign O[10] = {reg_P105_inst0_out[76],reg_P105_inst0_out[75],reg_P105_inst0_out[74],reg_P105_inst0_out[73],reg_P105_inst0_out[72],reg_P105_inst0_out[71],reg_P105_inst0_out[70]}; -assign O[9] = {reg_P105_inst0_out[69],reg_P105_inst0_out[68],reg_P105_inst0_out[67],reg_P105_inst0_out[66],reg_P105_inst0_out[65],reg_P105_inst0_out[64],reg_P105_inst0_out[63]}; -assign O[8] = {reg_P105_inst0_out[62],reg_P105_inst0_out[61],reg_P105_inst0_out[60],reg_P105_inst0_out[59],reg_P105_inst0_out[58],reg_P105_inst0_out[57],reg_P105_inst0_out[56]}; -assign O[7] = {reg_P105_inst0_out[55],reg_P105_inst0_out[54],reg_P105_inst0_out[53],reg_P105_inst0_out[52],reg_P105_inst0_out[51],reg_P105_inst0_out[50],reg_P105_inst0_out[49]}; -assign O[6] = {reg_P105_inst0_out[48],reg_P105_inst0_out[47],reg_P105_inst0_out[46],reg_P105_inst0_out[45],reg_P105_inst0_out[44],reg_P105_inst0_out[43],reg_P105_inst0_out[42]}; -assign O[5] = {reg_P105_inst0_out[41],reg_P105_inst0_out[40],reg_P105_inst0_out[39],reg_P105_inst0_out[38],reg_P105_inst0_out[37],reg_P105_inst0_out[36],reg_P105_inst0_out[35]}; -assign O[4] = {reg_P105_inst0_out[34],reg_P105_inst0_out[33],reg_P105_inst0_out[32],reg_P105_inst0_out[31],reg_P105_inst0_out[30],reg_P105_inst0_out[29],reg_P105_inst0_out[28]}; -assign O[3] = {reg_P105_inst0_out[27],reg_P105_inst0_out[26],reg_P105_inst0_out[25],reg_P105_inst0_out[24],reg_P105_inst0_out[23],reg_P105_inst0_out[22],reg_P105_inst0_out[21]}; -assign O[2] = {reg_P105_inst0_out[20],reg_P105_inst0_out[19],reg_P105_inst0_out[18],reg_P105_inst0_out[17],reg_P105_inst0_out[16],reg_P105_inst0_out[15],reg_P105_inst0_out[14]}; -assign O[1] = {reg_P105_inst0_out[13],reg_P105_inst0_out[12],reg_P105_inst0_out[11],reg_P105_inst0_out[10],reg_P105_inst0_out[9],reg_P105_inst0_out[8],reg_P105_inst0_out[7]}; -assign O[0] = {reg_P105_inst0_out[6],reg_P105_inst0_out[5],reg_P105_inst0_out[4],reg_P105_inst0_out[3],reg_P105_inst0_out[2],reg_P105_inst0_out[1],reg_P105_inst0_out[0]}; +assign O[14] = {_reg_out[104],_reg_out[103],_reg_out[102],_reg_out[101],_reg_out[100],_reg_out[99],_reg_out[98]}; +assign O[13] = {_reg_out[97],_reg_out[96],_reg_out[95],_reg_out[94],_reg_out[93],_reg_out[92],_reg_out[91]}; +assign O[12] = {_reg_out[90],_reg_out[89],_reg_out[88],_reg_out[87],_reg_out[86],_reg_out[85],_reg_out[84]}; +assign O[11] = {_reg_out[83],_reg_out[82],_reg_out[81],_reg_out[80],_reg_out[79],_reg_out[78],_reg_out[77]}; +assign O[10] = {_reg_out[76],_reg_out[75],_reg_out[74],_reg_out[73],_reg_out[72],_reg_out[71],_reg_out[70]}; +assign O[9] = {_reg_out[69],_reg_out[68],_reg_out[67],_reg_out[66],_reg_out[65],_reg_out[64],_reg_out[63]}; +assign O[8] = {_reg_out[62],_reg_out[61],_reg_out[60],_reg_out[59],_reg_out[58],_reg_out[57],_reg_out[56]}; +assign O[7] = {_reg_out[55],_reg_out[54],_reg_out[53],_reg_out[52],_reg_out[51],_reg_out[50],_reg_out[49]}; +assign O[6] = {_reg_out[48],_reg_out[47],_reg_out[46],_reg_out[45],_reg_out[44],_reg_out[43],_reg_out[42]}; +assign O[5] = {_reg_out[41],_reg_out[40],_reg_out[39],_reg_out[38],_reg_out[37],_reg_out[36],_reg_out[35]}; +assign O[4] = {_reg_out[34],_reg_out[33],_reg_out[32],_reg_out[31],_reg_out[30],_reg_out[29],_reg_out[28]}; +assign O[3] = {_reg_out[27],_reg_out[26],_reg_out[25],_reg_out[24],_reg_out[23],_reg_out[22],_reg_out[21]}; +assign O[2] = {_reg_out[20],_reg_out[19],_reg_out[18],_reg_out[17],_reg_out[16],_reg_out[15],_reg_out[14]}; +assign O[1] = {_reg_out[13],_reg_out[12],_reg_out[11],_reg_out[10],_reg_out[9],_reg_out[8],_reg_out[7]}; +assign O[0] = {_reg_out[6],_reg_out[5],_reg_out[4],_reg_out[3],_reg_out[2],_reg_out[1],_reg_out[0]}; endmodule module Test2 ( diff --git a/tests/test_syntax/gold/TestSequential2Assign.v b/tests/test_syntax/gold/TestSequential2Assign.v index 30f72d6d9..92f9d8a49 100644 --- a/tests/test_syntax/gold/TestSequential2Assign.v +++ b/tests/test_syntax/gold/TestSequential2Assign.v @@ -21,17 +21,17 @@ module Register ( output [3:0] O, input CLK ); -wire [3:0] reg_P4_inst0_out; +wire [3:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P4_inst0_out) + .out(_reg_out) ); -assign O = reg_P4_inst0_out; +assign O = _reg_out; endmodule module Basic ( diff --git a/tests/test_syntax/gold/TestSequential2Basic.v b/tests/test_syntax/gold/TestSequential2Basic.v index 30f72d6d9..92f9d8a49 100644 --- a/tests/test_syntax/gold/TestSequential2Basic.v +++ b/tests/test_syntax/gold/TestSequential2Basic.v @@ -21,17 +21,17 @@ module Register ( output [3:0] O, input CLK ); -wire [3:0] reg_P4_inst0_out; +wire [3:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P4_inst0_out) + .out(_reg_out) ); -assign O = reg_P4_inst0_out; +assign O = _reg_out; endmodule module Basic ( diff --git a/tests/test_syntax/gold/TestSequential2Counter.v b/tests/test_syntax/gold/TestSequential2Counter.v index e6bd4161b..28ad66508 100644 --- a/tests/test_syntax/gold/TestSequential2Counter.v +++ b/tests/test_syntax/gold/TestSequential2Counter.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(16'h0000), .width(16) -) reg_P16_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) diff --git a/tests/test_syntax/gold/TestSequential2CounterIf.v b/tests/test_syntax/gold/TestSequential2CounterIf.v index 75dbdac83..c570d5c56 100644 --- a/tests/test_syntax/gold/TestSequential2CounterIf.v +++ b/tests/test_syntax/gold/TestSequential2CounterIf.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(16'h0000), .width(16) -) reg_P16_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) @@ -38,16 +38,16 @@ module Mux2x_SequentialRegisterWrapperSInt16 ( input S, output [15:0] O ); -reg [15:0] coreir_commonlib_mux2x16_inst0_out; +reg [15:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x16_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x16_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x16_inst0_out; +assign O = mux_out; endmodule module Test2 ( diff --git a/tests/test_syntax/gold/TestSequential2CustomAnnotations.v b/tests/test_syntax/gold/TestSequential2CustomAnnotations.v index 10f4b0659..e2a8cbe2c 100644 --- a/tests/test_syntax/gold/TestSequential2CustomAnnotations.v +++ b/tests/test_syntax/gold/TestSequential2CustomAnnotations.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) diff --git a/tests/test_syntax/gold/TestSequential2GetItem.v b/tests/test_syntax/gold/TestSequential2GetItem.v index 26ca5eb57..330aeba8f 100644 --- a/tests/test_syntax/gold/TestSequential2GetItem.v +++ b/tests/test_syntax/gold/TestSequential2GetItem.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(3'h0), .width(3) -) reg_P3_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) @@ -37,26 +37,26 @@ module Register ( output [6:0] O [7:0], input CLK ); -wire [55:0] reg_P56_inst0_out; -wire [55:0] reg_P56_inst0_in; -assign reg_P56_inst0_in = {I[7],I[6],I[5],I[4],I[3],I[2],I[1],I[0]}; +wire [55:0] _reg_out; +wire [55:0] _reg_in; +assign _reg_in = {I[7],I[6],I[5],I[4],I[3],I[2],I[1],I[0]}; coreir_reg #( .clk_posedge(1'b1), .init(56'h00000000000000), .width(56) -) reg_P56_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P56_inst0_in), - .out(reg_P56_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O[7] = {reg_P56_inst0_out[55],reg_P56_inst0_out[54],reg_P56_inst0_out[53],reg_P56_inst0_out[52],reg_P56_inst0_out[51],reg_P56_inst0_out[50],reg_P56_inst0_out[49]}; -assign O[6] = {reg_P56_inst0_out[48],reg_P56_inst0_out[47],reg_P56_inst0_out[46],reg_P56_inst0_out[45],reg_P56_inst0_out[44],reg_P56_inst0_out[43],reg_P56_inst0_out[42]}; -assign O[5] = {reg_P56_inst0_out[41],reg_P56_inst0_out[40],reg_P56_inst0_out[39],reg_P56_inst0_out[38],reg_P56_inst0_out[37],reg_P56_inst0_out[36],reg_P56_inst0_out[35]}; -assign O[4] = {reg_P56_inst0_out[34],reg_P56_inst0_out[33],reg_P56_inst0_out[32],reg_P56_inst0_out[31],reg_P56_inst0_out[30],reg_P56_inst0_out[29],reg_P56_inst0_out[28]}; -assign O[3] = {reg_P56_inst0_out[27],reg_P56_inst0_out[26],reg_P56_inst0_out[25],reg_P56_inst0_out[24],reg_P56_inst0_out[23],reg_P56_inst0_out[22],reg_P56_inst0_out[21]}; -assign O[2] = {reg_P56_inst0_out[20],reg_P56_inst0_out[19],reg_P56_inst0_out[18],reg_P56_inst0_out[17],reg_P56_inst0_out[16],reg_P56_inst0_out[15],reg_P56_inst0_out[14]}; -assign O[1] = {reg_P56_inst0_out[13],reg_P56_inst0_out[12],reg_P56_inst0_out[11],reg_P56_inst0_out[10],reg_P56_inst0_out[9],reg_P56_inst0_out[8],reg_P56_inst0_out[7]}; -assign O[0] = {reg_P56_inst0_out[6],reg_P56_inst0_out[5],reg_P56_inst0_out[4],reg_P56_inst0_out[3],reg_P56_inst0_out[2],reg_P56_inst0_out[1],reg_P56_inst0_out[0]}; +assign O[7] = {_reg_out[55],_reg_out[54],_reg_out[53],_reg_out[52],_reg_out[51],_reg_out[50],_reg_out[49]}; +assign O[6] = {_reg_out[48],_reg_out[47],_reg_out[46],_reg_out[45],_reg_out[44],_reg_out[43],_reg_out[42]}; +assign O[5] = {_reg_out[41],_reg_out[40],_reg_out[39],_reg_out[38],_reg_out[37],_reg_out[36],_reg_out[35]}; +assign O[4] = {_reg_out[34],_reg_out[33],_reg_out[32],_reg_out[31],_reg_out[30],_reg_out[29],_reg_out[28]}; +assign O[3] = {_reg_out[27],_reg_out[26],_reg_out[25],_reg_out[24],_reg_out[23],_reg_out[22],_reg_out[21]}; +assign O[2] = {_reg_out[20],_reg_out[19],_reg_out[18],_reg_out[17],_reg_out[16],_reg_out[15],_reg_out[14]}; +assign O[1] = {_reg_out[13],_reg_out[12],_reg_out[11],_reg_out[10],_reg_out[9],_reg_out[8],_reg_out[7]}; +assign O[0] = {_reg_out[6],_reg_out[5],_reg_out[4],_reg_out[3],_reg_out[2],_reg_out[1],_reg_out[0]}; endmodule module Mux8xBits7 ( @@ -71,28 +71,28 @@ module Mux8xBits7 ( input [2:0] S, output [6:0] O ); -reg [6:0] coreir_commonlib_mux8x7_inst0_out; +reg [6:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux8x7_inst0_out = I0; + mux_out = I0; end else if (S == 1) begin - coreir_commonlib_mux8x7_inst0_out = I1; + mux_out = I1; end else if (S == 2) begin - coreir_commonlib_mux8x7_inst0_out = I2; + mux_out = I2; end else if (S == 3) begin - coreir_commonlib_mux8x7_inst0_out = I3; + mux_out = I3; end else if (S == 4) begin - coreir_commonlib_mux8x7_inst0_out = I4; + mux_out = I4; end else if (S == 5) begin - coreir_commonlib_mux8x7_inst0_out = I5; + mux_out = I5; end else if (S == 6) begin - coreir_commonlib_mux8x7_inst0_out = I6; + mux_out = I6; end else begin - coreir_commonlib_mux8x7_inst0_out = I7; + mux_out = I7; end end -assign O = coreir_commonlib_mux8x7_inst0_out; +assign O = mux_out; endmodule module Test2 ( diff --git a/tests/test_syntax/gold/TestSequential2Hierarchy.v b/tests/test_syntax/gold/TestSequential2Hierarchy.v index 5229d6488..45dd59053 100644 --- a/tests/test_syntax/gold/TestSequential2Hierarchy.v +++ b/tests/test_syntax/gold/TestSequential2Hierarchy.v @@ -21,17 +21,17 @@ module Register ( output [3:0] O, input CLK ); -wire [3:0] reg_P4_inst0_out; +wire [3:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P4_inst0_out) + .out(_reg_out) ); -assign O = reg_P4_inst0_out; +assign O = _reg_out; endmodule module Foo ( diff --git a/tests/test_syntax/gold/TestSequential2IteArray.v b/tests/test_syntax/gold/TestSequential2IteArray.v index 512da3cbd..3d054e66f 100644 --- a/tests/test_syntax/gold/TestSequential2IteArray.v +++ b/tests/test_syntax/gold/TestSequential2IteArray.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xBit ( @@ -40,16 +40,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Mux2xArray1__SequentialRegisterWrapperBit ( @@ -58,16 +58,16 @@ module Mux2xArray1__SequentialRegisterWrapperBit ( input S, output [0:0] O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out; +assign O = mux_out; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteArray2.v b/tests/test_syntax/gold/TestSequential2IteArray2.v index 45af3c53b..ad9e58b5b 100644 --- a/tests/test_syntax/gold/TestSequential2IteArray2.v +++ b/tests/test_syntax/gold/TestSequential2IteArray2.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xBit ( @@ -40,16 +40,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Mux2xArray2_Bit ( @@ -58,16 +58,16 @@ module Mux2xArray2_Bit ( input S, output [1:0] O ); -reg [1:0] coreir_commonlib_mux2x2_inst0_out; +reg [1:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x2_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x2_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x2_inst0_out; +assign O = mux_out; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteBits.v b/tests/test_syntax/gold/TestSequential2IteBits.v index f2b2cd295..df5196363 100644 --- a/tests/test_syntax/gold/TestSequential2IteBits.v +++ b/tests/test_syntax/gold/TestSequential2IteBits.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(8'h00), .width(8) -) reg_P8_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) @@ -38,16 +38,16 @@ module Mux2x_SequentialRegisterWrapperBits8 ( input S, output [7:0] O ); -reg [7:0] coreir_commonlib_mux2x8_inst0_out; +reg [7:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x8_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x8_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x8_inst0_out; +assign O = mux_out; endmodule module Mux2xTuplea__SequentialRegisterWrapperBits8 ( @@ -56,16 +56,16 @@ module Mux2xTuplea__SequentialRegisterWrapperBits8 ( output [7:0] O_a, input S ); -reg [7:0] coreir_commonlib_mux2x8_inst0_out; +reg [7:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x8_inst0_out = I0_a; + mux_out = I0_a; end else begin - coreir_commonlib_mux2x8_inst0_out = I1_a; + mux_out = I1_a; end end -assign O_a = coreir_commonlib_mux2x8_inst0_out; +assign O_a = mux_out; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteBits2.v b/tests/test_syntax/gold/TestSequential2IteBits2.v index e340e14a9..507178eb0 100644 --- a/tests/test_syntax/gold/TestSequential2IteBits2.v +++ b/tests/test_syntax/gold/TestSequential2IteBits2.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(8'h00), .width(8) -) reg_P8_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) @@ -38,16 +38,16 @@ module Mux2x_SequentialRegisterWrapperBits8 ( input S, output [7:0] O ); -reg [7:0] coreir_commonlib_mux2x8_inst0_out; +reg [7:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x8_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x8_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x8_inst0_out; +assign O = mux_out; endmodule module Mux2xTuplea__SequentialRegisterWrapperBits8 ( @@ -56,16 +56,16 @@ module Mux2xTuplea__SequentialRegisterWrapperBits8 ( output [7:0] O_a, input S ); -reg [7:0] coreir_commonlib_mux2x8_inst0_out; +reg [7:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x8_inst0_out = I0_a; + mux_out = I0_a; end else begin - coreir_commonlib_mux2x8_inst0_out = I1_a; + mux_out = I1_a; end end -assign O_a = coreir_commonlib_mux2x8_inst0_out; +assign O_a = mux_out; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteBits3.v b/tests/test_syntax/gold/TestSequential2IteBits3.v index 5419e4a12..0b4233dcf 100644 --- a/tests/test_syntax/gold/TestSequential2IteBits3.v +++ b/tests/test_syntax/gold/TestSequential2IteBits3.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2x_SequentialRegisterWrapperBit ( @@ -40,16 +40,16 @@ module Mux2x_SequentialRegisterWrapperBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Mux2xTuplea_Bits8 ( @@ -58,16 +58,16 @@ module Mux2xTuplea_Bits8 ( output [7:0] O_a, input S ); -reg [7:0] coreir_commonlib_mux2x8_inst0_out; +reg [7:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x8_inst0_out = I0_a; + mux_out = I0_a; end else begin - coreir_commonlib_mux2x8_inst0_out = I1_a; + mux_out = I1_a; end end -assign O_a = coreir_commonlib_mux2x8_inst0_out; +assign O_a = mux_out; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteComplex.v b/tests/test_syntax/gold/TestSequential2IteComplex.v index e7a6a5586..8ebb3e02f 100644 --- a/tests/test_syntax/gold/TestSequential2IteComplex.v +++ b/tests/test_syntax/gold/TestSequential2IteComplex.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(2'h0), .width(2) -) reg_P2_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) @@ -37,17 +37,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2x_SequentialRegisterWrapperBits2 ( @@ -56,16 +56,16 @@ module Mux2x_SequentialRegisterWrapperBits2 ( input S, output [1:0] O ); -reg [1:0] coreir_commonlib_mux2x2_inst0_out; +reg [1:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x2_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x2_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x2_inst0_out; +assign O = mux_out; endmodule module Mux2x_SequentialRegisterWrapperBit ( @@ -74,16 +74,16 @@ module Mux2x_SequentialRegisterWrapperBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Mux2xTuplea_TupleArray2__SequentialRegisterWrapperBit_b_Array2_Bit ( @@ -95,17 +95,17 @@ module Mux2xTuplea_TupleArray2__SequentialRegisterWrapperBit_b_Array2_Bit ( output [1:0] O_b, input S ); -reg [3:0] coreir_commonlib_mux2x4_inst0_out; +reg [3:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x4_inst0_out = {I0_b,I0_a__0[1],I0_a__0[0]}; + mux_out = {I0_b,I0_a__0[1],I0_a__0[0]}; end else begin - coreir_commonlib_mux2x4_inst0_out = {I1_b,I1_a__0[1],I1_a__0[0]}; + mux_out = {I1_b,I1_a__0[1],I1_a__0[0]}; end end -assign O_a__0 = {coreir_commonlib_mux2x4_inst0_out[1],coreir_commonlib_mux2x4_inst0_out[0]}; -assign O_b = {coreir_commonlib_mux2x4_inst0_out[3],coreir_commonlib_mux2x4_inst0_out[2]}; +assign O_a__0 = {mux_out[1],mux_out[0]}; +assign O_b = {mux_out[3],mux_out[2]}; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteComplexRegister.v b/tests/test_syntax/gold/TestSequential2IteComplexRegister.v index 8ff815c96..bec5a28d3 100644 --- a/tests/test_syntax/gold/TestSequential2IteComplexRegister.v +++ b/tests/test_syntax/gold/TestSequential2IteComplexRegister.v @@ -23,20 +23,20 @@ module Register ( output [1:0] O_a [0:0], output [1:0] O_b__0_c ); -wire [3:0] reg_P4_inst0_out; -wire [3:0] reg_P4_inst0_in; -assign reg_P4_inst0_in = {I_b__0_c,I_a[0]}; +wire [3:0] _reg_out; +wire [3:0] _reg_in; +assign _reg_in = {I_b__0_c,I_a[0]}; coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P4_inst0_in), - .out(reg_P4_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O_a[0] = {reg_P4_inst0_out[1],reg_P4_inst0_out[0]}; -assign O_b__0_c = {reg_P4_inst0_out[3],reg_P4_inst0_out[2]}; +assign O_a[0] = {_reg_out[1],_reg_out[0]}; +assign O_b__0_c = {_reg_out[3],_reg_out[2]}; endmodule module Mux2x_SequentialRegisterWrapperTuplea_Array1_Bits2_b_TupleTuplec_Array2_Bit ( @@ -48,17 +48,17 @@ module Mux2x_SequentialRegisterWrapperTuplea_Array1_Bits2_b_TupleTuplec_Array2_B output [1:0] O_b__0_c, input S ); -reg [3:0] coreir_commonlib_mux2x4_inst0_out; +reg [3:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x4_inst0_out = {I0_b__0_c,I0_a[0]}; + mux_out = {I0_b__0_c,I0_a[0]}; end else begin - coreir_commonlib_mux2x4_inst0_out = {I1_b__0_c,I1_a[0]}; + mux_out = {I1_b__0_c,I1_a[0]}; end end -assign O_a[0] = {coreir_commonlib_mux2x4_inst0_out[1],coreir_commonlib_mux2x4_inst0_out[0]}; -assign O_b__0_c = {coreir_commonlib_mux2x4_inst0_out[3],coreir_commonlib_mux2x4_inst0_out[2]}; +assign O_a[0] = {mux_out[1],mux_out[0]}; +assign O_b__0_c = {mux_out[3],mux_out[2]}; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteComplexRegister2.v b/tests/test_syntax/gold/TestSequential2IteComplexRegister2.v index 0afbbd946..2ad6249aa 100644 --- a/tests/test_syntax/gold/TestSequential2IteComplexRegister2.v +++ b/tests/test_syntax/gold/TestSequential2IteComplexRegister2.v @@ -23,20 +23,20 @@ module Register ( output [1:0] O_a [0:0], output [1:0] O_b__0_c ); -wire [3:0] reg_P4_inst0_out; -wire [3:0] reg_P4_inst0_in; -assign reg_P4_inst0_in = {I_b__0_c,I_a[0]}; +wire [3:0] _reg_out; +wire [3:0] _reg_in; +assign _reg_in = {I_b__0_c,I_a[0]}; coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P4_inst0_in), - .out(reg_P4_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O_a[0] = {reg_P4_inst0_out[1],reg_P4_inst0_out[0]}; -assign O_b__0_c = {reg_P4_inst0_out[3],reg_P4_inst0_out[2]}; +assign O_a[0] = {_reg_out[1],_reg_out[0]}; +assign O_b__0_c = {_reg_out[3],_reg_out[2]}; endmodule module Mux2x_SequentialRegisterWrapperTuplea_Array1_Bits2_b_TupleTuplec_Array2_Bit ( @@ -48,17 +48,17 @@ module Mux2x_SequentialRegisterWrapperTuplea_Array1_Bits2_b_TupleTuplec_Array2_B output [1:0] O_b__0_c, input S ); -reg [3:0] coreir_commonlib_mux2x4_inst0_out; +reg [3:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x4_inst0_out = {I0_b__0_c,I0_a[0]}; + mux_out = {I0_b__0_c,I0_a[0]}; end else begin - coreir_commonlib_mux2x4_inst0_out = {I1_b__0_c,I1_a[0]}; + mux_out = {I1_b__0_c,I1_a[0]}; end end -assign O_a[0] = {coreir_commonlib_mux2x4_inst0_out[1],coreir_commonlib_mux2x4_inst0_out[0]}; -assign O_b__0_c = {coreir_commonlib_mux2x4_inst0_out[3],coreir_commonlib_mux2x4_inst0_out[2]}; +assign O_a[0] = {mux_out[1],mux_out[0]}; +assign O_b__0_c = {mux_out[3],mux_out[2]}; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteNested.v b/tests/test_syntax/gold/TestSequential2IteNested.v index eab352a38..75eab7e7e 100644 --- a/tests/test_syntax/gold/TestSequential2IteNested.v +++ b/tests/test_syntax/gold/TestSequential2IteNested.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xTuplea_Tupleb__SequentialRegisterWrapperBit_c_Tuple_SequentialRegisterWrapperBit ( @@ -43,17 +43,17 @@ module Mux2xTuplea_Tupleb__SequentialRegisterWrapperBit_c_Tuple_SequentialRegist output O_c__0, input S ); -reg [1:0] coreir_commonlib_mux2x2_inst0_out; +reg [1:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x2_inst0_out = {I0_c__0,I0_a_b}; + mux_out = {I0_c__0,I0_a_b}; end else begin - coreir_commonlib_mux2x2_inst0_out = {I1_c__0,I1_a_b}; + mux_out = {I1_c__0,I1_a_b}; end end -assign O_a_b = coreir_commonlib_mux2x2_inst0_out[0]; -assign O_c__0 = coreir_commonlib_mux2x2_inst0_out[1]; +assign O_a_b = mux_out[0]; +assign O_c__0 = mux_out[1]; endmodule module Mux2xBit ( @@ -62,16 +62,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteProduct.v b/tests/test_syntax/gold/TestSequential2IteProduct.v index 1a8a28f78..136ffa89b 100644 --- a/tests/test_syntax/gold/TestSequential2IteProduct.v +++ b/tests/test_syntax/gold/TestSequential2IteProduct.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xTuplea__SequentialRegisterWrapperBit ( @@ -40,16 +40,16 @@ module Mux2xTuplea__SequentialRegisterWrapperBit ( output O_a, input S ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0_a; + mux_out = I0_a; end else begin - coreir_commonlib_mux2x1_inst0_out = I1_a; + mux_out = I1_a; end end -assign O_a = coreir_commonlib_mux2x1_inst0_out[0]; +assign O_a = mux_out[0]; endmodule module Mux2xBit ( @@ -58,16 +58,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteProduct2.v b/tests/test_syntax/gold/TestSequential2IteProduct2.v index 92feda102..ee3f6efa3 100644 --- a/tests/test_syntax/gold/TestSequential2IteProduct2.v +++ b/tests/test_syntax/gold/TestSequential2IteProduct2.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xTuplea__SequentialRegisterWrapperBit ( @@ -40,16 +40,16 @@ module Mux2xTuplea__SequentialRegisterWrapperBit ( output O_a, input S ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0_a; + mux_out = I0_a; end else begin - coreir_commonlib_mux2x1_inst0_out = I1_a; + mux_out = I1_a; end end -assign O_a = coreir_commonlib_mux2x1_inst0_out[0]; +assign O_a = mux_out[0]; endmodule module Mux2xBit ( @@ -58,16 +58,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteTuple.v b/tests/test_syntax/gold/TestSequential2IteTuple.v index f1ed6ab5c..442671d0e 100644 --- a/tests/test_syntax/gold/TestSequential2IteTuple.v +++ b/tests/test_syntax/gold/TestSequential2IteTuple.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xTuple_SequentialRegisterWrapperBit ( @@ -40,16 +40,16 @@ module Mux2xTuple_SequentialRegisterWrapperBit ( output O__0, input S ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0__0; + mux_out = I0__0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1__0; + mux_out = I1__0; end end -assign O__0 = coreir_commonlib_mux2x1_inst0_out[0]; +assign O__0 = mux_out[0]; endmodule module Mux2xBit ( @@ -58,16 +58,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2IteTuple2.v b/tests/test_syntax/gold/TestSequential2IteTuple2.v index 5a6ad3733..63ac37d04 100644 --- a/tests/test_syntax/gold/TestSequential2IteTuple2.v +++ b/tests/test_syntax/gold/TestSequential2IteTuple2.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xTuple_SequentialRegisterWrapperBit ( @@ -40,16 +40,16 @@ module Mux2xTuple_SequentialRegisterWrapperBit ( output O__0, input S ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0__0; + mux_out = I0__0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1__0; + mux_out = I1__0; end end -assign O__0 = coreir_commonlib_mux2x1_inst0_out[0]; +assign O__0 = mux_out[0]; endmodule module Mux2xBit ( @@ -58,16 +58,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v b/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v index 442d81df0..e2dff8a69 100644 --- a/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v +++ b/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v @@ -21,17 +21,17 @@ module Register ( output [3:0] O, input CLK ); -wire [3:0] reg_P4_inst0_out; +wire [3:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P4_inst0_out) + .out(_reg_out) ); -assign O = reg_P4_inst0_out; +assign O = _reg_out; endmodule module LoopUnroll ( diff --git a/tests/test_syntax/gold/TestSequential2Prev.v b/tests/test_syntax/gold/TestSequential2Prev.v index e3c7b244d..53ab444c8 100644 --- a/tests/test_syntax/gold/TestSequential2Prev.v +++ b/tests/test_syntax/gold/TestSequential2Prev.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(3'h0), .width(3) -) reg_P3_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) diff --git a/tests/test_syntax/gold/TestSequential2Product.v b/tests/test_syntax/gold/TestSequential2Product.v index 65835121c..2d1e04fa9 100644 --- a/tests/test_syntax/gold/TestSequential2Product.v +++ b/tests/test_syntax/gold/TestSequential2Product.v @@ -4,16 +4,16 @@ module Mux2xTuplea_Bit ( output O_a, input S ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0_a; + mux_out = I0_a; end else begin - coreir_commonlib_mux2x1_inst0_out = I1_a; + mux_out = I1_a; end end -assign O_a = coreir_commonlib_mux2x1_inst0_out[0]; +assign O_a = mux_out[0]; endmodule module Test ( diff --git a/tests/test_syntax/gold/TestSequential2Reset.v b/tests/test_syntax/gold/TestSequential2Reset.v index 9c20576a5..fec437107 100644 --- a/tests/test_syntax/gold/TestSequential2Reset.v +++ b/tests/test_syntax/gold/TestSequential2Reset.v @@ -27,16 +27,16 @@ module Mux2xUInt3 ( input S, output [2:0] O ); -reg [2:0] coreir_commonlib_mux2x3_inst0_out; +reg [2:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x3_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x3_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x3_inst0_out; +assign O = mux_out; endmodule module Register ( @@ -47,23 +47,23 @@ module Register ( input ASYNCRESET ); wire [2:0] enable_mux_O; -Mux2xUInt3 enable_mux ( - .I0(O), - .I1(I), - .S(CE), - .O(enable_mux_O) -); coreir_reg_arst #( .arst_posedge(1'b1), .clk_posedge(1'b1), .init(3'h0), .width(3) -) reg_PR3_inst0 ( +) _reg ( .clk(CLK), .arst(ASYNCRESET), .in(enable_mux_O), .out(O) ); +Mux2xUInt3 enable_mux ( + .I0(O), + .I1(I), + .S(CE), + .O(enable_mux_O) +); endmodule module Test2 ( diff --git a/tests/test_syntax/gold/TestSequential2ReturnTuple.v b/tests/test_syntax/gold/TestSequential2ReturnTuple.v index 68d15b486..fd3bca27f 100644 --- a/tests/test_syntax/gold/TestSequential2ReturnTuple.v +++ b/tests/test_syntax/gold/TestSequential2ReturnTuple.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(4'h0), .width(4) -) reg_P4_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) @@ -38,16 +38,16 @@ module Mux2x_SequentialRegisterWrapperBits4 ( input S, output [3:0] O ); -reg [3:0] coreir_commonlib_mux2x4_inst0_out; +reg [3:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x4_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x4_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x4_inst0_out; +assign O = mux_out; endmodule module Mux2xBits4 ( @@ -56,16 +56,16 @@ module Mux2xBits4 ( input S, output [3:0] O ); -reg [3:0] coreir_commonlib_mux2x4_inst0_out; +reg [3:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x4_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x4_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x4_inst0_out; +assign O = mux_out; endmodule module Basic ( diff --git a/tests/test_syntax/gold/TestSequential2Slice.v b/tests/test_syntax/gold/TestSequential2Slice.v index cf5b1dae5..a9d989752 100644 --- a/tests/test_syntax/gold/TestSequential2Slice.v +++ b/tests/test_syntax/gold/TestSequential2Slice.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(64'h0000000000000000), .width(64) -) reg_P64_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) @@ -92,124 +92,124 @@ module Mux56xBits8 ( input [5:0] S, output [7:0] O ); -reg [7:0] coreir_commonlib_mux56x8_inst0_out; +reg [7:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux56x8_inst0_out = I0; + mux_out = I0; end else if (S == 1) begin - coreir_commonlib_mux56x8_inst0_out = I1; + mux_out = I1; end else if (S == 2) begin - coreir_commonlib_mux56x8_inst0_out = I2; + mux_out = I2; end else if (S == 3) begin - coreir_commonlib_mux56x8_inst0_out = I3; + mux_out = I3; end else if (S == 4) begin - coreir_commonlib_mux56x8_inst0_out = I4; + mux_out = I4; end else if (S == 5) begin - coreir_commonlib_mux56x8_inst0_out = I5; + mux_out = I5; end else if (S == 6) begin - coreir_commonlib_mux56x8_inst0_out = I6; + mux_out = I6; end else if (S == 7) begin - coreir_commonlib_mux56x8_inst0_out = I7; + mux_out = I7; end else if (S == 8) begin - coreir_commonlib_mux56x8_inst0_out = I8; + mux_out = I8; end else if (S == 9) begin - coreir_commonlib_mux56x8_inst0_out = I9; + mux_out = I9; end else if (S == 10) begin - coreir_commonlib_mux56x8_inst0_out = I10; + mux_out = I10; end else if (S == 11) begin - coreir_commonlib_mux56x8_inst0_out = I11; + mux_out = I11; end else if (S == 12) begin - coreir_commonlib_mux56x8_inst0_out = I12; + mux_out = I12; end else if (S == 13) begin - coreir_commonlib_mux56x8_inst0_out = I13; + mux_out = I13; end else if (S == 14) begin - coreir_commonlib_mux56x8_inst0_out = I14; + mux_out = I14; end else if (S == 15) begin - coreir_commonlib_mux56x8_inst0_out = I15; + mux_out = I15; end else if (S == 16) begin - coreir_commonlib_mux56x8_inst0_out = I16; + mux_out = I16; end else if (S == 17) begin - coreir_commonlib_mux56x8_inst0_out = I17; + mux_out = I17; end else if (S == 18) begin - coreir_commonlib_mux56x8_inst0_out = I18; + mux_out = I18; end else if (S == 19) begin - coreir_commonlib_mux56x8_inst0_out = I19; + mux_out = I19; end else if (S == 20) begin - coreir_commonlib_mux56x8_inst0_out = I20; + mux_out = I20; end else if (S == 21) begin - coreir_commonlib_mux56x8_inst0_out = I21; + mux_out = I21; end else if (S == 22) begin - coreir_commonlib_mux56x8_inst0_out = I22; + mux_out = I22; end else if (S == 23) begin - coreir_commonlib_mux56x8_inst0_out = I23; + mux_out = I23; end else if (S == 24) begin - coreir_commonlib_mux56x8_inst0_out = I24; + mux_out = I24; end else if (S == 25) begin - coreir_commonlib_mux56x8_inst0_out = I25; + mux_out = I25; end else if (S == 26) begin - coreir_commonlib_mux56x8_inst0_out = I26; + mux_out = I26; end else if (S == 27) begin - coreir_commonlib_mux56x8_inst0_out = I27; + mux_out = I27; end else if (S == 28) begin - coreir_commonlib_mux56x8_inst0_out = I28; + mux_out = I28; end else if (S == 29) begin - coreir_commonlib_mux56x8_inst0_out = I29; + mux_out = I29; end else if (S == 30) begin - coreir_commonlib_mux56x8_inst0_out = I30; + mux_out = I30; end else if (S == 31) begin - coreir_commonlib_mux56x8_inst0_out = I31; + mux_out = I31; end else if (S == 32) begin - coreir_commonlib_mux56x8_inst0_out = I32; + mux_out = I32; end else if (S == 33) begin - coreir_commonlib_mux56x8_inst0_out = I33; + mux_out = I33; end else if (S == 34) begin - coreir_commonlib_mux56x8_inst0_out = I34; + mux_out = I34; end else if (S == 35) begin - coreir_commonlib_mux56x8_inst0_out = I35; + mux_out = I35; end else if (S == 36) begin - coreir_commonlib_mux56x8_inst0_out = I36; + mux_out = I36; end else if (S == 37) begin - coreir_commonlib_mux56x8_inst0_out = I37; + mux_out = I37; end else if (S == 38) begin - coreir_commonlib_mux56x8_inst0_out = I38; + mux_out = I38; end else if (S == 39) begin - coreir_commonlib_mux56x8_inst0_out = I39; + mux_out = I39; end else if (S == 40) begin - coreir_commonlib_mux56x8_inst0_out = I40; + mux_out = I40; end else if (S == 41) begin - coreir_commonlib_mux56x8_inst0_out = I41; + mux_out = I41; end else if (S == 42) begin - coreir_commonlib_mux56x8_inst0_out = I42; + mux_out = I42; end else if (S == 43) begin - coreir_commonlib_mux56x8_inst0_out = I43; + mux_out = I43; end else if (S == 44) begin - coreir_commonlib_mux56x8_inst0_out = I44; + mux_out = I44; end else if (S == 45) begin - coreir_commonlib_mux56x8_inst0_out = I45; + mux_out = I45; end else if (S == 46) begin - coreir_commonlib_mux56x8_inst0_out = I46; + mux_out = I46; end else if (S == 47) begin - coreir_commonlib_mux56x8_inst0_out = I47; + mux_out = I47; end else if (S == 48) begin - coreir_commonlib_mux56x8_inst0_out = I48; + mux_out = I48; end else if (S == 49) begin - coreir_commonlib_mux56x8_inst0_out = I49; + mux_out = I49; end else if (S == 50) begin - coreir_commonlib_mux56x8_inst0_out = I50; + mux_out = I50; end else if (S == 51) begin - coreir_commonlib_mux56x8_inst0_out = I51; + mux_out = I51; end else if (S == 52) begin - coreir_commonlib_mux56x8_inst0_out = I52; + mux_out = I52; end else if (S == 53) begin - coreir_commonlib_mux56x8_inst0_out = I53; + mux_out = I53; end else if (S == 54) begin - coreir_commonlib_mux56x8_inst0_out = I54; + mux_out = I54; end else begin - coreir_commonlib_mux56x8_inst0_out = I55; + mux_out = I55; end end -assign O = coreir_commonlib_mux56x8_inst0_out; +assign O = mux_out; endmodule module Mux2xBit ( @@ -218,16 +218,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module TestSequential2Slice ( diff --git a/tests/test_syntax/gold/test_562.v b/tests/test_syntax/gold/test_562.v index 0dc85e698..b4f8040b8 100644 --- a/tests/test_syntax/gold/test_562.v +++ b/tests/test_syntax/gold/test_562.v @@ -32,16 +32,16 @@ module Mux2xBits1 ( input S, output [0:0] O ); -wire [0:0] coreir_commonlib_mux2x1_inst0_out; -wire [0:0] coreir_commonlib_mux2x1_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0; -commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( - .in_data(coreir_commonlib_mux2x1_inst0_in_data), +wire [0:0] mux_out; +wire [0:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width1 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x1_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x1_inst0_out; +assign O = mux_out; endmodule module A ( diff --git a/tests/test_syntax/gold/test_combinational2_basic_if.v b/tests/test_syntax/gold/test_combinational2_basic_if.v index 58bf6a178..7deed787c 100644 --- a/tests/test_syntax/gold/test_combinational2_basic_if.v +++ b/tests/test_syntax/gold/test_combinational2_basic_if.v @@ -4,16 +4,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module basic_if ( diff --git a/tests/test_syntax/gold/test_combinational2_pre_post_passes.v b/tests/test_syntax/gold/test_combinational2_pre_post_passes.v index 0f9011778..e133c545b 100644 --- a/tests/test_syntax/gold/test_combinational2_pre_post_passes.v +++ b/tests/test_syntax/gold/test_combinational2_pre_post_passes.v @@ -4,16 +4,16 @@ module Mux2xBits3 ( input S, output [2:0] O ); -reg [2:0] coreir_commonlib_mux2x3_inst0_out; +reg [2:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x3_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x3_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x3_inst0_out; +assign O = mux_out; endmodule module pre_unroll ( diff --git a/tests/test_syntax/gold/test_inline_comb_basic.v b/tests/test_syntax/gold/test_inline_comb_basic.v index ecbc3dadb..3289b0473 100644 --- a/tests/test_syntax/gold/test_inline_comb_basic.v +++ b/tests/test_syntax/gold/test_inline_comb_basic.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xBit ( @@ -40,16 +40,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Main ( diff --git a/tests/test_syntax/gold/test_inline_comb_bv_bit_bool.v b/tests/test_syntax/gold/test_inline_comb_bv_bit_bool.v index 152818691..08ef041da 100644 --- a/tests/test_syntax/gold/test_inline_comb_bv_bit_bool.v +++ b/tests/test_syntax/gold/test_inline_comb_bv_bit_bool.v @@ -4,16 +4,16 @@ module Mux2xBits2 ( input S, output [1:0] O ); -reg [1:0] coreir_commonlib_mux2x2_inst0_out; +reg [1:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x2_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x2_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x2_inst0_out; +assign O = mux_out; endmodule module Mux2xBit ( @@ -22,16 +22,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Main ( diff --git a/tests/test_syntax/gold/test_inline_comb_list.v b/tests/test_syntax/gold/test_inline_comb_list.v index 29fee170f..3200ce1f6 100644 --- a/tests/test_syntax/gold/test_inline_comb_list.v +++ b/tests/test_syntax/gold/test_inline_comb_list.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xBit ( @@ -40,16 +40,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Main ( diff --git a/tests/test_syntax/gold/test_inline_comb_wire.v b/tests/test_syntax/gold/test_inline_comb_wire.v index 3179ac828..8d86048fc 100644 --- a/tests/test_syntax/gold/test_inline_comb_wire.v +++ b/tests/test_syntax/gold/test_inline_comb_wire.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module Mux2xBit ( @@ -40,16 +40,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module Main ( diff --git a/tests/test_type/gold/TestBitite.v b/tests/test_type/gold/TestBitite.v index 193e84d7a..9b639c757 100644 --- a/tests/test_type/gold/TestBitite.v +++ b/tests/test_type/gold/TestBitite.v @@ -32,16 +32,16 @@ module Mux2xBit ( input S, output O ); -wire [0:0] coreir_commonlib_mux2x1_inst0_out; -wire [0:0] coreir_commonlib_mux2x1_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0; -commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( - .in_data(coreir_commonlib_mux2x1_inst0_in_data), +wire [0:0] mux_out; +wire [0:0] mux_in_data [1:0]; +assign mux_in_data[1] = I1; +assign mux_in_data[0] = I0; +commonlib_muxn__N2__width1 mux ( + .in_data(mux_in_data), .in_sel(S), - .out(coreir_commonlib_mux2x1_inst0_out) + .out(mux_out) ); -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module TestITE ( diff --git a/tests/test_type/gold/TestReadyValidNoDeqWhen.v b/tests/test_type/gold/TestReadyValidNoDeqWhen.v index 3f883dc95..211b0eaaf 100644 --- a/tests/test_type/gold/TestReadyValidNoDeqWhen.v +++ b/tests/test_type/gold/TestReadyValidNoDeqWhen.v @@ -4,16 +4,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module TestReadyValidNoDeqWhen ( diff --git a/tests/test_type/gold/TestReadyValidNoEnqWhen.v b/tests/test_type/gold/TestReadyValidNoEnqWhen.v index 40420b296..02605c257 100644 --- a/tests/test_type/gold/TestReadyValidNoEnqWhen.v +++ b/tests/test_type/gold/TestReadyValidNoEnqWhen.v @@ -4,16 +4,16 @@ module Mux2xBits5 ( input S, output [4:0] O ); -reg [4:0] coreir_commonlib_mux2x5_inst0_out; +reg [4:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x5_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x5_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x5_inst0_out; +assign O = mux_out; endmodule module Mux2xBit ( @@ -22,16 +22,16 @@ module Mux2xBit ( input S, output O ); -reg [0:0] coreir_commonlib_mux2x1_inst0_out; +reg [0:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x1_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x1_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x1_inst0_out[0]; +assign O = mux_out[0]; endmodule module TestReadyValidNoEnqWhen ( diff --git a/tests/test_type/gold/TestReadyValidWhen.v b/tests/test_type/gold/TestReadyValidWhen.v index 1621bca5b..756b29ee5 100644 --- a/tests/test_type/gold/TestReadyValidWhen.v +++ b/tests/test_type/gold/TestReadyValidWhen.v @@ -4,16 +4,16 @@ module Mux2xBits5 ( input S, output [4:0] O ); -reg [4:0] coreir_commonlib_mux2x5_inst0_out; +reg [4:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x5_inst0_out = I0; + mux_out = I0; end else begin - coreir_commonlib_mux2x5_inst0_out = I1; + mux_out = I1; end end -assign O = coreir_commonlib_mux2x5_inst0_out; +assign O = mux_out; endmodule module TestReadyValidWhen ( diff --git a/tests/test_type/gold/test_array2_nested_bits_temporary.v b/tests/test_type/gold/test_array2_nested_bits_temporary.v index 531da0382..db6ff8685 100644 --- a/tests/test_type/gold/test_array2_nested_bits_temporary.v +++ b/tests/test_type/gold/test_array2_nested_bits_temporary.v @@ -25,7 +25,7 @@ coreir_reg #( .clk_posedge(1'b1), .init(8'h00), .width(8) -) reg_P8_inst0 ( +) _reg ( .clk(CLK), .in(I), .out(O) diff --git a/tests/test_type/gold/test_foo_magma_protocol.v b/tests/test_type/gold/test_foo_magma_protocol.v index cb3c73ec2..74f2df8d9 100644 --- a/tests/test_type/gold/test_foo_magma_protocol.v +++ b/tests/test_type/gold/test_foo_magma_protocol.v @@ -58,17 +58,17 @@ module Register ( output [0:0] O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out; +assign O = _reg_out; endmodule module Bar ( diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem.v b/tests/test_type/gold/test_ndarray_dynamic_getitem.v index 4112dc904..5aec961e0 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem.v @@ -21,30 +21,30 @@ module Register ( output [1:0] O [3:0][2:0], input CLK ); -wire [23:0] reg_P24_inst0_out; -wire [23:0] reg_P24_inst0_in; -assign reg_P24_inst0_in = {I[3][2],I[3][1],I[3][0],I[2][2],I[2][1],I[2][0],I[1][2],I[1][1],I[1][0],I[0][2],I[0][1],I[0][0]}; +wire [23:0] _reg_out; +wire [23:0] _reg_in; +assign _reg_in = {I[3][2],I[3][1],I[3][0],I[2][2],I[2][1],I[2][0],I[1][2],I[1][1],I[1][0],I[0][2],I[0][1],I[0][0]}; coreir_reg #( .clk_posedge(1'b1), .init(24'h000000), .width(24) -) reg_P24_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P24_inst0_in), - .out(reg_P24_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O[3][2] = {reg_P24_inst0_out[23],reg_P24_inst0_out[22]}; -assign O[3][1] = {reg_P24_inst0_out[21],reg_P24_inst0_out[20]}; -assign O[3][0] = {reg_P24_inst0_out[19],reg_P24_inst0_out[18]}; -assign O[2][2] = {reg_P24_inst0_out[17],reg_P24_inst0_out[16]}; -assign O[2][1] = {reg_P24_inst0_out[15],reg_P24_inst0_out[14]}; -assign O[2][0] = {reg_P24_inst0_out[13],reg_P24_inst0_out[12]}; -assign O[1][2] = {reg_P24_inst0_out[11],reg_P24_inst0_out[10]}; -assign O[1][1] = {reg_P24_inst0_out[9],reg_P24_inst0_out[8]}; -assign O[1][0] = {reg_P24_inst0_out[7],reg_P24_inst0_out[6]}; -assign O[0][2] = {reg_P24_inst0_out[5],reg_P24_inst0_out[4]}; -assign O[0][1] = {reg_P24_inst0_out[3],reg_P24_inst0_out[2]}; -assign O[0][0] = {reg_P24_inst0_out[1],reg_P24_inst0_out[0]}; +assign O[3][2] = {_reg_out[23],_reg_out[22]}; +assign O[3][1] = {_reg_out[21],_reg_out[20]}; +assign O[3][0] = {_reg_out[19],_reg_out[18]}; +assign O[2][2] = {_reg_out[17],_reg_out[16]}; +assign O[2][1] = {_reg_out[15],_reg_out[14]}; +assign O[2][0] = {_reg_out[13],_reg_out[12]}; +assign O[1][2] = {_reg_out[11],_reg_out[10]}; +assign O[1][1] = {_reg_out[9],_reg_out[8]}; +assign O[1][0] = {_reg_out[7],_reg_out[6]}; +assign O[0][2] = {_reg_out[5],_reg_out[4]}; +assign O[0][1] = {_reg_out[3],_reg_out[2]}; +assign O[0][0] = {_reg_out[1],_reg_out[0]}; endmodule module Mux4xArray3_Array2_Bit ( @@ -55,22 +55,22 @@ module Mux4xArray3_Array2_Bit ( input [1:0] S, output [1:0] O [2:0] ); -reg [5:0] coreir_commonlib_mux4x6_inst0_out; +reg [5:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux4x6_inst0_out = {I0[2],I0[1],I0[0]}; + mux_out = {I0[2],I0[1],I0[0]}; end else if (S == 1) begin - coreir_commonlib_mux4x6_inst0_out = {I1[2],I1[1],I1[0]}; + mux_out = {I1[2],I1[1],I1[0]}; end else if (S == 2) begin - coreir_commonlib_mux4x6_inst0_out = {I2[2],I2[1],I2[0]}; + mux_out = {I2[2],I2[1],I2[0]}; end else begin - coreir_commonlib_mux4x6_inst0_out = {I3[2],I3[1],I3[0]}; + mux_out = {I3[2],I3[1],I3[0]}; end end -assign O[2] = {coreir_commonlib_mux4x6_inst0_out[5],coreir_commonlib_mux4x6_inst0_out[4]}; -assign O[1] = {coreir_commonlib_mux4x6_inst0_out[3],coreir_commonlib_mux4x6_inst0_out[2]}; -assign O[0] = {coreir_commonlib_mux4x6_inst0_out[1],coreir_commonlib_mux4x6_inst0_out[0]}; +assign O[2] = {mux_out[5],mux_out[4]}; +assign O[1] = {mux_out[3],mux_out[2]}; +assign O[0] = {mux_out[1],mux_out[0]}; endmodule module Main ( diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v index 95bf263cf..bf77ee6f7 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v @@ -21,42 +21,42 @@ module Register ( output [1:0] O [1:0][3:0][2:0], input CLK ); -wire [47:0] reg_P48_inst0_out; -wire [47:0] reg_P48_inst0_in; -assign reg_P48_inst0_in = {I[1][3][2],I[1][3][1],I[1][3][0],I[1][2][2],I[1][2][1],I[1][2][0],I[1][1][2],I[1][1][1],I[1][1][0],I[1][0][2],I[1][0][1],I[1][0][0],I[0][3][2],I[0][3][1],I[0][3][0],I[0][2][2],I[0][2][1],I[0][2][0],I[0][1][2],I[0][1][1],I[0][1][0],I[0][0][2],I[0][0][1],I[0][0][0]}; +wire [47:0] _reg_out; +wire [47:0] _reg_in; +assign _reg_in = {I[1][3][2],I[1][3][1],I[1][3][0],I[1][2][2],I[1][2][1],I[1][2][0],I[1][1][2],I[1][1][1],I[1][1][0],I[1][0][2],I[1][0][1],I[1][0][0],I[0][3][2],I[0][3][1],I[0][3][0],I[0][2][2],I[0][2][1],I[0][2][0],I[0][1][2],I[0][1][1],I[0][1][0],I[0][0][2],I[0][0][1],I[0][0][0]}; coreir_reg #( .clk_posedge(1'b1), .init(48'h000000000000), .width(48) -) reg_P48_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P48_inst0_in), - .out(reg_P48_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O[1][3][2] = {reg_P48_inst0_out[47],reg_P48_inst0_out[46]}; -assign O[1][3][1] = {reg_P48_inst0_out[45],reg_P48_inst0_out[44]}; -assign O[1][3][0] = {reg_P48_inst0_out[43],reg_P48_inst0_out[42]}; -assign O[1][2][2] = {reg_P48_inst0_out[41],reg_P48_inst0_out[40]}; -assign O[1][2][1] = {reg_P48_inst0_out[39],reg_P48_inst0_out[38]}; -assign O[1][2][0] = {reg_P48_inst0_out[37],reg_P48_inst0_out[36]}; -assign O[1][1][2] = {reg_P48_inst0_out[35],reg_P48_inst0_out[34]}; -assign O[1][1][1] = {reg_P48_inst0_out[33],reg_P48_inst0_out[32]}; -assign O[1][1][0] = {reg_P48_inst0_out[31],reg_P48_inst0_out[30]}; -assign O[1][0][2] = {reg_P48_inst0_out[29],reg_P48_inst0_out[28]}; -assign O[1][0][1] = {reg_P48_inst0_out[27],reg_P48_inst0_out[26]}; -assign O[1][0][0] = {reg_P48_inst0_out[25],reg_P48_inst0_out[24]}; -assign O[0][3][2] = {reg_P48_inst0_out[23],reg_P48_inst0_out[22]}; -assign O[0][3][1] = {reg_P48_inst0_out[21],reg_P48_inst0_out[20]}; -assign O[0][3][0] = {reg_P48_inst0_out[19],reg_P48_inst0_out[18]}; -assign O[0][2][2] = {reg_P48_inst0_out[17],reg_P48_inst0_out[16]}; -assign O[0][2][1] = {reg_P48_inst0_out[15],reg_P48_inst0_out[14]}; -assign O[0][2][0] = {reg_P48_inst0_out[13],reg_P48_inst0_out[12]}; -assign O[0][1][2] = {reg_P48_inst0_out[11],reg_P48_inst0_out[10]}; -assign O[0][1][1] = {reg_P48_inst0_out[9],reg_P48_inst0_out[8]}; -assign O[0][1][0] = {reg_P48_inst0_out[7],reg_P48_inst0_out[6]}; -assign O[0][0][2] = {reg_P48_inst0_out[5],reg_P48_inst0_out[4]}; -assign O[0][0][1] = {reg_P48_inst0_out[3],reg_P48_inst0_out[2]}; -assign O[0][0][0] = {reg_P48_inst0_out[1],reg_P48_inst0_out[0]}; +assign O[1][3][2] = {_reg_out[47],_reg_out[46]}; +assign O[1][3][1] = {_reg_out[45],_reg_out[44]}; +assign O[1][3][0] = {_reg_out[43],_reg_out[42]}; +assign O[1][2][2] = {_reg_out[41],_reg_out[40]}; +assign O[1][2][1] = {_reg_out[39],_reg_out[38]}; +assign O[1][2][0] = {_reg_out[37],_reg_out[36]}; +assign O[1][1][2] = {_reg_out[35],_reg_out[34]}; +assign O[1][1][1] = {_reg_out[33],_reg_out[32]}; +assign O[1][1][0] = {_reg_out[31],_reg_out[30]}; +assign O[1][0][2] = {_reg_out[29],_reg_out[28]}; +assign O[1][0][1] = {_reg_out[27],_reg_out[26]}; +assign O[1][0][0] = {_reg_out[25],_reg_out[24]}; +assign O[0][3][2] = {_reg_out[23],_reg_out[22]}; +assign O[0][3][1] = {_reg_out[21],_reg_out[20]}; +assign O[0][3][0] = {_reg_out[19],_reg_out[18]}; +assign O[0][2][2] = {_reg_out[17],_reg_out[16]}; +assign O[0][2][1] = {_reg_out[15],_reg_out[14]}; +assign O[0][2][0] = {_reg_out[13],_reg_out[12]}; +assign O[0][1][2] = {_reg_out[11],_reg_out[10]}; +assign O[0][1][1] = {_reg_out[9],_reg_out[8]}; +assign O[0][1][0] = {_reg_out[7],_reg_out[6]}; +assign O[0][0][2] = {_reg_out[5],_reg_out[4]}; +assign O[0][0][1] = {_reg_out[3],_reg_out[2]}; +assign O[0][0][0] = {_reg_out[1],_reg_out[0]}; endmodule module Mux4xArray3_Array2_Bit ( @@ -67,22 +67,22 @@ module Mux4xArray3_Array2_Bit ( input [1:0] S, output [1:0] O [2:0] ); -reg [5:0] coreir_commonlib_mux4x6_inst0_out; +reg [5:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux4x6_inst0_out = {I0[2],I0[1],I0[0]}; + mux_out = {I0[2],I0[1],I0[0]}; end else if (S == 1) begin - coreir_commonlib_mux4x6_inst0_out = {I1[2],I1[1],I1[0]}; + mux_out = {I1[2],I1[1],I1[0]}; end else if (S == 2) begin - coreir_commonlib_mux4x6_inst0_out = {I2[2],I2[1],I2[0]}; + mux_out = {I2[2],I2[1],I2[0]}; end else begin - coreir_commonlib_mux4x6_inst0_out = {I3[2],I3[1],I3[0]}; + mux_out = {I3[2],I3[1],I3[0]}; end end -assign O[2] = {coreir_commonlib_mux4x6_inst0_out[5],coreir_commonlib_mux4x6_inst0_out[4]}; -assign O[1] = {coreir_commonlib_mux4x6_inst0_out[3],coreir_commonlib_mux4x6_inst0_out[2]}; -assign O[0] = {coreir_commonlib_mux4x6_inst0_out[1],coreir_commonlib_mux4x6_inst0_out[0]}; +assign O[2] = {mux_out[5],mux_out[4]}; +assign O[1] = {mux_out[3],mux_out[2]}; +assign O[0] = {mux_out[1],mux_out[0]}; endmodule module Main ( diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v index 7218d857b..b77b52390 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v @@ -21,42 +21,42 @@ module Register ( output [1:0] O [3:0][1:0][2:0], input CLK ); -wire [47:0] reg_P48_inst0_out; -wire [47:0] reg_P48_inst0_in; -assign reg_P48_inst0_in = {I[3][1][2],I[3][1][1],I[3][1][0],I[3][0][2],I[3][0][1],I[3][0][0],I[2][1][2],I[2][1][1],I[2][1][0],I[2][0][2],I[2][0][1],I[2][0][0],I[1][1][2],I[1][1][1],I[1][1][0],I[1][0][2],I[1][0][1],I[1][0][0],I[0][1][2],I[0][1][1],I[0][1][0],I[0][0][2],I[0][0][1],I[0][0][0]}; +wire [47:0] _reg_out; +wire [47:0] _reg_in; +assign _reg_in = {I[3][1][2],I[3][1][1],I[3][1][0],I[3][0][2],I[3][0][1],I[3][0][0],I[2][1][2],I[2][1][1],I[2][1][0],I[2][0][2],I[2][0][1],I[2][0][0],I[1][1][2],I[1][1][1],I[1][1][0],I[1][0][2],I[1][0][1],I[1][0][0],I[0][1][2],I[0][1][1],I[0][1][0],I[0][0][2],I[0][0][1],I[0][0][0]}; coreir_reg #( .clk_posedge(1'b1), .init(48'h000000000000), .width(48) -) reg_P48_inst0 ( +) _reg ( .clk(CLK), - .in(reg_P48_inst0_in), - .out(reg_P48_inst0_out) + .in(_reg_in), + .out(_reg_out) ); -assign O[3][1][2] = {reg_P48_inst0_out[47],reg_P48_inst0_out[46]}; -assign O[3][1][1] = {reg_P48_inst0_out[45],reg_P48_inst0_out[44]}; -assign O[3][1][0] = {reg_P48_inst0_out[43],reg_P48_inst0_out[42]}; -assign O[3][0][2] = {reg_P48_inst0_out[41],reg_P48_inst0_out[40]}; -assign O[3][0][1] = {reg_P48_inst0_out[39],reg_P48_inst0_out[38]}; -assign O[3][0][0] = {reg_P48_inst0_out[37],reg_P48_inst0_out[36]}; -assign O[2][1][2] = {reg_P48_inst0_out[35],reg_P48_inst0_out[34]}; -assign O[2][1][1] = {reg_P48_inst0_out[33],reg_P48_inst0_out[32]}; -assign O[2][1][0] = {reg_P48_inst0_out[31],reg_P48_inst0_out[30]}; -assign O[2][0][2] = {reg_P48_inst0_out[29],reg_P48_inst0_out[28]}; -assign O[2][0][1] = {reg_P48_inst0_out[27],reg_P48_inst0_out[26]}; -assign O[2][0][0] = {reg_P48_inst0_out[25],reg_P48_inst0_out[24]}; -assign O[1][1][2] = {reg_P48_inst0_out[23],reg_P48_inst0_out[22]}; -assign O[1][1][1] = {reg_P48_inst0_out[21],reg_P48_inst0_out[20]}; -assign O[1][1][0] = {reg_P48_inst0_out[19],reg_P48_inst0_out[18]}; -assign O[1][0][2] = {reg_P48_inst0_out[17],reg_P48_inst0_out[16]}; -assign O[1][0][1] = {reg_P48_inst0_out[15],reg_P48_inst0_out[14]}; -assign O[1][0][0] = {reg_P48_inst0_out[13],reg_P48_inst0_out[12]}; -assign O[0][1][2] = {reg_P48_inst0_out[11],reg_P48_inst0_out[10]}; -assign O[0][1][1] = {reg_P48_inst0_out[9],reg_P48_inst0_out[8]}; -assign O[0][1][0] = {reg_P48_inst0_out[7],reg_P48_inst0_out[6]}; -assign O[0][0][2] = {reg_P48_inst0_out[5],reg_P48_inst0_out[4]}; -assign O[0][0][1] = {reg_P48_inst0_out[3],reg_P48_inst0_out[2]}; -assign O[0][0][0] = {reg_P48_inst0_out[1],reg_P48_inst0_out[0]}; +assign O[3][1][2] = {_reg_out[47],_reg_out[46]}; +assign O[3][1][1] = {_reg_out[45],_reg_out[44]}; +assign O[3][1][0] = {_reg_out[43],_reg_out[42]}; +assign O[3][0][2] = {_reg_out[41],_reg_out[40]}; +assign O[3][0][1] = {_reg_out[39],_reg_out[38]}; +assign O[3][0][0] = {_reg_out[37],_reg_out[36]}; +assign O[2][1][2] = {_reg_out[35],_reg_out[34]}; +assign O[2][1][1] = {_reg_out[33],_reg_out[32]}; +assign O[2][1][0] = {_reg_out[31],_reg_out[30]}; +assign O[2][0][2] = {_reg_out[29],_reg_out[28]}; +assign O[2][0][1] = {_reg_out[27],_reg_out[26]}; +assign O[2][0][0] = {_reg_out[25],_reg_out[24]}; +assign O[1][1][2] = {_reg_out[23],_reg_out[22]}; +assign O[1][1][1] = {_reg_out[21],_reg_out[20]}; +assign O[1][1][0] = {_reg_out[19],_reg_out[18]}; +assign O[1][0][2] = {_reg_out[17],_reg_out[16]}; +assign O[1][0][1] = {_reg_out[15],_reg_out[14]}; +assign O[1][0][0] = {_reg_out[13],_reg_out[12]}; +assign O[0][1][2] = {_reg_out[11],_reg_out[10]}; +assign O[0][1][1] = {_reg_out[9],_reg_out[8]}; +assign O[0][1][0] = {_reg_out[7],_reg_out[6]}; +assign O[0][0][2] = {_reg_out[5],_reg_out[4]}; +assign O[0][0][1] = {_reg_out[3],_reg_out[2]}; +assign O[0][0][0] = {_reg_out[1],_reg_out[0]}; endmodule module Mux4xArray2_Array3_Array2_Bit ( @@ -67,25 +67,25 @@ module Mux4xArray2_Array3_Array2_Bit ( input [1:0] S, output [1:0] O [1:0][2:0] ); -reg [11:0] coreir_commonlib_mux4x12_inst0_out; +reg [11:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux4x12_inst0_out = {I0[1][2],I0[1][1],I0[1][0],I0[0][2],I0[0][1],I0[0][0]}; + mux_out = {I0[1][2],I0[1][1],I0[1][0],I0[0][2],I0[0][1],I0[0][0]}; end else if (S == 1) begin - coreir_commonlib_mux4x12_inst0_out = {I1[1][2],I1[1][1],I1[1][0],I1[0][2],I1[0][1],I1[0][0]}; + mux_out = {I1[1][2],I1[1][1],I1[1][0],I1[0][2],I1[0][1],I1[0][0]}; end else if (S == 2) begin - coreir_commonlib_mux4x12_inst0_out = {I2[1][2],I2[1][1],I2[1][0],I2[0][2],I2[0][1],I2[0][0]}; + mux_out = {I2[1][2],I2[1][1],I2[1][0],I2[0][2],I2[0][1],I2[0][0]}; end else begin - coreir_commonlib_mux4x12_inst0_out = {I3[1][2],I3[1][1],I3[1][0],I3[0][2],I3[0][1],I3[0][0]}; + mux_out = {I3[1][2],I3[1][1],I3[1][0],I3[0][2],I3[0][1],I3[0][0]}; end end -assign O[1][2] = {coreir_commonlib_mux4x12_inst0_out[11],coreir_commonlib_mux4x12_inst0_out[10]}; -assign O[1][1] = {coreir_commonlib_mux4x12_inst0_out[9],coreir_commonlib_mux4x12_inst0_out[8]}; -assign O[1][0] = {coreir_commonlib_mux4x12_inst0_out[7],coreir_commonlib_mux4x12_inst0_out[6]}; -assign O[0][2] = {coreir_commonlib_mux4x12_inst0_out[5],coreir_commonlib_mux4x12_inst0_out[4]}; -assign O[0][1] = {coreir_commonlib_mux4x12_inst0_out[3],coreir_commonlib_mux4x12_inst0_out[2]}; -assign O[0][0] = {coreir_commonlib_mux4x12_inst0_out[1],coreir_commonlib_mux4x12_inst0_out[0]}; +assign O[1][2] = {mux_out[11],mux_out[10]}; +assign O[1][1] = {mux_out[9],mux_out[8]}; +assign O[1][0] = {mux_out[7],mux_out[6]}; +assign O[0][2] = {mux_out[5],mux_out[4]}; +assign O[0][1] = {mux_out[3],mux_out[2]}; +assign O[0][0] = {mux_out[1],mux_out[0]}; endmodule module Main ( diff --git a/tests/test_type/gold/test_ndarray_get_slice.v b/tests/test_type/gold/test_ndarray_get_slice.v index f207f3359..b347cee77 100644 --- a/tests/test_type/gold/test_ndarray_get_slice.v +++ b/tests/test_type/gold/test_ndarray_get_slice.v @@ -6,25 +6,25 @@ module Mux4xArray2_Array3_Array2_Bit ( input [1:0] S, output [1:0] O [1:0][2:0] ); -reg [11:0] coreir_commonlib_mux4x12_inst0_out; +reg [11:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux4x12_inst0_out = {I0[1][2],I0[1][1],I0[1][0],I0[0][2],I0[0][1],I0[0][0]}; + mux_out = {I0[1][2],I0[1][1],I0[1][0],I0[0][2],I0[0][1],I0[0][0]}; end else if (S == 1) begin - coreir_commonlib_mux4x12_inst0_out = {I1[1][2],I1[1][1],I1[1][0],I1[0][2],I1[0][1],I1[0][0]}; + mux_out = {I1[1][2],I1[1][1],I1[1][0],I1[0][2],I1[0][1],I1[0][0]}; end else if (S == 2) begin - coreir_commonlib_mux4x12_inst0_out = {I2[1][2],I2[1][1],I2[1][0],I2[0][2],I2[0][1],I2[0][0]}; + mux_out = {I2[1][2],I2[1][1],I2[1][0],I2[0][2],I2[0][1],I2[0][0]}; end else begin - coreir_commonlib_mux4x12_inst0_out = {I3[1][2],I3[1][1],I3[1][0],I3[0][2],I3[0][1],I3[0][0]}; + mux_out = {I3[1][2],I3[1][1],I3[1][0],I3[0][2],I3[0][1],I3[0][0]}; end end -assign O[1][2] = {coreir_commonlib_mux4x12_inst0_out[11],coreir_commonlib_mux4x12_inst0_out[10]}; -assign O[1][1] = {coreir_commonlib_mux4x12_inst0_out[9],coreir_commonlib_mux4x12_inst0_out[8]}; -assign O[1][0] = {coreir_commonlib_mux4x12_inst0_out[7],coreir_commonlib_mux4x12_inst0_out[6]}; -assign O[0][2] = {coreir_commonlib_mux4x12_inst0_out[5],coreir_commonlib_mux4x12_inst0_out[4]}; -assign O[0][1] = {coreir_commonlib_mux4x12_inst0_out[3],coreir_commonlib_mux4x12_inst0_out[2]}; -assign O[0][0] = {coreir_commonlib_mux4x12_inst0_out[1],coreir_commonlib_mux4x12_inst0_out[0]}; +assign O[1][2] = {mux_out[11],mux_out[10]}; +assign O[1][1] = {mux_out[9],mux_out[8]}; +assign O[1][0] = {mux_out[7],mux_out[6]}; +assign O[0][2] = {mux_out[5],mux_out[4]}; +assign O[0][1] = {mux_out[3],mux_out[2]}; +assign O[0][0] = {mux_out[1],mux_out[0]}; endmodule module Main ( diff --git a/tests/test_type/gold/test_ndarray_set_slice.v b/tests/test_type/gold/test_ndarray_set_slice.v index 9c19bb640..9dce35ba0 100644 --- a/tests/test_type/gold/test_ndarray_set_slice.v +++ b/tests/test_type/gold/test_ndarray_set_slice.v @@ -4,18 +4,18 @@ module Mux2xArray3_Array2_Bit ( input S, output [1:0] O [2:0] ); -reg [5:0] coreir_commonlib_mux2x6_inst0_out; +reg [5:0] mux_out; always @(*) begin if (S == 0) begin - coreir_commonlib_mux2x6_inst0_out = {I0[2],I0[1],I0[0]}; + mux_out = {I0[2],I0[1],I0[0]}; end else begin - coreir_commonlib_mux2x6_inst0_out = {I1[2],I1[1],I1[0]}; + mux_out = {I1[2],I1[1],I1[0]}; end end -assign O[2] = {coreir_commonlib_mux2x6_inst0_out[5],coreir_commonlib_mux2x6_inst0_out[4]}; -assign O[1] = {coreir_commonlib_mux2x6_inst0_out[3],coreir_commonlib_mux2x6_inst0_out[2]}; -assign O[0] = {coreir_commonlib_mux2x6_inst0_out[1],coreir_commonlib_mux2x6_inst0_out[0]}; +assign O[2] = {mux_out[5],mux_out[4]}; +assign O[1] = {mux_out[3],mux_out[2]}; +assign O[0] = {mux_out[1],mux_out[0]}; endmodule module Main ( diff --git a/tests/test_verilog/gold/TestDisplay.v b/tests/test_verilog/gold/TestDisplay.v index 48b1b94c3..5a1e196ef 100644 --- a/tests/test_verilog/gold/TestDisplay.v +++ b/tests/test_verilog/gold/TestDisplay.v @@ -1,4 +1,4 @@ -// Generated by CIRCT circtorg-0.0.0-1018-g3a39b339f +// Generated by CIRCT unknown git version module TestDisplay( input I, CLK, diff --git a/tests/test_verilog/gold/TestFDisplay.v b/tests/test_verilog/gold/TestFDisplay.v index 758bdf4a5..f18510f63 100644 --- a/tests/test_verilog/gold/TestFDisplay.v +++ b/tests/test_verilog/gold/TestFDisplay.v @@ -1,4 +1,4 @@ -// Generated by CIRCT circtorg-0.0.0-1018-g3a39b339f +// Generated by CIRCT unknown git version module TestFDisplay( input I, CLK, @@ -12,13 +12,13 @@ module TestFDisplay( end // always_ff @(posedge) initial ff = 1'h0; - + integer \_file_test_fdisplay.log ; initial \_file_test_fdisplay.log = $fopen("test_fdisplay.log", "a"); always @(posedge CLK) begin if (CE) $fdisplay(\_file_test_fdisplay.log , "ff.O=%d, ff.I=%d", ff, I); end - + final $fclose(\_file_test_fdisplay.log ); assign O = ff; endmodule diff --git a/tests/test_verilog/gold/TestFLog.v b/tests/test_verilog/gold/TestFLog.v index 21e389f33..6e1de78f3 100644 --- a/tests/test_verilog/gold/TestFLog.v +++ b/tests/test_verilog/gold/TestFLog.v @@ -1,4 +1,4 @@ -// Generated by CIRCT circtorg-0.0.0-1018-g3a39b339f +// Generated by CIRCT unknown git version module TestFLog( input I, CLK, @@ -12,11 +12,11 @@ module TestFLog( end // always_ff @(posedge) initial ff = 1'h0; - + `ifndef MAGMA_LOG_LEVEL `define MAGMA_LOG_LEVEL 1 `endif - + integer \_file_test_flog.log ; initial \_file_test_flog.log = $fopen("test_flog.log", "a"); always @(posedge CLK) begin @@ -31,7 +31,7 @@ module TestFLog( always @(posedge CLK) begin if ((`MAGMA_LOG_LEVEL <= 3) && (CE)) $fdisplay(\_file_test_flog.log , "[ERROR] ff.O=%d, ff.I=%d", ff, I); end - + final $fclose(\_file_test_flog.log ); assign O = ff; endmodule diff --git a/tests/test_verilog/gold/TestLog.v b/tests/test_verilog/gold/TestLog.v index ed40d6ca1..039781ff6 100644 --- a/tests/test_verilog/gold/TestLog.v +++ b/tests/test_verilog/gold/TestLog.v @@ -1,4 +1,4 @@ -// Generated by CIRCT circtorg-0.0.0-1018-g3a39b339f +// Generated by CIRCT unknown git version module TestLog( input I, CLK, @@ -12,7 +12,7 @@ module TestLog( end // always_ff @(posedge) initial ff = 1'h0; - + `ifndef MAGMA_LOG_LEVEL `define MAGMA_LOG_LEVEL 1 `endif diff --git a/tests/test_verilog/gold/bind_test.v b/tests/test_verilog/gold/bind_test.v index 0bdda1a16..262cfaee8 100644 --- a/tests/test_verilog/gold/bind_test.v +++ b/tests/test_verilog/gold/bind_test.v @@ -77,6 +77,9 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; +bar_foo_SomeCircuit SomeCircuit_inst0 ( + .I(magma_Bits_4_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -140,9 +143,6 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); -bar_foo_SomeCircuit some_circ ( - .I(magma_Bits_4_xor_inst0_out) -); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; diff --git a/tests/test_verilog/gold/bind_uniq_test.v b/tests/test_verilog/gold/bind_uniq_test.v index 27b61373c..e43b6d3d8 100644 --- a/tests/test_verilog/gold/bind_uniq_test.v +++ b/tests/test_verilog/gold/bind_uniq_test.v @@ -115,6 +115,9 @@ wire [4:0] magma_Bits_5_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_5_inst0_O; wire temp3; +bar_foo_SomeCircuit_unq1 SomeCircuit_inst0 ( + .I(magma_Bits_5_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_5_inst0_O; assign _magma_bind_wire_1 = andr_5_inst0_O; assign _magma_bind_wire_2_0 = orr_5_inst0_O; @@ -185,9 +188,6 @@ orr_5 orr_5_inst0 ( .I(in1), .O(orr_5_inst0_O) ); -bar_foo_SomeCircuit_unq1 some_circ ( - .I(magma_Bits_5_xor_inst0_out) -); assign temp3 = andr_5_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -243,6 +243,9 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; +bar_foo_SomeCircuit SomeCircuit_inst0 ( + .I(magma_Bits_4_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -313,9 +316,6 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); -bar_foo_SomeCircuit some_circ ( - .I(magma_Bits_4_xor_inst0_out) -); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -343,16 +343,16 @@ endmodule module bar_foo_Main ( input CLK ); -wire RTL4_handshake_arr_0_valid; -wire RTL4_handshake_arr_1_valid; -wire RTL4_handshake_arr_2_valid; -wire RTL4_handshake_valid; -wire RTL4_out; -wire RTL5_handshake_arr_0_valid; -wire RTL5_handshake_arr_1_valid; -wire RTL5_handshake_arr_2_valid; -wire RTL5_handshake_valid; -wire RTL5_out; +wire RTL_inst0_handshake_arr_0_valid; +wire RTL_inst0_handshake_arr_1_valid; +wire RTL_inst0_handshake_arr_2_valid; +wire RTL_inst0_handshake_valid; +wire RTL_inst0_out; +wire RTL_inst1_handshake_arr_0_valid; +wire RTL_inst1_handshake_arr_1_valid; +wire RTL_inst1_handshake_arr_2_valid; +wire RTL_inst1_handshake_valid; +wire RTL_inst1_out; wire corebit_undriven_inst0_out; wire corebit_undriven_inst1_out; wire corebit_undriven_inst10_out; @@ -377,73 +377,73 @@ wire [3:0] undriven_inst0_out; wire [3:0] undriven_inst1_out; wire [4:0] undriven_inst2_out; wire [4:0] undriven_inst3_out; -wire [1:0] RTL4_ndarr [2:0]; -assign RTL4_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; -assign RTL4_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; -assign RTL4_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; -bar_foo_RTL RTL4 ( +wire [1:0] RTL_inst0_ndarr [2:0]; +assign RTL_inst0_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; +assign RTL_inst0_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; +assign RTL_inst0_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; +bar_foo_RTL RTL_inst0 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst1_out), - .handshake_arr_0_valid(RTL4_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL_inst0_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst2_out), - .handshake_arr_1_valid(RTL4_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL_inst0_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst3_out), - .handshake_arr_2_valid(RTL4_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL_inst0_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst0_out), - .handshake_valid(RTL4_handshake_valid), + .handshake_valid(RTL_inst0_handshake_valid), .in1(undriven_inst0_out), .in2(undriven_inst1_out), - .ndarr(RTL4_ndarr), - .out(RTL4_out) -); -wire [1:0] RTL5_ndarr [2:0]; -assign RTL5_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; -assign RTL5_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; -assign RTL5_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; -bar_foo_RTL_unq1 RTL5 ( + .ndarr(RTL_inst0_ndarr), + .out(RTL_inst0_out) +); +wire [1:0] RTL_inst1_ndarr [2:0]; +assign RTL_inst1_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; +assign RTL_inst1_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; +assign RTL_inst1_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; +bar_foo_RTL_unq1 RTL_inst1 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst11_out), - .handshake_arr_0_valid(RTL5_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL_inst1_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst12_out), - .handshake_arr_1_valid(RTL5_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL_inst1_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst13_out), - .handshake_arr_2_valid(RTL5_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL_inst1_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst10_out), - .handshake_valid(RTL5_handshake_valid), + .handshake_valid(RTL_inst1_handshake_valid), .in1(undriven_inst2_out), .in2(undriven_inst3_out), - .ndarr(RTL5_ndarr), - .out(RTL5_out) + .ndarr(RTL_inst1_ndarr), + .out(RTL_inst1_out) ); bar_corebit_term corebit_term_inst0 ( - .in(RTL4_out) + .in(RTL_inst0_out) ); bar_corebit_term corebit_term_inst1 ( - .in(RTL4_handshake_valid) + .in(RTL_inst0_handshake_valid) ); bar_corebit_term corebit_term_inst2 ( - .in(RTL4_handshake_arr_0_valid) + .in(RTL_inst0_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst3 ( - .in(RTL4_handshake_arr_1_valid) + .in(RTL_inst0_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst4 ( - .in(RTL4_handshake_arr_2_valid) + .in(RTL_inst0_handshake_arr_2_valid) ); bar_corebit_term corebit_term_inst5 ( - .in(RTL5_out) + .in(RTL_inst1_out) ); bar_corebit_term corebit_term_inst6 ( - .in(RTL5_handshake_valid) + .in(RTL_inst1_handshake_valid) ); bar_corebit_term corebit_term_inst7 ( - .in(RTL5_handshake_arr_0_valid) + .in(RTL_inst1_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst8 ( - .in(RTL5_handshake_arr_1_valid) + .in(RTL_inst1_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst9 ( - .in(RTL5_handshake_arr_2_valid) + .in(RTL_inst1_handshake_arr_2_valid) ); bar_corebit_undriven corebit_undriven_inst0 ( .out(corebit_undriven_inst0_out) diff --git a/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v b/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v index cf11cccc4..08fdf8762 100644 --- a/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v +++ b/tests/test_verilog/gold/test_inline_wire_insertion_bad_verilog.v @@ -1,4 +1,4 @@ -// Generated by CIRCT circtorg-0.0.0-1018-g3a39b339f +// Generated by CIRCT unknown git version module test_wire_insertion_bad_verilog( input [31:0] I, output O); From 894295627cb4df26c359a385ec7fb985878e45a6 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 7 Dec 2022 15:52:28 -0800 Subject: [PATCH 28/61] Update golds, add lstrip logic --- magma/debug_rewriter.py | 2 +- tests/gold/test_compile_guard_select_basic.v | 8 +- tests/gold/test_when_user_reg.mlir | 2 +- tests/gold/test_when_user_reg_enable.mlir | 2 +- ...ter_wrapper_elaborate_magma_registers.mlir | 6 +- ...ter_wrapper_elaborate_magma_registers.mlir | 2 +- tests/test_verilog/gold/bind_test.v | 6 +- tests/test_verilog/gold/bind_uniq_test.v | 98 +++++++++---------- 8 files changed, 63 insertions(+), 63 deletions(-) diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 5ef74dad2..0870631e6 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -41,7 +41,7 @@ def leave_FunctionDef( def debug(fn): indented_program_txt = inspect.getsource(fn) - program_txt = textwrap.dedent(indented_program_txt) + program_txt = textwrap.dedent(indented_program_txt).lstrip() tree = cst.parse_module(program_txt) wrapper = cst.metadata.MetadataWrapper(tree) tree = wrapper.visit(Transformer()) diff --git a/tests/gold/test_compile_guard_select_basic.v b/tests/gold/test_compile_guard_select_basic.v index 83e6f0238..5226ad1f6 100644 --- a/tests/gold/test_compile_guard_select_basic.v +++ b/tests/gold/test_compile_guard_select_basic.v @@ -21,17 +21,17 @@ module Register ( output O, input CLK ); -wire [0:0] reg_P1_inst0_out; +wire [0:0] _reg_out; coreir_reg #( .clk_posedge(1'b1), .init(1'h0), .width(1) -) reg_P1_inst0 ( +) _reg ( .clk(CLK), .in(I), - .out(reg_P1_inst0_out) + .out(_reg_out) ); -assign O = reg_P1_inst0_out[0]; +assign O = _reg_out[0]; endmodule module CompileGuardSelect_Bit_COND1_COND2_default ( diff --git a/tests/gold/test_when_user_reg.mlir b/tests/gold/test_when_user_reg.mlir index 80544c0c4..b55833270 100644 --- a/tests/gold/test_when_user_reg.mlir +++ b/tests/gold/test_when_user_reg.mlir @@ -9,7 +9,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i8 } } - %0 = hw.instance "Register_inst0" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) + %0 = hw.instance "x" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) hw.output %0 : i8 } } diff --git a/tests/gold/test_when_user_reg_enable.mlir b/tests/gold/test_when_user_reg_enable.mlir index 7e3537e53..3d08213cc 100644 --- a/tests/gold/test_when_user_reg_enable.mlir +++ b/tests/gold/test_when_user_reg_enable.mlir @@ -84,7 +84,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } } %49 = comb.concat %38, %37, %36, %35, %34, %33, %32, %31 : i1, i1, i1, i1, i1, i1, i1, i1 - %21 = hw.instance "Register_inst0" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) + %21 = hw.instance "x" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) hw.output %21 : i8 } } diff --git a/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir b/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir index 2833c8b00..3bae92146 100644 --- a/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir +++ b/tests/test_backend/test_mlir/golds/complex_register_wrapper_elaborate_magma_registers.mlir @@ -23,7 +23,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { %22 = comb.extract %14 from 7 : (i8) -> i1 %23 = hw.struct_extract %12["y"] : !hw.struct %24 = comb.concat %23, %22, %21, %20, %19, %18, %17, %16, %15 : i1, i1, i1, i1, i1, i1, i1, i1, i1 - %25 = sv.reg {name = "reg"} : !hw.inout + %25 = sv.reg {name = "_reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %25, %24 : i9 } (asyncreset : posedge %ASYNCRESET) { @@ -149,7 +149,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { %106 = comb.extract %90 from 14 : (i16) -> i1 %107 = comb.extract %90 from 15 : (i16) -> i1 %108 = comb.concat %107, %106, %105, %104, %103, %102, %101, %100, %99, %98, %97, %96, %95, %94, %93, %92, %89, %88, %87, %86, %85, %84, %83, %82, %81, %80, %79, %78, %77, %76, %75, %74, %71, %70, %69, %68, %67, %66, %65, %64, %63, %62, %61, %60, %59, %58, %57, %56, %53, %52, %51, %50, %49, %48, %47, %46, %45, %44, %43, %42, %41, %40, %39, %38, %35, %34, %33, %32, %31, %30, %29, %28, %27, %26, %25, %24, %23, %22, %21, %20, %17, %16, %15, %14, %13, %12, %11, %10, %9, %8, %7, %6, %5, %4, %3, %2 : i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1 - %110 = sv.reg {name = "reg_P96_inst0"} : !hw.inout + %110 = sv.reg {name = "_reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %110, %108 : i96 } @@ -266,7 +266,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @Register_unq2(%I: i8, %CE: i1, %CLK: i1) -> (O: i8) { %2 = hw.array_create %I, %0 : i8 %1 = hw.array_get %2[%CE] : !hw.array<2xi8>, i1 - %3 = sv.reg {name = "reg_P8_inst0"} : !hw.inout + %3 = sv.reg {name = "_reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %3, %1 : i8 } diff --git a/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir b/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir index c85d471f2..f8e918b3e 100644 --- a/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir +++ b/tests/test_backend/test_mlir/golds/simple_register_wrapper_elaborate_magma_registers.mlir @@ -1,6 +1,6 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @Register(%I: i8, %CLK: i1) -> (O: i8) { - %1 = sv.reg {name = "reg"} : !hw.inout + %1 = sv.reg {name = "_reg"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %1, %I : i8 } diff --git a/tests/test_verilog/gold/bind_test.v b/tests/test_verilog/gold/bind_test.v index 262cfaee8..0bdda1a16 100644 --- a/tests/test_verilog/gold/bind_test.v +++ b/tests/test_verilog/gold/bind_test.v @@ -77,9 +77,6 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; -bar_foo_SomeCircuit SomeCircuit_inst0 ( - .I(magma_Bits_4_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -143,6 +140,9 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); +bar_foo_SomeCircuit some_circ ( + .I(magma_Bits_4_xor_inst0_out) +); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; diff --git a/tests/test_verilog/gold/bind_uniq_test.v b/tests/test_verilog/gold/bind_uniq_test.v index e43b6d3d8..27b61373c 100644 --- a/tests/test_verilog/gold/bind_uniq_test.v +++ b/tests/test_verilog/gold/bind_uniq_test.v @@ -115,9 +115,6 @@ wire [4:0] magma_Bits_5_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_5_inst0_O; wire temp3; -bar_foo_SomeCircuit_unq1 SomeCircuit_inst0 ( - .I(magma_Bits_5_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_5_inst0_O; assign _magma_bind_wire_1 = andr_5_inst0_O; assign _magma_bind_wire_2_0 = orr_5_inst0_O; @@ -188,6 +185,9 @@ orr_5 orr_5_inst0 ( .I(in1), .O(orr_5_inst0_O) ); +bar_foo_SomeCircuit_unq1 some_circ ( + .I(magma_Bits_5_xor_inst0_out) +); assign temp3 = andr_5_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -243,9 +243,6 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; -bar_foo_SomeCircuit SomeCircuit_inst0 ( - .I(magma_Bits_4_xor_inst0_out) -); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -316,6 +313,9 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); +bar_foo_SomeCircuit some_circ ( + .I(magma_Bits_4_xor_inst0_out) +); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -343,16 +343,16 @@ endmodule module bar_foo_Main ( input CLK ); -wire RTL_inst0_handshake_arr_0_valid; -wire RTL_inst0_handshake_arr_1_valid; -wire RTL_inst0_handshake_arr_2_valid; -wire RTL_inst0_handshake_valid; -wire RTL_inst0_out; -wire RTL_inst1_handshake_arr_0_valid; -wire RTL_inst1_handshake_arr_1_valid; -wire RTL_inst1_handshake_arr_2_valid; -wire RTL_inst1_handshake_valid; -wire RTL_inst1_out; +wire RTL4_handshake_arr_0_valid; +wire RTL4_handshake_arr_1_valid; +wire RTL4_handshake_arr_2_valid; +wire RTL4_handshake_valid; +wire RTL4_out; +wire RTL5_handshake_arr_0_valid; +wire RTL5_handshake_arr_1_valid; +wire RTL5_handshake_arr_2_valid; +wire RTL5_handshake_valid; +wire RTL5_out; wire corebit_undriven_inst0_out; wire corebit_undriven_inst1_out; wire corebit_undriven_inst10_out; @@ -377,73 +377,73 @@ wire [3:0] undriven_inst0_out; wire [3:0] undriven_inst1_out; wire [4:0] undriven_inst2_out; wire [4:0] undriven_inst3_out; -wire [1:0] RTL_inst0_ndarr [2:0]; -assign RTL_inst0_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; -assign RTL_inst0_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; -assign RTL_inst0_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; -bar_foo_RTL RTL_inst0 ( +wire [1:0] RTL4_ndarr [2:0]; +assign RTL4_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; +assign RTL4_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; +assign RTL4_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; +bar_foo_RTL RTL4 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst1_out), - .handshake_arr_0_valid(RTL_inst0_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL4_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst2_out), - .handshake_arr_1_valid(RTL_inst0_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL4_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst3_out), - .handshake_arr_2_valid(RTL_inst0_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL4_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst0_out), - .handshake_valid(RTL_inst0_handshake_valid), + .handshake_valid(RTL4_handshake_valid), .in1(undriven_inst0_out), .in2(undriven_inst1_out), - .ndarr(RTL_inst0_ndarr), - .out(RTL_inst0_out) -); -wire [1:0] RTL_inst1_ndarr [2:0]; -assign RTL_inst1_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; -assign RTL_inst1_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; -assign RTL_inst1_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; -bar_foo_RTL_unq1 RTL_inst1 ( + .ndarr(RTL4_ndarr), + .out(RTL4_out) +); +wire [1:0] RTL5_ndarr [2:0]; +assign RTL5_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; +assign RTL5_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; +assign RTL5_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; +bar_foo_RTL_unq1 RTL5 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst11_out), - .handshake_arr_0_valid(RTL_inst1_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL5_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst12_out), - .handshake_arr_1_valid(RTL_inst1_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL5_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst13_out), - .handshake_arr_2_valid(RTL_inst1_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL5_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst10_out), - .handshake_valid(RTL_inst1_handshake_valid), + .handshake_valid(RTL5_handshake_valid), .in1(undriven_inst2_out), .in2(undriven_inst3_out), - .ndarr(RTL_inst1_ndarr), - .out(RTL_inst1_out) + .ndarr(RTL5_ndarr), + .out(RTL5_out) ); bar_corebit_term corebit_term_inst0 ( - .in(RTL_inst0_out) + .in(RTL4_out) ); bar_corebit_term corebit_term_inst1 ( - .in(RTL_inst0_handshake_valid) + .in(RTL4_handshake_valid) ); bar_corebit_term corebit_term_inst2 ( - .in(RTL_inst0_handshake_arr_0_valid) + .in(RTL4_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst3 ( - .in(RTL_inst0_handshake_arr_1_valid) + .in(RTL4_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst4 ( - .in(RTL_inst0_handshake_arr_2_valid) + .in(RTL4_handshake_arr_2_valid) ); bar_corebit_term corebit_term_inst5 ( - .in(RTL_inst1_out) + .in(RTL5_out) ); bar_corebit_term corebit_term_inst6 ( - .in(RTL_inst1_handshake_valid) + .in(RTL5_handshake_valid) ); bar_corebit_term corebit_term_inst7 ( - .in(RTL_inst1_handshake_arr_0_valid) + .in(RTL5_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst8 ( - .in(RTL_inst1_handshake_arr_1_valid) + .in(RTL5_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst9 ( - .in(RTL_inst1_handshake_arr_2_valid) + .in(RTL5_handshake_arr_2_valid) ); bar_corebit_undriven corebit_undriven_inst0 ( .out(corebit_undriven_inst0_out) From a1c7b68b0d93a4ed2cb1431f34ff9a798e56b408 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 7 Dec 2022 15:53:32 -0800 Subject: [PATCH 29/61] Add comment --- magma/debug_rewriter.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 0870631e6..49a980283 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -41,7 +41,12 @@ def leave_FunctionDef( def debug(fn): indented_program_txt = inspect.getsource(fn) - program_txt = textwrap.dedent(indented_program_txt).lstrip() + program_txt = textwrap.dedent(indented_program_txt) + # Dedenting might not work because they might have a triple block quote + # string that's not indented, so as a fallback we try removing the initial + # indent at least, which is fine if the body is overindented as long as it's + # consistent + program_txt = program_txt.lstrip() tree = cst.parse_module(program_txt) wrapper = cst.metadata.MetadataWrapper(tree) tree = wrapper.visit(Transformer()) From 2432a0ca996becd81fec4a53671d5cca6d3cf25b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 12:54:30 -0800 Subject: [PATCH 30/61] Guard behind debug mode flag --- conftest.py | 1 + magma/circuit.py | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/conftest.py b/conftest.py index 983a4c6a9..697ac54c8 100644 --- a/conftest.py +++ b/conftest.py @@ -5,5 +5,6 @@ @pytest.fixture(autouse=True) def magma_test(): + m.config.set_debug_mode(True) magma.config.set_compile_dir('callee_file_dir') reset_global_context() diff --git a/magma/circuit.py b/magma/circuit.py index e94f4a384..236d02b2a 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -254,7 +254,9 @@ class CircuitKind(type): def __prepare__(name, bases, **kwargs): ctx = DefinitionContext(StagedPlacer(name)) push_definition_context(ctx, use_staged_logger=True) - return NamerDict() + if get_debug_mode(): + return NamerDict() + return type.__prepare__(name, bases, **kwargs) """Metaclass for creating circuits.""" def __new__(metacls, name, bases, dct): From f6e3e0d6511f28cb5c337ca12e5eb072368efad4 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 12:56:42 -0800 Subject: [PATCH 31/61] Fix conftest --- conftest.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conftest.py b/conftest.py index 697ac54c8..c7137cecf 100644 --- a/conftest.py +++ b/conftest.py @@ -5,6 +5,6 @@ @pytest.fixture(autouse=True) def magma_test(): - m.config.set_debug_mode(True) + magma.config.set_debug_mode(True) magma.config.set_compile_dir('callee_file_dir') reset_global_context() From 0b1cd45c419b9dde5d98c875f7bcaac317f93a4e Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:02:42 -0800 Subject: [PATCH 32/61] Separate debug mode and namer dict flag --- conftest.py | 2 +- magma/circuit.py | 4 ++-- magma/config.py | 1 + magma/generator.py | 4 +++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/conftest.py b/conftest.py index c7137cecf..181558e0e 100644 --- a/conftest.py +++ b/conftest.py @@ -5,6 +5,6 @@ @pytest.fixture(autouse=True) def magma_test(): - magma.config.set_debug_mode(True) + magma.config.use_namer_dict = True magma.config.set_compile_dir('callee_file_dir') reset_global_context() diff --git a/magma/circuit.py b/magma/circuit.py index 236d02b2a..f32b5298e 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -14,7 +14,6 @@ from .common import deprecated, setattrs, OrderedIdentitySet from .interface import * from .wire import * -from .config import get_debug_mode, set_debug_mode from .debug import get_callee_frame_info, debug_info from .is_definition import isdefinition from .placer import Placer, StagedPlacer @@ -27,6 +26,7 @@ pass from magma.clock import is_clock_or_nested_clock, Clock, ClockTypes +from magma.config import get_debug_mode, set_debug_mode, config from magma.definition_context import ( DefinitionContext, definition_context_manager, @@ -254,7 +254,7 @@ class CircuitKind(type): def __prepare__(name, bases, **kwargs): ctx = DefinitionContext(StagedPlacer(name)) push_definition_context(ctx, use_staged_logger=True) - if get_debug_mode(): + if config.use_namer_dict(): return NamerDict() return type.__prepare__(name, bases, **kwargs) diff --git a/magma/config.py b/magma/config.py index b644135e5..1ca75a975 100644 --- a/magma/config.py +++ b/magma/config.py @@ -90,6 +90,7 @@ def __setitem__(self, key, value): config = ConfigManager( compile_dir=RuntimeConfig("normal"), debug_mode=RuntimeConfig(False), + use_namer_dict=RuntimeConfig(False) ) diff --git a/magma/generator.py b/magma/generator.py index b56f6ff7e..67cd70406 100644 --- a/magma/generator.py +++ b/magma/generator.py @@ -6,6 +6,7 @@ DebugDefineCircuitKind, NamerDict) from . import cache_definition from magma.common import ParamDict +from magma.config import config from hwtypes import BitVector @@ -144,7 +145,8 @@ def bind(cls, monitor): cls.bind_generators.append(monitor) def __setattr__(cls, key, value): - cls._namer_dict[key] = value + if config.use_namer_dict: + cls._namer_dict[key] = value super().__setattr__(key, value) From 00653f8be2d229d0a76c57c982efcc0975200162 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:05:07 -0800 Subject: [PATCH 33/61] Fix guard --- magma/circuit.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/magma/circuit.py b/magma/circuit.py index f32b5298e..814f94cef 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -254,7 +254,7 @@ class CircuitKind(type): def __prepare__(name, bases, **kwargs): ctx = DefinitionContext(StagedPlacer(name)) push_definition_context(ctx, use_staged_logger=True) - if config.use_namer_dict(): + if config.use_namer_dict: return NamerDict() return type.__prepare__(name, bases, **kwargs) From 37050656083962b376ae7f5e71db1c2c8bfa86e0 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:09:12 -0800 Subject: [PATCH 34/61] Fix conftest --- conftest.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/conftest.py b/conftest.py index 181558e0e..7d643255a 100644 --- a/conftest.py +++ b/conftest.py @@ -1,10 +1,11 @@ import pytest import magma.config +from magma.config import config from magma.util import reset_global_context @pytest.fixture(autouse=True) def magma_test(): - magma.config.use_namer_dict = True + config.use_namer_dict = True magma.config.set_compile_dir('callee_file_dir') reset_global_context() From 972657854a0f5087ac481a10819469853a3c1b9b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:11:57 -0800 Subject: [PATCH 35/61] Add config flag --- benchmarks/debug.py | 7 +++++-- conftest.py | 1 + magma/config.py | 3 ++- magma/generator.py | 3 +-- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/benchmarks/debug.py b/benchmarks/debug.py index 46d20610f..d5ac4965f 100644 --- a/benchmarks/debug.py +++ b/benchmarks/debug.py @@ -4,6 +4,11 @@ def gen_circuit(debug_mode, n=8): + if debug_mode == 0: + m.config.config.use_generator_debug_rewriter = True + else: + m.config.config.use_generator_debug_rewriter = False + class Foo(m.Generator2): if debug_mode == 2: def __init__(self, n): @@ -20,8 +25,6 @@ def __init__(self, n): self.io.O @= x.reduce_xor() m.config.set_debug_mode(False) else: - _disable_debug_ = True - def __init__(self, n): self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bit)) x = m.Bits[n]() diff --git a/conftest.py b/conftest.py index 7d643255a..1215ab47e 100644 --- a/conftest.py +++ b/conftest.py @@ -7,5 +7,6 @@ @pytest.fixture(autouse=True) def magma_test(): config.use_namer_dict = True + config.use_generator_debug_rewriter = True magma.config.set_compile_dir('callee_file_dir') reset_global_context() diff --git a/magma/config.py b/magma/config.py index 1ca75a975..bbfc1a69a 100644 --- a/magma/config.py +++ b/magma/config.py @@ -90,7 +90,8 @@ def __setitem__(self, key, value): config = ConfigManager( compile_dir=RuntimeConfig("normal"), debug_mode=RuntimeConfig(False), - use_namer_dict=RuntimeConfig(False) + use_namer_dict=RuntimeConfig(False), + use_generator_debug_rewriter=RuntimeConfig(False) ) diff --git a/magma/generator.py b/magma/generator.py index 76322a778..54090da9a 100644 --- a/magma/generator.py +++ b/magma/generator.py @@ -78,8 +78,7 @@ def _make_type(cls, *args, **kwargs): name = cls.__name__ bases = (cls._base_cls_,) dct = cls._base_metacls_.__prepare__(name, bases) - if not getattr(cls, "_disable_debug_", False): - # TODO: temp flag for debug bench, do not need + if config.use_generator_debug_rewriter: cls.__init__ = debug(cls.__init__) cls.__init__(dummy, *args, **kwargs) dct.update(dict(dummy.__dict__)) From 67ee66ba964c31c3aafe447c5413e18dd896d0c8 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:20:59 -0800 Subject: [PATCH 36/61] Update configure pattern --- conftest.py | 10 ++++++---- tests/test_ir_pass.py | 1 + 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/conftest.py b/conftest.py index 7d643255a..22472eb74 100644 --- a/conftest.py +++ b/conftest.py @@ -1,11 +1,13 @@ import pytest -import magma.config -from magma.config import config +from magma.config import config as magma_config from magma.util import reset_global_context +def pytst_configure(config): + magma_config.compile_dir = 'callee_file_dir' + magma_config.use_namer_dict = True + + @pytest.fixture(autouse=True) def magma_test(): - config.use_namer_dict = True - magma.config.set_compile_dir('callee_file_dir') reset_global_context() diff --git a/tests/test_ir_pass.py b/tests/test_ir_pass.py index 6087d78fd..e2711df5f 100644 --- a/tests/test_ir_pass.py +++ b/tests/test_ir_pass.py @@ -1,3 +1,4 @@ +from magma.config import config from magma.passes import IRPass from magma import Bit, Circuit, IO, In, Out, wire From 60a43827c637485f686a92849e1f1ea0bb9a1e5d Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:21:18 -0800 Subject: [PATCH 37/61] Fix typo --- conftest.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conftest.py b/conftest.py index 22472eb74..f67e39b47 100644 --- a/conftest.py +++ b/conftest.py @@ -3,7 +3,7 @@ from magma.util import reset_global_context -def pytst_configure(config): +def pytest_configure(config): magma_config.compile_dir = 'callee_file_dir' magma_config.use_namer_dict = True From 57cff72070625c8585456ff1354f1092e70bc46a Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:29:49 -0800 Subject: [PATCH 38/61] Fix bench --- benchmarks/debug.py | 2 +- benchmarks/debug.svg | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/benchmarks/debug.py b/benchmarks/debug.py index d5ac4965f..057a0bdf6 100644 --- a/benchmarks/debug.py +++ b/benchmarks/debug.py @@ -4,7 +4,7 @@ def gen_circuit(debug_mode, n=8): - if debug_mode == 0: + if debug_mode == 2: m.config.config.use_generator_debug_rewriter = True else: m.config.config.use_generator_debug_rewriter = False diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg index f5e4a888a..131c2b633 100644 --- a/benchmarks/debug.svg +++ b/benchmarks/debug.svg @@ -1,4 +1,4 @@ -Pygal000.020.020.040.040.060.060.080.080.10.10.120.120.140.140.160.160.180.180.20.20.220.220.240.240.099069942147.9435897435897446.507246155224150.259655003339.4280.00.096152385530.8564102564102449.5323991726975OffOldNew \ No newline at end of file +Pygal000.010.010.020.020.030.030.040.040.050.050.060.060.070.070.080.080.090.090.10.10.003796975012147.9435897435897539.34357985381220.08692598401339.4322.87856438523590.103392629530.8564102564102280.0OffOldNew \ No newline at end of file From ae238840bd1135deb6b426683f6c9abccd01ca99 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:31:38 -0800 Subject: [PATCH 39/61] update gold --- tests/gold/test_when_reg_ce_implicit_override.mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gold/test_when_reg_ce_implicit_override.mlir b/tests/gold/test_when_reg_ce_implicit_override.mlir index 417bf583d..c27f90871 100644 --- a/tests/gold/test_when_reg_ce_implicit_override.mlir +++ b/tests/gold/test_when_reg_ce_implicit_override.mlir @@ -11,7 +11,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %4, %I : i8 } } - %6 = sv.reg {name = "Register_inst0"} : !hw.inout + %6 = sv.reg {name = "x"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %x { sv.passign %6, %2 : i8 From ca331fb833f83e1bb756614673d085f7ce88a325 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:39:06 -0800 Subject: [PATCH 40/61] Fix guard --- magma/backend/coreir/insert_coreir_wires.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/magma/backend/coreir/insert_coreir_wires.py b/magma/backend/coreir/insert_coreir_wires.py index 1592ed98e..9465bfdca 100644 --- a/magma/backend/coreir/insert_coreir_wires.py +++ b/magma/backend/coreir/insert_coreir_wires.py @@ -66,8 +66,9 @@ def _make_wire(self, driver, value, definition): recast = ( self._flatten and ( - isinstance(value, _ClockType) - and not isinstance(wire_output, type(value)) + not isinstance(wire_output, type(value)) and + isinstance(value, _ClockType) or + isinstance(wire_output, _ClockType) ) ) if recast: From bd29c1196ae4a3786f62589825871ac8c5b9b08c Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 13 Dec 2022 13:47:51 -0800 Subject: [PATCH 41/61] Fix config --- conftest.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conftest.py b/conftest.py index 10b7b7368..b4bd2b5c5 100644 --- a/conftest.py +++ b/conftest.py @@ -6,7 +6,7 @@ def pytest_configure(config): magma_config.compile_dir = 'callee_file_dir' magma_config.use_namer_dict = True - config.use_generator_debug_rewriter = True + magma_config.use_generator_debug_rewriter = True @pytest.fixture(autouse=True) From a3a2452168f2251277a14548d053a9ca7a45bff7 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 15 Dec 2022 12:27:04 -0800 Subject: [PATCH 42/61] Temporarily disable namer-dict globally --- conftest.py | 3 +- tests/gold/TopGen.json | 14 +- .../gold/test_assign_operator2_3_coreir.json | 6 +- tests/gold/test_assign_operator2_3_verilog.v | 4 +- .../test_assign_operator2_None_coreir.json | 6 +- .../gold/test_assign_operator2_None_verilog.v | 4 +- tests/gold/test_assign_operator_3_coreir.json | 8 +- tests/gold/test_assign_operator_3_verilog.v | 6 +- .../test_assign_operator_None_coreir.json | 8 +- .../gold/test_assign_operator_None_verilog.v | 6 +- .../test_compile_guard_anon_driver_driven.v | 14 +- ...st_compile_guard_anon_driver_nested_type.v | 299 ++++++------------ tests/gold/test_compile_guard_assert.json | 16 +- .../gold/test_compile_guard_drive_output.json | 12 +- tests/gold/test_when_memory_Bits8.mlir | 2 +- .../test_when_memory_Tuplex_Bit_y_Bits7.mlir | 2 +- tests/gold/test_when_non_port.mlir | 5 +- tests/gold/test_when_recursive_non_port.mlir | 17 +- tests/gold/test_when_reg_ce.mlir | 2 +- .../gold/test_when_reg_ce_already_wired.mlir | 2 +- .../gold/test_when_reg_ce_explicit_wire.mlir | 2 +- .../test_when_reg_ce_explicit_wire_twice.mlir | 2 +- ...hen_reg_ce_explicit_wire_with_default.mlir | 2 +- .../test_when_reg_ce_implicit_override.mlir | 2 +- .../test_when_reg_ce_implicit_wire_twice.mlir | 2 +- tests/gold/test_when_reg_ce_multiple.mlir | 2 +- tests/gold/test_when_register_default.mlir | 2 +- tests/gold/test_when_register_no_default.mlir | 2 +- tests/gold/test_when_spurious_assign.mlir | 6 +- tests/gold/test_when_user_reg.mlir | 2 +- tests/gold/test_when_user_reg_enable.mlir | 2 +- tests/gold/uniquification_key_error_mux.json | 10 +- tests/gold/uniquify_equal.json | 10 +- tests/gold/uniquify_multiple_rename.json | 18 +- tests/gold/uniquify_unequal.json | 16 +- tests/test_backend/test_mlir/examples.py | 2 +- .../golds/complex_mixed_direction_ports2.mlir | 2 +- .../test_backend/test_mlir/golds/counter.mlir | 2 +- .../golds/simple_memory_wrapper.mlir | 2 +- .../golds/simple_module_params_instance.mlir | 2 +- .../test_mlir/golds/simple_redefinition.mlir | 4 +- .../test_mlir/golds/xmr_bind.mlir | 6 +- tests/test_circuit/gold/test_add8cin.json | 10 +- .../gold/test_anon_value_Array((2, Bit)).json | 13 +- .../gold/test_anon_value_Array((2, Bit)).v | 6 +- .../gold/test_anon_value_Bit.json | 12 +- tests/test_circuit/gold/test_anon_value_Bit.v | 6 +- .../gold/test_anon_value_Bits(2).json | 13 +- .../gold/test_anon_value_Bits(2).v | 6 +- .../test_anon_value_Tuple(x=Bit,y=Bit).json | 15 +- .../gold/test_anon_value_Tuple(x=Bit,y=Bit).v | 18 +- .../gold/test_ignore_undriven_coreir.json | 14 +- .../test_ignore_unused_undriven_hierarchy.v | 16 +- tests/test_circuit/gold/test_unwired_output.v | 4 +- tests/test_circuit/test_define.py | 2 +- tests/test_circuit/test_inspect.py | 4 +- tests/test_circuit/test_new_style_syntax.py | 14 +- tests/test_circuit/test_reg_enable_call.py | 8 +- tests/test_compile/gold/test_header_footer.v | 8 +- tests/test_coreir/gold/linker_test0.json | 8 +- .../gold/test_auto_wire_tuple_clocks.v | 8 +- .../test_multi_direction_tuple_instance.json | 6 +- tests/test_coreir/gold/test_nesting.json | 18 +- .../test_ignore_unused_undriven_hierarchy.v | 16 +- tests/test_errors/test_tuple_errors.py | 4 +- tests/test_higher/test_braid.py | 8 +- tests/test_higher/test_curry.py | 8 +- tests/test_higher/test_join.py | 2 +- tests/test_ir/gold/declaretest.v | 6 +- tests/test_ir/test_ir.py | 16 +- tests/test_ir_pass.py | 23 +- tests/test_meta/gold/creg.v | 6 +- ...oreir_wires_arr_tuple_TuplexInBityOutBit.v | 10 +- ...insert_coreir_wires_instance_Array5Bits5.v | 22 +- .../gold/insert_coreir_wires_instance_Bit.v | 8 +- .../gold/insert_coreir_wires_instance_Bits5.v | 8 +- ...sert_coreir_wires_instance_TupleBits5Bit.v | 12 +- ...t_coreir_wires_temp_array_not_whole_anon.v | 8 +- ...rt_coreir_wires_tuple_TuplexInBityOutBit.v | 10 +- tests/test_primitives/gold/test_memory_arr.v | 2 +- .../gold/test_memory_basic.mlir | 2 +- .../gold/test_memory_product.v | 2 +- .../gold/test_memory_product_init.v | 2 +- .../gold/test_memory_read_latency_False.v | 8 +- .../gold/test_memory_read_latency_True.v | 8 +- .../gold/test_memory_read_only.v | 8 +- tests/test_smart/test_smart_bits.py | 78 ++--- tests/test_symbol_table_generation.py | 13 +- .../gold/TestSequential2NestedLoopUnroll.v | 8 +- .../test_syntax/gold/test_inline_comb_basic.v | 15 +- .../test_syntax/gold/test_inline_comb_list.v | 14 +- .../test_syntax/gold/test_inline_comb_wire.v | 7 +- .../gold/test_renamed_args_wire.json | 6 +- .../gold/test_AsyncResetN[Out]_cast.v | 12 +- .../gold/test_AsyncReset[Out]_cast.v | 12 +- tests/test_type/gold/test_anon_bits.v | 25 +- tests/test_type/gold/test_array2_2d_tuple.v | 34 +- .../gold/test_array2_nested_bits_temporary.v | 20 +- .../gold/test_insert_wrap_casts_temporary.v | 47 +-- .../gold/test_ndarray_dynamic_getitem.v | 58 ++-- .../gold/test_ndarray_dynamic_getitem2.v | 106 +++---- .../gold/test_ndarray_dynamic_getitem3.v | 154 ++++----- tests/test_type/test_array2.py | 18 +- tests/test_type/test_clock.py | 2 +- tests/test_type/test_const_wire_golden.json | 4 +- .../test_coreir_wrap_golden_AsyncReset.json | 12 +- .../test_coreir_wrap_golden_Clock.json | 12 +- tests/test_verilog/gold/Top.v | 16 +- tests/test_verilog/gold/bind_test.v | 6 +- tests/test_verilog/gold/bind_uniq_test.v | 98 +++--- .../test_verilog/gold/test_inline_tuple.json | 46 +-- .../test_verilog/gold/test_inline_tuple.mlir | 10 +- tests/test_verilog/gold/test_inline_tuple.sv | 14 +- ...test_inline_verilog_share_default_clocks.v | 28 +- tests/test_verilog/gold/test_pad.v | 22 +- tests/test_verilog/gold/test_rxmod_top.json | 10 +- .../gold/top-declare-coreir-verilog.v | 14 +- .../test_verilog/gold/top-declare-coreir.json | 20 +- tests/test_verilog/gold/top-declare-verilog.v | 10 +- .../gold/top-define-coreir-verilog.json | 20 +- .../gold/top-define-coreir-verilog.v | 14 +- .../test_verilog/gold/top-define-coreir.json | 20 +- tests/test_verilog/gold/top-define-verilog.v | 10 +- tests/test_wire/gold/arg1.v | 6 +- tests/test_wire/gold/arg2.v | 6 +- tests/test_wire/gold/array1.v | 6 +- tests/test_wire/gold/array2.v | 6 +- tests/test_wire/gold/array3.v | 6 +- tests/test_wire/gold/call1.v | 6 +- tests/test_wire/gold/call2.v | 6 +- tests/test_wire/gold/compose.v | 10 +- tests/test_wire/gold/const0.v | 12 +- tests/test_wire/gold/const1.v | 12 +- tests/test_wire/gold/const_bits_Bits_1.v | 8 +- tests/test_wire/gold/const_bits_Bits_2.v | 8 +- tests/test_wire/gold/const_bits_Bits_3.v | 8 +- tests/test_wire/gold/const_bits_SInt_1.v | 8 +- tests/test_wire/gold/const_bits_SInt_2.v | 8 +- tests/test_wire/gold/const_bits_SInt_3.v | 8 +- tests/test_wire/gold/const_bits_UInt_1.v | 8 +- tests/test_wire/gold/const_bits_UInt_2.v | 8 +- tests/test_wire/gold/const_bits_UInt_3.v | 8 +- tests/test_wire/gold/flip.v | 6 +- tests/test_wire/gold/named1.v | 6 +- tests/test_wire/gold/named2a.v | 6 +- tests/test_wire/gold/named2b.v | 6 +- tests/test_wire/gold/named2c.v | 6 +- tests/test_wire/gold/pos.v | 6 +- tests/test_wire/test_check_wiring_context.py | 12 +- 149 files changed, 947 insertions(+), 1208 deletions(-) diff --git a/conftest.py b/conftest.py index f67e39b47..1eba87136 100644 --- a/conftest.py +++ b/conftest.py @@ -5,7 +5,8 @@ def pytest_configure(config): magma_config.compile_dir = 'callee_file_dir' - magma_config.use_namer_dict = True + # TODO: Enable this globally for testing + # magma_config.use_namer_dict = True @pytest.fixture(autouse=True) diff --git a/tests/gold/TopGen.json b/tests/gold/TopGen.json index 13138fbce..fd9add260 100644 --- a/tests/gold/TopGen.json +++ b/tests/gold/TopGen.json @@ -17,20 +17,20 @@ ["z","Bit"] ]], "instances":{ + "MyMux1x2_inst0":{ + "modref":"global.MyMux1x2" + }, "const_0_1":{ "genref":"coreir.const", "genargs":{"width":["Int",1]}, "modargs":{"value":[["BitVector",1],"1'h0"]} - }, - "mux":{ - "modref":"global.MyMux1x2" } }, "connections":[ - ["mux.S","const_0_1.out"], - ["self.x","mux.I0.0"], - ["self.y","mux.I1.0"], - ["self.z","mux.O.0"] + ["self.x","MyMux1x2_inst0.I0.0"], + ["self.y","MyMux1x2_inst0.I1.0"], + ["self.z","MyMux1x2_inst0.O.0"], + ["const_0_1.out","MyMux1x2_inst0.S"] ] } } diff --git a/tests/gold/test_assign_operator2_3_coreir.json b/tests/gold/test_assign_operator2_3_coreir.json index 5b8901bd2..486b0f5a6 100644 --- a/tests/gold/test_assign_operator2_3_coreir.json +++ b/tests/gold/test_assign_operator2_3_coreir.json @@ -16,13 +16,13 @@ ["c",["Array",3,"Bit"]] ]], "instances":{ - "and2":{ + "And3_inst0":{ "modref":"global.And3" } }, "connections":[ - ["and2.O","and2.I0"], - ["self.a","and2.I1"], + ["And3_inst0.O","And3_inst0.I0"], + ["self.a","And3_inst0.I1"], ["self.c","self.b"] ] } diff --git a/tests/gold/test_assign_operator2_3_verilog.v b/tests/gold/test_assign_operator2_3_verilog.v index d787afb1d..235247117 100644 --- a/tests/gold/test_assign_operator2_3_verilog.v +++ b/tests/gold/test_assign_operator2_3_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator2_3_verilog (input [2:0] a, input [2:0] b, output [2:0] c); -wire [2:0] and2_O; -And3 and2 (.I0(and2_O), .I1(a), .O(and2_O)); +wire [2:0] And3_inst0_O; +And3 And3_inst0 (.I0(And3_inst0_O), .I1(a), .O(And3_inst0_O)); assign c = b; endmodule diff --git a/tests/gold/test_assign_operator2_None_coreir.json b/tests/gold/test_assign_operator2_None_coreir.json index b349fb11f..6f2c2e82d 100644 --- a/tests/gold/test_assign_operator2_None_coreir.json +++ b/tests/gold/test_assign_operator2_None_coreir.json @@ -16,13 +16,13 @@ ["c","Bit"] ]], "instances":{ - "and2":{ + "AndNone_inst0":{ "modref":"global.AndNone" } }, "connections":[ - ["and2.O","and2.I0"], - ["self.a","and2.I1"], + ["AndNone_inst0.O","AndNone_inst0.I0"], + ["self.a","AndNone_inst0.I1"], ["self.c","self.b"] ] } diff --git a/tests/gold/test_assign_operator2_None_verilog.v b/tests/gold/test_assign_operator2_None_verilog.v index 9508980b2..2429c453a 100644 --- a/tests/gold/test_assign_operator2_None_verilog.v +++ b/tests/gold/test_assign_operator2_None_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator2_None_verilog (input a, input b, output c); -wire and2_O; -AndNone and2 (.I0(and2_O), .I1(a), .O(and2_O)); +wire AndNone_inst0_O; +AndNone AndNone_inst0 (.I0(AndNone_inst0_O), .I1(a), .O(AndNone_inst0_O)); assign c = b; endmodule diff --git a/tests/gold/test_assign_operator_3_coreir.json b/tests/gold/test_assign_operator_3_coreir.json index 850895368..47a75dfed 100644 --- a/tests/gold/test_assign_operator_3_coreir.json +++ b/tests/gold/test_assign_operator_3_coreir.json @@ -16,14 +16,14 @@ ["c",["Array",3,"Bit"]] ]], "instances":{ - "and2":{ + "And3_inst0":{ "modref":"global.And3" } }, "connections":[ - ["self.a","and2.I0"], - ["self.b","and2.I1"], - ["self.c","and2.O"] + ["self.a","And3_inst0.I0"], + ["self.b","And3_inst0.I1"], + ["self.c","And3_inst0.O"] ] } } diff --git a/tests/gold/test_assign_operator_3_verilog.v b/tests/gold/test_assign_operator_3_verilog.v index fdfd0e47b..b0aaf0f15 100644 --- a/tests/gold/test_assign_operator_3_verilog.v +++ b/tests/gold/test_assign_operator_3_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator_3_verilog (input [2:0] a, input [2:0] b, output [2:0] c); -wire [2:0] and2_O; -And3 and2 (.I0(a), .I1(b), .O(and2_O)); -assign c = and2_O; +wire [2:0] And3_inst0_O; +And3 And3_inst0 (.I0(a), .I1(b), .O(And3_inst0_O)); +assign c = And3_inst0_O; endmodule diff --git a/tests/gold/test_assign_operator_None_coreir.json b/tests/gold/test_assign_operator_None_coreir.json index cc6f8cb75..63b6c2aa6 100644 --- a/tests/gold/test_assign_operator_None_coreir.json +++ b/tests/gold/test_assign_operator_None_coreir.json @@ -16,14 +16,14 @@ ["c","Bit"] ]], "instances":{ - "and2":{ + "AndNone_inst0":{ "modref":"global.AndNone" } }, "connections":[ - ["self.a","and2.I0"], - ["self.b","and2.I1"], - ["self.c","and2.O"] + ["self.a","AndNone_inst0.I0"], + ["self.b","AndNone_inst0.I1"], + ["self.c","AndNone_inst0.O"] ] } } diff --git a/tests/gold/test_assign_operator_None_verilog.v b/tests/gold/test_assign_operator_None_verilog.v index 1311cfe38..f3015eab4 100644 --- a/tests/gold/test_assign_operator_None_verilog.v +++ b/tests/gold/test_assign_operator_None_verilog.v @@ -1,6 +1,6 @@ module test_assign_operator_None_verilog (input a, input b, output c); -wire and2_O; -AndNone and2 (.I0(a), .I1(b), .O(and2_O)); -assign c = and2_O; +wire AndNone_inst0_O; +AndNone AndNone_inst0 (.I0(a), .I1(b), .O(AndNone_inst0_O)); +assign c = AndNone_inst0_O; endmodule diff --git a/tests/gold/test_compile_guard_anon_driver_driven.v b/tests/gold/test_compile_guard_anon_driver_driven.v index 4f1a8a7b4..bda3fab10 100644 --- a/tests/gold/test_compile_guard_anon_driver_driven.v +++ b/tests/gold/test_compile_guard_anon_driver_driven.v @@ -16,13 +16,6 @@ module coreir_reg #( assign out = outReg; endmodule -module corebit_wire ( - input in, - output out -); - assign out = in; -endmodule - module Register ( input I, output O, @@ -57,16 +50,11 @@ module _Top ( input I, input CLK ); -wire x_out; `ifdef COND A A ( - .port_0(x_out), + .port_0(I), .port_1(CLK) ); `endif -corebit_wire x ( - .in(I), - .out(x_out) -); endmodule diff --git a/tests/gold/test_compile_guard_anon_driver_nested_type.v b/tests/gold/test_compile_guard_anon_driver_nested_type.v index 8420ec94e..ba6f4d9a2 100644 --- a/tests/gold/test_compile_guard_anon_driver_nested_type.v +++ b/tests/gold/test_compile_guard_anon_driver_nested_type.v @@ -1,12 +1,3 @@ -module coreir_wire #( - parameter width = 1 -) ( - input [width-1:0] in, - output [width-1:0] out -); - assign out = in; -endmodule - module coreir_reg #( parameter width = 1, parameter clk_posedge = 1, @@ -234,200 +225,110 @@ module _Top ( input I, input CLK ); -wire [9:0] x_0_x_out; -wire [9:0] x_1_x_out; -wire [9:0] x_2_x_out; -wire [9:0] x_3_x_out; -wire [9:0] x_4_x_out; -wire [9:0] x_5_x_out; -wire [9:0] x_6_x_out; -wire [9:0] x_7_x_out; -wire [9:0] x_8_x_out; -wire [9:0] x_9_x_out; `ifdef COND A A ( - .port_0(x_0_x_out[0]), - .port_1(x_0_x_out[1]), - .port_2(x_0_x_out[2]), - .port_3(x_0_x_out[3]), - .port_4(x_0_x_out[4]), - .port_5(x_0_x_out[5]), - .port_6(x_0_x_out[6]), - .port_7(x_0_x_out[7]), - .port_8(x_0_x_out[8]), - .port_9(x_0_x_out[9]), - .port_10(x_1_x_out[0]), - .port_11(x_1_x_out[1]), - .port_12(x_1_x_out[2]), - .port_13(x_1_x_out[3]), - .port_14(x_1_x_out[4]), - .port_15(x_1_x_out[5]), - .port_16(x_1_x_out[6]), - .port_17(x_1_x_out[7]), - .port_18(x_1_x_out[8]), - .port_19(x_1_x_out[9]), - .port_20(x_2_x_out[0]), - .port_21(x_2_x_out[1]), - .port_22(x_2_x_out[2]), - .port_23(x_2_x_out[3]), - .port_24(x_2_x_out[4]), - .port_25(x_2_x_out[5]), - .port_26(x_2_x_out[6]), - .port_27(x_2_x_out[7]), - .port_28(x_2_x_out[8]), - .port_29(x_2_x_out[9]), - .port_30(x_3_x_out[0]), - .port_31(x_3_x_out[1]), - .port_32(x_3_x_out[2]), - .port_33(x_3_x_out[3]), - .port_34(x_3_x_out[4]), - .port_35(x_3_x_out[5]), - .port_36(x_3_x_out[6]), - .port_37(x_3_x_out[7]), - .port_38(x_3_x_out[8]), - .port_39(x_3_x_out[9]), - .port_40(x_4_x_out[0]), - .port_41(x_4_x_out[1]), - .port_42(x_4_x_out[2]), - .port_43(x_4_x_out[3]), - .port_44(x_4_x_out[4]), - .port_45(x_4_x_out[5]), - .port_46(x_4_x_out[6]), - .port_47(x_4_x_out[7]), - .port_48(x_4_x_out[8]), - .port_49(x_4_x_out[9]), - .port_50(x_5_x_out[0]), - .port_51(x_5_x_out[1]), - .port_52(x_5_x_out[2]), - .port_53(x_5_x_out[3]), - .port_54(x_5_x_out[4]), - .port_55(x_5_x_out[5]), - .port_56(x_5_x_out[6]), - .port_57(x_5_x_out[7]), - .port_58(x_5_x_out[8]), - .port_59(x_5_x_out[9]), - .port_60(x_6_x_out[0]), - .port_61(x_6_x_out[1]), - .port_62(x_6_x_out[2]), - .port_63(x_6_x_out[3]), - .port_64(x_6_x_out[4]), - .port_65(x_6_x_out[5]), - .port_66(x_6_x_out[6]), - .port_67(x_6_x_out[7]), - .port_68(x_6_x_out[8]), - .port_69(x_6_x_out[9]), - .port_70(x_7_x_out[0]), - .port_71(x_7_x_out[1]), - .port_72(x_7_x_out[2]), - .port_73(x_7_x_out[3]), - .port_74(x_7_x_out[4]), - .port_75(x_7_x_out[5]), - .port_76(x_7_x_out[6]), - .port_77(x_7_x_out[7]), - .port_78(x_7_x_out[8]), - .port_79(x_7_x_out[9]), - .port_80(x_8_x_out[0]), - .port_81(x_8_x_out[1]), - .port_82(x_8_x_out[2]), - .port_83(x_8_x_out[3]), - .port_84(x_8_x_out[4]), - .port_85(x_8_x_out[5]), - .port_86(x_8_x_out[6]), - .port_87(x_8_x_out[7]), - .port_88(x_8_x_out[8]), - .port_89(x_8_x_out[9]), - .port_90(x_9_x_out[0]), - .port_91(x_9_x_out[1]), - .port_92(x_9_x_out[2]), - .port_93(x_9_x_out[3]), - .port_94(x_9_x_out[4]), - .port_95(x_9_x_out[5]), - .port_96(x_9_x_out[6]), - .port_97(x_9_x_out[7]), - .port_98(x_9_x_out[8]), - .port_99(x_9_x_out[9]), + .port_0(I), + .port_1(I), + .port_2(I), + .port_3(I), + .port_4(I), + .port_5(I), + .port_6(I), + .port_7(I), + .port_8(I), + .port_9(I), + .port_10(I), + .port_11(I), + .port_12(I), + .port_13(I), + .port_14(I), + .port_15(I), + .port_16(I), + .port_17(I), + .port_18(I), + .port_19(I), + .port_20(I), + .port_21(I), + .port_22(I), + .port_23(I), + .port_24(I), + .port_25(I), + .port_26(I), + .port_27(I), + .port_28(I), + .port_29(I), + .port_30(I), + .port_31(I), + .port_32(I), + .port_33(I), + .port_34(I), + .port_35(I), + .port_36(I), + .port_37(I), + .port_38(I), + .port_39(I), + .port_40(I), + .port_41(I), + .port_42(I), + .port_43(I), + .port_44(I), + .port_45(I), + .port_46(I), + .port_47(I), + .port_48(I), + .port_49(I), + .port_50(I), + .port_51(I), + .port_52(I), + .port_53(I), + .port_54(I), + .port_55(I), + .port_56(I), + .port_57(I), + .port_58(I), + .port_59(I), + .port_60(I), + .port_61(I), + .port_62(I), + .port_63(I), + .port_64(I), + .port_65(I), + .port_66(I), + .port_67(I), + .port_68(I), + .port_69(I), + .port_70(I), + .port_71(I), + .port_72(I), + .port_73(I), + .port_74(I), + .port_75(I), + .port_76(I), + .port_77(I), + .port_78(I), + .port_79(I), + .port_80(I), + .port_81(I), + .port_82(I), + .port_83(I), + .port_84(I), + .port_85(I), + .port_86(I), + .port_87(I), + .port_88(I), + .port_89(I), + .port_90(I), + .port_91(I), + .port_92(I), + .port_93(I), + .port_94(I), + .port_95(I), + .port_96(I), + .port_97(I), + .port_98(I), + .port_99(I), .port_100(CLK) ); `endif -wire [9:0] x_0_x_in; -assign x_0_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_0_x ( - .in(x_0_x_in), - .out(x_0_x_out) -); -wire [9:0] x_1_x_in; -assign x_1_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_1_x ( - .in(x_1_x_in), - .out(x_1_x_out) -); -wire [9:0] x_2_x_in; -assign x_2_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_2_x ( - .in(x_2_x_in), - .out(x_2_x_out) -); -wire [9:0] x_3_x_in; -assign x_3_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_3_x ( - .in(x_3_x_in), - .out(x_3_x_out) -); -wire [9:0] x_4_x_in; -assign x_4_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_4_x ( - .in(x_4_x_in), - .out(x_4_x_out) -); -wire [9:0] x_5_x_in; -assign x_5_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_5_x ( - .in(x_5_x_in), - .out(x_5_x_out) -); -wire [9:0] x_6_x_in; -assign x_6_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_6_x ( - .in(x_6_x_in), - .out(x_6_x_out) -); -wire [9:0] x_7_x_in; -assign x_7_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_7_x ( - .in(x_7_x_in), - .out(x_7_x_out) -); -wire [9:0] x_8_x_in; -assign x_8_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_8_x ( - .in(x_8_x_in), - .out(x_8_x_out) -); -wire [9:0] x_9_x_in; -assign x_9_x_in = {I,I,I,I,I,I,I,I,I,I}; -coreir_wire #( - .width(10) -) x_9_x ( - .in(x_9_x_in), - .out(x_9_x_out) -); endmodule diff --git a/tests/gold/test_compile_guard_assert.json b/tests/gold/test_compile_guard_assert.json index c420ca557..5c3dd1a15 100644 --- a/tests/gold/test_compile_guard_assert.json +++ b/tests/gold/test_compile_guard_assert.json @@ -12,6 +12,9 @@ "ASSERT_ON_compile_guard_inline_verilog_inst_0":{ "modref":"global.ASSERT_ON_compile_guard_inline_verilog_0" }, + "Register_inst0":{ + "modref":"global.Register_unq1" + }, "const_1_2":{ "genref":"coreir.const", "genargs":{"width":["Int",2]}, @@ -27,9 +30,6 @@ "genargs":{"width":["Int",4]}, "modargs":{"value":[["BitVector",4],"4'h3"]} }, - "count":{ - "modref":"global.Register_unq1" - }, "magma_Bit_not_inst0":{ "modref":"corebit.not" }, @@ -51,14 +51,14 @@ }, "connections":[ ["magma_Bit_or_inst0.out","ASSERT_ON_compile_guard_inline_verilog_inst_0.__magma_inline_value_0"], + ["self.port_0","Register_inst0.CE"], + ["self.port_1","Register_inst0.CLK"], + ["magma_UInt_2_add_inst0.out","Register_inst0.I"], + ["magma_UInt_2_add_inst0.in0","Register_inst0.O"], + ["magma_UInt_2_eq_inst0.in0","Register_inst0.O"], ["magma_UInt_2_add_inst0.in1","const_1_2.out"], ["magma_UInt_2_eq_inst0.in1","const_3_2.out"], ["magma_Bits_4_eq_inst0.in1","const_3_4.out"], - ["self.port_0","count.CE"], - ["self.port_1","count.CLK"], - ["magma_UInt_2_add_inst0.out","count.I"], - ["magma_UInt_2_add_inst0.in0","count.O"], - ["magma_UInt_2_eq_inst0.in0","count.O"], ["magma_UInt_2_eq_inst0.out","magma_Bit_not_inst0.in"], ["magma_Bit_or_inst0.in0","magma_Bit_not_inst0.out"], ["magma_Bits_4_eq_inst0.out","magma_Bit_or_inst0.in1"], diff --git a/tests/gold/test_compile_guard_drive_output.json b/tests/gold/test_compile_guard_drive_output.json index 726e0c088..bce3fec61 100644 --- a/tests/gold/test_compile_guard_drive_output.json +++ b/tests/gold/test_compile_guard_drive_output.json @@ -4,9 +4,9 @@ "modules":{ "CompileGuardCircuit_1":{ "type":["Record",[ - ["CLK",["Named","coreir.clkIn"]], ["port_0","Bit"], - ["port_1","BitIn"] + ["port_1",["Named","coreir.clkIn"]], + ["port_2","BitIn"] ]], "instances":{ "Register_inst0":{ @@ -21,11 +21,11 @@ } }, "connections":[ - ["self.CLK","Register_inst0.CLK"], + ["self.port_1","Register_inst0.CLK"], ["magma_Bit_xor_inst0.out","Register_inst0.I"], ["self.port_0","Register_inst0.O"], ["magma_Bit_xor_inst0.in1","bit_const_1_None.out"], - ["self.port_1","magma_Bit_xor_inst0.in0"] + ["self.port_2","magma_Bit_xor_inst0.in0"] ] }, "Register":{ @@ -60,9 +60,9 @@ } }, "connections":[ - ["self.CLK","CompileGuardCircuit_1.CLK"], ["self.O","CompileGuardCircuit_1.port_0"], - ["self.I","CompileGuardCircuit_1.port_1"] + ["self.CLK","CompileGuardCircuit_1.port_1"], + ["self.I","CompileGuardCircuit_1.port_2"] ] } } diff --git a/tests/gold/test_when_memory_Bits8.mlir b/tests/gold/test_when_memory_Bits8.mlir index 3d263e84b..4fa715ba6 100644 --- a/tests/gold/test_when_memory_Bits8.mlir +++ b/tests/gold/test_when_memory_Bits8.mlir @@ -13,7 +13,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } hw.module @test_when_memory_Bits8(%data0: i8, %addr0: i5, %en0: i1, %data1: i8, %addr1: i5, %en1: i1, %CLK: i1) -> (out: i8) { %0 = hw.constant 1 : i1 - %5 = hw.instance "mem" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA: %3: i8, WE: %4: i1) -> (RDATA: i8) + %5 = hw.instance "Memory_inst0" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA: %3: i8, WE: %4: i1) -> (RDATA: i8) %6 = hw.constant 255 : i8 %7 = hw.constant 0 : i5 %8 = hw.constant 0 : i8 diff --git a/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir b/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir index 1dceb7140..f4a09f84a 100644 --- a/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir +++ b/tests/gold/test_when_memory_Tuplex_Bit_y_Bits7.mlir @@ -30,7 +30,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } hw.module @test_when_memory_Tuplex_Bit_y_Bits7(%data0_x: i1, %data0_y: i7, %addr0: i5, %en0: i1, %data1_x: i1, %data1_y: i7, %addr1: i5, %en1: i1, %CLK: i1) -> (out_x: i1, out_y: i7) { %0 = hw.constant 1 : i1 - %6, %7 = hw.instance "mem" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA_x: %3: i1, WDATA_y: %4: i7, WE: %5: i1) -> (RDATA_x: i1, RDATA_y: i7) + %6, %7 = hw.instance "Memory_inst0" @Memory(RADDR: %1: i5, CLK: %CLK: i1, WADDR: %2: i5, WDATA_x: %3: i1, WDATA_y: %4: i7, WE: %5: i1) -> (RDATA_x: i1, RDATA_y: i7) %8 = hw.constant 127 : i7 %9 = hw.constant 0 : i5 %10 = hw.constant 0 : i1 diff --git a/tests/gold/test_when_non_port.mlir b/tests/gold/test_when_non_port.mlir index 7b126c6e2..9ceb6d9dc 100644 --- a/tests/gold/test_when_non_port.mlir +++ b/tests/gold/test_when_non_port.mlir @@ -11,9 +11,6 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %3, %1 : i1 } } - %5 = sv.wire sym @test_non_port.x {name="x"} : !hw.inout - sv.assign %5, %2 : i1 - %4 = sv.read_inout %5 : !hw.inout - hw.output %4 : i1 + hw.output %2 : i1 } } diff --git a/tests/gold/test_when_recursive_non_port.mlir b/tests/gold/test_when_recursive_non_port.mlir index ccbd6b058..f5e6cc8df 100644 --- a/tests/gold/test_when_recursive_non_port.mlir +++ b/tests/gold/test_when_recursive_non_port.mlir @@ -2,22 +2,19 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @test_recursive_non_port(%I: i2, %S: i1) -> (O0: i1, O1: i1) { %0 = comb.extract %I from 0 : (i2) -> i1 %1 = comb.extract %I from 1 : (i2) -> i1 + %4 = sv.reg : !hw.inout + %2 = sv.read_inout %4 : !hw.inout %5 = sv.reg : !hw.inout %3 = sv.read_inout %5 : !hw.inout - %6 = sv.reg : !hw.inout - %4 = sv.read_inout %6 : !hw.inout sv.alwayscomb { sv.if %S { - sv.bpassign %5, %0 : i1 - sv.bpassign %6, %2 : i1 + sv.bpassign %4, %0 : i1 + sv.bpassign %5, %2 : i1 } else { - sv.bpassign %5, %1 : i1 - sv.bpassign %6, %2 : i1 + sv.bpassign %4, %1 : i1 + sv.bpassign %5, %2 : i1 } } - %7 = sv.wire sym @test_recursive_non_port.x {name="x"} : !hw.inout - sv.assign %7, %3 : i1 - %2 = sv.read_inout %7 : !hw.inout - hw.output %2, %4 : i1, i1 + hw.output %2, %3 : i1, i1 } } diff --git a/tests/gold/test_when_reg_ce.mlir b/tests/gold/test_when_reg_ce.mlir index d247857f8..32cc3212a 100644 --- a/tests/gold/test_when_reg_ce.mlir +++ b/tests/gold/test_when_reg_ce.mlir @@ -14,7 +14,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %6, %0 : i1 } } - %7 = sv.reg {name = "x"} : !hw.inout + %7 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %4 { sv.passign %7, %3 : i8 diff --git a/tests/gold/test_when_reg_ce_already_wired.mlir b/tests/gold/test_when_reg_ce_already_wired.mlir index 1e1723cd6..398aa3054 100644 --- a/tests/gold/test_when_reg_ce_already_wired.mlir +++ b/tests/gold/test_when_reg_ce_already_wired.mlir @@ -8,7 +8,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i8 } } - %3 = sv.reg {name = "x"} : !hw.inout + %3 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %x { sv.passign %3, %1 : i8 diff --git a/tests/gold/test_when_reg_ce_explicit_wire.mlir b/tests/gold/test_when_reg_ce_explicit_wire.mlir index 1e104d48e..1736e9a3b 100644 --- a/tests/gold/test_when_reg_ce_explicit_wire.mlir +++ b/tests/gold/test_when_reg_ce_explicit_wire.mlir @@ -13,7 +13,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %5, %x : i1 } } - %6 = sv.reg {name = "x"} : !hw.inout + %6 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %3 { sv.passign %6, %2 : i8 diff --git a/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir b/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir index 291193684..ce52689b1 100644 --- a/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir +++ b/tests/gold/test_when_reg_ce_explicit_wire_twice.mlir @@ -20,7 +20,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } %8 = hw.constant -1 : i1 %7 = comb.xor %8, %y : i1 - %9 = sv.reg {name = "x"} : !hw.inout + %9 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %7 { sv.passign %9, %5 : i8 diff --git a/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir b/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir index 82761c5e3..78fcc92c2 100644 --- a/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir +++ b/tests/gold/test_when_reg_ce_explicit_wire_with_default.mlir @@ -13,7 +13,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %5, %x : i1 } } - %6 = sv.reg {name = "x"} : !hw.inout + %6 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %3 { sv.passign %6, %2 : i8 diff --git a/tests/gold/test_when_reg_ce_implicit_override.mlir b/tests/gold/test_when_reg_ce_implicit_override.mlir index c27f90871..417bf583d 100644 --- a/tests/gold/test_when_reg_ce_implicit_override.mlir +++ b/tests/gold/test_when_reg_ce_implicit_override.mlir @@ -11,7 +11,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %4, %I : i8 } } - %6 = sv.reg {name = "x"} : !hw.inout + %6 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %x { sv.passign %6, %2 : i8 diff --git a/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir b/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir index 2bf19a1a7..1b5863794 100644 --- a/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir +++ b/tests/gold/test_when_reg_ce_implicit_wire_twice.mlir @@ -29,7 +29,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %13, %9 : i1 } } - %14 = sv.reg {name = "x"} : !hw.inout + %14 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %11 { sv.passign %14, %10 : i8 diff --git a/tests/gold/test_when_reg_ce_multiple.mlir b/tests/gold/test_when_reg_ce_multiple.mlir index bbe9e3f80..4d956e703 100644 --- a/tests/gold/test_when_reg_ce_multiple.mlir +++ b/tests/gold/test_when_reg_ce_multiple.mlir @@ -23,7 +23,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } } } - %11 = sv.reg {name = "x"} : !hw.inout + %11 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %8 { sv.passign %11, %7 : i8 diff --git a/tests/gold/test_when_register_default.mlir b/tests/gold/test_when_register_default.mlir index 6d4cf419d..e0174761a 100644 --- a/tests/gold/test_when_register_default.mlir +++ b/tests/gold/test_when_register_default.mlir @@ -8,7 +8,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i1 } } - %3 = sv.reg {name = "reg"} : !hw.inout + %3 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %3, %1 : i1 } diff --git a/tests/gold/test_when_register_no_default.mlir b/tests/gold/test_when_register_no_default.mlir index f034b2dba..6418454b3 100644 --- a/tests/gold/test_when_register_no_default.mlir +++ b/tests/gold/test_when_register_no_default.mlir @@ -11,7 +11,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %3, %0 : i1 } } - %5 = sv.reg {name = "reg"} : !hw.inout + %5 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %5, %2 : i1 } diff --git a/tests/gold/test_when_spurious_assign.mlir b/tests/gold/test_when_spurious_assign.mlir index 5bd85186f..27b1b4a80 100644 --- a/tests/gold/test_when_spurious_assign.mlir +++ b/tests/gold/test_when_spurious_assign.mlir @@ -35,7 +35,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %15, %11 : i1 } } - %20 = sv.reg {name = "reg"} : !hw.inout + %20 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %0 { sv.passign %20, %x : i8 @@ -46,7 +46,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %20, %21 : i8 } %17 = sv.read_inout %20 : !hw.inout - %22 = sv.reg {name = "reg"} : !hw.inout + %22 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %0 { sv.passign %22, %6 : i8 @@ -57,7 +57,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %22, %23 : i8 } %18 = sv.read_inout %22 : !hw.inout - %24 = sv.reg {name = "reg"} : !hw.inout + %24 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.if %0 { sv.passign %24, %13 : i1 diff --git a/tests/gold/test_when_user_reg.mlir b/tests/gold/test_when_user_reg.mlir index b55833270..80544c0c4 100644 --- a/tests/gold/test_when_user_reg.mlir +++ b/tests/gold/test_when_user_reg.mlir @@ -9,7 +9,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %2, %I : i8 } } - %0 = hw.instance "x" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) + %0 = hw.instance "Register_inst0" @Register(I: %1: i8, CLK: %CLK: i1) -> (O: i8) hw.output %0 : i8 } } diff --git a/tests/gold/test_when_user_reg_enable.mlir b/tests/gold/test_when_user_reg_enable.mlir index 3d08213cc..7e3537e53 100644 --- a/tests/gold/test_when_user_reg_enable.mlir +++ b/tests/gold/test_when_user_reg_enable.mlir @@ -84,7 +84,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { } } %49 = comb.concat %38, %37, %36, %35, %34, %33, %32, %31 : i1, i1, i1, i1, i1, i1, i1, i1 - %21 = hw.instance "x" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) + %21 = hw.instance "Register_inst0" @Register(I: %49: i8, CE: %39: i1, CLK: %CLK: i1) -> (O: i8) hw.output %21 : i8 } } diff --git a/tests/gold/uniquification_key_error_mux.json b/tests/gold/uniquification_key_error_mux.json index 3379b5869..99cf534b1 100644 --- a/tests/gold/uniquification_key_error_mux.json +++ b/tests/gold/uniquification_key_error_mux.json @@ -10,16 +10,16 @@ ["O",["Array",6,"Bit"]] ]], "instances":{ - "mux":{ + "coreir_commonlib_mux2x6_inst0":{ "genref":"commonlib.muxn", "genargs":{"N":["Int",2], "width":["Int",6]} } }, "connections":[ - ["self.I0","mux.in.data.0"], - ["self.I1","mux.in.data.1"], - ["self.S","mux.in.sel.0"], - ["self.O","mux.out"] + ["self.I0","coreir_commonlib_mux2x6_inst0.in.data.0"], + ["self.I1","coreir_commonlib_mux2x6_inst0.in.data.1"], + ["self.S","coreir_commonlib_mux2x6_inst0.in.sel.0"], + ["self.O","coreir_commonlib_mux2x6_inst0.out"] ] }, "MuxWithDefaultWrapper_2_6_19_0":{ diff --git a/tests/gold/uniquify_equal.json b/tests/gold/uniquify_equal.json index 23d36ea43..125248f02 100644 --- a/tests/gold/uniquify_equal.json +++ b/tests/gold/uniquify_equal.json @@ -17,17 +17,17 @@ ["O","Bit"] ]], "instances":{ - "inst_0":{ + "foo_inst0":{ "modref":"global.foo" }, - "inst_1":{ + "foo_inst1":{ "modref":"global.foo" } }, "connections":[ - ["self.I","inst_0.I"], - ["inst_1.I","inst_0.O"], - ["self.O","inst_1.O"] + ["self.I","foo_inst0.I"], + ["foo_inst1.I","foo_inst0.O"], + ["self.O","foo_inst1.O"] ] } } diff --git a/tests/gold/uniquify_multiple_rename.json b/tests/gold/uniquify_multiple_rename.json index 96e152168..cae66fb58 100644 --- a/tests/gold/uniquify_multiple_rename.json +++ b/tests/gold/uniquify_multiple_rename.json @@ -30,23 +30,23 @@ ["O2",["Array",3,"Bit"]] ]], "instances":{ - "foo0":{ + "Foo_inst0":{ "modref":"global.Foo" }, - "foo1":{ + "Foo_inst1":{ "modref":"global.Foo_unq1" }, - "foo2":{ + "Foo_inst2":{ "modref":"global.Foo_unq1" } }, "connections":[ - ["self.I0","foo0.I"], - ["self.O0","foo0.O"], - ["self.I1","foo1.I"], - ["self.O1","foo1.O"], - ["self.I2","foo2.I"], - ["self.O2","foo2.O"] + ["self.I0","Foo_inst0.I"], + ["self.O0","Foo_inst0.O"], + ["self.I1","Foo_inst1.I"], + ["self.O1","Foo_inst1.O"], + ["self.I2","Foo_inst2.I"], + ["self.O2","Foo_inst2.O"] ] } } diff --git a/tests/gold/uniquify_unequal.json b/tests/gold/uniquify_unequal.json index 2c6aafe97..6211b15bf 100644 --- a/tests/gold/uniquify_unequal.json +++ b/tests/gold/uniquify_unequal.json @@ -26,18 +26,18 @@ ["O","Bit"] ]], "instances":{ - "bar_inst":{ - "modref":"global.foo_unq1" - }, - "foo_inst":{ + "foo_inst0":{ "modref":"global.foo" + }, + "foo_inst1":{ + "modref":"global.foo_unq1" } }, "connections":[ - ["foo_inst.O","bar_inst.I.0"], - ["foo_inst.O","bar_inst.I.1"], - ["self.O","bar_inst.O.0"], - ["self.I","foo_inst.I"] + ["self.I","foo_inst0.I"], + ["foo_inst1.I.0","foo_inst0.O"], + ["foo_inst1.I.1","foo_inst0.O"], + ["self.O","foo_inst1.O.0"] ] } } diff --git a/tests/test_backend/test_mlir/examples.py b/tests/test_backend/test_mlir/examples.py index a00455578..a03f4a6a0 100644 --- a/tests/test_backend/test_mlir/examples.py +++ b/tests/test_backend/test_mlir/examples.py @@ -442,7 +442,7 @@ class xmr_bind_asserts(m.Circuit): ProcessInlineVerilogPass(xmr_bind_asserts).run() -xmr_bind.bind(xmr_bind_asserts, xmr_bind.inst.inst.y) +xmr_bind.bind(xmr_bind_asserts, xmr_bind.inst.xmr_bind_grandchild_inst0.y) class simple_compile_guard(m.Circuit): diff --git a/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir b/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir index 3cbcd79f6..6174c86fd 100644 --- a/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir +++ b/tests/test_backend/test_mlir/golds/complex_mixed_direction_ports2.mlir @@ -3,7 +3,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %a_x : i8 } hw.module @complex_mixed_direction_ports2(%a_x: i8) -> (a_y: i8) { - %0 = hw.instance "simple" @simple_mixed_direction_ports(a_x: %a_x: i8) -> (a_y: i8) + %0 = hw.instance "simple_mixed_direction_ports_inst0" @simple_mixed_direction_ports(a_x: %a_x: i8) -> (a_y: i8) hw.output %0 : i8 } } diff --git a/tests/test_backend/test_mlir/golds/counter.mlir b/tests/test_backend/test_mlir/golds/counter.mlir index 8c430ad5b..0c5ad2480 100644 --- a/tests/test_backend/test_mlir/golds/counter.mlir +++ b/tests/test_backend/test_mlir/golds/counter.mlir @@ -2,7 +2,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.module @counter(%CLK: i1) -> (y: i16) { %0 = hw.constant 1 : i16 %2 = comb.add %1, %0 : i16 - %3 = sv.reg {name = "reg"} : !hw.inout + %3 = sv.reg {name = "Register_inst0"} : !hw.inout sv.alwaysff(posedge %CLK) { sv.passign %3, %2 : i16 } diff --git a/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir b/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir index 5a7ccf9f8..9b9aedb61 100644 --- a/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir +++ b/tests/test_backend/test_mlir/golds/simple_memory_wrapper.mlir @@ -12,7 +12,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %0 : i12 } hw.module @simple_memory_wrapper(%RADDR: i7, %CLK: i1, %WADDR: i7, %WDATA: i12, %WE: i1) -> (RDATA: i12) { - %0 = hw.instance "mem" @Memory(RADDR: %RADDR: i7, CLK: %CLK: i1, WADDR: %WADDR: i7, WDATA: %WDATA: i12, WE: %WE: i1) -> (RDATA: i12) + %0 = hw.instance "Memory_inst0" @Memory(RADDR: %RADDR: i7, CLK: %CLK: i1, WADDR: %WADDR: i7, WDATA: %WDATA: i12, WE: %WE: i1) -> (RDATA: i12) hw.output %0 : i12 } } diff --git a/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir b/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir index fc71bd207..3155b0c67 100644 --- a/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir +++ b/tests/test_backend/test_mlir/golds/simple_module_params_instance.mlir @@ -3,7 +3,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %I : i1 } hw.module @simple_module_params_instance(%I: i1) -> (O: i1) { - %0 = hw.instance "inst" @simple_module_params(I: %I: i1) -> (O: i1) + %0 = hw.instance "simple_module_params_inst0" @simple_module_params(I: %I: i1) -> (O: i1) hw.output %0 : i1 } } diff --git a/tests/test_backend/test_mlir/golds/simple_redefinition.mlir b/tests/test_backend/test_mlir/golds/simple_redefinition.mlir index 33497e348..ca49c5e7c 100644 --- a/tests/test_backend/test_mlir/golds/simple_redefinition.mlir +++ b/tests/test_backend/test_mlir/golds/simple_redefinition.mlir @@ -3,8 +3,8 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %a : i1 } hw.module @simple_redefinition(%a: i1) -> (y: i1) { - %0 = hw.instance "i0" @simple_redefinition_module(a: %a: i1) -> (y: i1) - %1 = hw.instance "i1" @simple_redefinition_module(a: %0: i1) -> (y: i1) + %0 = hw.instance "simple_redefinition_module_inst0" @simple_redefinition_module(a: %a: i1) -> (y: i1) + %1 = hw.instance "simple_redefinition_module_inst1" @simple_redefinition_module(a: %0: i1) -> (y: i1) hw.output %1 : i1 } } diff --git a/tests/test_backend/test_mlir/golds/xmr_bind.mlir b/tests/test_backend/test_mlir/golds/xmr_bind.mlir index 2e9b578de..a31b5ed1e 100644 --- a/tests/test_backend/test_mlir/golds/xmr_bind.mlir +++ b/tests/test_backend/test_mlir/golds/xmr_bind.mlir @@ -3,15 +3,15 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %a : i16 } hw.module @xmr_bind_child(%a: i16) -> (y: i16) { - %0 = hw.instance "inst" @xmr_bind_grandchild(a: %a: i16) -> (y: i16) + %0 = hw.instance "xmr_bind_grandchild_inst0" @xmr_bind_grandchild(a: %a: i16) -> (y: i16) hw.output %0 : i16 } hw.module @xmr_bind_asserts(%a: i16, %y: i16, %other: i16) -> () { sv.verbatim "assert property ({{0}} == 0);" (%other) : i16 } hw.module @xmr_bind(%a: i16) -> (y: i16) { - %0 = hw.instance "inst" @xmr_bind_child(a: %a: i16) -> (y: i16) - %1 = sv.xmr "inst", "inst", "y" : !hw.inout + %0 = hw.instance "xmr_bind_child_inst0" @xmr_bind_child(a: %a: i16) -> (y: i16) + %1 = sv.xmr "xmr_bind_child_inst0", "xmr_bind_grandchild_inst0", "y" : !hw.inout %2 = sv.read_inout %1 : !hw.inout hw.instance "xmr_bind_asserts_inst" sym @xmr_bind.xmr_bind_asserts_inst @xmr_bind_asserts(a: %a: i16, y: %0: i16, other: %2: i16) -> () {doNotPrint = 1} hw.output %0 : i16 diff --git a/tests/test_circuit/gold/test_add8cin.json b/tests/test_circuit/gold/test_add8cin.json index d4f324384..f8626cd7b 100644 --- a/tests/test_circuit/gold/test_add8cin.json +++ b/tests/test_circuit/gold/test_add8cin.json @@ -46,15 +46,15 @@ ["O",["Array",8,"Bit"]] ]], "instances":{ - "adder":{ + "Add8_cin_inst0":{ "modref":"global.Add8_cin" } }, "connections":[ - ["self.CIN","adder.CIN"], - ["self.I0","adder.I0"], - ["self.I1","adder.I1"], - ["self.O","adder.O"] + ["self.CIN","Add8_cin_inst0.CIN"], + ["self.I0","Add8_cin_inst0.I0"], + ["self.I1","Add8_cin_inst0.I1"], + ["self.O","Add8_cin_inst0.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json index 984717dab..48b134285 100644 --- a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json +++ b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).json @@ -16,19 +16,14 @@ ["O",["Array",2,"Bit"]] ]], "instances":{ - "and2":{ + "And2_inst0":{ "modref":"global.And2" - }, - "tmp":{ - "genref":"coreir.wire", - "genargs":{"width":["Int",2]} } }, "connections":[ - ["self.I0","and2.I0"], - ["self.I1","and2.I1"], - ["tmp.in","and2.O"], - ["tmp.out","self.O"] + ["self.I0","And2_inst0.I0"], + ["self.I1","And2_inst0.I1"], + ["self.O","And2_inst0.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v index 8465af807..058f17080 100644 --- a/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v +++ b/tests/test_circuit/gold/test_anon_value_Array((2, Bit)).v @@ -1,6 +1,6 @@ module main (input [1:0] I0, input [1:0] I1, output [1:0] O); -wire [1:0] and2_O; -And2 and2 (.I0(I0), .I1(I1), .O(and2_O)); -assign O = and2_O; +wire [1:0] And2_inst0_O; +And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_circuit/gold/test_anon_value_Bit.json b/tests/test_circuit/gold/test_anon_value_Bit.json index 44e36f2f5..1afbaed4d 100644 --- a/tests/test_circuit/gold/test_anon_value_Bit.json +++ b/tests/test_circuit/gold/test_anon_value_Bit.json @@ -16,18 +16,14 @@ ["O","Bit"] ]], "instances":{ - "and2":{ + "And2_inst0":{ "modref":"global.And2" - }, - "tmp":{ - "modref":"corebit.wire" } }, "connections":[ - ["self.I0","and2.I0"], - ["self.I1","and2.I1"], - ["tmp.in","and2.O"], - ["tmp.out","self.O"] + ["self.I0","And2_inst0.I0"], + ["self.I1","And2_inst0.I1"], + ["self.O","And2_inst0.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Bit.v b/tests/test_circuit/gold/test_anon_value_Bit.v index d7b3e2500..f0fc76a4f 100644 --- a/tests/test_circuit/gold/test_anon_value_Bit.v +++ b/tests/test_circuit/gold/test_anon_value_Bit.v @@ -1,6 +1,6 @@ module main (input I0, input I1, output O); -wire and2_O; -And2 and2 (.I0(I0), .I1(I1), .O(and2_O)); -assign O = and2_O; +wire And2_inst0_O; +And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_circuit/gold/test_anon_value_Bits(2).json b/tests/test_circuit/gold/test_anon_value_Bits(2).json index 984717dab..48b134285 100644 --- a/tests/test_circuit/gold/test_anon_value_Bits(2).json +++ b/tests/test_circuit/gold/test_anon_value_Bits(2).json @@ -16,19 +16,14 @@ ["O",["Array",2,"Bit"]] ]], "instances":{ - "and2":{ + "And2_inst0":{ "modref":"global.And2" - }, - "tmp":{ - "genref":"coreir.wire", - "genargs":{"width":["Int",2]} } }, "connections":[ - ["self.I0","and2.I0"], - ["self.I1","and2.I1"], - ["tmp.in","and2.O"], - ["tmp.out","self.O"] + ["self.I0","And2_inst0.I0"], + ["self.I1","And2_inst0.I1"], + ["self.O","And2_inst0.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Bits(2).v b/tests/test_circuit/gold/test_anon_value_Bits(2).v index 8465af807..058f17080 100644 --- a/tests/test_circuit/gold/test_anon_value_Bits(2).v +++ b/tests/test_circuit/gold/test_anon_value_Bits(2).v @@ -1,6 +1,6 @@ module main (input [1:0] I0, input [1:0] I1, output [1:0] O); -wire [1:0] and2_O; -And2 and2 (.I0(I0), .I1(I1), .O(and2_O)); -assign O = and2_O; +wire [1:0] And2_inst0_O; +And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json index ed95d6b6a..fe742125f 100644 --- a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json +++ b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json @@ -16,21 +16,14 @@ ["O",["Record",[["x","Bit"],["y","Bit"]]]] ]], "instances":{ - "and2":{ + "And2_inst0":{ "modref":"global.And2" - }, - "tmp":{ - "genref":"coreir.wire", - "genargs":{"width":["Int",2]} } }, "connections":[ - ["self.I0","and2.I0"], - ["self.I1","and2.I1"], - ["tmp.in.0","and2.O.x"], - ["tmp.in.1","and2.O.y"], - ["tmp.out.0","self.O.x"], - ["tmp.out.1","self.O.y"] + ["self.I0","And2_inst0.I0"], + ["self.I1","And2_inst0.I1"], + ["self.O","And2_inst0.O"] ] } } diff --git a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v index ebc227109..f18f6c484 100644 --- a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v +++ b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).v @@ -1,12 +1,12 @@ module main (input I0_x, input I0_y, input I1_x, input I1_y, output O_x, output O_y); -wire and2_I0_x; -wire and2_I0_y; -wire and2_I1_x; -wire and2_I1_y; -wire and2_O_x; -wire and2_O_y; -And2 and2 (.I0_x(I0_x), .I0_y(I0_y), .I1_x(I1_x), .I1_y(I1_y), .O_x(and2_O_x), .O_y(and2_O_y)); -assign O_x = and2_O_x; -assign O_y = and2_O_y; +wire And2_inst0_I0_x; +wire And2_inst0_I0_y; +wire And2_inst0_I1_x; +wire And2_inst0_I1_y; +wire And2_inst0_O_x; +wire And2_inst0_O_y; +And2 And2_inst0 (.I0_x(I0_x), .I0_y(I0_y), .I1_x(I1_x), .I1_y(I1_y), .O_x(And2_inst0_O_x), .O_y(And2_inst0_O_y)); +assign O_x = And2_inst0_O_x; +assign O_y = And2_inst0_O_y; endmodule diff --git a/tests/test_circuit/gold/test_ignore_undriven_coreir.json b/tests/test_circuit/gold/test_ignore_undriven_coreir.json index a8557a5b9..ec762b740 100644 --- a/tests/test_circuit/gold/test_ignore_undriven_coreir.json +++ b/tests/test_circuit/gold/test_ignore_undriven_coreir.json @@ -37,26 +37,26 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ + "Foo_inst0":{ + "modref":"global.Foo" + }, "corebit_term_inst0":{ "modref":"corebit.term" }, "corebit_undriven_inst0":{ "modref":"corebit.undriven" }, - "foo":{ - "modref":"global.Foo" - }, "magma_Bits_2_eq_inst0":{ "genref":"coreir.eq", "genargs":{"width":["Int",2]} } }, "connections":[ - ["foo.O1","corebit_term_inst0.in"], + ["self.CLK","Foo_inst0.CLK"], + ["magma_Bits_2_eq_inst0.out","Foo_inst0.I0"], + ["self.O0","Foo_inst0.O0"], + ["corebit_term_inst0.in","Foo_inst0.O1"], ["self.O1","corebit_undriven_inst0.out"], - ["self.CLK","foo.CLK"], - ["magma_Bits_2_eq_inst0.out","foo.I0"], - ["self.O0","foo.O0"], ["self.I0","magma_Bits_2_eq_inst0.in0"], ["self.I1","magma_Bits_2_eq_inst0.in1"] ] diff --git a/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v b/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v index a9107ec0a..226f50ed9 100644 --- a/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v +++ b/tests/test_circuit/gold/test_ignore_unused_undriven_hierarchy.v @@ -35,14 +35,20 @@ module Main ( output O2__1, output [1:0] O3 ); +wire Foo_inst0_O1; wire corebit_undriven_inst2_out; wire corebit_undriven_inst3_out; -wire foo_O1; +Foo Foo_inst0 ( + .I0(I0), + .I1(corebit_undriven_inst3_out), + .O0(O0), + .O1(Foo_inst0_O1) +); corebit_term corebit_term_inst0 ( .in(I1) ); corebit_term corebit_term_inst1 ( - .in(foo_O1) + .in(Foo_inst0_O1) ); corebit_undriven corebit_undriven_inst0 ( .out(O1) @@ -56,12 +62,6 @@ corebit_undriven corebit_undriven_inst2 ( corebit_undriven corebit_undriven_inst3 ( .out(corebit_undriven_inst3_out) ); -Foo foo ( - .I0(I0), - .I1(corebit_undriven_inst3_out), - .O0(O0), - .O1(foo_O1) -); assign O2__0 = 1'b1; assign O3 = {corebit_undriven_inst2_out,1'b1}; endmodule diff --git a/tests/test_circuit/gold/test_unwired_output.v b/tests/test_circuit/gold/test_unwired_output.v index 51961ec48..510420101 100644 --- a/tests/test_circuit/gold/test_unwired_output.v +++ b/tests/test_circuit/gold/test_unwired_output.v @@ -1,5 +1,5 @@ module main (input [1:0] I, output O); -wire and2_O; -And2 and2 (.I1(I[1]), .O(and2_O)); +wire And2_inst0_O; +And2 And2_inst0 (.I1(I[1]), .O(And2_inst0_O)); endmodule diff --git a/tests/test_circuit/test_define.py b/tests/test_circuit/test_define.py index 52ab36395..3af6e1c0c 100644 --- a/tests/test_circuit/test_define.py +++ b/tests/test_circuit/test_define.py @@ -121,7 +121,7 @@ class main(m.Circuit): m.compile("build/test_unwired_output", main, "verilog") assert check_files_equal(__file__, f"build/test_unwired_output.v", f"gold/test_unwired_output.v") - assert caplog.records[-2].msg == "main.and2.I0 not connected" + assert caplog.records[-2].msg == "main.And2_inst0.I0 not connected" assert caplog.records[-1].msg == "main.O is unwired" diff --git a/tests/test_circuit/test_inspect.py b/tests/test_circuit/test_inspect.py index d44110e62..6b6bc0aeb 100644 --- a/tests/test_circuit/test_inspect.py +++ b/tests/test_circuit/test_inspect.py @@ -62,6 +62,6 @@ class circ(m.Circuit): m.wire(io.O, anon.O) string = str(circ.anon) - assert string[:len("anon")] == "anon" + assert string[:len("AnonymousCircuitInst")] == "AnonymousCircuitInst" assert string[-len(""):] == "" - assert repr(circ.anon) == 'anon = AnonymousCircuitType("I0", array([And2_inst0.I0, And2_inst1.I0, And2_inst2.I0]), "I1", array([And2_inst0.I1, And2_inst1.I1, And2_inst2.I1]), "O", array([And2_inst0.O, And2_inst1.O, And2_inst2.O]))' + assert repr(circ.anon) == 'AnonymousCircuitType("I0", array([And2_inst0.I0, And2_inst1.I0, And2_inst2.I0]), "I1", array([And2_inst0.I1, And2_inst1.I1, And2_inst2.I1]), "O", array([And2_inst0.O, And2_inst1.O, And2_inst2.O]))' diff --git a/tests/test_circuit/test_new_style_syntax.py b/tests/test_circuit/test_new_style_syntax.py index 8b5c51be2..a365e1b48 100644 --- a/tests/test_circuit/test_new_style_syntax.py +++ b/tests/test_circuit/test_new_style_syntax.py @@ -125,14 +125,14 @@ class _Foo(m.Circuit): assert has_error( caplog, - "Cannot wire _Foo.I (Out(Bit)) to _Foo.bar.I (In(Bits[1]))") + "Cannot wire _Foo.I (Out(Bit)) to _Foo._Bar_inst0.I (In(Bits[1]))") assert has_error( caplog, - "Cannot wire _Foo.bar.O (Out(Bits[1])) to _Foo.O (In(Bit))") + "Cannot wire _Foo._Bar_inst0.O (Out(Bits[1])) to _Foo.O (In(Bit))") assert has_error(caplog, "_Foo.O not driven") assert has_error(caplog, "_Foo.O: Unconnected") - assert has_error(caplog, "_Foo.bar.I not driven") - assert has_error(caplog, "_Foo.bar.I: Unconnected") + assert has_error(caplog, "_Foo._Bar_inst0.I not driven") + assert has_error(caplog, "_Foo._Bar_inst0.I: Unconnected") def test_nested_definition(): @@ -149,9 +149,9 @@ class _Bar(m.Circuit): m.wire(bar.O, io.O) assert repr(_Foo) == """_Foo = DefineCircuit("_Foo", "I", In(Bit), "O", Out(Bit)) -bar = _Bar() -wire(_Foo.I, bar.I) -wire(bar.O, _Foo.O) +_Bar_inst0 = _Bar() +wire(_Foo.I, _Bar_inst0.I) +wire(_Bar_inst0.O, _Foo.O) EndCircuit()""" assert repr(_Foo._Bar) == """_Bar = DefineCircuit("_Bar", "I", In(Bit), "O", Out(Bit)) wire(_Bar.I, _Bar.O) diff --git a/tests/test_circuit/test_reg_enable_call.py b/tests/test_circuit/test_reg_enable_call.py index eeee955fe..261c1a8d1 100644 --- a/tests/test_circuit/test_reg_enable_call.py +++ b/tests/test_circuit/test_reg_enable_call.py @@ -13,12 +13,12 @@ class test_reg_enable_call(m.Circuit): assert repr(test_reg_enable_call) == """\ test_reg_enable_call = DefineCircuit("test_reg_enable_call", "I", In(Bits[5]), \ "O", Out(Bits[5]), "nen", In(Bit), "CLK", In(Clock)) +Register_inst0 = Register() magma_Bit_not_inst0 = magma_Bit_not() -reg = Register() +wire(test_reg_enable_call.I, Register_inst0.I) +wire(magma_Bit_not_inst0.out, Register_inst0.en) wire(test_reg_enable_call.nen, magma_Bit_not_inst0.in) -wire(test_reg_enable_call.I, reg.I) -wire(magma_Bit_not_inst0.out, reg.en) -wire(reg.O, test_reg_enable_call.O) +wire(Register_inst0.O, test_reg_enable_call.O) EndCircuit()\ """ m.compile("build/test_reg_enable_call", test_reg_enable_call) diff --git a/tests/test_compile/gold/test_header_footer.v b/tests/test_compile/gold/test_header_footer.v index a43723204..7f117b8cc 100644 --- a/tests/test_compile/gold/test_header_footer.v +++ b/tests/test_compile/gold/test_header_footer.v @@ -9,12 +9,12 @@ module Main ( input I, output O ); -wire foo_y; -Foo foo ( +wire Foo_inst0_y; +Foo Foo_inst0 ( .x(I), - .y(foo_y) + .y(Foo_inst0_y) ); -assign O = foo_y; +assign O = Foo_inst0_y; endmodule diff --git a/tests/test_coreir/gold/linker_test0.json b/tests/test_coreir/gold/linker_test0.json index 07e9899f7..aa3946362 100644 --- a/tests/test_coreir/gold/linker_test0.json +++ b/tests/test_coreir/gold/linker_test0.json @@ -9,15 +9,15 @@ ["O",["Array",16,"Bit"]] ]], "instances":{ - "smax":{ + "commonlib_smax_width_16_inst0":{ "genref":"commonlib.smax", "genargs":{"width":["Int",16]} } }, "connections":[ - ["smax.in0","self.I0"], - ["smax.in1","self.I1"], - ["smax.out","self.O"] + ["self.I0","commonlib_smax_width_16_inst0.in0"], + ["self.I1","commonlib_smax_width_16_inst0.in1"], + ["self.O","commonlib_smax_width_16_inst0.out"] ] }, "commonlib_smax_width_16":{ diff --git a/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v b/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v index 14c11b649..c0d080b5c 100644 --- a/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v +++ b/tests/test_coreir/gold/test_auto_wire_tuple_clocks.v @@ -5,13 +5,13 @@ module Main ( input clocks_clk, input clocks_rst ); -wire foo_O; -Foo foo ( +wire Foo_inst0_O; +Foo Foo_inst0 ( .I(I), - .O(foo_O), + .O(Foo_inst0_O), .clocks_clk(clocks_clk), .clocks_rst(clocks_rst) ); -assign O = foo_O; +assign O = Foo_inst0_O; endmodule diff --git a/tests/test_coreir/gold/test_multi_direction_tuple_instance.json b/tests/test_coreir/gold/test_multi_direction_tuple_instance.json index 377a53288..d01098506 100644 --- a/tests/test_coreir/gold/test_multi_direction_tuple_instance.json +++ b/tests/test_coreir/gold/test_multi_direction_tuple_instance.json @@ -15,13 +15,13 @@ ["ifc",["Record",[["I","BitIn"],["O","Bit"]]]] ]], "instances":{ - "foo_inst":{ + "Foo_inst0":{ "modref":"global.Foo" } }, "connections":[ - ["self.ifc.I","foo_inst.ifc.I"], - ["self.ifc.O","foo_inst.ifc.O"] + ["self.ifc.I","Foo_inst0.ifc.I"], + ["self.ifc.O","Foo_inst0.ifc.O"] ] } } diff --git a/tests/test_coreir/gold/test_nesting.json b/tests/test_coreir/gold/test_nesting.json index 5edf0b032..135697c48 100644 --- a/tests/test_coreir/gold/test_nesting.json +++ b/tests/test_coreir/gold/test_nesting.json @@ -15,23 +15,23 @@ ["I",["Record",[["x",["Record",[["a","BitIn"],["b","BitIn"]]]],["y",["Record",[["a","Bit"],["b","Bit"]]]],["z",["Record",[["a","BitIn"],["b","Bit"]]]]]]] ]], "instances":{ - "foo_inst0":{ + "Foo_inst0":{ "modref":"global.Foo" }, - "foo_inst1":{ + "Foo_inst1":{ "modref":"global.Foo" }, - "foo_inst2":{ + "Foo_inst2":{ "modref":"global.Foo" } }, "connections":[ - ["self.I.x.a","foo_inst0.ifc.I"], - ["self.I.y.a","foo_inst0.ifc.O"], - ["self.I.x.b","foo_inst1.ifc.I"], - ["self.I.y.b","foo_inst1.ifc.O"], - ["self.I.z.a","foo_inst2.ifc.I"], - ["self.I.z.b","foo_inst2.ifc.O"] + ["self.I.x.a","Foo_inst0.ifc.I"], + ["self.I.y.a","Foo_inst0.ifc.O"], + ["self.I.x.b","Foo_inst1.ifc.I"], + ["self.I.y.b","Foo_inst1.ifc.O"], + ["self.I.z.a","Foo_inst2.ifc.I"], + ["self.I.z.b","Foo_inst2.ifc.O"] ] } } diff --git a/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v b/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v index 35ea3d1cc..54a3a5eb6 100644 --- a/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v +++ b/tests/test_deprecated/test_old_io_syntax/gold/test_ignore_unused_undriven_hierarchy.v @@ -31,13 +31,19 @@ module Main ( output O0, output O1 ); +wire Foo_inst0_O1; wire corebit_undriven_inst1_out; -wire foo_O1; +Foo Foo_inst0 ( + .I0(I0), + .I1(corebit_undriven_inst1_out), + .O0(O0), + .O1(Foo_inst0_O1) +); corebit_term corebit_term_inst0 ( .in(I1) ); corebit_term corebit_term_inst1 ( - .in(foo_O1) + .in(Foo_inst0_O1) ); corebit_undriven corebit_undriven_inst0 ( .out(O1) @@ -45,11 +51,5 @@ corebit_undriven corebit_undriven_inst0 ( corebit_undriven corebit_undriven_inst1 ( .out(corebit_undriven_inst1_out) ); -Foo foo ( - .I0(I0), - .I1(corebit_undriven_inst1_out), - .O0(O0), - .O1(foo_O1) -); endmodule diff --git a/tests/test_errors/test_tuple_errors.py b/tests/test_errors/test_tuple_errors.py index c8d14cfcb..2b869f1b1 100644 --- a/tests/test_errors/test_tuple_errors.py +++ b/tests/test_errors/test_tuple_errors.py @@ -188,5 +188,5 @@ class Bar(m.Circuit): assert caplog.messages[0] == "Bar.z.x not driven" assert caplog.messages[1] == "Bar.z.x: Unconnected" - assert caplog.messages[2] == "foo.z.y not driven" - assert caplog.messages[3] == "foo.z.y: Unconnected" + assert caplog.messages[2] == "Foo_inst0.z.y not driven" + assert caplog.messages[3] == "Foo_inst0.z.y: Unconnected" diff --git a/tests/test_higher/test_braid.py b/tests/test_higher/test_braid.py index 7f43a7ed4..fb0adb3de 100644 --- a/tests/test_higher/test_braid.py +++ b/tests/test_higher/test_braid.py @@ -11,13 +11,13 @@ class _Top(Circuit): lut1 = And2(name='lut1') lut = braid([lut0,lut1]) - assert repr(lut) == 'lut = AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", array([lut0.I1, lut1.I1]), "O", array([lut0.O, lut1.O]))' + assert repr(lut) == 'AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", array([lut0.I1, lut1.I1]), "O", array([lut0.O, lut1.O]))' lut = braid([lut0,lut1], foldargs={'I1':'O'}) - assert repr(lut) == 'lut_1 = AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", lut1.O)' + assert repr(lut) == 'AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", lut1.O)' lut = braid([lut0,lut1], scanargs={'I1':'O'}) - assert repr(lut) == 'lut_2 = AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", array([lut0.O, lut1.O]))' + assert repr(lut) == 'AnonymousCircuitType("I0", array([lut0.I0, lut1.I0]), "I1", lut0.I1, "O", array([lut0.O, lut1.O]))' def test_compose(): @@ -37,6 +37,6 @@ class _Top(Circuit): assert repr(lut1) == 'lut1 = Buf(name="lut1")' assert repr(lut2) == 'lut2 = Buf(name="lut2")' - assert repr(lut3) == 'lut3 = AnonymousCircuitType("I", lut2.I, "O", lut1.O)' + assert repr(lut3) == 'AnonymousCircuitType("I", lut2.I, "O", lut1.O)' diff --git a/tests/test_higher/test_curry.py b/tests/test_higher/test_curry.py index e3199f7d6..91d2fc078 100644 --- a/tests/test_higher/test_curry.py +++ b/tests/test_higher/test_curry.py @@ -16,8 +16,8 @@ class _Top(Circuit): lut3 = _Top.lut3 assert repr(lut1) == 'lut1 = LUT2(name="lut1")' - assert repr(lut2) == 'lut2 = AnonymousCircuitType("I", array([lut1.I0, lut1.I1]), "O", lut1.O)' - assert repr(lut3) == 'lut3 = AnonymousCircuitType("I0", lut1.I0, "I1", lut1.I1, "O", lut1.O)' + assert repr(lut2) == 'AnonymousCircuitType("I", array([lut1.I0, lut1.I1]), "O", lut1.O)' + assert repr(lut3) == 'AnonymousCircuitType("I0", lut1.I0, "I1", lut1.I1, "O", lut1.O)' def test_rom(): class ROM2(Circuit): @@ -35,7 +35,7 @@ class _Top(Circuit): rom3 = _Top.rom3 assert repr(rom1) == 'rom1 = ROM2(name="rom1")' - assert repr(rom2) == 'rom2 = AnonymousCircuitType("I0", rom1.I[0], "I1", rom1.I[1], "O", rom1.O)' - assert repr(rom3) == 'rom3 = AnonymousCircuitType("I", array([rom1.I[0], rom1.I[1]]), "O", rom1.O)' + assert repr(rom2) == 'AnonymousCircuitType("I0", rom1.I[0], "I1", rom1.I[1], "O", rom1.O)' + assert repr(rom3) == 'AnonymousCircuitType("I", array([rom1.I[0], rom1.I[1]]), "O", rom1.O)' diff --git a/tests/test_higher/test_join.py b/tests/test_higher/test_join.py index 1dbfe6ab0..8d1ff9cdf 100644 --- a/tests/test_higher/test_join.py +++ b/tests/test_higher/test_join.py @@ -10,4 +10,4 @@ class _Top(m.Circuit): and1 = And2(name='and1') a = m.join(and0, and1) - assert repr(_Top.a) == 'a = AnonymousCircuitType("I0", array([and0.I0, and1.I0]), "I1", array([and0.I1, and1.I1]), "O", array([and0.O, and1.O]))' + assert repr(_Top.a) == 'AnonymousCircuitType("I0", array([and0.I0, and1.I0]), "I1", array([and0.I1, and1.I1]), "O", array([and0.O, and1.O]))' diff --git a/tests/test_ir/gold/declaretest.v b/tests/test_ir/gold/declaretest.v index 2534dfb8a..f0fc76a4f 100644 --- a/tests/test_ir/gold/declaretest.v +++ b/tests/test_ir/gold/declaretest.v @@ -1,6 +1,6 @@ module main (input I0, input I1, output O); -wire inst0_O; -And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O)); -assign O = inst0_O; +wire And2_inst0_O; +And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_ir/test_ir.py b/tests/test_ir/test_ir.py index 7afd00c47..16f54ef32 100644 --- a/tests/test_ir/test_ir.py +++ b/tests/test_ir/test_ir.py @@ -26,15 +26,15 @@ class main(Circuit): #print(result) assert result == """\ AndN2 = DefineCircuit("AndN2", "I", Array[(2, In(Bit))], "O", Out(Bit)) -and2 = And2() -wire(AndN2.I[0], and2.I0) -wire(AndN2.I[1], and2.I1) -wire(and2.O, AndN2.O) +And2_inst0 = And2() +wire(AndN2.I[0], And2_inst0.I0) +wire(AndN2.I[1], And2_inst0.I1) +wire(And2_inst0.O, AndN2.O) EndCircuit() main = DefineCircuit("main", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) -and2 = AndN2() -wire(main.I0, and2.I[0]) -wire(main.I1, and2.I[1]) -wire(and2.O, main.O) +AndN2_inst0 = AndN2() +wire(main.I0, AndN2_inst0.I[0]) +wire(main.I1, AndN2_inst0.I[1]) +wire(AndN2_inst0.O, main.O) EndCircuit() """ diff --git a/tests/test_ir_pass.py b/tests/test_ir_pass.py index e2711df5f..a28c1f795 100644 --- a/tests/test_ir_pass.py +++ b/tests/test_ir_pass.py @@ -1,4 +1,3 @@ -from magma.config import config from magma.passes import IRPass from magma import Bit, Circuit, IO, In, Out, wire @@ -28,17 +27,17 @@ def test_basic(): EndCircuit() _Top = DefineCircuit("_Top", "I", In(Bit), "O", Out(Bit)) -cell_0 = _Cell() -cell_1 = _Cell() -cell_2 = _Cell() -cell_3 = _Cell() -cell_4 = _Cell() -wire(_Top.I, cell_0.I) -wire(cell_0.O, cell_1.I) -wire(cell_1.O, cell_2.I) -wire(cell_2.O, cell_3.I) -wire(cell_3.O, cell_4.I) -wire(cell_4.O, _Top.O) +_Cell_inst0 = _Cell() +_Cell_inst1 = _Cell() +_Cell_inst2 = _Cell() +_Cell_inst3 = _Cell() +_Cell_inst4 = _Cell() +wire(_Top.I, _Cell_inst0.I) +wire(_Cell_inst0.O, _Cell_inst1.I) +wire(_Cell_inst1.O, _Cell_inst2.I) +wire(_Cell_inst2.O, _Cell_inst3.I) +wire(_Cell_inst3.O, _Cell_inst4.I) +wire(_Cell_inst4.O, _Top.O) EndCircuit() """ diff --git a/tests/test_meta/gold/creg.v b/tests/test_meta/gold/creg.v index b027aaf5a..2b0c803e1 100644 --- a/tests/test_meta/gold/creg.v +++ b/tests/test_meta/gold/creg.v @@ -7,8 +7,8 @@ assign O = {DFF_inst1_O,DFF_inst0_O}; endmodule module main (input CLK, input [1:0] I, output [1:0] O); -wire [1:0] reg_O; -Register2 reg (.I(I), .O(reg_O), .CLK(CLK)); -assign O = reg_O; +wire [1:0] Register2_inst0_O; +Register2 Register2_inst0 (.I(I), .O(Register2_inst0_O), .CLK(CLK)); +assign O = Register2_inst0_O; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v b/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v index 0d47e23a2..e8f80c4b3 100644 --- a/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v +++ b/tests/test_passes/gold/insert_coreir_wires_arr_tuple_TuplexInBityOutBit.v @@ -5,17 +5,17 @@ module Main ( input z_1_x, output z_1_y ); +wire Foo_inst0_z_0_y; wire a_x; wire a_y; -wire foo_z_0_y; -assign a_x = foo_z_0_y; -assign a_y = z_0_x; -Foo foo ( +Foo Foo_inst0 ( .z_0_x(a_y), - .z_0_y(foo_z_0_y), + .z_0_y(Foo_inst0_z_0_y), .z_1_x(z_0_x), .z_1_y(z_1_y) ); +assign a_x = Foo_inst0_z_0_y; +assign a_y = z_0_x; assign z_0_y = a_x; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v b/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v index 4b06bac37..17ee499f1 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_Array5Bits5.v @@ -3,19 +3,19 @@ module Main ( input [4:0] I [4:0], output [4:0] O [4:0] ); -wire [4:0] foo_O [4:0]; +wire [4:0] Foo_inst0_O [4:0]; wire [24:0] x; -wire [4:0] foo_I [4:0]; -assign foo_I[4] = I[4]; -assign foo_I[3] = I[3]; -assign foo_I[2] = I[2]; -assign foo_I[1] = I[1]; -assign foo_I[0] = I[0]; -Foo foo ( - .I(foo_I), - .O(foo_O) +wire [4:0] Foo_inst0_I [4:0]; +assign Foo_inst0_I[4] = I[4]; +assign Foo_inst0_I[3] = I[3]; +assign Foo_inst0_I[2] = I[2]; +assign Foo_inst0_I[1] = I[1]; +assign Foo_inst0_I[0] = I[0]; +Foo Foo_inst0 ( + .I(Foo_inst0_I), + .O(Foo_inst0_O) ); -assign x = {foo_O[4],foo_O[3],foo_O[2],foo_O[1],foo_O[0]}; +assign x = {Foo_inst0_O[4],Foo_inst0_O[3],Foo_inst0_O[2],Foo_inst0_O[1],Foo_inst0_O[0]}; assign O[4] = {x[24],x[23],x[22],x[21],x[20]}; assign O[3] = {x[19],x[18],x[17],x[16],x[15]}; assign O[2] = {x[14],x[13],x[12],x[11],x[10]}; diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v b/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v index 7474efa07..924b0e9f6 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_Bit.v @@ -3,13 +3,13 @@ module Main ( input I, output O ); -wire foo_O; +wire Foo_inst0_O; wire x; -Foo foo ( +Foo Foo_inst0 ( .I(I), - .O(foo_O) + .O(Foo_inst0_O) ); -assign x = foo_O; +assign x = Foo_inst0_O; assign O = x; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v b/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v index ea155721d..d7d5a5b1c 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_Bits5.v @@ -3,13 +3,13 @@ module Main ( input [4:0] I, output [4:0] O ); -wire [4:0] foo_O; +wire [4:0] Foo_inst0_O; wire [4:0] x; -Foo foo ( +Foo Foo_inst0 ( .I(I), - .O(foo_O) + .O(Foo_inst0_O) ); -assign x = foo_O; +assign x = Foo_inst0_O; assign O = x; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v b/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v index 13dfba1f2..f90b70a5b 100644 --- a/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v +++ b/tests/test_passes/gold/insert_coreir_wires_instance_TupleBits5Bit.v @@ -5,16 +5,16 @@ module Main ( output [4:0] O__0, output O__1 ); -wire [4:0] foo_O__0; -wire foo_O__1; +wire [4:0] Foo_inst0_O__0; +wire Foo_inst0_O__1; wire [5:0] x; -Foo foo ( +Foo Foo_inst0 ( .I__0(I__0), .I__1(I__1), - .O__0(foo_O__0), - .O__1(foo_O__1) + .O__0(Foo_inst0_O__0), + .O__1(Foo_inst0_O__1) ); -assign x = {foo_O__1,foo_O__0}; +assign x = {Foo_inst0_O__1,Foo_inst0_O__0}; assign O__0 = {x[4],x[3],x[2],x[1],x[0]}; assign O__1 = x[5]; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v b/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v index fa6ac905b..c93a32a7e 100644 --- a/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v +++ b/tests/test_passes/gold/insert_coreir_wires_temp_array_not_whole_anon.v @@ -3,15 +3,11 @@ module Main ( output [1:0] O0, output [1:0] O1 ); -wire [1:0] x_0; -wire [1:0] x_1; wire y; wire z; -assign x_0 = {z,y}; -assign x_1 = {y,z}; assign y = I[1]; assign z = I[0]; -assign O0 = {x_1[0],x_0[0]}; -assign O1 = {x_0[1],x_1[1]}; +assign O0 = {z,y}; +assign O1 = {z,y}; endmodule diff --git a/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v b/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v index 84b8c5b1a..769644c3b 100644 --- a/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v +++ b/tests/test_passes/gold/insert_coreir_wires_tuple_TuplexInBityOutBit.v @@ -3,15 +3,15 @@ module Main ( input z_x, output z_y ); +wire Foo_inst0_z_y; wire a_x; wire a_y; -wire foo_z_y; -assign a_x = foo_z_y; -assign a_y = z_x; -Foo foo ( +Foo Foo_inst0 ( .z_x(a_y), - .z_y(foo_z_y) + .z_y(Foo_inst0_z_y) ); +assign a_x = Foo_inst0_z_y; +assign a_y = z_x; assign z_y = a_x; endmodule diff --git a/tests/test_primitives/gold/test_memory_arr.v b/tests/test_primitives/gold/test_memory_arr.v index 26604c101..59bad0e8f 100644 --- a/tests/test_primitives/gold/test_memory_arr.v +++ b/tests/test_primitives/gold/test_memory_arr.v @@ -90,7 +90,7 @@ module test_memory_arr ( input [4:0] wdata_1_Y, input wen ); -Memory Mem4xT ( +Memory Memory_inst0 ( .CLK(clk), .RADDR(raddr), .RDATA_0_X(rdata_0_X), diff --git a/tests/test_primitives/gold/test_memory_basic.mlir b/tests/test_primitives/gold/test_memory_basic.mlir index a5e5b9ce2..a149d8c6f 100644 --- a/tests/test_primitives/gold/test_memory_basic.mlir +++ b/tests/test_primitives/gold/test_memory_basic.mlir @@ -32,7 +32,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { sv.bpassign %9, %0 : i1 } } - %10 = hw.instance "Mem4x5" @Memory(RADDR: %raddr: i2, CLK: %clk: i1, WADDR: %4: i2, WDATA: %5: i5, WE: %6: i1) -> (RDATA: i5) + %10 = hw.instance "Memory_inst0" @Memory(RADDR: %raddr: i2, CLK: %clk: i1, WADDR: %4: i2, WDATA: %5: i5, WE: %6: i1) -> (RDATA: i5) hw.output %10 : i5 } } diff --git a/tests/test_primitives/gold/test_memory_product.v b/tests/test_primitives/gold/test_memory_product.v index 3a3f3dc20..b2e75f196 100644 --- a/tests/test_primitives/gold/test_memory_product.v +++ b/tests/test_primitives/gold/test_memory_product.v @@ -80,7 +80,7 @@ module test_memory_product ( input [4:0] wdata_Y, input wen ); -Memory Mem4xT ( +Memory Memory_inst0 ( .CLK(clk), .RADDR(raddr), .RDATA_X(rdata_X), diff --git a/tests/test_primitives/gold/test_memory_product_init.v b/tests/test_primitives/gold/test_memory_product_init.v index 5bad4a38e..0b38a0055 100644 --- a/tests/test_primitives/gold/test_memory_product_init.v +++ b/tests/test_primitives/gold/test_memory_product_init.v @@ -71,7 +71,7 @@ module test_memory_product_init ( output [7:0] rdata_X, output [7:0] rdata_Y ); -Memory Mem4xT ( +Memory Memory_inst0 ( .CLK(clk), .RADDR(raddr), .RDATA_X(rdata_X), diff --git a/tests/test_primitives/gold/test_memory_read_latency_False.v b/tests/test_primitives/gold/test_memory_read_latency_False.v index 59c76ca83..7b066466c 100644 --- a/tests/test_primitives/gold/test_memory_read_latency_False.v +++ b/tests/test_primitives/gold/test_memory_read_latency_False.v @@ -179,15 +179,15 @@ module test_memory_read_latency_False ( input clk, input wen ); -wire [4:0] Mem4x5_RDATA; -Memory Mem4x5 ( +wire [4:0] Memory_inst0_RDATA; +Memory Memory_inst0 ( .RADDR(raddr), - .RDATA(Mem4x5_RDATA), + .RDATA(Memory_inst0_RDATA), .CLK(clk), .WADDR(waddr), .WDATA(wdata), .WE(wen) ); -assign rdata = Mem4x5_RDATA; +assign rdata = Memory_inst0_RDATA; endmodule diff --git a/tests/test_primitives/gold/test_memory_read_latency_True.v b/tests/test_primitives/gold/test_memory_read_latency_True.v index e61ce1bbf..3b91cd527 100644 --- a/tests/test_primitives/gold/test_memory_read_latency_True.v +++ b/tests/test_primitives/gold/test_memory_read_latency_True.v @@ -167,16 +167,16 @@ module test_memory_read_latency_True ( input wen, input ren ); -wire [4:0] Mem4x5_RDATA; -Memory Mem4x5 ( +wire [4:0] Memory_inst0_RDATA; +Memory Memory_inst0 ( .RADDR(raddr), - .RDATA(Mem4x5_RDATA), + .RDATA(Memory_inst0_RDATA), .CLK(clk), .RE(ren), .WADDR(waddr), .WDATA(wdata), .WE(wen) ); -assign rdata = Mem4x5_RDATA; +assign rdata = Memory_inst0_RDATA; endmodule diff --git a/tests/test_primitives/gold/test_memory_read_only.v b/tests/test_primitives/gold/test_memory_read_only.v index 8a76c364b..6010ab1f6 100644 --- a/tests/test_primitives/gold/test_memory_read_only.v +++ b/tests/test_primitives/gold/test_memory_read_only.v @@ -105,12 +105,12 @@ module test_memory_read_only ( output [4:0] rdata, input clk ); -wire [4:0] Mem4x5_RDATA; -Memory Mem4x5 ( +wire [4:0] Memory_inst0_RDATA; +Memory Memory_inst0 ( .RADDR(raddr), - .RDATA(Mem4x5_RDATA), + .RDATA(Memory_inst0_RDATA), .CLK(clk) ); -assign rdata = Mem4x5_RDATA; +assign rdata = Memory_inst0_RDATA; endmodule diff --git a/tests/test_smart/test_smart_bits.py b/tests/test_smart/test_smart_bits.py index a603191d5..e7a7ce044 100644 --- a/tests/test_smart/test_smart_bits.py +++ b/tests/test_smart/test_smart_bits.py @@ -59,9 +59,10 @@ class _Test(m.Circuit): O1=m.Out(m.smart.SmartBits[8]), O2=m.Out(m.smart.SmartBits[12]), O3=m.Out(m.smart.SmartBits[16])) - io.O1 @= op(io.I0, io.I1) - io.O2 @= op(io.I0, io.I1) - io.O3 @= op(io.I0, io.I1) + val = op(io.I0, io.I1) + io.O1 @= val + io.O2 @= val + io.O3 @= val class _Gold(m.Circuit): name = "test_binop" @@ -72,8 +73,9 @@ class _Gold(m.Circuit): O2=m.Out(m.UInt[12]), O3=m.Out(m.UInt[16])) O1 = m.UInt[8]() - io.O1 @= op(m.zext_to(io.I0, 12), io.I1)[:8] - io.O1._resolve_bulk_wire() # force elaboration for repr test + O1 @= op(m.zext_to(io.I0, 12), io.I1)[:8] + O1[0] # force elaboration for repr test + io.O1 @= O1 io.O2 @= op(m.zext_to(io.I0, 12), io.I1) io.O3 @= op(m.zext_to(io.I0, 16), m.zext_to(io.I1, 16)) @@ -119,10 +121,9 @@ class _Test(m.Circuit): I1=m.In(m.smart.SmartBits[4]), O1=m.Out(m.smart.SmartBits[8]), O2=m.Out(m.smart.SmartBits[16])) - io.O1 @= io.I0 << io.I1 - O2 = m.smart.SmartBits[16]() - O2 @= io.I0 << io.I1 - io.O2 @= O2 + val = io.I0 << io.I1 + io.O1 @= val + io.O2 @= val class _Gold(m.Circuit): name = "test_lshift" @@ -132,7 +133,7 @@ class _Gold(m.Circuit): O1=m.Out(m.UInt[8]), O2=m.Out(m.UInt[16])) io.O1 @= io.I0 << m.zext_to(io.I1, 8) - O2 = m.Bits[16]() + O2 = m.UInt[16]() O2 @= m.zext_to(io.I0 << m.zext_to(io.I1, 8), 16) io.O2 @= O2 @@ -150,13 +151,10 @@ class _Test(m.Circuit): O1=m.Out(m.smart.SmartBits[4]), O2=m.Out(m.smart.SmartBits[8]), O3=m.Out(m.smart.SmartBits[16])) - O1 = m.smart.SmartBits[4]() - O1 @= io.I0 >> io.I1 - io.O1 @= O1 - io.O2 @= io.I0 >> io.I1 - O3 = m.smart.SmartBits[16]() - O3 @= io.I0 >> io.I1 - io.O3 @= O3 + val = io.I0 >> io.I1 + io.O1 @= val + io.O2 @= val + io.O3 @= val class _Gold(m.Circuit): name = "test_rshift" @@ -166,12 +164,12 @@ class _Gold(m.Circuit): O1=m.Out(m.UInt[4]), O2=m.Out(m.UInt[8]), O3=m.Out(m.UInt[16])) - O1 = m.Bits[4]() + O1 = m.UInt[4]() O1 @= (io.I0 >> m.zext_to(io.I1, 8))[:4] O1[0] # force elaboration for repr test io.O1 @= O1 io.O2 @= m.zext_to(io.I0 >> m.zext_to(io.I1, 8), 8) - O3 = m.Bits[16]() + O3 = m.UInt[16]() O3 @= m.zext_to(io.I0 >> m.zext_to(io.I1, 8), 16) io.O3 @= O3 @@ -189,12 +187,9 @@ class _Test(m.Circuit): I2=m.In(m.smart.SmartBits[10]), O1=m.Out(m.smart.SmartBits[4]), O2=m.Out(m.smart.SmartBits[16])) - O1 = m.smart.SmartBits[4]() - O1 @= m.smart.concat(io.I0 + io.I1, io.I2) - io.O1 @= O1 - O2 = m.smart.SmartBits[16]() - O2 @= m.smart.concat(io.I0 + io.I1, io.I2) - io.O2 @= O2 + val = m.smart.concat(io.I0 + io.I1, io.I2) + io.O1 @= val + io.O2 @= val class _Gold(m.Circuit): name = "test_concat" @@ -204,10 +199,10 @@ class _Gold(m.Circuit): I2=m.In(m.UInt[10]), O1=m.Out(m.UInt[4]), O2=m.Out(m.UInt[16])) - O1 = m.Bits[4]() + O1 = m.UInt[4]() O1 @= m.concat(io.I0 + m.zext_to(io.I1, 8), io.I2)[:4] io.O1 @= O1 - O2 = m.Bits[16]() + O2 = m.UInt[16]() O2 @= m.concat(io.I0 + m.zext_to(io.I1, 8), io.I2)[:16] io.O2 @= O2 @@ -225,12 +220,8 @@ class _Test(m.Circuit): O1=m.Out(m.smart.SmartBits[24]), O2=m.Out(m.smart.SmartBits[6]), ) - O1 = m.smart.SmartBits[24]() - O1 @= m.smart.repeat(io.I0, 3) - io.O1 @= O1 - O2 = m.smart.SmartBits[6]() - O2 @= m.smart.repeat(io.I1[0], 6) - io.O2 @= O2 + io.O1 @= m.smart.repeat(io.I0, 3) + io.O2 @= m.smart.repeat(io.I1[0], 6) class _Gold(m.Circuit): name = "test_repeat" @@ -240,9 +231,9 @@ class _Gold(m.Circuit): O1=m.Out(m.UInt[24]), O2=m.Out(m.UInt[6]), ) - O1 = m.Bits[24]() # force elaboration for repr test + O1 = m.UInt[24]() # force elaboration for repr test O1 @= m.as_bits(m.repeat(io.I0, 3)) - O2 = m.Bits[6]() # force elaboration for repr test + O2 = m.UInt[6]() # force elaboration for repr test O2 @= m.repeat(io.I1[0], 6) io.O1 @= O1 io.O2 @= O2 @@ -261,8 +252,9 @@ class _Test(m.Circuit): I0=m.In(m.smart.SmartBits[8]), O1=m.Out(m.smart.SmartBits[4]), O2=m.Out(m.smart.SmartBits[16])) - io.O1 @= op(io.I0) - io.O2 @= op(io.I0) + val = op(io.I0) + io.O1 @= val + io.O2 @= val class _Gold(m.Circuit): name = "test_unary" @@ -270,8 +262,10 @@ class _Gold(m.Circuit): I0=m.In(m.UInt[8]), O1=m.Out(m.UInt[4]), O2=m.Out(m.UInt[16])) - io.O1 @= op(io.I0)[:4] - io.O1[0] # force elaboration for repr test + O1 = m.UInt[4]() + O1 @= op(io.I0)[:4] + O1[0] # force elaboration for repr test + io.O1 @= O1 io.O2 @= op(m.zext_to(io.I0, 16)) return _Test, _Gold @@ -539,9 +533,7 @@ class _Test(m.Circuit): S=m.In(m.smart.SmartBits[8]), O0=m.Out(m.smart.SmartBits[16]), ) - O0 = m.smart.SmartBits[16]() - O0 @= m.smart.mux([io.I0, io.I1], io.S) - io.O0 @= O0 + io.O0 @= m.smart.mux([io.I0, io.I1], io.S) class _Gold(m.Circuit): name = "test_mux" @@ -551,7 +543,7 @@ class _Gold(m.Circuit): S=m.In(m.UInt[8]), O0=m.Out(m.UInt[16]), ) - O0 = m.Bits[16]() # force elaboration for repr test + O0 = m.UInt[16]() # force elaboration for repr test O0 @= m.zext_to(m.mux([m.zext_to(io.I0, 12), io.I1], io.S[0]), 16) io.O0 @= O0 diff --git a/tests/test_symbol_table_generation.py b/tests/test_symbol_table_generation.py index e83d30160..b531b5e9b 100644 --- a/tests/test_symbol_table_generation.py +++ b/tests/test_symbol_table_generation.py @@ -26,12 +26,12 @@ class DFFInit1(m.Circuit): symbol_table = _compile("build/DFFInit1", DFFInit1) assert symbol_table.get_module_name("DFFInit1") == "DFFInit1" - assert (symbol_table.get_instance_name("DFFInit1", "dff_inst") == - (SYMBOL_TABLE_EMPTY, "dff_inst")) + assert (symbol_table.get_instance_name("DFFInit1", "SB_DFF_inst0") == + (SYMBOL_TABLE_EMPTY, "SB_DFF_inst0")) assert symbol_table.get_port_name("DFFInit1", "D") == "D" assert symbol_table.get_port_name("DFFInit1", "Q") == "Q" assert symbol_table.get_port_name("DFFInit1", "C") == "C" - instance_type = symbol_table.get_instance_type("DFFInit1", "dff_inst") + instance_type = symbol_table.get_instance_type("DFFInit1", "SB_DFF_inst0") assert instance_type == "SB_DFF" @@ -50,11 +50,10 @@ class DFFList(m.Circuit): symbol_table = _compile("build/DFFList", DFFList) for i in range(10): - inst_name = f"dff_{i}" - name = symbol_table.get_instance_name("DFFList", inst_name) - assert name == (SYMBOL_TABLE_EMPTY, inst_name) + name = symbol_table.get_instance_name("DFFList", f"SB_DFF_inst{i}") + assert name == (SYMBOL_TABLE_EMPTY, f"SB_DFF_inst{i}") instance_type = symbol_table.get_instance_type( - "DFFList", inst_name) + "DFFList", f"SB_DFF_inst{i}") assert instance_type == "SB_DFF" diff --git a/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v b/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v index 442d81df0..4e96c41e3 100644 --- a/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v +++ b/tests/test_syntax/gold/TestSequential2NestedLoopUnroll.v @@ -44,7 +44,7 @@ wire [3:0] Register_inst1_O; wire [3:0] Register_inst2_O; wire [3:0] Register_inst3_O; wire [3:0] Register_inst4_O; -wire [3:0] call_result_O; +wire [3:0] Register_inst5_O; Register Register_inst0 ( .I(I), .O(Register_inst0_O), @@ -70,11 +70,11 @@ Register Register_inst4 ( .O(Register_inst4_O), .CLK(CLK) ); -Register call_result ( +Register Register_inst5 ( .I(Register_inst4_O), - .O(call_result_O), + .O(Register_inst5_O), .CLK(CLK) ); -assign O = call_result_O; +assign O = Register_inst5_O; endmodule diff --git a/tests/test_syntax/gold/test_inline_comb_basic.v b/tests/test_syntax/gold/test_inline_comb_basic.v index ecbc3dadb..6cf079e39 100644 --- a/tests/test_syntax/gold/test_inline_comb_basic.v +++ b/tests/test_syntax/gold/test_inline_comb_basic.v @@ -59,11 +59,8 @@ module Main ( input CLK ); wire Mux2xBit_inst0_O; -wire Mux2xBit_inst1_O; -wire O1; wire magma_Bit_not_inst0_out; wire magma_Bit_not_inst1_out; -wire reg_O; Mux2xBit Mux2xBit_inst0 ( .I0(O0), .I1(magma_Bit_not_inst0_out), @@ -74,16 +71,14 @@ Mux2xBit Mux2xBit_inst1 ( .I0(O0), .I1(magma_Bit_not_inst1_out), .S(invert), - .O(Mux2xBit_inst1_O) + .O(O1) ); -assign O1 = Mux2xBit_inst1_O; -assign magma_Bit_not_inst0_out = ~ O0; -assign magma_Bit_not_inst1_out = ~ O0; -Register reg ( +Register Register_inst0 ( .I(Mux2xBit_inst0_O), - .O(reg_O), + .O(O0), .CLK(CLK) ); -assign O1 = O1; +assign magma_Bit_not_inst0_out = ~ O0; +assign magma_Bit_not_inst1_out = ~ O0; endmodule diff --git a/tests/test_syntax/gold/test_inline_comb_list.v b/tests/test_syntax/gold/test_inline_comb_list.v index 29fee170f..3d5181469 100644 --- a/tests/test_syntax/gold/test_inline_comb_list.v +++ b/tests/test_syntax/gold/test_inline_comb_list.v @@ -58,27 +58,27 @@ module Main ( output O1, input CLK ); +wire Register_inst0_O; wire magma_Bit_not_inst0_out; wire magma_Bit_not_inst1_out; -wire reg_O; Mux2xBit Mux2xBit_inst0 ( - .I0(\reg _O), + .I0(Register_inst0_O), .I1(magma_Bit_not_inst0_out), .S(s), .O(O0) ); Mux2xBit Mux2xBit_inst1 ( .I0(magma_Bit_not_inst1_out), - .I1(\reg _O), + .I1(Register_inst0_O), .S(s), .O(O1) ); -assign magma_Bit_not_inst0_out = ~ \reg _O; -assign magma_Bit_not_inst1_out = ~ \reg _O; -Register reg ( +Register Register_inst0 ( .I(O0), - .O(reg_O), + .O(Register_inst0_O), .CLK(CLK) ); +assign magma_Bit_not_inst0_out = ~ Register_inst0_O; +assign magma_Bit_not_inst1_out = ~ Register_inst0_O; endmodule diff --git a/tests/test_syntax/gold/test_inline_comb_wire.v b/tests/test_syntax/gold/test_inline_comb_wire.v index 3179ac828..d71a60a7c 100644 --- a/tests/test_syntax/gold/test_inline_comb_wire.v +++ b/tests/test_syntax/gold/test_inline_comb_wire.v @@ -59,18 +59,17 @@ module Main ( ); wire Mux2xBit_inst0_O; wire magma_Bit_not_inst0_out; -wire reg_O; Mux2xBit Mux2xBit_inst0 ( .I0(O), .I1(magma_Bit_not_inst0_out), .S(invert), .O(Mux2xBit_inst0_O) ); -assign magma_Bit_not_inst0_out = ~ O; -Register reg ( +Register Register_inst0 ( .I(Mux2xBit_inst0_O), - .O(reg_O), + .O(O), .CLK(CLK) ); +assign magma_Bit_not_inst0_out = ~ O; endmodule diff --git a/tests/test_syntax/gold/test_renamed_args_wire.json b/tests/test_syntax/gold/test_renamed_args_wire.json index 096cba389..8d8ff1d8f 100644 --- a/tests/test_syntax/gold/test_renamed_args_wire.json +++ b/tests/test_syntax/gold/test_renamed_args_wire.json @@ -8,13 +8,13 @@ ["O","Bit"] ]], "instances":{ - "inv":{ + "invert_inst0":{ "modref":"global.invert" } }, "connections":[ - ["self.O","inv.O"], - ["self.I","inv.a"] + ["self.O","invert_inst0.O"], + ["self.I","invert_inst0.a"] ] }, "Not":{ diff --git a/tests/test_type/gold/test_AsyncResetN[Out]_cast.v b/tests/test_type/gold/test_AsyncResetN[Out]_cast.v index 65d32cf48..a9a725671 100644 --- a/tests/test_type/gold/test_AsyncResetN[Out]_cast.v +++ b/tests/test_type/gold/test_AsyncResetN[Out]_cast.v @@ -19,6 +19,7 @@ module AsyncResetTest ( input T_Tuple_in_T, input T_in ); +wire Inst_inst0_O; wire coreir_wrapInAsyncResetN_inst0_out; wire coreir_wrapInAsyncResetN_inst1_out; wire coreir_wrapInAsyncResetN_inst2_out; @@ -30,7 +31,10 @@ wire coreir_wrapOutAsyncResetN_inst1_out; wire coreir_wrapOutAsyncResetN_inst2_out; wire coreir_wrapOutAsyncResetN_inst3_out; wire coreir_wrapOutAsyncResetN_inst4_out; -wire inst_O; +Inst Inst_inst0 ( + .O(Inst_inst0_O), + .I(coreir_wrapOutAsyncResetN_inst0_out) +); coreir_wrap coreir_wrapInAsyncResetN_inst0 ( .in(T_Tuple_in_T), .out(coreir_wrapInAsyncResetN_inst0_out) @@ -52,7 +56,7 @@ coreir_wrap coreir_wrapInAsyncResetN_inst4 ( .out(coreir_wrapInAsyncResetN_inst4_out) ); coreir_wrap coreir_wrapInAsyncResetN_inst5 ( - .in(inst_O), + .in(Inst_inst0_O), .out(coreir_wrapInAsyncResetN_inst5_out) ); coreir_wrap coreir_wrapOutAsyncResetN_inst0 ( @@ -75,10 +79,6 @@ coreir_wrap coreir_wrapOutAsyncResetN_inst4 ( .in(I_Arr[2]), .out(coreir_wrapOutAsyncResetN_inst4_out) ); -Inst inst ( - .O(inst_O), - .I(coreir_wrapOutAsyncResetN_inst0_out) -); assign Bit_Arr_out = {coreir_wrapInAsyncResetN_inst5_out,coreir_wrapInAsyncResetN_inst4_out,coreir_wrapInAsyncResetN_inst3_out,coreir_wrapInAsyncResetN_inst2_out}; assign Bit_out = coreir_wrapInAsyncResetN_inst1_out; assign O = coreir_wrapOutAsyncResetN_inst1_out; diff --git a/tests/test_type/gold/test_AsyncReset[Out]_cast.v b/tests/test_type/gold/test_AsyncReset[Out]_cast.v index 08545543c..62a52ccd1 100644 --- a/tests/test_type/gold/test_AsyncReset[Out]_cast.v +++ b/tests/test_type/gold/test_AsyncReset[Out]_cast.v @@ -19,6 +19,7 @@ module AsyncResetTest ( input T_Tuple_in_T, input T_in ); +wire Inst_inst0_O; wire coreir_wrapInAsyncReset_inst0_out; wire coreir_wrapInAsyncReset_inst1_out; wire coreir_wrapInAsyncReset_inst2_out; @@ -30,7 +31,10 @@ wire coreir_wrapOutAsyncReset_inst1_out; wire coreir_wrapOutAsyncReset_inst2_out; wire coreir_wrapOutAsyncReset_inst3_out; wire coreir_wrapOutAsyncReset_inst4_out; -wire inst_O; +Inst Inst_inst0 ( + .O(Inst_inst0_O), + .I(coreir_wrapOutAsyncReset_inst0_out) +); coreir_wrap coreir_wrapInAsyncReset_inst0 ( .in(T_Tuple_in_T), .out(coreir_wrapInAsyncReset_inst0_out) @@ -52,7 +56,7 @@ coreir_wrap coreir_wrapInAsyncReset_inst4 ( .out(coreir_wrapInAsyncReset_inst4_out) ); coreir_wrap coreir_wrapInAsyncReset_inst5 ( - .in(inst_O), + .in(Inst_inst0_O), .out(coreir_wrapInAsyncReset_inst5_out) ); coreir_wrap coreir_wrapOutAsyncReset_inst0 ( @@ -75,10 +79,6 @@ coreir_wrap coreir_wrapOutAsyncReset_inst4 ( .in(I_Arr[2]), .out(coreir_wrapOutAsyncReset_inst4_out) ); -Inst inst ( - .O(inst_O), - .I(coreir_wrapOutAsyncReset_inst0_out) -); assign Bit_Arr_out = {coreir_wrapInAsyncReset_inst5_out,coreir_wrapInAsyncReset_inst4_out,coreir_wrapInAsyncReset_inst3_out,coreir_wrapInAsyncReset_inst2_out}; assign Bit_out = coreir_wrapInAsyncReset_inst1_out; assign O = coreir_wrapOutAsyncReset_inst1_out; diff --git a/tests/test_type/gold/test_anon_bits.v b/tests/test_type/gold/test_anon_bits.v index 7d027caba..1df2f4f51 100644 --- a/tests/test_type/gold/test_anon_bits.v +++ b/tests/test_type/gold/test_anon_bits.v @@ -1,30 +1,7 @@ -module coreir_wire #( - parameter width = 1 -) ( - input [width-1:0] in, - output [width-1:0] out -); - assign out = in; -endmodule - module Test ( input [4:0] I, output [4:0] O ); -wire [4:0] x_out; -wire [4:0] y_out; -coreir_wire #( - .width(5) -) x ( - .in(y_out), - .out(x_out) -); -coreir_wire #( - .width(5) -) y ( - .in(I), - .out(y_out) -); -assign O = x_out; +assign O = I; endmodule diff --git a/tests/test_type/gold/test_array2_2d_tuple.v b/tests/test_type/gold/test_array2_2d_tuple.v index 4bc66b2ad..9dbbad017 100644 --- a/tests/test_type/gold/test_array2_2d_tuple.v +++ b/tests/test_type/gold/test_array2_2d_tuple.v @@ -1,34 +1,16 @@ -module coreir_wire #( - parameter width = 1 -) ( - input [width-1:0] in, - output [width-1:0] out -); - assign out = in; -endmodule - module Foo ( input [3:0] I_c_0_a [3:0], input [3:0] I_c_1_a [3:0], output [3:0] O_c_0_a [3:0], output [3:0] O_c_1_a [3:0] ); -wire [31:0] temp_out; -wire [31:0] temp_in; -assign temp_in = {I_c_0_a[0],I_c_0_a[1],I_c_0_a[2],I_c_0_a[3],I_c_1_a[0],I_c_1_a[1],I_c_1_a[2],I_c_1_a[3]}; -coreir_wire #( - .width(32) -) temp ( - .in(temp_in), - .out(temp_out) -); -assign O_c_0_a[3] = {temp_out[15],temp_out[14],temp_out[13],temp_out[12]}; -assign O_c_0_a[2] = {temp_out[11],temp_out[10],temp_out[9],temp_out[8]}; -assign O_c_0_a[1] = {temp_out[7],temp_out[6],temp_out[5],temp_out[4]}; -assign O_c_0_a[0] = {temp_out[3],temp_out[2],temp_out[1],temp_out[0]}; -assign O_c_1_a[3] = {temp_out[31],temp_out[30],temp_out[29],temp_out[28]}; -assign O_c_1_a[2] = {temp_out[27],temp_out[26],temp_out[25],temp_out[24]}; -assign O_c_1_a[1] = {temp_out[23],temp_out[22],temp_out[21],temp_out[20]}; -assign O_c_1_a[0] = {temp_out[19],temp_out[18],temp_out[17],temp_out[16]}; +assign O_c_0_a[3] = I_c_1_a[0]; +assign O_c_0_a[2] = I_c_1_a[1]; +assign O_c_0_a[1] = I_c_1_a[2]; +assign O_c_0_a[0] = I_c_1_a[3]; +assign O_c_1_a[3] = I_c_0_a[0]; +assign O_c_1_a[2] = I_c_0_a[1]; +assign O_c_1_a[1] = I_c_0_a[2]; +assign O_c_1_a[0] = I_c_0_a[3]; endmodule diff --git a/tests/test_type/gold/test_array2_nested_bits_temporary.v b/tests/test_type/gold/test_array2_nested_bits_temporary.v index 531da0382..157c2573b 100644 --- a/tests/test_type/gold/test_array2_nested_bits_temporary.v +++ b/tests/test_type/gold/test_array2_nested_bits_temporary.v @@ -37,6 +37,7 @@ module Foo ( output [7:0] O [3:0], input CLK ); +wire [7:0] Register_inst0_O; wire magma_Bit_and_inst0_out; wire magma_Bit_and_inst1_out; wire magma_Bit_and_inst2_out; @@ -50,25 +51,24 @@ wire [7:0] pointer_0; wire [7:0] pointer_1; wire [7:0] pointer_2; wire [7:0] pointer_3; -wire [7:0] reg_O; +Register Register_inst0 ( + .I(write_pointer), + .O(Register_inst0_O), + .CLK(CLK) +); assign magma_Bit_and_inst0_out = pointer_0[7] & 1'b1; assign magma_Bit_and_inst1_out = pointer_1[7] & 1'b1; assign magma_Bit_and_inst2_out = pointer_2[7] & 1'b1; assign magma_Bit_and_inst3_out = pointer_3[7] & 1'b1; -assign magma_UInt_8_add_inst0_out = 8'(\reg _O + 8'h00); -assign magma_UInt_8_add_inst1_out = 8'(\reg _O + 8'h01); -assign magma_UInt_8_add_inst2_out = 8'(\reg _O + 8'h02); -assign magma_UInt_8_add_inst3_out = 8'(\reg _O + 8'h03); +assign magma_UInt_8_add_inst0_out = 8'(Register_inst0_O + 8'h00); +assign magma_UInt_8_add_inst1_out = 8'(Register_inst0_O + 8'h01); +assign magma_UInt_8_add_inst2_out = 8'(Register_inst0_O + 8'h02); +assign magma_UInt_8_add_inst3_out = 8'(Register_inst0_O + 8'h03); assign pointer = {magma_UInt_8_add_inst3_out,magma_UInt_8_add_inst2_out,magma_UInt_8_add_inst1_out,magma_UInt_8_add_inst0_out}; assign pointer_0 = magma_UInt_8_add_inst0_out; assign pointer_1 = magma_UInt_8_add_inst1_out; assign pointer_2 = magma_UInt_8_add_inst2_out; assign pointer_3 = magma_UInt_8_add_inst3_out; -Register reg ( - .I(write_pointer), - .O(reg_O), - .CLK(CLK) -); assign O[3] = {pointer[31],pointer[30],pointer[29],pointer[28],pointer[27],pointer[26],pointer[25],pointer[24]}; assign O[2] = {pointer[23],pointer[22],pointer[21],pointer[20],pointer[19],pointer[18],pointer[17],pointer[16]}; assign O[1] = {pointer[15],pointer[14],pointer[13],pointer[12],pointer[11],pointer[10],pointer[9],pointer[8]}; diff --git a/tests/test_type/gold/test_insert_wrap_casts_temporary.v b/tests/test_type/gold/test_insert_wrap_casts_temporary.v index bd37eff28..23b95c1d6 100644 --- a/tests/test_type/gold/test_insert_wrap_casts_temporary.v +++ b/tests/test_type/gold/test_insert_wrap_casts_temporary.v @@ -19,65 +19,28 @@ module corebit_term ( endmodule -module WireClock ( - input I, - output O -); -wire Wire_inst0_out; -wire coreir_wrapInClock_inst0_out; -wire coreir_wrapOutClock_inst0_out; -corebit_wire Wire_inst0 ( - .in(coreir_wrapInClock_inst0_out), - .out(Wire_inst0_out) -); -coreir_wrap coreir_wrapInClock_inst0 ( - .in(I), - .out(coreir_wrapInClock_inst0_out) -); -coreir_wrap coreir_wrapOutClock_inst0 ( - .in(Wire_inst0_out), - .out(coreir_wrapOutClock_inst0_out) -); -assign O = coreir_wrapOutClock_inst0_out; -endmodule - module Bar ( input CLK, input RESETN ); wire coreir_wrapInClock_inst0_out; wire coreir_wrapOutClock_inst0_out; -wire temp0_O; wire temp1_out; -wire temp2_O; -wire temp3_out; +Foo Foo_inst0 ( + .CLK(coreir_wrapOutClock_inst0_out) +); coreir_wrap coreir_wrapInClock_inst0 ( - .in(temp0_O), + .in(CLK), .out(coreir_wrapInClock_inst0_out) ); coreir_wrap coreir_wrapOutClock_inst0 ( .in(temp1_out), .out(coreir_wrapOutClock_inst0_out) ); -Foo foo0 ( - .CLK(coreir_wrapOutClock_inst0_out) -); -WireClock temp0 ( - .I(CLK), - .O(temp0_O) -); corebit_wire temp1 ( .in(coreir_wrapInClock_inst0_out), .out(temp1_out) ); -WireClock temp2 ( - .I(CLK), - .O(temp2_O) -); -corebit_wire temp3 ( - .in(RESETN), - .out(temp3_out) -); -always @(posedge temp2_O) disable iff (! temp3_out) $display("Hello"); +always @(posedge CLK) disable iff (! RESETN) $display("Hello"); endmodule diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem.v b/tests/test_type/gold/test_ndarray_dynamic_getitem.v index 4112dc904..ec5ac0f46 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem.v @@ -79,23 +79,23 @@ module Main ( input CLK ); wire [1:0] Mux4xArray3_Array2_Bit_inst0_O [2:0]; -wire [1:0] mem_O [3:0][2:0]; +wire [1:0] Register_inst0_O [3:0][2:0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I0 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I0[2] = mem_O[0][2]; -assign Mux4xArray3_Array2_Bit_inst0_I0[1] = mem_O[0][1]; -assign Mux4xArray3_Array2_Bit_inst0_I0[0] = mem_O[0][0]; +assign Mux4xArray3_Array2_Bit_inst0_I0[2] = Register_inst0_O[0][2]; +assign Mux4xArray3_Array2_Bit_inst0_I0[1] = Register_inst0_O[0][1]; +assign Mux4xArray3_Array2_Bit_inst0_I0[0] = Register_inst0_O[0][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I1 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I1[2] = mem_O[1][2]; -assign Mux4xArray3_Array2_Bit_inst0_I1[1] = mem_O[1][1]; -assign Mux4xArray3_Array2_Bit_inst0_I1[0] = mem_O[1][0]; +assign Mux4xArray3_Array2_Bit_inst0_I1[2] = Register_inst0_O[1][2]; +assign Mux4xArray3_Array2_Bit_inst0_I1[1] = Register_inst0_O[1][1]; +assign Mux4xArray3_Array2_Bit_inst0_I1[0] = Register_inst0_O[1][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I2 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I2[2] = mem_O[2][2]; -assign Mux4xArray3_Array2_Bit_inst0_I2[1] = mem_O[2][1]; -assign Mux4xArray3_Array2_Bit_inst0_I2[0] = mem_O[2][0]; +assign Mux4xArray3_Array2_Bit_inst0_I2[2] = Register_inst0_O[2][2]; +assign Mux4xArray3_Array2_Bit_inst0_I2[1] = Register_inst0_O[2][1]; +assign Mux4xArray3_Array2_Bit_inst0_I2[0] = Register_inst0_O[2][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I3 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I3[2] = mem_O[3][2]; -assign Mux4xArray3_Array2_Bit_inst0_I3[1] = mem_O[3][1]; -assign Mux4xArray3_Array2_Bit_inst0_I3[0] = mem_O[3][0]; +assign Mux4xArray3_Array2_Bit_inst0_I3[2] = Register_inst0_O[3][2]; +assign Mux4xArray3_Array2_Bit_inst0_I3[1] = Register_inst0_O[3][1]; +assign Mux4xArray3_Array2_Bit_inst0_I3[0] = Register_inst0_O[3][0]; Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .I0(Mux4xArray3_Array2_Bit_inst0_I0), .I1(Mux4xArray3_Array2_Bit_inst0_I1), @@ -104,22 +104,22 @@ Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .S(raddr), .O(Mux4xArray3_Array2_Bit_inst0_O) ); -wire [1:0] mem_I [3:0][2:0]; -assign mem_I[3][2] = mem_O[3][2]; -assign mem_I[3][1] = mem_O[3][1]; -assign mem_I[3][0] = mem_O[3][0]; -assign mem_I[2][2] = mem_O[2][2]; -assign mem_I[2][1] = mem_O[2][1]; -assign mem_I[2][0] = mem_O[2][0]; -assign mem_I[1][2] = mem_O[1][2]; -assign mem_I[1][1] = mem_O[1][1]; -assign mem_I[1][0] = mem_O[1][0]; -assign mem_I[0][2] = mem_O[0][2]; -assign mem_I[0][1] = mem_O[0][1]; -assign mem_I[0][0] = mem_O[0][0]; -Register mem ( - .I(mem_I), - .O(mem_O), +wire [1:0] Register_inst0_I [3:0][2:0]; +assign Register_inst0_I[3][2] = Register_inst0_O[3][2]; +assign Register_inst0_I[3][1] = Register_inst0_O[3][1]; +assign Register_inst0_I[3][0] = Register_inst0_O[3][0]; +assign Register_inst0_I[2][2] = Register_inst0_O[2][2]; +assign Register_inst0_I[2][1] = Register_inst0_O[2][1]; +assign Register_inst0_I[2][0] = Register_inst0_O[2][0]; +assign Register_inst0_I[1][2] = Register_inst0_O[1][2]; +assign Register_inst0_I[1][1] = Register_inst0_O[1][1]; +assign Register_inst0_I[1][0] = Register_inst0_O[1][0]; +assign Register_inst0_I[0][2] = Register_inst0_O[0][2]; +assign Register_inst0_I[0][1] = Register_inst0_O[0][1]; +assign Register_inst0_I[0][0] = Register_inst0_O[0][0]; +Register Register_inst0 ( + .I(Register_inst0_I), + .O(Register_inst0_O), .CLK(CLK) ); assign rdata[2] = Mux4xArray3_Array2_Bit_inst0_O[2]; diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v index 95bf263cf..9b85af60d 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem2.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem2.v @@ -94,23 +94,23 @@ module Main ( ); wire [1:0] Mux4xArray3_Array2_Bit_inst0_O [2:0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_O [2:0]; -wire [1:0] mem_O [1:0][3:0][2:0]; +wire [1:0] Register_inst0_O [1:0][3:0][2:0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I0 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I0[2] = mem_O[0][0][2]; -assign Mux4xArray3_Array2_Bit_inst0_I0[1] = mem_O[0][0][1]; -assign Mux4xArray3_Array2_Bit_inst0_I0[0] = mem_O[0][0][0]; +assign Mux4xArray3_Array2_Bit_inst0_I0[2] = Register_inst0_O[0][0][2]; +assign Mux4xArray3_Array2_Bit_inst0_I0[1] = Register_inst0_O[0][0][1]; +assign Mux4xArray3_Array2_Bit_inst0_I0[0] = Register_inst0_O[0][0][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I1 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I1[2] = mem_O[0][1][2]; -assign Mux4xArray3_Array2_Bit_inst0_I1[1] = mem_O[0][1][1]; -assign Mux4xArray3_Array2_Bit_inst0_I1[0] = mem_O[0][1][0]; +assign Mux4xArray3_Array2_Bit_inst0_I1[2] = Register_inst0_O[0][1][2]; +assign Mux4xArray3_Array2_Bit_inst0_I1[1] = Register_inst0_O[0][1][1]; +assign Mux4xArray3_Array2_Bit_inst0_I1[0] = Register_inst0_O[0][1][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I2 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I2[2] = mem_O[0][2][2]; -assign Mux4xArray3_Array2_Bit_inst0_I2[1] = mem_O[0][2][1]; -assign Mux4xArray3_Array2_Bit_inst0_I2[0] = mem_O[0][2][0]; +assign Mux4xArray3_Array2_Bit_inst0_I2[2] = Register_inst0_O[0][2][2]; +assign Mux4xArray3_Array2_Bit_inst0_I2[1] = Register_inst0_O[0][2][1]; +assign Mux4xArray3_Array2_Bit_inst0_I2[0] = Register_inst0_O[0][2][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst0_I3 [2:0]; -assign Mux4xArray3_Array2_Bit_inst0_I3[2] = mem_O[0][3][2]; -assign Mux4xArray3_Array2_Bit_inst0_I3[1] = mem_O[0][3][1]; -assign Mux4xArray3_Array2_Bit_inst0_I3[0] = mem_O[0][3][0]; +assign Mux4xArray3_Array2_Bit_inst0_I3[2] = Register_inst0_O[0][3][2]; +assign Mux4xArray3_Array2_Bit_inst0_I3[1] = Register_inst0_O[0][3][1]; +assign Mux4xArray3_Array2_Bit_inst0_I3[0] = Register_inst0_O[0][3][0]; Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .I0(Mux4xArray3_Array2_Bit_inst0_I0), .I1(Mux4xArray3_Array2_Bit_inst0_I1), @@ -120,21 +120,21 @@ Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst0 ( .O(Mux4xArray3_Array2_Bit_inst0_O) ); wire [1:0] Mux4xArray3_Array2_Bit_inst1_I0 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I0[2] = mem_O[1][0][2]; -assign Mux4xArray3_Array2_Bit_inst1_I0[1] = mem_O[1][0][1]; -assign Mux4xArray3_Array2_Bit_inst1_I0[0] = mem_O[1][0][0]; +assign Mux4xArray3_Array2_Bit_inst1_I0[2] = Register_inst0_O[1][0][2]; +assign Mux4xArray3_Array2_Bit_inst1_I0[1] = Register_inst0_O[1][0][1]; +assign Mux4xArray3_Array2_Bit_inst1_I0[0] = Register_inst0_O[1][0][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_I1 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I1[2] = mem_O[1][1][2]; -assign Mux4xArray3_Array2_Bit_inst1_I1[1] = mem_O[1][1][1]; -assign Mux4xArray3_Array2_Bit_inst1_I1[0] = mem_O[1][1][0]; +assign Mux4xArray3_Array2_Bit_inst1_I1[2] = Register_inst0_O[1][1][2]; +assign Mux4xArray3_Array2_Bit_inst1_I1[1] = Register_inst0_O[1][1][1]; +assign Mux4xArray3_Array2_Bit_inst1_I1[0] = Register_inst0_O[1][1][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_I2 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I2[2] = mem_O[1][2][2]; -assign Mux4xArray3_Array2_Bit_inst1_I2[1] = mem_O[1][2][1]; -assign Mux4xArray3_Array2_Bit_inst1_I2[0] = mem_O[1][2][0]; +assign Mux4xArray3_Array2_Bit_inst1_I2[2] = Register_inst0_O[1][2][2]; +assign Mux4xArray3_Array2_Bit_inst1_I2[1] = Register_inst0_O[1][2][1]; +assign Mux4xArray3_Array2_Bit_inst1_I2[0] = Register_inst0_O[1][2][0]; wire [1:0] Mux4xArray3_Array2_Bit_inst1_I3 [2:0]; -assign Mux4xArray3_Array2_Bit_inst1_I3[2] = mem_O[1][3][2]; -assign Mux4xArray3_Array2_Bit_inst1_I3[1] = mem_O[1][3][1]; -assign Mux4xArray3_Array2_Bit_inst1_I3[0] = mem_O[1][3][0]; +assign Mux4xArray3_Array2_Bit_inst1_I3[2] = Register_inst0_O[1][3][2]; +assign Mux4xArray3_Array2_Bit_inst1_I3[1] = Register_inst0_O[1][3][1]; +assign Mux4xArray3_Array2_Bit_inst1_I3[0] = Register_inst0_O[1][3][0]; Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst1 ( .I0(Mux4xArray3_Array2_Bit_inst1_I0), .I1(Mux4xArray3_Array2_Bit_inst1_I1), @@ -143,34 +143,34 @@ Mux4xArray3_Array2_Bit Mux4xArray3_Array2_Bit_inst1 ( .S(raddr1), .O(Mux4xArray3_Array2_Bit_inst1_O) ); -wire [1:0] mem_I [1:0][3:0][2:0]; -assign mem_I[1][3][2] = mem_O[1][3][2]; -assign mem_I[1][3][1] = mem_O[1][3][1]; -assign mem_I[1][3][0] = mem_O[1][3][0]; -assign mem_I[1][2][2] = mem_O[1][2][2]; -assign mem_I[1][2][1] = mem_O[1][2][1]; -assign mem_I[1][2][0] = mem_O[1][2][0]; -assign mem_I[1][1][2] = mem_O[1][1][2]; -assign mem_I[1][1][1] = mem_O[1][1][1]; -assign mem_I[1][1][0] = mem_O[1][1][0]; -assign mem_I[1][0][2] = mem_O[1][0][2]; -assign mem_I[1][0][1] = mem_O[1][0][1]; -assign mem_I[1][0][0] = mem_O[1][0][0]; -assign mem_I[0][3][2] = mem_O[0][3][2]; -assign mem_I[0][3][1] = mem_O[0][3][1]; -assign mem_I[0][3][0] = mem_O[0][3][0]; -assign mem_I[0][2][2] = mem_O[0][2][2]; -assign mem_I[0][2][1] = mem_O[0][2][1]; -assign mem_I[0][2][0] = mem_O[0][2][0]; -assign mem_I[0][1][2] = mem_O[0][1][2]; -assign mem_I[0][1][1] = mem_O[0][1][1]; -assign mem_I[0][1][0] = mem_O[0][1][0]; -assign mem_I[0][0][2] = mem_O[0][0][2]; -assign mem_I[0][0][1] = mem_O[0][0][1]; -assign mem_I[0][0][0] = mem_O[0][0][0]; -Register mem ( - .I(mem_I), - .O(mem_O), +wire [1:0] Register_inst0_I [1:0][3:0][2:0]; +assign Register_inst0_I[1][3][2] = Register_inst0_O[1][3][2]; +assign Register_inst0_I[1][3][1] = Register_inst0_O[1][3][1]; +assign Register_inst0_I[1][3][0] = Register_inst0_O[1][3][0]; +assign Register_inst0_I[1][2][2] = Register_inst0_O[1][2][2]; +assign Register_inst0_I[1][2][1] = Register_inst0_O[1][2][1]; +assign Register_inst0_I[1][2][0] = Register_inst0_O[1][2][0]; +assign Register_inst0_I[1][1][2] = Register_inst0_O[1][1][2]; +assign Register_inst0_I[1][1][1] = Register_inst0_O[1][1][1]; +assign Register_inst0_I[1][1][0] = Register_inst0_O[1][1][0]; +assign Register_inst0_I[1][0][2] = Register_inst0_O[1][0][2]; +assign Register_inst0_I[1][0][1] = Register_inst0_O[1][0][1]; +assign Register_inst0_I[1][0][0] = Register_inst0_O[1][0][0]; +assign Register_inst0_I[0][3][2] = Register_inst0_O[0][3][2]; +assign Register_inst0_I[0][3][1] = Register_inst0_O[0][3][1]; +assign Register_inst0_I[0][3][0] = Register_inst0_O[0][3][0]; +assign Register_inst0_I[0][2][2] = Register_inst0_O[0][2][2]; +assign Register_inst0_I[0][2][1] = Register_inst0_O[0][2][1]; +assign Register_inst0_I[0][2][0] = Register_inst0_O[0][2][0]; +assign Register_inst0_I[0][1][2] = Register_inst0_O[0][1][2]; +assign Register_inst0_I[0][1][1] = Register_inst0_O[0][1][1]; +assign Register_inst0_I[0][1][0] = Register_inst0_O[0][1][0]; +assign Register_inst0_I[0][0][2] = Register_inst0_O[0][0][2]; +assign Register_inst0_I[0][0][1] = Register_inst0_O[0][0][1]; +assign Register_inst0_I[0][0][0] = Register_inst0_O[0][0][0]; +Register Register_inst0 ( + .I(Register_inst0_I), + .O(Register_inst0_O), .CLK(CLK) ); assign rdata0[2] = Mux4xArray3_Array2_Bit_inst0_O[2]; diff --git a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v index 7218d857b..0e635aa46 100644 --- a/tests/test_type/gold/test_ndarray_dynamic_getitem3.v +++ b/tests/test_type/gold/test_ndarray_dynamic_getitem3.v @@ -97,35 +97,35 @@ module Main ( ); wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_O [1:0][2:0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_O [1:0][2:0]; -wire [1:0] mem_O [3:0][1:0][2:0]; +wire [1:0] Register_inst0_O [3:0][1:0][2:0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I0 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][2] = mem_O[0][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][1] = mem_O[0][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][0] = mem_O[0][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][2] = mem_O[0][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][1] = mem_O[0][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][0] = mem_O[0][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][2] = Register_inst0_O[0][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][1] = Register_inst0_O[0][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[1][0] = Register_inst0_O[0][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][2] = Register_inst0_O[0][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][1] = Register_inst0_O[0][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I0[0][0] = Register_inst0_O[0][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I1 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][2] = mem_O[1][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][1] = mem_O[1][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][0] = mem_O[1][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][2] = mem_O[1][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][1] = mem_O[1][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][0] = mem_O[1][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][2] = Register_inst0_O[1][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][1] = Register_inst0_O[1][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[1][0] = Register_inst0_O[1][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][2] = Register_inst0_O[1][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][1] = Register_inst0_O[1][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I1[0][0] = Register_inst0_O[1][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I2 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][2] = mem_O[2][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][1] = mem_O[2][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][0] = mem_O[2][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][2] = mem_O[2][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][1] = mem_O[2][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][0] = mem_O[2][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][2] = Register_inst0_O[2][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][1] = Register_inst0_O[2][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[1][0] = Register_inst0_O[2][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][2] = Register_inst0_O[2][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][1] = Register_inst0_O[2][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I2[0][0] = Register_inst0_O[2][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst0_I3 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][2] = mem_O[3][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][1] = mem_O[3][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][0] = mem_O[3][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][2] = mem_O[3][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][1] = mem_O[3][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][0] = mem_O[3][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][2] = Register_inst0_O[3][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][1] = Register_inst0_O[3][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[1][0] = Register_inst0_O[3][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][2] = Register_inst0_O[3][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][1] = Register_inst0_O[3][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst0_I3[0][0] = Register_inst0_O[3][0][0]; Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst0 ( .I0(Mux4xArray2_Array3_Array2_Bit_inst0_I0), .I1(Mux4xArray2_Array3_Array2_Bit_inst0_I1), @@ -135,33 +135,33 @@ Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst0 ( .O(Mux4xArray2_Array3_Array2_Bit_inst0_O) ); wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I0 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][2] = mem_O[0][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][1] = mem_O[0][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][0] = mem_O[0][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][2] = mem_O[0][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][1] = mem_O[0][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][0] = mem_O[0][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][2] = Register_inst0_O[0][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][1] = Register_inst0_O[0][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[1][0] = Register_inst0_O[0][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][2] = Register_inst0_O[0][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][1] = Register_inst0_O[0][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I0[0][0] = Register_inst0_O[0][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I1 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][2] = mem_O[1][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][1] = mem_O[1][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][0] = mem_O[1][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][2] = mem_O[1][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][1] = mem_O[1][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][0] = mem_O[1][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][2] = Register_inst0_O[1][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][1] = Register_inst0_O[1][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[1][0] = Register_inst0_O[1][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][2] = Register_inst0_O[1][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][1] = Register_inst0_O[1][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I1[0][0] = Register_inst0_O[1][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I2 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][2] = mem_O[2][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][1] = mem_O[2][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][0] = mem_O[2][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][2] = mem_O[2][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][1] = mem_O[2][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][0] = mem_O[2][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][2] = Register_inst0_O[2][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][1] = Register_inst0_O[2][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[1][0] = Register_inst0_O[2][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][2] = Register_inst0_O[2][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][1] = Register_inst0_O[2][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I2[0][0] = Register_inst0_O[2][0][0]; wire [1:0] Mux4xArray2_Array3_Array2_Bit_inst1_I3 [1:0][2:0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][2] = mem_O[3][1][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][1] = mem_O[3][1][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][0] = mem_O[3][1][0]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][2] = mem_O[3][0][2]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][1] = mem_O[3][0][1]; -assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][0] = mem_O[3][0][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][2] = Register_inst0_O[3][1][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][1] = Register_inst0_O[3][1][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[1][0] = Register_inst0_O[3][1][0]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][2] = Register_inst0_O[3][0][2]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][1] = Register_inst0_O[3][0][1]; +assign Mux4xArray2_Array3_Array2_Bit_inst1_I3[0][0] = Register_inst0_O[3][0][0]; Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst1 ( .I0(Mux4xArray2_Array3_Array2_Bit_inst1_I0), .I1(Mux4xArray2_Array3_Array2_Bit_inst1_I1), @@ -170,34 +170,34 @@ Mux4xArray2_Array3_Array2_Bit Mux4xArray2_Array3_Array2_Bit_inst1 ( .S(raddr1), .O(Mux4xArray2_Array3_Array2_Bit_inst1_O) ); -wire [1:0] mem_I [3:0][1:0][2:0]; -assign mem_I[3][1][2] = mem_O[3][1][2]; -assign mem_I[3][1][1] = mem_O[3][1][1]; -assign mem_I[3][1][0] = mem_O[3][1][0]; -assign mem_I[3][0][2] = mem_O[3][0][2]; -assign mem_I[3][0][1] = mem_O[3][0][1]; -assign mem_I[3][0][0] = mem_O[3][0][0]; -assign mem_I[2][1][2] = mem_O[2][1][2]; -assign mem_I[2][1][1] = mem_O[2][1][1]; -assign mem_I[2][1][0] = mem_O[2][1][0]; -assign mem_I[2][0][2] = mem_O[2][0][2]; -assign mem_I[2][0][1] = mem_O[2][0][1]; -assign mem_I[2][0][0] = mem_O[2][0][0]; -assign mem_I[1][1][2] = mem_O[1][1][2]; -assign mem_I[1][1][1] = mem_O[1][1][1]; -assign mem_I[1][1][0] = mem_O[1][1][0]; -assign mem_I[1][0][2] = mem_O[1][0][2]; -assign mem_I[1][0][1] = mem_O[1][0][1]; -assign mem_I[1][0][0] = mem_O[1][0][0]; -assign mem_I[0][1][2] = mem_O[0][1][2]; -assign mem_I[0][1][1] = mem_O[0][1][1]; -assign mem_I[0][1][0] = mem_O[0][1][0]; -assign mem_I[0][0][2] = mem_O[0][0][2]; -assign mem_I[0][0][1] = mem_O[0][0][1]; -assign mem_I[0][0][0] = mem_O[0][0][0]; -Register mem ( - .I(mem_I), - .O(mem_O), +wire [1:0] Register_inst0_I [3:0][1:0][2:0]; +assign Register_inst0_I[3][1][2] = Register_inst0_O[3][1][2]; +assign Register_inst0_I[3][1][1] = Register_inst0_O[3][1][1]; +assign Register_inst0_I[3][1][0] = Register_inst0_O[3][1][0]; +assign Register_inst0_I[3][0][2] = Register_inst0_O[3][0][2]; +assign Register_inst0_I[3][0][1] = Register_inst0_O[3][0][1]; +assign Register_inst0_I[3][0][0] = Register_inst0_O[3][0][0]; +assign Register_inst0_I[2][1][2] = Register_inst0_O[2][1][2]; +assign Register_inst0_I[2][1][1] = Register_inst0_O[2][1][1]; +assign Register_inst0_I[2][1][0] = Register_inst0_O[2][1][0]; +assign Register_inst0_I[2][0][2] = Register_inst0_O[2][0][2]; +assign Register_inst0_I[2][0][1] = Register_inst0_O[2][0][1]; +assign Register_inst0_I[2][0][0] = Register_inst0_O[2][0][0]; +assign Register_inst0_I[1][1][2] = Register_inst0_O[1][1][2]; +assign Register_inst0_I[1][1][1] = Register_inst0_O[1][1][1]; +assign Register_inst0_I[1][1][0] = Register_inst0_O[1][1][0]; +assign Register_inst0_I[1][0][2] = Register_inst0_O[1][0][2]; +assign Register_inst0_I[1][0][1] = Register_inst0_O[1][0][1]; +assign Register_inst0_I[1][0][0] = Register_inst0_O[1][0][0]; +assign Register_inst0_I[0][1][2] = Register_inst0_O[0][1][2]; +assign Register_inst0_I[0][1][1] = Register_inst0_O[0][1][1]; +assign Register_inst0_I[0][1][0] = Register_inst0_O[0][1][0]; +assign Register_inst0_I[0][0][2] = Register_inst0_O[0][0][2]; +assign Register_inst0_I[0][0][1] = Register_inst0_O[0][0][1]; +assign Register_inst0_I[0][0][0] = Register_inst0_O[0][0][0]; +Register Register_inst0 ( + .I(Register_inst0_I), + .O(Register_inst0_O), .CLK(CLK) ); assign rdata0[2] = Mux4xArray2_Array3_Array2_Bit_inst0_O[0][2]; diff --git a/tests/test_type/test_array2.py b/tests/test_type/test_array2.py index 61b478d5d..d004ad4b3 100644 --- a/tests/test_type/test_array2.py +++ b/tests/test_type/test_array2.py @@ -485,16 +485,14 @@ class Foo(m.Circuit): expected = """\ Foo = DefineCircuit("Foo", "I", Tuple(c=Array[(2, X)]), "O", Tuple(c=Array[(2, X)])) -temp = Tuple(c=Array[(2, X)])(name="temp") -wire(temp, Foo.O) -wire(Foo.I.c[1].a[3], temp.c[0].a[0]) -wire(Foo.I.c[1].a[2], temp.c[0].a[1]) -wire(Foo.I.c[1].a[1], temp.c[0].a[2]) -wire(Foo.I.c[1].a[0], temp.c[0].a[3]) -wire(Foo.I.c[0].a[3], temp.c[1].a[0]) -wire(Foo.I.c[0].a[2], temp.c[1].a[1]) -wire(Foo.I.c[0].a[1], temp.c[1].a[2]) -wire(Foo.I.c[0].a[0], temp.c[1].a[3]) +wire(Foo.I.c[1].a[3], Foo.O.c[0].a[0]) +wire(Foo.I.c[1].a[2], Foo.O.c[0].a[1]) +wire(Foo.I.c[1].a[1], Foo.O.c[0].a[2]) +wire(Foo.I.c[1].a[0], Foo.O.c[0].a[3]) +wire(Foo.I.c[0].a[3], Foo.O.c[1].a[0]) +wire(Foo.I.c[0].a[2], Foo.O.c[1].a[1]) +wire(Foo.I.c[0].a[1], Foo.O.c[1].a[2]) +wire(Foo.I.c[0].a[0], Foo.O.c[1].a[3]) EndCircuit()\ """ assert repr(Foo) == expected, repr(Foo) diff --git a/tests/test_type/test_clock.py b/tests/test_type/test_clock.py index 13286632c..c3ef07bf2 100644 --- a/tests/test_type/test_clock.py +++ b/tests/test_type/test_clock.py @@ -490,4 +490,4 @@ class Bar(m.Circuit): m.compile("build/Bar", Bar) - assert caplog.messages[0] == "foo.y.clk not driven, will attempt to automatically wire" + assert caplog.messages[0] == "Foo_inst0.y.clk not driven, will attempt to automatically wire" diff --git a/tests/test_type/test_const_wire_golden.json b/tests/test_type/test_const_wire_golden.json index 00304f8ff..22f4874df 100644 --- a/tests/test_type/test_const_wire_golden.json +++ b/tests/test_type/test_const_wire_golden.json @@ -16,12 +16,12 @@ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "foo_inst":{ + "foo_inst0":{ "modref":"global.foo" } }, "connections":[ - ["foo_inst.I","bit_const_0_None.out"], + ["foo_inst0.I","bit_const_0_None.out"], ["self.O","bit_const_0_None.out"] ] } diff --git a/tests/test_type/test_coreir_wrap_golden_AsyncReset.json b/tests/test_type/test_coreir_wrap_golden_AsyncReset.json index 16becb9ab..fc5a4cdaa 100644 --- a/tests/test_type/test_coreir_wrap_golden_AsyncReset.json +++ b/tests/test_type/test_coreir_wrap_golden_AsyncReset.json @@ -17,18 +17,18 @@ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "foo_inst":{ - "modref":"global.foo" - }, - "wrap":{ + "coreir_wrapBit_inst0":{ "genref":"coreir.wrap", "genargs":{"type":["CoreIRType",["Named","coreir.arst"]]} + }, + "foo_inst0":{ + "modref":"global.foo" } }, "connections":[ + ["coreir_wrapBit_inst0.in","bit_const_0_None.out"], ["self.O","bit_const_0_None.out"], - ["wrap.in","bit_const_0_None.out"], - ["wrap.out","foo_inst.r"] + ["foo_inst0.r","coreir_wrapBit_inst0.out"] ] } } diff --git a/tests/test_type/test_coreir_wrap_golden_Clock.json b/tests/test_type/test_coreir_wrap_golden_Clock.json index 127fb1a01..e626a5582 100644 --- a/tests/test_type/test_coreir_wrap_golden_Clock.json +++ b/tests/test_type/test_coreir_wrap_golden_Clock.json @@ -17,18 +17,18 @@ "modref":"corebit.const", "modargs":{"value":["Bool",false]} }, - "foo_inst":{ - "modref":"global.foo" - }, - "wrap":{ + "coreir_wrapBit_inst0":{ "genref":"coreir.wrap", "genargs":{"type":["CoreIRType",["Named","coreir.clk"]]} + }, + "foo_inst0":{ + "modref":"global.foo" } }, "connections":[ + ["coreir_wrapBit_inst0.in","bit_const_0_None.out"], ["self.O","bit_const_0_None.out"], - ["wrap.in","bit_const_0_None.out"], - ["wrap.out","foo_inst.r"] + ["foo_inst0.r","coreir_wrapBit_inst0.out"] ] } } diff --git a/tests/test_verilog/gold/Top.v b/tests/test_verilog/gold/Top.v index b4577f6c4..75ac24de1 100644 --- a/tests/test_verilog/gold/Top.v +++ b/tests/test_verilog/gold/Top.v @@ -4,22 +4,22 @@ module Top ( output O, input CLK ); -wire ff0_O; -wire ff1_O; +wire FF_inst0_O; +wire FF_inst1_O; FF #( .init(0) -) ff0 ( +) FF_inst0 ( .I(I), - .O(ff0_O), + .O(FF_inst0_O), .CLK(CLK) ); FF #( .init(1) -) ff1 ( - .I(ff0_O), - .O(ff1_O), +) FF_inst1 ( + .I(FF_inst0_O), + .O(FF_inst1_O), .CLK(CLK) ); -assign O = ff1_O; +assign O = FF_inst1_O; endmodule diff --git a/tests/test_verilog/gold/bind_test.v b/tests/test_verilog/gold/bind_test.v index 0bdda1a16..262cfaee8 100644 --- a/tests/test_verilog/gold/bind_test.v +++ b/tests/test_verilog/gold/bind_test.v @@ -77,6 +77,9 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; +bar_foo_SomeCircuit SomeCircuit_inst0 ( + .I(magma_Bits_4_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -140,9 +143,6 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); -bar_foo_SomeCircuit some_circ ( - .I(magma_Bits_4_xor_inst0_out) -); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; diff --git a/tests/test_verilog/gold/bind_uniq_test.v b/tests/test_verilog/gold/bind_uniq_test.v index 27b61373c..e43b6d3d8 100644 --- a/tests/test_verilog/gold/bind_uniq_test.v +++ b/tests/test_verilog/gold/bind_uniq_test.v @@ -115,6 +115,9 @@ wire [4:0] magma_Bits_5_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_5_inst0_O; wire temp3; +bar_foo_SomeCircuit_unq1 SomeCircuit_inst0 ( + .I(magma_Bits_5_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_5_inst0_O; assign _magma_bind_wire_1 = andr_5_inst0_O; assign _magma_bind_wire_2_0 = orr_5_inst0_O; @@ -185,9 +188,6 @@ orr_5 orr_5_inst0 ( .I(in1), .O(orr_5_inst0_O) ); -bar_foo_SomeCircuit_unq1 some_circ ( - .I(magma_Bits_5_xor_inst0_out) -); assign temp3 = andr_5_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -243,6 +243,9 @@ wire [3:0] magma_Bits_4_xor_inst0_out; wire [19:0] nested_other_circ_x_y [0:0]; wire orr_4_inst0_O; wire temp3; +bar_foo_SomeCircuit SomeCircuit_inst0 ( + .I(magma_Bits_4_xor_inst0_out) +); assign _magma_bind_wire_0 = orr_4_inst0_O; assign _magma_bind_wire_1 = andr_4_inst0_O; assign _magma_bind_wire_2_0 = orr_4_inst0_O; @@ -313,9 +316,6 @@ orr_4 orr_4_inst0 ( .I(in1), .O(orr_4_inst0_O) ); -bar_foo_SomeCircuit some_circ ( - .I(magma_Bits_4_xor_inst0_out) -); assign temp3 = andr_4_inst0_O; wire [5:0] term_inst0_in; assign term_inst0_in = {ndarr[2],ndarr[1],ndarr[0]}; @@ -343,16 +343,16 @@ endmodule module bar_foo_Main ( input CLK ); -wire RTL4_handshake_arr_0_valid; -wire RTL4_handshake_arr_1_valid; -wire RTL4_handshake_arr_2_valid; -wire RTL4_handshake_valid; -wire RTL4_out; -wire RTL5_handshake_arr_0_valid; -wire RTL5_handshake_arr_1_valid; -wire RTL5_handshake_arr_2_valid; -wire RTL5_handshake_valid; -wire RTL5_out; +wire RTL_inst0_handshake_arr_0_valid; +wire RTL_inst0_handshake_arr_1_valid; +wire RTL_inst0_handshake_arr_2_valid; +wire RTL_inst0_handshake_valid; +wire RTL_inst0_out; +wire RTL_inst1_handshake_arr_0_valid; +wire RTL_inst1_handshake_arr_1_valid; +wire RTL_inst1_handshake_arr_2_valid; +wire RTL_inst1_handshake_valid; +wire RTL_inst1_out; wire corebit_undriven_inst0_out; wire corebit_undriven_inst1_out; wire corebit_undriven_inst10_out; @@ -377,73 +377,73 @@ wire [3:0] undriven_inst0_out; wire [3:0] undriven_inst1_out; wire [4:0] undriven_inst2_out; wire [4:0] undriven_inst3_out; -wire [1:0] RTL4_ndarr [2:0]; -assign RTL4_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; -assign RTL4_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; -assign RTL4_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; -bar_foo_RTL RTL4 ( +wire [1:0] RTL_inst0_ndarr [2:0]; +assign RTL_inst0_ndarr[2] = {corebit_undriven_inst9_out,corebit_undriven_inst8_out}; +assign RTL_inst0_ndarr[1] = {corebit_undriven_inst7_out,corebit_undriven_inst6_out}; +assign RTL_inst0_ndarr[0] = {corebit_undriven_inst5_out,corebit_undriven_inst4_out}; +bar_foo_RTL RTL_inst0 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst1_out), - .handshake_arr_0_valid(RTL4_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL_inst0_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst2_out), - .handshake_arr_1_valid(RTL4_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL_inst0_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst3_out), - .handshake_arr_2_valid(RTL4_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL_inst0_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst0_out), - .handshake_valid(RTL4_handshake_valid), + .handshake_valid(RTL_inst0_handshake_valid), .in1(undriven_inst0_out), .in2(undriven_inst1_out), - .ndarr(RTL4_ndarr), - .out(RTL4_out) -); -wire [1:0] RTL5_ndarr [2:0]; -assign RTL5_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; -assign RTL5_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; -assign RTL5_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; -bar_foo_RTL_unq1 RTL5 ( + .ndarr(RTL_inst0_ndarr), + .out(RTL_inst0_out) +); +wire [1:0] RTL_inst1_ndarr [2:0]; +assign RTL_inst1_ndarr[2] = {corebit_undriven_inst19_out,corebit_undriven_inst18_out}; +assign RTL_inst1_ndarr[1] = {corebit_undriven_inst17_out,corebit_undriven_inst16_out}; +assign RTL_inst1_ndarr[0] = {corebit_undriven_inst15_out,corebit_undriven_inst14_out}; +bar_foo_RTL_unq1 RTL_inst1 ( .CLK(CLK), .handshake_arr_0_ready(corebit_undriven_inst11_out), - .handshake_arr_0_valid(RTL5_handshake_arr_0_valid), + .handshake_arr_0_valid(RTL_inst1_handshake_arr_0_valid), .handshake_arr_1_ready(corebit_undriven_inst12_out), - .handshake_arr_1_valid(RTL5_handshake_arr_1_valid), + .handshake_arr_1_valid(RTL_inst1_handshake_arr_1_valid), .handshake_arr_2_ready(corebit_undriven_inst13_out), - .handshake_arr_2_valid(RTL5_handshake_arr_2_valid), + .handshake_arr_2_valid(RTL_inst1_handshake_arr_2_valid), .handshake_ready(corebit_undriven_inst10_out), - .handshake_valid(RTL5_handshake_valid), + .handshake_valid(RTL_inst1_handshake_valid), .in1(undriven_inst2_out), .in2(undriven_inst3_out), - .ndarr(RTL5_ndarr), - .out(RTL5_out) + .ndarr(RTL_inst1_ndarr), + .out(RTL_inst1_out) ); bar_corebit_term corebit_term_inst0 ( - .in(RTL4_out) + .in(RTL_inst0_out) ); bar_corebit_term corebit_term_inst1 ( - .in(RTL4_handshake_valid) + .in(RTL_inst0_handshake_valid) ); bar_corebit_term corebit_term_inst2 ( - .in(RTL4_handshake_arr_0_valid) + .in(RTL_inst0_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst3 ( - .in(RTL4_handshake_arr_1_valid) + .in(RTL_inst0_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst4 ( - .in(RTL4_handshake_arr_2_valid) + .in(RTL_inst0_handshake_arr_2_valid) ); bar_corebit_term corebit_term_inst5 ( - .in(RTL5_out) + .in(RTL_inst1_out) ); bar_corebit_term corebit_term_inst6 ( - .in(RTL5_handshake_valid) + .in(RTL_inst1_handshake_valid) ); bar_corebit_term corebit_term_inst7 ( - .in(RTL5_handshake_arr_0_valid) + .in(RTL_inst1_handshake_arr_0_valid) ); bar_corebit_term corebit_term_inst8 ( - .in(RTL5_handshake_arr_1_valid) + .in(RTL_inst1_handshake_arr_1_valid) ); bar_corebit_term corebit_term_inst9 ( - .in(RTL5_handshake_arr_2_valid) + .in(RTL_inst1_handshake_arr_2_valid) ); bar_corebit_undriven corebit_undriven_inst0 ( .out(corebit_undriven_inst0_out) diff --git a/tests/test_verilog/gold/test_inline_tuple.json b/tests/test_verilog/gold/test_inline_tuple.json index cd73459be..b258f9a15 100644 --- a/tests/test_verilog/gold/test_inline_tuple.json +++ b/tests/test_verilog/gold/test_inline_tuple.json @@ -84,6 +84,9 @@ ["CLK",["Named","coreir.clkIn"]] ]], "instances":{ + "DelayUnit_inst0":{ + "modref":"global.DelayUnit" + }, "Main_inline_verilog_inst_0":{ "modref":"global.Main_inline_verilog_0" }, @@ -107,37 +110,34 @@ }, "_magma_inline_wire3":{ "modref":"corebit.wire" - }, - "delay":{ - "modref":"global.DelayUnit" } }, "connections":[ + ["Main_inline_verilog_inst_2.__magma_inline_value_0","DelayUnit_inst0;_magma_inline_wire4.out"], + ["Main_inline_verilog_inst_2.__magma_inline_value_1","DelayUnit_inst0;_magma_inline_wire5.out"], + ["Main_inline_verilog_inst_3.__magma_inline_value_0","DelayUnit_inst0;inner_delay;_magma_inline_wire6.out"], + ["Main_inline_verilog_inst_3.__magma_inline_value_1","DelayUnit_inst0;inner_delay;_magma_inline_wire7.out"], + ["self.CLK","DelayUnit_inst0.CLK"], + ["self.I.1.data","DelayUnit_inst0.INPUT.0.data"], + ["_magma_inline_wire3.in","DelayUnit_inst0.INPUT.0.ready"], + ["self.I.1.ready","DelayUnit_inst0.INPUT.0.ready"], + ["self.I.1.valid","DelayUnit_inst0.INPUT.0.valid"], + ["self.I.0.data","DelayUnit_inst0.INPUT.1.data"], + ["self.I.0.ready","DelayUnit_inst0.INPUT.1.ready"], + ["self.I.0.valid","DelayUnit_inst0.INPUT.1.valid"], + ["self.O.1.data","DelayUnit_inst0.OUTPUT.0.data"], + ["self.O.1.ready","DelayUnit_inst0.OUTPUT.0.ready"], + ["self.O.1.valid","DelayUnit_inst0.OUTPUT.0.valid"], + ["self.O.0.data","DelayUnit_inst0.OUTPUT.1.data"], + ["self.O.0.ready","DelayUnit_inst0.OUTPUT.1.ready"], + ["_magma_inline_wire2.in","DelayUnit_inst0.OUTPUT.1.valid"], + ["self.O.0.valid","DelayUnit_inst0.OUTPUT.1.valid"], ["_magma_inline_wire0.out","Main_inline_verilog_inst_0.__magma_inline_value_0"], ["_magma_inline_wire1.out","Main_inline_verilog_inst_0.__magma_inline_value_1"], ["_magma_inline_wire2.out","Main_inline_verilog_inst_1.__magma_inline_value_0"], ["_magma_inline_wire3.out","Main_inline_verilog_inst_1.__magma_inline_value_1"], - ["delay;_magma_inline_wire4.out","Main_inline_verilog_inst_2.__magma_inline_value_0"], - ["delay;_magma_inline_wire5.out","Main_inline_verilog_inst_2.__magma_inline_value_1"], - ["delay;inner_delay;_magma_inline_wire6.out","Main_inline_verilog_inst_3.__magma_inline_value_0"], - ["delay;inner_delay;_magma_inline_wire7.out","Main_inline_verilog_inst_3.__magma_inline_value_1"], ["self.I.0.valid","_magma_inline_wire0.in"], - ["self.O.1.ready","_magma_inline_wire1.in"], - ["delay.OUTPUT.1.valid","_magma_inline_wire2.in"], - ["delay.INPUT.0.ready","_magma_inline_wire3.in"], - ["self.CLK","delay.CLK"], - ["self.I.1.data","delay.INPUT.0.data"], - ["self.I.1.ready","delay.INPUT.0.ready"], - ["self.I.1.valid","delay.INPUT.0.valid"], - ["self.I.0.data","delay.INPUT.1.data"], - ["self.I.0.ready","delay.INPUT.1.ready"], - ["self.I.0.valid","delay.INPUT.1.valid"], - ["self.O.1.data","delay.OUTPUT.0.data"], - ["self.O.1.ready","delay.OUTPUT.0.ready"], - ["self.O.1.valid","delay.OUTPUT.0.valid"], - ["self.O.0.data","delay.OUTPUT.1.data"], - ["self.O.0.ready","delay.OUTPUT.1.ready"], - ["self.O.0.valid","delay.OUTPUT.1.valid"] + ["self.O.1.ready","_magma_inline_wire1.in"] ] }, "Main_inline_verilog_0":{ diff --git a/tests/test_verilog/gold/test_inline_tuple.mlir b/tests/test_verilog/gold/test_inline_tuple.mlir index 114215f00..bd0957331 100644 --- a/tests/test_verilog/gold/test_inline_tuple.mlir +++ b/tests/test_verilog/gold/test_inline_tuple.mlir @@ -9,17 +9,17 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { hw.output %1, %0, %4, %5, %2, %3 : i1, i1, i5, i1, i5, i1 } hw.module @Main(%I_0_data: i5, %I_0_valid: i1, %I_1_data: i5, %I_1_valid: i1, %O_0_ready: i1, %O_1_ready: i1, %CLK: i1) -> (I_0_ready: i1, I_1_ready: i1, O_0_data: i5, O_0_valid: i1, O_1_data: i5, O_1_valid: i1) { - %0, %1, %2, %3, %4, %5 = hw.instance "delay" @DelayUnit(INPUT_0_data: %I_1_data: i5, INPUT_0_valid: %I_1_valid: i1, INPUT_1_data: %I_0_data: i5, INPUT_1_valid: %I_0_valid: i1, OUTPUT_0_ready: %O_1_ready: i1, OUTPUT_1_ready: %O_0_ready: i1, CLK: %CLK: i1) -> (INPUT_0_ready: i1, INPUT_1_ready: i1, OUTPUT_0_data: i5, OUTPUT_0_valid: i1, OUTPUT_1_data: i5, OUTPUT_1_valid: i1) + %0, %1, %2, %3, %4, %5 = hw.instance "DelayUnit_inst0" @DelayUnit(INPUT_0_data: %I_1_data: i5, INPUT_0_valid: %I_1_valid: i1, INPUT_1_data: %I_0_data: i5, INPUT_1_valid: %I_0_valid: i1, OUTPUT_0_ready: %O_1_ready: i1, OUTPUT_1_ready: %O_0_ready: i1, CLK: %CLK: i1) -> (INPUT_0_ready: i1, INPUT_1_ready: i1, OUTPUT_0_data: i5, OUTPUT_0_valid: i1, OUTPUT_1_data: i5, OUTPUT_1_valid: i1) sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%I_0_valid, %O_1_ready) : i1, i1 sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%5, %0) : i1, i1 - %7 = sv.xmr "delay", "inner_delay", "OUTPUT_0_valid" : !hw.inout + %7 = sv.xmr "DelayUnit_inst0", "inner_delay", "OUTPUT_0_valid" : !hw.inout %6 = sv.read_inout %7 : !hw.inout - %9 = sv.xmr "delay", "inner_delay", "INPUT_1_ready" : !hw.inout + %9 = sv.xmr "DelayUnit_inst0", "inner_delay", "INPUT_1_ready" : !hw.inout %8 = sv.read_inout %9 : !hw.inout sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%6, %8) : i1, i1 - %11 = sv.xmr "delay", "inner_delay", "inner_inner_delay", "OUTPUT_0_valid" : !hw.inout + %11 = sv.xmr "DelayUnit_inst0", "inner_delay", "inner_inner_delay", "OUTPUT_0_valid" : !hw.inout %10 = sv.read_inout %11 : !hw.inout - %13 = sv.xmr "delay", "inner_delay", "inner_inner_delay", "INPUT_1_ready" : !hw.inout + %13 = sv.xmr "DelayUnit_inst0", "inner_delay", "inner_inner_delay", "INPUT_1_ready" : !hw.inout %12 = sv.read_inout %13 : !hw.inout sv.verbatim "assert property (@(posedge CLK) {{0}} |-> ##3 {{1}});" (%10, %12) : i1, i1 hw.output %1, %0, %4, %5, %2, %3 : i1, i1, i5, i1, i5, i1 diff --git a/tests/test_verilog/gold/test_inline_tuple.sv b/tests/test_verilog/gold/test_inline_tuple.sv index f73dfabdb..a32668959 100644 --- a/tests/test_verilog/gold/test_inline_tuple.sv +++ b/tests/test_verilog/gold/test_inline_tuple.sv @@ -95,11 +95,7 @@ wire _magma_inline_wire0; wire _magma_inline_wire1; wire _magma_inline_wire2; wire _magma_inline_wire3; -assign _magma_inline_wire0 = I_0_valid; -assign _magma_inline_wire1 = O_1_ready; -assign _magma_inline_wire2 = O_0_valid; -assign _magma_inline_wire3 = I_1_ready; -DelayUnit delay ( +DelayUnit DelayUnit_inst0 ( .CLK(CLK), .INPUT_0_data(I_1_data), .INPUT_0_ready(I_1_ready), @@ -114,9 +110,13 @@ DelayUnit delay ( .OUTPUT_1_ready(O_0_ready), .OUTPUT_1_valid(O_0_valid) ); +assign _magma_inline_wire0 = I_0_valid; +assign _magma_inline_wire1 = O_1_ready; +assign _magma_inline_wire2 = O_0_valid; +assign _magma_inline_wire3 = I_1_ready; assert property (@(posedge CLK) _magma_inline_wire0 |-> ##3 _magma_inline_wire1); assert property (@(posedge CLK) _magma_inline_wire2 |-> ##3 _magma_inline_wire3); -assert property (@(posedge CLK) delay._magma_inline_wire4.out |-> ##3 delay._magma_inline_wire5.out); -assert property (@(posedge CLK) delay.inner_delay._magma_inline_wire6.out |-> ##3 delay.inner_delay._magma_inline_wire7.out); +assert property (@(posedge CLK) DelayUnit_inst0._magma_inline_wire4.out |-> ##3 DelayUnit_inst0._magma_inline_wire5.out); +assert property (@(posedge CLK) DelayUnit_inst0.inner_delay._magma_inline_wire6.out |-> ##3 DelayUnit_inst0.inner_delay._magma_inline_wire7.out); endmodule diff --git a/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v b/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v index 533294d60..5c4bf3c30 100644 --- a/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v +++ b/tests/test_verilog/gold/test_inline_verilog_share_default_clocks.v @@ -11,41 +11,17 @@ module corebit_term ( endmodule -module WireClock ( - input I, - output O -); -wire Wire_inst0; -wire coreir_wrapInClock_inst0_out; -assign Wire_inst0 = coreir_wrapInClock_inst0_out; -coreir_wrap coreir_wrapInClock_inst0 ( - .in(I), - .out(coreir_wrapInClock_inst0_out) -); -coreir_wrap coreir_wrapOutClock_inst0 ( - .in(Wire_inst0), - .out(O) -); -endmodule - module Foo ( input x, input y, input CLK, input RESET ); -wire clk_O; -wire rst; -WireClock clk ( - .I(CLK), - .O(clk_O) -); -assign rst = RESET; -assert property (@(posedge clk_O) disable iff (! rst) x |-> ##1 y); +assert property (@(posedge CLK) disable iff (! RESET) x |-> ##1 y); -assert property (@(posedge clk_O) disable iff (! rst) x |-> ##1 y); +assert property (@(posedge CLK) disable iff (! RESET) x |-> ##1 y); endmodule diff --git a/tests/test_verilog/gold/test_pad.v b/tests/test_verilog/gold/test_pad.v index b66da2f13..e4f6a402e 100644 --- a/tests/test_verilog/gold/test_pad.v +++ b/tests/test_verilog/gold/test_pad.v @@ -10,29 +10,29 @@ endmodule module Top ( inout pad ); +wire PRWDWUWSWCDGH_V_inst0_C; +wire PRWDWUWSWCDGH_V_inst0_PAD; wire bit_const_0_None_out; -wire pad_C; -wire pad_PAD; -corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -PRWDWUWSWCDGH_V pad ( - .C(pad_C), +PRWDWUWSWCDGH_V PRWDWUWSWCDGH_V_inst0 ( + .C(PRWDWUWSWCDGH_V_inst0_C), .DS0(bit_const_0_None_out), .DS1(bit_const_0_None_out), .DS2(bit_const_0_None_out), .I(bit_const_0_None_out), .IE(bit_const_0_None_out), .OEN(bit_const_0_None_out), - .PAD(pad_PAD), + .PAD(PRWDWUWSWCDGH_V_inst0_PAD), .PU(bit_const_0_None_out), .PD(bit_const_0_None_out), .ST(bit_const_0_None_out), .SL(bit_const_0_None_out), .RTE(bit_const_0_None_out) ); -assign pad_PAD = pad; +corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +assign PRWDWUWSWCDGH_V_inst0_PAD = pad; endmodule diff --git a/tests/test_verilog/gold/test_rxmod_top.json b/tests/test_verilog/gold/test_rxmod_top.json index ca813d76b..50696bd03 100644 --- a/tests/test_verilog/gold/test_rxmod_top.json +++ b/tests/test_verilog/gold/test_rxmod_top.json @@ -19,15 +19,15 @@ ["valid","Bit"] ]], "instances":{ - "RXMOD_inst":{ + "RXMOD_inst0":{ "modref":"global.RXMOD" } }, "connections":[ - ["self.CLK","RXMOD_inst.CLK"], - ["self.RX","RXMOD_inst.RX"], - ["self.data","RXMOD_inst.data"], - ["self.valid","RXMOD_inst.valid"] + ["self.CLK","RXMOD_inst0.CLK"], + ["self.RX","RXMOD_inst0.RX"], + ["self.data","RXMOD_inst0.data"], + ["self.valid","RXMOD_inst0.valid"] ] } } diff --git a/tests/test_verilog/gold/top-declare-coreir-verilog.v b/tests/test_verilog/gold/top-declare-coreir-verilog.v index 829e1366d..58780ec4f 100644 --- a/tests/test_verilog/gold/top-declare-coreir-verilog.v +++ b/tests/test_verilog/gold/top-declare-coreir-verilog.v @@ -5,24 +5,24 @@ module Top ( input CLK, input ASYNCRESET ); -wire ff0_q; -wire ff1_q; +wire FF_inst0_q; +wire FF_inst1_q; FF #( .init(0) -) ff0 ( +) FF_inst0 ( .clk(CLK), .rst(ASYNCRESET), .d(I[0]), - .q(ff0_q) + .q(FF_inst0_q) ); FF #( .init(1) -) ff1 ( +) FF_inst1 ( .clk(CLK), .rst(ASYNCRESET), .d(I[1]), - .q(ff1_q) + .q(FF_inst1_q) ); -assign O = {ff1_q,ff0_q}; +assign O = {FF_inst1_q,FF_inst0_q}; endmodule diff --git a/tests/test_verilog/gold/top-declare-coreir.json b/tests/test_verilog/gold/top-declare-coreir.json index 37349e172..60cf73d8c 100644 --- a/tests/test_verilog/gold/top-declare-coreir.json +++ b/tests/test_verilog/gold/top-declare-coreir.json @@ -19,24 +19,24 @@ ["ASYNCRESET",["Named","coreir.arstIn"]] ]], "instances":{ - "ff0":{ + "FF_inst0":{ "modref":"global.FF", "modargs":{"init":["Int",0]} }, - "ff1":{ + "FF_inst1":{ "modref":"global.FF", "modargs":{"init":["Int",1]} } }, "connections":[ - ["self.CLK","ff0.clk"], - ["self.I.0","ff0.d"], - ["self.O.0","ff0.q"], - ["self.ASYNCRESET","ff0.rst"], - ["self.CLK","ff1.clk"], - ["self.I.1","ff1.d"], - ["self.O.1","ff1.q"], - ["self.ASYNCRESET","ff1.rst"] + ["self.CLK","FF_inst0.clk"], + ["self.I.0","FF_inst0.d"], + ["self.O.0","FF_inst0.q"], + ["self.ASYNCRESET","FF_inst0.rst"], + ["self.CLK","FF_inst1.clk"], + ["self.I.1","FF_inst1.d"], + ["self.O.1","FF_inst1.q"], + ["self.ASYNCRESET","FF_inst1.rst"] ] } } diff --git a/tests/test_verilog/gold/top-declare-verilog.v b/tests/test_verilog/gold/top-declare-verilog.v index b3fd203cb..a1a45f2d4 100644 --- a/tests/test_verilog/gold/top-declare-verilog.v +++ b/tests/test_verilog/gold/top-declare-verilog.v @@ -1,8 +1,8 @@ module Top (input [1:0] I, output [1:0] O, input CLK, input ASYNCRESET); -wire ff0_q; -wire ff1_q; -FF #(.init(0)) ff0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(ff0_q)); -FF #(.init(1)) ff1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(ff1_q)); -assign O = {ff1_q,ff0_q}; +wire FF_inst0_q; +wire FF_inst1_q; +FF #(.init(0)) FF_inst0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(FF_inst0_q)); +FF #(.init(1)) FF_inst1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(FF_inst1_q)); +assign O = {FF_inst1_q,FF_inst0_q}; endmodule diff --git a/tests/test_verilog/gold/top-define-coreir-verilog.json b/tests/test_verilog/gold/top-define-coreir-verilog.json index 82f5596a0..666561022 100644 --- a/tests/test_verilog/gold/top-define-coreir-verilog.json +++ b/tests/test_verilog/gold/top-define-coreir-verilog.json @@ -20,24 +20,24 @@ ["ASYNCRESET",["Named","coreir.arstIn"]] ]], "instances":{ - "ff0":{ + "FF_inst0":{ "modref":"global.FF", "modargs":{"init":["Int",0]} }, - "ff1":{ + "FF_inst1":{ "modref":"global.FF", "modargs":{"init":["Int",1]} } }, "connections":[ - ["self.CLK","ff0.clk"], - ["self.I.0","ff0.d"], - ["self.O.0","ff0.q"], - ["self.ASYNCRESET","ff0.rst"], - ["self.CLK","ff1.clk"], - ["self.I.1","ff1.d"], - ["self.O.1","ff1.q"], - ["self.ASYNCRESET","ff1.rst"] + ["self.CLK","FF_inst0.clk"], + ["self.I.0","FF_inst0.d"], + ["self.O.0","FF_inst0.q"], + ["self.ASYNCRESET","FF_inst0.rst"], + ["self.CLK","FF_inst1.clk"], + ["self.I.1","FF_inst1.d"], + ["self.O.1","FF_inst1.q"], + ["self.ASYNCRESET","FF_inst1.rst"] ] } } diff --git a/tests/test_verilog/gold/top-define-coreir-verilog.v b/tests/test_verilog/gold/top-define-coreir-verilog.v index 9927f702e..8ec930410 100644 --- a/tests/test_verilog/gold/top-define-coreir-verilog.v +++ b/tests/test_verilog/gold/top-define-coreir-verilog.v @@ -18,24 +18,24 @@ module Top ( input CLK, input ASYNCRESET ); -wire ff0_q; -wire ff1_q; +wire FF_inst0_q; +wire FF_inst1_q; FF #( .init(0) -) ff0 ( +) FF_inst0 ( .clk(CLK), .rst(ASYNCRESET), .d(I[0]), - .q(ff0_q) + .q(FF_inst0_q) ); FF #( .init(1) -) ff1 ( +) FF_inst1 ( .clk(CLK), .rst(ASYNCRESET), .d(I[1]), - .q(ff1_q) + .q(FF_inst1_q) ); -assign O = {ff1_q,ff0_q}; +assign O = {FF_inst1_q,FF_inst0_q}; endmodule diff --git a/tests/test_verilog/gold/top-define-coreir.json b/tests/test_verilog/gold/top-define-coreir.json index 82f5596a0..666561022 100644 --- a/tests/test_verilog/gold/top-define-coreir.json +++ b/tests/test_verilog/gold/top-define-coreir.json @@ -20,24 +20,24 @@ ["ASYNCRESET",["Named","coreir.arstIn"]] ]], "instances":{ - "ff0":{ + "FF_inst0":{ "modref":"global.FF", "modargs":{"init":["Int",0]} }, - "ff1":{ + "FF_inst1":{ "modref":"global.FF", "modargs":{"init":["Int",1]} } }, "connections":[ - ["self.CLK","ff0.clk"], - ["self.I.0","ff0.d"], - ["self.O.0","ff0.q"], - ["self.ASYNCRESET","ff0.rst"], - ["self.CLK","ff1.clk"], - ["self.I.1","ff1.d"], - ["self.O.1","ff1.q"], - ["self.ASYNCRESET","ff1.rst"] + ["self.CLK","FF_inst0.clk"], + ["self.I.0","FF_inst0.d"], + ["self.O.0","FF_inst0.q"], + ["self.ASYNCRESET","FF_inst0.rst"], + ["self.CLK","FF_inst1.clk"], + ["self.I.1","FF_inst1.d"], + ["self.O.1","FF_inst1.q"], + ["self.ASYNCRESET","FF_inst1.rst"] ] } } diff --git a/tests/test_verilog/gold/top-define-verilog.v b/tests/test_verilog/gold/top-define-verilog.v index 7711cc225..6f149ccf2 100644 --- a/tests/test_verilog/gold/top-define-verilog.v +++ b/tests/test_verilog/gold/top-define-verilog.v @@ -13,10 +13,10 @@ end assign q = ff; endmodule module Top (input [1:0] I, output [1:0] O, input CLK, input ASYNCRESET); -wire ff0_q; -wire ff1_q; -FF #(.init(0)) ff0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(ff0_q)); -FF #(.init(1)) ff1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(ff1_q)); -assign O = {ff1_q,ff0_q}; +wire FF_inst0_q; +wire FF_inst1_q; +FF #(.init(0)) FF_inst0 (.clk(CLK), .rst(ASYNCRESET), .d(I[0]), .q(FF_inst0_q)); +FF #(.init(1)) FF_inst1 (.clk(CLK), .rst(ASYNCRESET), .d(I[1]), .q(FF_inst1_q)); +assign O = {FF_inst1_q,FF_inst0_q}; endmodule diff --git a/tests/test_wire/gold/arg1.v b/tests/test_wire/gold/arg1.v index e822d65af..6e284cc40 100644 --- a/tests/test_wire/gold/arg1.v +++ b/tests/test_wire/gold/arg1.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire buf_O; -Buf buf (.I(I), .O(buf_O)); -assign O = buf_O; +wire Buf_inst0_O; +Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/arg2.v b/tests/test_wire/gold/arg2.v index d60c51b3d..313319687 100644 --- a/tests/test_wire/gold/arg2.v +++ b/tests/test_wire/gold/arg2.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire a_O; -And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); -assign O = a_O; +wire And2_inst0_O; +And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_wire/gold/array1.v b/tests/test_wire/gold/array1.v index a70b46989..3d7d9c6e9 100644 --- a/tests/test_wire/gold/array1.v +++ b/tests/test_wire/gold/array1.v @@ -1,6 +1,6 @@ module main (output O); -wire a_O; -AndN2 a (.I(2'd2'), .O(a_O)); -assign O = a_O; +wire AndN2_inst0_O; +AndN2 AndN2_inst0 (.I(2'd2'), .O(AndN2_inst0_O)); +assign O = AndN2_inst0_O; endmodule diff --git a/tests/test_wire/gold/array2.v b/tests/test_wire/gold/array2.v index 580c8faab..c5c2c43e3 100644 --- a/tests/test_wire/gold/array2.v +++ b/tests/test_wire/gold/array2.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire a_O; -AndN2 a (.I({1'b1,I}), .O(a_O)); -assign O = a_O; +wire AndN2_inst0_O; +AndN2 AndN2_inst0 (.I({1'b1,I}), .O(AndN2_inst0_O)); +assign O = AndN2_inst0_O; endmodule diff --git a/tests/test_wire/gold/array3.v b/tests/test_wire/gold/array3.v index 883a26712..39561f7c1 100644 --- a/tests/test_wire/gold/array3.v +++ b/tests/test_wire/gold/array3.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire a_O; -AndN2 a (.I(I), .O(a_O)); -assign O = a_O; +wire AndN2_inst0_O; +AndN2 AndN2_inst0 (.I(I), .O(AndN2_inst0_O)); +assign O = AndN2_inst0_O; endmodule diff --git a/tests/test_wire/gold/call1.v b/tests/test_wire/gold/call1.v index 1d3827732..f0fc76a4f 100644 --- a/tests/test_wire/gold/call1.v +++ b/tests/test_wire/gold/call1.v @@ -1,6 +1,6 @@ module main (input I0, input I1, output O); -wire a_O; -And2 a (.I0(I0), .I1(I1), .O(a_O)); -assign O = a_O; +wire And2_inst0_O; +And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_wire/gold/call2.v b/tests/test_wire/gold/call2.v index 883a26712..39561f7c1 100644 --- a/tests/test_wire/gold/call2.v +++ b/tests/test_wire/gold/call2.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire a_O; -AndN2 a (.I(I), .O(a_O)); -assign O = a_O; +wire AndN2_inst0_O; +AndN2 AndN2_inst0 (.I(I), .O(AndN2_inst0_O)); +assign O = AndN2_inst0_O; endmodule diff --git a/tests/test_wire/gold/compose.v b/tests/test_wire/gold/compose.v index 55e337026..f7ea820c8 100644 --- a/tests/test_wire/gold/compose.v +++ b/tests/test_wire/gold/compose.v @@ -1,8 +1,8 @@ module main (input I, output O); -wire buf1_O; -wire buf2_O; -Buf buf1 (.I(I), .O(buf1_O)); -Buf buf2 (.I(buf1_O), .O(buf2_O)); -assign O = buf2_O; +wire Buf_inst0_O; +wire Buf_inst1_O; +Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); +Buf Buf_inst1 (.I(Buf_inst0_O), .O(Buf_inst1_O)); +assign O = Buf_inst1_O; endmodule diff --git a/tests/test_wire/gold/const0.v b/tests/test_wire/gold/const0.v index 5fc945e12..2cee40ff4 100644 --- a/tests/test_wire/gold/const0.v +++ b/tests/test_wire/gold/const0.v @@ -10,17 +10,17 @@ endmodule module main ( output O ); +wire Buf_inst0_O; wire bit_const_0_None_out; -wire buf_O; +Buf Buf_inst0 ( + .I(bit_const_0_None_out), + .O(Buf_inst0_O) +); corebit_const #( .value(1'b0) ) bit_const_0_None ( .out(bit_const_0_None_out) ); -Buf buf ( - .I(bit_const_0_None_out), - .O(buf_O) -); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const1.v b/tests/test_wire/gold/const1.v index 684e4acb8..e2620020e 100644 --- a/tests/test_wire/gold/const1.v +++ b/tests/test_wire/gold/const1.v @@ -10,17 +10,17 @@ endmodule module main ( output O ); +wire Buf_inst0_O; wire bit_const_1_None_out; -wire buf_O; +Buf Buf_inst0 ( + .I(bit_const_1_None_out), + .O(Buf_inst0_O) +); corebit_const #( .value(1'b1) ) bit_const_1_None ( .out(bit_const_1_None_out) ); -Buf buf ( - .I(bit_const_1_None_out), - .O(buf_O) -); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_Bits_1.v b/tests/test_wire/gold/const_bits_Bits_1.v index 834a0d74b..43529ec03 100644 --- a/tests/test_wire/gold/const_bits_Bits_1.v +++ b/tests/test_wire/gold/const_bits_Bits_1.v @@ -11,11 +11,11 @@ endmodule module main ( output [0:0] O ); -wire [0:0] buf_O; +wire [0:0] Buf_inst0_O; wire [0:0] const_1_1_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_1_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(1'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_1 ( .out(const_1_1_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_Bits_2.v b/tests/test_wire/gold/const_bits_Bits_2.v index 2a674cbbc..3d20c257d 100644 --- a/tests/test_wire/gold/const_bits_Bits_2.v +++ b/tests/test_wire/gold/const_bits_Bits_2.v @@ -11,11 +11,11 @@ endmodule module main ( output [1:0] O ); -wire [1:0] buf_O; +wire [1:0] Buf_inst0_O; wire [1:0] const_1_2_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_2_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(2'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_2 ( .out(const_1_2_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_Bits_3.v b/tests/test_wire/gold/const_bits_Bits_3.v index 553febf62..58d89acdc 100644 --- a/tests/test_wire/gold/const_bits_Bits_3.v +++ b/tests/test_wire/gold/const_bits_Bits_3.v @@ -11,11 +11,11 @@ endmodule module main ( output [2:0] O ); -wire [2:0] buf_O; +wire [2:0] Buf_inst0_O; wire [2:0] const_1_3_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_3_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(3'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_3 ( .out(const_1_3_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_SInt_1.v b/tests/test_wire/gold/const_bits_SInt_1.v index 834a0d74b..43529ec03 100644 --- a/tests/test_wire/gold/const_bits_SInt_1.v +++ b/tests/test_wire/gold/const_bits_SInt_1.v @@ -11,11 +11,11 @@ endmodule module main ( output [0:0] O ); -wire [0:0] buf_O; +wire [0:0] Buf_inst0_O; wire [0:0] const_1_1_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_1_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(1'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_1 ( .out(const_1_1_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_SInt_2.v b/tests/test_wire/gold/const_bits_SInt_2.v index 2a674cbbc..3d20c257d 100644 --- a/tests/test_wire/gold/const_bits_SInt_2.v +++ b/tests/test_wire/gold/const_bits_SInt_2.v @@ -11,11 +11,11 @@ endmodule module main ( output [1:0] O ); -wire [1:0] buf_O; +wire [1:0] Buf_inst0_O; wire [1:0] const_1_2_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_2_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(2'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_2 ( .out(const_1_2_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_SInt_3.v b/tests/test_wire/gold/const_bits_SInt_3.v index 553febf62..58d89acdc 100644 --- a/tests/test_wire/gold/const_bits_SInt_3.v +++ b/tests/test_wire/gold/const_bits_SInt_3.v @@ -11,11 +11,11 @@ endmodule module main ( output [2:0] O ); -wire [2:0] buf_O; +wire [2:0] Buf_inst0_O; wire [2:0] const_1_3_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_3_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(3'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_3 ( .out(const_1_3_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_UInt_1.v b/tests/test_wire/gold/const_bits_UInt_1.v index 834a0d74b..43529ec03 100644 --- a/tests/test_wire/gold/const_bits_UInt_1.v +++ b/tests/test_wire/gold/const_bits_UInt_1.v @@ -11,11 +11,11 @@ endmodule module main ( output [0:0] O ); -wire [0:0] buf_O; +wire [0:0] Buf_inst0_O; wire [0:0] const_1_1_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_1_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(1'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_1 ( .out(const_1_1_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_UInt_2.v b/tests/test_wire/gold/const_bits_UInt_2.v index 2a674cbbc..3d20c257d 100644 --- a/tests/test_wire/gold/const_bits_UInt_2.v +++ b/tests/test_wire/gold/const_bits_UInt_2.v @@ -11,11 +11,11 @@ endmodule module main ( output [1:0] O ); -wire [1:0] buf_O; +wire [1:0] Buf_inst0_O; wire [1:0] const_1_2_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_2_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(2'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_2 ( .out(const_1_2_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/const_bits_UInt_3.v b/tests/test_wire/gold/const_bits_UInt_3.v index 553febf62..58d89acdc 100644 --- a/tests/test_wire/gold/const_bits_UInt_3.v +++ b/tests/test_wire/gold/const_bits_UInt_3.v @@ -11,11 +11,11 @@ endmodule module main ( output [2:0] O ); -wire [2:0] buf_O; +wire [2:0] Buf_inst0_O; wire [2:0] const_1_3_out; -Buf buf ( +Buf Buf_inst0 ( .I(const_1_3_out), - .O(buf_O) + .O(Buf_inst0_O) ); coreir_const #( .value(3'h1), @@ -23,6 +23,6 @@ coreir_const #( ) const_1_3 ( .out(const_1_3_out) ); -assign O = \buf _O; +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/flip.v b/tests/test_wire/gold/flip.v index d3656aafc..d6d13c39b 100644 --- a/tests/test_wire/gold/flip.v +++ b/tests/test_wire/gold/flip.v @@ -1,6 +1,6 @@ module main (output O); -wire buf_O; -Buf buf (.I(1'b1), .O(buf_O)); -assign O = buf_O; +wire Buf_inst0_O; +Buf Buf_inst0 (.I(1'b1), .O(Buf_inst0_O)); +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/named1.v b/tests/test_wire/gold/named1.v index e822d65af..6e284cc40 100644 --- a/tests/test_wire/gold/named1.v +++ b/tests/test_wire/gold/named1.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire buf_O; -Buf buf (.I(I), .O(buf_O)); -assign O = buf_O; +wire Buf_inst0_O; +Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/gold/named2a.v b/tests/test_wire/gold/named2a.v index d60c51b3d..313319687 100644 --- a/tests/test_wire/gold/named2a.v +++ b/tests/test_wire/gold/named2a.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire a_O; -And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); -assign O = a_O; +wire And2_inst0_O; +And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_wire/gold/named2b.v b/tests/test_wire/gold/named2b.v index d60c51b3d..313319687 100644 --- a/tests/test_wire/gold/named2b.v +++ b/tests/test_wire/gold/named2b.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire a_O; -And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); -assign O = a_O; +wire And2_inst0_O; +And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_wire/gold/named2c.v b/tests/test_wire/gold/named2c.v index d60c51b3d..313319687 100644 --- a/tests/test_wire/gold/named2c.v +++ b/tests/test_wire/gold/named2c.v @@ -1,6 +1,6 @@ module main (input [1:0] I, output O); -wire a_O; -And2 a (.I0(I[0]), .I1(I[1]), .O(a_O)); -assign O = a_O; +wire And2_inst0_O; +And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O)); +assign O = And2_inst0_O; endmodule diff --git a/tests/test_wire/gold/pos.v b/tests/test_wire/gold/pos.v index e822d65af..6e284cc40 100644 --- a/tests/test_wire/gold/pos.v +++ b/tests/test_wire/gold/pos.v @@ -1,6 +1,6 @@ module main (input I, output O); -wire buf_O; -Buf buf (.I(I), .O(buf_O)); -assign O = buf_O; +wire Buf_inst0_O; +Buf Buf_inst0 (.I(I), .O(Buf_inst0_O)); +assign O = Buf_inst0_O; endmodule diff --git a/tests/test_wire/test_check_wiring_context.py b/tests/test_wire/test_check_wiring_context.py index 244c6e9ee..db29e7893 100644 --- a/tests/test_wire/test_check_wiring_context.py +++ b/tests/test_wire/test_check_wiring_context.py @@ -43,8 +43,8 @@ class Bar(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Bar", Bar) - assert str(e.value) == ("Cannot wire Foo.x to Bar._z.in because they are " - "not from the same definition context") + assert str(e.value) == ("Cannot wire Foo.x to Bar.y because they are not " + "from the same definition context") def test_bad_temp2(caplog): @@ -61,8 +61,8 @@ class Bar(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Foo", Foo) - assert str(e.value) == ("Cannot wire Bar.x to Foo.z.in because they are " - "not from the same definition context") + assert str(e.value) == ("Cannot wire Bar.x to Foo.y because they are not " + "from the same definition context") def test_bad_portview(caplog): @@ -87,7 +87,7 @@ class Biz(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Foo", Biz) - assert str(e.value) == ("Cannot wire bar.foo.y to Biz.y because they " + assert str(e.value) == ("Cannot wire Bar.Foo_inst0.y to Biz.y because they " "are not from the same definition context") @@ -109,7 +109,7 @@ class Baz(m.Circuit): with pytest.raises(MagmaCompileException) as e: m.compile("build/Bar", Bar) - assert str(e.value) == ("Cannot wire Baz.bar.y to Bar.foo.x " + assert str(e.value) == ("Cannot wire Baz.Bar_inst0.y to Bar.Foo_inst0.x " "because they are not from the same definition " "context") From d0812ebe3f929dd6cb01e044d641900c47a6e8a8 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 15 Dec 2022 12:56:21 -0800 Subject: [PATCH 43/61] Add namer dict tests --- tests/gold/test_basic_namer_dict.mlir | 10 +++ tests/gold/test_namer_dict_already_named.mlir | 10 +++ tests/gold/test_namer_dict_multiple.mlir | 14 +++ tests/gold/test_namer_dict_smart_bits.mlir | 29 +++++++ tests/test_namer_dict.py | 85 +++++++++++++++++++ 5 files changed, 148 insertions(+) create mode 100644 tests/gold/test_basic_namer_dict.mlir create mode 100644 tests/gold/test_namer_dict_already_named.mlir create mode 100644 tests/gold/test_namer_dict_multiple.mlir create mode 100644 tests/gold/test_namer_dict_smart_bits.mlir create mode 100644 tests/test_namer_dict.py diff --git a/tests/gold/test_basic_namer_dict.mlir b/tests/gold/test_basic_namer_dict.mlir new file mode 100644 index 000000000..96eaeaa2e --- /dev/null +++ b/tests/gold/test_basic_namer_dict.mlir @@ -0,0 +1,10 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module.extern @Foo(%I: i8) -> (O: i8) + hw.module @test_basic_namer_dict(%I: i8) -> (O: i8) { + %1 = sv.wire sym @test_basic_namer_dict.x {name="x"} : !hw.inout + sv.assign %1, %I : i8 + %0 = sv.read_inout %1 : !hw.inout + %2 = hw.instance "foo" @Foo(I: %0: i8) -> (O: i8) + hw.output %2 : i8 + } +} diff --git a/tests/gold/test_namer_dict_already_named.mlir b/tests/gold/test_namer_dict_already_named.mlir new file mode 100644 index 000000000..1d7a17885 --- /dev/null +++ b/tests/gold/test_namer_dict_already_named.mlir @@ -0,0 +1,10 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module.extern @Foo(%I: i8) -> (O: i8) + hw.module @test_namer_dict_already_named(%I: i8) -> (O: i8) { + %1 = sv.wire sym @test_namer_dict_already_named.y {name="y"} : !hw.inout + sv.assign %1, %I : i8 + %0 = sv.read_inout %1 : !hw.inout + %2 = hw.instance "bar" @Foo(I: %0: i8) -> (O: i8) + hw.output %2 : i8 + } +} diff --git a/tests/gold/test_namer_dict_multiple.mlir b/tests/gold/test_namer_dict_multiple.mlir new file mode 100644 index 000000000..03de17847 --- /dev/null +++ b/tests/gold/test_namer_dict_multiple.mlir @@ -0,0 +1,14 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module.extern @Foo(%I: i8) -> (O: i8) + hw.module @test_namer_dict_multiple(%I: i8) -> (O: i8) { + %1 = sv.wire sym @test_namer_dict_multiple.x_0 {name="x_0"} : !hw.inout + sv.assign %1, %I : i8 + %0 = sv.read_inout %1 : !hw.inout + %2 = hw.instance "foo_0" @Foo(I: %0: i8) -> (O: i8) + %4 = sv.wire sym @test_namer_dict_multiple.x_1 {name="x_1"} : !hw.inout + sv.assign %4, %2 : i8 + %3 = sv.read_inout %4 : !hw.inout + %5 = hw.instance "foo_1" @Foo(I: %3: i8) -> (O: i8) + hw.output %5 : i8 + } +} diff --git a/tests/gold/test_namer_dict_smart_bits.mlir b/tests/gold/test_namer_dict_smart_bits.mlir new file mode 100644 index 000000000..7d48919a3 --- /dev/null +++ b/tests/gold/test_namer_dict_smart_bits.mlir @@ -0,0 +1,29 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module @test_namer_dict_smart_bits(%I0: i8, %I1: i8) -> (O: i9) { + %0 = comb.extract %I0 from 0 : (i8) -> i1 + %1 = comb.extract %I0 from 1 : (i8) -> i1 + %2 = comb.extract %I0 from 2 : (i8) -> i1 + %3 = comb.extract %I0 from 3 : (i8) -> i1 + %4 = comb.extract %I0 from 4 : (i8) -> i1 + %5 = comb.extract %I0 from 5 : (i8) -> i1 + %6 = comb.extract %I0 from 6 : (i8) -> i1 + %7 = comb.extract %I0 from 7 : (i8) -> i1 + %8 = hw.constant 0 : i1 + %9 = comb.concat %8, %7, %6, %5, %4, %3, %2, %1, %0 : i1, i1, i1, i1, i1, i1, i1, i1, i1 + %10 = comb.extract %I1 from 0 : (i8) -> i1 + %11 = comb.extract %I1 from 1 : (i8) -> i1 + %12 = comb.extract %I1 from 2 : (i8) -> i1 + %13 = comb.extract %I1 from 3 : (i8) -> i1 + %14 = comb.extract %I1 from 4 : (i8) -> i1 + %15 = comb.extract %I1 from 5 : (i8) -> i1 + %16 = comb.extract %I1 from 6 : (i8) -> i1 + %17 = comb.extract %I1 from 7 : (i8) -> i1 + %18 = hw.constant 0 : i1 + %19 = comb.concat %18, %17, %16, %15, %14, %13, %12, %11, %10 : i1, i1, i1, i1, i1, i1, i1, i1, i1 + %20 = comb.add %9, %19 : i9 + %22 = sv.wire sym @test_namer_dict_smart_bits.x {name="x"} : !hw.inout + sv.assign %22, %20 : i9 + %21 = sv.read_inout %22 : !hw.inout + hw.output %21 : i9 + } +} diff --git a/tests/test_namer_dict.py b/tests/test_namer_dict.py new file mode 100644 index 000000000..98baa0cd8 --- /dev/null +++ b/tests/test_namer_dict.py @@ -0,0 +1,85 @@ +import pytest +import magma as m +from magma.config import config +from magma.testing.utils import check_gold + + +@pytest.fixture(autouse=True) +def use_namer_dict(): + config.use_namer_dict = True + yield + config.use_namer_dict = False + + +def test_basic_namer_dict(): + + class Foo(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + + class test_basic_namer_dict(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + foo = Foo() + assert foo.name == "foo" + x = m.Bits[8]() + assert x.name.name == "x" + x @= io.I + io.O @= foo(x) + + m.compile("build/test_basic_namer_dict", test_basic_namer_dict, + output="mlir") + assert check_gold(__file__, f"test_basic_namer_dict.mlir") + + +def test_namer_dict_multiple(): + + class Foo(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + + class test_namer_dict_multiple(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + foo = Foo() + x = m.Bits[8]() + x @= io.I + y = foo(x) + foo = Foo() + x = m.Bits[8]() + x @= y + io.O @= foo(x) + + m.compile("build/test_namer_dict_multiple", test_namer_dict_multiple, + output="mlir") + assert check_gold(__file__, f"test_namer_dict_multiple.mlir") + + +def test_namer_dict_smart_bits(): + + class test_namer_dict_smart_bits(m.Circuit): + io = m.IO(I0=m.In(m.smart.SmartBits[8]), + I1=m.In(m.smart.SmartBits[8]), + O=m.Out(m.smart.SmartBits[9])) + x = m.smart.SmartBits[9]() + x @= io.I0 + io.I1 + io.O @= x + + m.compile("build/test_namer_dict_smart_bits", test_namer_dict_smart_bits, + output="mlir") + assert check_gold(__file__, f"test_namer_dict_smart_bits.mlir") + + +def test_namer_dict_already_named(): + + class Foo(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + + class test_namer_dict_already_named(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + foo = Foo(name="bar") + assert foo.name == "bar" + x = m.Bits[8](name="y") + assert x.name.name == "y" + x @= io.I + io.O @= foo(x) + + m.compile("build/test_namer_dict_already_named", + test_namer_dict_already_named, output="mlir") + assert check_gold(__file__, f"test_namer_dict_already_named.mlir") From e4b0226fb9f59b119d85b0bb08fe4fcfc0833244 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 15 Dec 2022 12:58:37 -0800 Subject: [PATCH 44/61] Add generator test --- tests/gold/test_namer_dict_generator.mlir | 8 ++++++++ tests/test_namer_dict.py | 13 +++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 tests/gold/test_namer_dict_generator.mlir diff --git a/tests/gold/test_namer_dict_generator.mlir b/tests/gold/test_namer_dict_generator.mlir new file mode 100644 index 000000000..768331716 --- /dev/null +++ b/tests/gold/test_namer_dict_generator.mlir @@ -0,0 +1,8 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module @Foo(%I: i8) -> (O: i8) { + %1 = sv.wire sym @Foo.x {name="x"} : !hw.inout + sv.assign %1, %I : i8 + %0 = sv.read_inout %1 : !hw.inout + hw.output %0 : i8 + } +} diff --git a/tests/test_namer_dict.py b/tests/test_namer_dict.py index 98baa0cd8..32d561a8a 100644 --- a/tests/test_namer_dict.py +++ b/tests/test_namer_dict.py @@ -83,3 +83,16 @@ class test_namer_dict_already_named(m.Circuit): m.compile("build/test_namer_dict_already_named", test_namer_dict_already_named, output="mlir") assert check_gold(__file__, f"test_namer_dict_already_named.mlir") + + +def test_namer_dict_generator(): + + class Foo(m.Generator2): + def __init__(self, n): + self.io = m.IO(I=m.In(m.Bits[n]), O=m.Out(m.Bits[n])) + self.x = m.Bits[n]() + self.x @= self.io.I + self.io.O @= self.x + + m.compile("build/test_namer_dict_generator", Foo(8), output="mlir") + assert check_gold(__file__, f"test_namer_dict_generator.mlir") From 8b96d189320852c4edb3517a500d119b3887d76b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 15 Dec 2022 14:01:31 -0800 Subject: [PATCH 45/61] Add collision logic --- magma/circuit.py | 27 +++++++++++++++++++++++++-- tests/test_namer_dict.py | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 814f94cef..82f30975a 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -227,6 +227,7 @@ def __setitem__(self, key, value): # SmartExpr doesn't have a magma_value # TODO: This probably shouldn't be a protocol type then pass + # TODO: Refactor shared code between these cases if ( (isinstance(value, Type) and hasattr(value, "name") and isinstance(value.name, AnonRef)) or @@ -241,8 +242,30 @@ def __setitem__(self, key, value): self._set_name(f"{key}_0", values[0]) self._set_name(f"{key}_{len(values)}", value) values.append(value) - # TODO: Should we handle name collisions between explicitly named values - # and inferred names? + elif isinstance(type(value), CircuitKind): + values = self._inferred_names.setdefault(value.name, []) + if len(values) == 0: + pass + else: + if len(values) == 1: + self._set_name(f"{value.name}_0", values[0]) + self._set_name(f"{value.name}_{len(values)}", value) + values.append(value) + elif ( + isinstance(value, Type) and + hasattr(value, "name") and + isinstance(value.name, TempNamedRef) + ): + values = self._inferred_names.setdefault(value.name.name, []) + if len(values) == 0: + values.append(value) + elif len(values) == 1 and values[0] is value: + pass + else: + if len(values) == 1: + self._set_name(f"{value.name.name}_0", values[0]) + self._set_name(f"{value.name.name}_{len(values)}", value) + values.append(value) super().__setitem__(key, orig_value) diff --git a/tests/test_namer_dict.py b/tests/test_namer_dict.py index 32d561a8a..7ae10bc0d 100644 --- a/tests/test_namer_dict.py +++ b/tests/test_namer_dict.py @@ -96,3 +96,38 @@ def __init__(self, n): m.compile("build/test_namer_dict_generator", Foo(8), output="mlir") assert check_gold(__file__, f"test_namer_dict_generator.mlir") + + +def test_namer_dict_explicit_collision_inst(): + + class Foo(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + + class test_namer_dict_explicit_collision_inst(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + x = Foo(name="foo") + foo = Foo() + io.O @= foo(x(io.I)) + + m.compile("build/test_namer_dict_explicit_collision_inst", + test_namer_dict_explicit_collision_inst, output="mlir") + assert check_gold(__file__, f"test_namer_dict_explicit_collision_inst.mlir") + + +def test_namer_dict_explicit_collision_value(): + + class Foo(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + + class test_namer_dict_explicit_collision_value(m.Circuit): + io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + x = m.Bits[8](name="y") + x @= io.I + y = m.Bits[8]() + y @= x + io.O @= y + + m.compile("build/test_namer_dict_explicit_collision_value", + test_namer_dict_explicit_collision_value, output="mlir") + assert check_gold(__file__, + f"test_namer_dict_explicit_collision_value.mlir") From 411205b37df1c7550c19b3bc9b4fc8ccc235893f Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 15 Dec 2022 14:01:44 -0800 Subject: [PATCH 46/61] Update comment --- magma/circuit.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 82f30975a..787e79357 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -224,8 +224,7 @@ def __setitem__(self, key, value): try: value = magma_value(value) except NotImplementedError: - # SmartExpr doesn't have a magma_value - # TODO: This probably shouldn't be a protocol type then + # SmartExpr doesn't have a magma_value yet pass # TODO: Refactor shared code between these cases if ( From 397baf6b03ea1458234d5ebdc7b125c792f4d892 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 15 Dec 2022 14:20:46 -0800 Subject: [PATCH 47/61] Add missing gold files --- .../gold/test_namer_dict_explicit_collision_inst.mlir | 8 ++++++++ .../test_namer_dict_explicit_collision_value.mlir | 11 +++++++++++ 2 files changed, 19 insertions(+) create mode 100644 tests/gold/test_namer_dict_explicit_collision_inst.mlir create mode 100644 tests/gold/test_namer_dict_explicit_collision_value.mlir diff --git a/tests/gold/test_namer_dict_explicit_collision_inst.mlir b/tests/gold/test_namer_dict_explicit_collision_inst.mlir new file mode 100644 index 000000000..577f1b62b --- /dev/null +++ b/tests/gold/test_namer_dict_explicit_collision_inst.mlir @@ -0,0 +1,8 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module.extern @Foo(%I: i8) -> (O: i8) + hw.module @test_namer_dict_explicit_collision_inst(%I: i8) -> (O: i8) { + %0 = hw.instance "foo_0" @Foo(I: %I: i8) -> (O: i8) + %1 = hw.instance "foo_1" @Foo(I: %0: i8) -> (O: i8) + hw.output %1 : i8 + } +} diff --git a/tests/gold/test_namer_dict_explicit_collision_value.mlir b/tests/gold/test_namer_dict_explicit_collision_value.mlir new file mode 100644 index 000000000..81e96e62e --- /dev/null +++ b/tests/gold/test_namer_dict_explicit_collision_value.mlir @@ -0,0 +1,11 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module @test_namer_dict_explicit_collision_value(%I: i8) -> (O: i8) { + %1 = sv.wire sym @test_namer_dict_explicit_collision_value.y_0 {name="y_0"} : !hw.inout + sv.assign %1, %I : i8 + %0 = sv.read_inout %1 : !hw.inout + %3 = sv.wire sym @test_namer_dict_explicit_collision_value.y_1 {name="y_1"} : !hw.inout + sv.assign %3, %0 : i8 + %2 = sv.read_inout %3 : !hw.inout + hw.output %2 : i8 + } +} From 3295e3ebd8cfaf65dcc635d5136c203dc62b8d63 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:32:52 -0800 Subject: [PATCH 48/61] Refactor --- magma/circuit.py | 98 ++++++++++--------- .../gold/test_namer_dict_smart_bits_lazy.mlir | 26 +++++ tests/test_namer_dict.py | 30 ++++++ 3 files changed, 110 insertions(+), 44 deletions(-) create mode 100644 tests/gold/test_namer_dict_smart_bits_lazy.mlir diff --git a/magma/circuit.py b/magma/circuit.py index 787e79357..8c9d06e29 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -8,7 +8,7 @@ import operator from collections import namedtuple, Counter import os -from typing import Callable, Dict, List +from typing import Callable, Dict, List, Union from . import cache_definition from .common import deprecated, setattrs, OrderedIdentitySet @@ -218,55 +218,65 @@ def _set_name(self, key, value): key = TempNamedRef(key, value) value.name = key + def _check_unique_name( + self, + key: str, + value: Union[Type, LazyNamedValue, 'Circuit'], + ): + """If key has been seen more than once, "uniquify" the names by append + _{i} to them. + """ + values = self._inferred_names.setdefault(key, []) + if len(values) == 0: + self._set_name(key, value) + elif any(value is x for x in values): + # Already uniquified + return + else: + if len(values) == 1: + # Make the first value consistent by append _0 + self._set_name(f"{key}_0", values[0]) + self._set_name(f"{key}_{len(values)}", value) + values.append(value) + + def _set_value_name(self, key: str, value: Type): + if not hasattr(value, "name"): + # Interface object is a Type without a name + return + if isinstance(value.name, AnonRef): + self._check_unique_name(key, value) + elif isinstance(value.name, TempNamedRef): + self._check_unique_name(value.name.name, value) + + def _set_lazy_value_or_inst_name( + self, + key: str, + value: Union[LazyNamedValue, 'Circuit'] + ): + if not value.name: + self._check_unique_name(key, value) + else: + # We do not expect a LazyNamedValue (SmartExpr) to be given an + # explicit name (since it can only be constructed by forming an + # anonymous expression). + assert not isinstance(value, LazyNamedValue) + self._check_unique_name(value.name, value) + def __setitem__(self, key, value): - orig_value = value + super().__setitem__(key, value) if isinstance(value, LazyNamedValue): try: value = magma_value(value) except NotImplementedError: - # SmartExpr doesn't have a magma_value yet - pass - # TODO: Refactor shared code between these cases - if ( - (isinstance(value, Type) and hasattr(value, "name") and - isinstance(value.name, AnonRef)) or - (isinstance(value, LazyNamedValue) and not value.name) or - (isinstance(type(value), CircuitKind) and not value.name) - ): - values = self._inferred_names.setdefault(key, []) - if len(values) == 0: - self._set_name(key, value) - else: - if len(values) == 1: - self._set_name(f"{key}_0", values[0]) - self._set_name(f"{key}_{len(values)}", value) - values.append(value) + pass # SmartExpr doesn't have a magma_value yet + if isinstance(value, Type): + self._set_value_name(key, value) + elif isinstance(value, LazyNamedValue): + self._set_lazy_value_or_inst_name(key, value) elif isinstance(type(value), CircuitKind): - values = self._inferred_names.setdefault(value.name, []) - if len(values) == 0: - pass - else: - if len(values) == 1: - self._set_name(f"{value.name}_0", values[0]) - self._set_name(f"{value.name}_{len(values)}", value) - values.append(value) - elif ( - isinstance(value, Type) and - hasattr(value, "name") and - isinstance(value.name, TempNamedRef) - ): - values = self._inferred_names.setdefault(value.name.name, []) - if len(values) == 0: - values.append(value) - elif len(values) == 1 and values[0] is value: - pass - else: - if len(values) == 1: - self._set_name(f"{value.name.name}_0", values[0]) - self._set_name(f"{value.name.name}_{len(values)}", value) - values.append(value) - - super().__setitem__(key, orig_value) + # NOTE: we check type(value) because this code is run in the Circuit + # class creation pipeline (so Circuit may not be defined yet). + self._set_lazy_value_or_inst_name(key, value) def __hash__(self): return hash(tuple(sorted(self.items()))) diff --git a/tests/gold/test_namer_dict_smart_bits_lazy.mlir b/tests/gold/test_namer_dict_smart_bits_lazy.mlir new file mode 100644 index 000000000..4f7052466 --- /dev/null +++ b/tests/gold/test_namer_dict_smart_bits_lazy.mlir @@ -0,0 +1,26 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module @test_namer_dict_smart_bits_lazy(%I0: i8, %I1: i8) -> (O: i9) { + %0 = comb.extract %I0 from 0 : (i8) -> i1 + %1 = comb.extract %I0 from 1 : (i8) -> i1 + %2 = comb.extract %I0 from 2 : (i8) -> i1 + %3 = comb.extract %I0 from 3 : (i8) -> i1 + %4 = comb.extract %I0 from 4 : (i8) -> i1 + %5 = comb.extract %I0 from 5 : (i8) -> i1 + %6 = comb.extract %I0 from 6 : (i8) -> i1 + %7 = comb.extract %I0 from 7 : (i8) -> i1 + %8 = hw.constant 0 : i1 + %9 = comb.concat %8, %7, %6, %5, %4, %3, %2, %1, %0 : i1, i1, i1, i1, i1, i1, i1, i1, i1 + %10 = comb.extract %I1 from 0 : (i8) -> i1 + %11 = comb.extract %I1 from 1 : (i8) -> i1 + %12 = comb.extract %I1 from 2 : (i8) -> i1 + %13 = comb.extract %I1 from 3 : (i8) -> i1 + %14 = comb.extract %I1 from 4 : (i8) -> i1 + %15 = comb.extract %I1 from 5 : (i8) -> i1 + %16 = comb.extract %I1 from 6 : (i8) -> i1 + %17 = comb.extract %I1 from 7 : (i8) -> i1 + %18 = hw.constant 0 : i1 + %19 = comb.concat %18, %17, %16, %15, %14, %13, %12, %11, %10 : i1, i1, i1, i1, i1, i1, i1, i1, i1 + %20 = comb.add %9, %19 : i9 + hw.output %20 : i9 + } +} diff --git a/tests/test_namer_dict.py b/tests/test_namer_dict.py index 7ae10bc0d..53e13aacc 100644 --- a/tests/test_namer_dict.py +++ b/tests/test_namer_dict.py @@ -66,6 +66,36 @@ class test_namer_dict_smart_bits(m.Circuit): assert check_gold(__file__, f"test_namer_dict_smart_bits.mlir") +def test_namer_dict_smart_bits_lazy(): + + class test_namer_dict_smart_bits_lazy(m.Circuit): + io = m.IO(I0=m.In(m.smart.SmartBits[8]), + I1=m.In(m.smart.SmartBits[8]), + O=m.Out(m.smart.SmartBits[9])) + x = io.I0 + io.I1 + io.O @= x + + m.compile("build/test_namer_dict_smart_bits_lazy", + test_namer_dict_smart_bits_lazy, + output="mlir") + assert check_gold(__file__, f"test_namer_dict_smart_bits_lazy.mlir") + + +def test_namer_dict_smart_bits_lazy_explicit(): + + class test_namer_dict_smart_bits_lazy(m.Circuit): + io = m.IO(I0=m.In(m.smart.SmartBits[8]), + I1=m.In(m.smart.SmartBits[8]), + O=m.Out(m.smart.SmartBits[9])) + x = io.I0 + io.I1 + io.O @= x + + m.compile("build/test_namer_dict_smart_bits_lazy", + test_namer_dict_smart_bits_lazy, + output="mlir") + assert check_gold(__file__, f"test_namer_dict_smart_bits_lazy.mlir") + + def test_namer_dict_already_named(): class Foo(m.Circuit): From b3cd6d5fb37830dc16287017bfb3b5d032621619 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:47:26 -0800 Subject: [PATCH 49/61] Add lazy logic --- magma/circuit.py | 4 ---- magma/smart/eval.py | 11 +++++++++-- magma/smart/smart_bits.py | 3 +++ tests/gold/test_namer_dict_smart_bits_lazy.mlir | 5 ++++- tests/test_namer_dict.py | 13 +++++++------ 5 files changed, 23 insertions(+), 13 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 8c9d06e29..aba03d88f 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -256,10 +256,6 @@ def _set_lazy_value_or_inst_name( if not value.name: self._check_unique_name(key, value) else: - # We do not expect a LazyNamedValue (SmartExpr) to be given an - # explicit name (since it can only be constructed by forming an - # anonymous expression). - assert not isinstance(value, LazyNamedValue) self._check_unique_name(value.name, value) def __setitem__(self, key, value): diff --git a/magma/smart/eval.py b/magma/smart/eval.py index 0dea98b71..79fb581c2 100644 --- a/magma/smart/eval.py +++ b/magma/smart/eval.py @@ -5,6 +5,7 @@ from magma.bits import Bits from magma.bitutils import clog2 from magma.common import MroVisitor, Stack +from magma.ref import TempNamedRef from magma.smart.smart_bits import ( SmartExprMeta, SmartExpr, @@ -403,5 +404,11 @@ def evaluate_assignment(lhs: SmartBits, rhs: SmartExpr) -> SmartBits: signednesses = _determine_result_signednesses(root) root = _insert_signednesses(root, widths, signednesses) root = _push_down_extensions(root, widths, signednesses) - result = SmartBits.from_bits(_evaluate(root), rhs.name) - return _force_width(result, len(lhs)) + evaluated = SmartBits.from_bits(_evaluate(root), rhs.name) + result = _force_width(evaluated, len(lhs)) + if not rhs.name or isinstance(rhs, SmartBits): + return result + # SmartExpr was given a lazy name, apply it now + temp = type(result).undirected_t(name=rhs.name) + temp @= result + return temp diff --git a/magma/smart/smart_bits.py b/magma/smart/smart_bits.py index 43819d9c7..38ede1037 100644 --- a/magma/smart/smart_bits.py +++ b/magma/smart/smart_bits.py @@ -152,6 +152,9 @@ def zext(self, width) -> 'SmartExtendOp': def sext(self, width) -> 'SmartExtendOp': return SmartExtendOp(width, True, self) + def const(self) -> bool: + return False + class SmartOp(SmartExpr, metaclass=SmartExprMeta): def __init__(self, op, *args): diff --git a/tests/gold/test_namer_dict_smart_bits_lazy.mlir b/tests/gold/test_namer_dict_smart_bits_lazy.mlir index 4f7052466..7acc32618 100644 --- a/tests/gold/test_namer_dict_smart_bits_lazy.mlir +++ b/tests/gold/test_namer_dict_smart_bits_lazy.mlir @@ -21,6 +21,9 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"} { %18 = hw.constant 0 : i1 %19 = comb.concat %18, %17, %16, %15, %14, %13, %12, %11, %10 : i1, i1, i1, i1, i1, i1, i1, i1, i1 %20 = comb.add %9, %19 : i9 - hw.output %20 : i9 + %22 = sv.wire sym @test_namer_dict_smart_bits_lazy.x {name="x"} : !hw.inout + sv.assign %22, %20 : i9 + %21 = sv.read_inout %22 : !hw.inout + hw.output %21 : i9 } } diff --git a/tests/test_namer_dict.py b/tests/test_namer_dict.py index 53e13aacc..a8b62b358 100644 --- a/tests/test_namer_dict.py +++ b/tests/test_namer_dict.py @@ -81,19 +81,20 @@ class test_namer_dict_smart_bits_lazy(m.Circuit): assert check_gold(__file__, f"test_namer_dict_smart_bits_lazy.mlir") -def test_namer_dict_smart_bits_lazy_explicit(): +def test_namer_dict_smart_bits_lazy_rename(): - class test_namer_dict_smart_bits_lazy(m.Circuit): + class test_namer_dict_smart_bits_lazy_rename(m.Circuit): io = m.IO(I0=m.In(m.smart.SmartBits[8]), I1=m.In(m.smart.SmartBits[8]), O=m.Out(m.smart.SmartBits[9])) x = io.I0 + io.I1 - io.O @= x + y = x + io.O @= y - m.compile("build/test_namer_dict_smart_bits_lazy", - test_namer_dict_smart_bits_lazy, + m.compile("build/test_namer_dict_smart_bits_lazy_rename", + test_namer_dict_smart_bits_lazy_rename, output="mlir") - assert check_gold(__file__, f"test_namer_dict_smart_bits_lazy.mlir") + assert check_gold(__file__, f"test_namer_dict_smart_bits_lazy_rename.mlir") def test_namer_dict_already_named(): From ede8c1c10df81d262568a4445d5fe7bb585bdeb5 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:47:58 -0800 Subject: [PATCH 50/61] Add comment --- magma/circuit.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/magma/circuit.py b/magma/circuit.py index aba03d88f..06810c861 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -205,6 +205,8 @@ def _get_intermediate_values(value): class LazyNamedValue: + """Used for SmartExpr because it does not have a magma value until it's + resolved (stages the naming of the resolved value)""" pass From 911ae9f477fc55e9c13a2687f39f09982820e4a8 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:48:09 -0800 Subject: [PATCH 51/61] Formatting --- magma/circuit.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 06810c861..5d9f76ea6 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -226,8 +226,7 @@ def _check_unique_name( value: Union[Type, LazyNamedValue, 'Circuit'], ): """If key has been seen more than once, "uniquify" the names by append - _{i} to them. - """ + _{i} to them.""" values = self._inferred_names.setdefault(key, []) if len(values) == 0: self._set_name(key, value) From c4a4a1233f60a5f3cc54831ecb200670c36951c5 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:48:24 -0800 Subject: [PATCH 52/61] Formatting --- magma/circuit.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 5d9f76ea6..4eca5fd06 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -242,8 +242,7 @@ def _check_unique_name( def _set_value_name(self, key: str, value: Type): if not hasattr(value, "name"): - # Interface object is a Type without a name - return + return # Interface object is a Type without a name. if isinstance(value.name, AnonRef): self._check_unique_name(key, value) elif isinstance(value.name, TempNamedRef): From 84db2cc70129a2105ac3d85a45d1487c784caa02 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:49:10 -0800 Subject: [PATCH 53/61] Add note on commit for golds --- conftest.py | 1 + magma/smart/eval.py | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/conftest.py b/conftest.py index 1eba87136..ddf75657b 100644 --- a/conftest.py +++ b/conftest.py @@ -6,6 +6,7 @@ def pytest_configure(config): magma_config.compile_dir = 'callee_file_dir' # TODO: Enable this globally for testing + # revert a3a2452168f2251277a14548d053a9ca7a45bff7 for golds # magma_config.use_namer_dict = True diff --git a/magma/smart/eval.py b/magma/smart/eval.py index 79fb581c2..b60414a64 100644 --- a/magma/smart/eval.py +++ b/magma/smart/eval.py @@ -408,7 +408,7 @@ def evaluate_assignment(lhs: SmartBits, rhs: SmartExpr) -> SmartBits: result = _force_width(evaluated, len(lhs)) if not rhs.name or isinstance(rhs, SmartBits): return result - # SmartExpr was given a lazy name, apply it now + # SmartExpr was given a lazy name, apply it now. temp = type(result).undirected_t(name=rhs.name) temp @= result return temp From c943ca35c4b721c7dad3a75e2bcc12d5c2842168 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:50:53 -0800 Subject: [PATCH 54/61] Revert wire changes --- magma/backend/coreir/insert_coreir_wires.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/magma/backend/coreir/insert_coreir_wires.py b/magma/backend/coreir/insert_coreir_wires.py index 9465bfdca..1592ed98e 100644 --- a/magma/backend/coreir/insert_coreir_wires.py +++ b/magma/backend/coreir/insert_coreir_wires.py @@ -66,9 +66,8 @@ def _make_wire(self, driver, value, definition): recast = ( self._flatten and ( - not isinstance(wire_output, type(value)) and - isinstance(value, _ClockType) or - isinstance(wire_output, _ClockType) + isinstance(value, _ClockType) + and not isinstance(wire_output, type(value)) ) ) if recast: From 619679887cb7eaf0bf2a7b9ff2fee0f546214ebe Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 12:53:58 -0800 Subject: [PATCH 55/61] Rework register logic --- magma/circuit.py | 5 ++++- magma/config.py | 9 +++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 4eca5fd06..4f87389c5 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -26,7 +26,7 @@ pass from magma.clock import is_clock_or_nested_clock, Clock, ClockTypes -from magma.config import get_debug_mode, set_debug_mode, config +from magma.config import get_debug_mode, set_debug_mode, config, RuntimeConfig from magma.definition_context import ( DefinitionContext, definition_context_manager, @@ -278,6 +278,9 @@ def __hash__(self): return hash(tuple(sorted(self.items()))) +config.register(use_namer_dict=RuntimeConfig(False)) + + class CircuitKind(type): def __prepare__(name, bases, **kwargs): ctx = DefinitionContext(StagedPlacer(name)) diff --git a/magma/config.py b/magma/config.py index 1ca75a975..9a5963d14 100644 --- a/magma/config.py +++ b/magma/config.py @@ -59,8 +59,7 @@ class ConfigManager: __entries = {} def __init__(self, **kwargs): - for key, value in kwargs.items(): - ConfigManager.__entries[key] = value + self._register(**kwargs) def _register(self, **kwargs): for key, value in kwargs.items(): @@ -68,6 +67,9 @@ def _register(self, **kwargs): raise RuntimeError(f"Config with key '{key}' already exists") ConfigManager.__entries[key] = value + def register(self, **kwargs): + self._register(**kwargs) + def __get(self, key): return ConfigManager.__entries[key].get() @@ -89,8 +91,7 @@ def __setitem__(self, key, value): config = ConfigManager( compile_dir=RuntimeConfig("normal"), - debug_mode=RuntimeConfig(False), - use_namer_dict=RuntimeConfig(False) + debug_mode=RuntimeConfig(False) ) From 24c10acdfe7625aa559f462257be8cd995f18145 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 13:00:29 -0800 Subject: [PATCH 56/61] Cleanup smartbits logic --- magma/smart/eval.py | 2 +- magma/smart/smart_bits.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/magma/smart/eval.py b/magma/smart/eval.py index b60414a64..3bfc8cda5 100644 --- a/magma/smart/eval.py +++ b/magma/smart/eval.py @@ -404,7 +404,7 @@ def evaluate_assignment(lhs: SmartBits, rhs: SmartExpr) -> SmartBits: signednesses = _determine_result_signednesses(root) root = _insert_signednesses(root, widths, signednesses) root = _push_down_extensions(root, widths, signednesses) - evaluated = SmartBits.from_bits(_evaluate(root), rhs.name) + evaluated = SmartBits.from_bits(_evaluate(root)) result = _force_width(evaluated, len(lhs)) if not rhs.name or isinstance(rhs, SmartBits): return result diff --git a/magma/smart/smart_bits.py b/magma/smart/smart_bits.py index 38ede1037..e6c94bacc 100644 --- a/magma/smart/smart_bits.py +++ b/magma/smart/smart_bits.py @@ -453,13 +453,13 @@ def wire(self, other, debug_info): MagmaProtocol.wire(self, other, debug_info) @staticmethod - def from_bits(value, name=None): + def from_bits(value): if isinstance(value, Bit): value = bits(value) if not isinstance(value, Bits): raise TypeError(value) signed = isinstance(value, SInt) - return SmartBits[len(value), signed](value, name=name) + return SmartBits[len(value), signed](value) def __str__(self): signed = type(self)._signed_ From 568afb6a52a3ce980e2a4f846ad2b8175ac772d1 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 13:07:59 -0800 Subject: [PATCH 57/61] Avoid LazyNamedValue logic --- magma/circuit.py | 29 ++++++----------------------- magma/smart/smart_bits.py | 6 +++--- 2 files changed, 9 insertions(+), 26 deletions(-) diff --git a/magma/circuit.py b/magma/circuit.py index 4f87389c5..3cb54cc33 100644 --- a/magma/circuit.py +++ b/magma/circuit.py @@ -36,7 +36,7 @@ ) from magma.find_unconnected_ports import find_and_log_unconnected_ports from magma.logging import root_logger, capture_logs -from magma.protocol_type import magma_value +from magma.protocol_type import MagmaProtocol from magma.ref import TempNamedRef, AnonRef from magma.t import In, Type from magma.view import PortView @@ -204,26 +204,20 @@ def _get_intermediate_values(value): return values -class LazyNamedValue: - """Used for SmartExpr because it does not have a magma value until it's - resolved (stages the naming of the resolved value)""" - pass - - class NamerDict(dict): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) self._inferred_names = {} def _set_name(self, key, value): - if isinstance(value, Type): + if isinstance(value, (Type, MagmaProtocol)): key = TempNamedRef(key, value) value.name = key def _check_unique_name( self, key: str, - value: Union[Type, LazyNamedValue, 'Circuit'], + value: Union[Type, 'Circuit'], ): """If key has been seen more than once, "uniquify" the names by append _{i} to them.""" @@ -248,11 +242,7 @@ def _set_value_name(self, key: str, value: Type): elif isinstance(value.name, TempNamedRef): self._check_unique_name(value.name.name, value) - def _set_lazy_value_or_inst_name( - self, - key: str, - value: Union[LazyNamedValue, 'Circuit'] - ): + def _set_inst_name(self, key: str, value: 'Circuit'): if not value.name: self._check_unique_name(key, value) else: @@ -260,19 +250,12 @@ def _set_lazy_value_or_inst_name( def __setitem__(self, key, value): super().__setitem__(key, value) - if isinstance(value, LazyNamedValue): - try: - value = magma_value(value) - except NotImplementedError: - pass # SmartExpr doesn't have a magma_value yet - if isinstance(value, Type): + if isinstance(value, (Type, MagmaProtocol)): self._set_value_name(key, value) - elif isinstance(value, LazyNamedValue): - self._set_lazy_value_or_inst_name(key, value) elif isinstance(type(value), CircuitKind): # NOTE: we check type(value) because this code is run in the Circuit # class creation pipeline (so Circuit may not be defined yet). - self._set_lazy_value_or_inst_name(key, value) + self._set_inst_name(key, value) def __hash__(self): return hash(tuple(sorted(self.items()))) diff --git a/magma/smart/smart_bits.py b/magma/smart/smart_bits.py index e6c94bacc..10bee0abf 100644 --- a/magma/smart/smart_bits.py +++ b/magma/smart/smart_bits.py @@ -6,22 +6,22 @@ from magma.bit import Bit from magma.bits import Bits, BitsMeta, SInt, reduce as bits_reduce -from magma.circuit import LazyNamedValue from magma.conversions import uint, bits, sint from magma.conversions import concat as bits_concat from magma.debug import debug_wire from magma.protocol_type import MagmaProtocolMeta, MagmaProtocol +from magma.ref import AnonRef class SmartExprMeta(MagmaProtocolMeta): pass -class SmartExpr(MagmaProtocol, LazyNamedValue, metaclass=SmartExprMeta): +class SmartExpr(MagmaProtocol, metaclass=SmartExprMeta): __hash__ = object.__hash__ def __init__(self): - self._name = None + self._name = AnonRef() @property def name(self): From bd8882629a08ab1d909ce06d1a322f9620a6d21e Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 13:11:13 -0800 Subject: [PATCH 58/61] Update smartbits protocol logic --- magma/protocol_type.py | 8 ++++++++ magma/smart/smart_bits.py | 18 ++++++++---------- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/magma/protocol_type.py b/magma/protocol_type.py index cf14c8c8b..4fc7395ef 100644 --- a/magma/protocol_type.py +++ b/magma/protocol_type.py @@ -140,6 +140,14 @@ def const(self): def set_enclosing_when_context(self, ctx): self._get_magma_value_().set_enclosing_when_context(ctx) + @property + def name(self): + return self._get_magma_value_().name + + @name.setter + def name(self, value): + self._get_magma_value_().name = value + def magma_type(T): if issubclass(T, MagmaProtocol): diff --git a/magma/smart/smart_bits.py b/magma/smart/smart_bits.py index 10bee0abf..66bf9ee0e 100644 --- a/magma/smart/smart_bits.py +++ b/magma/smart/smart_bits.py @@ -22,14 +22,20 @@ class SmartExpr(MagmaProtocol, metaclass=SmartExprMeta): def __init__(self): self._name = AnonRef() + self._value = None @property def name(self): - return self._name + if self._value is None: + return self._name + return self._value.name @name.setter def name(self, value): - self._name = value + if self._value is None: + self._name = value + else: + self._value.name = value @property @abc.abstractmethod @@ -468,14 +474,6 @@ def __str__(self): def connection_iter(self): yield from zip(self, self.trace()) - @property - def name(self): - return self._get_magma_value_().name - - @name.setter - def name(self, value): - self._get_magma_value_().name = value - SmartBit = SmartBits[1] From 2a32127b66fa416194d01b67bb4d67dd1196775a Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 13:28:42 -0800 Subject: [PATCH 59/61] Add missing gold --- ...est_namer_dict_smart_bits_lazy_rename.mlir | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 tests/gold/test_namer_dict_smart_bits_lazy_rename.mlir diff --git a/tests/gold/test_namer_dict_smart_bits_lazy_rename.mlir b/tests/gold/test_namer_dict_smart_bits_lazy_rename.mlir new file mode 100644 index 000000000..a51c34913 --- /dev/null +++ b/tests/gold/test_namer_dict_smart_bits_lazy_rename.mlir @@ -0,0 +1,29 @@ +module attributes {circt.loweringOptions = "locationInfoStyle=none"} { + hw.module @test_namer_dict_smart_bits_lazy_rename(%I0: i8, %I1: i8) -> (O: i9) { + %0 = comb.extract %I0 from 0 : (i8) -> i1 + %1 = comb.extract %I0 from 1 : (i8) -> i1 + %2 = comb.extract %I0 from 2 : (i8) -> i1 + %3 = comb.extract %I0 from 3 : (i8) -> i1 + %4 = comb.extract %I0 from 4 : (i8) -> i1 + %5 = comb.extract %I0 from 5 : (i8) -> i1 + %6 = comb.extract %I0 from 6 : (i8) -> i1 + %7 = comb.extract %I0 from 7 : (i8) -> i1 + %8 = hw.constant 0 : i1 + %9 = comb.concat %8, %7, %6, %5, %4, %3, %2, %1, %0 : i1, i1, i1, i1, i1, i1, i1, i1, i1 + %10 = comb.extract %I1 from 0 : (i8) -> i1 + %11 = comb.extract %I1 from 1 : (i8) -> i1 + %12 = comb.extract %I1 from 2 : (i8) -> i1 + %13 = comb.extract %I1 from 3 : (i8) -> i1 + %14 = comb.extract %I1 from 4 : (i8) -> i1 + %15 = comb.extract %I1 from 5 : (i8) -> i1 + %16 = comb.extract %I1 from 6 : (i8) -> i1 + %17 = comb.extract %I1 from 7 : (i8) -> i1 + %18 = hw.constant 0 : i1 + %19 = comb.concat %18, %17, %16, %15, %14, %13, %12, %11, %10 : i1, i1, i1, i1, i1, i1, i1, i1, i1 + %20 = comb.add %9, %19 : i9 + %22 = sv.wire sym @test_namer_dict_smart_bits_lazy_rename.x {name="x"} : !hw.inout + sv.assign %22, %20 : i9 + %21 = sv.read_inout %22 : !hw.inout + hw.output %21 : i9 + } +} From 0404c3ce31f8d18cf65d3592ce37934c8d7b9308 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 13:45:50 -0800 Subject: [PATCH 60/61] Remove metadata logic --- benchmarks/debug.svg | 6 +++--- magma/debug_rewriter.py | 6 +----- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/benchmarks/debug.svg b/benchmarks/debug.svg index 131c2b633..532f3c2cd 100644 --- a/benchmarks/debug.svg +++ b/benchmarks/debug.svg @@ -1,4 +1,4 @@ -Pygal000.010.010.020.020.030.030.040.040.050.050.060.060.070.070.080.080.090.090.10.10.003796975012147.9435897435897539.34357985381220.08692598401339.4322.87856438523590.103392629530.8564102564102280.0OffOldNew \ No newline at end of file +Pygal000.010.010.020.020.030.030.040.040.050.050.060.060.070.070.003851449001147.9435897435897536.21549287656430.07967011601339.4280.000000000000060.07454027602530.8564102564102297.3353678419317OffOldNew \ No newline at end of file diff --git a/magma/debug_rewriter.py b/magma/debug_rewriter.py index 49a980283..3abc8cd78 100644 --- a/magma/debug_rewriter.py +++ b/magma/debug_rewriter.py @@ -21,9 +21,6 @@ def leave_Assign( if not isinstance(updated_node.targets[0].target, cst.Name): return updated_node - pos = self.get_metadata(cst.metadata.PositionProvider, - original_node).start - value_str = cst.Module((cst.Expr(updated_node.value), )).code name = updated_node.targets[0].target.value targets = updated_node.targets + ( cst.AssignTarget(cst.parse_expression(f"self.{name}")), @@ -48,8 +45,7 @@ def debug(fn): # consistent program_txt = program_txt.lstrip() tree = cst.parse_module(program_txt) - wrapper = cst.metadata.MetadataWrapper(tree) - tree = wrapper.visit(Transformer()) + tree = tree.visit(Transformer()) namespace = dict(**fn.__globals__) exec(tree.code, namespace) From a6b7028bd37389779fefca56e55f7da94b95988e Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 16 Dec 2022 13:56:18 -0800 Subject: [PATCH 61/61] Need namerdict for generator test --- conftest.py | 1 + 1 file changed, 1 insertion(+) diff --git a/conftest.py b/conftest.py index cd0f0eb5a..bed35cadd 100644 --- a/conftest.py +++ b/conftest.py @@ -5,6 +5,7 @@ def pytest_configure(config): magma_config.compile_dir = 'callee_file_dir' + magma_config.use_namer_dict = True magma_config.use_generator_debug_rewriter = True # TODO: Enable this globally for testing # revert a3a2452168f2251277a14548d053a9ca7a45bff7 for golds