From aaa9da1657650b7aac8d0f8a21e89c7f10b57eb8 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Mon, 22 Nov 2021 18:33:29 +0200 Subject: [PATCH 01/17] Convert README to markdown --- examples/native-blink/README.md | 27 +++++++++++++++++++++++ examples/native-blink/README.rst | 38 -------------------------------- examples/stc-blink/README.md | 27 +++++++++++++++++++++++ examples/stc-blink/README.rst | 38 -------------------------------- examples/stc-header/README.md | 27 +++++++++++++++++++++++ examples/stc-header/README.rst | 38 -------------------------------- 6 files changed, 81 insertions(+), 114 deletions(-) create mode 100644 examples/native-blink/README.md delete mode 100644 examples/native-blink/README.rst create mode 100644 examples/stc-blink/README.md delete mode 100644 examples/stc-blink/README.rst create mode 100644 examples/stc-header/README.md delete mode 100644 examples/stc-header/README.rst diff --git a/examples/native-blink/README.md b/examples/native-blink/README.md new file mode 100644 index 0000000..1899e34 --- /dev/null +++ b/examples/native-blink/README.md @@ -0,0 +1,27 @@ +How to build PlatformIO based project +===================================== + +1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +2. Download [development platform with examples](https://github.com/platformio/platform-intel_mcs51/archive/develop.zip) +3. Extract ZIP archive +4. Run these commands: + +```shell +# Change directory to example +$ cd platform-intel_mcs51/examples/native-blink + +# Build project +$ pio run + +# Upload firmware +$ pio run --target upload + +# Build specific environment +$ pio run -e stc15f204ea + +# Upload firmware for the specific environment +$ pio run -e stc15f204ea --target upload + +# Clean build files +$ pio run --target clean +``` diff --git a/examples/native-blink/README.rst b/examples/native-blink/README.rst deleted file mode 100644 index ab5e1c3..0000000 --- a/examples/native-blink/README.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. Copyright 2014-present PlatformIO - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - -How to build PlatformIO based project -===================================== - -1. `Install PlatformIO Core `_ -2. Download `development platform with examples `_ -3. Extract ZIP archive -4. Run these commands: - -.. code-block:: bash - - # Change directory to example - > cd platform-intel_mcs51/examples/native-blink - - # Build project - > platformio run - - # Upload firmware - > platformio run --target upload - - # Build specific environment - > platformio run -e stc15f204ea - - # Upload firmware for the specific environment - > platformio run -e stc15f204ea --target upload - - # Clean build files - > platformio run --target clean diff --git a/examples/stc-blink/README.md b/examples/stc-blink/README.md new file mode 100644 index 0000000..e86dc39 --- /dev/null +++ b/examples/stc-blink/README.md @@ -0,0 +1,27 @@ +How to build PlatformIO based project +===================================== + +1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +2. Download [development platform with examples](https://github.com/platformio/platform-intel_mcs51/archive/develop.zip) +3. Extract ZIP archive +4. Run these commands: + +```shell +# Change directory to example +$ cd platform-intel_mcs51/examples/stc-blink + +# Build project +$ pio run + +# Upload firmware +$ pio run --target upload + +# Build specific environment +$ pio run -e stc15w408as + +# Upload firmware for the specific environment +$ pio run -e stc15w408as --target upload + +# Clean build files +$ pio run --target clean +``` diff --git a/examples/stc-blink/README.rst b/examples/stc-blink/README.rst deleted file mode 100644 index 2a8e6ea..0000000 --- a/examples/stc-blink/README.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. Copyright 2014-present PlatformIO - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - -How to build PlatformIO based project -===================================== - -1. `Install PlatformIO Core `_ -2. Download `development platform with examples `_ -3. Extract ZIP archive -4. Run these commands: - -.. code-block:: bash - - # Change directory to example - > cd platform-intel_mcs51/examples/stc-blink - - # Build project - > platformio run - - # Upload firmware - > platformio run --target upload - - # Build specific environment - > platformio run -e stc15w408as - - # Upload firmware for the specific environment - > platformio run -e stc15w408as --target upload - - # Clean build files - > platformio run --target clean diff --git a/examples/stc-header/README.md b/examples/stc-header/README.md new file mode 100644 index 0000000..afc3510 --- /dev/null +++ b/examples/stc-header/README.md @@ -0,0 +1,27 @@ +How to build PlatformIO based project +===================================== + +1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +2. Download [development platform with examples](https://github.com/platformio/platform-intel_mcs51/archive/develop.zip) +3. Extract ZIP archive +4. Run these commands: + +```shell +# Change directory to example +$ cd platform-intel_mcs51/examples/stc-header + +# Build project +$ pio run + +# Upload firmware +$ pio run --target upload + +# Build specific environment +$ pio run -e stc15w408as + +# Upload firmware for the specific environment +$ pio run -e stc15w408as --target upload + +# Clean build files +$ pio run --target clean +``` diff --git a/examples/stc-header/README.rst b/examples/stc-header/README.rst deleted file mode 100644 index c52e16d..0000000 --- a/examples/stc-header/README.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. Copyright 2014-present PlatformIO - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - -How to build PlatformIO based project -===================================== - -1. `Install PlatformIO Core `_ -2. Download `development platform with examples `_ -3. Extract ZIP archive -4. Run these commands: - -.. code-block:: bash - - # Change directory to example - > cd platform-intel_mcs51/examples/stc-header - - # Build project - > platformio run - - # Upload firmware - > platformio run --target upload - - # Build specific environment - > platformio run -e stc15w408as - - # Upload firmware for the specific environment - > platformio run -e stc15w408as --target upload - - # Clean build files - > platformio run --target clean From 57fa6517c4bebe0a846b33a347f5b8d436474916 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Thu, 31 Mar 2022 14:23:42 +0300 Subject: [PATCH 02/17] Switch docs to HTTP --- README.md | 8 ++++---- examples/native-blink/README.md | 2 +- examples/native-blink/platformio.ini | 2 +- examples/stc-blink/README.md | 2 +- examples/stc-header/README.md | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index ccdc109..010d36b 100644 --- a/README.md +++ b/README.md @@ -4,13 +4,13 @@ The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex instruction set computer (CISC) instruction set, single chip microcontroller (µC) series developed by Intel in 1980 for use in embedded systems. -* [Home](http://platformio.org/platforms/intel_mcs51) (home page in PlatformIO Registry) -* [Documentation](http://docs.platformio.org/page/platforms/intel_mcs51.html) (advanced usage, packages, boards, frameworks, etc.) +* [Home](https://registry.platformio.org/platforms/platformio/intel_mcs51) (home page in PlatformIO Registry) +* [Documentation](https://docs.platformio.org/page/platforms/intel_mcs51.html) (advanced usage, packages, boards, frameworks, etc.) # Usage 1. [Install PlatformIO](http://platformio.org) -2. Create PlatformIO project and configure a platform option in [platformio.ini](http://docs.platformio.org/page/projectconf.html) file: +2. Create PlatformIO project and configure a platform option in [platformio.ini](https://docs.platformio.org/page/projectconf.html) file: ## Stable version @@ -32,4 +32,4 @@ board = ... # Configuration -Please navigate to [documentation](http://docs.platformio.org/page/platforms/intel_mcs51.html). +Please navigate to [documentation](https://docs.platformio.org/page/platforms/intel_mcs51.html). diff --git a/examples/native-blink/README.md b/examples/native-blink/README.md index 1899e34..3b149e1 100644 --- a/examples/native-blink/README.md +++ b/examples/native-blink/README.md @@ -1,7 +1,7 @@ How to build PlatformIO based project ===================================== -1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +1. [Install PlatformIO Core](https://docs.platformio.org/page/core.html) 2. Download [development platform with examples](https://github.com/platformio/platform-intel_mcs51/archive/develop.zip) 3. Extract ZIP archive 4. Run these commands: diff --git a/examples/native-blink/platformio.ini b/examples/native-blink/platformio.ini index 1419e4b..243b804 100644 --- a/examples/native-blink/platformio.ini +++ b/examples/native-blink/platformio.ini @@ -5,7 +5,7 @@ ; Library options: dependencies, extra library storages ; ; Please visit documentation for the other options and examples -; http://docs.platformio.org/page/projectconf.html +; https://docs.platformio.org/page/projectconf.html [env:stc15f204ea] platform = intel_mcs51 diff --git a/examples/stc-blink/README.md b/examples/stc-blink/README.md index e86dc39..ca9a5fa 100644 --- a/examples/stc-blink/README.md +++ b/examples/stc-blink/README.md @@ -1,7 +1,7 @@ How to build PlatformIO based project ===================================== -1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +1. [Install PlatformIO Core](https://docs.platformio.org/page/core.html) 2. Download [development platform with examples](https://github.com/platformio/platform-intel_mcs51/archive/develop.zip) 3. Extract ZIP archive 4. Run these commands: diff --git a/examples/stc-header/README.md b/examples/stc-header/README.md index afc3510..b552bbb 100644 --- a/examples/stc-header/README.md +++ b/examples/stc-header/README.md @@ -1,7 +1,7 @@ How to build PlatformIO based project ===================================== -1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +1. [Install PlatformIO Core](https://docs.platformio.org/page/core.html) 2. Download [development platform with examples](https://github.com/platformio/platform-intel_mcs51/archive/develop.zip) 3. Extract ZIP archive 4. Run these commands: From 67dca44e0cc1192b759f1c46fefd653d1d3d0eba Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Fri, 8 Apr 2022 12:54:59 +0300 Subject: [PATCH 03/17] Symlink dev-platform --- .travis.yml | 2 +- appveyor.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index d19878c..869442a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -10,7 +10,7 @@ env: install: - pip install -U https://github.com/platformio/platformio/archive/develop.zip - - platformio platform install file://. + - pio pkg install --global --platform symlink://. script: - platformio run -d $PLATFORMIO_PROJECT_DIR diff --git a/appveyor.yml b/appveyor.yml index dc7f38d..806a054 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -10,7 +10,7 @@ install: - cmd: git submodule update --init --recursive - cmd: SET PATH=C:\Python36\Scripts;%PATH% - cmd: pip3 install -U https://github.com/platformio/platformio/archive/develop.zip -- cmd: platformio platform install file://. +- cmd: pio pkg install --global --platform symlink://. test_script: - cmd: platformio run -d %PLATFORMIO_PROJECT_DIR% From d0a8315012bb9af9e4470b05ba118b640afd83de Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 10 Apr 2022 19:36:41 +0300 Subject: [PATCH 04/17] Add native blink example written in assembly --- builder/main.py | 4 ++- examples/assembly-blink/.gitignore | 1 + examples/assembly-blink/include/README | 39 ++++++++++++++++++++++ examples/assembly-blink/lib/README | 46 ++++++++++++++++++++++++++ examples/assembly-blink/platformio.ini | 13 ++++++++ examples/assembly-blink/src/main.s | 34 +++++++++++++++++++ examples/assembly-blink/test/README | 11 ++++++ 7 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 examples/assembly-blink/.gitignore create mode 100644 examples/assembly-blink/include/README create mode 100644 examples/assembly-blink/lib/README create mode 100644 examples/assembly-blink/platformio.ini create mode 100644 examples/assembly-blink/src/main.s create mode 100644 examples/assembly-blink/test/README diff --git a/builder/main.py b/builder/main.py index 00f0216..a1d2598 100644 --- a/builder/main.py +++ b/builder/main.py @@ -73,7 +73,9 @@ def _parseSdccFlags(flags): ) env.Append( - ASFLAGS=env.get("CCFLAGS", [])[:], + ASFLAGS=[ + "-l", "-s" + ], CFLAGS=[ "--std-sdcc11" diff --git a/examples/assembly-blink/.gitignore b/examples/assembly-blink/.gitignore new file mode 100644 index 0000000..03f4a3c --- /dev/null +++ b/examples/assembly-blink/.gitignore @@ -0,0 +1 @@ +.pio diff --git a/examples/assembly-blink/include/README b/examples/assembly-blink/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/assembly-blink/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/assembly-blink/lib/README b/examples/assembly-blink/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/assembly-blink/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/assembly-blink/platformio.ini b/examples/assembly-blink/platformio.ini new file mode 100644 index 0000000..15f4256 --- /dev/null +++ b/examples/assembly-blink/platformio.ini @@ -0,0 +1,13 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env:stc15f204ea] +platform = intel_mcs51 +board = stc15f204ea diff --git a/examples/assembly-blink/src/main.s b/examples/assembly-blink/src/main.s new file mode 100644 index 0000000..0187a45 --- /dev/null +++ b/examples/assembly-blink/src/main.s @@ -0,0 +1,34 @@ +.module blink + +.area HOME (CODE) +.area XSEG (DATA) +.area PSEG (DATA) +.area INTV (ABS) +.org 0x0000 +_int_reset: + ljmp main + +.area CSEG (ABS, CODE) +.org 0x0090 +main: + cpl P3.2 + acall delay + cpl P3.3 + acall delay + cpl P3.4 + acall delay + cpl P3.5 + acall delay + nop + nop + nop + nop + sjmp main + +delay: + mov r4, #0x00 + mov r3, #0x00 +wait: + djnz r4, wait + djnz r3, wait + ret \ No newline at end of file diff --git a/examples/assembly-blink/test/README b/examples/assembly-blink/test/README new file mode 100644 index 0000000..b94d089 --- /dev/null +++ b/examples/assembly-blink/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PlatformIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PlatformIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html From df8bd8977538b89a0f44a8d27d49b332b316d59c Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 10 Apr 2022 19:42:19 +0300 Subject: [PATCH 05/17] Switch to Github Actions --- .github/FUNDING.yml | 1 + .github/workflows/examples.yml | 34 ++++++++++++++++++++++++++++++++++ .travis.yml | 25 ------------------------- README.md | 3 +-- appveyor.yml | 24 ------------------------ 5 files changed, 36 insertions(+), 51 deletions(-) create mode 100644 .github/FUNDING.yml create mode 100644 .github/workflows/examples.yml delete mode 100644 .travis.yml delete mode 100644 appveyor.yml diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 0000000..6f70f7e --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1 @@ +custom: https://platformio.org/donate diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml new file mode 100644 index 0000000..0094722 --- /dev/null +++ b/.github/workflows/examples.yml @@ -0,0 +1,34 @@ +name: Examples + +on: [push, pull_request] + +jobs: + build: + strategy: + fail-fast: false + matrix: + os: [ubuntu-latest, windows-latest, macos-latest] + python-version: [3.7] + example: + - "examples/assembly-blink" + - "examples/native-blink" + - "examples/native-blink" + - "examples/stc-blink" + - "examples/stc-header" + runs-on: ${{ matrix.os }} + steps: + - uses: actions/checkout@v2 + with: + submodules: "recursive" + - name: Set up Python ${{ matrix.python-version }} + uses: actions/setup-python@v3 + with: + python-version: ${{ matrix.python-version }} + - name: Install dependencies + run: | + python -m pip install --upgrade pip + pip install -U https://github.com/platformio/platformio/archive/develop.zip + pio pkg install --global --platform symlink://. + - name: Build examples + run: | + platformio run -d ${{ matrix.example }} diff --git a/.travis.yml b/.travis.yml deleted file mode 100644 index 869442a..0000000 --- a/.travis.yml +++ /dev/null @@ -1,25 +0,0 @@ -language: python -python: - - "2.7" - - "3.6" - -env: - - PLATFORMIO_PROJECT_DIR=examples/native-blink - - PLATFORMIO_PROJECT_DIR=examples/stc-blink - - PLATFORMIO_PROJECT_DIR=examples/stc-header - -install: - - pip install -U https://github.com/platformio/platformio/archive/develop.zip - - pio pkg install --global --platform symlink://. - -script: - - platformio run -d $PLATFORMIO_PROJECT_DIR - -notifications: - email: false - - slack: - rooms: - secure: rj5uPo81WQHQ6o5hNkIwvptlQezVY6jjsdedqsTAPzRxDGGa3M8NdXJyPLmR2MgN7wDF0UctJC+btiedAcW1G1Szbi7YNTGPhEvUDcJAhTmDVBbNlviHO0xL77wQLXWmEZBLAIiHGGaVoE0wbCryVqCf7pHfK5q7FkgJ1t2tM2QtzBn8IZdAi05RqSuiq6rOZlevg3txUMji6kNaAu3OiqQQmQzDuTyELEi3G/nkqJ5Wze5KoY3ILxYhqCSplodptksZfE+b1o9rMgutNR0QlTORmzP2FM71TtlU9b68XB24Gc1nv49wHdhiZ/EnqAZfyDdFa4IoHPk+GleY0Nm2eCOTSdkbmMagtp8ZhZS9okHsWLhKHkJTNjGawUOHRy99jti1kEWf/Uici1rkqi4CJHbxr83cEFOjGYZYI4SQWBBKyYAB0uqAfRK6QUAQKwutjiyOSwtfzncWtVpP4bSLE2n8prt1Vhbphy8w9etyy+DjjqSgAj4Mr13k/HlaVxfm9OwU2qHtx/TkzA76tNe0af5DNsmDGl8nEV3sMmtT0SselSUkE5DWTag/RiEVM8fX/K+/gw8PnCmxiY28I9F0EisGlitUS19NbUA0nLIO/3V6E8heilzAhMxe3FYPil/0FdQQE/vT4tefofrg4fEV4l9mP3AFNB3yomGIx1h6Bfs= - on_failure: always - on_success: change diff --git a/README.md b/README.md index 010d36b..0e98188 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,5 @@ # Intel MCS-51 (8051): development platform for [PlatformIO](http://platformio.org) -[![Build Status](https://travis-ci.org/platformio/platform-intel_mcs51.svg?branch=develop)](https://travis-ci.org/platformio/platform-intel_mcs51) -[![Build status](https://ci.appveyor.com/api/projects/status/0207sb475heyoaxa/branch/develop?svg=true)](https://ci.appveyor.com/project/ivankravets/platform-intel-mcs51/branch/develop) +[![Build Status](https://github.com/platformio/platform-intel_mcs51/workflows/Examples/badge.svg)](https://github.com/platformio/platform-intel_mcs51/actions) The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex instruction set computer (CISC) instruction set, single chip microcontroller (µC) series developed by Intel in 1980 for use in embedded systems. diff --git a/appveyor.yml b/appveyor.yml deleted file mode 100644 index 806a054..0000000 --- a/appveyor.yml +++ /dev/null @@ -1,24 +0,0 @@ -build: off -environment: - - matrix: - - PLATFORMIO_PROJECT_DIR: "examples/native-blink" - - PLATFORMIO_PROJECT_DIR: "examples/stc-blink" - - PLATFORMIO_PROJECT_DIR: "examples/stc-header" - -install: -- cmd: git submodule update --init --recursive -- cmd: SET PATH=C:\Python36\Scripts;%PATH% -- cmd: pip3 install -U https://github.com/platformio/platformio/archive/develop.zip -- cmd: pio pkg install --global --platform symlink://. - -test_script: -- cmd: platformio run -d %PLATFORMIO_PROJECT_DIR% - -notifications: - - provider: Slack - incoming_webhook: - secure: E9H0SU0Ju7WLDvgxsV8cs3J62T3nTTX7QkEjsczN0Sto/c9hWkVfhc5gGWUkxhlD975cokHByKGJIdwYwCewqOI+7BrcT8U+nlga4Uau7J8= - on_build_success: false - on_build_failure: true - on_build_status_changed: true From 04663e18147b34906fddc73317e14ecbb6a6de73 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 10 Apr 2022 19:51:06 +0300 Subject: [PATCH 06/17] Remove duplicated example from CI --- .github/workflows/examples.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml index 0094722..fb5e21e 100644 --- a/.github/workflows/examples.yml +++ b/.github/workflows/examples.yml @@ -12,7 +12,6 @@ jobs: example: - "examples/assembly-blink" - "examples/native-blink" - - "examples/native-blink" - "examples/stc-blink" - "examples/stc-header" runs-on: ${{ matrix.os }} From 0c97261b0c652a6d0a39729508fb6421dbb0bead Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 10 Apr 2022 21:40:09 +0300 Subject: [PATCH 07/17] Fix "ValueError" when casting F_CPU to int // Resolve #40 --- builder/main.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builder/main.py b/builder/main.py index a1d2598..a58786e 100644 --- a/builder/main.py +++ b/builder/main.py @@ -145,7 +145,7 @@ def _parseSdccFlags(flags): upload_actions = [] if upload_protocol == "stcgal": - f_cpu_khz = int(board_config.get("build.f_cpu")) / 1000 + f_cpu_khz = int(board_config.get("build.f_cpu").strip('L')) / 1000 stcgal_protocol = board_config.get("upload.stcgal_protocol") stcgal = join(env.PioPlatform().get_package_dir("tool-stcgal") or "", "stcgal.py") env.Replace( From 20d13a73a3055672bf3740e2eb7b9a922bcbe181 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 10 Apr 2022 21:43:07 +0300 Subject: [PATCH 08/17] Update SDCC toolchain to the v4.2.0 // Resolve #35 --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index baf54d4..ab4db16 100644 --- a/platform.json +++ b/platform.json @@ -23,7 +23,7 @@ "toolchain-sdcc": { "type": "toolchain", "owner": "platformio", - "version": "~1.30804.10766" + "version": "~1.40200.0" }, "tool-stcgal": { "type": "uploader", From 7e880b5ad0cf2aeddc6701f9ce88d8f6bf16fdfe Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 10 Apr 2022 23:07:47 +0300 Subject: [PATCH 09/17] Use SDCC v4.1.0 for Linux --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index ab4db16..9d212cd 100644 --- a/platform.json +++ b/platform.json @@ -23,7 +23,7 @@ "toolchain-sdcc": { "type": "toolchain", "owner": "platformio", - "version": "~1.40200.0" + "version": ">=1.40100.0,<1.40201.0", }, "tool-stcgal": { "type": "uploader", From e867d651632ec9b04a06fc5bd7a3bd55969f1138 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 10 Apr 2022 23:10:46 +0300 Subject: [PATCH 10/17] Fix broken manifest --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index 9d212cd..4015213 100644 --- a/platform.json +++ b/platform.json @@ -23,7 +23,7 @@ "toolchain-sdcc": { "type": "toolchain", "owner": "platformio", - "version": ">=1.40100.0,<1.40201.0", + "version": ">=1.40100.0,<1.40201.0" }, "tool-stcgal": { "type": "uploader", From 81bf8cc30f33d1926efdb1f80a2d6802e7c1f378 Mon Sep 17 00:00:00 2001 From: Tony Date: Mon, 11 Apr 2022 04:42:23 -0400 Subject: [PATCH 11/17] Add initial support for CH559 (WIP/RFC) (#29) * Add WIP chtool upload Add uploader to support CH55x MCS-51 USB chips * Add CH559 board definition * Update ch559.json change f_cpu to match reset state, per data sheet: After reset, Fosc = 12MHz, Fpll = 288MHz, Fusb4x = 48MHz, Fsys = 12MHz. * fix the omission of "env.Replace" Now working with manual placement of ch55xtool.py in project folder * update python3 to $PYTHONEXE Per https://github.com/platformio/platform-intel_mcs51/pull/29#discussion_r846836842 --- boards/ch559.json | 20 ++++++++++++++++++++ builder/main.py | 15 +++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 boards/ch559.json diff --git a/boards/ch559.json b/boards/ch559.json new file mode 100644 index 0000000..e55ffc1 --- /dev/null +++ b/boards/ch559.json @@ -0,0 +1,20 @@ +{ + "build": { + "f_cpu": "12000000L", + "size_iram": 256, + "size_xram": 6144, + "size_code": 65536, + "size_heap": 128, + "mcu": "ch559", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 6400, + "maximum_size": 65536, + "protocol": "ch55x" + }, + "name": "CH559", + "url": "http://www.wch-ic.com/products/CH559.html", + "vendor": "WCH" +} diff --git a/builder/main.py b/builder/main.py index a58786e..e264677 100644 --- a/builder/main.py +++ b/builder/main.py @@ -163,6 +163,21 @@ def _parseSdccFlags(flags): env.VerboseAction("$UPLOADCMD", "Uploading $SOURCE") ] +# CH55x upload tool +elif upload_protocol == "ch55x": + env.Replace( + UPLOADER="ch55xtool.py", + UPLOADERFLAGS=[ + "-f" + ], + UPLOADCMD="$PYTHONEXE $UPLOADER $UPLOADERFLAGS $BUILD_DIR/${PROGNAME}.bin") + + upload_actions = [ + env.VerboseAction(" ".join(["$OBJCOPY","-I","ihex","-O","binary", + "$SOURCE", "$BUILD_DIR/${PROGNAME}.bin"]), "Creating binary"), + env.VerboseAction("$UPLOADCMD", "Uploading ${PROGNAME}.bin") + ] + # custom upload tool elif upload_protocol == "custom": upload_actions = [env.VerboseAction("$UPLOADCMD", "Uploading $SOURCE")] From 6402cc747528692b663cd64535e1493209618b5e Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Mon, 11 Apr 2022 11:54:41 +0300 Subject: [PATCH 12/17] Add tool-vnproch55x --- builder/main.py | 11 ++++++----- platform.json | 7 +++++++ 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/builder/main.py b/builder/main.py index e264677..8035177 100644 --- a/builder/main.py +++ b/builder/main.py @@ -51,6 +51,7 @@ def _parseSdccFlags(flags): env = DefaultEnvironment() +platform = env.PioPlatform() board_config = env.BoardConfig() env.Replace( @@ -62,7 +63,7 @@ def _parseSdccFlags(flags): OBJCOPY="sdobjcopy", OBJSUFFIX=".rel", LIBSUFFIX=".lib", - SIZETOOL=join(env.PioPlatform().get_dir(), "builder", "size.py"), + SIZETOOL=join(platform.get_dir(), "builder", "size.py"), SIZECHECKCMD='$PYTHONEXE $SIZETOOL $SOURCES', SIZEPRINTCMD='"$PYTHONEXE" $SIZETOOL $SOURCES', @@ -147,15 +148,15 @@ def _parseSdccFlags(flags): if upload_protocol == "stcgal": f_cpu_khz = int(board_config.get("build.f_cpu").strip('L')) / 1000 stcgal_protocol = board_config.get("upload.stcgal_protocol") - stcgal = join(env.PioPlatform().get_package_dir("tool-stcgal") or "", "stcgal.py") env.Replace( + UPLOADER=join(platform.get_package_dir("tool-stcgal") or "", "stcgal.py"), UPLOADERFLAGS=[ "-P", stcgal_protocol, "-p", "$UPLOAD_PORT", "-t", int(f_cpu_khz), "-a" ], - UPLOADCMD='"$PYTHONEXE" %s $UPLOADERFLAGS $SOURCE' % stcgal) + UPLOADCMD='"$PYTHONEXE" "$UPLOADER" $UPLOADERFLAGS $SOURCE') upload_actions = [ env.VerboseAction(env.AutodetectUploadPort, @@ -166,11 +167,11 @@ def _parseSdccFlags(flags): # CH55x upload tool elif upload_protocol == "ch55x": env.Replace( - UPLOADER="ch55xtool.py", + UPLOADER="vnproch55x", UPLOADERFLAGS=[ "-f" ], - UPLOADCMD="$PYTHONEXE $UPLOADER $UPLOADERFLAGS $BUILD_DIR/${PROGNAME}.bin") + UPLOADCMD="$UPLOADER $UPLOADERFLAGS $BUILD_DIR/${PROGNAME}.bin") upload_actions = [ env.VerboseAction(" ".join(["$OBJCOPY","-I","ihex","-O","binary", diff --git a/platform.json b/platform.json index 4015213..bf3b5ac 100644 --- a/platform.json +++ b/platform.json @@ -27,8 +27,15 @@ }, "tool-stcgal": { "type": "uploader", + "optional": true, "owner": "platformio", "version": "~1.104.0" + }, + "tool-vnproch55x": { + "type": "uploader", + "optional": true, + "owner": "platformio", + "version": "~1.0.220407" } } } From 559d003dac00b12a92eb360d244be211969b0218 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Mon, 11 Apr 2022 11:56:08 +0300 Subject: [PATCH 13/17] Apply Black formatter --- builder/main.py | 113 ++++++++++++++++++++++++++---------------------- 1 file changed, 61 insertions(+), 52 deletions(-) diff --git a/builder/main.py b/builder/main.py index 8035177..1a4642e 100644 --- a/builder/main.py +++ b/builder/main.py @@ -21,13 +21,18 @@ def __getSize(size_type, env): # FIXME: i don't really know how to do this right. see: # https://community.platformio.org/t/missing-integers-in-board-extra-flags-in-board-json/821 - return str(env.BoardConfig().get("build", { - # defaults - "size_heap": 1024, - "size_iram": 256, - "size_xram": 65536, - "size_code": 65536, - })[size_type]) + return str( + env.BoardConfig().get( + "build", + { + # defaults + "size_heap": 1024, + "size_iram": 256, + "size_xram": 65536, + "size_code": 65536, + }, + )[size_type] + ) def _parseSdccFlags(flags): @@ -64,42 +69,32 @@ def _parseSdccFlags(flags): OBJSUFFIX=".rel", LIBSUFFIX=".lib", SIZETOOL=join(platform.get_dir(), "builder", "size.py"), - - SIZECHECKCMD='$PYTHONEXE $SIZETOOL $SOURCES', + SIZECHECKCMD="$PYTHONEXE $SIZETOOL $SOURCES", SIZEPRINTCMD='"$PYTHONEXE" $SIZETOOL $SOURCES', SIZEPROGREGEXP=r"^ROM/EPROM/FLASH\s+[a-fx\d]+\s+[a-fx\d]+\s+(\d+).*", - PROGNAME="firmware", - PROGSUFFIX=".hex" + PROGSUFFIX=".hex", ) env.Append( - ASFLAGS=[ - "-l", "-s" - ], - - CFLAGS=[ - "--std-sdcc11" - ], - + ASFLAGS=["-l", "-s"], + CFLAGS=["--std-sdcc11"], CCFLAGS=[ "--opt-code-size", # optimize for size - "--peep-return", # peephole optimization for return instructions - "-m%s" % board_config.get("build.cpu") - ], - - CPPDEFINES=[ - "F_CPU=$BOARD_F_CPU", - "HEAP_SIZE=" + __getSize("size_heap", env) + "--peep-return", # peephole optimization for return instructions + "-m%s" % board_config.get("build.cpu"), ], - + CPPDEFINES=["F_CPU=$BOARD_F_CPU", "HEAP_SIZE=" + __getSize("size_heap", env)], LINKFLAGS=[ "-m%s" % board_config.get("build.cpu"), - "--iram-size", __getSize("size_iram", env), - "--xram-size", __getSize("size_xram", env), - "--code-size", __getSize("size_code", env), - "--out-fmt-ihx" - ] + "--iram-size", + __getSize("size_iram", env), + "--xram-size", + __getSize("size_xram", env), + "--code-size", + __getSize("size_code", env), + "--out-fmt-ihx", + ], ) if int(ARGUMENTS.get("PIOVERBOSE", 0)): @@ -109,12 +104,12 @@ def _parseSdccFlags(flags): if env.get("BUILD_FLAGS"): _parsed, _unparsed = _parseSdccFlags(env.get("BUILD_FLAGS")) env.Append(CCFLAGS=_parsed) - env['BUILD_FLAGS'] = _unparsed + env["BUILD_FLAGS"] = _unparsed project_sdcc_flags = None if env.get("SRC_BUILD_FLAGS"): project_sdcc_flags, _unparsed = _parseSdccFlags(env.get("SRC_BUILD_FLAGS")) - env['SRC_BUILD_FLAGS'] = _unparsed + env["SRC_BUILD_FLAGS"] = _unparsed # # Target: Build executable and linkable firmware @@ -134,8 +129,8 @@ def _parseSdccFlags(flags): # target_size = env.Alias( - "size", target_firm, - env.VerboseAction("$SIZEPRINTCMD", "Calculating size $SOURCE")) + "size", target_firm, env.VerboseAction("$SIZEPRINTCMD", "Calculating size $SOURCE") +) AlwaysBuild(target_size) # @@ -146,37 +141,51 @@ def _parseSdccFlags(flags): upload_actions = [] if upload_protocol == "stcgal": - f_cpu_khz = int(board_config.get("build.f_cpu").strip('L')) / 1000 + f_cpu_khz = int(board_config.get("build.f_cpu").strip("L")) / 1000 stcgal_protocol = board_config.get("upload.stcgal_protocol") env.Replace( UPLOADER=join(platform.get_package_dir("tool-stcgal") or "", "stcgal.py"), UPLOADERFLAGS=[ - "-P", stcgal_protocol, - "-p", "$UPLOAD_PORT", - "-t", int(f_cpu_khz), - "-a" + "-P", + stcgal_protocol, + "-p", + "$UPLOAD_PORT", + "-t", + int(f_cpu_khz), + "-a", ], - UPLOADCMD='"$PYTHONEXE" "$UPLOADER" $UPLOADERFLAGS $SOURCE') + UPLOADCMD='"$PYTHONEXE" "$UPLOADER" $UPLOADERFLAGS $SOURCE', + ) upload_actions = [ - env.VerboseAction(env.AutodetectUploadPort, - "Looking for upload port..."), - env.VerboseAction("$UPLOADCMD", "Uploading $SOURCE") + env.VerboseAction(env.AutodetectUploadPort, "Looking for upload port..."), + env.VerboseAction("$UPLOADCMD", "Uploading $SOURCE"), ] # CH55x upload tool elif upload_protocol == "ch55x": env.Replace( UPLOADER="vnproch55x", - UPLOADERFLAGS=[ - "-f" - ], - UPLOADCMD="$UPLOADER $UPLOADERFLAGS $BUILD_DIR/${PROGNAME}.bin") + UPLOADERFLAGS=["-f"], + UPLOADCMD="$UPLOADER $UPLOADERFLAGS $BUILD_DIR/${PROGNAME}.bin", + ) upload_actions = [ - env.VerboseAction(" ".join(["$OBJCOPY","-I","ihex","-O","binary", - "$SOURCE", "$BUILD_DIR/${PROGNAME}.bin"]), "Creating binary"), - env.VerboseAction("$UPLOADCMD", "Uploading ${PROGNAME}.bin") + env.VerboseAction( + " ".join( + [ + "$OBJCOPY", + "-I", + "ihex", + "-O", + "binary", + "$SOURCE", + "$BUILD_DIR/${PROGNAME}.bin", + ] + ), + "Creating binary", + ), + env.VerboseAction("$UPLOADCMD", "Uploading ${PROGNAME}.bin"), ] # custom upload tool From b4b7fe18241c67d3a9584f9ab7ce5288c1afb042 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Mon, 11 Apr 2022 12:09:00 +0300 Subject: [PATCH 14/17] Uppercase board manifest for the target devices --- boards/{ch559.json => CH559.json} | 0 boards/{n79e8432.json => N79E8432.json} | 0 boards/{n79e844.json => N79E844.json} | 0 boards/{n79e845.json => N79E845.json} | 0 boards/{n79e854.json => N79E854.json} | 0 boards/{n79e855.json => N79E855.json} | 0 boards/{stc15f204ea.json => STC15F204EA.json} | 0 boards/{stc15f2k60s2.json => STC15F2K60S2.json} | 0 boards/{stc15w204s.json => STC15W204S.json} | 0 boards/{stc15w404as.json => STC15W404AS.json} | 0 boards/{stc15w408as.json => STC15W408AS.json} | 0 boards/{stc89c52rc.json => STC89C52RC.json} | 0 examples/assembly-blink/platformio.ini | 2 +- examples/native-blink/platformio.ini | 6 +++--- examples/stc-blink/platformio.ini | 8 ++++---- examples/stc-header/platformio.ini | 8 ++++---- 16 files changed, 12 insertions(+), 12 deletions(-) rename boards/{ch559.json => CH559.json} (100%) rename boards/{n79e8432.json => N79E8432.json} (100%) rename boards/{n79e844.json => N79E844.json} (100%) rename boards/{n79e845.json => N79E845.json} (100%) rename boards/{n79e854.json => N79E854.json} (100%) rename boards/{n79e855.json => N79E855.json} (100%) rename boards/{stc15f204ea.json => STC15F204EA.json} (100%) rename boards/{stc15f2k60s2.json => STC15F2K60S2.json} (100%) rename boards/{stc15w204s.json => STC15W204S.json} (100%) rename boards/{stc15w404as.json => STC15W404AS.json} (100%) rename boards/{stc15w408as.json => STC15W408AS.json} (100%) rename boards/{stc89c52rc.json => STC89C52RC.json} (100%) diff --git a/boards/ch559.json b/boards/CH559.json similarity index 100% rename from boards/ch559.json rename to boards/CH559.json diff --git a/boards/n79e8432.json b/boards/N79E8432.json similarity index 100% rename from boards/n79e8432.json rename to boards/N79E8432.json diff --git a/boards/n79e844.json b/boards/N79E844.json similarity index 100% rename from boards/n79e844.json rename to boards/N79E844.json diff --git a/boards/n79e845.json b/boards/N79E845.json similarity index 100% rename from boards/n79e845.json rename to boards/N79E845.json diff --git a/boards/n79e854.json b/boards/N79E854.json similarity index 100% rename from boards/n79e854.json rename to boards/N79E854.json diff --git a/boards/n79e855.json b/boards/N79E855.json similarity index 100% rename from boards/n79e855.json rename to boards/N79E855.json diff --git a/boards/stc15f204ea.json b/boards/STC15F204EA.json similarity index 100% rename from boards/stc15f204ea.json rename to boards/STC15F204EA.json diff --git a/boards/stc15f2k60s2.json b/boards/STC15F2K60S2.json similarity index 100% rename from boards/stc15f2k60s2.json rename to boards/STC15F2K60S2.json diff --git a/boards/stc15w204s.json b/boards/STC15W204S.json similarity index 100% rename from boards/stc15w204s.json rename to boards/STC15W204S.json diff --git a/boards/stc15w404as.json b/boards/STC15W404AS.json similarity index 100% rename from boards/stc15w404as.json rename to boards/STC15W404AS.json diff --git a/boards/stc15w408as.json b/boards/STC15W408AS.json similarity index 100% rename from boards/stc15w408as.json rename to boards/STC15W408AS.json diff --git a/boards/stc89c52rc.json b/boards/STC89C52RC.json similarity index 100% rename from boards/stc89c52rc.json rename to boards/STC89C52RC.json diff --git a/examples/assembly-blink/platformio.ini b/examples/assembly-blink/platformio.ini index 15f4256..113b6da 100644 --- a/examples/assembly-blink/platformio.ini +++ b/examples/assembly-blink/platformio.ini @@ -10,4 +10,4 @@ [env:stc15f204ea] platform = intel_mcs51 -board = stc15f204ea +board = STC15F204EA diff --git a/examples/native-blink/platformio.ini b/examples/native-blink/platformio.ini index 243b804..c6542b0 100644 --- a/examples/native-blink/platformio.ini +++ b/examples/native-blink/platformio.ini @@ -9,12 +9,12 @@ [env:stc15f204ea] platform = intel_mcs51 -board = stc15f204ea +board = STC15F204EA [env:stc15w404as] platform = intel_mcs51 -board = stc15w404as +board = STC15W404AS [env:stc15w408as] platform = intel_mcs51 -board = stc15w408as +board = STC15W408AS diff --git a/examples/stc-blink/platformio.ini b/examples/stc-blink/platformio.ini index 8890b51..e24ecd8 100644 --- a/examples/stc-blink/platformio.ini +++ b/examples/stc-blink/platformio.ini @@ -10,16 +10,16 @@ [env:stc15f204ea] platform = intel_mcs51 -board = stc15f204ea +board = STC15F204EA [env:stc15w204s] platform = intel_mcs51 -board = stc15w204s +board = STC15W204S [env:stc15w404as] platform = intel_mcs51 -board = stc15w404as +board = STC15W404AS [env:stc15w408as] platform = intel_mcs51 -board = stc15w408as +board = STC15W408AS diff --git a/examples/stc-header/platformio.ini b/examples/stc-header/platformio.ini index 8890b51..e24ecd8 100644 --- a/examples/stc-header/platformio.ini +++ b/examples/stc-header/platformio.ini @@ -10,16 +10,16 @@ [env:stc15f204ea] platform = intel_mcs51 -board = stc15f204ea +board = STC15F204EA [env:stc15w204s] platform = intel_mcs51 -board = stc15w204s +board = STC15W204S [env:stc15w404as] platform = intel_mcs51 -board = stc15w404as +board = STC15W404AS [env:stc15w408as] platform = intel_mcs51 -board = stc15w408as +board = STC15W408AS From 92c08147017c1d906317c8bbd834fb72f702ba58 Mon Sep 17 00:00:00 2001 From: snovotill <37263727+snovotill@users.noreply.github.com> Date: Mon, 11 Apr 2022 02:35:18 -0700 Subject: [PATCH 15/17] added some new boards and universal header + blink samples (#41) * added some new boards and universal header + blink samples * Update README.md * Added comment explaining interrupt vector nomenclature * Added more board definitions and final cleanup. Done. * Added many more STC MCUs as board files * added all contemporary Nuvoton MCUs * Revert back README * Delete eol.sh * Delete workspace.code-workspace * Convert device targets to uppercase * Fix header case Co-authored-by: snovotill Co-authored-by: Ivan Kravets --- .github/workflows/examples.yml | 2 + boards/AT89S51.json | 27 + boards/AT89S52.json | 27 + boards/Generic8051.json | 21 + boards/Generic8052.json | 21 + boards/IAP12C5A62S2.json | 27 + boards/IAP15F106.json | 27 + boards/IAP15F206A.json | 27 + boards/IAP15F2K61S.json | 27 + boards/IAP15F2K61S2.json | 27 + boards/IAP15F413AD.json | 27 + boards/IAP15W105.json | 27 + boards/IAP15W1K29S.json | 27 + boards/IAP15W205S.json | 27 + boards/IAP15W413AS.json | 27 + boards/IAP15W413S.json | 27 + boards/IAP15W4K58S4.json | 27 + boards/IAP15W4K61S4.json | 27 + boards/IAP15W4K63S4.json | 27 + boards/IRC15F107W.json | 27 + boards/IRC15F2K63S2.json | 27 + boards/IRC15W107.json | 27 + boards/IRC15W1K31S.json | 27 + boards/IRC15W207S.json | 27 + boards/IRC15W415AS.json | 27 + boards/IRC15W415S.json | 27 + boards/ML51BB9AE.json | 27 + boards/ML51DB9AE.json | 27 + boards/ML51EB9AE.json | 27 + boards/ML51EC0AE.json | 27 + boards/ML51FB9AE.json | 27 + boards/ML51LD1AE.json | 27 + boards/ML51OB9AE.json | 27 + boards/ML51PB9AE.json | 27 + boards/ML51PC0AE.json | 27 + boards/ML51SD1AE.json | 27 + boards/ML51TB9AE.json | 27 + boards/ML51TC0AE.json | 27 + boards/ML51TC1AE.json | 27 + boards/ML51TD1AE.json | 27 + boards/ML51UB9AE.json | 27 + boards/ML51UC0AE.json | 27 + boards/ML51XB9AE.json | 27 + boards/ML54LD1AE.json | 27 + boards/ML54MD1AE.json | 27 + boards/ML54SD1AE.json | 27 + boards/ML56LD1AE.json | 27 + boards/ML56MD1AE.json | 27 + boards/ML56SD1AE.json | 27 + boards/MS51BA9AE.json | 27 + boards/MS51DA9AE.json | 27 + boards/MS51EC0AE.json | 27 + boards/MS51FB9AE.json | 27 + boards/MS51FC0AE.json | 27 + boards/MS51IA9AE.json | 27 + boards/MS51PC0AE.json | 27 + boards/MS51TC0AE.json | 27 + boards/MS51XB9AE.json | 27 + boards/MS51XB9BE.json | 27 + boards/MS51XC0BE.json | 27 + boards/N76E003.json | 26 + boards/N76E616.json | 26 + boards/N76E885.json | 26 + boards/N78E055.json | 27 + boards/N78E059.json | 27 + boards/N78E366.json | 26 + boards/N78E517.json | 26 + boards/N79E352.json | 26 + boards/N79E715.json | 26 + boards/N79E813.json | 27 + boards/N79E8132.json | 27 + boards/N79E814.json | 27 + boards/N79E815.json | 27 + boards/N79E822.json | 27 + boards/N79E823.json | 27 + boards/N79E824.json | 27 + boards/N79E825.json | 27 + boards/N79E843.json | 27 + boards/N79E8432.json | 9 +- boards/N79E844.json | 10 +- boards/N79E845.json | 10 +- boards/N79E854.json | 10 +- boards/N79E855.json | 9 +- boards/N79E875.json | 26 + boards/STC12C5A08S2.json | 27 + boards/STC12C5A16S2.json | 27 + boards/STC12C5A32S2.json | 27 + boards/STC12C5A40S2.json | 27 + boards/STC12C5A48S2.json | 27 + boards/STC12C5A52S2.json | 27 + boards/STC12C5A56S2.json | 27 + boards/STC12C5A60S2.json | 27 + boards/STC15F100.json | 27 + boards/STC15F100W.json | 27 + boards/STC15F101.json | 27 + boards/STC15F101E.json | 27 + boards/STC15F101W.json | 27 + boards/STC15F102.json | 27 + boards/STC15F102E.json | 27 + boards/STC15F102W.json | 27 + boards/STC15F103.json | 27 + boards/STC15F103E.json | 27 + boards/STC15F103W.json | 27 + boards/STC15F104.json | 27 + boards/STC15F104E.json | 27 + boards/STC15F104W.json | 27 + boards/STC15F105.json | 27 + boards/STC15F105E.json | 27 + boards/STC15F105W.json | 27 + boards/STC15F201A.json | 27 + boards/STC15F201EA.json | 27 + boards/STC15F202A.json | 27 + boards/STC15F202EA.json | 27 + boards/STC15F203A.json | 27 + boards/STC15F203EA.json | 27 + boards/STC15F204A.json | 27 + boards/STC15F204EA.json | 7 +- boards/STC15F205A.json | 27 + boards/STC15F205EA.json | 27 + boards/STC15F2K08S2.json | 27 + boards/STC15F2K16S2.json | 27 + boards/STC15F2K24AS.json | 27 + boards/STC15F2K24S2.json | 27 + boards/STC15F2K32S2.json | 27 + boards/STC15F2K40S2.json | 27 + boards/STC15F2K48S2.json | 27 + boards/STC15F2K52S2.json | 27 + boards/STC15F2K56S2.json | 27 + boards/STC15F2K60S2.json | 11 +- boards/STC15F408AD.json | 27 + boards/STC15W100.json | 27 + boards/STC15W101.json | 27 + boards/STC15W102.json | 27 + boards/STC15W103.json | 27 + boards/STC15W104.json | 27 + boards/STC15W1K16S.json | 27 + boards/STC15W1K20S.json | 27 + boards/STC15W1K24S.json | 27 + boards/STC15W201S.json | 27 + boards/STC15W202S.json | 27 + boards/STC15W203S.json | 27 + boards/STC15W204S.json | 7 +- boards/STC15W401AS.json | 27 + boards/STC15W402AS.json | 27 + boards/STC15W404AS.json | 9 +- boards/STC15W404S.json | 27 + boards/STC15W408AS.json | 7 +- boards/STC15W408S.json | 27 + boards/STC15W410S.json | 27 + boards/STC15W4K16S4.json | 27 + boards/STC15W4K32S4.json | 27 + boards/STC15W4K40S4.json | 27 + boards/STC15W4K48S4.json | 27 + boards/STC15W4K56S4.json | 27 + boards/STC89C516RD+.json | 27 + boards/STC89C51RC.json | 27 + boards/STC89C52RC.json | 7 +- boards/STC89C53RC.json | 27 + boards/STC89C54RD+.json | 27 + boards/STC89C58RD+.json | 27 + boards/STC8A4K16S2A12.json | 27 + boards/STC8A4K32S2A12.json | 27 + boards/STC8A4K60S2A12.json | 27 + boards/STC8A4K64S2A12.json | 27 + boards/STC8A8K16D4.json | 27 + boards/STC8A8K16S4A12.json | 27 + boards/STC8A8K32D4.json | 27 + boards/STC8A8K32S4A12.json | 27 + boards/STC8A8K60D4.json | 27 + boards/STC8A8K60S4A12.json | 27 + boards/STC8A8K64D4.json | 27 + boards/STC8A8K64S4A12.json | 27 + boards/STC8C1K08.json | 27 + boards/STC8C1K12.json | 27 + boards/STC8C2K16S2.json | 27 + boards/STC8C2K16S4.json | 27 + boards/STC8C2K32S2.json | 27 + boards/STC8C2K32S4.json | 27 + boards/STC8C2K60S2.json | 27 + boards/STC8C2K60S4.json | 27 + boards/STC8C2K64S2.json | 27 + boards/STC8C2K64S4.json | 27 + boards/STC8F1K08.json | 27 + boards/STC8F1K08S.json | 27 + boards/STC8F1K08S2.json | 27 + boards/STC8F1K08S2A10.json | 27 + boards/STC8F1K17.json | 27 + boards/STC8F1K17S2.json | 27 + boards/STC8F2K08S2.json | 27 + boards/STC8F2K16S2.json | 27 + boards/STC8F2K16S4.json | 27 + boards/STC8F2K32S2.json | 27 + boards/STC8F2K32S4.json | 27 + boards/STC8F2K60S2.json | 27 + boards/STC8F2K60S4.json | 27 + boards/STC8F2K64S2.json | 27 + boards/STC8F2K64S4.json | 27 + boards/STC8G1K08.json | 27 + boards/STC8G1K08A.json | 27 + boards/STC8G1K08T.json | 27 + boards/STC8G1K12.json | 27 + boards/STC8G1K12A.json | 27 + boards/STC8G1K17.json | 27 + boards/STC8G1K17A.json | 27 + boards/STC8G1K17T.json | 27 + boards/STC8G2K16S2.json | 27 + boards/STC8G2K16S4.json | 27 + boards/STC8G2K32S2.json | 27 + boards/STC8G2K32S4.json | 27 + boards/STC8G2K60S2.json | 27 + boards/STC8G2K60S4.json | 27 + boards/STC8G2K64S2.json | 27 + boards/STC8G2K64S4.json | 27 + boards/STC8H04.json | 27 + boards/STC8H04A10.json | 27 + boards/STC8H1K08.json | 27 + boards/STC8H1K08S2.json | 27 + boards/STC8H1K08S2A10.json | 27 + boards/STC8H1K12.json | 27 + boards/STC8H1K16.json | 27 + boards/STC8H1K16S2.json | 27 + boards/STC8H1K16S2A10.json | 27 + boards/STC8H1K17.json | 27 + boards/STC8H1K24.json | 27 + boards/STC8H1K28.json | 27 + boards/STC8H1K32S2.json | 27 + boards/STC8H1K32S2A10.json | 27 + boards/STC8H1K33.json | 27 + boards/STC8H1K64S2A10.json | 27 + boards/STC8H2K32T.json | 27 + boards/STC8H2K48T.json | 27 + boards/STC8H2K60T.json | 27 + boards/STC8H2K64T.json | 27 + boards/STC8H3K32S2.json | 27 + boards/STC8H3K32S4.json | 27 + boards/STC8H3K48S2.json | 27 + boards/STC8H3K48S4.json | 27 + boards/STC8H3K60S2.json | 27 + boards/STC8H3K60S4.json | 27 + boards/STC8H3K64S2.json | 27 + boards/STC8H3K64S4.json | 27 + boards/STC8H4K32LCD.json | 27 + boards/STC8H4K32TLCD.json | 27 + boards/STC8H4K32TLR.json | 27 + boards/STC8H4K48LCD.json | 27 + boards/STC8H4K48TLCD.json | 27 + boards/STC8H4K48TLR.json | 27 + boards/STC8H4K60LCD.json | 27 + boards/STC8H4K60TLCD.json | 27 + boards/STC8H4K60TLR.json | 27 + boards/STC8H4K64LCD.json | 27 + boards/STC8H4K64TLCD.json | 27 + boards/STC8H4K64TLR.json | 27 + boards/STC8H8K32U.json | 27 + boards/STC8H8K48U.json | 27 + boards/STC8H8K60U.json | 27 + boards/STC8H8K64U.json | 27 + boards/W79E2051.json | 27 + boards/W79E4051.json | 27 + boards/W79E632.json | 26 + boards/W79E633.json | 26 + boards/W79E658.json | 27 + boards/W79E659.json | 27 + boards/W79E8213.json | 26 + examples/anymcu-blink/include/README | 39 + examples/anymcu-blink/lib/README | 46 ++ examples/anymcu-blink/platformio.ini | 13 + examples/anymcu-blink/src/Generic8051.h | 217 +++++ examples/anymcu-blink/src/Generic8052.h | 246 ++++++ examples/anymcu-blink/src/N76E003.h | 968 +++++++++++++++++++++++ examples/anymcu-blink/src/STC12C20xx.h | 340 ++++++++ examples/anymcu-blink/src/STC12C54xx.h | 340 ++++++++ examples/anymcu-blink/src/STC12C56xx.h | 339 ++++++++ examples/anymcu-blink/src/STC12C5Axx.h | 420 ++++++++++ examples/anymcu-blink/src/STC15.h | 406 ++++++++++ examples/anymcu-blink/src/STC15W4K.h | 472 +++++++++++ examples/anymcu-blink/src/STC89xx.h | 298 +++++++ examples/anymcu-blink/src/STC8Fxx.h | 715 +++++++++++++++++ examples/anymcu-blink/src/STC90C5xAD.h | 298 +++++++ examples/anymcu-blink/src/delay.c | 50 ++ examples/anymcu-blink/src/delay.h | 9 + examples/anymcu-blink/src/main.c | 106 +++ examples/anymcu-blink/test/README | 11 + examples/anymcu-header/.gitignore | 2 + examples/anymcu-header/.travis.yml | 67 ++ examples/anymcu-header/README.rst | 38 + examples/anymcu-header/include/README | 39 + examples/anymcu-header/lib/README | 46 ++ examples/anymcu-header/platformio.ini | 25 + examples/anymcu-header/src/Generic8051.h | 217 +++++ examples/anymcu-header/src/Generic8052.h | 246 ++++++ examples/anymcu-header/src/N76E003.h | 968 +++++++++++++++++++++++ examples/anymcu-header/src/STC12C20xx.h | 340 ++++++++ examples/anymcu-header/src/STC12C54xx.h | 340 ++++++++ examples/anymcu-header/src/STC12C56xx.h | 339 ++++++++ examples/anymcu-header/src/STC12C5Axx.h | 420 ++++++++++ examples/anymcu-header/src/STC15.h | 406 ++++++++++ examples/anymcu-header/src/STC15W4K.h | 472 +++++++++++ examples/anymcu-header/src/STC89xx.h | 298 +++++++ examples/anymcu-header/src/STC8Fxx.h | 715 +++++++++++++++++ examples/anymcu-header/src/STC90C5xAD.h | 298 +++++++ examples/anymcu-header/src/main.c | 36 + examples/anymcu-header/test/README | 11 + 303 files changed, 17510 insertions(+), 25 deletions(-) create mode 100644 boards/AT89S51.json create mode 100644 boards/AT89S52.json create mode 100644 boards/Generic8051.json create mode 100644 boards/Generic8052.json create mode 100644 boards/IAP12C5A62S2.json create mode 100644 boards/IAP15F106.json create mode 100644 boards/IAP15F206A.json create mode 100644 boards/IAP15F2K61S.json create mode 100644 boards/IAP15F2K61S2.json create mode 100644 boards/IAP15F413AD.json create mode 100644 boards/IAP15W105.json create mode 100644 boards/IAP15W1K29S.json create mode 100644 boards/IAP15W205S.json create mode 100644 boards/IAP15W413AS.json create mode 100644 boards/IAP15W413S.json create mode 100644 boards/IAP15W4K58S4.json create mode 100644 boards/IAP15W4K61S4.json create mode 100644 boards/IAP15W4K63S4.json create mode 100644 boards/IRC15F107W.json create mode 100644 boards/IRC15F2K63S2.json create mode 100644 boards/IRC15W107.json create mode 100644 boards/IRC15W1K31S.json create mode 100644 boards/IRC15W207S.json create mode 100644 boards/IRC15W415AS.json create mode 100644 boards/IRC15W415S.json create mode 100644 boards/ML51BB9AE.json create mode 100644 boards/ML51DB9AE.json create mode 100644 boards/ML51EB9AE.json create mode 100644 boards/ML51EC0AE.json create mode 100644 boards/ML51FB9AE.json create mode 100644 boards/ML51LD1AE.json create mode 100644 boards/ML51OB9AE.json create mode 100644 boards/ML51PB9AE.json create mode 100644 boards/ML51PC0AE.json create mode 100644 boards/ML51SD1AE.json create mode 100644 boards/ML51TB9AE.json create mode 100644 boards/ML51TC0AE.json create mode 100644 boards/ML51TC1AE.json create mode 100644 boards/ML51TD1AE.json create mode 100644 boards/ML51UB9AE.json create mode 100644 boards/ML51UC0AE.json create mode 100644 boards/ML51XB9AE.json create mode 100644 boards/ML54LD1AE.json create mode 100644 boards/ML54MD1AE.json create mode 100644 boards/ML54SD1AE.json create mode 100644 boards/ML56LD1AE.json create mode 100644 boards/ML56MD1AE.json create mode 100644 boards/ML56SD1AE.json create mode 100644 boards/MS51BA9AE.json create mode 100644 boards/MS51DA9AE.json create mode 100644 boards/MS51EC0AE.json create mode 100644 boards/MS51FB9AE.json create mode 100644 boards/MS51FC0AE.json create mode 100644 boards/MS51IA9AE.json create mode 100644 boards/MS51PC0AE.json create mode 100644 boards/MS51TC0AE.json create mode 100644 boards/MS51XB9AE.json create mode 100644 boards/MS51XB9BE.json create mode 100644 boards/MS51XC0BE.json create mode 100644 boards/N76E003.json create mode 100644 boards/N76E616.json create mode 100644 boards/N76E885.json create mode 100644 boards/N78E055.json create mode 100644 boards/N78E059.json create mode 100644 boards/N78E366.json create mode 100644 boards/N78E517.json create mode 100644 boards/N79E352.json create mode 100644 boards/N79E715.json create mode 100644 boards/N79E813.json create mode 100644 boards/N79E8132.json create mode 100644 boards/N79E814.json create mode 100644 boards/N79E815.json create mode 100644 boards/N79E822.json create mode 100644 boards/N79E823.json create mode 100644 boards/N79E824.json create mode 100644 boards/N79E825.json create mode 100644 boards/N79E843.json create mode 100644 boards/N79E875.json create mode 100644 boards/STC12C5A08S2.json create mode 100644 boards/STC12C5A16S2.json create mode 100644 boards/STC12C5A32S2.json create mode 100644 boards/STC12C5A40S2.json create mode 100644 boards/STC12C5A48S2.json create mode 100644 boards/STC12C5A52S2.json create mode 100644 boards/STC12C5A56S2.json create mode 100644 boards/STC12C5A60S2.json create mode 100644 boards/STC15F100.json create mode 100644 boards/STC15F100W.json create mode 100644 boards/STC15F101.json create mode 100644 boards/STC15F101E.json create mode 100644 boards/STC15F101W.json create mode 100644 boards/STC15F102.json create mode 100644 boards/STC15F102E.json create mode 100644 boards/STC15F102W.json create mode 100644 boards/STC15F103.json create mode 100644 boards/STC15F103E.json create mode 100644 boards/STC15F103W.json create mode 100644 boards/STC15F104.json create mode 100644 boards/STC15F104E.json create mode 100644 boards/STC15F104W.json create mode 100644 boards/STC15F105.json create mode 100644 boards/STC15F105E.json create mode 100644 boards/STC15F105W.json create mode 100644 boards/STC15F201A.json create mode 100644 boards/STC15F201EA.json create mode 100644 boards/STC15F202A.json create mode 100644 boards/STC15F202EA.json create mode 100644 boards/STC15F203A.json create mode 100644 boards/STC15F203EA.json create mode 100644 boards/STC15F204A.json create mode 100644 boards/STC15F205A.json create mode 100644 boards/STC15F205EA.json create mode 100644 boards/STC15F2K08S2.json create mode 100644 boards/STC15F2K16S2.json create mode 100644 boards/STC15F2K24AS.json create mode 100644 boards/STC15F2K24S2.json create mode 100644 boards/STC15F2K32S2.json create mode 100644 boards/STC15F2K40S2.json create mode 100644 boards/STC15F2K48S2.json create mode 100644 boards/STC15F2K52S2.json create mode 100644 boards/STC15F2K56S2.json create mode 100644 boards/STC15F408AD.json create mode 100644 boards/STC15W100.json create mode 100644 boards/STC15W101.json create mode 100644 boards/STC15W102.json create mode 100644 boards/STC15W103.json create mode 100644 boards/STC15W104.json create mode 100644 boards/STC15W1K16S.json create mode 100644 boards/STC15W1K20S.json create mode 100644 boards/STC15W1K24S.json create mode 100644 boards/STC15W201S.json create mode 100644 boards/STC15W202S.json create mode 100644 boards/STC15W203S.json create mode 100644 boards/STC15W401AS.json create mode 100644 boards/STC15W402AS.json create mode 100644 boards/STC15W404S.json create mode 100644 boards/STC15W408S.json create mode 100644 boards/STC15W410S.json create mode 100644 boards/STC15W4K16S4.json create mode 100644 boards/STC15W4K32S4.json create mode 100644 boards/STC15W4K40S4.json create mode 100644 boards/STC15W4K48S4.json create mode 100644 boards/STC15W4K56S4.json create mode 100644 boards/STC89C516RD+.json create mode 100644 boards/STC89C51RC.json create mode 100644 boards/STC89C53RC.json create mode 100644 boards/STC89C54RD+.json create mode 100644 boards/STC89C58RD+.json create mode 100644 boards/STC8A4K16S2A12.json create mode 100644 boards/STC8A4K32S2A12.json create mode 100644 boards/STC8A4K60S2A12.json create mode 100644 boards/STC8A4K64S2A12.json create mode 100644 boards/STC8A8K16D4.json create mode 100644 boards/STC8A8K16S4A12.json create mode 100644 boards/STC8A8K32D4.json create mode 100644 boards/STC8A8K32S4A12.json create mode 100644 boards/STC8A8K60D4.json create mode 100644 boards/STC8A8K60S4A12.json create mode 100644 boards/STC8A8K64D4.json create mode 100644 boards/STC8A8K64S4A12.json create mode 100644 boards/STC8C1K08.json create mode 100644 boards/STC8C1K12.json create mode 100644 boards/STC8C2K16S2.json create mode 100644 boards/STC8C2K16S4.json create mode 100644 boards/STC8C2K32S2.json create mode 100644 boards/STC8C2K32S4.json create mode 100644 boards/STC8C2K60S2.json create mode 100644 boards/STC8C2K60S4.json create mode 100644 boards/STC8C2K64S2.json create mode 100644 boards/STC8C2K64S4.json create mode 100644 boards/STC8F1K08.json create mode 100644 boards/STC8F1K08S.json create mode 100644 boards/STC8F1K08S2.json create mode 100644 boards/STC8F1K08S2A10.json create mode 100644 boards/STC8F1K17.json create mode 100644 boards/STC8F1K17S2.json create mode 100644 boards/STC8F2K08S2.json create mode 100644 boards/STC8F2K16S2.json create mode 100644 boards/STC8F2K16S4.json create mode 100644 boards/STC8F2K32S2.json create mode 100644 boards/STC8F2K32S4.json create mode 100644 boards/STC8F2K60S2.json create mode 100644 boards/STC8F2K60S4.json create mode 100644 boards/STC8F2K64S2.json create mode 100644 boards/STC8F2K64S4.json create mode 100644 boards/STC8G1K08.json create mode 100644 boards/STC8G1K08A.json create mode 100644 boards/STC8G1K08T.json create mode 100644 boards/STC8G1K12.json create mode 100644 boards/STC8G1K12A.json create mode 100644 boards/STC8G1K17.json create mode 100644 boards/STC8G1K17A.json create mode 100644 boards/STC8G1K17T.json create mode 100644 boards/STC8G2K16S2.json create mode 100644 boards/STC8G2K16S4.json create mode 100644 boards/STC8G2K32S2.json create mode 100644 boards/STC8G2K32S4.json create mode 100644 boards/STC8G2K60S2.json create mode 100644 boards/STC8G2K60S4.json create mode 100644 boards/STC8G2K64S2.json create mode 100644 boards/STC8G2K64S4.json create mode 100644 boards/STC8H04.json create mode 100644 boards/STC8H04A10.json create mode 100644 boards/STC8H1K08.json create mode 100644 boards/STC8H1K08S2.json create mode 100644 boards/STC8H1K08S2A10.json create mode 100644 boards/STC8H1K12.json create mode 100644 boards/STC8H1K16.json create mode 100644 boards/STC8H1K16S2.json create mode 100644 boards/STC8H1K16S2A10.json create mode 100644 boards/STC8H1K17.json create mode 100644 boards/STC8H1K24.json create mode 100644 boards/STC8H1K28.json create mode 100644 boards/STC8H1K32S2.json create mode 100644 boards/STC8H1K32S2A10.json create mode 100644 boards/STC8H1K33.json create mode 100644 boards/STC8H1K64S2A10.json create mode 100644 boards/STC8H2K32T.json create mode 100644 boards/STC8H2K48T.json create mode 100644 boards/STC8H2K60T.json create mode 100644 boards/STC8H2K64T.json create mode 100644 boards/STC8H3K32S2.json create mode 100644 boards/STC8H3K32S4.json create mode 100644 boards/STC8H3K48S2.json create mode 100644 boards/STC8H3K48S4.json create mode 100644 boards/STC8H3K60S2.json create mode 100644 boards/STC8H3K60S4.json create mode 100644 boards/STC8H3K64S2.json create mode 100644 boards/STC8H3K64S4.json create mode 100644 boards/STC8H4K32LCD.json create mode 100644 boards/STC8H4K32TLCD.json create mode 100644 boards/STC8H4K32TLR.json create mode 100644 boards/STC8H4K48LCD.json create mode 100644 boards/STC8H4K48TLCD.json create mode 100644 boards/STC8H4K48TLR.json create mode 100644 boards/STC8H4K60LCD.json create mode 100644 boards/STC8H4K60TLCD.json create mode 100644 boards/STC8H4K60TLR.json create mode 100644 boards/STC8H4K64LCD.json create mode 100644 boards/STC8H4K64TLCD.json create mode 100644 boards/STC8H4K64TLR.json create mode 100644 boards/STC8H8K32U.json create mode 100644 boards/STC8H8K48U.json create mode 100644 boards/STC8H8K60U.json create mode 100644 boards/STC8H8K64U.json create mode 100644 boards/W79E2051.json create mode 100644 boards/W79E4051.json create mode 100644 boards/W79E632.json create mode 100644 boards/W79E633.json create mode 100644 boards/W79E658.json create mode 100644 boards/W79E659.json create mode 100644 boards/W79E8213.json create mode 100644 examples/anymcu-blink/include/README create mode 100644 examples/anymcu-blink/lib/README create mode 100644 examples/anymcu-blink/platformio.ini create mode 100644 examples/anymcu-blink/src/Generic8051.h create mode 100644 examples/anymcu-blink/src/Generic8052.h create mode 100644 examples/anymcu-blink/src/N76E003.h create mode 100644 examples/anymcu-blink/src/STC12C20xx.h create mode 100644 examples/anymcu-blink/src/STC12C54xx.h create mode 100644 examples/anymcu-blink/src/STC12C56xx.h create mode 100644 examples/anymcu-blink/src/STC12C5Axx.h create mode 100644 examples/anymcu-blink/src/STC15.h create mode 100644 examples/anymcu-blink/src/STC15W4K.h create mode 100644 examples/anymcu-blink/src/STC89xx.h create mode 100644 examples/anymcu-blink/src/STC8Fxx.h create mode 100644 examples/anymcu-blink/src/STC90C5xAD.h create mode 100644 examples/anymcu-blink/src/delay.c create mode 100644 examples/anymcu-blink/src/delay.h create mode 100644 examples/anymcu-blink/src/main.c create mode 100644 examples/anymcu-blink/test/README create mode 100644 examples/anymcu-header/.gitignore create mode 100644 examples/anymcu-header/.travis.yml create mode 100644 examples/anymcu-header/README.rst create mode 100644 examples/anymcu-header/include/README create mode 100644 examples/anymcu-header/lib/README create mode 100644 examples/anymcu-header/platformio.ini create mode 100644 examples/anymcu-header/src/Generic8051.h create mode 100644 examples/anymcu-header/src/Generic8052.h create mode 100644 examples/anymcu-header/src/N76E003.h create mode 100644 examples/anymcu-header/src/STC12C20xx.h create mode 100644 examples/anymcu-header/src/STC12C54xx.h create mode 100644 examples/anymcu-header/src/STC12C56xx.h create mode 100644 examples/anymcu-header/src/STC12C5Axx.h create mode 100644 examples/anymcu-header/src/STC15.h create mode 100644 examples/anymcu-header/src/STC15W4K.h create mode 100644 examples/anymcu-header/src/STC89xx.h create mode 100644 examples/anymcu-header/src/STC8Fxx.h create mode 100644 examples/anymcu-header/src/STC90C5xAD.h create mode 100644 examples/anymcu-header/src/main.c create mode 100644 examples/anymcu-header/test/README diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml index fb5e21e..a32f3b3 100644 --- a/.github/workflows/examples.yml +++ b/.github/workflows/examples.yml @@ -10,6 +10,8 @@ jobs: os: [ubuntu-latest, windows-latest, macos-latest] python-version: [3.7] example: + - "examples/anymcu-blink" + - "examples/anymcu-header" - "examples/assembly-blink" - "examples/native-blink" - "examples/stc-blink" diff --git a/boards/AT89S51.json b/boards/AT89S51.json new file mode 100644 index 0000000..85e1261 --- /dev/null +++ b/boards/AT89S51.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DAT89S51 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_AT89S51", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "at89s51", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 4096, + "protocol": "avrdude", + "avrdude_protocol": "AT89S51", + "protocols": [ + "usbasp", + "avrisp" + ] + }, + "name": "Generic AT89S51", + "url": "https://www.microchip.com/wwwproducts/en/AT89S51", + "vendor": "Microchip & Atmel" +} diff --git a/boards/AT89S52.json b/boards/AT89S52.json new file mode 100644 index 0000000..d7256a7 --- /dev/null +++ b/boards/AT89S52.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DAT89S52 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_AT89S52", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 8192, + "size_heap": 64, + "mcu": "at89s52", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 8192, + "protocol": "avrdude", + "avrdude_protocol": "AT89S52", + "protocols": [ + "usbasp", + "avrisp" + ] + }, + "name": "Generic AT89S52", + "url": "https://www.microchip.com/wwwproducts/en/AT89S52", + "vendor": "Microchip & Atmel" +} diff --git a/boards/Generic8051.json b/boards/Generic8051.json new file mode 100644 index 0000000..ac4655a --- /dev/null +++ b/boards/Generic8051.json @@ -0,0 +1,21 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DGeneric8051 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_Generic8051", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "8051", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 4096 + }, + "name": "Generic 8051", + "url": "https://en.wikipedia.org/wiki/Intel_8051", + "vendor": "Intel & Licensees" +} diff --git a/boards/Generic8052.json b/boards/Generic8052.json new file mode 100644 index 0000000..81e70ad --- /dev/null +++ b/boards/Generic8052.json @@ -0,0 +1,21 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DGeneric8052 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_Generic8052", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 8192, + "size_heap": 64, + "mcu": "8052", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 8192 + }, + "name": "Generic 8052", + "url": "https://en.wikipedia.org/wiki/Intel_8051", + "vendor": "Intel & licensees" +} diff --git a/boards/IAP12C5A62S2.json b/boards/IAP12C5A62S2.json new file mode 100644 index 0000000..519db47 --- /dev/null +++ b/boards/IAP12C5A62S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DIAP12C5A62S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 63488, + "size_heap": 128, + "mcu": "iap12c5a62s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 63488, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP12C5A62S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/IAP15F106.json b/boards/IAP15F106.json new file mode 100644 index 0000000..a867695 --- /dev/null +++ b/boards/IAP15F106.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DIAP15F106 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 6144, + "size_heap": 64, + "mcu": "iap15f106", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 6144, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15F106", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/IAP15F206A.json b/boards/IAP15F206A.json new file mode 100644 index 0000000..8f2fb1f --- /dev/null +++ b/boards/IAP15F206A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DIAP15F206A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 6144, + "size_heap": 64, + "mcu": "iap15f206a", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 6144, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15F206A", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/IAP15F2K61S.json b/boards/IAP15F2K61S.json new file mode 100644 index 0000000..57c0b62 --- /dev/null +++ b/boards/IAP15F2K61S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS -DIAP15F2K61S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 62464, + "size_heap": 128, + "mcu": "iap15f2k61s", + "cpu": "mcs51", + "variant": "stc15f2kxxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 62464, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15F2K61S", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/IAP15F2K61S2.json b/boards/IAP15F2K61S2.json new file mode 100644 index 0000000..efd1395 --- /dev/null +++ b/boards/IAP15F2K61S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DIAP15F2K61S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 62464, + "size_heap": 128, + "mcu": "iap15f2k61s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 62464, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15F2K61S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/IAP15F413AD.json b/boards/IAP15F413AD.json new file mode 100644 index 0000000..1c319ca --- /dev/null +++ b/boards/IAP15F413AD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F4XXAD -DIAP15F413AD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F4XXAD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 13312, + "size_heap": 128, + "mcu": "iap15f413ad", + "cpu": "mcs51", + "variant": "stc15f4xxad" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 13312, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15F413AD", + "url": "http://www.stcmicro.com/STC/STC15F408AD.html", + "vendor": "STC" +} diff --git a/boards/IAP15W105.json b/boards/IAP15W105.json new file mode 100644 index 0000000..e3001da --- /dev/null +++ b/boards/IAP15W105.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W10X -DIAP15W105 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 5120, + "size_heap": 64, + "mcu": "iap15w105", + "cpu": "mcs51", + "variant": "stc15w10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 5120, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W105", + "url": "https://www.stcmicro.com/STC/STC15W104.html", + "vendor": "STC" +} diff --git a/boards/IAP15W1K29S.json b/boards/IAP15W1K29S.json new file mode 100644 index 0000000..a1d612e --- /dev/null +++ b/boards/IAP15W1K29S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W1KXXS -DIAP15W1k29S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W1KXXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 768, + "size_code": 29696, + "size_heap": 128, + "mcu": "iap15w1k29s", + "cpu": "mcs51", + "variant": "stc15w1kxxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 29696, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W1K29S", + "url": "http://www.stcmicro.com/STC/STC15W1K24S.html", + "vendor": "STC" +} diff --git a/boards/IAP15W205S.json b/boards/IAP15W205S.json new file mode 100644 index 0000000..47e25a9 --- /dev/null +++ b/boards/IAP15W205S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W20XS -DIAP15W205S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W20XS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 5120, + "size_heap": 64, + "mcu": "iap15w205s", + "cpu": "mcs51", + "variant": "stc15w20xs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 5120, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W205S", + "url": "https://www.stcmicro.com/STC/STC15W204S.html", + "vendor": "STC" +} diff --git a/boards/IAP15W413AS.json b/boards/IAP15W413AS.json new file mode 100644 index 0000000..7b9ba6d --- /dev/null +++ b/boards/IAP15W413AS.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W40XAS -DIAP15W413AS -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W40XAS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 13312, + "size_heap": 128, + "mcu": "iap15w413as", + "cpu": "mcs51", + "variant": "stc15w40xas" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 13312, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W413AS", + "url": "https://www.stcmicro.com/STC/STC15W408AS.html", + "vendor": "STC" +} diff --git a/boards/IAP15W413S.json b/boards/IAP15W413S.json new file mode 100644 index 0000000..b631b4b --- /dev/null +++ b/boards/IAP15W413S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4XXS -DIAP15W413S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4XXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 13312, + "size_heap": 128, + "mcu": "iap15w413s", + "cpu": "mcs51", + "variant": "stc15w4xxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 13312, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W413S", + "url": "http://www.stcmicro.com/STC/STC15W408S.html", + "vendor": "STC" +} diff --git a/boards/IAP15W4K58S4.json b/boards/IAP15W4K58S4.json new file mode 100644 index 0000000..1abb590 --- /dev/null +++ b/boards/IAP15W4K58S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DIAP15W4K58S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 59392, + "size_heap": 128, + "mcu": "iap15w4k58s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 59392, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W4K58S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/IAP15W4K61S4.json b/boards/IAP15W4K61S4.json new file mode 100644 index 0000000..f8e652a --- /dev/null +++ b/boards/IAP15W4K61S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DIAP15W4K61S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 62464, + "size_heap": 128, + "mcu": "iap15w4k61s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 62464, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W4K61S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/IAP15W4K63S4.json b/boards/IAP15W4K63S4.json new file mode 100644 index 0000000..072b50a --- /dev/null +++ b/boards/IAP15W4K63S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DIAP15W4K63S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 65024, + "size_heap": 128, + "mcu": "iap15w4k63s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 65024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IAP15W4K63S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/IRC15F107W.json b/boards/IRC15F107W.json new file mode 100644 index 0000000..3aaf036 --- /dev/null +++ b/boards/IRC15F107W.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10XW -DIRC15F107W -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10XW", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 6144, + "size_heap": 64, + "mcu": "irc15f107w", + "cpu": "mcs51", + "variant": "stc15f10xw" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 6144, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IRC15F107W", + "url": "https://www.stcmicro.com/STC/STC15F104W.html", + "vendor": "STC" +} diff --git a/boards/IRC15F2K63S2.json b/boards/IRC15F2K63S2.json new file mode 100644 index 0000000..42edb1f --- /dev/null +++ b/boards/IRC15F2K63S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DIRC15F2K63S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 65024, + "size_heap": 128, + "mcu": "irc15f2k63s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 65024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IRC15F2K63S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/IRC15W107.json b/boards/IRC15W107.json new file mode 100644 index 0000000..566bf97 --- /dev/null +++ b/boards/IRC15W107.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W10X -DIRC15W107 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 7168, + "size_heap": 64, + "mcu": "irc15w107", + "cpu": "mcs51", + "variant": "stc15w10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 7168, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IRC15W107", + "url": "https://www.stcmicro.com/STC/STC15W104.html", + "vendor": "STC" +} diff --git a/boards/IRC15W1K31S.json b/boards/IRC15W1K31S.json new file mode 100644 index 0000000..2f605c3 --- /dev/null +++ b/boards/IRC15W1K31S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W1KXXS -DIRC15W1K31S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W1KXXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 768, + "size_code": 32256, + "size_heap": 128, + "mcu": "irc15w1k31s", + "cpu": "mcs51", + "variant": "stc15w1kxxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 32256, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IRC15W1K31S", + "url": "http://www.stcmicro.com/STC/STC15W1K24S.html", + "vendor": "STC" +} diff --git a/boards/IRC15W207S.json b/boards/IRC15W207S.json new file mode 100644 index 0000000..c096b70 --- /dev/null +++ b/boards/IRC15W207S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W20XS -DIRC15W207S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W20XS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 7680, + "size_heap": 64, + "mcu": "irc15w207s", + "cpu": "mcs51", + "variant": "stc15w20xs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 7680, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IRC15W207S", + "url": "https://www.stcmicro.com/STC/STC15W204S.html", + "vendor": "STC" +} diff --git a/boards/IRC15W415AS.json b/boards/IRC15W415AS.json new file mode 100644 index 0000000..3aa30f9 --- /dev/null +++ b/boards/IRC15W415AS.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W40XAS -DIRC15W415AS -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W40XAS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 15872, + "size_heap": 128, + "mcu": "irc15w415as", + "cpu": "mcs51", + "variant": "stc15w40xas" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 15872, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IRC15W415AS", + "url": "https://www.stcmicro.com/STC/STC15W408AS.html", + "vendor": "STC" +} diff --git a/boards/IRC15W415S.json b/boards/IRC15W415S.json new file mode 100644 index 0000000..244f226 --- /dev/null +++ b/boards/IRC15W415S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4XXS -DIRC15W415S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4XXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 15872, + "size_heap": 128, + "mcu": "irc15w415s", + "cpu": "mcs51", + "variant": "stc15w4xxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 15872, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic IRC15W415S", + "url": "http://www.stcmicro.com/STC/STC15W404S.html", + "vendor": "STC" +} diff --git a/boards/ML51BB9AE.json b/boards/ML51BB9AE.json new file mode 100644 index 0000000..2d275f2 --- /dev/null +++ b/boards/ML51BB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51BB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51bb9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51bb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51BB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51DB9AE.json b/boards/ML51DB9AE.json new file mode 100644 index 0000000..f7e4295 --- /dev/null +++ b/boards/ML51DB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51DB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51db9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51db9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51DB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51EB9AE.json b/boards/ML51EB9AE.json new file mode 100644 index 0000000..db4623b --- /dev/null +++ b/boards/ML51EB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51EB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51eb9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51eb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51EB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51EC0AE.json b/boards/ML51EC0AE.json new file mode 100644 index 0000000..a9513b3 --- /dev/null +++ b/boards/ML51EC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51EC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ml51ec0ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51ec0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51EC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51FB9AE.json b/boards/ML51FB9AE.json new file mode 100644 index 0000000..c879de3 --- /dev/null +++ b/boards/ML51FB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51FB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51fb9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51fb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51FB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51LD1AE.json b/boards/ML51LD1AE.json new file mode 100644 index 0000000..f748e9f --- /dev/null +++ b/boards/ML51LD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51LD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml51ld1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51ld1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51LD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51OB9AE.json b/boards/ML51OB9AE.json new file mode 100644 index 0000000..907af67 --- /dev/null +++ b/boards/ML51OB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51OB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51ob9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51ob9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51OB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51PB9AE.json b/boards/ML51PB9AE.json new file mode 100644 index 0000000..55a156d --- /dev/null +++ b/boards/ML51PB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51PB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51pb9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51pb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51PB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51PC0AE.json b/boards/ML51PC0AE.json new file mode 100644 index 0000000..f2d0989 --- /dev/null +++ b/boards/ML51PC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51PC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ml51pc0ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51pc0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51PC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51SD1AE.json b/boards/ML51SD1AE.json new file mode 100644 index 0000000..65293e6 --- /dev/null +++ b/boards/ML51SD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51SD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml51sd1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51sd1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51SD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51TB9AE.json b/boards/ML51TB9AE.json new file mode 100644 index 0000000..d71bb16 --- /dev/null +++ b/boards/ML51TB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51TB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51tb9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51tb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51TB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51TC0AE.json b/boards/ML51TC0AE.json new file mode 100644 index 0000000..372b320 --- /dev/null +++ b/boards/ML51TC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51TC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ml51tc0ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51tc0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51TC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51TC1AE.json b/boards/ML51TC1AE.json new file mode 100644 index 0000000..3d86935 --- /dev/null +++ b/boards/ML51TC1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51TC1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ml51tc1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51tc1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51TC1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51TD1AE.json b/boards/ML51TD1AE.json new file mode 100644 index 0000000..0dab3b7 --- /dev/null +++ b/boards/ML51TD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51TD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml51td1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51td1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51TD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51UB9AE.json b/boards/ML51UB9AE.json new file mode 100644 index 0000000..390a24c --- /dev/null +++ b/boards/ML51UB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51UB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51ub9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51ub9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51UB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51UC0AE.json b/boards/ML51UC0AE.json new file mode 100644 index 0000000..127f01b --- /dev/null +++ b/boards/ML51UC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51UC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ml51uc0ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51uc0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51UC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML51XB9AE.json b/boards/ML51XB9AE.json new file mode 100644 index 0000000..2b20249 --- /dev/null +++ b/boards/ML51XB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML51XB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ml51xb9ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml51xb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML51XB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML54LD1AE.json b/boards/ML54LD1AE.json new file mode 100644 index 0000000..1ab054d --- /dev/null +++ b/boards/ML54LD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML54LD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml54ld1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml54ld1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML54LD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML54MD1AE.json b/boards/ML54MD1AE.json new file mode 100644 index 0000000..e78d1b3 --- /dev/null +++ b/boards/ML54MD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML54MD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml54md1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml54md1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML54MD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML54SD1AE.json b/boards/ML54SD1AE.json new file mode 100644 index 0000000..a95ed97 --- /dev/null +++ b/boards/ML54SD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML54SD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml54sd1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml54sd1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML54SD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML56LD1AE.json b/boards/ML56LD1AE.json new file mode 100644 index 0000000..13b40f5 --- /dev/null +++ b/boards/ML56LD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML56LD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml56ld1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml56ld1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML56LD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML56MD1AE.json b/boards/ML56MD1AE.json new file mode 100644 index 0000000..0f03706 --- /dev/null +++ b/boards/ML56MD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML56MD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml56md1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml56md1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML56MD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/ML56SD1AE.json b/boards/ML56SD1AE.json new file mode 100644 index 0000000..8458afc --- /dev/null +++ b/boards/ML56SD1AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DML51X -DML56SD1AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_ML51X", + "f_cpu": "24000000L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "ml56sd1ae", + "cpu": "mcs51", + "variant": "ml51x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ml56sd1ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic ML56SD1AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-power-ml51-series/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51BA9AE.json b/boards/MS51BA9AE.json new file mode 100644 index 0000000..61e8ae8 --- /dev/null +++ b/boards/MS51BA9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XA -DMS51BA9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XA", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "ms51ba9ae", + "cpu": "mcs51", + "variant": "ms51xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51ba9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51BA9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51ba9ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51DA9AE.json b/boards/MS51DA9AE.json new file mode 100644 index 0000000..0fd75ca --- /dev/null +++ b/boards/MS51DA9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XA -DMS51DA9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XA", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "ms51da9ae", + "cpu": "mcs51", + "variant": "ms51xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51da9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51DA9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51da9ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51EC0AE.json b/boards/MS51EC0AE.json new file mode 100644 index 0000000..0faec03 --- /dev/null +++ b/boards/MS51EC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XC -DMS51EC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XC", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ms51ec0ae", + "cpu": "mcs51", + "variant": "ms51xc" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51ec0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51EC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51ec0ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51FB9AE.json b/boards/MS51FB9AE.json new file mode 100644 index 0000000..ec007f4 --- /dev/null +++ b/boards/MS51FB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XB -DMS51FB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XB", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ms51fb9ae", + "cpu": "mcs51", + "variant": "ms51xb" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51fb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51FB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51fb9ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51FC0AE.json b/boards/MS51FC0AE.json new file mode 100644 index 0000000..6a34ec5 --- /dev/null +++ b/boards/MS51FC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XC -DMS51FC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XC", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ms51fc0ae", + "cpu": "mcs51", + "variant": "ms51xc" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51fc0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51FC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51fc0ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51IA9AE.json b/boards/MS51IA9AE.json new file mode 100644 index 0000000..6cf30ca --- /dev/null +++ b/boards/MS51IA9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XA -DMS51IA9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XA", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "ms51ia9ae", + "cpu": "mcs51", + "variant": "ms51xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51ia9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51IA9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51PC0AE.json b/boards/MS51PC0AE.json new file mode 100644 index 0000000..334ba54 --- /dev/null +++ b/boards/MS51PC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XC -DMS51PC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XC", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ms51pc0ae", + "cpu": "mcs51", + "variant": "ms51xc" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51pc0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51PC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51pc0ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51TC0AE.json b/boards/MS51TC0AE.json new file mode 100644 index 0000000..34670c5 --- /dev/null +++ b/boards/MS51TC0AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XC -DMS51TC0AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XC", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ms51tc0ae", + "cpu": "mcs51", + "variant": "ms51xc" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51tc0ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51TC0AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51tc0ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51XB9AE.json b/boards/MS51XB9AE.json new file mode 100644 index 0000000..32542fc --- /dev/null +++ b/boards/MS51XB9AE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XB -DMS51XB9AE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XB", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ms51xb9ae", + "cpu": "mcs51", + "variant": "ms51xb" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51xb9ae", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51XB9AE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51xb9ae/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51XB9BE.json b/boards/MS51XB9BE.json new file mode 100644 index 0000000..98529c8 --- /dev/null +++ b/boards/MS51XB9BE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XB -DMS51XB9BE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XB", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "ms51xb9be", + "cpu": "mcs51", + "variant": "ms51xb" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51xb9be", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51XB9BE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/", + "vendor": "Nuvoton" +} diff --git a/boards/MS51XC0BE.json b/boards/MS51XC0BE.json new file mode 100644 index 0000000..4c7e07b --- /dev/null +++ b/boards/MS51XC0BE.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DMS51XC -DMS51XC0BE -DNAKED_ARCH_MCS51 -DNAKED_MCS51_MS51XC", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "ms51xc0be", + "cpu": "mcs51", + "variant": "ms51xc" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "ms51xc0be", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic MS51XC0BE", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/industrial-8051-series/ms51xc0be/", + "vendor": "Nuvoton" +} diff --git a/boards/N76E003.json b/boards/N76E003.json new file mode 100644 index 0000000..6bf0cae --- /dev/null +++ b/boards/N76E003.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN76E003 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N76E003", + "f_cpu": "16000000L", + "size_iram": 256, + "size_xram": 768, + "size_code": 18432, + "size_heap": 128, + "mcu": "n76e003", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 18432, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n76e003", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N76E003", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n76e003/", + "vendor": "Nuvoton" +} diff --git a/boards/N76E616.json b/boards/N76E616.json new file mode 100644 index 0000000..880924e --- /dev/null +++ b/boards/N76E616.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN76E616 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N76E616", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 18432, + "size_heap": 128, + "mcu": "n76e616", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 18432, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n76e616", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N76E616", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n76e616/", + "vendor": "Nuvoton" +} diff --git a/boards/N76E885.json b/boards/N76E885.json new file mode 100644 index 0000000..c648123 --- /dev/null +++ b/boards/N76E885.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN76E885 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N76E885", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 18432, + "size_heap": 128, + "mcu": "n76e885", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 18432, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n76e885", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N76E885", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n76e885/", + "vendor": "Nuvoton" +} diff --git a/boards/N78E055.json b/boards/N78E055.json new file mode 100644 index 0000000..1ac3ca4 --- /dev/null +++ b/boards/N78E055.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN78E05X -DN78E055 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N78E05X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "n78e055", + "cpu": "mcs51", + "variant": "n78e05x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n78e055", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N78E055", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/n78e055a/", + "vendor": "Nuvoton" +} diff --git a/boards/N78E059.json b/boards/N78E059.json new file mode 100644 index 0000000..e2859e1 --- /dev/null +++ b/boards/N78E059.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN78E05X -DN78E059 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N78E05X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 32768, + "size_heap": 128, + "mcu": "n78e059", + "cpu": "mcs51", + "variant": "n78e05x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n78e059", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N78E059", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/n78e059a/", + "vendor": "Nuvoton" +} diff --git a/boards/N78E366.json b/boards/N78E366.json new file mode 100644 index 0000000..3336d1c --- /dev/null +++ b/boards/N78E366.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN78E366 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N78E366", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 65536, + "size_heap": 128, + "mcu": "n78e366", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n78e366", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N78E366", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/n78e366a/", + "vendor": "Nuvoton" +} diff --git a/boards/N78E517.json b/boards/N78E517.json new file mode 100644 index 0000000..2319779 --- /dev/null +++ b/boards/N78E517.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN78E517 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N78E517", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 65536, + "size_heap": 128, + "mcu": "n78e517", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n78e517", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N78E517", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/n78e517a/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E352.json b/boards/N79E352.json new file mode 100644 index 0000000..8fcee45 --- /dev/null +++ b/boards/N79E352.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E352 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E352", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 0, + "size_code": 8192, + "size_heap": 64, + "mcu": "n79e352", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e352", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E352", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/n79e352r/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E715.json b/boards/N79E715.json new file mode 100644 index 0000000..5466ce6 --- /dev/null +++ b/boards/N79E715.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E715 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E715", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 16384, + "size_heap": 128, + "mcu": "n79e715", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e715", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E715", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e715/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E813.json b/boards/N79E813.json new file mode 100644 index 0000000..37597a0 --- /dev/null +++ b/boards/N79E813.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E81X -DN79E813 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E81X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 4096, + "size_heap": 128, + "mcu": "n79e813", + "cpu": "mcs51", + "variant": "n79e81x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 4096, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e813", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E813", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E8132.json b/boards/N79E8132.json new file mode 100644 index 0000000..16f5cbd --- /dev/null +++ b/boards/N79E8132.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E81X -DN79E8132 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E81X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 4096, + "size_heap": 128, + "mcu": "n79e8132", + "cpu": "mcs51", + "variant": "n79e81x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 4096, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e8132", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E8132", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e8132/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E814.json b/boards/N79E814.json new file mode 100644 index 0000000..ec64f3a --- /dev/null +++ b/boards/N79E814.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E81X -DN79E814 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E81X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 8192, + "size_heap": 128, + "mcu": "n79e814", + "cpu": "mcs51", + "variant": "n79e81x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e814", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E814", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e814/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E815.json b/boards/N79E815.json new file mode 100644 index 0000000..e5077e8 --- /dev/null +++ b/boards/N79E815.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E81X -DN79E815 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E81X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 16384, + "size_heap": 128, + "mcu": "n79e815", + "cpu": "mcs51", + "variant": "n79e81x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e815", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E815", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e815/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E822.json b/boards/N79E822.json new file mode 100644 index 0000000..68902fd --- /dev/null +++ b/boards/N79E822.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E82X -DN79E822 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E82X", + "f_cpu": "6000000L", + "size_iram": 256, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "n79e822", + "cpu": "mcs51", + "variant": "n79e82x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 2048, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e822", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E822", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e822/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E823.json b/boards/N79E823.json new file mode 100644 index 0000000..2349d9c --- /dev/null +++ b/boards/N79E823.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E82X -DN79E823 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E82X", + "f_cpu": "6000000L", + "size_iram": 256, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "n79e823", + "cpu": "mcs51", + "variant": "n79e82x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 4096, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e823", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E823", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e823/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E824.json b/boards/N79E824.json new file mode 100644 index 0000000..f893088 --- /dev/null +++ b/boards/N79E824.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E82X -DN79E824 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E82X", + "f_cpu": "6000000L", + "size_iram": 256, + "size_xram": 0, + "size_code": 8192, + "size_heap": 64, + "mcu": "n79e824", + "cpu": "mcs51", + "variant": "n79e82x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e824", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E824", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e824/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E825.json b/boards/N79E825.json new file mode 100644 index 0000000..64531bd --- /dev/null +++ b/boards/N79E825.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E82X -DN79E825 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E82X", + "f_cpu": "6000000L", + "size_iram": 256, + "size_xram": 0, + "size_code": 16384, + "size_heap": 64, + "mcu": "n79e825", + "cpu": "mcs51", + "variant": "n79e82x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e825", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E825", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e825/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E843.json b/boards/N79E843.json new file mode 100644 index 0000000..5407678 --- /dev/null +++ b/boards/N79E843.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E84X -DN79E843 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E84X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 4096, + "size_heap": 128, + "mcu": "n79e843", + "cpu": "mcs51", + "variant": "n79e84x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 4096, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e843", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E843", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/", + "vendor": "Nuvoton" +} diff --git a/boards/N79E8432.json b/boards/N79E8432.json index d8bdafa..a1ced0f 100644 --- a/boards/N79E8432.json +++ b/boards/N79E8432.json @@ -14,9 +14,14 @@ "frameworks": [], "upload": { "maximum_ram_size": 512, - "maximum_size": 4096 + "maximum_size": 4096, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e8432", + "protocols": [ + "nuvoprog" + ] }, "name": "Generic N79E8432", - "url": "http://www.nuvoton.com/hq/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e8432/", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e8432/", "vendor": "Nuvoton" } diff --git a/boards/N79E844.json b/boards/N79E844.json index f8ceeff..d00c0c7 100644 --- a/boards/N79E844.json +++ b/boards/N79E844.json @@ -6,6 +6,7 @@ "size_iram": 256, "size_xram": 256, "size_code": 8192, + "size_heap": 128, "mcu": "n79e844", "cpu": "mcs51", "variant": "n79e84x" @@ -13,9 +14,14 @@ "frameworks": [], "upload": { "maximum_ram_size": 512, - "maximum_size": 8192 + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e844", + "protocols": [ + "nuvoprog" + ] }, "name": "Generic N79E844", - "url": "http://www.nuvoton.com/hq/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e844/", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e844/", "vendor": "Nuvoton" } diff --git a/boards/N79E845.json b/boards/N79E845.json index 3394a36..99bd71c 100644 --- a/boards/N79E845.json +++ b/boards/N79E845.json @@ -6,6 +6,7 @@ "size_iram": 256, "size_xram": 256, "size_code": 16384, + "size_heap": 128, "mcu": "n79e845", "cpu": "mcs51", "variant": "n79e84x" @@ -13,9 +14,14 @@ "frameworks": [], "upload": { "maximum_ram_size": 512, - "maximum_size": 16384 + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e845", + "protocols": [ + "nuvoprog" + ] }, "name": "Generic N79E845", - "url": "http://www.nuvoton.com/hq/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e845/", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e845/", "vendor": "Nuvoton" } diff --git a/boards/N79E854.json b/boards/N79E854.json index deea215..e6f6e83 100644 --- a/boards/N79E854.json +++ b/boards/N79E854.json @@ -6,6 +6,7 @@ "size_iram": 256, "size_xram": 256, "size_code": 8192, + "size_heap": 128, "mcu": "n79e854", "cpu": "mcs51", "variant": "n79e85x" @@ -13,9 +14,14 @@ "frameworks": [], "upload": { "maximum_ram_size": 512, - "maximum_size": 8192 + "maximum_size": 8192, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e854", + "protocols": [ + "nuvoprog" + ] }, "name": "Generic N79E854", - "url": "http://www.nuvoton.com/hq/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e854/", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e854/", "vendor": "Nuvoton" } diff --git a/boards/N79E855.json b/boards/N79E855.json index c1bd518..04c3ec1 100644 --- a/boards/N79E855.json +++ b/boards/N79E855.json @@ -14,9 +14,14 @@ "frameworks": [], "upload": { "maximum_ram_size": 512, - "maximum_size": 16384 + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e855", + "protocols": [ + "nuvoprog" + ] }, "name": "Generic N79E855", - "url": "http://www.nuvoton.com/hq/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e855/", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e855/", "vendor": "Nuvoton" } diff --git a/boards/N79E875.json b/boards/N79E875.json new file mode 100644 index 0000000..a2cbd56 --- /dev/null +++ b/boards/N79E875.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DN79E875 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N79E875", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 256, + "size_code": 16384, + "size_heap": 128, + "mcu": "n79e875", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 16384, + "protocol": "nuvoprog", + "nuvoprog_protocol": "n79e875", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic N79E875", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n79e875/", + "vendor": "Nuvoton" +} diff --git a/boards/STC12C5A08S2.json b/boards/STC12C5A08S2.json new file mode 100644 index 0000000..fdd4bd5 --- /dev/null +++ b/boards/STC12C5A08S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A08S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc12c5a08s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A08S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC12C5A16S2.json b/boards/STC12C5A16S2.json new file mode 100644 index 0000000..e1615f4 --- /dev/null +++ b/boards/STC12C5A16S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A16S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc12c5a16s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A16S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC12C5A32S2.json b/boards/STC12C5A32S2.json new file mode 100644 index 0000000..e11602f --- /dev/null +++ b/boards/STC12C5A32S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A32S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc12c5a32s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A32S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC12C5A40S2.json b/boards/STC12C5A40S2.json new file mode 100644 index 0000000..3f9fce6 --- /dev/null +++ b/boards/STC12C5A40S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A40S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 40960, + "size_heap": 128, + "mcu": "stc12c5a40s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 40960, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A40S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC12C5A48S2.json b/boards/STC12C5A48S2.json new file mode 100644 index 0000000..f596031 --- /dev/null +++ b/boards/STC12C5A48S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A48S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc12c5a48s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A48S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC12C5A52S2.json b/boards/STC12C5A52S2.json new file mode 100644 index 0000000..edded90 --- /dev/null +++ b/boards/STC12C5A52S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A52S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 53248, + "size_heap": 128, + "mcu": "stc12c5a52s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 53248, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A52S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC12C5A56S2.json b/boards/STC12C5A56S2.json new file mode 100644 index 0000000..2bef1b1 --- /dev/null +++ b/boards/STC12C5A56S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A56S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 57344, + "size_heap": 128, + "mcu": "stc12c5a56s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 57344, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A56S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC12C5A60S2.json b/boards/STC12C5A60S2.json new file mode 100644 index 0000000..a338da9 --- /dev/null +++ b/boards/STC12C5A60S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC12C5AXXS2 -DSTC12C5A60S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC12C5AXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 61140, + "size_heap": 128, + "mcu": "stc12c5a60s2", + "cpu": "mcs51", + "variant": "stc12c5axxS2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 61140, + "protocol": "stcgal", + "stcgal_protocol": "stc12", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC12C5A60S2", + "url": "http://www.stcmicro.com/stc/stc12c5a32s2.html", + "vendor": "STC" +} diff --git a/boards/STC15F100.json b/boards/STC15F100.json new file mode 100644 index 0000000..7a7bf97 --- /dev/null +++ b/boards/STC15F100.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F100 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 512, + "size_heap": 64, + "mcu": "stc15f100", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 512, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F100", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F100W.json b/boards/STC15F100W.json new file mode 100644 index 0000000..e07ff45 --- /dev/null +++ b/boards/STC15F100W.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10XW -DSTC15F100W -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10XW", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 512, + "size_heap": 64, + "mcu": "stc15f100w", + "cpu": "mcs51", + "variant": "stc15f10xw" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 512, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F100W", + "url": "https://www.stcmicro.com/STC/STC15F104W.html", + "vendor": "STC" +} diff --git a/boards/STC15F101.json b/boards/STC15F101.json new file mode 100644 index 0000000..28fd3f5 --- /dev/null +++ b/boards/STC15F101.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F101 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 1024, + "size_heap": 64, + "mcu": "stc15f101", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F101", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F101E.json b/boards/STC15F101E.json new file mode 100644 index 0000000..0723d22 --- /dev/null +++ b/boards/STC15F101E.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F101E -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 1024, + "size_heap": 64, + "mcu": "stc15f101e", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F101E", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F101W.json b/boards/STC15F101W.json new file mode 100644 index 0000000..452e9bf --- /dev/null +++ b/boards/STC15F101W.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10XW -DSTC15F101W -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10XW", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 1024, + "size_heap": 64, + "mcu": "stc15f101w", + "cpu": "mcs51", + "variant": "stc15f10xw" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F101W", + "url": "https://www.stcmicro.com/STC/STC15F104W.html", + "vendor": "STC" +} diff --git a/boards/STC15F102.json b/boards/STC15F102.json new file mode 100644 index 0000000..b75ace1 --- /dev/null +++ b/boards/STC15F102.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F102 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "stc15f102", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F102", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F102E.json b/boards/STC15F102E.json new file mode 100644 index 0000000..7823dc6 --- /dev/null +++ b/boards/STC15F102E.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F102E -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "stc15f102e", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F102E", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F102W.json b/boards/STC15F102W.json new file mode 100644 index 0000000..b1f4562 --- /dev/null +++ b/boards/STC15F102W.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10XW -DSTC15F102W -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10XW", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "stc15f102w", + "cpu": "mcs51", + "variant": "stc15f10xw" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F102W", + "url": "https://www.stcmicro.com/STC/STC15F104W.html", + "vendor": "STC" +} diff --git a/boards/STC15F103.json b/boards/STC15F103.json new file mode 100644 index 0000000..bd6bc30 --- /dev/null +++ b/boards/STC15F103.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F103 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 3072, + "size_heap": 64, + "mcu": "stc15f103", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 3072, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F103", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F103E.json b/boards/STC15F103E.json new file mode 100644 index 0000000..40c1e2b --- /dev/null +++ b/boards/STC15F103E.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F103E -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 3072, + "size_heap": 64, + "mcu": "stc15f103e", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 3072, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F103E", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F103W.json b/boards/STC15F103W.json new file mode 100644 index 0000000..a94585f --- /dev/null +++ b/boards/STC15F103W.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10XW -DSTC15F103W -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10XW", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 3072, + "size_heap": 64, + "mcu": "stc15f103w", + "cpu": "mcs51", + "variant": "stc15f10xw" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 3072, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F103W", + "url": "https://www.stcmicro.com/STC/STC15F104W.html", + "vendor": "STC" +} diff --git a/boards/STC15F104.json b/boards/STC15F104.json new file mode 100644 index 0000000..a756511 --- /dev/null +++ b/boards/STC15F104.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F104 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "stc15f104", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F104", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F104E.json b/boards/STC15F104E.json new file mode 100644 index 0000000..6898086 --- /dev/null +++ b/boards/STC15F104E.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F104E -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "stc15f104e", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F104E", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F104W.json b/boards/STC15F104W.json new file mode 100644 index 0000000..ee71d7e --- /dev/null +++ b/boards/STC15F104W.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10XW -DSTC15F104W -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10XW", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "stc15f104w", + "cpu": "mcs51", + "variant": "stc15f10xw" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F104W", + "url": "https://www.stcmicro.com/STC/STC15F104W.html", + "vendor": "STC" +} diff --git a/boards/STC15F105.json b/boards/STC15F105.json new file mode 100644 index 0000000..eda1bba --- /dev/null +++ b/boards/STC15F105.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F105 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 5120, + "size_heap": 64, + "mcu": "stc15f105", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 5120, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F105", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F105E.json b/boards/STC15F105E.json new file mode 100644 index 0000000..01ce546 --- /dev/null +++ b/boards/STC15F105E.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10X -DSTC15F105E -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 5120, + "size_heap": 64, + "mcu": "stc15f105e", + "cpu": "mcs51", + "variant": "stc15f10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 5120, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F105E", + "url": "http://www.stcmicro.com/STC/STC15F100.html", + "vendor": "STC" +} diff --git a/boards/STC15F105W.json b/boards/STC15F105W.json new file mode 100644 index 0000000..7931952 --- /dev/null +++ b/boards/STC15F105W.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F10XW -DSTC15F105W -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F10XW", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 5120, + "size_heap": 64, + "mcu": "stc15f105w", + "cpu": "mcs51", + "variant": "stc15f10xw" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 5120, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F105W", + "url": "https://www.stcmicro.com/STC/STC15F104W.html", + "vendor": "STC" +} diff --git a/boards/STC15F201A.json b/boards/STC15F201A.json new file mode 100644 index 0000000..0814aba --- /dev/null +++ b/boards/STC15F201A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F201A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 1024, + "size_heap": 64, + "mcu": "stc15f201a", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F201A", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F201EA.json b/boards/STC15F201EA.json new file mode 100644 index 0000000..3b6061f --- /dev/null +++ b/boards/STC15F201EA.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F201EA -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 1024, + "size_heap": 64, + "mcu": "stc15f201ea", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F201EA", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F202A.json b/boards/STC15F202A.json new file mode 100644 index 0000000..f7adf05 --- /dev/null +++ b/boards/STC15F202A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F202A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "stc15f202a", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F202A", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F202EA.json b/boards/STC15F202EA.json new file mode 100644 index 0000000..1f03979 --- /dev/null +++ b/boards/STC15F202EA.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F202EA -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "stc15f202ea", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F202EA", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F203A.json b/boards/STC15F203A.json new file mode 100644 index 0000000..0af9aa3 --- /dev/null +++ b/boards/STC15F203A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F203A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 3072, + "size_heap": 64, + "mcu": "stc15f203a", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 3072, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F203A", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F203EA.json b/boards/STC15F203EA.json new file mode 100644 index 0000000..ba58b04 --- /dev/null +++ b/boards/STC15F203EA.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F203EA -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 3072, + "size_heap": 64, + "mcu": "stc15f203ea", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 3072, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F203EA", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F204A.json b/boards/STC15F204A.json new file mode 100644 index 0000000..e114b67 --- /dev/null +++ b/boards/STC15F204A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F204A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "stc15f204a", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F204A", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F204EA.json b/boards/STC15F204EA.json index f19112e..94e0016 100644 --- a/boards/STC15F204EA.json +++ b/boards/STC15F204EA.json @@ -1,12 +1,15 @@ { "build": { - "f_cpu": "11059200", + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F204EA -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", "size_iram": 256, "size_xram": 0, "size_code": 4096, "size_heap": 64, "mcu": "stc15f204ea", - "cpu": "mcs51" + "cpu": "mcs51", + "variant": "stc15f20xa" }, "frameworks": [], "upload": { diff --git a/boards/STC15F205A.json b/boards/STC15F205A.json new file mode 100644 index 0000000..8765da5 --- /dev/null +++ b/boards/STC15F205A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F205A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 5120, + "size_heap": 64, + "mcu": "stc15f205a", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 5120, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F205A", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F205EA.json b/boards/STC15F205EA.json new file mode 100644 index 0000000..eaf53cb --- /dev/null +++ b/boards/STC15F205EA.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F20XA -DSTC15F205EA -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F20XA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 5120, + "size_heap": 64, + "mcu": "stc15f205ea", + "cpu": "mcs51", + "variant": "stc15f20xa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 5120, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F205EA", + "url": "https://www.stcmicro.com/STC/STC15F204EA.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K08S2.json b/boards/STC15F2K08S2.json new file mode 100644 index 0000000..553a3cf --- /dev/null +++ b/boards/STC15F2K08S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K08S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc15f2k08s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K08S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K16S2.json b/boards/STC15F2K16S2.json new file mode 100644 index 0000000..b3823cf --- /dev/null +++ b/boards/STC15F2K16S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K16S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc15f2k16s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K16S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K24AS.json b/boards/STC15F2K24AS.json new file mode 100644 index 0000000..2798649 --- /dev/null +++ b/boards/STC15F2K24AS.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXAS -DSTC15F2K24AS -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXAS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 24576, + "size_heap": 128, + "mcu": "stc15f2k24as", + "cpu": "mcs51", + "variant": "stc15f2kxxas" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 24576, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K24AS", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K24S2.json b/boards/STC15F2K24S2.json new file mode 100644 index 0000000..0e39b1e --- /dev/null +++ b/boards/STC15F2K24S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K24S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 24576, + "size_heap": 128, + "mcu": "stc15f2k24s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 24576, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K24S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K32S2.json b/boards/STC15F2K32S2.json new file mode 100644 index 0000000..b56c84b --- /dev/null +++ b/boards/STC15F2K32S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K32S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc15f2k32s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K32S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K40S2.json b/boards/STC15F2K40S2.json new file mode 100644 index 0000000..77ecd96 --- /dev/null +++ b/boards/STC15F2K40S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K40S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 40960, + "size_heap": 128, + "mcu": "stc15f2k40s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 40960, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K40S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K48S2.json b/boards/STC15F2K48S2.json new file mode 100644 index 0000000..69c9cb9 --- /dev/null +++ b/boards/STC15F2K48S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K48S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc15f2k48s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K48S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K52S2.json b/boards/STC15F2K52S2.json new file mode 100644 index 0000000..edf13f2 --- /dev/null +++ b/boards/STC15F2K52S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K52S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "6000000L", + "size_iram": 256, + "size_xram": 1536, + "size_code": 53248, + "size_heap": 128, + "mcu": "stc15f2k52s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 53248, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K52S2", + "url": "https://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K56S2.json b/boards/STC15F2K56S2.json new file mode 100644 index 0000000..33ec58e --- /dev/null +++ b/boards/STC15F2K56S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K56S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1792, + "size_code": 57344, + "size_heap": 128, + "mcu": "stc15f2k56s2", + "cpu": "mcs51", + "variant": "stc15f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 57344, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F2K56S2", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", + "vendor": "STC" +} diff --git a/boards/STC15F2K60S2.json b/boards/STC15F2K60S2.json index 4fe5c60..07ea83f 100644 --- a/boards/STC15F2K60S2.json +++ b/boards/STC15F2K60S2.json @@ -1,12 +1,15 @@ { "build": { - "f_cpu": "6000000", + "core": "naked", + "extra_flags": "-DSTC15F2KXXS2 -DSTC15F2K60S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F2KXXS2", + "f_cpu": "11059200L", "size_iram": 256, - "size_xram": 1536, + "size_xram": 1792, "size_code": 61440, "size_heap": 128, "mcu": "stc15f2k60s2", - "cpu": "mcs51" + "cpu": "mcs51", + "variant": "stc15f2kxxs2" }, "frameworks": [], "upload": { @@ -19,6 +22,6 @@ ] }, "name": "Generic STC15F2K60S2", - "url": "https://www.stcmicro.com/STC/STC15F2K32S2.html", + "url": "http://www.stcmicro.com/STC/STC15F2K32S2.html", "vendor": "STC" } diff --git a/boards/STC15F408AD.json b/boards/STC15F408AD.json new file mode 100644 index 0000000..ab4988b --- /dev/null +++ b/boards/STC15F408AD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15F4XXAD -DSTC15F408AD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15F4XXAD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc15f408ad", + "cpu": "mcs51", + "variant": "stc15f4xxad" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15F408AD", + "url": "http://www.stcmicro.com/STC/STC15F408AD.html", + "vendor": "STC" +} diff --git a/boards/STC15W100.json b/boards/STC15W100.json new file mode 100644 index 0000000..ddc60bf --- /dev/null +++ b/boards/STC15W100.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W10X -DSTC15W100 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 512, + "size_heap": 64, + "mcu": "stc15w100", + "cpu": "mcs51", + "variant": "stc15w10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 512, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W100", + "url": "https://www.stcmicro.com/STC/STC15W104.html", + "vendor": "STC" +} diff --git a/boards/STC15W101.json b/boards/STC15W101.json new file mode 100644 index 0000000..783ed3e --- /dev/null +++ b/boards/STC15W101.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W10X -DSTC15W101 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 1024, + "size_heap": 64, + "mcu": "stc15w101", + "cpu": "mcs51", + "variant": "stc15w10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W101", + "url": "https://www.stcmicro.com/STC/STC15W104.html", + "vendor": "STC" +} diff --git a/boards/STC15W102.json b/boards/STC15W102.json new file mode 100644 index 0000000..b9d8273 --- /dev/null +++ b/boards/STC15W102.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W10X -DSTC15W102 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "stc15w102", + "cpu": "mcs51", + "variant": "stc15w10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W102", + "url": "https://www.stcmicro.com/STC/STC15W104.html", + "vendor": "STC" +} diff --git a/boards/STC15W103.json b/boards/STC15W103.json new file mode 100644 index 0000000..6e89865 --- /dev/null +++ b/boards/STC15W103.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W10X -DSTC15W103 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 3072, + "size_heap": 64, + "mcu": "stc15w103", + "cpu": "mcs51", + "variant": "stc15w10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 3072, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W103", + "url": "https://www.stcmicro.com/STC/STC15W104.html", + "vendor": "STC" +} diff --git a/boards/STC15W104.json b/boards/STC15W104.json new file mode 100644 index 0000000..77cffd8 --- /dev/null +++ b/boards/STC15W104.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W10X -DSTC15W104 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W10X", + "f_cpu": "11059200L", + "size_iram": 128, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "stc15w104", + "cpu": "mcs51", + "variant": "stc15w10x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W104", + "url": "https://www.stcmicro.com/STC/STC15W104.html", + "vendor": "STC" +} diff --git a/boards/STC15W1K16S.json b/boards/STC15W1K16S.json new file mode 100644 index 0000000..7add20c --- /dev/null +++ b/boards/STC15W1K16S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W1KXXS -DSTC15W1K16S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W1KXXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 768, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc15w1k16s", + "cpu": "mcs51", + "variant": "stc15w1kxxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W1K16S", + "url": "http://www.stcmicro.com/STC/STC15W1K24S.html", + "vendor": "STC" +} diff --git a/boards/STC15W1K20S.json b/boards/STC15W1K20S.json new file mode 100644 index 0000000..3df094c --- /dev/null +++ b/boards/STC15W1K20S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W1KXXS -DSTC15W1K20S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W1KXXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 768, + "size_code": 20480, + "size_heap": 128, + "mcu": "stc15w1k20s", + "cpu": "mcs51", + "variant": "stc15w1kxxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 20480, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W1K20S", + "url": "http://www.stcmicro.com/STC/STC15W1K24S.html", + "vendor": "STC" +} diff --git a/boards/STC15W1K24S.json b/boards/STC15W1K24S.json new file mode 100644 index 0000000..c0b886e --- /dev/null +++ b/boards/STC15W1K24S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W1KXXS -DSTC15W1K24S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W1KXXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 768, + "size_code": 24576, + "size_heap": 128, + "mcu": "stc15w1k24s", + "cpu": "mcs51", + "variant": "stc15w1kxxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 24576, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W1K24S", + "url": "http://www.stcmicro.com/STC/STC15W1K24S.html", + "vendor": "STC" +} diff --git a/boards/STC15W201S.json b/boards/STC15W201S.json new file mode 100644 index 0000000..bb30640 --- /dev/null +++ b/boards/STC15W201S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W20XS -DSTC15W201S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W20XS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 1024, + "size_heap": 64, + "mcu": "stc15w201s", + "cpu": "mcs51", + "variant": "stc15w20xs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W201S", + "url": "https://www.stcmicro.com/STC/STC15W204S.html", + "vendor": "STC" +} diff --git a/boards/STC15W202S.json b/boards/STC15W202S.json new file mode 100644 index 0000000..9027ea6 --- /dev/null +++ b/boards/STC15W202S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W20XS -DSTC15W202S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W20XS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "stc15w202s", + "cpu": "mcs51", + "variant": "stc15w20xs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W202S", + "url": "https://www.stcmicro.com/STC/STC15W204S.html", + "vendor": "STC" +} diff --git a/boards/STC15W203S.json b/boards/STC15W203S.json new file mode 100644 index 0000000..8e61df3 --- /dev/null +++ b/boards/STC15W203S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W20XS -DSTC15W203S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W20XS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 3072, + "size_heap": 64, + "mcu": "stc15w203s", + "cpu": "mcs51", + "variant": "stc15w20xs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 3072, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W203S", + "url": "https://www.stcmicro.com/STC/STC15W204S.html", + "vendor": "STC" +} diff --git a/boards/STC15W204S.json b/boards/STC15W204S.json index 1ef54da..d951141 100644 --- a/boards/STC15W204S.json +++ b/boards/STC15W204S.json @@ -1,12 +1,15 @@ { "build": { - "f_cpu": "11059200", + "core": "naked", + "extra_flags": "-DSTC15W20XS -DSTC15W204S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W20XS", + "f_cpu": "11059200L", "size_iram": 256, "size_xram": 0, "size_code": 4096, "size_heap": 64, "mcu": "stc15w204s", - "cpu": "mcs51" + "cpu": "mcs51", + "variant": "stc15w20xs" }, "frameworks": [], "upload": { diff --git a/boards/STC15W401AS.json b/boards/STC15W401AS.json new file mode 100644 index 0000000..82e12e4 --- /dev/null +++ b/boards/STC15W401AS.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W40XAS -DSTC15W401AS -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W40XAS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 1024, + "size_heap": 128, + "mcu": "stc15w401as", + "cpu": "mcs51", + "variant": "stc15w40xas" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 1024, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W401AS", + "url": "https://www.stcmicro.com/STC/STC15W408AS.html", + "vendor": "STC" +} diff --git a/boards/STC15W402AS.json b/boards/STC15W402AS.json new file mode 100644 index 0000000..3b051dc --- /dev/null +++ b/boards/STC15W402AS.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W40XAS -DSTC15W402AS -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W40XAS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 2048, + "size_heap": 128, + "mcu": "stc15w402as", + "cpu": "mcs51", + "variant": "stc15w40xas" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 2048, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W402AS", + "url": "https://www.stcmicro.com/STC/STC15W408AS.html", + "vendor": "STC" +} diff --git a/boards/STC15W404AS.json b/boards/STC15W404AS.json index 0d3542c..ba738af 100644 --- a/boards/STC15W404AS.json +++ b/boards/STC15W404AS.json @@ -1,12 +1,15 @@ { "build": { - "f_cpu": "11059200", + "core": "naked", + "extra_flags": "-DSTC15W40XAS -DSTC15W404AS -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W40XAS", + "f_cpu": "11059200L", "size_iram": 256, "size_xram": 256, "size_code": 4096, "size_heap": 128, "mcu": "stc15w404as", - "cpu": "mcs51" + "cpu": "mcs51", + "variant": "stc15w40xas" }, "frameworks": [], "upload": { @@ -19,6 +22,6 @@ ] }, "name": "Generic STC15W404AS", - "url": "https://www.stcmicro.com/STC/STC15W404AS.html", + "url": "https://www.stcmicro.com/STC/STC15W408AS.html", "vendor": "STC" } diff --git a/boards/STC15W404S.json b/boards/STC15W404S.json new file mode 100644 index 0000000..5261733 --- /dev/null +++ b/boards/STC15W404S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4XXS -DSTC15W404S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4XXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 4096, + "size_heap": 128, + "mcu": "stc15w404s", + "cpu": "mcs51", + "variant": "stc15w4xxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W404S", + "url": "http://www.stcmicro.com/STC/STC15W404S.html", + "vendor": "STC" +} diff --git a/boards/STC15W408AS.json b/boards/STC15W408AS.json index e1ebd43..25af0ca 100644 --- a/boards/STC15W408AS.json +++ b/boards/STC15W408AS.json @@ -1,12 +1,15 @@ { "build": { - "f_cpu": "11059200", + "core": "naked", + "extra_flags": "-DSTC15W40XAS -DSTC15W408AS -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W40XAS", + "f_cpu": "11059200L", "size_iram": 256, "size_xram": 256, "size_code": 8192, "size_heap": 128, "mcu": "stc15w408as", - "cpu": "mcs51" + "cpu": "mcs51", + "variant": "stc15w40xas" }, "frameworks": [], "upload": { diff --git a/boards/STC15W408S.json b/boards/STC15W408S.json new file mode 100644 index 0000000..bcd8088 --- /dev/null +++ b/boards/STC15W408S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4XXS -DSTC15W408S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4XXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc15w408s", + "cpu": "mcs51", + "variant": "stc15w4xxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W408S", + "url": "http://www.stcmicro.com/STC/STC15W408S.html", + "vendor": "STC" +} diff --git a/boards/STC15W410S.json b/boards/STC15W410S.json new file mode 100644 index 0000000..aa75a64 --- /dev/null +++ b/boards/STC15W410S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4XXS -DSTC15W410S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4XXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 10240, + "size_heap": 128, + "mcu": "stc15w410s", + "cpu": "mcs51", + "variant": "stc15w4xxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 10240, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W410S", + "url": "http://www.stcmicro.com/STC/STC15W404S.html", + "vendor": "STC" +} diff --git a/boards/STC15W4K16S4.json b/boards/STC15W4K16S4.json new file mode 100644 index 0000000..f23e020 --- /dev/null +++ b/boards/STC15W4K16S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DSTC15W4K16S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc15w4k16s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W4K16S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/STC15W4K32S4.json b/boards/STC15W4K32S4.json new file mode 100644 index 0000000..776936d --- /dev/null +++ b/boards/STC15W4K32S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DSTC15W4K32S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc15w4k32s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W4K32S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/STC15W4K40S4.json b/boards/STC15W4K40S4.json new file mode 100644 index 0000000..ca1542c --- /dev/null +++ b/boards/STC15W4K40S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DSTC15W4K40S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 40960, + "size_heap": 128, + "mcu": "stc15w4k40s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 40960, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W4K40S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/STC15W4K48S4.json b/boards/STC15W4K48S4.json new file mode 100644 index 0000000..049dd00 --- /dev/null +++ b/boards/STC15W4K48S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DSTC15W4K48S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc15w4k48s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W4K48S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/STC15W4K56S4.json b/boards/STC15W4K56S4.json new file mode 100644 index 0000000..38d4942 --- /dev/null +++ b/boards/STC15W4K56S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC15W4KXXS4 -DSTC15W4K56S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC15W4KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3840, + "size_code": 57344, + "size_heap": 128, + "mcu": "stc15w4k56s4", + "cpu": "mcs51", + "variant": "stc15w4kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4096, + "maximum_size": 57344, + "protocol": "stcgal", + "stcgal_protocol": "stc15", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC15W4K56S4", + "url": "http://www.stcmicro.com/STC/STC15W4K32S4.html", + "vendor": "STC" +} diff --git a/boards/STC89C516RD+.json b/boards/STC89C516RD+.json new file mode 100644 index 0000000..fc67977 --- /dev/null +++ b/boards/STC89C516RD+.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC89C5XRX -DSTC89C516RD+ -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC89C5XRX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc89c516rd+", + "cpu": "mcs51", + "variant": "stc89c5xrx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc89", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC89C516RD+", + "url": "https://www.stcmicro.com/STC/STC89C52RC.html", + "vendor": "STC" +} diff --git a/boards/STC89C51RC.json b/boards/STC89C51RC.json new file mode 100644 index 0000000..f1ec677 --- /dev/null +++ b/boards/STC89C51RC.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC89C5XRX -DSTC89C51RC -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC89C5XRX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 4096, + "size_heap": 128, + "mcu": "stc89c51rc", + "cpu": "mcs51", + "variant": "stc89c5xrx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc89", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC89C51RC", + "url": "https://www.stcmicro.com/STC/STC89C52RC.html", + "vendor": "STC" +} diff --git a/boards/STC89C52RC.json b/boards/STC89C52RC.json index ae4629d..b8019e8 100644 --- a/boards/STC89C52RC.json +++ b/boards/STC89C52RC.json @@ -1,12 +1,15 @@ { "build": { - "f_cpu": "11059200", + "core": "naked", + "extra_flags": "-DSTC89C5XRX -DSTC89C52RC -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC89C5XRX", + "f_cpu": "11059200L", "size_iram": 256, "size_xram": 256, "size_code": 8192, "size_heap": 128, "mcu": "stc89c52rc", - "cpu": "mcs51" + "cpu": "mcs51", + "variant": "stc89c5xrx" }, "frameworks": [], "upload": { diff --git a/boards/STC89C53RC.json b/boards/STC89C53RC.json new file mode 100644 index 0000000..776a9ff --- /dev/null +++ b/boards/STC89C53RC.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC89C5XRX -DSTC89C53RC -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC89C5XRX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 256, + "size_code": 13312, + "size_heap": 128, + "mcu": "stc89c53rc", + "cpu": "mcs51", + "variant": "stc89c5xrx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 512, + "maximum_size": 13312, + "protocol": "stcgal", + "stcgal_protocol": "stc89", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC89C53RC", + "url": "https://www.stcmicro.com/STC/STC89C52RC.html", + "vendor": "STC" +} diff --git a/boards/STC89C54RD+.json b/boards/STC89C54RD+.json new file mode 100644 index 0000000..467e120 --- /dev/null +++ b/boards/STC89C54RD+.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC89C5XRX -DSTC89C54RD+ -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC89C5XRX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc89c54rd+", + "cpu": "mcs51", + "variant": "stc89c5xrx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc89", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC89C54RD+", + "url": "https://www.stcmicro.com/STC/STC89C52RC.html", + "vendor": "STC" +} diff --git a/boards/STC89C58RD+.json b/boards/STC89C58RD+.json new file mode 100644 index 0000000..762cacb --- /dev/null +++ b/boards/STC89C58RD+.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC89C5XRX -DSTC89C58RD+ -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC89C5XRX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc89c58rd+", + "cpu": "mcs51", + "variant": "stc89c5xrx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc89", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC89C58RD+", + "url": "https://www.stcmicro.com/STC/STC89C52RC.html", + "vendor": "STC" +} diff --git a/boards/STC8A4K16S2A12.json b/boards/STC8A4K16S2A12.json new file mode 100644 index 0000000..7edd16d --- /dev/null +++ b/boards/STC8A4K16S2A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A4KXXS2A12 -DSTC8A4K16S2A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A4KXXS2A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8a4k16s2a12", + "cpu": "mcs51", + "variant": "stc8a4kxxs2a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A4K16S2A12", + "url": "http://www.stcmicro.com/STC/STC8A4K64S2A12.html", + "vendor": "STC" +} diff --git a/boards/STC8A4K32S2A12.json b/boards/STC8A4K32S2A12.json new file mode 100644 index 0000000..96f3191 --- /dev/null +++ b/boards/STC8A4K32S2A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A4KXXS2A12 -DSTC8A4K32S2A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A4KXXS2A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8a4k32s2a12", + "cpu": "mcs51", + "variant": "stc8a4kxxs2a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A4K32S2A12", + "url": "http://www.stcmicro.com/STC/STC8A4K64S2A12.html", + "vendor": "STC" +} diff --git a/boards/STC8A4K60S2A12.json b/boards/STC8A4K60S2A12.json new file mode 100644 index 0000000..f55c9f9 --- /dev/null +++ b/boards/STC8A4K60S2A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A4KXXS2A12 -DSTC8A4K60S2A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A4KXXS2A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8a4k60s2a12", + "cpu": "mcs51", + "variant": "stc8a4kxxs2a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A4K60S2A12", + "url": "http://www.stcmicro.com/STC/STC8A4K64S2A12.html", + "vendor": "STC" +} diff --git a/boards/STC8A4K64S2A12.json b/boards/STC8A4K64S2A12.json new file mode 100644 index 0000000..b410e15 --- /dev/null +++ b/boards/STC8A4K64S2A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A4KXXS2A12 -DSTC8A4K64S2A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A4KXXS2A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8a4k64s2a12", + "cpu": "mcs51", + "variant": "stc8a4kxxs2a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A4K64S2A12", + "url": "http://www.stcmicro.com/STC/STC8A4K64S2A12.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K16D4.json b/boards/STC8A8K16D4.json new file mode 100644 index 0000000..8c5dbdc --- /dev/null +++ b/boards/STC8A8K16D4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXD4 -DSTC8A8K16D4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXD4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8a8k16d4", + "cpu": "mcs51", + "variant": "stc8a8kxxd4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K16D4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K16S4A12.json b/boards/STC8A8K16S4A12.json new file mode 100644 index 0000000..d343a28 --- /dev/null +++ b/boards/STC8A8K16S4A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXS4A12 -DSTC8A8K16S4A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXS4A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8a8k16s4a12", + "cpu": "mcs51", + "variant": "stc8a8kxxs4a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K16S4A12", + "url": "http://www.stcmicro.com/STC/STC8A8K64S4A12.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K32D4.json b/boards/STC8A8K32D4.json new file mode 100644 index 0000000..c7d1dc4 --- /dev/null +++ b/boards/STC8A8K32D4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXD4 -DSTC8A8K32D4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXD4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8a8k32d4", + "cpu": "mcs51", + "variant": "stc8a8kxxd4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K32D4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K32S4A12.json b/boards/STC8A8K32S4A12.json new file mode 100644 index 0000000..cb48dc9 --- /dev/null +++ b/boards/STC8A8K32S4A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXS4A12 -DSTC8A8K32S4A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXS4A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8a8k32s4a12", + "cpu": "mcs51", + "variant": "stc8a8kxxs4a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K32S4A12", + "url": "http://www.stcmicro.com/STC/STC8A8K64S4A12.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K60D4.json b/boards/STC8A8K60D4.json new file mode 100644 index 0000000..f0190ba --- /dev/null +++ b/boards/STC8A8K60D4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXD4 -DSTC8A8K60D4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXD4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8a8k60d4", + "cpu": "mcs51", + "variant": "stc8a8kxxd4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K60D4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K60S4A12.json b/boards/STC8A8K60S4A12.json new file mode 100644 index 0000000..2089603 --- /dev/null +++ b/boards/STC8A8K60S4A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXS4A12 -DSTC8A8K60S4A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXS4A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8a8k60s4a12", + "cpu": "mcs51", + "variant": "stc8a8kxxs4a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K60S4A12", + "url": "http://www.stcmicro.com/STC/STC8A8K64S4A12.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K64D4.json b/boards/STC8A8K64D4.json new file mode 100644 index 0000000..db35eea --- /dev/null +++ b/boards/STC8A8K64D4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXD4 -DSTC8A8K64D4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXD4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8a8k64d4", + "cpu": "mcs51", + "variant": "stc8a8kxxd4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K64D4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8A8K64S4A12.json b/boards/STC8A8K64S4A12.json new file mode 100644 index 0000000..3ff554f --- /dev/null +++ b/boards/STC8A8K64S4A12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8A8KXXS4A12 -DSTC8A8K64S4A12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8A8KXXS4A12", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8a8k64s4a12", + "cpu": "mcs51", + "variant": "stc8a8kxxs4a12" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8A8K64S4A12", + "url": "http://www.stcmicro.com/STC/STC8A8K64S4A12.html", + "vendor": "STC" +} diff --git a/boards/STC8C1K08.json b/boards/STC8C1K08.json new file mode 100644 index 0000000..407cbd9 --- /dev/null +++ b/boards/STC8C1K08.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C1KXX -DSTC8C1K08 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8c1k08", + "cpu": "mcs51", + "variant": "stc8c1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C1K08", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C1K12.json b/boards/STC8C1K12.json new file mode 100644 index 0000000..e6369c1 --- /dev/null +++ b/boards/STC8C1K12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C1KXX -DSTC8C1K12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 12288, + "size_heap": 128, + "mcu": "stc8c1k12", + "cpu": "mcs51", + "variant": "stc8c1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 12288, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C1K12", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K16S2.json b/boards/STC8C2K16S2.json new file mode 100644 index 0000000..ccbeaaa --- /dev/null +++ b/boards/STC8C2K16S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS2 -DSTC8C2K16S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8c2k16s2", + "cpu": "mcs51", + "variant": "stc8c2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K16S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K16S4.json b/boards/STC8C2K16S4.json new file mode 100644 index 0000000..952716b --- /dev/null +++ b/boards/STC8C2K16S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS4 -DSTC8C2K16S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8c2k16s4", + "cpu": "mcs51", + "variant": "stc8c2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K16S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K32S2.json b/boards/STC8C2K32S2.json new file mode 100644 index 0000000..fc82fab --- /dev/null +++ b/boards/STC8C2K32S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS2 -DSTC8C2K32S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8c2k32s2", + "cpu": "mcs51", + "variant": "stc8c2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K32S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K32S4.json b/boards/STC8C2K32S4.json new file mode 100644 index 0000000..cddb82f --- /dev/null +++ b/boards/STC8C2K32S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS4 -DSTC8C2K32S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8c2k32s4", + "cpu": "mcs51", + "variant": "stc8c2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K32S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K60S2.json b/boards/STC8C2K60S2.json new file mode 100644 index 0000000..8811f48 --- /dev/null +++ b/boards/STC8C2K60S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS2 -DSTC8C2K60S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8c2k60s2", + "cpu": "mcs51", + "variant": "stc8c2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K60S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K60S4.json b/boards/STC8C2K60S4.json new file mode 100644 index 0000000..d0b9dc2 --- /dev/null +++ b/boards/STC8C2K60S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS4 -DSTC8C2K60S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8c2k60s4", + "cpu": "mcs51", + "variant": "stc8c2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K60S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K64S2.json b/boards/STC8C2K64S2.json new file mode 100644 index 0000000..60d7f1b --- /dev/null +++ b/boards/STC8C2K64S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS2 -DSTC8C2K64S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8c2k64s2", + "cpu": "mcs51", + "variant": "stc8c2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K64S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8C2K64S4.json b/boards/STC8C2K64S4.json new file mode 100644 index 0000000..0972f54 --- /dev/null +++ b/boards/STC8C2K64S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8C2KXXS4 -DSTC8C2K64S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8C2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8c2k64s4", + "cpu": "mcs51", + "variant": "stc8c2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8C2K64S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8F1K08.json b/boards/STC8F1K08.json new file mode 100644 index 0000000..2da086e --- /dev/null +++ b/boards/STC8F1K08.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F1KXX -DSTC8F1K08 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8f1k08", + "cpu": "mcs51", + "variant": "stc8f1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F1K08", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8F1K08S.json b/boards/STC8F1K08S.json new file mode 100644 index 0000000..25cc843 --- /dev/null +++ b/boards/STC8F1K08S.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F1KXXS -DSTC8F1K08S -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F1KXXS", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8f1k08s", + "cpu": "mcs51", + "variant": "stc8f1kxxs" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F1K08S", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8F1K08S2.json b/boards/STC8F1K08S2.json new file mode 100644 index 0000000..8e18aba --- /dev/null +++ b/boards/STC8F1K08S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F1KXXS2 -DSTC8F1K08S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F1KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8f1k08s2", + "cpu": "mcs51", + "variant": "stc8f1kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F1K08S2", + "url": "http://www.stcmicro.com/STC/STC8F1K08S2.html", + "vendor": "STC" +} diff --git a/boards/STC8F1K08S2A10.json b/boards/STC8F1K08S2A10.json new file mode 100644 index 0000000..3036c7d --- /dev/null +++ b/boards/STC8F1K08S2A10.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F1KXXS2A10 -DSTC8F1K08S2A10 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F1KXXS2A10", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8f1k08s2A10", + "cpu": "mcs51", + "variant": "stc8f1kxxs2A10" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F1K08S2A10", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8F1K17.json b/boards/STC8F1K17.json new file mode 100644 index 0000000..b8bb9ba --- /dev/null +++ b/boards/STC8F1K17.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F1KXX -DSTC8F1K17 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 17408, + "size_heap": 128, + "mcu": "stc8f1k17", + "cpu": "mcs51", + "variant": "stc8f1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 17408, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F1K17", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8F1K17S2.json b/boards/STC8F1K17S2.json new file mode 100644 index 0000000..19188fa --- /dev/null +++ b/boards/STC8F1K17S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F1KXXS2 -DSTC8F1K17S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F1KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 17408, + "size_heap": 128, + "mcu": "stc8f1k17s2", + "cpu": "mcs51", + "variant": "stc8f1kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 17408, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F1K17S2", + "url": "http://www.stcmicro.com/STC/STC8F1K08S2.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K08S2.json b/boards/STC8F2K08S2.json new file mode 100644 index 0000000..7f12ee8 --- /dev/null +++ b/boards/STC8F2K08S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS2 -DSTC8F2K08S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8f2k08s2", + "cpu": "mcs51", + "variant": "stc8f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K08S2", + "url": "http://www.stcmicro.com/STC/STC8F1K08S2.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K16S2.json b/boards/STC8F2K16S2.json new file mode 100644 index 0000000..ec349db --- /dev/null +++ b/boards/STC8F2K16S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS2 -DSTC8F2K16S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8f2k16s2", + "cpu": "mcs51", + "variant": "stc8f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K16S2", + "url": "http://www.stcmicro.com/STC/STC8F2K64S2.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K16S4.json b/boards/STC8F2K16S4.json new file mode 100644 index 0000000..d53b49b --- /dev/null +++ b/boards/STC8F2K16S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS4 -DSTC8F2K16S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8f2k16s4", + "cpu": "mcs51", + "variant": "stc8f2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K16S4", + "url": "http://www.stcmicro.com/STC/STC8F2K64S4.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K32S2.json b/boards/STC8F2K32S2.json new file mode 100644 index 0000000..d627e40 --- /dev/null +++ b/boards/STC8F2K32S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS2 -DSTC8F2K32S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8f2k32s2", + "cpu": "mcs51", + "variant": "stc8f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K32S2", + "url": "http://www.stcmicro.com/STC/STC8F2K64S2.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K32S4.json b/boards/STC8F2K32S4.json new file mode 100644 index 0000000..8a48aa9 --- /dev/null +++ b/boards/STC8F2K32S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS4 -DSTC8F2K32S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8f2k32s4", + "cpu": "mcs51", + "variant": "stc8f2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K32S4", + "url": "http://www.stcmicro.com/STC/STC8F2K64S4.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K60S2.json b/boards/STC8F2K60S2.json new file mode 100644 index 0000000..e3b367d --- /dev/null +++ b/boards/STC8F2K60S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS2 -DSTC8F2K60S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8f2k60s2", + "cpu": "mcs51", + "variant": "stc8f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K60S2", + "url": "http://www.stcmicro.com/STC/STC8F2K64S2.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K60S4.json b/boards/STC8F2K60S4.json new file mode 100644 index 0000000..097a029 --- /dev/null +++ b/boards/STC8F2K60S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS4 -DSTC8F2K60S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8f2k60s4", + "cpu": "mcs51", + "variant": "stc8f2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K60S4", + "url": "http://www.stcmicro.com/STC/STC8F2K64S4.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K64S2.json b/boards/STC8F2K64S2.json new file mode 100644 index 0000000..23473fd --- /dev/null +++ b/boards/STC8F2K64S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS2 -DSTC8F2K64S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8f2k64s2", + "cpu": "mcs51", + "variant": "stc8f2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K64S2", + "url": "http://www.stcmicro.com/STC/STC8F2K64S2.html", + "vendor": "STC" +} diff --git a/boards/STC8F2K64S4.json b/boards/STC8F2K64S4.json new file mode 100644 index 0000000..63d8c9e --- /dev/null +++ b/boards/STC8F2K64S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8F2KXXS4 -DSTC8F2K64S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8F2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8f2k64s4", + "cpu": "mcs51", + "variant": "stc8f2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8F2K64S4", + "url": "http://www.stcmicro.com/STC/STC8F2K64S4.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K08.json b/boards/STC8G1K08.json new file mode 100644 index 0000000..01e063a --- /dev/null +++ b/boards/STC8G1K08.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXX -DSTC8G1K08 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8g1k08", + "cpu": "mcs51", + "variant": "stc8g1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K08", + "url": "http://www.stcmicro.com/stc/stc8g1k08.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K08A.json b/boards/STC8G1K08A.json new file mode 100644 index 0000000..dd78ca5 --- /dev/null +++ b/boards/STC8G1K08A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXXA -DSTC8G1K08A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXXA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8g1k08a", + "cpu": "mcs51", + "variant": "stc8g1kxxa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K08A", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K08T.json b/boards/STC8G1K08T.json new file mode 100644 index 0000000..3bdb86a --- /dev/null +++ b/boards/STC8G1K08T.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXXT -DSTC8G1K08T -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXXT", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 128, + "mcu": "stc8g1k08t", + "cpu": "mcs51", + "variant": "stc8g1kxxt" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K08T", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K12.json b/boards/STC8G1K12.json new file mode 100644 index 0000000..56b41cc --- /dev/null +++ b/boards/STC8G1K12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXX -DSTC8G1K12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 12288, + "size_heap": 128, + "mcu": "stc8g1k12", + "cpu": "mcs51", + "variant": "stc8g1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 12288, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K12", + "url": "http://www.stcmicro.com/stc/stc8g1k08.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K12A.json b/boards/STC8G1K12A.json new file mode 100644 index 0000000..b60a90c --- /dev/null +++ b/boards/STC8G1K12A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXXA -DSTC8G1K12A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXXA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 12288, + "size_heap": 128, + "mcu": "stc8g1k12a", + "cpu": "mcs51", + "variant": "stc8g1kxxa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 12288, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K12A", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K17.json b/boards/STC8G1K17.json new file mode 100644 index 0000000..904a268 --- /dev/null +++ b/boards/STC8G1K17.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXX -DSTC8G1K17 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 17408, + "size_heap": 128, + "mcu": "stc8g1k17", + "cpu": "mcs51", + "variant": "stc8g1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 17408, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K17", + "url": "http://www.stcmicro.com/stc/stc8g1k08.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K17A.json b/boards/STC8G1K17A.json new file mode 100644 index 0000000..89e1bd1 --- /dev/null +++ b/boards/STC8G1K17A.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXXA -DSTC8G1K17A -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXXA", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 17408, + "size_heap": 128, + "mcu": "stc8g1k17a", + "cpu": "mcs51", + "variant": "stc8g1kxxa" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 17408, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K17A", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G1K17T.json b/boards/STC8G1K17T.json new file mode 100644 index 0000000..00c0155 --- /dev/null +++ b/boards/STC8G1K17T.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G1KXXT -DSTC8G1K17T -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G1KXXT", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 17408, + "size_heap": 128, + "mcu": "stc8g1k17t", + "cpu": "mcs51", + "variant": "stc8g1kxxt" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 17408, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G1K17T", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K16S2.json b/boards/STC8G2K16S2.json new file mode 100644 index 0000000..a044f05 --- /dev/null +++ b/boards/STC8G2K16S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS2 -DSTC8G2K16S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8g2k16s2", + "cpu": "mcs51", + "variant": "stc8g2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K16S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K16S4.json b/boards/STC8G2K16S4.json new file mode 100644 index 0000000..139fbdc --- /dev/null +++ b/boards/STC8G2K16S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS4 -DSTC8G2K16S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 16384, + "size_heap": 128, + "mcu": "stc8g2k16s4", + "cpu": "mcs51", + "variant": "stc8g2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K16S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K32S2.json b/boards/STC8G2K32S2.json new file mode 100644 index 0000000..bb4f84b --- /dev/null +++ b/boards/STC8G2K32S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS2 -DSTC8G2K32S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8g2k32s2", + "cpu": "mcs51", + "variant": "stc8g2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K32S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K32S4.json b/boards/STC8G2K32S4.json new file mode 100644 index 0000000..a0b26a8 --- /dev/null +++ b/boards/STC8G2K32S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS4 -DSTC8G2K32S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8g2k32s4", + "cpu": "mcs51", + "variant": "stc8g2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K32S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K60S2.json b/boards/STC8G2K60S2.json new file mode 100644 index 0000000..8e6baa7 --- /dev/null +++ b/boards/STC8G2K60S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS2 -DSTC8G2K60S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8g2k60s2", + "cpu": "mcs51", + "variant": "stc8g2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K60S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K60S4.json b/boards/STC8G2K60S4.json new file mode 100644 index 0000000..1af4e4f --- /dev/null +++ b/boards/STC8G2K60S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS4 -DSTC8G2K60S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8g2k60s4", + "cpu": "mcs51", + "variant": "stc8g2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K60S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K64S2.json b/boards/STC8G2K64S2.json new file mode 100644 index 0000000..0357f49 --- /dev/null +++ b/boards/STC8G2K64S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS2 -DSTC8G2K64S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8g2k64s2", + "cpu": "mcs51", + "variant": "stc8g2kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K64S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8G2K64S4.json b/boards/STC8G2K64S4.json new file mode 100644 index 0000000..0d2fefe --- /dev/null +++ b/boards/STC8G2K64S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8G2KXXS4 -DSTC8G2K64S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8G2KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8g2k64s4", + "cpu": "mcs51", + "variant": "stc8g2kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8G2K64S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H04.json b/boards/STC8H04.json new file mode 100644 index 0000000..d0a47ae --- /dev/null +++ b/boards/STC8H04.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H0X -DSTC8H04 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H0X", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "stc8h04", + "cpu": "mcs51", + "variant": "stc8h0x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H04", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H04A10.json b/boards/STC8H04A10.json new file mode 100644 index 0000000..ef40abe --- /dev/null +++ b/boards/STC8H04A10.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H0XA10 -DSTC8H04A10 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H0XA10", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "stc8h04a10", + "cpu": "mcs51", + "variant": "stc8h0xa10" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 4096, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H04A10", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K08.json b/boards/STC8H1K08.json new file mode 100644 index 0000000..bcd7eb2 --- /dev/null +++ b/boards/STC8H1K08.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXX -DSTC8H1K08 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 64, + "mcu": "stc8h1k08", + "cpu": "mcs51", + "variant": "stc8h1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K08", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K08S2.json b/boards/STC8H1K08S2.json new file mode 100644 index 0000000..9fda0c0 --- /dev/null +++ b/boards/STC8H1K08S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXXS2 -DSTC8H1K08S2-DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 64, + "mcu": "stc8h1k08s2", + "cpu": "mcs51", + "variant": "stc8h1kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K08S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K08S2A10.json b/boards/STC8H1K08S2A10.json new file mode 100644 index 0000000..e014207 --- /dev/null +++ b/boards/STC8H1K08S2A10.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXXS2A10 -DSTC8H1K08S2A10-DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXXS2A10", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 8192, + "size_heap": 64, + "mcu": "stc8h1k08s2a10", + "cpu": "mcs51", + "variant": "stc8h1kxxs2a10" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 8192, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K08S2A10", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K12.json b/boards/STC8H1K12.json new file mode 100644 index 0000000..4af3fa3 --- /dev/null +++ b/boards/STC8H1K12.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXX -DSTC8H1K12 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 12288, + "size_heap": 64, + "mcu": "stc8h1k12", + "cpu": "mcs51", + "variant": "stc8h1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 12288, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K12", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K16.json b/boards/STC8H1K16.json new file mode 100644 index 0000000..4f34185 --- /dev/null +++ b/boards/STC8H1K16.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXX -DSTC8H1K16 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 64, + "mcu": "stc8h1k16", + "cpu": "mcs51", + "variant": "stc8h1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K16", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K16S2.json b/boards/STC8H1K16S2.json new file mode 100644 index 0000000..a17e09d --- /dev/null +++ b/boards/STC8H1K16S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXXS2 -DSTC8H1K16S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 64, + "mcu": "stc8h1k16s2", + "cpu": "mcs51", + "variant": "stc8h1kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K16S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K16S2A10.json b/boards/STC8H1K16S2A10.json new file mode 100644 index 0000000..a5c3690 --- /dev/null +++ b/boards/STC8H1K16S2A10.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXXS2A10 -DSTC8H1K16S2A10 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXXS2A10", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 16384, + "size_heap": 64, + "mcu": "stc8h1k16s2a10", + "cpu": "mcs51", + "variant": "stc8h1kxxs2a10" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 16384, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K16S2A10", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K17.json b/boards/STC8H1K17.json new file mode 100644 index 0000000..e7ab326 --- /dev/null +++ b/boards/STC8H1K17.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXX -DSTC8H1K17 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 17408, + "size_heap": 64, + "mcu": "stc8h1k17", + "cpu": "mcs51", + "variant": "stc8h1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 17408, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K17", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K24.json b/boards/STC8H1K24.json new file mode 100644 index 0000000..fe77f04 --- /dev/null +++ b/boards/STC8H1K24.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXX -DSTC8H1K24 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 24576, + "size_heap": 64, + "mcu": "stc8h1k24", + "cpu": "mcs51", + "variant": "stc8h1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 24576, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K24", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K28.json b/boards/STC8H1K28.json new file mode 100644 index 0000000..ac40f9c --- /dev/null +++ b/boards/STC8H1K28.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXX -DSTC8H1K28 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 28672, + "size_heap": 64, + "mcu": "stc8h1k28", + "cpu": "mcs51", + "variant": "stc8h1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 28672, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K28", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K32S2.json b/boards/STC8H1K32S2.json new file mode 100644 index 0000000..5335fcd --- /dev/null +++ b/boards/STC8H1K32S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXXS2 -DSTC8H1K32S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 32768, + "size_heap": 64, + "mcu": "stc8h1k32s2", + "cpu": "mcs51", + "variant": "stc8h1kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K32S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K32S2A10.json b/boards/STC8H1K32S2A10.json new file mode 100644 index 0000000..c587125 --- /dev/null +++ b/boards/STC8H1K32S2A10.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXXS2A10 -DSTC8H1K32S2A10 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXXS2A10", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 32768, + "size_heap": 64, + "mcu": "stc8h1k32s2a10", + "cpu": "mcs51", + "variant": "stc8h1kxxs2a10" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K32S2A10", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K33.json b/boards/STC8H1K33.json new file mode 100644 index 0000000..8d4cccf --- /dev/null +++ b/boards/STC8H1K33.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXX -DSTC8H1K33 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXX", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 33792, + "size_heap": 64, + "mcu": "stc8h1k33", + "cpu": "mcs51", + "variant": "stc8h1kxx" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 33792, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K33", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H1K64S2A10.json b/boards/STC8H1K64S2A10.json new file mode 100644 index 0000000..f5c13bc --- /dev/null +++ b/boards/STC8H1K64S2A10.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H1KXXS2A10 -DSTC8H1K64S2A10 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H1KXXS2A10", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 32768, + "size_heap": 64, + "mcu": "stc8h1k64s2a10", + "cpu": "mcs51", + "variant": "stc8h1kxxs2a10" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H1K64S2A10", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H2K32T.json b/boards/STC8H2K32T.json new file mode 100644 index 0000000..2ab01e0 --- /dev/null +++ b/boards/STC8H2K32T.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H2KXXT -DSTC8H2K32T -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H2KXXT", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h2k32t", + "cpu": "mcs51", + "variant": "stc8h2kxxt" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H2K32T", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H2K48T.json b/boards/STC8H2K48T.json new file mode 100644 index 0000000..8f84a4e --- /dev/null +++ b/boards/STC8H2K48T.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H2KXXT -DSTC8H2K48T -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H2KXXT", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc8h2k48t", + "cpu": "mcs51", + "variant": "stc8h2kxxt" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H2K48T", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H2K60T.json b/boards/STC8H2K60T.json new file mode 100644 index 0000000..2a66150 --- /dev/null +++ b/boards/STC8H2K60T.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H2KXXT -DSTC8H2K60T -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H2KXXT", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8h2k60t", + "cpu": "mcs51", + "variant": "stc8h2kxxt" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H2K60T", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H2K64T.json b/boards/STC8H2K64T.json new file mode 100644 index 0000000..5334f0d --- /dev/null +++ b/boards/STC8H2K64T.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H2KXXT -DSTC8H2K64T -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H2KXXT", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 2048, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8h2k64t", + "cpu": "mcs51", + "variant": "stc8h2kxxt" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 2304, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H2K64T", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K32S2.json b/boards/STC8H3K32S2.json new file mode 100644 index 0000000..5a433ef --- /dev/null +++ b/boards/STC8H3K32S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS2 -DSTC8H3K32S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h3k32s2", + "cpu": "mcs51", + "variant": "stc8h3kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K32S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K32S4.json b/boards/STC8H3K32S4.json new file mode 100644 index 0000000..5d1c3a7 --- /dev/null +++ b/boards/STC8H3K32S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS4 -DSTC8H3K32S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h3k32s4", + "cpu": "mcs51", + "variant": "stc8h3kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K32S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K48S2.json b/boards/STC8H3K48S2.json new file mode 100644 index 0000000..540b271 --- /dev/null +++ b/boards/STC8H3K48S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS2 -DSTC8H3K48S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h3k48s2", + "cpu": "mcs51", + "variant": "stc8h3kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K48S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K48S4.json b/boards/STC8H3K48S4.json new file mode 100644 index 0000000..f386989 --- /dev/null +++ b/boards/STC8H3K48S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS4 -DSTC8H3K48S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc8h3k48s4", + "cpu": "mcs51", + "variant": "stc8h3kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K48S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K60S2.json b/boards/STC8H3K60S2.json new file mode 100644 index 0000000..e394733 --- /dev/null +++ b/boards/STC8H3K60S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS2 -DSTC8H3K60S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8h3k60s2", + "cpu": "mcs51", + "variant": "stc8h3kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K60S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K60S4.json b/boards/STC8H3K60S4.json new file mode 100644 index 0000000..7efa55e --- /dev/null +++ b/boards/STC8H3K60S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS4 -DSTC8H3K60S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8h3k60s4", + "cpu": "mcs51", + "variant": "stc8h3kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K60S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K64S2.json b/boards/STC8H3K64S2.json new file mode 100644 index 0000000..4902dfd --- /dev/null +++ b/boards/STC8H3K64S2.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS2 -DSTC8H3K64S2 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS2", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8h3k64s2", + "cpu": "mcs51", + "variant": "stc8h3kxxs2" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K64S2", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H3K64S4.json b/boards/STC8H3K64S4.json new file mode 100644 index 0000000..e5d6c26 --- /dev/null +++ b/boards/STC8H3K64S4.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H3KXXS4 -DSTC8H3K64S4 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H3KXXS4", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 3072, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8h3k64s4", + "cpu": "mcs51", + "variant": "stc8h3kxxs4" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 3328, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H3K64S4", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K32LCD.json b/boards/STC8H4K32LCD.json new file mode 100644 index 0000000..1566a35 --- /dev/null +++ b/boards/STC8H4K32LCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXLCD -DSTC8H4K32LCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h4k32lcd", + "cpu": "mcs51", + "variant": "stc8h4kxxlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K32LCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K32TLCD.json b/boards/STC8H4K32TLCD.json new file mode 100644 index 0000000..91916f6 --- /dev/null +++ b/boards/STC8H4K32TLCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLCD -DSTC8H4K32TLCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h4k32tlcd", + "cpu": "mcs51", + "variant": "stc8h4kxxtlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K32TLCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K32TLR.json b/boards/STC8H4K32TLR.json new file mode 100644 index 0000000..202b01f --- /dev/null +++ b/boards/STC8H4K32TLR.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLR -DSTC8H4K32TLR -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLR", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h4k32tlr", + "cpu": "mcs51", + "variant": "stc8h4kxxtlr" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K32TLR", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K48LCD.json b/boards/STC8H4K48LCD.json new file mode 100644 index 0000000..37209c7 --- /dev/null +++ b/boards/STC8H4K48LCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXLCD -DSTC8H4K48LCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc8h4k48lcd", + "cpu": "mcs51", + "variant": "stc8h4kxxlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K48LCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K48TLCD.json b/boards/STC8H4K48TLCD.json new file mode 100644 index 0000000..0f1b700 --- /dev/null +++ b/boards/STC8H4K48TLCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLCD -DSTC8H4K48TLCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc8h4k48tlcd", + "cpu": "mcs51", + "variant": "stc8h4kxxtlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K48TLCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K48TLR.json b/boards/STC8H4K48TLR.json new file mode 100644 index 0000000..1de7001 --- /dev/null +++ b/boards/STC8H4K48TLR.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLR -DSTC8H4K48TLR -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLR", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc8h4k48tlr", + "cpu": "mcs51", + "variant": "stc8h4kxxtlr" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K48TLR", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K60LCD.json b/boards/STC8H4K60LCD.json new file mode 100644 index 0000000..4b490f9 --- /dev/null +++ b/boards/STC8H4K60LCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXLCD -DSTC8H4K60LCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8h4k60lcd", + "cpu": "mcs51", + "variant": "stc8h4kxxlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K60LCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K60TLCD.json b/boards/STC8H4K60TLCD.json new file mode 100644 index 0000000..e2b1d70 --- /dev/null +++ b/boards/STC8H4K60TLCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLCD -DSTC8H4K60TLCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8h4k60tlcd", + "cpu": "mcs51", + "variant": "stc8h4kxxtlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K60TLCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K60TLR.json b/boards/STC8H4K60TLR.json new file mode 100644 index 0000000..7f0be36 --- /dev/null +++ b/boards/STC8H4K60TLR.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLR -DSTC8H4K60TLR -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLR", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8h4k60tlr", + "cpu": "mcs51", + "variant": "stc8h4kxxtlr" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K60TLR", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K64LCD.json b/boards/STC8H4K64LCD.json new file mode 100644 index 0000000..4331958 --- /dev/null +++ b/boards/STC8H4K64LCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXLCD -DSTC8H4K64LCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8h4k64lcd", + "cpu": "mcs51", + "variant": "stc8h4kxxlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K64LCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K64TLCD.json b/boards/STC8H4K64TLCD.json new file mode 100644 index 0000000..e47c0f2 --- /dev/null +++ b/boards/STC8H4K64TLCD.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLCD -DSTC8H4K64TLCD -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLCD", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8h4k64tlcd", + "cpu": "mcs51", + "variant": "stc8h4kxxtlcd" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K64TLCD", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H4K64TLR.json b/boards/STC8H4K64TLR.json new file mode 100644 index 0000000..5ca96a0 --- /dev/null +++ b/boards/STC8H4K64TLR.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H4KXXTLR -DSTC8H4K64TLR -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H4KXXTLR", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 4096, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8h4k64tlr", + "cpu": "mcs51", + "variant": "stc8h4kxxtlr" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 4352, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H4K64TLR", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H8K32U.json b/boards/STC8H8K32U.json new file mode 100644 index 0000000..087839f --- /dev/null +++ b/boards/STC8H8K32U.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H8KXXU -DSTC8H8K32U -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H8KXXU", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 32768, + "size_heap": 128, + "mcu": "stc8h8k32u", + "cpu": "mcs51", + "variant": "stc8h8kxxu" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 32768, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H8K32U", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H8K48U.json b/boards/STC8H8K48U.json new file mode 100644 index 0000000..6d86980 --- /dev/null +++ b/boards/STC8H8K48U.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H8KXXU -DSTC8H8K48U -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H8KXXU", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 49152, + "size_heap": 128, + "mcu": "stc8h8k48u", + "cpu": "mcs51", + "variant": "stc8h8kxxu" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 49152, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H8K48U", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H8K60U.json b/boards/STC8H8K60U.json new file mode 100644 index 0000000..d496889 --- /dev/null +++ b/boards/STC8H8K60U.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H8KXXU -DSTC8H8K60U -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H8KXXU", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 61440, + "size_heap": 128, + "mcu": "stc8h8k60u", + "cpu": "mcs51", + "variant": "stc8h8kxxu" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 61440, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H8K60U", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/STC8H8K64U.json b/boards/STC8H8K64U.json new file mode 100644 index 0000000..ff0da37 --- /dev/null +++ b/boards/STC8H8K64U.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DSTC8H8KXXU -DSTC8H8K64U -DNAKED_ARCH_MCS51 -DNAKED_MCS51_STC8H8KXXU", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 8192, + "size_code": 65536, + "size_heap": 128, + "mcu": "stc8h8k64u", + "cpu": "mcs51", + "variant": "stc8h8kxxu" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 8448, + "maximum_size": 65536, + "protocol": "stcgal", + "stcgal_protocol": "stc8", + "protocols": [ + "stcgal" + ] + }, + "name": "Generic STC8H8K64U", + "url": "http://www.stcmicro.com/stc/stc51.html", + "vendor": "STC" +} diff --git a/boards/W79E2051.json b/boards/W79E2051.json new file mode 100644 index 0000000..22a319e --- /dev/null +++ b/boards/W79E2051.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DW79EX051 -DW79E2051 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_W79EX051", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 0, + "size_code": 2048, + "size_heap": 64, + "mcu": "w79e2051", + "cpu": "mcs51", + "variant": "w79ex051" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 2048, + "protocol": "nuvoprog", + "nuvoprog_protocol": "w79e2051", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic W79E2051", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/w79e2051/", + "vendor": "Nuvoton" +} diff --git a/boards/W79E4051.json b/boards/W79E4051.json new file mode 100644 index 0000000..1027144 --- /dev/null +++ b/boards/W79E4051.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DW79EX051 -DW79E4051 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_W79EX051", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "w79e4051", + "cpu": "mcs51", + "variant": "w79ex051" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 256, + "maximum_size": 4096, + "protocol": "nuvoprog", + "nuvoprog_protocol": "w79e4051", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic W79E4051", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/w79e4051/", + "vendor": "Nuvoton" +} diff --git a/boards/W79E632.json b/boards/W79E632.json new file mode 100644 index 0000000..ffb2ef2 --- /dev/null +++ b/boards/W79E632.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DW79E632 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_W79E632", + "f_cpu": "11059200L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 65536, + "size_heap": 128, + "mcu": "w79e632", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "w79e632", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic W79E632", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/w79e632a/", + "vendor": "Nuvoton" +} diff --git a/boards/W79E633.json b/boards/W79E633.json new file mode 100644 index 0000000..9130843 --- /dev/null +++ b/boards/W79E633.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DW79E633 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_W79E633", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 65536, + "size_heap": 128, + "mcu": "w79e633", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "w79e633", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic W79E633", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/w79e633a/", + "vendor": "Nuvoton" +} diff --git a/boards/W79E658.json b/boards/W79E658.json new file mode 100644 index 0000000..8692e9c --- /dev/null +++ b/boards/W79E658.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DW79E65X -DW79E658 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_W79E65X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 65536, + "size_heap": 128, + "mcu": "w79e658", + "cpu": "mcs51", + "variant": "w79e65x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 65536, + "protocol": "nuvoprog", + "nuvoprog_protocol": "w79e658", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic W79E658", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/w79e658a/", + "vendor": "Nuvoton" +} diff --git a/boards/W79E659.json b/boards/W79E659.json new file mode 100644 index 0000000..810e04c --- /dev/null +++ b/boards/W79E659.json @@ -0,0 +1,27 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DW79E65X -DW79E659 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_W79E65X", + "f_cpu": "22118400L", + "size_iram": 256, + "size_xram": 1024, + "size_code": 32768, + "size_heap": 128, + "mcu": "w79e659", + "cpu": "mcs51", + "variant": "w79e65x" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 1280, + "maximum_size": 32768, + "protocol": "nuvoprog", + "nuvoprog_protocol": "w79e659", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic W79E659", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/standard-8051-series/w79e659a/", + "vendor": "Nuvoton" +} diff --git a/boards/W79E8213.json b/boards/W79E8213.json new file mode 100644 index 0000000..2c7c4cc --- /dev/null +++ b/boards/W79E8213.json @@ -0,0 +1,26 @@ +{ + "build": { + "core": "naked", + "extra_flags": "-DW79E8213 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_W79E8213", + "f_cpu": "20000000L", + "size_iram": 128, + "size_xram": 0, + "size_code": 4096, + "size_heap": 64, + "mcu": "w79e8213", + "cpu": "mcs51" + }, + "frameworks": [], + "upload": { + "maximum_ram_size": 128, + "maximum_size": 4096, + "protocol": "nuvoprog", + "nuvoprog_protocol": "w79e8213", + "protocols": [ + "nuvoprog" + ] + }, + "name": "Generic W79E8213", + "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/w79e8213/", + "vendor": "Nuvoton" +} diff --git a/examples/anymcu-blink/include/README b/examples/anymcu-blink/include/README new file mode 100644 index 0000000..45496b1 --- /dev/null +++ b/examples/anymcu-blink/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/anymcu-blink/lib/README b/examples/anymcu-blink/lib/README new file mode 100644 index 0000000..8c9c29c --- /dev/null +++ b/examples/anymcu-blink/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/anymcu-blink/platformio.ini b/examples/anymcu-blink/platformio.ini new file mode 100644 index 0000000..75c43e1 --- /dev/null +++ b/examples/anymcu-blink/platformio.ini @@ -0,0 +1,13 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env:n76e003] +platform = intel_mcs51 +board = N76E003 diff --git a/examples/anymcu-blink/src/Generic8051.h b/examples/anymcu-blink/src/Generic8051.h new file mode 100644 index 0000000..75dd3ba --- /dev/null +++ b/examples/anymcu-blink/src/Generic8051.h @@ -0,0 +1,217 @@ +#ifndef Generic8051_H +#define Generic8051_H +#include + +// Includes extra compatibility enhancements over original 8051.h +// Suitable for use with the original basic 8051 series MCU. +// This header file was verified against the MCS-51 manual. +// After this file is included you don't have to include "reg51.h". +// Comments beginning with //- indicate 8051. +// Comments begining with //= indicate defacto standard aliases. +// X means undefined, U means unchanged, C means config dependent. + +//SFR DECLARATION NOTE POR RESET VALUE DESCRIPTION +#define _P0 0x80 + SFR(P0, _P0); //- 1111'1111 Port 0 + SBIT( P0_0, _P0, 0); //- + SBIT( P00, _P0, 0); //= + SBIT( P0_1, _P0, 1); //- + SBIT( P01, _P0, 1); //= + SBIT( P0_2, _P0, 2); //- + SBIT( P02, _P0, 2); //= + SBIT( P0_3, _P0, 3); //- + SBIT( P03, _P0, 3); //= + SBIT( P0_4, _P0, 4); //- + SBIT( P04, _P0, 4); //= + SBIT( P0_5, _P0, 5); //- + SBIT( P05, _P0, 5); //= + SBIT( P0_6, _P0, 6); //- + SBIT( P06, _P0, 6); //= + SBIT( P0_7, _P0, 7); //- + SBIT( P07, _P0, 7); //= + +#define _SP 0x81 + SFR(SP, _SP); //- 0000'0111 Stack pointer + +#define _DPL 0x82 + SFR(DPL, _DPL); //- 0000'0000 Data pointer low byte + +#define _DPH 0x83 + SFR(DPH, _DPH); //- 0000'0000 Data pointer high byte + +#define _PCON 0x87 + SFR(PCON, _PCON); //- 0XXX'0000 Power Control + #define IDL 0x01 //- + #define PD 0x02 //- + #define GF0 0x04 //- + #define GF1 0x08 //- + #define SMOD 0x80 //- + +#define _TCON 0x88 + SFR(TCON, _TCON); //- 0000'0000 Timer/Counter Control + SBIT(IT0, _TCON, 0); //- + SBIT(IE0, _TCON, 1); //- + SBIT(IT1, _TCON, 2); //- + SBIT(IE1, _TCON, 3); //- + SBIT(TR0, _TCON, 4); //- + SBIT(TF0, _TCON, 5); //- + SBIT(TR1, _TCON, 6); //- + SBIT(TF1, _TCON, 7); //- + +#define _TMOD 0x89 + SFR(TMOD, _TMOD); //- 0000'0000 Timer/Counter Mode Control + #define T0_M0 0x01 //- + #define T0_M1 0x02 //- + #define T0_CT 0x04 //- + #define T0_GATE 0x08 //- + #define T1_M0 0x10 //- + #define T1_M1 0x20 //- + #define T1_CT 0x40 //- + #define T1_GATE 0x80 //- + +#define _TL0 0x8A + SFR(TL0, _TL0); //- 0000'0000 Timer/Counter 0 Low Byte + +#define _TL1 0x8B + SFR(TL1, _TL1); //- 0000'0000 Timer/Counter 1 Low Byte + +#define _TH0 0x8C + SFR(TH0, _TH0); //- 0000'0000 Timer/Counter 0 High Byte + +#define _TH1 0x8D + SFR(TH1, _TH1); //- 0000'0000 Timer/Counter 1 High Byte + +#define _P1 0x90 + SFR(P1, _P1); //- 1111'1111 Port 1 + SBIT( P1_0, _P1, 0); //- + SBIT( P10, _P1, 0); //= + SBIT( P1_1, _P1, 1); //- + SBIT( P11, _P1, 1); //= + SBIT( P1_2, _P1, 2); //- + SBIT( P12, _P1, 2); //= + SBIT( P1_3, _P1, 3); //- + SBIT( P13, _P1, 3); //= + SBIT( P1_4, _P1, 4); //- + SBIT( P14, _P1, 4); //= + SBIT( P1_5, _P1, 5); //- + SBIT( P15, _P1, 5); //= + SBIT( P1_6, _P1, 6); //- + SBIT( P16, _P1, 6); //= + SBIT( P1_7, _P1, 7); //- + SBIT( P17, _P1, 7); //= + +#define _SCON 0x98 + SFR(SCON, _SCON); //- 0000'0000 Serial Port 0 Control + SBIT( RI, _SCON, 0); //- + SBIT( TI, _SCON, 1); //- + SBIT( RB8, _SCON, 2); //- + SBIT( TB8, _SCON, 3); //- + SBIT( REN, _SCON, 4); //- + SBIT( SM2, _SCON, 5); //- + SBIT( SM1, _SCON, 6); //- + SBIT( SM0, _SCON, 7); //- + +#define _SBUF 0x99 + SFR(SBUF, _SBUF); //- XXXX'XXXX Serial Port 0 Data Buffer + +#define _P2 0xA0 + SFR(P2, _P2); //- 1111'1111 Port 2 + SBIT( P2_0, _P2, 0); //- + SBIT( P20, _P2, 0); //= + SBIT( P2_1, _P2, 1); //- + SBIT( P2_2, _P2, 2); //- + SBIT( P2_3, _P2, 3); //- + SBIT( P2_4, _P2, 4); //- + SBIT( P2_5, _P2, 5); //- + SBIT( P2_6, _P2, 6); //- + SBIT( P2_7, _P2, 7); //- + +#define _IE 0xA8 + SFR(IE, _IE); //- 0XX0'0000 Interrupt Enable (8051) + SBIT(EX0, _IE, 0); //- + SBIT(ET0, _IE, 1); //- + SBIT(EX1, _IE, 2); //- + SBIT(ET1, _IE, 3); //- + SBIT(ES, _IE, 4); //- + SBIT(ET2, _IE, 5); //- + SBIT(EA, _IE, 7); //- + +#define _P3 0xB0 + SFR(P3, _P3); //- 1111'1111 Port 3 + SBIT( P3_0, _P3, 0); //- + SBIT( P30, _P3, 0); //= + SBIT( RXD, _P3, 0); //- + SBIT( P3_1, _P3, 1); //- + SBIT( P31, _P3, 1); //= + SBIT( TXD, _P3, 1); //- + SBIT( P3_2, _P3, 2); //= + SBIT( P32, _P3, 2); //= + SBIT( INT0, _P3, 2); //- + SBIT( P3_3, _P3, 3); //- + SBIT( P33, _P3, 3); //- + SBIT( INT1, _P3, 3); //- + SBIT( P3_4, _P3, 4); //- + SBIT( P34, _P3, 4); //- + SBIT( T0, _P3, 4); //- + SBIT( P3_5, _P3, 5); //- + SBIT( P35, _P3, 5); //- + SBIT( T1, _P3, 5); //- + SBIT( P3_6, _P3, 6); //- + SBIT( P36, _P3, 6); //- + SBIT( WR, _P3, 6); //- + SBIT( P3_7, _P3, 7); //- + SBIT( P37, _P3, 7); //- + SBIT( RD, _P3, 7); //- + +#define _IP 0xB8 + SFR(IP, _IP); //- XXX0'0000 Interrupt priority (8051) + SBIT(PX0, _IP, 0); //- + SBIT(PT0, _IP, 1); //- + SBIT(PX1, _IP, 2); //- + SBIT(PT1, _IP, 3); //- + SBIT(PS, _IP, 4); //- + SBIT(PT2, _IP, 5); //- + +#define _PSW 0xD0 //- 0000'0000 Program status word + SFR(PSW, _PSW); //- + SBIT( P, _PSW, 0); //- + SBIT( F1, _PSW, 1); //- + SBIT( OV, _PSW, 2); //- + SBIT( RS0, _PSW, 3); //- + SBIT( RS1, _PSW, 4); //- + SBIT( F0, _PSW, 5); //- + SBIT( AC, _PSW, 6); //- + SBIT( CY, _PSW, 7); //- + +#define _ACC 0xE0 + SFR(ACC, _ACC); //- 0000'0000 Accumulator + SBIT( ACC_0, _ACC, 0); //- + SBIT( ACC_1, _ACC, 1); //- + SBIT( ACC_2, _ACC, 2); //- + SBIT( ACC_3, _ACC, 3); //- + SBIT( ACC_4, _ACC, 4); //- + SBIT( ACC_5, _ACC, 5); //- + SBIT( ACC_6, _ACC, 6); //- + SBIT( ACC_7, _ACC, 7); //- + +#define _B 0xF0 + SFR(B, _B); //- 0000'0000 B register + SBIT( B_0, _B, 0); //- + SBIT( B_1, _B, 1); //- + SBIT( B_2, _B, 2); //- + SBIT( B_3, _B, 3); //- + SBIT( B_4, _B, 4); //- + SBIT( B_5, _B, 5); //- + SBIT( B_6, _B, 6); //- + SBIT( B_7, _B, 7); //- + +//Reset vector absolute address declaration + #define RST_VECTOR 0x00 //- 0x00 Reset Vector +//Interrupt numbers: Address = ( Number * 8 ) + 3 + #define EX0_VECTOR 0 //- 0x03 External Interrupt 0 + #define ET0_VECTOR 1 //- 0x0B Timer 0 + #define EX1_VECTOR 2 //- 0x13 External Interrupt 1 + #define ET1_VECTOR 3 //- 0x1B Timer 1 + #define ES_VECTOR 4 //- 0x23 Serial Port 0 + +#endif \ No newline at end of file diff --git a/examples/anymcu-blink/src/Generic8052.h b/examples/anymcu-blink/src/Generic8052.h new file mode 100644 index 0000000..b737d0e --- /dev/null +++ b/examples/anymcu-blink/src/Generic8052.h @@ -0,0 +1,246 @@ +#ifndef Generic8052_H +#define Generic8052_H +#include + +// Includes extra compatibility enhancements over original 8052.h +// Suitable for use with the original basic 8052 series MCU. +// This header file was verified against the MCS-51 manual. +// After this file is included you don't have to include "reg51.h". +// Comments beginning with //- indicate 8051 and //+ indicate 8052. +// Comments begining with //= indicate defacto standard aliases. +// X means undefined, U means unchanged, C means config dependent. + +//SFR DECLARATION NOTE POR RESET VALUE DESCRIPTION +#define _P0 0x80 + SFR(P0, _P0); //- 1111'1111 Port 0 + SBIT( P0_0, _P0, 0); //- + SBIT( P00, _P0, 0); //= + SBIT( P0_1, _P0, 1); //- + SBIT( P01, _P0, 1); //= + SBIT( P0_2, _P0, 2); //- + SBIT( P02, _P0, 2); //= + SBIT( P0_3, _P0, 3); //- + SBIT( P03, _P0, 3); //= + SBIT( P0_4, _P0, 4); //- + SBIT( P04, _P0, 4); //= + SBIT( P0_5, _P0, 5); //- + SBIT( P05, _P0, 5); //= + SBIT( P0_6, _P0, 6); //- + SBIT( P06, _P0, 6); //= + SBIT( P0_7, _P0, 7); //- + SBIT( P07, _P0, 7); //= + +#define _SP 0x81 + SFR(SP, _SP); //- 0000'0111 Stack pointer + +#define _DPL 0x82 + SFR(DPL, _DPL); //- 0000'0000 Data pointer low byte + +#define _DPH 0x83 + SFR(DPH, _DPH); //- 0000'0000 Data pointer high byte + +#define _PCON 0x87 + SFR(PCON, _PCON); //- 0XXX'0000 Power Control + #define IDL 0x01 //- + #define PD 0x02 //- + #define GF0 0x04 //- + #define GF1 0x08 //- + #define SMOD 0x80 //- + +#define _TCON 0x88 + SFR(TCON, _TCON); //- 0000'0000 Timer/Counter Control + SBIT(IT0, _TCON, 0); //- + SBIT(IE0, _TCON, 1); //- + SBIT(IT1, _TCON, 2); //- + SBIT(IE1, _TCON, 3); //- + SBIT(TR0, _TCON, 4); //- + SBIT(TF0, _TCON, 5); //- + SBIT(TR1, _TCON, 6); //- + SBIT(TF1, _TCON, 7); //- + +#define _TMOD 0x89 + SFR(TMOD, _TMOD); //- 0000'0000 Timer/Counter Mode Control + #define T0_M0 0x01 //- + #define T0_M1 0x02 //- + #define T0_CT 0x04 //- + #define T0_GATE 0x08 //- + #define T1_M0 0x10 //- + #define T1_M1 0x20 //- + #define T1_CT 0x40 //- + #define T1_GATE 0x80 //- + +#define _TL0 0x8A + SFR(TL0, _TL0); //- 0000'0000 Timer/Counter 0 Low Byte + +#define _TL1 0x8B + SFR(TL1, _TL1); //- 0000'0000 Timer/Counter 1 Low Byte + +#define _TH0 0x8C + SFR(TH0, _TH0); //- 0000'0000 Timer/Counter 0 High Byte + +#define _TH1 0x8D + SFR(TH1, _TH1); //- 0000'0000 Timer/Counter 1 High Byte + +#define _P1 0x90 + SFR(P1, _P1); //- 1111'1111 Port 1 + SBIT( P1_0, _P1, 0); //- + SBIT( P10, _P1, 0); //= + SBIT( T2, _P1, 0); //+ + SBIT( P1_1, _P1, 1); //- + SBIT( P11, _P1, 1); //= + SBIT( T2EX, _P1, 1); //+ + SBIT( P1_2, _P1, 2); //- + SBIT( P12, _P1, 2); //= + SBIT( P1_3, _P1, 3); //- + SBIT( P13, _P1, 3); //= + SBIT( P1_4, _P1, 4); //- + SBIT( P14, _P1, 4); //= + SBIT( P1_5, _P1, 5); //- + SBIT( P15, _P1, 5); //= + SBIT( P1_6, _P1, 6); //- + SBIT( P16, _P1, 6); //= + SBIT( P1_7, _P1, 7); //- + SBIT( P17, _P1, 7); //= + +#define _SCON 0x98 + SFR(SCON, _SCON); //- 0000'0000 Serial Port 0 Control + SBIT( RI, _SCON, 0); //- + SBIT( TI, _SCON, 1); //- + SBIT( RB8, _SCON, 2); //- + SBIT( TB8, _SCON, 3); //- + SBIT( REN, _SCON, 4); //- + SBIT( SM2, _SCON, 5); //- + SBIT( SM1, _SCON, 6); //- + SBIT( SM0, _SCON, 7); //- + +#define _SBUF 0x99 + SFR(SBUF, _SBUF); //- XXXX'XXXX Serial Port 0 Data Buffer + +#define _P2 0xA0 + SFR(P2, _P2); //- 1111'1111 Port 2 + SBIT( P2_0, _P2, 0); //- + SBIT( P20, _P2, 0); //= + SBIT( P2_1, _P2, 1); //- + SBIT( P2_2, _P2, 2); //- + SBIT( P2_3, _P2, 3); //- + SBIT( P2_4, _P2, 4); //- + SBIT( P2_5, _P2, 5); //- + SBIT( P2_6, _P2, 6); //- + SBIT( P2_7, _P2, 7); //- + +#define _IE 0xA8 +//SFR(IE, _IE); //- 0XX0'0000 Interrupt Enable (8051) + SFR(IE, _IE); //+ 0X00'0000 Interrupt Enable (8052) + SBIT(EX0, _IE, 0); //- + SBIT(ET0, _IE, 1); //- + SBIT(EX1, _IE, 2); //- + SBIT(ET1, _IE, 3); //- + SBIT(ES, _IE, 4); //- + SBIT(ET2, _IE, 5); //- + SBIT(EA, _IE, 7); //- + +#define _P3 0xB0 + SFR(P3, _P3); //- 1111'1111 Port 3 + SBIT( P3_0, _P3, 0); //- + SBIT( P30, _P3, 0); //= + SBIT( RXD, _P3, 0); //- + SBIT( P3_1, _P3, 1); //- + SBIT( P31, _P3, 1); //= + SBIT( TXD, _P3, 1); //- + SBIT( P3_2, _P3, 2); //= + SBIT( P32, _P3, 2); //= + SBIT( INT0, _P3, 2); //- + SBIT( P3_3, _P3, 3); //- + SBIT( P33, _P3, 3); //- + SBIT( INT1, _P3, 3); //- + SBIT( P3_4, _P3, 4); //- + SBIT( P34, _P3, 4); //- + SBIT( T0, _P3, 4); //- + SBIT( P3_5, _P3, 5); //- + SBIT( P35, _P3, 5); //- + SBIT( T1, _P3, 5); //- + SBIT( P3_6, _P3, 6); //- + SBIT( P36, _P3, 6); //- + SBIT( WR, _P3, 6); //- + SBIT( P3_7, _P3, 7); //- + SBIT( P37, _P3, 7); //- + SBIT( RD, _P3, 7); //- + +#define _IP 0xB8 +//SFR(IP, _IP); //- XXX0'0000 Interrupt priority (8051) + SFR(IP, _IP); //+ XX00'0000 Interrupt priority (8052) + SBIT(PX0, _IP, 0); //- + SBIT(PT0, _IP, 1); //- + SBIT(PX1, _IP, 2); //- + SBIT(PT1, _IP, 3); //- + SBIT(PS, _IP, 4); //- + SBIT(PT2, _IP, 5); //- + +#define _T2CON 0xC8 + SFR(T2CON, _T2CON); //+ 0000'0000 Timer/Counter 2 Control + SBIT( CM_RL2, _T2CON, 0); //+ + SBIT( CP_RL2, _T2CON, 0); //+ + SBIT( C_T2, _T2CON, 1); //+ + SBIT( TR2, _T2CON, 2); //+ + SBIT( EXEN2, _T2CON, 3); //+ + SBIT( TCLK, _T2CON, 4); //+ + SBIT( RCLK, _T2CON, 5); //+ + SBIT( EXF2, _T2CON, 6); //+ + SBIT(TF2, _T2CON, 7); //+ + +#define _RCAP2L 0xCA + SFR(RCAP2L, _RCAP2L); //+ 0000'0000 T/C 2 Capture Reg. Low byte + +#define _RCAP2H 0xCB + SFR(RCAP2H, _RCAP2H); //+ 0000'0000 T/C 2 Capture Reg. High byte + +#define _TL2 0xCC + SFR(TL2, _TL2); //+ 0000'0000 Timer/Counter 2 Low Byte + +#define _TH2 0xCD + SFR(TH2, _TH2); //+ 0000'0000 Timer/Counter 2 High Byte + +#define _PSW 0xD0 //- 0000'0000 Program status word + SFR(PSW, _PSW); //- + SBIT( P, _PSW, 0); //- + SBIT( F1, _PSW, 1); //- + SBIT( OV, _PSW, 2); //- + SBIT( RS0, _PSW, 3); //- + SBIT( RS1, _PSW, 4); //- + SBIT( F0, _PSW, 5); //- + SBIT( AC, _PSW, 6); //- + SBIT( CY, _PSW, 7); //- + +#define _ACC 0xE0 + SFR(ACC, _ACC); //- 0000'0000 Accumulator + SBIT( ACC_0, _ACC, 0); //- + SBIT( ACC_1, _ACC, 1); //- + SBIT( ACC_2, _ACC, 2); //- + SBIT( ACC_3, _ACC, 3); //- + SBIT( ACC_4, _ACC, 4); //- + SBIT( ACC_5, _ACC, 5); //- + SBIT( ACC_6, _ACC, 6); //- + SBIT( ACC_7, _ACC, 7); //- + +#define _B 0xF0 + SFR(B, _B); //- 0000'0000 B register + SBIT( B_0, _B, 0); //- + SBIT( B_1, _B, 1); //- + SBIT( B_2, _B, 2); //- + SBIT( B_3, _B, 3); //- + SBIT( B_4, _B, 4); //- + SBIT( B_5, _B, 5); //- + SBIT( B_6, _B, 6); //- + SBIT( B_7, _B, 7); //- + +//Reset vector absolute address declaration +#define RST_VECTOR 0x00 //- 0x00 Reset Vector +//Interrupt numbers: Address = ( Number * 8 ) + 3 +#define EX0_VECTOR 0 //- 0x03 External Interrupt 0 +#define ET0_VECTOR 1 //- 0x0B Timer 0 +#define EX1_VECTOR 2 //- 0x13 External Interrupt 1 +#define ET1_VECTOR 3 //- 0x1B Timer 1 +#define ES_VECTOR 4 //- 0x23 Serial Port 0 +#define ET2_VECTOR 5 //+ 0x2B Timer 2 + +#endif \ No newline at end of file diff --git a/examples/anymcu-blink/src/N76E003.h b/examples/anymcu-blink/src/N76E003.h new file mode 100644 index 0000000..a44d997 --- /dev/null +++ b/examples/anymcu-blink/src/N76E003.h @@ -0,0 +1,968 @@ +#ifndef N76E003_H +#define N76E003_H +#include + +// Suitable for use with all N76E003 series MCU. +// This header file was verified against the official Nuvoton BSP +// however it corrects a number of Nuvoton BSP inconsistencies. +// After this file is included you don't have to include "reg51.h". +// Comments begining with /// indicate non 8051/8052 extensions. +// Comments beginning with //- indicate 8051 and //+ indicate 8052. +// Comments begining with //= indicate defacto standard aliases. +// X means undefined, U means unchanged, C means config dependent. + +//SFR DEFINITION | NOTE | POR RESET VALUE | DESCRIPTION +#define _P0 0x80 + SFR(P0, _P0); //- 1111'1111 Port 0 + SBIT( P0_0, _P0, 0); //- + SBIT( P00, _P0, 0); //= + SBIT( MOSI, _P0, 0); /// + SBIT( T1, _P0, 0); /// + SBIT( P0_1, _P0, 1); //- + SBIT( P01, _P0, 1); //= + SBIT( MISO, _P0, 1); /// + SBIT( P0_2, _P0, 2); //- + SBIT( P02, _P0, 2); //= + SBIT( RXD_1, _P0, 2); /// + SBIT( P0_3, _P0, 3); //- + SBIT( P03, _P0, 3); //= + SBIT( P0_4, _P0, 4); //- + SBIT( P04, _P0, 4); //= + SBIT( P0_5, _P0, 5); //- + SBIT( P05, _P0, 5); //= + SBIT( T0, _P0, 5); /// + SBIT( P0_6, _P0, 6); //- + SBIT( P06, _P0, 6); //= + SBIT( P0_7, _P0, 7); //- + SBIT( P07, _P0, 7); //= + +#define _SP 0x81 + SFR(SP, _SP); //- 0000'0111 Stack pointer + +#define _DPL 0x82 + SFR(DPL, _DPL); //- 0000'0000 Data pointer low byte + +#define _DPH 0x83 + SFR(DPH, _DPH); //- 0000'0000 Data pointer high byte + +#define _RCTRIM0 0x84 + SFR(RCTRIM0, _RCTRIM0); /// 0000'0000 Internal RC trim value high byte + +#define _RCTRIM1 0x85 + SFR(RCTRIM1, _RCTRIM1); /// 0000'0000 Internal RC trim value low byte + +#define _RWK 0x86 + SFR(RWK, _RWK); /// 0000'0000 Self wake-up timer reload byte + +#define _PCON 0x87 +//SFR(PCON, _PCON); //- 0XXX'0000 Power Control (8051) + SFR(PCON, _PCON); /// 0001'0000 Power Control (N76E003) + #define IDL 0x01 //- + #define PD 0x02 //- + #define GF0 0x04 //- + #define GF1 0x08 //- + #define POF 0x10 /// + #define SMOD0 0x40 /// + #define SMOD 0x80 //- + +#define _TCON 0x88 + SFR(TCON, _TCON); //- 0000'0000 Timer/Counter Control + SBIT(IT0, _TCON, 0); //- + SBIT(IE0, _TCON, 1); //- + SBIT(IT1, _TCON, 2); //- + SBIT(IE1, _TCON, 3); //- + SBIT(TR0, _TCON, 4); //- + SBIT(TF0, _TCON, 5); //- + SBIT(TR1, _TCON, 6); //- + SBIT(TF1, _TCON, 7); //- + +#define _TMOD 0x89 + SFR(TMOD, _TMOD); //- 0000'0000 Timer/Counter Mode Control + #define T0_M0 0x01 //- + #define T0_M1 0x02 //- + #define T0_CT 0x04 //- + #define T0_GATE 0x08 //- + #define T1_M0 0x10 //- + #define T1_M1 0x20 //- + #define T1_CT 0x40 //- + #define T1_GATE 0x80 //- + +#define _TL0 0x8A + SFR(TL0, _TL0); //- 0000'0000 Timer/Counter 0 Low Byte + +#define _TL1 0x8B + SFR(TL1, _TL1); //- 0000'0000 Timer/Counter 1 Low Byte + +#define _TH0 0x8C + SFR(TH0, _TH0); //- 0000'0000 Timer/Counter 0 High Byte + +#define _TH1 0x8D + SFR(TH1, _TH1); //- 0000'0000 Timer/Counter 1 High Byte + +#define _CKCON 0x8E + SFR(CKCON, _CKCON); /// 0000'0000 Clock control + #define CLOEN 0x02 /// + #define T0M 0x08 /// + #define T1M 0x10 /// + #define PWMCKS 0x40 /// + +#define _WKCON 0x8F + SFR(WKCON, _WKCON); /// 0000'0000 Self wake-up timer control + #define WKPS 0x07 /// + #define WKTR 0x08 /// + #define WKTF 0x10 /// + +#define _P1 0x90 + SFR(P1, _P1); //- 1111'1111 Port 1 + SBIT( P1_0, _P1, 0); //- + SBIT( P10, _P1, 0); //= +//SBIT( T2, _P1, 0); //+ Software defined on N76E003 + SBIT( SPCLK, _P1, 0); /// + SBIT( P1_1, _P1, 1); //- + SBIT( P11, _P1, 1); //= +//SBIT( T2EX, _P1, 1); //+ Software defined on N76E003 + SBIT( P1_2, _P1, 2); //- + SBIT( P12, _P1, 2); //= + SBIT( P1_3, _P1, 3); //- + SBIT( P13, _P1, 3); //= + SBIT( P1_4, _P1, 4); //- + SBIT( P14, _P1, 4); //= + SBIT( FB, _P1, 4); /// + SBIT( P1_5, _P1, 5); //- + SBIT( P15, _P1, 5); //= + SBIT( SS, _P1, 5); /// + SBIT( P1_6, _P1, 6); //- + SBIT( P16, _P1, 6); //= + SBIT( TXD_1, _P1, 6); /// + SBIT( P1_7, _P1, 7); //- + SBIT( INT1, _P1, 7); /// + SBIT( P17, _P1, 7); //= + +#define _SFRS 0x91 + SFR(SFRS, _SFRS); /// TA 0000'0000 SFR page selection + #define SFRPAGE 0x01 /// + +#define _CAPCON0 0x92 + SFR(CAPCON0, _CAPCON0); /// 0000'0000 Input capture control 0 + #define CAPF0 0x01 /// + #define CAPF1 0x02 /// + #define CAPF2 0x04 /// + #define CAPEN0 0x10 /// + #define CAPEN1 0x20 /// + #define CAPEN2 0x40 /// + +#define _CAPCON1 0x93 + SFR(CAPCON1, _CAPCON1); /// 0000'0000 Input capture control 1 + #define CAP0LS 0x03 /// + #define CAP1LS 0x0C /// + #define CAP2LS 0x30 /// + +#define _CAPCON2 0x94 + SFR(CAPCON2, _CAPCON2); /// 0000'0000 Input capture control 2 + #define ENF0 0x10 /// + #define ENF1 0x20 /// + #define ENF2 0x40 /// + +#define _CKDIV 0x95 + SFR(CKDIV, _CKDIV); /// 0000'0000 Clock divider + +#define _CKSWT 0x96 + SFR(CKSWT, _CKSWT); /// TA 0011'0000 Clock switch + #define OSC 0x06 /// + #define ECLKST 0x08 /// + #define LIRCST 0x10 /// + #define HIRCST 0x20 /// + +#define _CKEN 0x97 + SFR(CKEN, _CKEN); /// TA 0011'0000 Clock enable + #define CKSWTF 0x01 /// + #define HIRCEN 0x20 /// + #define EXTEN 0xC0 /// + +#define _SCON 0x98 + SFR(SCON, _SCON); //- 0000'0000 Serial Port 0 Control + SBIT( RI, _SCON, 0); //- + SBIT( TI, _SCON, 1); //- + SBIT( RB8, _SCON, 2); //- + SBIT( TB8, _SCON, 3); //- + SBIT( REN, _SCON, 4); //- + SBIT( SM2, _SCON, 5); //- + SBIT( SM1, _SCON, 6); //- +//SBIT( SM0, _SCON, 7); //- (8051) + SBIT( SM0, _SCON, 7); /// Write (N76E003) + SBIT( FE, _SCON, 7); /// Read + +#define _SBUF 0x99 +//SFR(SBUF, _SBUF); //- XXXX'XXXX Serial Port 0 Data Buffer (8051) + SFR(SBUF, _SBUF); /// 0000'0000 Serial Port 0 Data Buffer (N76E003) + +#define _SBUF_1 0x9A + SFR(SBUF_1, _SBUF_1); /// 0000'0000 Serial port 1 data buffer + +#define _EIE 0x9B + SFR(EIE, _EIE); /// 0000'0000 Extensive interrupt enable + #define EI2C 0x01 /// + #define EPI 0x02 /// + #define ECAP 0x04 /// + #define EPWM 0x08 /// + #define EWDT 0x10 /// + #define EFB 0x20 /// + #define ESPI 0x40 /// + #define ET2 0x80 /// + +#define _EIE1 0x9C + SFR(EIE1, _EIE1); /// 0000'0000 Extensive interrupt enable 1 + #define EX_1 0x01 /// + #define ET3 0x02 /// + #define EWKT 0x04 /// + +#define _CHPCON 0x9F + SFR(CHPCON, _CHPCON); /// TA 0000'00C0 Chip control + #define IAPEN 0x01 /// + #define BS 0x02 /// + #define IAPFF 0x40 /// + #define SWRST 0x80 /// + +#define _P2 0xA0 +//SFR(P2, _P2); //- 1111'1111 Port 2 (8051) + SFR(P2, _P2); /// 0000'000X Port 2 (N76E003) + SBIT( P2_0, _P2, 0); //- + SBIT( P20, _P2, 0); //= + SBIT( RST, _P2, 0); /// +//SBIT( P2_1, _P2, 1); //- Not available on N76E003 +//SBIT( P2_2, _P2, 2); //- Not available on N76E003 +//SBIT( P2_3, _P2, 3); //- Not available on N76E003 +//SBIT( P2_4, _P2, 4); //- Not available on N76E003 +//SBIT( P2_5, _P2, 5); //- Not available on N76E003 +//SBIT( P2_6, _P2, 6); //- Not available on N76E003 +//SBIT( P2_7, _P2, 7); //- Not available on N76E003 + +#define _AUXR1 0xA2 + SFR(AUXR1, _AUXR1); /// 0000'0000 Auxiliary register 1 + #define UART0PX 0x04 /// + #define GF2 0x08 /// + #define HardF 0x20 /// + #define RSTPINF 0x40 /// + #define SWRF 0x80 /// + +#define _BODCON0 0xA3 + SFR(BODCON0, _BODCON0); /// TA CCCC'XC0X Brown-out detection control 0 + #define BOS 0x01 /// + #define BORF 0x02 /// + #define BORST 0x04 /// + #define BOF 0x08 /// + #define BOV 0x30 /// + #define BODEN 0x80 /// + +#define _IAPTRG 0xA4 + SFR(IAPTRG, _IAPTRG); /// TA 0000'0000 IAP trigger + #define IAPGO 0x01 /// + +#define _IAPUEN 0xA5 + SFR(IAPUEN, _IAPUEN); /// TA 0000'0000 IAP update enable + #define APUEN 0x01 /// + #define LDUEN 0x02 /// + #define CFUEN 0x04 /// + +#define _IAPAL 0xA6 + SFR(IAPAL, _IAPAL); /// 0000'0000 IAP address low byte + +#define _IAPAH 0xA7 + SFR(IAPAH, _IAPAH); /// 0000'0000 IAP address high byte + +#define _IE 0xA8 +//SFR(IE, _IE); //- 0XX0'0000 Interrupt Enable (8051) +//SFR(IE, _IE); //+ 0X00'0000 Interrupt Enable (8052) + SFR(IE, _IE); /// 0000'0000 Interrupt Enable (N76E003) + SBIT(EX0, _IE, 0); //- + SBIT(ET0, _IE, 1); //- + SBIT(EX1, _IE, 2); //- + SBIT(ET1, _IE, 3); //- + SBIT(ES, _IE, 4); //- + SBIT(EBOD, _IE, 5); /// (N76E003) +//SBIT(ET2, _IE, 5); //- (8051) + SBIT(EADC, _IE, 6); /// + SBIT(EA, _IE, 7); //- + +#define _SADDR 0xA9 + SFR(SADDR, _SADDR); /// 0000'0000 Slave 0 address + +#define _WDCON 0xAA + SFR(WDCON, _WDCON); /// TA 0000'0111 Watchdog timer control + #define WDPS 0x07 /// + #define WDTRF 0x08 /// + #define WIDPD 0x10 /// + #define WDTF 0x20 /// + #define WDCLR 0x40 /// + #define WDTR 0x80 /// + +#define _BODCON1 0xAB + SFR(BODCON1, _BODCON1); /// TA 0000'0001 Brown-out detection control 1 + #define BODFLT 0x01 /// + #define LPBOD 0x06 /// + +#define _P3M1 0xAC + SFR(P3M1, _P3M1); /// 0000'0001 P3 mode select 1 + #define P3M1_0 0x01 /// + +#define _P3S 0xAC + SFR(P3S, _P3S); /// Page1 0000'0000 P3 Schmitt trigger input + #define P3S_0 0x01 /// + +#define _P3M2 0xAD + SFR(P3M2, _P3M2); /// 0000'0000 P3 mode select 2 + #define P3M2_0 0x01 /// + +#define _P3SR 0xAD + SFR(P3SR, _P3SR); /// Page1 0000'0000 P3 slew rate + #define P3SR_0 0x01 /// + +#define _IAPFD 0xAE + SFR(IAPFD, _IAPFD); /// 0000'0000 IAP flash data + +#define _IAPCN 0xAF + SFR(IAPCN, _IAPCN); /// 0011'0000 IAP control + #define FCTRL 0x0F /// + #define FCEN 0x10 /// + #define FOEN 0x20 /// + #define IAPB 0xC0 /// + +#define _P3 0xB0 +//SFR(P3, _P3); //- 1111'1111 Port 3 (8051) + SFR(P3, _P3); /// 0000'0001 Port 3 (N76E003) + SBIT( P3_0, _P3, 0); //- + SBIT( P30, _P3, 0); //= +//SBIT( RXD, _P3, 0); //- Software defined on N76E003 + SBIT( INT0, _P3, 0); /// + SBIT( XIN, _P3, 0); /// +//SBIT( P3_1, _P3, 1); //- Not available on N76E003 +//SBIT( P31, _P3, 1); //= Not available on N76E003 +//SBIT( TXD, _P3, 1); //- Software defined on N76E003 +//SBIT( P3_2, _P3, 2); //= Not available on N76E003 +//SBIT( P32, _P3, 2); //= Not available on N76E003 +//SBIT( INT0, _P3, 2); //- Mapped to P3.0 on N76E003 +//SBIT( P3_3, _P3, 3); //- Not available on N76E003 +//SBIT( P33, _P3, 3); //- Not available on N76E003 +//SBIT( INT1, _P3, 3); //- Mapped to P1.7 on N76E003 +//SBIT( P3_4, _P3, 4); //- Not available on N76E003 +//SBIT( P34, _P3, 4); //- Not available on N76E003 +//SBIT( T0, _P3, 4); //- Mapped to P0.5 on N76E003 +//SBIT( P3_5, _P3, 5); //- Not available on N76E003 +//SBIT( P35, _P3, 5); //- Not available on N76E003 +//SBIT( T1, _P3, 5); //- Mapped to P0.0 on N76E003 +//SBIT( P3_6, _P3, 6); //- Not available on N76E003 +//SBIT( P36, _P3, 6); //- Not available on N76E003 +//SBIT( WR, _P3, 6); //- Not available on N76E003 +//SBIT( P3_7, _P3, 7); //- Not available on N76E003 +//SBIT( P37, _P3, 7); //- Not available on N76E003 +//SBIT( RD, _P3, 7); //- Not available on N76E003 + +#define _P0M1 0xB1 + SFR(P0M1, _P0M1); /// 1111'1111 P0 mode select 1 + #define P0M1_0 0x01 /// + #define P0M1_1 0x02 /// + #define P0M1_2 0x04 /// + #define P0M1_3 0x08 /// + #define P0M1_4 0x10 /// + #define P0M1_5 0x20 /// + #define P0M1_6 0x40 /// + #define P0M1_7 0x80 /// + +#define _P0S 0xB1 + SFR(P0S, _P0S); /// Page1 0000'0000 P0 Schmitt trigger input + #define P0S1_0 0x01 /// + #define P0S1_1 0x02 /// + #define P0S1_2 0x04 /// + #define P0S1_3 0x08 /// + #define P0S1_4 0x10 /// + #define P0S1_5 0x20 /// + #define P0S1_6 0x40 /// + #define P0S1_7 0x80 /// + +#define _P0M2 0xB2 + SFR(P0M2, _P0M2); /// 0000'0000 P0 mode select 2 + #define P0M2_0 0x01 /// + #define P0M2_1 0x02 /// + #define P0M2_2 0x04 /// + #define P0M2_3 0x08 /// + #define P0M2_4 0x10 /// + #define P0M2_5 0x20 /// + #define P0M2_6 0x40 /// + #define P0M2_7 0x80 /// + +#define _P0SR 0xB2 + SFR(P0SR, _P0SR); /// Page1 0000'0000 P0 slew rate + #define P0SR1_0 0x01 /// + #define P0SR1_1 0x02 /// + #define P0SR1_2 0x04 /// + #define P0SR1_3 0x08 /// + #define P0SR1_4 0x10 /// + #define P0SR1_5 0x20 /// + #define P0SR1_6 0x40 /// + #define P0SR1_7 0x80 /// + +#define _P1M1 0xB3 + SFR(P1M1, _P1M1); /// 1111'1111 P1 mode select 1 + #define P1M1_0 0x01 /// + #define P1M1_1 0x02 /// + #define P1M1_2 0x04 /// + #define P1M1_3 0x08 /// + #define P1M1_4 0x10 /// + #define P1M1_5 0x20 /// + #define P1M1_6 0x40 /// + #define P1M1_7 0x80 /// + +#define _P1S 0xB3 + SFR(P1S, _P1S); /// Page1 0000'0000 P1 Schmitt trigger input + #define P1S1_0 0x01 /// + #define P1S1_1 0x02 /// + #define P1S1_2 0x04 /// + #define P1S1_3 0x08 /// + #define P1S1_4 0x10 /// + #define P1S1_5 0x20 /// + #define P1S1_6 0x40 /// + #define P1S1_7 0x80 /// + +#define _P1M2 0xB4 + SFR(P1M2, _P1M2); /// 0000'0000 P1 mode select 2 + #define P1M2_0 0x01 /// + #define P1M2_1 0x02 /// + #define P1M2_2 0x04 /// + #define P1M2_3 0x08 /// + #define P1M2_4 0x10 /// + #define P1M2_5 0x20 /// + #define P1M2_6 0x40 /// + #define P1M2_7 0x80 /// + +#define _P1SR 0xB4 + SFR(P1SR, _P1SR); /// Page1 0000'0000 P1 slew rate + #define P1SR1_0 0x01 /// + #define P1SR1_1 0x02 /// + #define P1SR1_2 0x04 /// + #define P1SR1_3 0x08 /// + #define P1SR1_4 0x10 /// + #define P1SR1_5 0x20 /// + #define P1SR1_6 0x40 /// + #define P1SR1_7 0x80 /// + +#define _P2S 0xB5 + SFR(P2S, _P2S); /// 0000'0000 P20 setting and Timer 0/1 output enable + #define P2S_0 0x01 /// + #define T0OE 0x04 /// + #define T1OE 0x08 /// + #define P20UP 0x80 /// + +#define _IPH 0xB7 + SFR(IPH, _IPH); /// 0000'0000 Interrupt priority high + #define PX0H 0x01 /// + #define PT0H 0x02 /// + #define PX1H 0x04 /// + #define PT1H 0x08 /// + #define PSH 0x10 /// + #define PBODH 0x20 /// + #define PADCH 0x40 /// + +#define _PWMINTC 0xB7 + SFR(PWMINTC, _PWMINTC); ///Page1 0000'0000 PWM interrupt control + #define INTSEL0 0x01 /// + #define INTSEL1 0x02 /// + #define INTSEL2 0x04 /// + #define INTTYP0 0x10 /// + #define INTTYP1 0x20 /// + +#define _IP 0xB8 +//SFR(IP, _IP); //- XXX0'0000 Interrupt priority (8051) +//SFR(IP, _IP); //+ XX00'0000 Interrupt priority (8052) + SFR(IP, _IP); /// 0000'0000 Interrupt priority (N76E003) + SBIT(PX0, _IP, 0); //- + SBIT(PT0, _IP, 1); //- + SBIT(PX1, _IP, 2); //- + SBIT(PT1, _IP, 3); //- + SBIT(PS, _IP, 4); //- + SBIT(PBOD, _IP, 5); /// (N76E003) +//SBIT(PT2, _IP, 5); //- (8051) + SBIT(PADC, _IP, 6); /// + +#define _SADEN 0xB9 + SFR(SADEN, _SADEN); /// 0000'0000 Slave 0 address mask + +#define _SADEN_1 0xBA + SFR(SADEN_1, _SADEN_1); /// 0000'0000 Slave 1 address mask + +#define _SADDR_1 0xBB + SFR(SADDR_1, _SADDR_1); /// 0000'0000 Slave 1 address + +#define _I2DAT 0xBC + SFR(I2DAT, _I2DAT); /// 0000'0000 I2C data + +#define _I2STAT 0xBD + SFR(I2STAT, _I2STAT); /// 1111'1000 I2C status + #define I2STAT 0xF8 /// + +#define _I2CLK 0xBE + SFR(I2CLK, _I2CLK); /// 0000'1001 I2C clock + +#define _I2TOC 0xBF + SFR(I2TOC, _I2TOC); /// 0000'0000 I2C time-out counter + #define I2TOF 0x01 /// + #define DIV 0x02 /// + #define I2TOCEN 0x04 /// + +#define _I2CON 0xC0 + SFR(I2CON, _I2CON); /// 0000'0000 I2C control + SBIT( I2CPX, _I2CON, 0); /// + SBIT( AA, _I2CON, 2); /// + SBIT( SI, _I2CON, 3); /// + SBIT( STO, _I2CON, 4); /// + SBIT( STA, _I2CON, 5); /// + SBIT( I2CEN, _I2CON, 6); /// + +#define _I2ADDR 0xC1 + SFR(I2ADDR, _I2ADDR); /// 0000'0000 I2C own slave address + #define GC 0x01 /// + #define I2ADDR 0xFE /// + +#define _ADCRL 0xC2 + SFR(ADCRL, _ADCRL); /// 0000'0000 ADC result low byte + +#define _ADCRH 0xC3 + SFR(ADCRH, _ADCRH); /// 0000'0000 ADC result high byte + +#define _T3CON 0xC4 + SFR(T3CON, _T3CON); /// 0000'0000 Timer 3 control + #define T3PS 0x07 /// + #define TR3 0x80 /// + #define TF3 0x10 /// + #define BRCK 0x20 /// + #define SMOD0_1 0x40 /// + #define SMOD_1 0x80 /// + +#define _PWM4H 0xC4 + SFR(PWM4H, _PWM4H); /// Page1 0000'0000 PWM4 duty high byte + +#define _RL3 0xC5 /// 0000'0000 Timer 3 reload low byte + SFR(RL3, _RL3); /// + +#define _PWM5H 0xC5 + SFR(PWM5H, _PWM5H); /// Page1 0000'0000 PWM5 duty high byte + +#define _RH3 0xC6 + SFR(RH3, _RH3); /// 0000'0000 Timer 3 reload high byte + +#define _PIOCON1 0xC6 + SFR(PIOCON1, _PIOCON1); /// Page1 0000'0000 PWM I/O switch 1 + #define PIO11 0x02 /// + #define PIO12 0x04 /// + #define PIO13 0x08 /// + #define PIO15 0x20 /// + +#define _TA 0xC7 + SFR(TA, _TA); /// 0000'0000 Timed access protection + +#define _T2CON 0xC8 + SFR(T2CON, _T2CON); //+ 0000'0000 Timer/Counter 2 Control + SBIT( CM_RL2, _T2CON, 0); //+ +//SBIT( CP_RL2, _T2CON, 0); //+ (8051) +//SBIT( C_T2, _T2CON, 1); //+ (8051) + SBIT( TR2, _T2CON, 2); //+ +//SBIT( EXEN2, _T2CON, 3); //+ (8051) +//SBIT( TCLK, _T2CON, 4); //+ (8051) +//SBIT( RCLK, _T2CON, 5); //+ (8051) +//SBIT( EXF2, _T2CON, 6); //+ (8051) + SBIT(TF2, _T2CON, 7); //+ + +#define _T2MOD 0xC9 + SFR(T2MOD, _T2MOD); /// 0000'0000 Timer 2 mode + #define LDTS 0x03 /// + #define CMPCR 0x04 /// + #define CAPCR 0x08 /// + #define T2DIV 0x70 /// + #define LDEN 0x80 /// + +#define _RCMP2L 0xCA + SFR(RCMP2L, _RCMP2L); /// 0000'0000 Timer 2 compare low byte (N76E003) + +//#define _RCAP2L 0xCA +//SFR(RCAP2L, _RCAP2L); //+ 0000'0000 T/C 2 Capture Reg. Low byte (8052) + +#define _RCMP2H 0xCB + SFR(RCMP2H, _RCMP2H); /// 0000'0000 Timer 2 compare high byte (N76E003) + +//#define _RCAP2H 0xCB +//SFR(RCAP2H, _RCAP2H); //+ 0000'0000 T/C 2 Capture Reg. High byte (8052) + +#define _TL2 0xCC + SFR(TL2, _TL2); //+ 0000'0000 Timer/Counter 2 Low Byte + +#define _PWM4L 0xCC + SFR(PWM4L, _PWM4L); /// Page1 0000'0000 PWM4 duty low byte + +#define _TH2 0xCD + SFR(TH2, _TH2); //+ 0000'0000 Timer/Counter 2 High Byte + +#define _PWM5L 0xCD + SFR(PWM5L, _PWM5L); ///Page1 0000'0000 PWM5 duty low byte + +#define _ADCMPL 0xCE + SFR(ADCMPL, _ADCMPL); /// 0000'0000 ADC compare low byte + +#define _ADCMPH 0xCF + SFR(ADCMPH, _ADCMPH); /// 0000'0000 ADC compare high byte + +#define _PSW 0xD0 //- 0000'0000 Program status word + SFR(PSW, _PSW); //- + SBIT( P, _PSW, 0); //- + SBIT( F1, _PSW, 1); //- + SBIT( OV, _PSW, 2); //- + SBIT( RS0, _PSW, 3); //- + SBIT( RS1, _PSW, 4); //- + SBIT( F0, _PSW, 5); //- + SBIT( AC, _PSW, 6); //- + SBIT( CY, _PSW, 7); //- + +#define _PWMPH 0xD1 + SFR(PWMPH, _PWMPH); /// 0000'0000 PWM period high byte + +#define _PWM0H 0xD2 + SFR(PWM0H, _PWM0H); /// 0000'0000 PWM0 duty high byte + +#define _PWM1H 0xD3 + SFR(PWM1H, _PWM1H); /// 0000'0000 PWM1 duty high byte + +#define _PWM2H 0xD4 + SFR(PWM2H, _PWM2H); /// 0000'0000 PWM2 duty high byte + +#define _PWM3H 0xD5 + SFR(PWM3H, _PWM3H); /// 0000'0000 PWM3 duty high byte + +#define _PNP 0xD6 + SFR(PNP, _PNP); /// 0000'0000 PWM negative polarity + #define PNP0 0x01 /// + #define PNP1 0x02 /// + #define PNP2 0x04 /// + #define PNP3 0x08 /// + #define PNP4 0x10 /// + #define PNP5 0x20 /// + +#define _FBD 0xD7 + SFR(FBD, _FBD); /// 0000'0000 Brake data + #define FBD0 0x01 /// + #define FBD1 0x02 /// + #define FBD2 0x04 /// + #define FBD3 0x08 /// + #define FBD4 0x10 /// + #define FBD5 0x20 /// + #define FBINLS 0x40 /// + #define FBF 0x80 /// + +#define _PWMCON0 0xD8 + SFR(PWMCON0, _PWMCON0); /// 0000'0000 PWM control 0 + SBIT( CLRPWM, _PWMCON0, 4); /// + SBIT( PWMF, _PWMCON0, 5); /// + SBIT( LOAD, _PWMCON0, 6); /// + SBIT( PWMRUN, _PWMCON0, 7); /// + +#define _PWMPL 0xD9 + SFR(PWMPL, _PWMPL); /// 0000'0000 PWM period low byte + +#define _PWM0L 0xDA + SFR(PWM0L, _PWM0L); /// 0000'0000 PWM0 duty low byte + +#define _PWM1L 0xDB + SFR(PWM1L, _PWM1L); /// 0000'0000 PWM1 duty low byte + +#define _PWM2L 0xDC + SFR(PWM2L, _PWM2L); /// 0000'0000 PWM2 duty low byte + +#define _PWM3L 0xDD + SFR(PWM3L, _PWM3L); /// 0000'0000 PWM3 duty low byte + +#define _PIOCON0 0xDE + SFR(PIOCON0, _PIOCON0); /// 0000'0000 PWM I/O switch 0 + #define PIO00 0x01 /// + #define PIO01 0x02 /// + #define PIO02 0x04 /// + #define PIO03 0x08 /// + #define PIO04 0x10 /// + #define PIO05 0x20 /// + +#define _PWMCON1 0xDF + SFR(PWMCON1, _PWMCON1); /// 0000'0000 PWM control 1 + #define PWMDIV 0x07 /// + #define FBINEN 0x08 /// + #define PWMTYP 0x10 /// + #define GP 0x20 /// + #define PWMMOD 0xC0 /// + +#define _ACC 0xE0 + SFR(ACC, _ACC); //- 0000'0000 Accumulator + SBIT( ACC_0, _ACC, 0); //- + SBIT( ACC_1, _ACC, 1); //- + SBIT( ACC_2, _ACC, 2); //- + SBIT( ACC_3, _ACC, 3); //- + SBIT( ACC_4, _ACC, 4); //- + SBIT( ACC_5, _ACC, 5); //- + SBIT( ACC_6, _ACC, 6); //- + SBIT( ACC_7, _ACC, 7); //- + +#define _ADCCON1 0xE1 + SFR(ADCCON1, _ADCCON1); /// 0000'0000 ADC control 1 + #define ADCEN 0x01 /// + #define ADCEX 0x02 /// + #define ETGTYP 0x0C /// + #define STADCPX 0x40 /// + +#define _ADCCON2 0xE2 + SFR(ADCCON2, _ADCCON2); /// 0000'0000 ADC control 2 + #define ADCDLY_8 0x01 /// + #define ADCMPO 0x10 /// + #define ADCMPEN 0x20 /// + #define ADCMPOP 0x40 /// + #define ADFBEN 0x80 /// + +#define _ADCDLY 0xE3 + SFR(ADCDLY, _ADCDLY); /// 0000'0000 ADC trigger delay + +#define _C0L 0xE4 + SFR(C0L, _C0L); /// 0000'0000 Input capture 0 low byte + +#define _C0H 0xE5 + SFR(C0H, _C0H); /// 0000'0000 Input capture 0 high byte + +#define _C1L 0xE6 + SFR(C1L, _C1L); /// 0000'0000 Input capture 1 low byte + +#define _C1H 0xE7 + SFR(C1H, _C1H); /// 0000'0000 Input capture 1 high byte + +#define _ADCCON0 0xE8 + SFR(ADCCON0, _ADCCON0); /// 0000'0000 ADC control 0 + SBIT( ADCHS0, _ADCCON0, 0); /// + SBIT( ADCHS1, _ADCCON0, 1); /// + SBIT( ADCHS2, _ADCCON0, 2); /// + SBIT( ADCHS3, _ADCCON0, 3); /// + SBIT( ETGSEL0, _ADCCON0, 4); /// + SBIT( ETGSEL1, _ADCCON0, 5); /// + SBIT( ADCS, _ADCCON0, 6); /// + SBIT( ADCF, _ADCCON0, 7); /// + +#define _PICON 0xE9 +SFR(PICON, _PICON); /// 0000'0000 Pin interrupt control + #define PIPS 0x03 /// + #define PITO 0x04 /// + #define PIT1 0x08 /// + #define PIT2 0x10 /// + #define PIT3 0x20 /// + #define PIT45 0x40 /// + #define PIT67 0x80 /// + +#define _PINEN 0xEA +SFR(PINEN, _PINEN); /// 0000'0000 Pin interrupt low level/falling edge enable + #define PINEN0 0x01 /// + #define PINEN1 0x02 /// + #define PINEN2 0x04 /// + #define PINEN3 0x08 /// + #define PINEN4 0x10 /// + #define PINEN5 0x20 /// + #define PIN3N6 0x40 /// + #define PINEN7 0x80 /// + +#define _PIPEN 0xEB +SFR(PIPEN, _PIPEN); /// 0000'0000 Pin interrupt high level/rising edge enable + #define PIPEN0 0x01 /// + #define PIPEN1 0x02 /// + #define PIPEN2 0x04 /// + #define PIPEN3 0x08 /// + #define PIPEN4 0x10 /// + #define PIPEN5 0x20 /// + #define PIP3N6 0x40 /// + #define PIPEN7 0x80 /// + +#define _PIF 0xEC + SFR(PIF, _PIF); /// 0000'0000 Pin interrupt flag + #define PIF0 0x01 /// + #define PIF1 0x02 /// + #define PIF2 0x04 /// + #define PIF3 0x08 /// + #define PIF4 0x10 /// + #define PIF5 0x20 /// + #define PIF6 0x40 /// + #define PIF7 0x80 /// + +#define _C2L 0xED + SFR(C2L, _C2L); /// 0000'0000 Input capture 2 low byte + +#define _C2H 0xEE + SFR(C2H, _C2H); /// 0000'0000 Input capture 2 high byte + +#define _EIP 0xEF + SFR(EIP, _EIP); /// 0000'0000 Extensive interrupt priority + #define PI2C 0x01 /// + #define PPI 0x02 /// + #define PCAP 0x04 /// + #define PPWM 0x08 /// + #define PWDT 0x10 /// + #define PFB 0x20 /// + #define PSPI 0x40 /// + #define PT2 0x80 /// + +#define _B 0xF0 + SFR(B, _B); //- 0000'0000 B register + SBIT( B_0, _B, 0); //- + SBIT( B_1, _B, 1); //- + SBIT( B_2, _B, 2); //- + SBIT( B_3, _B, 3); //- + SBIT( B_4, _B, 4); //- + SBIT( B_5, _B, 5); //- + SBIT( B_6, _B, 6); //- + SBIT( B_7, _B, 7); //- + +#define _CAPCON3 0xF1 + SFR(CAPCON3, _CAPCON3); /// 0000'0000 Input capture control 3 + #define CAP00 0x01 /// + #define CAP01 0x02 /// + #define CAP02 0x04 /// + #define CAP03 0x08 /// + #define CAP10 0x10 /// + #define CAP11 0x20 /// + #define CAP12 0x40 /// + #define CAP13 0x80 /// + +#define _CAPCON4 0xF2 + SFR(CAPCON4, _CAPCON4); /// 0000'0000 Input capture control 4 + #define CAP20 0x01 /// + #define CAP21 0x02 /// + #define CAP22 0x04 /// + #define CAP23 0x08 /// + +#define _SPCR 0xF3 + SFR(SPCR, _SPCR); /// 0000'0000 SPI control + #define SPR0 0x01 /// + #define SPR1 0x02 /// + #define CPHA 0x04 /// + #define CPOL 0x08 /// + #define MSTR 0x10 /// + #define LSBFE 0x20 /// + #define SPIEN 0x40 /// + #define SSOE 0x80 /// + +#define _SPCR2 0xF3 + SFR(SPCR2, _SPCR2); ///Page1 0000'0000 SPI control 2 + #define SPIS0 0x01 /// + #define SPIS1 0x02 /// + +#define _SPSR 0xF4 + SFR(SPSR, _SPSR); /// 0000'0000 SPI status + #define TXBUF 0x04 /// + #define DISMODF 0x08 /// + #define MODF 0x10 /// + #define SPIOVF 0x20 /// + #define WCOL 0x40 /// + #define SPIF 0x80 /// + +#define _SPDR 0xF5 + SFR(SPDR, _SPDR); /// 0000'0000 SPI data + +#define _AINDIDS 0xF6 + SFR(AINDIDS, _AINDIDS); /// 0000'0000 ADC channel digital input disable + #define P17DIDS 0x01 /// + #define P30DIDS 0x02 /// + #define P07DIDS 0x04 /// + #define P06DIDS 0x08 /// + #define P05DIDS 0x10 /// + #define P04DIDS 0x20 /// + #define P03DIDS 0x40 /// + #define P11DIDS 0x80 /// + +#define _EIPH 0xF7 + SFR(EIPH, _EIPH); /// 0000'0000 Extensive interrupt priority high + #define PI2CH 0x01 /// + #define PPIH 0x02 /// + #define PCAPH 0x04 /// + #define PPWMH 0x08 /// + #define PWDTH 0x10 /// + #define PFBH 0x20 /// + #define PSPIH 0x40 /// + #define PT2H 0x80 /// + +#define _SCON_1 0xF8 + SFR(SCON_1, _SCON_1); /// 0000'0000 Serial port 1 control + SBIT( RI_1, _SCON_1, 0); /// + SBIT( TI_1, _SCON_1, 1); /// + SBIT( RB8_1, _SCON_1, 2); /// + SBIT( TB8_1, _SCON_1, 3); /// + SBIT( REN_1, _SCON_1, 4); /// + SBIT( SM2_1, _SCON_1, 5); /// + SBIT( SM1_1, _SCON_1, 6); /// + SBIT( SM0_1, _SCON_1, 7); /// Write + SBIT( FE_1, _SCON_1, 7); /// Read + +#define _PDTEN 0xF9 + SFR(PDTEN, _PDTEN); /// TA 0000'0000 PWM dead time enable + #define PDT01N 0x01 /// + #define PDT23N 0x02 /// + #define PDT45N 0x04 /// + #define PDTCNT_8 0x10 /// + +#define _PDTCNT 0xFA + SFR(PDTCNT, _PDTCNT); /// TA 0000'0000 PWM dead-time counter + +#define _PMEN 0xFB + SFR(PMEN, _PMEN); /// 0000'0000 PWM mask enable + #define PMEN0 0x01 /// + #define PMEN1 0x02 /// + #define PMEN2 0x04 /// + #define PMEN3 0x08 /// + #define PMEN4 0x10 /// + #define PMEN5 0x20 /// + +#define _PMD 0xFC + SFR(PMD, _PMD); /// 0000'0000 PWM mask data + #define PMD0 0x01 /// + #define PMD1 0x02 /// + #define PMD2 0x04 /// + #define PMD3 0x08 /// + #define PMD4 0x10 /// + #define PMD5 0x20 /// + +#define _PORDIS 0xFD + SFR(PORDIS, _PORDIS); /// TA 0000'0000 POR disable + +#define _EIP1 0xFE + SFR(EIP1, _EIP1); /// 0000'0000 Extensive interrupt priority 1 + #define PS_1 0x01 /// + #define PT3 0x02 /// + #define PWKT 0x04 /// + +#define _EIPH1 0xFF + SFR(EIPH1, _EIPH1); /// 0000'0000 Extensive interrupt priority high 1 + #define PSH_1 0x01 /// + #define PT3H 0x02 /// + #define PWKTH 0x04 /// + +//Reset vector absolute address declaration +#define RST_VECTOR 0x00 //- 0x00 Reset Vector +//Interrupt numbers: Address = ( Number * 8 ) + 3 +//Vectors are named after their corresponding interrupt +//enable register bit, so that we don't have to make up +//names and can be consisten across different 8051 MCUs +#define EX0_VECTOR 0 //- 0x03 External Interrupt 0 +#define ET0_VECTOR 1 //- 0x0B Timer 0 +#define EX1_VECTOR 2 //- 0x13 External Interrupt 1 +#define ET1_VECTOR 3 //- 0x1B Timer 1 +#define ES_VECTOR 4 //- 0x23 Serial Port 0 +#define ET2_VECTOR 5 //+ 0x2B Timer 2 +#define EI2C_VECTOR 6 /// 0x33 I2C +#define EP1_VECTOR 7 /// 0x3B Pin Interrupt +#define EBOD_VECTOR 8 /// 0x43 Brown-out +#define ESPI_VECTOR 9 /// 0x4B SPI +#define EWDT_VECTOR 10 /// 0x53 Watchdog timer +#define EADC_VECTOR 11 /// 0x5B ADC +#define ECAP_VECTOR 12 /// 0x63 Input Capture +#define EPWM_VECTOR 13 /// 0x6B PWM +#define EFB_VECTOR 14 /// 0x73 Fault Brake Event +#define ES1_VECTOR 15 /// 0x7B Serial Port 1 +#define ET3_VECTOR 16 /// 0x83 Timer 3 +#define EWKT_VECTOR 17 /// 0x8B Self Wake-up Timer + +#endif \ No newline at end of file diff --git a/examples/anymcu-blink/src/STC12C20xx.h b/examples/anymcu-blink/src/STC12C20xx.h new file mode 100644 index 0000000..d7ef855 --- /dev/null +++ b/examples/anymcu-blink/src/STC12C20xx.h @@ -0,0 +1,340 @@ +#ifndef STC12C20xx_H +#define STC12C20xx_H + +#include + +// 适用于 STC12C20xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR or change */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +/* Watchdog Timer Register */ +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +/* ISP_IAP_EEPROM Register */ +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* IDLE, Clock Divider */ +#define _IDLE_CLK 0xc7 +SFR(IDLE_CLK, 0xc7); +#define _WAKE_CLKO 0x8F +SFR(WAKE_CLKO, 0x8F); + +/* I_O Port Mode Set Register */ +#define _P0M0 0x93 +SFR(P0M0, 0x93); +#define _P0M1 0x94 +SFR(P0M1, 0x94); +#define _P1M0 0x91 +SFR(P1M0, 0x91); +#define _P1M1 0x92 +SFR(P1M1, 0x92); +#define _P2M0 0x95 +SFR(P2M0, 0x95); +#define _P2M1 0x96 +SFR(P2M1, 0x96); +#define _P3M0 0xb1 +SFR(P3M0, 0xb1); +#define _P3M1 0xb2 +SFR(P3M1, 0xb2); + +/* SPI Register */ +#define _SPSTAT 0x84 +SFR(SPSTAT, 0x84); +#define _SPCTL 0x85 +SFR(SPCTL, 0x85); +#define _SPDAT 0x86 +SFR(SPDAT, 0x86); + +/* ADC Register */ +#define _ADC_CONTR 0xc5 +SFR(ADC_CONTR, 0xc5); +#define _ADC_DATA 0xc6 +SFR(ADC_DATA, 0xc6); +#define _ADC_LOW2 0xbe +SFR(ADC_LOW2, 0xbe); + +/* PCA SFR */ +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CCAPM5 0xDF +SFR(CCAPM5, 0xDF); + +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CCAP5L 0xEF +SFR(CCAP5L, 0xEF); + +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +#define _CCAP5H 0xFF +SFR(CCAP5H, 0xFF); + +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); +#define _PCA_PWM3 0xF5 +SFR(PCA_PWM3, 0xF5); +#define _PCA_PWM4 0xF6 +SFR(PCA_PWM4, 0xF6); +#define _PCA_PWM5 0xF7 +SFR(PCA_PWM5, 0xF7); + +/* CCON */ +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF5, _CCON, 5); +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); + +/* Above is STC additional SFR or change */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +//#define _AUXR1 0xA2 +//SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* PCA Pin */ +SBIT(CEX3, _P2, 4); +SBIT(CEX2, _P2, 0); +SBIT(CEX1, _P3, 5); +SBIT(CEX0, _P3, 7); +SBIT(ECI, _P3, 4); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EPCA_LVD, _IE, 6); +SBIT(EADC_SPI, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +SBIT(PPCA_LVD, _IP, 6); +SBIT(PADC_SPI, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +#endif diff --git a/examples/anymcu-blink/src/STC12C54xx.h b/examples/anymcu-blink/src/STC12C54xx.h new file mode 100644 index 0000000..7a1d7c5 --- /dev/null +++ b/examples/anymcu-blink/src/STC12C54xx.h @@ -0,0 +1,340 @@ +#ifndef STC12C54xx_H +#define STC12C54xx_H + +#include + +// 适用于 STC12C54xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR or change */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +/* Watchdog Timer Register */ +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +/* ISP_IAP_EEPROM Register */ +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* System Clock Divider */ +#define _CLK_DIV 0xc7 +SFR(CLK_DIV, 0xc7); + +/* I_O Port Mode Set Register */ +#define _P0M0 0x93 +SFR(P0M0, 0x93); +#define _P0M1 0x94 +SFR(P0M1, 0x94); +#define _P1M0 0x91 +SFR(P1M0, 0x91); +#define _P1M1 0x92 +SFR(P1M1, 0x92); +#define _P2M0 0x95 +SFR(P2M0, 0x95); +#define _P2M1 0x96 +SFR(P2M1, 0x96); +#define _P3M0 0xb1 +SFR(P3M0, 0xb1); +#define _P3M1 0xb2 +SFR(P3M1, 0xb2); + +/* SPI Register */ +#define _SPSTAT 0x84 +SFR(SPSTAT, 0x84); +#define _SPCTL 0x85 +SFR(SPCTL, 0x85); +#define _SPDAT 0x86 +SFR(SPDAT, 0x86); + +/* ADC Register */ +#define _ADC_CONTR 0xc5 +SFR(ADC_CONTR, 0xc5); +#define _ADC_DATA 0xc6 +SFR(ADC_DATA, 0xc6); +#define _ADC_LOW2 0xbe +SFR(ADC_LOW2, 0xbe); + +/* PCA SFR */ +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CCAPM5 0xDF +SFR(CCAPM5, 0xDF); + +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CCAP5L 0xEF +SFR(CCAP5L, 0xEF); + +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +#define _CCAP5H 0xFF +SFR(CCAP5H, 0xFF); + +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); +#define _PCA_PWM3 0xF5 +SFR(PCA_PWM3, 0xF5); +#define _PCA_PWM4 0xF6 +SFR(PCA_PWM4, 0xF6); +#define _PCA_PWM5 0xF7 +SFR(PCA_PWM5, 0xF7); + +/* CCON */ +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF5, _CCON, 5); +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); + + +/* Above is STC additional SFR or change */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x99 +SFR(SCON, 0x99); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +//#define _AUXR1 0xA2 +//SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* PCA Pin */ + +SBIT(CEX3, _P2, 4); +SBIT(CEX2, _P2, 0); +SBIT(CEX1, _P3, 5); +SBIT(CEX0, _P3, 7); +SBIT(ECI, _P3, 4); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EPCA_LVD, _IE, 6); +SBIT(EADC_SPI, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +SBIT(PPCA_LVD, _IP, 6); +SBIT(PADC_SPI, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +#endif diff --git a/examples/anymcu-blink/src/STC12C56xx.h b/examples/anymcu-blink/src/STC12C56xx.h new file mode 100644 index 0000000..70ab5b6 --- /dev/null +++ b/examples/anymcu-blink/src/STC12C56xx.h @@ -0,0 +1,339 @@ +#ifndef STC12C56xx_H +#define STC12C56xx_H + +#include + +// 适用于 STC12C56xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR or change */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +/* Watchdog Timer Register */ +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +/* ISP_IAP_EEPROM Register */ +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* System Clock Divider */ +#define _CLK_DIV 0xc7 +SFR(CLK_DIV, 0xc7); + +/* I_O Port Mode Set Register */ +#define _P0M0 0x93 +SFR(P0M0, 0x93); +#define _P0M1 0x94 +SFR(P0M1, 0x94); +#define _P1M0 0x91 +SFR(P1M0, 0x91); +#define _P1M1 0x92 +SFR(P1M1, 0x92); +#define _P2M0 0x95 +SFR(P2M0, 0x95); +#define _P2M1 0x96 +SFR(P2M1, 0x96); +#define _P3M0 0xb1 +SFR(P3M0, 0xb1); +#define _P3M1 0xb2 +SFR(P3M1, 0xb2); + +/* SPI Register */ +#define _SPSTAT 0x84 +SFR(SPSTAT, 0x84); +#define _SPCTL 0x85 +SFR(SPCTL, 0x85); +#define _SPDAT 0x86 +SFR(SPDAT, 0x86); + +/* ADC Register */ +#define _ADC_CONTR 0xc5 +SFR(ADC_CONTR, 0xc5); +#define _ADC_DATA 0xc6 +SFR(ADC_DATA, 0xc6); +#define _ADC_LOW2 0xbe +SFR(ADC_LOW2, 0xbe); + +/* PCA SFR */ +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CCAPM5 0xDF +SFR(CCAPM5, 0xDF); + +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CCAP5L 0xEF +SFR(CCAP5L, 0xEF); + +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +#define _CCAP5H 0xFF +SFR(CCAP5H, 0xFF); + +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); +#define _PCA_PWM3 0xF5 +SFR(PCA_PWM3, 0xF5); +#define _PCA_PWM4 0xF6 +SFR(PCA_PWM4, 0xF6); +#define _PCA_PWM5 0xF7 +SFR(PCA_PWM5, 0xF7); + +/* CCON */ +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF5, _CCON, 5); +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); + + +/* Above is STC additional SFR or change */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +//#define _AUXR1 0xA2 +//SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* PCA Pin */ +SBIT(CEX3, _P2, 4); +SBIT(CEX2, _P2, 0); +SBIT(CEX1, _P3, 5); +SBIT(CEX0, _P3, 7); +SBIT(ECI, _P3, 4); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EPCA_LVD, _IE, 6); +SBIT(EADC_SPI, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +SBIT(PPCA_LVD, _IP, 6); +SBIT(PADC_SPI, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +#endif diff --git a/examples/anymcu-blink/src/STC12C5Axx.h b/examples/anymcu-blink/src/STC12C5Axx.h new file mode 100644 index 0000000..851ae5b --- /dev/null +++ b/examples/anymcu-blink/src/STC12C5Axx.h @@ -0,0 +1,420 @@ +#ifndef STC12C5Axx_H +#define STC12C5Axx_H + +#include + +// 适用于 STC10Fxx / STC11Fxx / STC12C5Axx / STC12C52xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + + //新一代 1T 8051系列 单片机内核特殊功能寄存器 C51 Core SFRs + // 7 6 5 4 3 2 1 0 Reset Value +#define _ACC 0xE0 +SFR(ACC, 0xE0); //Accumulator 0000,0000 +#define _B 0xF0 +SFR(B, 0xF0); //B Register 0000,0000 +#define _PSW 0xD0 +SFR(CCAP0H, 0xFA); //PCA 模块 0 的捕捉/比较寄存器高 8 位。 0000,0000 +SFR(PSW, 0xD0); //Program Status Word CY AC F0 RS1 RS0 OV F1 P 0000,0000 + +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +#define _SP 0x81 +SFR(SP, 0x81); //Stack Pointer 0000,0111 +#define _DPL 0x82 +SFR(DPL, 0x82); //Data Pointer Low Byte 0000,0000 +#define _DPH 0x83 +SFR(DPH, 0x83); //Data Pointer High Byte 0000,0000 + + //新一代 1T 8051系列 单片机系统管理特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _PCON 0x87 +SFR(PCON, 0x87); //Power Control SMOD SMOD0 LVDF POF GF1 GF0 PD IDL 0001,0000 + // 7 6 5 4 3 2 1 0 Reset Value +#define _AUXR 0x8E +SFR(AUXR, 0x8E); //Auxiliary Register T0x12 T1x12 UART_M0x6 BRTR S2SMOD BRTx12 EXTRAM S1BRS 0000,0000 + +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); //Auxiliary Register 1 - PCA_P4 SPI_P4 S2_P4 GF2 ADRJ - DPS 0000,0000 +/* +PCA_P4: + 0, 缺省PCA 在P1 口 + 1，PCA/PWM 从P1 口切换到P4 口: ECI 从P1.2 切换到P4.1 口， + PCA0/PWM0 从P1.3 切换到P4.2 口 + PCA1/PWM1 从P1.4 切换到P4.3 口 +SPI_P4: + 0, 缺省SPI 在P1 口 + 1，SPI 从P1 口切换到P4 口: SPICLK 从P1.7 切换到P4.3 口 + MISO 从P1.6 切换到P4.2 口 + MOSI 从P1.5 切换到P4.1 口 + SS 从P1.4 切换到P4.0 口 +S2_P4: + 0, 缺省UART2 在P1 口 + 1，UART2 从P1 口切换到P4 口: TxD2 从P1.3 切换到P4.3 口 + RxD2 从P1.2 切换到P4.2 口 +GF2: 通用标志位 + +ADRJ: + 0, 10 位A/D 转换结果的高8 位放在ADC_RES 寄存器, 低2 位放在ADC_RESL 寄存器 + 1，10 位A/D 转换结果的最高2 位放在ADC_RES 寄存器的低2 位, 低8 位放在ADC_RESL 寄存器 + +DPS: 0, 使用缺省数据指针DPTR0 + 1，使用另一个数据指针DPTR1 +*/ + +#define _WAKE_CLKO 0x8F +SFR(WAKE_CLKO, 0x8F); //附加的 SFR WAK1_CLKO +/* + 7 6 5 4 3 2 1 0 Reset Value + PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE LVD_WAKE _ T1CLKO T0CLKO 0000,0000B + +b7 - PCAWAKEUP : PCA 中断可唤醒 powerdown。 +b6 - RXD_PIN_IE : 当 P3.0(RXD) 下降沿置位 RI 时可唤醒 powerdown(必须打开相应中断)。 +b5 - T1_PIN_IE : 当 T1 脚下降沿置位 T1 中断标志时可唤醒 powerdown(必须打开相应中断)。 +b4 - T0_PIN_IE : 当 T0 脚下降沿置位 T0 中断标志时可唤醒 powerdown(必须打开相应中断)。 +b3 - LVD_WAKE : 当 CMPIN 脚低电平置位 LVD 中断标志时可唤醒 powerdown(必须打开相应中断)。 +b2 - +b1 - T1CLKO : 允许 T1CKO(P3.5) 脚输出 T1 溢出脉冲，Fck1, 1/2 T1 溢出率 +b0 - T0CLKO : 允许 T0CKO(P3.4) 脚输出 T0 溢出脉冲，Fck0, 1/2 T1 溢出率 +*/ + +#define _CLK_DIV 0x97 +SFR(CLK_DIV, 0x97); //Clock Divder - - - - - CLKS2 CLKS1 CLKS0 xxxx,x000 + +#define _BUS_SPEED 0xA1 +SFR(BUS_SPEED, 0xA1); //Stretch register - - ALES1 ALES0 - RWS2 RWS1 RWS0 xx10,x011 +/* +ALES1 and ALES0: +00 : The P0 address setup time and hold time to ALE negative edge is one clock cycle +01 : The P0 address setup time and hold time to ALE negative edge is two clock cycles. +10 : The P0 address setup time and hold time to ALE negative edge is three clock cycles. (default) +11 : The P0 address setup time and hold time to ALE negative edge is four clock cycles. + +RWS2,RWS1,RWS0: + 000 : The MOVX read/write pulse is 1 clock cycle. + 001 : The MOVX read/write pulse is 2 clock cycles. + 010 : The MOVX read/write pulse is 3 clock cycles. + 011 : The MOVX read/write pulse is 4 clock cycles. (default) + 100 : The MOVX read/write pulse is 5 clock cycles. + 101 : The MOVX read/write pulse is 6 clock cycles. + 110 : The MOVX read/write pulse is 7 clock cycles. + 111 : The MOVX read/write pulse is 8 clock cycles. +*/ + + //新一代 1T 8051系列 单片机中断特殊功能寄存器 + //有的中断控制、中断标志位散布在其它特殊功能寄存器中，这些位在位地址中定义 + //其中有的位无位寻址能力，请参阅 新一代 1T 8051系列 单片机中文指南 + // 7 6 5 4 3 2 1 0 Reset Value +#define _IE 0xA8 +SFR(IE, 0xA8); //中断控制寄存器 EA ELVD EADC ES ET1 EX1 ET0 EX0 0x00,0000 + +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); //低压监测中断允许位 +SBIT(EADC, _IE, 5); //ADC 中断允许位 +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +#define _IE2 0xAF +SFR(IE2, 0xAF); //Auxiliary Interrupt - - - - - - ESPI ES2 0000,0000B + + // 7 6 5 4 3 2 1 0 Reset Value +#define _IP 0xB8 +SFR(IP, 0xB8); //中断优先级低位 PPCA PLVD PADC PS PT1 PX1 PT0 PX0 0000,0000 + +SBIT(PPCA, _IP, 7); //PCA 模块中断优先级 +SBIT(PLVD, _IP, 6); //低压监测中断优先级 +SBIT(PADC, _IP, 5); //ADC 中断优先级 +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + + // 7 6 5 4 3 2 1 0 Reset Value +#define _IPH 0xB7 +SFR(IPH, 0xB7); //中断优先级高位 PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H 0000,0000 +#define _IP2 0xB5 +SFR(IP2, 0xB5); // - - - - - - PSPI PS2 xxxx,xx00 +#define _IPH2 0xB6 +SFR(IPH2, 0xB6); // - - - - - - PSPIH PS2H xxxx,xx00 + + //新一代 1T 8051系列 单片机I/O 口特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _P0 0x80 +SFR(P0, 0x80); //8 bitPort0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 1111,1111 +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P0M0 0x94 +SFR(P0M0, 0x94); // 0000,0000 +#define _P0M1 0x93 +SFR(P0M1, 0x93); // 0000,0000 +#define _P1 0x90 +SFR(P1, 0x90); //8 bitPort1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 1111,1111 +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P1M0 0x92 +SFR(P1M0, 0x92); // 0000,0000 +#define _P1M1 0x91 +SFR(P1M1, 0x91); // 0000,0000 +#define _P1ASF 0x9D +SFR(P1ASF, 0x9D); //P1 analog special function +#define _P2 0xA0 +SFR(P2, 0xA0); //8 bitPort2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 1111,1111 +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P2M0 0x96 +SFR(P2M0, 0x96); // 0000,0000 +#define _P2M1 0x95 +SFR(P2M1, 0x95); // 0000,0000 +#define _P3 0xB0 +SFR(P3, 0xB0); //8 bitPort3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 1111,1111 +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _P3M0 0xB2 +SFR(P3M0, 0xB2); // 0000,0000 +#define _P3M1 0xB1 +SFR(P3M1, 0xB1); // 0000,0000 +#define _P4 0xC0 +SFR(P4, 0xC0); //8 bitPort4 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 1111,1111 +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +#define _P4M0 0xB4 +SFR(P4M0, 0xB4); // 0000,0000 +#define _P4M1 0xB3 +SFR(P4M1, 0xB3); // 0000,0000 + // 7 6 5 4 3 2 1 0 Reset Value +#define _P4SW 0xBB +SFR(P4SW, 0xBB); //Port-4 switch - LVD_P4.6 ALE_P4.5 NA_P4.4 - - - - x000,xxxx + +#define _P5 0xC8 +SFR(P5, 0xC8); //8 bitPort5 - - - - P5.3 P5.2 P5.1 P5.0 xxxx,1111 +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +#define _P5M0 0xCA +SFR(P5M0, 0xCA); // 0000,0000 +#define _P5M1 0xC9 +SFR(P5M1, 0xC9); // 0000,0000 + + //新一代 1T 8051系列 单片机定时器特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _TCON 0x88 +SFR(TCON, 0x88); //T0/T1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0000,0000 + +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +#define _TMOD 0x89 +SFR(TMOD, 0x89); //T0/T1 Modes GATE1 C/T1 M1_1 M1_0 GATE0 C/T0 M0_1 M0_0 0000,0000 +#define _TL0 0x8A +SFR(TL0, 0x8A); //T0 Low Byte 0000,0000 +#define _TH0 0x8C +SFR(TH0, 0x8C); //T0 High Byte 0000,0000 +#define _TL1 0x8B +SFR(TL1, 0x8B); //T1 Low Byte 0000,0000 +#define _TH1 0x8D +SFR(TH1, 0x8D); //T1 High Byte 0000,0000 + + //新一代 1T 8051系列 单片机串行口特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _SCON 0x98 +SFR(SCON, 0x98); //Serial Control SM0/FE SM1 SM2 REN TB8 RB8 TI RI 0000,0000 + +SBIT(SM0, _SCON, 7); //SM0/FE +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +#define _SBUF 0x99 +SFR(SBUF, 0x99); //Serial Data Buffer xxxx,xxxx +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); //Slave Address Mask 0000,0000 +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); //Slave Address 0000,0000 + + // 7 6 5 4 3 2 1 0 Reset Value +#define _S2CON 0x9A +SFR(S2CON, 0x9A); //S2 Control S2SM0 S2SM1 S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B +#define _S2BUF 0x9B +SFR(S2BUF, 0x9B); //S2 Serial Buffer xxxx,xxxx +#define _BRT 0x9C +SFR(BRT, 0x9C); //S2 Baud-Rate Timer 0000,0000 + + //新一代 1T 8051系列 单片机看门狗定时器特殊功能寄存器 +#define _WDT_CONTR 0xC1 +SFR(WDT_CONTR, 0xC1); //Watch-Dog-Timer Control register + // 7 6 5 4 3 2 1 0 Reset Value + // WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0 xx00,0000 + + //新一代 1T 8051系列 单片机PCA/PWM 特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _CCON 0xD8 +SFR(CCON, 0xD8); //PCA 控制寄存器。 CF CR - - - - CCF1 CCF0 00xx,xx00 + +SBIT(CF, _CCON, 7); //PCA计数器溢出标志,由硬件或软件置位,必须由软件清0。 +SBIT(CR, _CCON, 6); //1:允许 PCA 计数器计数, 必须由软件清0。 + +SBIT(CCF1, _CCON, 1); //PCA 模块1 中断标志, 由硬件置位, 必须由软件清0。 +SBIT(CCF0, _CCON, 0); //PCA 模块0 中断标志, 由硬件置位, 必须由软件清0。 + +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); //PCA 工作模式寄存器。 CIDL - - - CPS2 CPS1 CPS0 ECF 0xxx,x000 +/* +CIDL: idle 状态时 PCA 计数器是否继续计数, 0: 继续计数, 1: 停止计数。 + +CPS2: PCA 计数器脉冲源选择位 2。 +CPS1: PCA 计数器脉冲源选择位 1。 +CPS0: PCA 计数器脉冲源选择位 0。 + CPS2 CPS1 CPS0 + 0 0 0 系统时钟频率 fosc/12。 + 0 0 1 系统时钟频率 fosc/2。 + 0 1 0 Timer0 溢出。 + 0 1 1 由 ECI/P3.4 脚输入的外部时钟，最大 fosc/2。 + 1 0 0 系统时钟频率， Fosc/1 + 1 0 1 系统时钟频率/4，Fosc/4 + 1 1 0 系统时钟频率/6，Fosc/6 + 1 1 1 系统时钟频率/8，Fosc/8 + +ECF: PCA计数器溢出中断允许位, 1--允许 CF(CCON.7) 产生中断。 +*/ + +#define _CL 0xE9 +SFR(CL, 0xE9); //PCA 计数器低位 0000,0000 +#define _CH 0xF9 +SFR(CH, 0xF9); //PCA 计数器高位 0000,0000 + + // 7 6 5 4 3 2 1 0 Reset Value +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); //PCA 模块0 PWM 寄存器 - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x000,0000 +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); //PCA 模块1 PWM 寄存器 - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x000,0000 + +//ECOMn, 1:允许比较功能。 +//CAPPn, 1:允许上升沿触发捕捉功能。 +//CAPNn, 1:允许下降沿触发捕捉功能。 +//MATn, 1:当匹配情况发生时, 允许 CCON 中的 CCFn 置位。 +//TOGn, 1:当匹配情况发生时, CEXn 将翻转。 +//PWMn, 1:将 CEXn 设置为 PWM 输出。 +//ECCFn, 1:允许 CCON 中的 CCFn 触发中断。 + +//ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn +// 0 0 0 0 0 0 0 0x00 未启用任何功能。 +// x 1 0 0 0 0 x 0x21 16位CEXn上升沿触发捕捉功能。 +// x 0 1 0 0 0 x 0x11 16位CEXn下降沿触发捕捉功能。 +// x 1 1 0 0 0 x 0x31 16位CEXn边沿(上、下沿)触发捕捉功能。 +// 1 0 0 1 0 0 x 0x49 16位软件定时器。 +// 1 0 0 1 1 0 x 0x4d 16位高速脉冲输出。 +// 1 0 0 0 0 1 0 0x42 8位 PWM。 + +//ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn +// 0 0 0 0 0 0 0 0x00 无此操作 +// 1 0 0 0 0 1 0 0x42 普通8位PWM, 无中断 +// 1 1 0 0 0 1 1 0x63 PWM输出由低变高可产生中断 +// 1 0 1 0 0 1 1 0x53 PWM输出由高变低可产生中断 +// 1 1 1 0 0 1 1 0x73 PWM输出由低变高或由高变低都可产生中断 + + +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); //PCA 模块 0 的捕捉/比较寄存器低 8 位。 0000,0000 +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); //PCA 模块 0 的捕捉/比较寄存器高 8 位。 0000,0000 +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); //PCA 模块 1 的捕捉/比较寄存器低 8 位。 0000,0000 +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); //PCA 模块 1 的捕捉/比较寄存器高 8 位。 0000,0000 + + // 7 6 5 4 3 2 1 0 Reset Value +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); //PCA 模块0 PWM 寄存器。- - - - - - EPC0H EPC0L xxxx,xx00 +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); //PCA 模块1 PWM 寄存器。- - - - - - EPC1H EPC1L xxxx,xx00 + //PCA_PWMn: 7 6 5 4 3 2 1 0 + // - - - - - - EPCnH EPCnL + //B7-B2: 保留 + //B1(EPCnH): 在 PWM 模式下，与 CCAPnH 组成 9 位数。 + //B0(EPCnL): 在 PWM 模式下，与 CCAPnL 组成 9 位数。 + + //新一代 1T 8051系列 单片机 ADC 特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _ADC_CONTR 0xBC +SFR(ADC_CONTR, 0xBC); //A/D 转换控制寄存器 ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000,0000 +#define _ADC_RES 0xBD +SFR(ADC_RES, 0xBD); //A/D 转换结果高8位 ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 0000,0000 +#define _ADC_RESL 0xBE +SFR(ADC_RESL, 0xBE); //A/D 转换结果低2位 - - - - - - ADCV.1 ADCV.0 0000,0000 + + //新一代 1T 8051系列 单片机 SPI 特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _SPCTL 0xCE +SFR(SPCTL, 0xCE); //SPI Control Register SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 0000,0100 +#define _SPSTAT 0xCD +SFR(SPSTAT, 0xCD); //SPI Status Register SPIF WCOL - - - - - - 00xx,xxxx +#define _SPDAT 0xCF +SFR(SPDAT, 0xCF); //SPI Data Register 0000,0000 + + //新一代 1T 8051系列 单片机 IAP/ISP 特殊功能寄存器 +#define _IAP_DATA 0xC2 +SFR(IAP_DATA, 0xC2); +#define _IAP_ADDRH 0xC3 +SFR(IAP_ADDRH, 0xC3); +#define _IAP_ADDRL 0xC4 +SFR(IAP_ADDRL, 0xC4); + // 7 6 5 4 3 2 1 0 Reset Value +#define _IAP_CMD 0xC5 +SFR(IAP_CMD, 0xC5); //IAP Mode Table 0 - - - - - MS1 MS0 0xxx,xx00 +#define _IAP_TRIG 0xC6 +SFR(IAP_TRIG, 0xC6); +#define _IAP_CONTR 0xC7 +SFR(IAP_CONTR, 0xC7); //IAP Control Register IAPEN SWBS SWRST CFAIL - WT2 WT1 WT0 0000,x000 + +#endif + diff --git a/examples/anymcu-blink/src/STC15.h b/examples/anymcu-blink/src/STC15.h new file mode 100644 index 0000000..a929917 --- /dev/null +++ b/examples/anymcu-blink/src/STC15.h @@ -0,0 +1,406 @@ +#ifndef STC15_H +#define STC15_H +#include + +// Suitable for use with most STC15x series MCU. +// This header file was verified against the official STC ISP Tool. +// After this file is included you don't have to include "REG51.H" + +// Special Function Register //Reset Value Description +#define _ACC 0xE0 +SFR(ACC, 0xE0); //0000,0000 Accumulator +#define _B 0xF0 +SFR(B, 0xF0); //0000,0000 B Register +#define _PSW 0xD0 +SFR(PSW, 0xD0); //0000,0000 Program status word +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(F1, _PSW, 1); +SBIT(P, _PSW, 0); +#define _SP 0x81 +SFR(SP, 0x81); //0000,0111 Stack Pointer +#define _DPL 0x82 +SFR(DPL, 0x82); //0000,0000 Data Pointer Low Byte +#define _DPH 0x83 +SFR(DPH, 0x83); //0000,0000 Data Pointer High Byte + +// I/O Port Special Function Register +#define _P0 0x80 +SFR(P0, 0x80); //1111,1111 Port 0 +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +SBIT(P0_0, _P0, 0); +SBIT(P0_1, _P0, 1); +SBIT(P0_2, _P0, 2); +SBIT(P0_3, _P0, 3); +SBIT(P0_4, _P0, 4); +SBIT(P0_5, _P0, 5); +SBIT(P0_6, _P0, 6); +SBIT(P0_7, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); //1111,1111 Port 1 +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +SBIT(P1_0, _P1, 0); +SBIT(P1_1, _P1, 1); +SBIT(P1_2, _P1, 2); +SBIT(P1_3, _P1, 3); +SBIT(P1_4, _P1, 4); +SBIT(P1_5, _P1, 5); +SBIT(P1_6, _P1, 6); +SBIT(P1_7, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); //1111,1111 Port 2 +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +SBIT(P2_0, _P2, 0); +SBIT(P2_1, _P2, 1); +SBIT(P2_2, _P2, 2); +SBIT(P2_3, _P2, 3); +SBIT(P2_4, _P2, 4); +SBIT(P2_5, _P2, 5); +SBIT(P2_6, _P2, 6); +SBIT(P2_7, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); //1111,1111 Port 3 +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +SBIT(P3_0, _P3, 0); +SBIT(P3_1, _P3, 1); +SBIT(P3_2, _P3, 2); +SBIT(P3_3, _P3, 3); +SBIT(P3_4, _P3, 4); +SBIT(P3_5, _P3, 5); +SBIT(P3_6, _P3, 6); +SBIT(P3_7, _P3, 7); +#define _P4 0xC0 +SFR(P4, 0xC0); //1111,1111 Port 4 +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +SBIT(P4_0, _P4, 0); +SBIT(P4_1, _P4, 1); +SBIT(P4_2, _P4, 2); +SBIT(P4_3, _P4, 3); +SBIT(P4_4, _P4, 4); +SBIT(P4_5, _P4, 5); +SBIT(P4_6, _P4, 6); +SBIT(P4_7, _P4, 7); +#define _P5 0xC8 +SFR(P5, 0xC8); //xxxx,1111 Port 5 +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +SBIT(P54, _P5, 4); +SBIT(P55, _P5, 5); +SBIT(P56, _P5, 6); +SBIT(P57, _P5, 7); +SBIT(P5_0, _P5, 0); +SBIT(P5_1, _P5, 1); +SBIT(P5_2, _P5, 2); +SBIT(P5_3, _P5, 3); +SBIT(P5_4, _P5, 4); +SBIT(P5_5, _P5, 5); +SBIT(P5_6, _P5, 6); +SBIT(P5_7, _P5, 7); +#define _P6 0xE8 +SFR(P6, 0xE8); //0000,0000 Port 6 +SBIT(P60, _P6, 0); +SBIT(P61, _P6, 1); +SBIT(P62, _P6, 2); +SBIT(P63, _P6, 3); +SBIT(P64, _P6, 4); +SBIT(P65, _P6, 5); +SBIT(P66, _P6, 6); +SBIT(P67, _P6, 7); +SBIT(P6_0, _P6, 0); +SBIT(P6_1, _P6, 1); +SBIT(P6_2, _P6, 2); +SBIT(P6_3, _P6, 3); +SBIT(P6_4, _P6, 4); +SBIT(P6_5, _P6, 5); +SBIT(P6_6, _P6, 6); +SBIT(P6_7, _P6, 7); +#define _P7 0xF8 +SFR(P7, 0xF8); //0000,0000 Port 7 +SBIT(P70, _P7, 0); +SBIT(P71, _P7, 1); +SBIT(P72, _P7, 2); +SBIT(P73, _P7, 3); +SBIT(P74, _P7, 4); +SBIT(P75, _P7, 5); +SBIT(P76, _P7, 6); +SBIT(P77, _P7, 7); +SBIT(P70, _P7, 0); +SBIT(P7_1, _P7, 1); +SBIT(P7_2, _P7, 2); +SBIT(P7_3, _P7, 3); +SBIT(P7_4, _P7, 4); +SBIT(P7_5, _P7, 5); +SBIT(P7_6, _P7, 6); +SBIT(P7_7, _P7, 7); +#define _P0M0 0x94 +SFR(P0M0, 0x94); //0000,0000 Port 0 Mode Register 0 +#define _P0M1 0x93 +SFR(P0M1, 0x93); //0000,0000 Port 0 Mode Register 1 +#define _P1M0 0x92 +SFR(P1M0, 0x92); //0000,0000 Port 1 Mode Register 0 +#define _P1M1 0x91 +SFR(P1M1, 0x91); //0000,0000 Port 1 Mode Register 1 +#define _P2M0 0x96 +SFR(P2M0, 0x96); //0000,0000 Port 2 Mode Register 0 +#define _P2M1 0x95 +SFR(P2M1, 0x95); //0000,0000 Port 2 Mode Register 1 +#define _P3M0 0xB2 +SFR(P3M0, 0xB2); //0000,0000 Port 3 Mode Register 0 +#define _P3M1 0xB1 +SFR(P3M1, 0xB1); //0000,0000 Port 3 Mode Register 1 +#define _P4M0 0xB4 +SFR(P4M0, 0xB4); //0000,0000 Port 4 Mode Register 0 +#define _P4M1 0xB3 +SFR(P4M1, 0xB3); //0000,0000 Port 4 Mode Register 1 +#define _P5M0 0xCA +SFR(P5M0, 0xCA); //0000,0000 Port 5 Mode Register 0 +#define _P5M1 0xC9 +SFR(P5M1, 0xC9); //0000,0000 Port 5 Mode Register 1 +#define _P6M0 0xCC +SFR(P6M0, 0xCC); //0000,0000 Port 6 Mode Register 0 +#define _P6M1 0xCB +SFR(P6M1, 0xCB); //0000,0000 Port 6 Mode Register 1 +#define _P7M0 0xE2 +SFR(P7M0, 0xE2); //0000,0000 Port 7 Mode Register 0 +#define _P7M1 0xE1 +SFR(P7M1, 0xE1); //0000,0000 Port 7 Mode Register 1 + +// System management special function register +#define _PCON 0x87 +SFR(PCON, 0x87); //0001,0000 Power Control Register +#define _AUXR 0x8E +SFR(AUXR, 0x8E); //0000,0000 Auxiliary Register +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); //0000,0000 Auxiliary Register 1 +#define _P_SW1 0xA2 +SFR(P_SW1, 0xA2); //0000,0000 Peripheral Port Switching Register 1 +#define _CLK_DIV 0x97 +SFR(CLK_DIV, 0x97); //xxxx,x000 Clock Division Control Register +#define _BUS_SPEED 0xA1 +SFR(BUS_SPEED, 0xA1); //xx10,x011 Bus Speed Control Register +#define _P1ASF 0x9D +SFR(P1ASF, 0x9D); //0000,0000 Port 1 Analog Function Configuration Register +#define _P_SW2 0xBA +SFR(P_SW2, 0xBA); //0xxx,x000 Peripheral Port Switching Register +#define _IRC_CLKO 0xBB +SFR(IRC_CLKO, 0xBB); //0000,0000 Internal Oscillator Clock Output Control Register + +// Interrupt special function register +#define _IE 0xA8 +SFR(IE, 0xA8); //0000,0000 Interrupt Control Register +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); +SBIT(EADC, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); +#define _IP 0xB8 +SFR(IP, 0xB8); //0000,0000 Interrupt Priority Register +SBIT(PPCA, _IP, 7); +SBIT(PLVD, _IP, 6); +SBIT(PADC, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); +#define _IE2 0xAF +SFR(IE2, 0xAF); //0000,0000 Interrupt Control Register 2 +#define _IP2 0xB5 +SFR(IP2, 0xB5); //xxxx,xx00 Interrupt Priority Register 2 +#define _INT_CLKO 0x8F +SFR(INT_CLKO, 0x8F); //0000,0000 External Interrupt and Clock Output Control Register + +// Timer Special Function Register +#define _TCON 0x88 +SFR(TCON, 0x88); //0000,0000 T0/T1 Control Register +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); +#define _TMOD 0x89 +SFR(TMOD, 0x89); //0000,0000 T0/T1 Mode Register +#define _TL0 0x8A +SFR(TL0, 0x8A); //0000,0000 T0 Low Byte +#define _TL1 0x8B +SFR(TL1, 0x8B); //0000,0000 T1 Low Byte +#define _TH0 0x8C +SFR(TH0, 0x8C); //0000,0000 T0 High Byte +#define _TH1 0x8D +SFR(TH1, 0x8D); //0000,0000 T1 High Byte +#define _T4T3M 0xD1 +SFR(T4T3M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T3T4M 0xD1 +SFR(T3T4M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T4H 0xD2 +SFR(T4H, 0xD2); //0000,0000 T4 High Byte +#define _T4L 0xD3 +SFR(T4L, 0xD3); //0000,0000 T4 Low Byte +#define _T3H 0xD4 +SFR(T3H, 0xD4); //0000,0000 T3 High Byte +#define _T3L 0xD5 +SFR(T3L, 0xD5); //0000,0000 T3 Low Byte +#define _T2H 0xD6 +SFR(T2H, 0xD6); //0000,0000 T2 High Byte +#define _T2L 0xD7 +SFR(T2L, 0xD7); //0000,0000 T2 Low Byte +#define _WKTCL 0xAA +SFR(WKTCL, 0xAA); //0000,0000 Power Down Wakeup Timer Low Byte +#define _WKTCH 0xAB +SFR(WKTCH, 0xAB); //0000,0000 Power Down Wakeup Timer High Byte +#define _WDT_CONTR 0xC1 +SFR(WDT_CONTR, 0xC1); //0000,0000 Watchdog Control Register + +// Serial port special function register +#define _SCON 0x98 +SFR(SCON, 0x98); //0000,0000 Serial Port 1 Control Register +SBIT(SM0, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); +#define _SBUF 0x99 +SFR(SBUF, 0x99); //xxxx,xxxx Serial Port 1 Data Register +#define _S2CON 0x9A +SFR(S2CON, 0x9A); //0000,0000 Serial Port 2 Control Register +#define _S2BUF 0x9B +SFR(S2BUF, 0x9B); //xxxx,xxxx Serial Port 2 Data Register +#define _S3CON 0xAC +SFR(S3CON, 0xAC); //0000,0000 Serial Port 3 Control Register +#define _S3BUF 0xAD +SFR(S3BUF, 0xAD); //xxxx,xxxx Serial Port 3 Data Register +#define _S4CON 0x84 +SFR(S4CON, 0x84); //0000,0000 Serial Port 4 Control Register +#define _S4BUF 0x85 +SFR(S4BUF, 0x85); //xxxx,xxxx Serial Port 4 Data Register +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); //0000,0000 Slave Address Register +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); //0000,0000 Slave Address Mask Register + +// ADC Special Function Register +#define _ADC_CONTR 0xBC +SFR(ADC_CONTR, 0xBC); //0000,0000 A/D Conversion Control Register +#define _ADC_RES 0xBD +SFR(ADC_RES, 0xBD); //0000,0000 A/D Conversion Result High 8 Bits +#define _ADC_RESL 0xBE +SFR(ADC_RESL, 0xBE); //0000,0000 A/D Conversion Result Low 2 Bits + +// SPI Special Function Register +#define _SPSTAT 0xCD +SFR(SPSTAT, 0xCD); //00xx,xxxx SPI Status Register +#define _SPCTL 0xCE +SFR(SPCTL, 0xCE); //0000,0100 SPI Control Register +#define _SPDAT 0xCF +SFR(SPDAT, 0xCF); //0000,0000 SPI Data Register + +// IAP/ISP Special Function Register +#define _IAP_DATA 0xC2 +SFR(IAP_DATA, 0xC2); //0000,0000 EEPROM data register +#define _IAP_ADDRH 0xC3 +SFR(IAP_ADDRH, 0xC3); //0000,0000 EEPROM address high byte +#define _IAP_ADDRL 0xC4 +SFR(IAP_ADDRL, 0xC4); //0000,0000 EEPROM address low byte +#define _IAP_CMD 0xC5 +SFR(IAP_CMD, 0xC5); //xxxx,xx00 EEPROM Command Register +#define _IAP_TRIG 0xC6 +SFR(IAP_TRIG, 0xC6); //0000,0000 EEPRPM Command Trigger +#define _IAP_CONTR 0xC7 +SFR(IAP_CONTR, 0xC7); //0000,x000 EEPROM Control Register + +// PCA/PWM Special Function Register +#define _CCON 0xD8 +SFR(CCON, 0xD8); //00xx,xx00 PCA Control Register +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); //0xxx,x000 PCA Working Mode Register +#define _CL 0xE9 +SFR(CL, 0xE9); //0000,0000 PCA Counter Low Byte +#define _CH 0xF9 +SFR(CH, 0xF9); //0000,0000 PCA Counter High Byte +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); //0000,0000 PCA Module 0 PWM Register +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); //0000,0000 PCA Module 1 PWM Register +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); //0000,0000 PCA Module 2 PWM Register +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); //0000,0000 PCA Module 0 Capture/Compare Register Low Byte +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); //0000,0000 PCA Module 1 Capture/Compare Register Low Byte +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); //0000,0000 PCA Module 2 Capture/Compare Register Low Byte +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); //xxxx,xx00 PCA Module 0 PWM Register +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); //xxxx,xx00 PCA Module 1 PWM Register +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); //xxxx,xx00 PCA Module 2 PWM Register +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); //0000,0000 PCA Module 0 Capture/Compare Register High Byte +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); //0000,0000 PCA Module 1 Capture/Compare Register High Byte +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); //0000,0000 PCA Module 2 Capture/Compare Register High Byte + +// Comparator Special Function Register +#define _CMPCR1 0xE6 +SFR(CMPCR1, 0xE6); //0000,0000 Comparator Control Register 1 +#define _CMPCR2 0xE7 +SFR(CMPCR2, 0xE7); //0000,0000 Comparator Control Register 2 + +#endif diff --git a/examples/anymcu-blink/src/STC15W4K.h b/examples/anymcu-blink/src/STC15W4K.h new file mode 100644 index 0000000..8287fdb --- /dev/null +++ b/examples/anymcu-blink/src/STC15W4K.h @@ -0,0 +1,472 @@ +#ifndef STC15W4K_H +#define STC15W4K_H +#include + +// Suitable for use with STC15W4K series MCU with enhanced PWM. +// This header file was verified against the official STC ISP Tool. +// After this file is included you don't have to include "reg51.h" + +///////////////////////////////////////////////// +// Note regarding STC15W4K32S4 series of chips: +// All IO ports related to PWM are high after power-on and +// need to be set to quasi-two-way or strong push-pull modes: +// P0.6/P0.7/P1.6/P1.7/P2.1/P2.2/P2.3/P2.7/P3.7/P4.2/P4.4/P4.5 +///////////////////////////////////////////////// + +// Special Function Register //Reset Value Description +#define _ACC 0xE0 +SFR(ACC, 0xE0); //0000,0000 Accumulator +#define _B 0xF0 +SFR(B, 0xF0); //0000,0000 B Register +#define _PSW 0xD0 +SFR(PSW, 0xD0); //0000,0000 Program status word +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(F1, _PSW, 1); +SBIT(P, _PSW, 0); +#define _SP 0x81 +SFR(SP, 0x81); //0000,0111 Stack Pointer +#define _DPL 0x82 +SFR(DPL, 0x82); //0000,0000 Data Pointer Low Byte +#define _DPH 0x83 +SFR(DPH, 0x83); //0000,0000 Data Pointer High Byte + +// I/O Port Special Function Register +#define _P0 0x80 +SFR(P0, 0x80); //1111,1111 Port 0 +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +SBIT(P0_0, _P0, 0); +SBIT(P0_1, _P0, 1); +SBIT(P0_2, _P0, 2); +SBIT(P0_3, _P0, 3); +SBIT(P0_4, _P0, 4); +SBIT(P0_5, _P0, 5); +SBIT(P0_6, _P0, 6); +SBIT(P0_7, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); //1111,1111 Port 1 +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +SBIT(P1_0, _P1, 0); +SBIT(P1_1, _P1, 1); +SBIT(P1_2, _P1, 2); +SBIT(P1_3, _P1, 3); +SBIT(P1_4, _P1, 4); +SBIT(P1_5, _P1, 5); +SBIT(P1_6, _P1, 6); +SBIT(P1_7, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); //1111,1111 Port 2 +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +SBIT(P2_0, _P2, 0); +SBIT(P2_1, _P2, 1); +SBIT(P2_2, _P2, 2); +SBIT(P2_3, _P2, 3); +SBIT(P2_4, _P2, 4); +SBIT(P2_5, _P2, 5); +SBIT(P2_6, _P2, 6); +SBIT(P2_7, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); //1111,1111 Port 3 +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +SBIT(P3_0, _P3, 0); +SBIT(P3_1, _P3, 1); +SBIT(P3_2, _P3, 2); +SBIT(P3_3, _P3, 3); +SBIT(P3_4, _P3, 4); +SBIT(P3_5, _P3, 5); +SBIT(P3_6, _P3, 6); +SBIT(P3_7, _P3, 7); +#define _P4 0xC0 +SFR(P4, 0xC0); //1111,1111 Port 4 +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +SBIT(P4_0, _P4, 0); +SBIT(P4_1, _P4, 1); +SBIT(P4_2, _P4, 2); +SBIT(P4_3, _P4, 3); +SBIT(P4_4, _P4, 4); +SBIT(P4_5, _P4, 5); +SBIT(P4_6, _P4, 6); +SBIT(P4_7, _P4, 7); +#define _P5 0xC8 +SFR(P5, 0xC8); //xxxx,1111 Port 5 +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +SBIT(P54, _P5, 4); +SBIT(P55, _P5, 5); +SBIT(P56, _P5, 6); +SBIT(P57, _P5, 7); +SBIT(P5_0, _P5, 0); +SBIT(P5_1, _P5, 1); +SBIT(P5_2, _P5, 2); +SBIT(P5_3, _P5, 3); +SBIT(P5_4, _P5, 4); +SBIT(P5_5, _P5, 5); +SBIT(P5_6, _P5, 6); +SBIT(P5_7, _P5, 7); +#define _P6 0xE8 +SFR(P6, 0xE8); //0000,0000 Port 6 +SBIT(P60, _P6, 0); +SBIT(P61, _P6, 1); +SBIT(P62, _P6, 2); +SBIT(P63, _P6, 3); +SBIT(P64, _P6, 4); +SBIT(P65, _P6, 5); +SBIT(P66, _P6, 6); +SBIT(P67, _P6, 7); +SBIT(P6_0, _P6, 0); +SBIT(P6_1, _P6, 1); +SBIT(P6_2, _P6, 2); +SBIT(P6_3, _P6, 3); +SBIT(P6_4, _P6, 4); +SBIT(P6_5, _P6, 5); +SBIT(P6_6, _P6, 6); +SBIT(P6_7, _P6, 7); +#define _P7 0xF8 +SFR(P7, 0xF8); //0000,0000 Port 7 +SBIT(P70, _P7, 0); +SBIT(P71, _P7, 1); +SBIT(P72, _P7, 2); +SBIT(P73, _P7, 3); +SBIT(P74, _P7, 4); +SBIT(P75, _P7, 5); +SBIT(P76, _P7, 6); +SBIT(P77, _P7, 7); +SBIT(P70, _P7, 0); +SBIT(P7_1, _P7, 1); +SBIT(P7_2, _P7, 2); +SBIT(P7_3, _P7, 3); +SBIT(P7_4, _P7, 4); +SBIT(P7_5, _P7, 5); +SBIT(P7_6, _P7, 6); +SBIT(P7_7, _P7, 7); +#define _P0M0 0x94 +SFR(P0M0, 0x94); //0000,0000 Port 0 Mode Register 0 +#define _P0M1 0x93 +SFR(P0M1, 0x93); //0000,0000 Port 0 Mode Register 1 +#define _P1M0 0x92 +SFR(P1M0, 0x92); //0000,0000 Port 1 Mode Register 0 +#define _P1M1 0x91 +SFR(P1M1, 0x91); //0000,0000 Port 1 Mode Register 1 +#define _P2M0 0x96 +SFR(P2M0, 0x96); //0000,0000 Port 2 Mode Register 0 +#define _P2M1 0x95 +SFR(P2M1, 0x95); //0000,0000 Port 2 Mode Register 1 +#define _P3M0 0xB2 +SFR(P3M0, 0xB2); //0000,0000 Port 3 Mode Register 0 +#define _P3M1 0xB1 +SFR(P3M1, 0xB1); //0000,0000 Port 3 Mode Register 1 +#define _P4M0 0xB4 +SFR(P4M0, 0xB4); //0000,0000 Port 4 Mode Register 0 +#define _P4M1 0xB3 +SFR(P4M1, 0xB3); //0000,0000 Port 4 Mode Register 1 +#define _P5M0 0xCA +SFR(P5M0, 0xCA); //0000,0000 Port 5 Mode Register 0 +#define _P5M1 0xC9 +SFR(P5M1, 0xC9); //0000,0000 Port 5 Mode Register 1 +#define _P6M0 0xCC +SFR(P6M0, 0xCC); //0000,0000 Port 6 Mode Register 0 +#define _P6M1 0xCB +SFR(P6M1, 0xCB); //0000,0000 Port 6 Mode Register 1 +#define _P7M0 0xE2 +SFR(P7M0, 0xE2); //0000,0000 Port 7 Mode Register 0 +#define _P7M1 0xE1 +SFR(P7M1, 0xE1); //0000,0000 Port 7 Mode Register 1 + +// System management special function register +#define _PCON 0x87 +SFR(PCON, 0x87); //0001,0000 Power Control Register +#define _AUXR 0x8E +SFR(AUXR, 0x8E); //0000,0000 Auxiliary Register +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); //0000,0000 Auxiliary Register 1 +#define _P_SW1 0xA2 +SFR(P_SW1, 0xA2); //0000,0000 Peripheral Port Switching Register 1 +#define _CLK_DIV 0x97 +SFR(CLK_DIV, 0x97); //xxxx,x000 Clock Division Control Register +#define _BUS_SPEED 0xA1 +SFR(BUS_SPEED, 0xA1); //xx10,x011 Bus Speed Control Register +#define _P1ASF 0x9D +SFR(P1ASF, 0x9D); //0000,0000 Port 1 Analog Function Configuration Register +#define _P_SW2 0xBA +SFR(P_SW2, 0xBA); //0xxx,x000 Peripheral Port Switching Register +#define _IRC_CLKO 0xBB +SFR(IRC_CLKO, 0xBB); //0000,0000 Internal Oscillator Clock Output Control Register + +// Interrupt special function register +#define _IE 0xA8 +SFR(IE, 0xA8); //0000,0000 Interrupt Control Register +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); +SBIT(EADC, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); +#define _IP 0xB8 +SFR(IP, 0xB8); //0000,0000 Interrupt Priority Register +SBIT(PPCA, _IP, 7); +SBIT(PLVD, _IP, 6); +SBIT(PADC, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); +#define _IE2 0xAF +SFR(IE2, 0xAF); //0000,0000 Interrupt Control Register 2 +#define _IP2 0xB5 +SFR(IP2, 0xB5); //xxxx,xx00 Interrupt Priority Register 2 +#define _INT_CLKO 0x8F +SFR(INT_CLKO, 0x8F); //0000,0000 External Interrupt and Clock Output Control Register + +// Timer Special Function Register +#define _TCON 0x88 +SFR(TCON, 0x88); //0000,0000 T0/T1 Control Register +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); +#define _TMOD 0x89 +SFR(TMOD, 0x89); //0000,0000 T0/T1 Mode Register +#define _TL0 0x8A +SFR(TL0, 0x8A); //0000,0000 T0 Low Byte +#define _TL1 0x8B +SFR(TL1, 0x8B); //0000,0000 T1 Low Byte +#define _TH0 0x8C +SFR(TH0, 0x8C); //0000,0000 T0 High Byte +#define _TH1 0x8D +SFR(TH1, 0x8D); //0000,0000 T1 High Byte +#define _T4T3M 0xD1 +SFR(T4T3M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T3T4M 0xD1 +SFR(T3T4M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T4H 0xD2 +SFR(T4H, 0xD2); //0000,0000 T4 High Byte +#define _T4L 0xD3 +SFR(T4L, 0xD3); //0000,0000 T4 Low Byte +#define _T3H 0xD4 +SFR(T3H, 0xD4); //0000,0000 T3 High Byte +#define _T3L 0xD5 +SFR(T3L, 0xD5); //0000,0000 T3 Low Byte +#define _T2H 0xD6 +SFR(T2H, 0xD6); //0000,0000 T2 High Byte +#define _T2L 0xD7 +SFR(T2L, 0xD7); //0000,0000 T2 Low Byte +#define _WKTCL 0xAA +SFR(WKTCL, 0xAA); //0000,0000 Power Down Wakeup Timer Low Byte +#define _WKTCH 0xAB +SFR(WKTCH, 0xAB); //0000,0000 Power Down Wakeup Timer High Byte +#define _WDT_CONTR 0xC1 +SFR(WDT_CONTR, 0xC1); //0000,0000 Watchdog Control Register + +// Serial port special function register +#define _SCON 0x98 +SFR(SCON, 0x98); //0000,0000 Serial Port 1 Control Register +SBIT(SM0, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); +#define _SBUF 0x99 +SFR(SBUF, 0x99); //xxxx,xxxx Serial Port 1 Data Register +#define _S2CON 0x9A +SFR(S2CON, 0x9A); //0000,0000 Serial Port 2 Control Register +#define _S2BUF 0x9B +SFR(S2BUF, 0x9B); //xxxx,xxxx Serial Port 2 Data Register +#define _S3CON 0xAC +SFR(S3CON, 0xAC); //0000,0000 Serial Port 3 Control Register +#define _S3BUF 0xAD +SFR(S3BUF, 0xAD); //xxxx,xxxx Serial Port 3 Data Register +#define _S4CON 0x84 +SFR(S4CON, 0x84); //0000,0000 Serial Port 4 Control Register +#define _S4BUF 0x85 +SFR(S4BUF, 0x85); //xxxx,xxxx Serial Port 4 Data Register +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); //0000,0000 Slave Address Register +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); //0000,0000 Slave Address Mask Register + +// ADC Special Function Register +#define _ADC_CONTR 0xBC +SFR(ADC_CONTR, 0xBC); //0000,0000 A/D Conversion Control Register +#define _ADC_RES 0xBD +SFR(ADC_RES, 0xBD); //0000,0000 A/D Conversion Result High 8 Bits +#define _ADC_RESL 0xBE +SFR(ADC_RESL, 0xBE); //0000,0000 A/D Conversion Result Low 2 Bits + +// SPI Special Function Register +#define _SPSTAT 0xCD +SFR(SPSTAT, 0xCD); //00xx,xxxx SPI Status Register +#define _SPCTL 0xCE +SFR(SPCTL, 0xCE); //0000,0100 SPI Control Register +#define _SPDAT 0xCF +SFR(SPDAT, 0xCF); //0000,0000 SPI Data Register + +// IAP/ISP Special Function Register +#define _IAP_DATA 0xC2 +SFR(IAP_DATA, 0xC2); //0000,0000 EEPROM data register +#define _IAP_ADDRH 0xC3 +SFR(IAP_ADDRH, 0xC3); //0000,0000 EEPROM address high byte +#define _IAP_ADDRL 0xC4 +SFR(IAP_ADDRL, 0xC4); //0000,0000 EEPROM address low byte +#define _IAP_CMD 0xC5 +SFR(IAP_CMD, 0xC5); //xxxx,xx00 EEPROM Command Register +#define _IAP_TRIG 0xC6 +SFR(IAP_TRIG, 0xC6); //0000,0000 EEPRPM Command Trigger +#define _IAP_CONTR 0xC7 +SFR(IAP_CONTR, 0xC7); //0000,x000 EEPROM Control Register + +// PCA/PWM Special Function Register +#define _CCON 0xD8 +SFR(CCON, 0xD8); //00xx,xx00 PCA Control Register +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); //0xxx,x000 PCA Working Mode Register +#define _CL 0xE9 +SFR(CL, 0xE9); //0000,0000 PCA Counter Low Byte +#define _CH 0xF9 +SFR(CH, 0xF9); //0000,0000 PCA Counter High Byte +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); //0000,0000 PCA Module 0 PWM Register +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); //0000,0000 PCA Module 1 PWM Register +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); //0000,0000 PCA Module 2 PWM Register +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); //0000,0000 PCA Module 0 Capture/Compare Register Low Byte +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); //0000,0000 PCA Module 1 Capture/Compare Register Low Byte +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); //0000,0000 PCA Module 2 Capture/Compare Register Low Byte +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); //xxxx,xx00 PCA Module 0 PWM Register +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); //xxxx,xx00 PCA Module 1 PWM Register +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); //xxxx,xx00 PCA Module 2 PWM Register +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); //0000,0000 PCA Module 0 Capture/Compare Register High Byte +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); //0000,0000 PCA Module 1 Capture/Compare Register High Byte +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); //0000,0000 PCA Module 2 Capture/Compare Register High Byte + +// Comparator Special Function Register +#define _CMPCR1 0xE6 +SFR(CMPCR1, 0xE6); //0000,0000 Comparator Control Register 1 +#define _CMPCR2 0xE7 +SFR(CMPCR2, 0xE7); //0000,0000 Comparator Control Register 2 + +// Enhanced PWM waveform generator special function register +#define _PWMCFG 0xF1 +SFR(PWMCFG, 0xF1); //x000,0000 PWM Special Function Register +#define _PWMCR 0xF5 +SFR(PWMCR, 0xF5); //0000,0000 PWM Control Register +#define _PWMIF 0xF6 +SFR(PWMIF, 0xF6); //x000,0000 Interrupt Flag Register +#define _PWMFDCR 0xF7 +SFR(PWMFDCR, 0xF7); //xx00,0000 PWM External Exception Detection Control Register + +// The following special function registers are in the extended RAM area. +// You need to set bit7 of P_SW2 to 1 to read and write them normally. +#define PWMC (*(unsigned int volatile xdata *)0xfff0) +#define PWMCH (*(unsigned char volatile xdata *)0xfff0) +#define PWMCL (*(unsigned char volatile xdata *)0xfff1) +#define PWMCKS (*(unsigned char volatile xdata *)0xfff2) +#define PWM2T1 (*(unsigned int volatile xdata *)0xff00) +#define PWM2T1H (*(unsigned char volatile xdata *)0xff00) +#define PWM2T1L (*(unsigned char volatile xdata *)0xff01) +#define PWM2T2 (*(unsigned int volatile xdata *)0xff02) +#define PWM2T2H (*(unsigned char volatile xdata *)0xff02) +#define PWM2T2L (*(unsigned char volatile xdata *)0xff03) +#define PWM2CR (*(unsigned char volatile xdata *)0xff04) +#define PWM3T1 (*(unsigned int volatile xdata *)0xff10) +#define PWM3T1H (*(unsigned char volatile xdata *)0xff10) +#define PWM3T1L (*(unsigned char volatile xdata *)0xff11) +#define PWM3T2 (*(unsigned int volatile xdata *)0xff12) +#define PWM3T2H (*(unsigned char volatile xdata *)0xff12) +#define PWM3T2L (*(unsigned char volatile xdata *)0xff13) +#define PWM3CR (*(unsigned char volatile xdata *)0xff14) +#define PWM4T1 (*(unsigned int volatile xdata *)0xff20) +#define PWM4T1H (*(unsigned char volatile xdata *)0xff20) +#define PWM4T1L (*(unsigned char volatile xdata *)0xff21) +#define PWM4T2 (*(unsigned int volatile xdata *)0xff22) +#define PWM4T2H (*(unsigned char volatile xdata *)0xff22) +#define PWM4T2L (*(unsigned char volatile xdata *)0xff23) +#define PWM4CR (*(unsigned char volatile xdata *)0xff24) +#define PWM5T1 (*(unsigned int volatile xdata *)0xff30) +#define PWM5T1H (*(unsigned char volatile xdata *)0xff30) +#define PWM5T1L (*(unsigned char volatile xdata *)0xff31) +#define PWM5T2 (*(unsigned int volatile xdata *)0xff32) +#define PWM5T2H (*(unsigned char volatile xdata *)0xff32) +#define PWM5T2L (*(unsigned char volatile xdata *)0xff33) +#define PWM5CR (*(unsigned char volatile xdata *)0xff34) +#define PWM6T1 (*(unsigned int volatile xdata *)0xff40) +#define PWM6T1H (*(unsigned char volatile xdata *)0xff40) +#define PWM6T1L (*(unsigned char volatile xdata *)0xff41) +#define PWM6T2 (*(unsigned int volatile xdata *)0xff42) +#define PWM6T2H (*(unsigned char volatile xdata *)0xff42) +#define PWM6T2L (*(unsigned char volatile xdata *)0xff43) +#define PWM6CR (*(unsigned char volatile xdata *)0xff44) +#define PWM7T1 (*(unsigned int volatile xdata *)0xff50) +#define PWM7T1H (*(unsigned char volatile xdata *)0xff50) +#define PWM7T1L (*(unsigned char volatile xdata *)0xff51) +#define PWM7T2 (*(unsigned int volatile xdata *)0xff52) +#define PWM7T2H (*(unsigned char volatile xdata *)0xff52) +#define PWM7T2L (*(unsigned char volatile xdata *)0xff53) +#define PWM7CR (*(unsigned char volatile xdata *)0xff54) + +#endif diff --git a/examples/anymcu-blink/src/STC89xx.h b/examples/anymcu-blink/src/STC89xx.h new file mode 100644 index 0000000..094667c --- /dev/null +++ b/examples/anymcu-blink/src/STC89xx.h @@ -0,0 +1,298 @@ +#ifndef STC89xx_H +#define STC89xx_H + +#include + +// 适用于 STC89xx / STC90xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR*/ + +/* + * #define _AUXR 0x8e + * SFR(AUXR, 0x8e); + * #define _AUXR1 0xa2 + * SFR(AUXR1, 0xa2); + * #define _IPH 0xb7 + * SFR(IPH, 0xb7); + */ + +#define _P4 0xe8 +SFR(P4, 0xe8); +SBIT(P46, _P4, 6); +SBIT(P45, _P4, 5); //ISP下载需勾选"ALE脚用作P4.5口" +SBIT(P44, _P4, 4); +SBIT(P43, _P4, 3); +SBIT(P42, _P4, 2); +SBIT(P41, _P4, 1); +SBIT(P40, _P4, 0); + +#define _XICON 0xc0 +SFR(XICON, 0xc0); + +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* Above is STC additional SFR */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* PCA SFR +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +*/ + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EC, _IE, 6); +SBIT(ET2, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +/* SBIT(PPC, _IP, 6);*/ +SBIT(PT2, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +/* P1 */ +/* PCA +SBIT(CEX4, _P1, 7); +SBIT(CEX3, _P1, 6); +SBIT(CEX2, _P1, 5); +SBIT(CEX1, _P1, 4); +SBIT(CEX0, _P1, 3); +SBIT(ECI, _P1, 2); +*/ + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* CCON */ +/* PCA +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); + +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +*/ + +#endif diff --git a/examples/anymcu-blink/src/STC8Fxx.h b/examples/anymcu-blink/src/STC8Fxx.h new file mode 100644 index 0000000..97b9f12 --- /dev/null +++ b/examples/anymcu-blink/src/STC8Fxx.h @@ -0,0 +1,715 @@ +#ifndef STC8Fxx_H +#define STC8Fxx_H + +#include + +// 包含本头文件后,不用另外再包含"REG51.H" +// 适用于 STC8Fxx / STC8Axx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +//内核特殊功能寄存器 +#define _ACC 0xe0 +SFR(ACC, 0xe0); +#define _B 0xf0 +SFR(B, 0xf0); +#define _PSW 0xd0 +SFR(PSW, 0xd0); +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _TA 0xae +SFR(TA, 0xae); +#define _DPS 0xe3 +SFR(DPS, 0xe3); +#define _DPL1 0xe4 +SFR(DPL1, 0xe4); +#define _DPH1 0xe5 +SFR(DPH1, 0xe5); + +//I/O 口特殊功能寄存器 +#define _P0 0x80 +SFR(P0, 0x80); +#define _P1 0x90 +SFR(P1, 0x90); +#define _P2 0xa0 +SFR(P2, 0xa0); +#define _P3 0xb0 +SFR(P3, 0xb0); +#define _P4 0xc0 +SFR(P4, 0xc0); +#define _P5 0xc8 +SFR(P5, 0xc8); +#define _P6 0xe8 +SFR(P6, 0xe8); +#define _P7 0xf8 +SFR(P7, 0xf8); +#define _P0M0 0x94 +SFR(P0M0, 0x94); +#define _P0M1 0x93 +SFR(P0M1, 0x93); +#define _P1M0 0x92 +SFR(P1M0, 0x92); +#define _P1M1 0x91 +SFR(P1M1, 0x91); +#define _P2M0 0x96 +SFR(P2M0, 0x96); +#define _P2M1 0x95 +SFR(P2M1, 0x95); +#define _P3M0 0xb2 +SFR(P3M0, 0xb2); +#define _P3M1 0xb1 +SFR(P3M1, 0xb1); +#define _P4M0 0xb4 +SFR(P4M0, 0xb4); +#define _P4M1 0xb3 +SFR(P4M1, 0xb3); +#define _P5M0 0xca +SFR(P5M0, 0xca); +#define _P5M1 0xc9 +SFR(P5M1, 0xc9); +#define _P6M0 0xcc +SFR(P6M0, 0xcc); +#define _P6M1 0xcb +SFR(P6M1, 0xcb); +#define _P7M0 0xe2 +SFR(P7M0, 0xe2); +#define _P7M1 0xe1 +SFR(P7M1, 0xe1); + +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +SBIT(P54, _P5, 4); +SBIT(P55, _P5, 5); +SBIT(P56, _P5, 6); +SBIT(P57, _P5, 7); +SBIT(P60, _P6, 0); +SBIT(P61, _P6, 1); +SBIT(P62, _P6, 2); +SBIT(P63, _P6, 3); +SBIT(P64, _P6, 4); +SBIT(P65, _P6, 5); +SBIT(P66, _P6, 6); +SBIT(P67, _P6, 7); +SBIT(P70, _P7, 0); +SBIT(P71, _P7, 1); +SBIT(P72, _P7, 2); +SBIT(P73, _P7, 3); +SBIT(P74, _P7, 4); +SBIT(P75, _P7, 5); +SBIT(P76, _P7, 6); +SBIT(P77, _P7, 7); + +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define P0PU (*(unsigned char volatile xdata *)0xfe10) +#define P1PU (*(unsigned char volatile xdata *)0xfe11) +#define P2PU (*(unsigned char volatile xdata *)0xfe12) +#define P3PU (*(unsigned char volatile xdata *)0xfe13) +#define P4PU (*(unsigned char volatile xdata *)0xfe14) +#define P5PU (*(unsigned char volatile xdata *)0xfe15) +#define P6PU (*(unsigned char volatile xdata *)0xfe16) +#define P7PU (*(unsigned char volatile xdata *)0xfe17) +#define P0NCS (*(unsigned char volatile xdata *)0xfe18) +#define P1NCS (*(unsigned char volatile xdata *)0xfe19) +#define P2NCS (*(unsigned char volatile xdata *)0xfe1a) +#define P3NCS (*(unsigned char volatile xdata *)0xfe1b) +#define P4NCS (*(unsigned char volatile xdata *)0xfe1c) +#define P5NCS (*(unsigned char volatile xdata *)0xfe1d) +#define P6NCS (*(unsigned char volatile xdata *)0xfe1e) +#define P7NCS (*(unsigned char volatile xdata *)0xfe1f) + +//系统管理特殊功能寄存器 +#define _PCON 0x87 +SFR(PCON, 0x87); +#define SMOD 0x80 +#define SMOD0 0x40 +#define LVDF 0x20 +#define POF 0x10 +#define GF1 0x08 +#define GF0 0x04 +#define PD 0x02 +#define IDL 0x01 +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define T0x12 0x80 +#define T1x12 0x40 +#define UART_M0x6 0x20 +#define T2R 0x10 +#define T2_CT 0x08 +#define T2x12 0x04 +#define EXTRAM 0x02 +#define S1ST2 0x01 +#define _AUXR2 0x97 +SFR(AUXR2, 0x97); +#define TXLNRX 0x10 +#define _BUS_SPEED 0xa1 +SFR(BUS_SPEED, 0xa1); +#define _P_SW1 0xa2 +SFR(P_SW1, 0xa2); +#define _P_SW2 0xba +SFR(P_SW2, 0xba); +#define EAXFR 0x80 +#define _VOCTRL 0xbb +SFR(VOCTRL, 0xbb); +#define _RSTCFG 0xff +SFR(RSTCFG, 0xff); + +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define CKSEL (*(unsigned char volatile xdata *)0xfe00) +#define CLKDIV (*(unsigned char volatile xdata *)0xfe01) +#define IRC24MCR (*(unsigned char volatile xdata *)0xfe02) +#define XOSCCR (*(unsigned char volatile xdata *)0xfe03) +#define IRC32KCR (*(unsigned char volatile xdata *)0xfe04) + +//中断特殊功能寄存器 +#define _IE 0xa8 +SFR(IE, 0xa8); +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); +SBIT(EADC, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); +#define _IE2 0xaf +SFR(IE2, 0xaf); +#define ET4 0x40 +#define ET3 0x20 +#define ES4 0x10 +#define ES3 0x08 +#define ET2 0x04 +#define ESPI 0x02 +#define ES2 0x01 +#define _IP 0xb8 +SFR(IP, 0xb8); +SBIT(PPCA, _IP, 7); +SBIT(PLVD, _IP, 6); +SBIT(PADC, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); +#define _IP2 0xb5 +SFR(IP2, 0xb5); +#define PI2C 0x40 +#define PCMP 0x20 +#define PX4 0x10 +#define PPWMFD 0x08 +#define PPWM 0x04 +#define PSPI 0x02 +#define PS2 0x01 +#define _IPH 0xb7 +SFR(IPH, 0xb7); +#define PPCAH 0x80 +#define PLVDH 0x40 +#define PADCH 0x20 +#define PSH 0x10 +#define PT1H 0x08 +#define PX1H 0x04 +#define PT0H 0x02 +#define PX0H 0x01 +#define _IP2H 0xb6 +SFR(IP2H, 0xb6); +#define PI2CH 0x40 +#define PCMPH 0x20 +#define PX4H 0x10 +#define PPWMFDH 0x08 +#define PPWMH 0x04 +#define PSPIH 0x02 +#define PS2H 0x01 +#define _INTCLKO 0x8f +SFR(INTCLKO, 0x8f); +#define EX4 0x40 +#define EX3 0x20 +#define EX2 0x10 +#define T2CLKO 0x04 +#define T1CLKO 0x02 +#define T0CLKO 0x01 +#define _AUXINTIF 0xef +SFR(AUXINTIF, 0xef); +#define INT4IF 0x40 +#define INT3IF 0x20 +#define INT2IF 0x10 +#define T4IF 0x04 +#define T3IF 0x02 +#define T2IF 0x01 + +//定时器特殊功能寄存器 +#define _TCON 0x88 +SFR(TCON, 0x88); +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define T1_GATE 0x80 +#define T1_CT 0x40 +#define T1_M1 0x20 +#define T1_M0 0x10 +#define T0_GATE 0x08 +#define T0_CT 0x04 +#define T0_M1 0x02 +#define T0_M0 0x01 +#define _TL0 0x8a +SFR(TL0, 0x8a); +#define _TL1 0x8b +SFR(TL1, 0x8b); +#define _TH0 0x8c +SFR(TH0, 0x8c); +#define _TH1 0x8d +SFR(TH1, 0x8d); +#define _T4T3M 0xd1 +SFR(T4T3M, 0xd1); +#define T4R 0x80 +#define T4_CT 0x40 +#define T4x12 0x20 +#define T4CLKO 0x10 +#define T3R 0x08 +#define T3_CT 0x04 +#define T3x12 0x02 +#define T3CLKO 0x01 +#define _T4H 0xd2 +SFR(T4H, 0xd2); +#define _T4L 0xd3 +SFR(T4L, 0xd3); +#define _T3H 0xd4 +SFR(T3H, 0xd4); +#define _T3L 0xd5 +SFR(T3L, 0xd5); +#define _T2H 0xd6 +SFR(T2H, 0xd6); +#define _T2L 0xd7 +SFR(T2L, 0xd7); +#define _TH4 0xd2 +SFR(TH4, 0xd2); +#define _TL4 0xd3 +SFR(TL4, 0xd3); +#define _TH3 0xd4 +SFR(TH3, 0xd4); +#define _TL3 0xd5 +SFR(TL3, 0xd5); +#define _TH2 0xd6 +SFR(TH2, 0xd6); +#define _TL2 0xd7 +SFR(TL2, 0xd7); +#define _WKTCL 0xaa +SFR(WKTCL, 0xaa); +#define _WKTCH 0xab +SFR(WKTCH, 0xab); +#define WKTEN 0x80 +#define _WDT_CONTR 0xc1 +SFR(WDT_CONTR, 0xc1); +#define WDT_FLAG 0x80 +#define EN_WDT 0x20 +#define CLR_WDT 0x10 +#define IDL_WDT 0x08 + +//串行口特殊功能寄存器 +#define _SCON 0x98 +SFR(SCON, 0x98); +SBIT(SM0, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); +#define _SBUF 0x99 +SFR(SBUF, 0x99); +#define _S2CON 0x9a +SFR(S2CON, 0x9a); +#define S2SM0 0x80 +#define S2ST4 0x40 +#define S2SM2 0x20 +#define S2REN 0x10 +#define S2TB8 0x08 +#define S2RB8 0x04 +#define S2TI 0x02 +#define S2RI 0x01 +#define _S2BUF 0x9b +SFR(S2BUF, 0x9b); +#define _S3CON 0xac +SFR(S3CON, 0xac); +#define S3SM0 0x80 +#define S3ST4 0x40 +#define S3SM2 0x20 +#define S3REN 0x10 +#define S3TB8 0x08 +#define S3RB8 0x04 +#define S3TI 0x02 +#define S3RI 0x01 +#define _S3BUF 0xad +SFR(S3BUF, 0xad); +#define _S4CON 0x84 +SFR(S4CON, 0x84); +#define S4SM0 0x80 +#define S4ST4 0x40 +#define S4SM2 0x20 +#define S4REN 0x10 +#define S4TB8 0x08 +#define S4RB8 0x04 +#define S4TI 0x02 +#define S4RI 0x01 +#define _S4BUF 0x85 +SFR(S4BUF, 0x85); +#define _SADDR 0xa9 +SFR(SADDR, 0xa9); +#define _SADEN 0xb9 +SFR(SADEN, 0xb9); + +//ADC 特殊功能寄存器 +#define _ADC_CONTR 0xbc +SFR(ADC_CONTR, 0xbc); +#define ADC_POWER 0x80 +#define ADC_START 0x40 +#define ADC_FLAG 0x20 +#define _ADC_RES 0xbd +SFR(ADC_RES, 0xbd); +#define _ADC_RESL 0xbe +SFR(ADC_RESL, 0xbe); +#define _ADCCFG 0xde +SFR(ADCCFG, 0xde); +#define ADC_RESFMT 0x20 + +//SPI 特殊功能寄存器 +#define _SPSTAT 0xcd +SFR(SPSTAT, 0xcd); +#define SPIF 0x80 +#define WCOL 0x40 +#define _SPCTL 0xce +SFR(SPCTL, 0xce); +#define SSIG 0x80 +#define SPEN 0x40 +#define DORD 0x20 +#define MSTR 0x10 +#define CPOL 0x08 +#define CPHA 0x04 +#define _SPDAT 0xcf +SFR(SPDAT, 0xcf); + +//IAP/ISP 特殊功能寄存器 +#define _IAP_DATA 0xc2 +SFR(IAP_DATA, 0xc2); +#define _IAP_ADDRH 0xc3 +SFR(IAP_ADDRH, 0xc3); +#define _IAP_ADDRL 0xc4 +SFR(IAP_ADDRL, 0xc4); +#define _IAP_CMD 0xc5 +SFR(IAP_CMD, 0xc5); +#define IAP_IDL 0x00 +#define IAP_READ 0x01 +#define IAP_WRITE 0x02 +#define IAP_ERASE 0x03 +#define _IAP_TRIG 0xc6 +SFR(IAP_TRIG, 0xc6); +#define _IAP_CONTR 0xc7 +SFR(IAP_CONTR, 0xc7); +#define IAPEN 0x80 +#define SWBS 0x40 +#define SWRST 0x20 +#define CMD_FAIL 0x10 +#define _ISP_DATA 0xc2 +SFR(ISP_DATA, 0xc2); +#define _ISP_ADDRH 0xc3 +SFR(ISP_ADDRH, 0xc3); +#define _ISP_ADDRL 0xc4 +SFR(ISP_ADDRL, 0xc4); +#define _ISP_CMD 0xc5 +SFR(ISP_CMD, 0xc5); +#define _ISP_TRIG 0xc6 +SFR(ISP_TRIG, 0xc6); +#define _ISP_CONTR 0xc7 +SFR(ISP_CONTR, 0xc7); + +//比较器特殊功能寄存器 +#define _CMPCR1 0xe6 +SFR(CMPCR1, 0xe6); +#define CMPEN 0x80 +#define CMPIF 0x40 +#define PIE 0x20 +#define NIE 0x10 +#define PIS 0x08 +#define NIS 0x04 +#define CMPOE 0x02 +#define CMPRES 0x01 +#define _CMPCR2 0xe7 +SFR(CMPCR2, 0xe7); +#define INVCMPO 0x80 +#define DISFLT 0x40 + +//PCA/PWM 特殊功能寄存器 +#define _CCON 0xd8 +SFR(CCON, 0xd8); +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +#define _CMOD 0xd9 +SFR(CMOD, 0xd9); +#define CIDL 0x80 +#define ECF 0x01 +#define _CL 0xe9 +SFR(CL, 0xe9); +#define _CH 0xf9 +SFR(CH, 0xf9); +#define _CCAPM0 0xda +SFR(CCAPM0, 0xda); +#define ECOM0 0x40 +#define CCAPP0 0x20 +#define CCAPN0 0x10 +#define MAT0 0x08 +#define TOG0 0x04 +#define PWM0 0x02 +#define ECCF0 0x01 +#define _CCAPM1 0xdb +SFR(CCAPM1, 0xdb); +#define ECOM1 0x40 +#define CCAPP1 0x20 +#define CCAPN1 0x10 +#define MAT1 0x08 +#define TOG1 0x04 +#define PWM1 0x02 +#define ECCF1 0x01 +#define _CCAPM2 0xdc +SFR(CCAPM2, 0xdc); +#define ECOM2 0x40 +#define CCAPP2 0x20 +#define CCAPN2 0x10 +#define MAT2 0x08 +#define TOG2 0x04 +#define PWM2 0x02 +#define ECCF2 0x01 +#define _CCAPM3 0xdd +SFR(CCAPM3, 0xdd); +#define ECOM3 0x40 +#define CCAPP3 0x20 +#define CCAPN3 0x10 +#define MAT3 0x08 +#define TOG3 0x04 +#define PWM3 0x02 +#define ECCF3 0x01 +#define _CCAP0L 0xea +SFR(CCAP0L, 0xea); +#define _CCAP1L 0xeb +SFR(CCAP1L, 0xeb); +#define _CCAP2L 0xec +SFR(CCAP2L, 0xec); +#define _CCAP3L 0xed +SFR(CCAP3L, 0xed); +#define _CCAP0H 0xfa +SFR(CCAP0H, 0xfa); +#define _CCAP1H 0xfb +SFR(CCAP1H, 0xfb); +#define _CCAP2H 0xfc +SFR(CCAP2H, 0xfc); +#define _CCAP3H 0xfd +SFR(CCAP3H, 0xfd); +#define _PCA_PWM0 0xf2 +SFR(PCA_PWM0, 0xf2); +#define _PCA_PWM1 0xf3 +SFR(PCA_PWM1, 0xf3); +#define _PCA_PWM2 0xf4 +SFR(PCA_PWM2, 0xf4); +#define _PCA_PWM3 0xf5 +SFR(PCA_PWM3, 0xf5); + +//增强型PWM波形发生器特殊功能寄存器 +#define _PWMCFG 0xf1 +SFR(PWMCFG, 0xf1); +#define CBIF 0x80 +#define ETADC 0x40 +#define _PWMIF 0xf6 +SFR(PWMIF, 0xf6); +#define C7IF 0x80 +#define C6IF 0x40 +#define C5IF 0x20 +#define C4IF 0x10 +#define C3IF 0x08 +#define C2IF 0x04 +#define C1IF 0x02 +#define C0IF 0x01 +#define _PWMFDCR 0xf7 +SFR(PWMFDCR, 0xf7); +#define INVCMP 0x80 +#define INVIO 0x40 +#define ENFD 0x20 +#define FLTFLIO 0x10 +#define EFDI 0x08 +#define FDCMP 0x04 +#define FDIO 0x02 +#define FDIF 0x01 +#define _PWMCR 0xfe +SFR(PWMCR, 0xfe); +#define ENPWM 0x80 +#define ECBI 0x40 + +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define PWMC (*(unsigned int volatile xdata *)0xfff0) +#define PWMCH (*(unsigned char volatile xdata *)0xfff0) +#define PWMCL (*(unsigned char volatile xdata *)0xfff1) +#define PWMCKS (*(unsigned char volatile xdata *)0xfff2) +#define TADCP (*(unsigned char volatile xdata *)0xfff3) +#define TADCPH (*(unsigned char volatile xdata *)0xfff3) +#define TADCPL (*(unsigned char volatile xdata *)0xfff4) +#define PWM0T1 (*(unsigned int volatile xdata *)0xff00) +#define PWM0T1H (*(unsigned char volatile xdata *)0xff00) +#define PWM0T1L (*(unsigned char volatile xdata *)0xff01) +#define PWM0T2 (*(unsigned int volatile xdata *)0xff02) +#define PWM0T2H (*(unsigned char volatile xdata *)0xff02) +#define PWM0T2L (*(unsigned char volatile xdata *)0xff03) +#define PWM0CR (*(unsigned char volatile xdata *)0xff04) +#define PWM0HLD (*(unsigned char volatile xdata *)0xff05) +#define PWM1T1 (*(unsigned int volatile xdata *)0xff10) +#define PWM1T1H (*(unsigned char volatile xdata *)0xff10) +#define PWM1T1L (*(unsigned char volatile xdata *)0xff11) +#define PWM1T2 (*(unsigned int volatile xdata *)0xff12) +#define PWM1T2H (*(unsigned char volatile xdata *)0xff12) +#define PWM1T2L (*(unsigned char volatile xdata *)0xff13) +#define PWM1CR (*(unsigned char volatile xdata *)0xff14) +#define PWM1HLD (*(unsigned char volatile xdata *)0xff15) +#define PWM2T1 (*(unsigned int volatile xdata *)0xff20) +#define PWM2T1H (*(unsigned char volatile xdata *)0xff20) +#define PWM2T1L (*(unsigned char volatile xdata *)0xff21) +#define PWM2T2 (*(unsigned int volatile xdata *)0xff22) +#define PWM2T2H (*(unsigned char volatile xdata *)0xff22) +#define PWM2T2L (*(unsigned char volatile xdata *)0xff23) +#define PWM2CR (*(unsigned char volatile xdata *)0xff24) +#define PWM2HLD (*(unsigned char volatile xdata *)0xff25) +#define PWM3T1 (*(unsigned int volatile xdata *)0xff30) +#define PWM3T1H (*(unsigned char volatile xdata *)0xff30) +#define PWM3T1L (*(unsigned char volatile xdata *)0xff31) +#define PWM3T2 (*(unsigned int volatile xdata *)0xff32) +#define PWM3T2H (*(unsigned char volatile xdata *)0xff32) +#define PWM3T2L (*(unsigned char volatile xdata *)0xff33) +#define PWM3CR (*(unsigned char volatile xdata *)0xff34) +#define PWM3HLD (*(unsigned char volatile xdata *)0xff35) +#define PWM4T1 (*(unsigned int volatile xdata *)0xff40) +#define PWM4T1H (*(unsigned char volatile xdata *)0xff40) +#define PWM4T1L (*(unsigned char volatile xdata *)0xff41) +#define PWM4T2 (*(unsigned int volatile xdata *)0xff42) +#define PWM4T2H (*(unsigned char volatile xdata *)0xff42) +#define PWM4T2L (*(unsigned char volatile xdata *)0xff43) +#define PWM4CR (*(unsigned char volatile xdata *)0xff44) +#define PWM4HLD (*(unsigned char volatile xdata *)0xff45) +#define PWM5T1 (*(unsigned int volatile xdata *)0xff50) +#define PWM5T1H (*(unsigned char volatile xdata *)0xff50) +#define PWM5T1L (*(unsigned char volatile xdata *)0xff51) +#define PWM5T2 (*(unsigned int volatile xdata *)0xff52) +#define PWM5T2H (*(unsigned char volatile xdata *)0xff52) +#define PWM5T2L (*(unsigned char volatile xdata *)0xff53) +#define PWM5CR (*(unsigned char volatile xdata *)0xff54) +#define PWM5HLD (*(unsigned char volatile xdata *)0xff55) +#define PWM6T1 (*(unsigned int volatile xdata *)0xff60) +#define PWM6T1H (*(unsigned char volatile xdata *)0xff60) +#define PWM6T1L (*(unsigned char volatile xdata *)0xff61) +#define PWM6T2 (*(unsigned int volatile xdata *)0xff62) +#define PWM6T2H (*(unsigned char volatile xdata *)0xff62) +#define PWM6T2L (*(unsigned char volatile xdata *)0xff63) +#define PWM6CR (*(unsigned char volatile xdata *)0xff64) +#define PWM6HLD (*(unsigned char volatile xdata *)0xff65) +#define PWM7T1 (*(unsigned int volatile xdata *)0xff70) +#define PWM7T1H (*(unsigned char volatile xdata *)0xff70) +#define PWM7T1L (*(unsigned char volatile xdata *)0xff71) +#define PWM7T2 (*(unsigned int volatile xdata *)0xff72) +#define PWM7T2H (*(unsigned char volatile xdata *)0xff72) +#define PWM7T2L (*(unsigned char volatile xdata *)0xff73) +#define PWM7CR (*(unsigned char volatile xdata *)0xff74) +#define PWM7HLD (*(unsigned char volatile xdata *)0xff75) + +//I2C特殊功能寄存器 +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define I2CCFG (*(unsigned char volatile xdata *)0xfe80) +#define ENI2C 0x80 +#define MSSL 0x40 +#define I2CMSCR (*(unsigned char volatile xdata *)0xfe81) +#define EMSI 0x80 +#define I2CMSST (*(unsigned char volatile xdata *)0xfe82) +#define MSBUSY 0x80 +#define MSIF 0x40 +#define MSACKI 0x02 +#define MSACKO 0x01 +#define I2CSLCR (*(unsigned char volatile xdata *)0xfe83) +#define ESTAI 0x40 +#define ERXI 0x20 +#define ETXI 0x10 +#define ESTOI 0x08 +#define SLRST 0x01 +#define I2CSLST (*(unsigned char volatile xdata *)0xfe84) +#define SLBUSY 0x80 +#define STAIF 0x40 +#define RXIF 0x20 +#define TXIF 0x10 +#define STOIF 0x08 +#define TXING 0x04 +#define SLACKI 0x02 +#define SLACKO 0x01 +#define I2CSLADR (*(unsigned char volatile xdata *)0xfe85) +#define I2CTXD (*(unsigned char volatile xdata *)0xfe86) +#define I2CRXD (*(unsigned char volatile xdata *)0xfe87) + +#endif diff --git a/examples/anymcu-blink/src/STC90C5xAD.h b/examples/anymcu-blink/src/STC90C5xAD.h new file mode 100644 index 0000000..0141a22 --- /dev/null +++ b/examples/anymcu-blink/src/STC90C5xAD.h @@ -0,0 +1,298 @@ +#ifndef STC90C5xAD_H +#define STC90C5xAD_H + +#include + +// 适用于 STC90C5xAD 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _AUXR1 0xa2 +SFR(AUXR1, 0xa2); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +#define _P4 0xc0 +SFR(P4, 0xc0); +SBIT(P46, _P4, 6); +SBIT(P45, _P4, 5); //ISP下载需勾选"ALE脚用作P4.5口" +SBIT(P44, _P4, 4); +SBIT(P43, _P4, 3); +SBIT(P42, _P4, 2); +SBIT(P41, _P4, 1); +SBIT(P40, _P4, 0); + +#define _XICON 0xe8 +SFR(XICON, 0xe8); + +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* Above is STC additional SFR */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* PCA SFR +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +*/ + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EC, _IE, 6); +SBIT(ET2, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +//SBIT(PPC, _IP, 6); +SBIT(PT2, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +/* P1 */ +/* PCA +SBIT(CEX4, _P1, 7); +SBIT(CEX3, _P1, 6); +SBIT(CEX2, _P1, 5); +SBIT(CEX1, _P1, 4); +SBIT(CEX0, _P1, 3); +SBIT(ECI, _P1, 2); +*/ + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* CCON */ +/* PCA +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); + +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +*/ + +#endif diff --git a/examples/anymcu-blink/src/delay.c b/examples/anymcu-blink/src/delay.c new file mode 100644 index 0000000..65e18b3 --- /dev/null +++ b/examples/anymcu-blink/src/delay.c @@ -0,0 +1,50 @@ +#include "delay.h" + +#define MAIN_Fosc 16000000L //Define the clock +//#define MAIN_Fosc 11059200L //Define the clock + +void delay_c_ms(unsigned char ms) //Software delay in mili-sec +{ //Calibrated for STC on SDCC + unsigned int i; + do + { + i = MAIN_Fosc / 13000; + while (--i); // 14T per loop + } while (--ms); +} + +void delay_c_ds(unsigned char ds) //Software delay in deci-sec +{ //Calibrated for STC on SDCC + unsigned int i; + do + { + i = MAIN_Fosc / 1300; + while (--i); // 14T per loop + } while (--ds); +} + +void delay_s_ms(unsigned char ms) //Software delay in mili-sec +{ //Calibrated for Nuvoton N76E003 + ms; //Must declare delay variable + __asm + MOV R2,dpl //Variable ms was passed via dpl + 00001$: MOV R1,#0x08 //8 x 12.5ms produces 1ms total + 00002$: MOV R0,#0xFA //FA is 12.5ms (or C7 is 100us) + 00003$: DJNZ R0,00003$ + DJNZ R1,00002$ + DJNZ R2,00001$ + __endasm; +} + +void delay_s_ds(unsigned char ds) //Software delay in deci-sec +{ //Calibrated for Nuvoton N76E003 + ds; //Must declare delay variable + __asm + MOV R2,dpl //Variable ds was passed via dpl + 00001$: MOV R1,#0x50 //80 x 12.5ms produces 1ds total + 00002$: MOV R0,#0xFA //FA is 12.5ms (or C7 is 100us) + 00003$: DJNZ R0,00003$ + DJNZ R1,00002$ + DJNZ R2,00001$ + __endasm; +} diff --git a/examples/anymcu-blink/src/delay.h b/examples/anymcu-blink/src/delay.h new file mode 100644 index 0000000..1cb8b9a --- /dev/null +++ b/examples/anymcu-blink/src/delay.h @@ -0,0 +1,9 @@ +#ifndef __DELAY_H +#define __DELAY_H + +void delay_c_ms(unsigned char ms); +void delay_s_ms(unsigned char ms); +void delay_c_ds(unsigned char ds); +void delay_s_ds(unsigned char ds); + +#endif diff --git a/examples/anymcu-blink/src/main.c b/examples/anymcu-blink/src/main.c new file mode 100644 index 0000000..7440c7a --- /dev/null +++ b/examples/anymcu-blink/src/main.c @@ -0,0 +1,106 @@ +// Blink example for all mcs51 boards with automatic LED pin +// Your boardname.json should pass the MCU names shown below +// Include files by board name listed in alphabetical order: +#if defined(N76E003) + #include "N76E003.h" + #define ledPin P14 + #define INIT_PIN P1M1 &= 0xFE; P1M2 &= 0xFE; + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 4 +#elif defined(STC15F10XW) + #include "STC15.h" + #define ledPin P33 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 3 pin 3 +#elif defined(STC15F20XA) + #include "STC15.h" + #define ledPin P33 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 3 pin 3 +#elif defined(STC15F2KXXS2) + #include "STC15.h" + #define ledPin P10 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#elif defined(STC15W10X) + #include "STC15.h" + #define ledPin P33 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 3 pin 3 +#elif defined(STC15W20XS) + #include "STC15.h" + #define ledPin P33 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 3 pin 3 +#elif defined(STC15W40XAS) + #include "STC15.h" + #define ledPin P10 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#elif defined(STC12C5AXXS2) + #include + #define ledPin P10 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#elif defined(STC89C5XRX) + #include + #define ledPin P10 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#elif defined(AT89S51) + #include + #define ledPin P10 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#elif defined(AT89S52) + #include + #define ledPin P10 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#elif defined(Generic8052) + #include "Generic8052.h" + #define ledPin P1_0 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#else // Assume Generic8051 + #include "Generic8051.h" + #define ledPin P1_0 + #define INIT_PIN //Pin init not needed + //print this out as an info during compilation + #warning Connect LED to MCU port 1 pin 0 +#endif +#include "delay.h" +/*----------------------------------------------------------------------------- + MAIN ROUTINE +-----------------------------------------------------------------------------*/ +void main(void) +{ + INIT_PIN // Macro if needed to initialize output pin + while (1) + { + ledPin = 0x00; // LED on + delay_c_ds(250); // Software delay 2500ms + ledPin = 0xff; // LED off + delay_s_ds(250); // Software delay 2500ms + + // int n; + // ledPin = 0; // LED on + // for (n = 0; n < 50000; n++); // waste some cycles + // ledPin = 1; // LED off + // for (n = 0; n < 50000; n++); // waste some cycles + } +} +/*----------------------------------------------------------------------------- + END OF MODULE +-----------------------------------------------------------------------------*/ diff --git a/examples/anymcu-blink/test/README b/examples/anymcu-blink/test/README new file mode 100644 index 0000000..e7d1588 --- /dev/null +++ b/examples/anymcu-blink/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PlatformIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PlatformIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html diff --git a/examples/anymcu-header/.gitignore b/examples/anymcu-header/.gitignore new file mode 100644 index 0000000..6c69f4c --- /dev/null +++ b/examples/anymcu-header/.gitignore @@ -0,0 +1,2 @@ +.pioenvs +.piolibdeps diff --git a/examples/anymcu-header/.travis.yml b/examples/anymcu-header/.travis.yml new file mode 100644 index 0000000..7c486f1 --- /dev/null +++ b/examples/anymcu-header/.travis.yml @@ -0,0 +1,67 @@ +# Continuous Integration (CI) is the practice, in software +# engineering, of merging all developer working copies with a shared mainline +# several times a day < https://docs.platformio.org/page/ci/index.html > +# +# Documentation: +# +# * Travis CI Embedded Builds with PlatformIO +# < https://docs.travis-ci.com/user/integration/platformio/ > +# +# * PlatformIO integration with Travis CI +# < https://docs.platformio.org/page/ci/travis.html > +# +# * User Guide for `platformio ci` command +# < https://docs.platformio.org/page/userguide/cmd_ci.html > +# +# +# Please choose one of the following templates (proposed below) and uncomment +# it (remove "# " before each line) or use own configuration according to the +# Travis CI documentation (see above). +# + + +# +# Template #1: General project. Test it using existing `platformio.ini`. +# + +# language: python +# python: +# - "2.7" +# +# sudo: false +# cache: +# directories: +# - "~/.platformio" +# +# install: +# - pip install -U platformio +# - platformio update +# +# script: +# - platformio run + + +# +# Template #2: The project is intended to be used as a library with examples. +# + +# language: python +# python: +# - "2.7" +# +# sudo: false +# cache: +# directories: +# - "~/.platformio" +# +# env: +# - PLATFORMIO_CI_SRC=path/to/test/file.c +# - PLATFORMIO_CI_SRC=examples/file.ino +# - PLATFORMIO_CI_SRC=path/to/test/directory +# +# install: +# - pip install -U platformio +# - platformio update +# +# script: +# - platformio ci --lib="." --board=ID_1 --board=ID_2 --board=ID_N diff --git a/examples/anymcu-header/README.rst b/examples/anymcu-header/README.rst new file mode 100644 index 0000000..c52e16d --- /dev/null +++ b/examples/anymcu-header/README.rst @@ -0,0 +1,38 @@ +.. Copyright 2014-present PlatformIO + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +How to build PlatformIO based project +===================================== + +1. `Install PlatformIO Core `_ +2. Download `development platform with examples `_ +3. Extract ZIP archive +4. Run these commands: + +.. code-block:: bash + + # Change directory to example + > cd platform-intel_mcs51/examples/stc-header + + # Build project + > platformio run + + # Upload firmware + > platformio run --target upload + + # Build specific environment + > platformio run -e stc15w408as + + # Upload firmware for the specific environment + > platformio run -e stc15w408as --target upload + + # Clean build files + > platformio run --target clean diff --git a/examples/anymcu-header/include/README b/examples/anymcu-header/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/anymcu-header/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/anymcu-header/lib/README b/examples/anymcu-header/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/anymcu-header/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/anymcu-header/platformio.ini b/examples/anymcu-header/platformio.ini new file mode 100644 index 0000000..e24ecd8 --- /dev/null +++ b/examples/anymcu-header/platformio.ini @@ -0,0 +1,25 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env:stc15f204ea] +platform = intel_mcs51 +board = STC15F204EA + +[env:stc15w204s] +platform = intel_mcs51 +board = STC15W204S + +[env:stc15w404as] +platform = intel_mcs51 +board = STC15W404AS + +[env:stc15w408as] +platform = intel_mcs51 +board = STC15W408AS diff --git a/examples/anymcu-header/src/Generic8051.h b/examples/anymcu-header/src/Generic8051.h new file mode 100644 index 0000000..75dd3ba --- /dev/null +++ b/examples/anymcu-header/src/Generic8051.h @@ -0,0 +1,217 @@ +#ifndef Generic8051_H +#define Generic8051_H +#include + +// Includes extra compatibility enhancements over original 8051.h +// Suitable for use with the original basic 8051 series MCU. +// This header file was verified against the MCS-51 manual. +// After this file is included you don't have to include "reg51.h". +// Comments beginning with //- indicate 8051. +// Comments begining with //= indicate defacto standard aliases. +// X means undefined, U means unchanged, C means config dependent. + +//SFR DECLARATION NOTE POR RESET VALUE DESCRIPTION +#define _P0 0x80 + SFR(P0, _P0); //- 1111'1111 Port 0 + SBIT( P0_0, _P0, 0); //- + SBIT( P00, _P0, 0); //= + SBIT( P0_1, _P0, 1); //- + SBIT( P01, _P0, 1); //= + SBIT( P0_2, _P0, 2); //- + SBIT( P02, _P0, 2); //= + SBIT( P0_3, _P0, 3); //- + SBIT( P03, _P0, 3); //= + SBIT( P0_4, _P0, 4); //- + SBIT( P04, _P0, 4); //= + SBIT( P0_5, _P0, 5); //- + SBIT( P05, _P0, 5); //= + SBIT( P0_6, _P0, 6); //- + SBIT( P06, _P0, 6); //= + SBIT( P0_7, _P0, 7); //- + SBIT( P07, _P0, 7); //= + +#define _SP 0x81 + SFR(SP, _SP); //- 0000'0111 Stack pointer + +#define _DPL 0x82 + SFR(DPL, _DPL); //- 0000'0000 Data pointer low byte + +#define _DPH 0x83 + SFR(DPH, _DPH); //- 0000'0000 Data pointer high byte + +#define _PCON 0x87 + SFR(PCON, _PCON); //- 0XXX'0000 Power Control + #define IDL 0x01 //- + #define PD 0x02 //- + #define GF0 0x04 //- + #define GF1 0x08 //- + #define SMOD 0x80 //- + +#define _TCON 0x88 + SFR(TCON, _TCON); //- 0000'0000 Timer/Counter Control + SBIT(IT0, _TCON, 0); //- + SBIT(IE0, _TCON, 1); //- + SBIT(IT1, _TCON, 2); //- + SBIT(IE1, _TCON, 3); //- + SBIT(TR0, _TCON, 4); //- + SBIT(TF0, _TCON, 5); //- + SBIT(TR1, _TCON, 6); //- + SBIT(TF1, _TCON, 7); //- + +#define _TMOD 0x89 + SFR(TMOD, _TMOD); //- 0000'0000 Timer/Counter Mode Control + #define T0_M0 0x01 //- + #define T0_M1 0x02 //- + #define T0_CT 0x04 //- + #define T0_GATE 0x08 //- + #define T1_M0 0x10 //- + #define T1_M1 0x20 //- + #define T1_CT 0x40 //- + #define T1_GATE 0x80 //- + +#define _TL0 0x8A + SFR(TL0, _TL0); //- 0000'0000 Timer/Counter 0 Low Byte + +#define _TL1 0x8B + SFR(TL1, _TL1); //- 0000'0000 Timer/Counter 1 Low Byte + +#define _TH0 0x8C + SFR(TH0, _TH0); //- 0000'0000 Timer/Counter 0 High Byte + +#define _TH1 0x8D + SFR(TH1, _TH1); //- 0000'0000 Timer/Counter 1 High Byte + +#define _P1 0x90 + SFR(P1, _P1); //- 1111'1111 Port 1 + SBIT( P1_0, _P1, 0); //- + SBIT( P10, _P1, 0); //= + SBIT( P1_1, _P1, 1); //- + SBIT( P11, _P1, 1); //= + SBIT( P1_2, _P1, 2); //- + SBIT( P12, _P1, 2); //= + SBIT( P1_3, _P1, 3); //- + SBIT( P13, _P1, 3); //= + SBIT( P1_4, _P1, 4); //- + SBIT( P14, _P1, 4); //= + SBIT( P1_5, _P1, 5); //- + SBIT( P15, _P1, 5); //= + SBIT( P1_6, _P1, 6); //- + SBIT( P16, _P1, 6); //= + SBIT( P1_7, _P1, 7); //- + SBIT( P17, _P1, 7); //= + +#define _SCON 0x98 + SFR(SCON, _SCON); //- 0000'0000 Serial Port 0 Control + SBIT( RI, _SCON, 0); //- + SBIT( TI, _SCON, 1); //- + SBIT( RB8, _SCON, 2); //- + SBIT( TB8, _SCON, 3); //- + SBIT( REN, _SCON, 4); //- + SBIT( SM2, _SCON, 5); //- + SBIT( SM1, _SCON, 6); //- + SBIT( SM0, _SCON, 7); //- + +#define _SBUF 0x99 + SFR(SBUF, _SBUF); //- XXXX'XXXX Serial Port 0 Data Buffer + +#define _P2 0xA0 + SFR(P2, _P2); //- 1111'1111 Port 2 + SBIT( P2_0, _P2, 0); //- + SBIT( P20, _P2, 0); //= + SBIT( P2_1, _P2, 1); //- + SBIT( P2_2, _P2, 2); //- + SBIT( P2_3, _P2, 3); //- + SBIT( P2_4, _P2, 4); //- + SBIT( P2_5, _P2, 5); //- + SBIT( P2_6, _P2, 6); //- + SBIT( P2_7, _P2, 7); //- + +#define _IE 0xA8 + SFR(IE, _IE); //- 0XX0'0000 Interrupt Enable (8051) + SBIT(EX0, _IE, 0); //- + SBIT(ET0, _IE, 1); //- + SBIT(EX1, _IE, 2); //- + SBIT(ET1, _IE, 3); //- + SBIT(ES, _IE, 4); //- + SBIT(ET2, _IE, 5); //- + SBIT(EA, _IE, 7); //- + +#define _P3 0xB0 + SFR(P3, _P3); //- 1111'1111 Port 3 + SBIT( P3_0, _P3, 0); //- + SBIT( P30, _P3, 0); //= + SBIT( RXD, _P3, 0); //- + SBIT( P3_1, _P3, 1); //- + SBIT( P31, _P3, 1); //= + SBIT( TXD, _P3, 1); //- + SBIT( P3_2, _P3, 2); //= + SBIT( P32, _P3, 2); //= + SBIT( INT0, _P3, 2); //- + SBIT( P3_3, _P3, 3); //- + SBIT( P33, _P3, 3); //- + SBIT( INT1, _P3, 3); //- + SBIT( P3_4, _P3, 4); //- + SBIT( P34, _P3, 4); //- + SBIT( T0, _P3, 4); //- + SBIT( P3_5, _P3, 5); //- + SBIT( P35, _P3, 5); //- + SBIT( T1, _P3, 5); //- + SBIT( P3_6, _P3, 6); //- + SBIT( P36, _P3, 6); //- + SBIT( WR, _P3, 6); //- + SBIT( P3_7, _P3, 7); //- + SBIT( P37, _P3, 7); //- + SBIT( RD, _P3, 7); //- + +#define _IP 0xB8 + SFR(IP, _IP); //- XXX0'0000 Interrupt priority (8051) + SBIT(PX0, _IP, 0); //- + SBIT(PT0, _IP, 1); //- + SBIT(PX1, _IP, 2); //- + SBIT(PT1, _IP, 3); //- + SBIT(PS, _IP, 4); //- + SBIT(PT2, _IP, 5); //- + +#define _PSW 0xD0 //- 0000'0000 Program status word + SFR(PSW, _PSW); //- + SBIT( P, _PSW, 0); //- + SBIT( F1, _PSW, 1); //- + SBIT( OV, _PSW, 2); //- + SBIT( RS0, _PSW, 3); //- + SBIT( RS1, _PSW, 4); //- + SBIT( F0, _PSW, 5); //- + SBIT( AC, _PSW, 6); //- + SBIT( CY, _PSW, 7); //- + +#define _ACC 0xE0 + SFR(ACC, _ACC); //- 0000'0000 Accumulator + SBIT( ACC_0, _ACC, 0); //- + SBIT( ACC_1, _ACC, 1); //- + SBIT( ACC_2, _ACC, 2); //- + SBIT( ACC_3, _ACC, 3); //- + SBIT( ACC_4, _ACC, 4); //- + SBIT( ACC_5, _ACC, 5); //- + SBIT( ACC_6, _ACC, 6); //- + SBIT( ACC_7, _ACC, 7); //- + +#define _B 0xF0 + SFR(B, _B); //- 0000'0000 B register + SBIT( B_0, _B, 0); //- + SBIT( B_1, _B, 1); //- + SBIT( B_2, _B, 2); //- + SBIT( B_3, _B, 3); //- + SBIT( B_4, _B, 4); //- + SBIT( B_5, _B, 5); //- + SBIT( B_6, _B, 6); //- + SBIT( B_7, _B, 7); //- + +//Reset vector absolute address declaration + #define RST_VECTOR 0x00 //- 0x00 Reset Vector +//Interrupt numbers: Address = ( Number * 8 ) + 3 + #define EX0_VECTOR 0 //- 0x03 External Interrupt 0 + #define ET0_VECTOR 1 //- 0x0B Timer 0 + #define EX1_VECTOR 2 //- 0x13 External Interrupt 1 + #define ET1_VECTOR 3 //- 0x1B Timer 1 + #define ES_VECTOR 4 //- 0x23 Serial Port 0 + +#endif \ No newline at end of file diff --git a/examples/anymcu-header/src/Generic8052.h b/examples/anymcu-header/src/Generic8052.h new file mode 100644 index 0000000..b737d0e --- /dev/null +++ b/examples/anymcu-header/src/Generic8052.h @@ -0,0 +1,246 @@ +#ifndef Generic8052_H +#define Generic8052_H +#include + +// Includes extra compatibility enhancements over original 8052.h +// Suitable for use with the original basic 8052 series MCU. +// This header file was verified against the MCS-51 manual. +// After this file is included you don't have to include "reg51.h". +// Comments beginning with //- indicate 8051 and //+ indicate 8052. +// Comments begining with //= indicate defacto standard aliases. +// X means undefined, U means unchanged, C means config dependent. + +//SFR DECLARATION NOTE POR RESET VALUE DESCRIPTION +#define _P0 0x80 + SFR(P0, _P0); //- 1111'1111 Port 0 + SBIT( P0_0, _P0, 0); //- + SBIT( P00, _P0, 0); //= + SBIT( P0_1, _P0, 1); //- + SBIT( P01, _P0, 1); //= + SBIT( P0_2, _P0, 2); //- + SBIT( P02, _P0, 2); //= + SBIT( P0_3, _P0, 3); //- + SBIT( P03, _P0, 3); //= + SBIT( P0_4, _P0, 4); //- + SBIT( P04, _P0, 4); //= + SBIT( P0_5, _P0, 5); //- + SBIT( P05, _P0, 5); //= + SBIT( P0_6, _P0, 6); //- + SBIT( P06, _P0, 6); //= + SBIT( P0_7, _P0, 7); //- + SBIT( P07, _P0, 7); //= + +#define _SP 0x81 + SFR(SP, _SP); //- 0000'0111 Stack pointer + +#define _DPL 0x82 + SFR(DPL, _DPL); //- 0000'0000 Data pointer low byte + +#define _DPH 0x83 + SFR(DPH, _DPH); //- 0000'0000 Data pointer high byte + +#define _PCON 0x87 + SFR(PCON, _PCON); //- 0XXX'0000 Power Control + #define IDL 0x01 //- + #define PD 0x02 //- + #define GF0 0x04 //- + #define GF1 0x08 //- + #define SMOD 0x80 //- + +#define _TCON 0x88 + SFR(TCON, _TCON); //- 0000'0000 Timer/Counter Control + SBIT(IT0, _TCON, 0); //- + SBIT(IE0, _TCON, 1); //- + SBIT(IT1, _TCON, 2); //- + SBIT(IE1, _TCON, 3); //- + SBIT(TR0, _TCON, 4); //- + SBIT(TF0, _TCON, 5); //- + SBIT(TR1, _TCON, 6); //- + SBIT(TF1, _TCON, 7); //- + +#define _TMOD 0x89 + SFR(TMOD, _TMOD); //- 0000'0000 Timer/Counter Mode Control + #define T0_M0 0x01 //- + #define T0_M1 0x02 //- + #define T0_CT 0x04 //- + #define T0_GATE 0x08 //- + #define T1_M0 0x10 //- + #define T1_M1 0x20 //- + #define T1_CT 0x40 //- + #define T1_GATE 0x80 //- + +#define _TL0 0x8A + SFR(TL0, _TL0); //- 0000'0000 Timer/Counter 0 Low Byte + +#define _TL1 0x8B + SFR(TL1, _TL1); //- 0000'0000 Timer/Counter 1 Low Byte + +#define _TH0 0x8C + SFR(TH0, _TH0); //- 0000'0000 Timer/Counter 0 High Byte + +#define _TH1 0x8D + SFR(TH1, _TH1); //- 0000'0000 Timer/Counter 1 High Byte + +#define _P1 0x90 + SFR(P1, _P1); //- 1111'1111 Port 1 + SBIT( P1_0, _P1, 0); //- + SBIT( P10, _P1, 0); //= + SBIT( T2, _P1, 0); //+ + SBIT( P1_1, _P1, 1); //- + SBIT( P11, _P1, 1); //= + SBIT( T2EX, _P1, 1); //+ + SBIT( P1_2, _P1, 2); //- + SBIT( P12, _P1, 2); //= + SBIT( P1_3, _P1, 3); //- + SBIT( P13, _P1, 3); //= + SBIT( P1_4, _P1, 4); //- + SBIT( P14, _P1, 4); //= + SBIT( P1_5, _P1, 5); //- + SBIT( P15, _P1, 5); //= + SBIT( P1_6, _P1, 6); //- + SBIT( P16, _P1, 6); //= + SBIT( P1_7, _P1, 7); //- + SBIT( P17, _P1, 7); //= + +#define _SCON 0x98 + SFR(SCON, _SCON); //- 0000'0000 Serial Port 0 Control + SBIT( RI, _SCON, 0); //- + SBIT( TI, _SCON, 1); //- + SBIT( RB8, _SCON, 2); //- + SBIT( TB8, _SCON, 3); //- + SBIT( REN, _SCON, 4); //- + SBIT( SM2, _SCON, 5); //- + SBIT( SM1, _SCON, 6); //- + SBIT( SM0, _SCON, 7); //- + +#define _SBUF 0x99 + SFR(SBUF, _SBUF); //- XXXX'XXXX Serial Port 0 Data Buffer + +#define _P2 0xA0 + SFR(P2, _P2); //- 1111'1111 Port 2 + SBIT( P2_0, _P2, 0); //- + SBIT( P20, _P2, 0); //= + SBIT( P2_1, _P2, 1); //- + SBIT( P2_2, _P2, 2); //- + SBIT( P2_3, _P2, 3); //- + SBIT( P2_4, _P2, 4); //- + SBIT( P2_5, _P2, 5); //- + SBIT( P2_6, _P2, 6); //- + SBIT( P2_7, _P2, 7); //- + +#define _IE 0xA8 +//SFR(IE, _IE); //- 0XX0'0000 Interrupt Enable (8051) + SFR(IE, _IE); //+ 0X00'0000 Interrupt Enable (8052) + SBIT(EX0, _IE, 0); //- + SBIT(ET0, _IE, 1); //- + SBIT(EX1, _IE, 2); //- + SBIT(ET1, _IE, 3); //- + SBIT(ES, _IE, 4); //- + SBIT(ET2, _IE, 5); //- + SBIT(EA, _IE, 7); //- + +#define _P3 0xB0 + SFR(P3, _P3); //- 1111'1111 Port 3 + SBIT( P3_0, _P3, 0); //- + SBIT( P30, _P3, 0); //= + SBIT( RXD, _P3, 0); //- + SBIT( P3_1, _P3, 1); //- + SBIT( P31, _P3, 1); //= + SBIT( TXD, _P3, 1); //- + SBIT( P3_2, _P3, 2); //= + SBIT( P32, _P3, 2); //= + SBIT( INT0, _P3, 2); //- + SBIT( P3_3, _P3, 3); //- + SBIT( P33, _P3, 3); //- + SBIT( INT1, _P3, 3); //- + SBIT( P3_4, _P3, 4); //- + SBIT( P34, _P3, 4); //- + SBIT( T0, _P3, 4); //- + SBIT( P3_5, _P3, 5); //- + SBIT( P35, _P3, 5); //- + SBIT( T1, _P3, 5); //- + SBIT( P3_6, _P3, 6); //- + SBIT( P36, _P3, 6); //- + SBIT( WR, _P3, 6); //- + SBIT( P3_7, _P3, 7); //- + SBIT( P37, _P3, 7); //- + SBIT( RD, _P3, 7); //- + +#define _IP 0xB8 +//SFR(IP, _IP); //- XXX0'0000 Interrupt priority (8051) + SFR(IP, _IP); //+ XX00'0000 Interrupt priority (8052) + SBIT(PX0, _IP, 0); //- + SBIT(PT0, _IP, 1); //- + SBIT(PX1, _IP, 2); //- + SBIT(PT1, _IP, 3); //- + SBIT(PS, _IP, 4); //- + SBIT(PT2, _IP, 5); //- + +#define _T2CON 0xC8 + SFR(T2CON, _T2CON); //+ 0000'0000 Timer/Counter 2 Control + SBIT( CM_RL2, _T2CON, 0); //+ + SBIT( CP_RL2, _T2CON, 0); //+ + SBIT( C_T2, _T2CON, 1); //+ + SBIT( TR2, _T2CON, 2); //+ + SBIT( EXEN2, _T2CON, 3); //+ + SBIT( TCLK, _T2CON, 4); //+ + SBIT( RCLK, _T2CON, 5); //+ + SBIT( EXF2, _T2CON, 6); //+ + SBIT(TF2, _T2CON, 7); //+ + +#define _RCAP2L 0xCA + SFR(RCAP2L, _RCAP2L); //+ 0000'0000 T/C 2 Capture Reg. Low byte + +#define _RCAP2H 0xCB + SFR(RCAP2H, _RCAP2H); //+ 0000'0000 T/C 2 Capture Reg. High byte + +#define _TL2 0xCC + SFR(TL2, _TL2); //+ 0000'0000 Timer/Counter 2 Low Byte + +#define _TH2 0xCD + SFR(TH2, _TH2); //+ 0000'0000 Timer/Counter 2 High Byte + +#define _PSW 0xD0 //- 0000'0000 Program status word + SFR(PSW, _PSW); //- + SBIT( P, _PSW, 0); //- + SBIT( F1, _PSW, 1); //- + SBIT( OV, _PSW, 2); //- + SBIT( RS0, _PSW, 3); //- + SBIT( RS1, _PSW, 4); //- + SBIT( F0, _PSW, 5); //- + SBIT( AC, _PSW, 6); //- + SBIT( CY, _PSW, 7); //- + +#define _ACC 0xE0 + SFR(ACC, _ACC); //- 0000'0000 Accumulator + SBIT( ACC_0, _ACC, 0); //- + SBIT( ACC_1, _ACC, 1); //- + SBIT( ACC_2, _ACC, 2); //- + SBIT( ACC_3, _ACC, 3); //- + SBIT( ACC_4, _ACC, 4); //- + SBIT( ACC_5, _ACC, 5); //- + SBIT( ACC_6, _ACC, 6); //- + SBIT( ACC_7, _ACC, 7); //- + +#define _B 0xF0 + SFR(B, _B); //- 0000'0000 B register + SBIT( B_0, _B, 0); //- + SBIT( B_1, _B, 1); //- + SBIT( B_2, _B, 2); //- + SBIT( B_3, _B, 3); //- + SBIT( B_4, _B, 4); //- + SBIT( B_5, _B, 5); //- + SBIT( B_6, _B, 6); //- + SBIT( B_7, _B, 7); //- + +//Reset vector absolute address declaration +#define RST_VECTOR 0x00 //- 0x00 Reset Vector +//Interrupt numbers: Address = ( Number * 8 ) + 3 +#define EX0_VECTOR 0 //- 0x03 External Interrupt 0 +#define ET0_VECTOR 1 //- 0x0B Timer 0 +#define EX1_VECTOR 2 //- 0x13 External Interrupt 1 +#define ET1_VECTOR 3 //- 0x1B Timer 1 +#define ES_VECTOR 4 //- 0x23 Serial Port 0 +#define ET2_VECTOR 5 //+ 0x2B Timer 2 + +#endif \ No newline at end of file diff --git a/examples/anymcu-header/src/N76E003.h b/examples/anymcu-header/src/N76E003.h new file mode 100644 index 0000000..a44d997 --- /dev/null +++ b/examples/anymcu-header/src/N76E003.h @@ -0,0 +1,968 @@ +#ifndef N76E003_H +#define N76E003_H +#include + +// Suitable for use with all N76E003 series MCU. +// This header file was verified against the official Nuvoton BSP +// however it corrects a number of Nuvoton BSP inconsistencies. +// After this file is included you don't have to include "reg51.h". +// Comments begining with /// indicate non 8051/8052 extensions. +// Comments beginning with //- indicate 8051 and //+ indicate 8052. +// Comments begining with //= indicate defacto standard aliases. +// X means undefined, U means unchanged, C means config dependent. + +//SFR DEFINITION | NOTE | POR RESET VALUE | DESCRIPTION +#define _P0 0x80 + SFR(P0, _P0); //- 1111'1111 Port 0 + SBIT( P0_0, _P0, 0); //- + SBIT( P00, _P0, 0); //= + SBIT( MOSI, _P0, 0); /// + SBIT( T1, _P0, 0); /// + SBIT( P0_1, _P0, 1); //- + SBIT( P01, _P0, 1); //= + SBIT( MISO, _P0, 1); /// + SBIT( P0_2, _P0, 2); //- + SBIT( P02, _P0, 2); //= + SBIT( RXD_1, _P0, 2); /// + SBIT( P0_3, _P0, 3); //- + SBIT( P03, _P0, 3); //= + SBIT( P0_4, _P0, 4); //- + SBIT( P04, _P0, 4); //= + SBIT( P0_5, _P0, 5); //- + SBIT( P05, _P0, 5); //= + SBIT( T0, _P0, 5); /// + SBIT( P0_6, _P0, 6); //- + SBIT( P06, _P0, 6); //= + SBIT( P0_7, _P0, 7); //- + SBIT( P07, _P0, 7); //= + +#define _SP 0x81 + SFR(SP, _SP); //- 0000'0111 Stack pointer + +#define _DPL 0x82 + SFR(DPL, _DPL); //- 0000'0000 Data pointer low byte + +#define _DPH 0x83 + SFR(DPH, _DPH); //- 0000'0000 Data pointer high byte + +#define _RCTRIM0 0x84 + SFR(RCTRIM0, _RCTRIM0); /// 0000'0000 Internal RC trim value high byte + +#define _RCTRIM1 0x85 + SFR(RCTRIM1, _RCTRIM1); /// 0000'0000 Internal RC trim value low byte + +#define _RWK 0x86 + SFR(RWK, _RWK); /// 0000'0000 Self wake-up timer reload byte + +#define _PCON 0x87 +//SFR(PCON, _PCON); //- 0XXX'0000 Power Control (8051) + SFR(PCON, _PCON); /// 0001'0000 Power Control (N76E003) + #define IDL 0x01 //- + #define PD 0x02 //- + #define GF0 0x04 //- + #define GF1 0x08 //- + #define POF 0x10 /// + #define SMOD0 0x40 /// + #define SMOD 0x80 //- + +#define _TCON 0x88 + SFR(TCON, _TCON); //- 0000'0000 Timer/Counter Control + SBIT(IT0, _TCON, 0); //- + SBIT(IE0, _TCON, 1); //- + SBIT(IT1, _TCON, 2); //- + SBIT(IE1, _TCON, 3); //- + SBIT(TR0, _TCON, 4); //- + SBIT(TF0, _TCON, 5); //- + SBIT(TR1, _TCON, 6); //- + SBIT(TF1, _TCON, 7); //- + +#define _TMOD 0x89 + SFR(TMOD, _TMOD); //- 0000'0000 Timer/Counter Mode Control + #define T0_M0 0x01 //- + #define T0_M1 0x02 //- + #define T0_CT 0x04 //- + #define T0_GATE 0x08 //- + #define T1_M0 0x10 //- + #define T1_M1 0x20 //- + #define T1_CT 0x40 //- + #define T1_GATE 0x80 //- + +#define _TL0 0x8A + SFR(TL0, _TL0); //- 0000'0000 Timer/Counter 0 Low Byte + +#define _TL1 0x8B + SFR(TL1, _TL1); //- 0000'0000 Timer/Counter 1 Low Byte + +#define _TH0 0x8C + SFR(TH0, _TH0); //- 0000'0000 Timer/Counter 0 High Byte + +#define _TH1 0x8D + SFR(TH1, _TH1); //- 0000'0000 Timer/Counter 1 High Byte + +#define _CKCON 0x8E + SFR(CKCON, _CKCON); /// 0000'0000 Clock control + #define CLOEN 0x02 /// + #define T0M 0x08 /// + #define T1M 0x10 /// + #define PWMCKS 0x40 /// + +#define _WKCON 0x8F + SFR(WKCON, _WKCON); /// 0000'0000 Self wake-up timer control + #define WKPS 0x07 /// + #define WKTR 0x08 /// + #define WKTF 0x10 /// + +#define _P1 0x90 + SFR(P1, _P1); //- 1111'1111 Port 1 + SBIT( P1_0, _P1, 0); //- + SBIT( P10, _P1, 0); //= +//SBIT( T2, _P1, 0); //+ Software defined on N76E003 + SBIT( SPCLK, _P1, 0); /// + SBIT( P1_1, _P1, 1); //- + SBIT( P11, _P1, 1); //= +//SBIT( T2EX, _P1, 1); //+ Software defined on N76E003 + SBIT( P1_2, _P1, 2); //- + SBIT( P12, _P1, 2); //= + SBIT( P1_3, _P1, 3); //- + SBIT( P13, _P1, 3); //= + SBIT( P1_4, _P1, 4); //- + SBIT( P14, _P1, 4); //= + SBIT( FB, _P1, 4); /// + SBIT( P1_5, _P1, 5); //- + SBIT( P15, _P1, 5); //= + SBIT( SS, _P1, 5); /// + SBIT( P1_6, _P1, 6); //- + SBIT( P16, _P1, 6); //= + SBIT( TXD_1, _P1, 6); /// + SBIT( P1_7, _P1, 7); //- + SBIT( INT1, _P1, 7); /// + SBIT( P17, _P1, 7); //= + +#define _SFRS 0x91 + SFR(SFRS, _SFRS); /// TA 0000'0000 SFR page selection + #define SFRPAGE 0x01 /// + +#define _CAPCON0 0x92 + SFR(CAPCON0, _CAPCON0); /// 0000'0000 Input capture control 0 + #define CAPF0 0x01 /// + #define CAPF1 0x02 /// + #define CAPF2 0x04 /// + #define CAPEN0 0x10 /// + #define CAPEN1 0x20 /// + #define CAPEN2 0x40 /// + +#define _CAPCON1 0x93 + SFR(CAPCON1, _CAPCON1); /// 0000'0000 Input capture control 1 + #define CAP0LS 0x03 /// + #define CAP1LS 0x0C /// + #define CAP2LS 0x30 /// + +#define _CAPCON2 0x94 + SFR(CAPCON2, _CAPCON2); /// 0000'0000 Input capture control 2 + #define ENF0 0x10 /// + #define ENF1 0x20 /// + #define ENF2 0x40 /// + +#define _CKDIV 0x95 + SFR(CKDIV, _CKDIV); /// 0000'0000 Clock divider + +#define _CKSWT 0x96 + SFR(CKSWT, _CKSWT); /// TA 0011'0000 Clock switch + #define OSC 0x06 /// + #define ECLKST 0x08 /// + #define LIRCST 0x10 /// + #define HIRCST 0x20 /// + +#define _CKEN 0x97 + SFR(CKEN, _CKEN); /// TA 0011'0000 Clock enable + #define CKSWTF 0x01 /// + #define HIRCEN 0x20 /// + #define EXTEN 0xC0 /// + +#define _SCON 0x98 + SFR(SCON, _SCON); //- 0000'0000 Serial Port 0 Control + SBIT( RI, _SCON, 0); //- + SBIT( TI, _SCON, 1); //- + SBIT( RB8, _SCON, 2); //- + SBIT( TB8, _SCON, 3); //- + SBIT( REN, _SCON, 4); //- + SBIT( SM2, _SCON, 5); //- + SBIT( SM1, _SCON, 6); //- +//SBIT( SM0, _SCON, 7); //- (8051) + SBIT( SM0, _SCON, 7); /// Write (N76E003) + SBIT( FE, _SCON, 7); /// Read + +#define _SBUF 0x99 +//SFR(SBUF, _SBUF); //- XXXX'XXXX Serial Port 0 Data Buffer (8051) + SFR(SBUF, _SBUF); /// 0000'0000 Serial Port 0 Data Buffer (N76E003) + +#define _SBUF_1 0x9A + SFR(SBUF_1, _SBUF_1); /// 0000'0000 Serial port 1 data buffer + +#define _EIE 0x9B + SFR(EIE, _EIE); /// 0000'0000 Extensive interrupt enable + #define EI2C 0x01 /// + #define EPI 0x02 /// + #define ECAP 0x04 /// + #define EPWM 0x08 /// + #define EWDT 0x10 /// + #define EFB 0x20 /// + #define ESPI 0x40 /// + #define ET2 0x80 /// + +#define _EIE1 0x9C + SFR(EIE1, _EIE1); /// 0000'0000 Extensive interrupt enable 1 + #define EX_1 0x01 /// + #define ET3 0x02 /// + #define EWKT 0x04 /// + +#define _CHPCON 0x9F + SFR(CHPCON, _CHPCON); /// TA 0000'00C0 Chip control + #define IAPEN 0x01 /// + #define BS 0x02 /// + #define IAPFF 0x40 /// + #define SWRST 0x80 /// + +#define _P2 0xA0 +//SFR(P2, _P2); //- 1111'1111 Port 2 (8051) + SFR(P2, _P2); /// 0000'000X Port 2 (N76E003) + SBIT( P2_0, _P2, 0); //- + SBIT( P20, _P2, 0); //= + SBIT( RST, _P2, 0); /// +//SBIT( P2_1, _P2, 1); //- Not available on N76E003 +//SBIT( P2_2, _P2, 2); //- Not available on N76E003 +//SBIT( P2_3, _P2, 3); //- Not available on N76E003 +//SBIT( P2_4, _P2, 4); //- Not available on N76E003 +//SBIT( P2_5, _P2, 5); //- Not available on N76E003 +//SBIT( P2_6, _P2, 6); //- Not available on N76E003 +//SBIT( P2_7, _P2, 7); //- Not available on N76E003 + +#define _AUXR1 0xA2 + SFR(AUXR1, _AUXR1); /// 0000'0000 Auxiliary register 1 + #define UART0PX 0x04 /// + #define GF2 0x08 /// + #define HardF 0x20 /// + #define RSTPINF 0x40 /// + #define SWRF 0x80 /// + +#define _BODCON0 0xA3 + SFR(BODCON0, _BODCON0); /// TA CCCC'XC0X Brown-out detection control 0 + #define BOS 0x01 /// + #define BORF 0x02 /// + #define BORST 0x04 /// + #define BOF 0x08 /// + #define BOV 0x30 /// + #define BODEN 0x80 /// + +#define _IAPTRG 0xA4 + SFR(IAPTRG, _IAPTRG); /// TA 0000'0000 IAP trigger + #define IAPGO 0x01 /// + +#define _IAPUEN 0xA5 + SFR(IAPUEN, _IAPUEN); /// TA 0000'0000 IAP update enable + #define APUEN 0x01 /// + #define LDUEN 0x02 /// + #define CFUEN 0x04 /// + +#define _IAPAL 0xA6 + SFR(IAPAL, _IAPAL); /// 0000'0000 IAP address low byte + +#define _IAPAH 0xA7 + SFR(IAPAH, _IAPAH); /// 0000'0000 IAP address high byte + +#define _IE 0xA8 +//SFR(IE, _IE); //- 0XX0'0000 Interrupt Enable (8051) +//SFR(IE, _IE); //+ 0X00'0000 Interrupt Enable (8052) + SFR(IE, _IE); /// 0000'0000 Interrupt Enable (N76E003) + SBIT(EX0, _IE, 0); //- + SBIT(ET0, _IE, 1); //- + SBIT(EX1, _IE, 2); //- + SBIT(ET1, _IE, 3); //- + SBIT(ES, _IE, 4); //- + SBIT(EBOD, _IE, 5); /// (N76E003) +//SBIT(ET2, _IE, 5); //- (8051) + SBIT(EADC, _IE, 6); /// + SBIT(EA, _IE, 7); //- + +#define _SADDR 0xA9 + SFR(SADDR, _SADDR); /// 0000'0000 Slave 0 address + +#define _WDCON 0xAA + SFR(WDCON, _WDCON); /// TA 0000'0111 Watchdog timer control + #define WDPS 0x07 /// + #define WDTRF 0x08 /// + #define WIDPD 0x10 /// + #define WDTF 0x20 /// + #define WDCLR 0x40 /// + #define WDTR 0x80 /// + +#define _BODCON1 0xAB + SFR(BODCON1, _BODCON1); /// TA 0000'0001 Brown-out detection control 1 + #define BODFLT 0x01 /// + #define LPBOD 0x06 /// + +#define _P3M1 0xAC + SFR(P3M1, _P3M1); /// 0000'0001 P3 mode select 1 + #define P3M1_0 0x01 /// + +#define _P3S 0xAC + SFR(P3S, _P3S); /// Page1 0000'0000 P3 Schmitt trigger input + #define P3S_0 0x01 /// + +#define _P3M2 0xAD + SFR(P3M2, _P3M2); /// 0000'0000 P3 mode select 2 + #define P3M2_0 0x01 /// + +#define _P3SR 0xAD + SFR(P3SR, _P3SR); /// Page1 0000'0000 P3 slew rate + #define P3SR_0 0x01 /// + +#define _IAPFD 0xAE + SFR(IAPFD, _IAPFD); /// 0000'0000 IAP flash data + +#define _IAPCN 0xAF + SFR(IAPCN, _IAPCN); /// 0011'0000 IAP control + #define FCTRL 0x0F /// + #define FCEN 0x10 /// + #define FOEN 0x20 /// + #define IAPB 0xC0 /// + +#define _P3 0xB0 +//SFR(P3, _P3); //- 1111'1111 Port 3 (8051) + SFR(P3, _P3); /// 0000'0001 Port 3 (N76E003) + SBIT( P3_0, _P3, 0); //- + SBIT( P30, _P3, 0); //= +//SBIT( RXD, _P3, 0); //- Software defined on N76E003 + SBIT( INT0, _P3, 0); /// + SBIT( XIN, _P3, 0); /// +//SBIT( P3_1, _P3, 1); //- Not available on N76E003 +//SBIT( P31, _P3, 1); //= Not available on N76E003 +//SBIT( TXD, _P3, 1); //- Software defined on N76E003 +//SBIT( P3_2, _P3, 2); //= Not available on N76E003 +//SBIT( P32, _P3, 2); //= Not available on N76E003 +//SBIT( INT0, _P3, 2); //- Mapped to P3.0 on N76E003 +//SBIT( P3_3, _P3, 3); //- Not available on N76E003 +//SBIT( P33, _P3, 3); //- Not available on N76E003 +//SBIT( INT1, _P3, 3); //- Mapped to P1.7 on N76E003 +//SBIT( P3_4, _P3, 4); //- Not available on N76E003 +//SBIT( P34, _P3, 4); //- Not available on N76E003 +//SBIT( T0, _P3, 4); //- Mapped to P0.5 on N76E003 +//SBIT( P3_5, _P3, 5); //- Not available on N76E003 +//SBIT( P35, _P3, 5); //- Not available on N76E003 +//SBIT( T1, _P3, 5); //- Mapped to P0.0 on N76E003 +//SBIT( P3_6, _P3, 6); //- Not available on N76E003 +//SBIT( P36, _P3, 6); //- Not available on N76E003 +//SBIT( WR, _P3, 6); //- Not available on N76E003 +//SBIT( P3_7, _P3, 7); //- Not available on N76E003 +//SBIT( P37, _P3, 7); //- Not available on N76E003 +//SBIT( RD, _P3, 7); //- Not available on N76E003 + +#define _P0M1 0xB1 + SFR(P0M1, _P0M1); /// 1111'1111 P0 mode select 1 + #define P0M1_0 0x01 /// + #define P0M1_1 0x02 /// + #define P0M1_2 0x04 /// + #define P0M1_3 0x08 /// + #define P0M1_4 0x10 /// + #define P0M1_5 0x20 /// + #define P0M1_6 0x40 /// + #define P0M1_7 0x80 /// + +#define _P0S 0xB1 + SFR(P0S, _P0S); /// Page1 0000'0000 P0 Schmitt trigger input + #define P0S1_0 0x01 /// + #define P0S1_1 0x02 /// + #define P0S1_2 0x04 /// + #define P0S1_3 0x08 /// + #define P0S1_4 0x10 /// + #define P0S1_5 0x20 /// + #define P0S1_6 0x40 /// + #define P0S1_7 0x80 /// + +#define _P0M2 0xB2 + SFR(P0M2, _P0M2); /// 0000'0000 P0 mode select 2 + #define P0M2_0 0x01 /// + #define P0M2_1 0x02 /// + #define P0M2_2 0x04 /// + #define P0M2_3 0x08 /// + #define P0M2_4 0x10 /// + #define P0M2_5 0x20 /// + #define P0M2_6 0x40 /// + #define P0M2_7 0x80 /// + +#define _P0SR 0xB2 + SFR(P0SR, _P0SR); /// Page1 0000'0000 P0 slew rate + #define P0SR1_0 0x01 /// + #define P0SR1_1 0x02 /// + #define P0SR1_2 0x04 /// + #define P0SR1_3 0x08 /// + #define P0SR1_4 0x10 /// + #define P0SR1_5 0x20 /// + #define P0SR1_6 0x40 /// + #define P0SR1_7 0x80 /// + +#define _P1M1 0xB3 + SFR(P1M1, _P1M1); /// 1111'1111 P1 mode select 1 + #define P1M1_0 0x01 /// + #define P1M1_1 0x02 /// + #define P1M1_2 0x04 /// + #define P1M1_3 0x08 /// + #define P1M1_4 0x10 /// + #define P1M1_5 0x20 /// + #define P1M1_6 0x40 /// + #define P1M1_7 0x80 /// + +#define _P1S 0xB3 + SFR(P1S, _P1S); /// Page1 0000'0000 P1 Schmitt trigger input + #define P1S1_0 0x01 /// + #define P1S1_1 0x02 /// + #define P1S1_2 0x04 /// + #define P1S1_3 0x08 /// + #define P1S1_4 0x10 /// + #define P1S1_5 0x20 /// + #define P1S1_6 0x40 /// + #define P1S1_7 0x80 /// + +#define _P1M2 0xB4 + SFR(P1M2, _P1M2); /// 0000'0000 P1 mode select 2 + #define P1M2_0 0x01 /// + #define P1M2_1 0x02 /// + #define P1M2_2 0x04 /// + #define P1M2_3 0x08 /// + #define P1M2_4 0x10 /// + #define P1M2_5 0x20 /// + #define P1M2_6 0x40 /// + #define P1M2_7 0x80 /// + +#define _P1SR 0xB4 + SFR(P1SR, _P1SR); /// Page1 0000'0000 P1 slew rate + #define P1SR1_0 0x01 /// + #define P1SR1_1 0x02 /// + #define P1SR1_2 0x04 /// + #define P1SR1_3 0x08 /// + #define P1SR1_4 0x10 /// + #define P1SR1_5 0x20 /// + #define P1SR1_6 0x40 /// + #define P1SR1_7 0x80 /// + +#define _P2S 0xB5 + SFR(P2S, _P2S); /// 0000'0000 P20 setting and Timer 0/1 output enable + #define P2S_0 0x01 /// + #define T0OE 0x04 /// + #define T1OE 0x08 /// + #define P20UP 0x80 /// + +#define _IPH 0xB7 + SFR(IPH, _IPH); /// 0000'0000 Interrupt priority high + #define PX0H 0x01 /// + #define PT0H 0x02 /// + #define PX1H 0x04 /// + #define PT1H 0x08 /// + #define PSH 0x10 /// + #define PBODH 0x20 /// + #define PADCH 0x40 /// + +#define _PWMINTC 0xB7 + SFR(PWMINTC, _PWMINTC); ///Page1 0000'0000 PWM interrupt control + #define INTSEL0 0x01 /// + #define INTSEL1 0x02 /// + #define INTSEL2 0x04 /// + #define INTTYP0 0x10 /// + #define INTTYP1 0x20 /// + +#define _IP 0xB8 +//SFR(IP, _IP); //- XXX0'0000 Interrupt priority (8051) +//SFR(IP, _IP); //+ XX00'0000 Interrupt priority (8052) + SFR(IP, _IP); /// 0000'0000 Interrupt priority (N76E003) + SBIT(PX0, _IP, 0); //- + SBIT(PT0, _IP, 1); //- + SBIT(PX1, _IP, 2); //- + SBIT(PT1, _IP, 3); //- + SBIT(PS, _IP, 4); //- + SBIT(PBOD, _IP, 5); /// (N76E003) +//SBIT(PT2, _IP, 5); //- (8051) + SBIT(PADC, _IP, 6); /// + +#define _SADEN 0xB9 + SFR(SADEN, _SADEN); /// 0000'0000 Slave 0 address mask + +#define _SADEN_1 0xBA + SFR(SADEN_1, _SADEN_1); /// 0000'0000 Slave 1 address mask + +#define _SADDR_1 0xBB + SFR(SADDR_1, _SADDR_1); /// 0000'0000 Slave 1 address + +#define _I2DAT 0xBC + SFR(I2DAT, _I2DAT); /// 0000'0000 I2C data + +#define _I2STAT 0xBD + SFR(I2STAT, _I2STAT); /// 1111'1000 I2C status + #define I2STAT 0xF8 /// + +#define _I2CLK 0xBE + SFR(I2CLK, _I2CLK); /// 0000'1001 I2C clock + +#define _I2TOC 0xBF + SFR(I2TOC, _I2TOC); /// 0000'0000 I2C time-out counter + #define I2TOF 0x01 /// + #define DIV 0x02 /// + #define I2TOCEN 0x04 /// + +#define _I2CON 0xC0 + SFR(I2CON, _I2CON); /// 0000'0000 I2C control + SBIT( I2CPX, _I2CON, 0); /// + SBIT( AA, _I2CON, 2); /// + SBIT( SI, _I2CON, 3); /// + SBIT( STO, _I2CON, 4); /// + SBIT( STA, _I2CON, 5); /// + SBIT( I2CEN, _I2CON, 6); /// + +#define _I2ADDR 0xC1 + SFR(I2ADDR, _I2ADDR); /// 0000'0000 I2C own slave address + #define GC 0x01 /// + #define I2ADDR 0xFE /// + +#define _ADCRL 0xC2 + SFR(ADCRL, _ADCRL); /// 0000'0000 ADC result low byte + +#define _ADCRH 0xC3 + SFR(ADCRH, _ADCRH); /// 0000'0000 ADC result high byte + +#define _T3CON 0xC4 + SFR(T3CON, _T3CON); /// 0000'0000 Timer 3 control + #define T3PS 0x07 /// + #define TR3 0x80 /// + #define TF3 0x10 /// + #define BRCK 0x20 /// + #define SMOD0_1 0x40 /// + #define SMOD_1 0x80 /// + +#define _PWM4H 0xC4 + SFR(PWM4H, _PWM4H); /// Page1 0000'0000 PWM4 duty high byte + +#define _RL3 0xC5 /// 0000'0000 Timer 3 reload low byte + SFR(RL3, _RL3); /// + +#define _PWM5H 0xC5 + SFR(PWM5H, _PWM5H); /// Page1 0000'0000 PWM5 duty high byte + +#define _RH3 0xC6 + SFR(RH3, _RH3); /// 0000'0000 Timer 3 reload high byte + +#define _PIOCON1 0xC6 + SFR(PIOCON1, _PIOCON1); /// Page1 0000'0000 PWM I/O switch 1 + #define PIO11 0x02 /// + #define PIO12 0x04 /// + #define PIO13 0x08 /// + #define PIO15 0x20 /// + +#define _TA 0xC7 + SFR(TA, _TA); /// 0000'0000 Timed access protection + +#define _T2CON 0xC8 + SFR(T2CON, _T2CON); //+ 0000'0000 Timer/Counter 2 Control + SBIT( CM_RL2, _T2CON, 0); //+ +//SBIT( CP_RL2, _T2CON, 0); //+ (8051) +//SBIT( C_T2, _T2CON, 1); //+ (8051) + SBIT( TR2, _T2CON, 2); //+ +//SBIT( EXEN2, _T2CON, 3); //+ (8051) +//SBIT( TCLK, _T2CON, 4); //+ (8051) +//SBIT( RCLK, _T2CON, 5); //+ (8051) +//SBIT( EXF2, _T2CON, 6); //+ (8051) + SBIT(TF2, _T2CON, 7); //+ + +#define _T2MOD 0xC9 + SFR(T2MOD, _T2MOD); /// 0000'0000 Timer 2 mode + #define LDTS 0x03 /// + #define CMPCR 0x04 /// + #define CAPCR 0x08 /// + #define T2DIV 0x70 /// + #define LDEN 0x80 /// + +#define _RCMP2L 0xCA + SFR(RCMP2L, _RCMP2L); /// 0000'0000 Timer 2 compare low byte (N76E003) + +//#define _RCAP2L 0xCA +//SFR(RCAP2L, _RCAP2L); //+ 0000'0000 T/C 2 Capture Reg. Low byte (8052) + +#define _RCMP2H 0xCB + SFR(RCMP2H, _RCMP2H); /// 0000'0000 Timer 2 compare high byte (N76E003) + +//#define _RCAP2H 0xCB +//SFR(RCAP2H, _RCAP2H); //+ 0000'0000 T/C 2 Capture Reg. High byte (8052) + +#define _TL2 0xCC + SFR(TL2, _TL2); //+ 0000'0000 Timer/Counter 2 Low Byte + +#define _PWM4L 0xCC + SFR(PWM4L, _PWM4L); /// Page1 0000'0000 PWM4 duty low byte + +#define _TH2 0xCD + SFR(TH2, _TH2); //+ 0000'0000 Timer/Counter 2 High Byte + +#define _PWM5L 0xCD + SFR(PWM5L, _PWM5L); ///Page1 0000'0000 PWM5 duty low byte + +#define _ADCMPL 0xCE + SFR(ADCMPL, _ADCMPL); /// 0000'0000 ADC compare low byte + +#define _ADCMPH 0xCF + SFR(ADCMPH, _ADCMPH); /// 0000'0000 ADC compare high byte + +#define _PSW 0xD0 //- 0000'0000 Program status word + SFR(PSW, _PSW); //- + SBIT( P, _PSW, 0); //- + SBIT( F1, _PSW, 1); //- + SBIT( OV, _PSW, 2); //- + SBIT( RS0, _PSW, 3); //- + SBIT( RS1, _PSW, 4); //- + SBIT( F0, _PSW, 5); //- + SBIT( AC, _PSW, 6); //- + SBIT( CY, _PSW, 7); //- + +#define _PWMPH 0xD1 + SFR(PWMPH, _PWMPH); /// 0000'0000 PWM period high byte + +#define _PWM0H 0xD2 + SFR(PWM0H, _PWM0H); /// 0000'0000 PWM0 duty high byte + +#define _PWM1H 0xD3 + SFR(PWM1H, _PWM1H); /// 0000'0000 PWM1 duty high byte + +#define _PWM2H 0xD4 + SFR(PWM2H, _PWM2H); /// 0000'0000 PWM2 duty high byte + +#define _PWM3H 0xD5 + SFR(PWM3H, _PWM3H); /// 0000'0000 PWM3 duty high byte + +#define _PNP 0xD6 + SFR(PNP, _PNP); /// 0000'0000 PWM negative polarity + #define PNP0 0x01 /// + #define PNP1 0x02 /// + #define PNP2 0x04 /// + #define PNP3 0x08 /// + #define PNP4 0x10 /// + #define PNP5 0x20 /// + +#define _FBD 0xD7 + SFR(FBD, _FBD); /// 0000'0000 Brake data + #define FBD0 0x01 /// + #define FBD1 0x02 /// + #define FBD2 0x04 /// + #define FBD3 0x08 /// + #define FBD4 0x10 /// + #define FBD5 0x20 /// + #define FBINLS 0x40 /// + #define FBF 0x80 /// + +#define _PWMCON0 0xD8 + SFR(PWMCON0, _PWMCON0); /// 0000'0000 PWM control 0 + SBIT( CLRPWM, _PWMCON0, 4); /// + SBIT( PWMF, _PWMCON0, 5); /// + SBIT( LOAD, _PWMCON0, 6); /// + SBIT( PWMRUN, _PWMCON0, 7); /// + +#define _PWMPL 0xD9 + SFR(PWMPL, _PWMPL); /// 0000'0000 PWM period low byte + +#define _PWM0L 0xDA + SFR(PWM0L, _PWM0L); /// 0000'0000 PWM0 duty low byte + +#define _PWM1L 0xDB + SFR(PWM1L, _PWM1L); /// 0000'0000 PWM1 duty low byte + +#define _PWM2L 0xDC + SFR(PWM2L, _PWM2L); /// 0000'0000 PWM2 duty low byte + +#define _PWM3L 0xDD + SFR(PWM3L, _PWM3L); /// 0000'0000 PWM3 duty low byte + +#define _PIOCON0 0xDE + SFR(PIOCON0, _PIOCON0); /// 0000'0000 PWM I/O switch 0 + #define PIO00 0x01 /// + #define PIO01 0x02 /// + #define PIO02 0x04 /// + #define PIO03 0x08 /// + #define PIO04 0x10 /// + #define PIO05 0x20 /// + +#define _PWMCON1 0xDF + SFR(PWMCON1, _PWMCON1); /// 0000'0000 PWM control 1 + #define PWMDIV 0x07 /// + #define FBINEN 0x08 /// + #define PWMTYP 0x10 /// + #define GP 0x20 /// + #define PWMMOD 0xC0 /// + +#define _ACC 0xE0 + SFR(ACC, _ACC); //- 0000'0000 Accumulator + SBIT( ACC_0, _ACC, 0); //- + SBIT( ACC_1, _ACC, 1); //- + SBIT( ACC_2, _ACC, 2); //- + SBIT( ACC_3, _ACC, 3); //- + SBIT( ACC_4, _ACC, 4); //- + SBIT( ACC_5, _ACC, 5); //- + SBIT( ACC_6, _ACC, 6); //- + SBIT( ACC_7, _ACC, 7); //- + +#define _ADCCON1 0xE1 + SFR(ADCCON1, _ADCCON1); /// 0000'0000 ADC control 1 + #define ADCEN 0x01 /// + #define ADCEX 0x02 /// + #define ETGTYP 0x0C /// + #define STADCPX 0x40 /// + +#define _ADCCON2 0xE2 + SFR(ADCCON2, _ADCCON2); /// 0000'0000 ADC control 2 + #define ADCDLY_8 0x01 /// + #define ADCMPO 0x10 /// + #define ADCMPEN 0x20 /// + #define ADCMPOP 0x40 /// + #define ADFBEN 0x80 /// + +#define _ADCDLY 0xE3 + SFR(ADCDLY, _ADCDLY); /// 0000'0000 ADC trigger delay + +#define _C0L 0xE4 + SFR(C0L, _C0L); /// 0000'0000 Input capture 0 low byte + +#define _C0H 0xE5 + SFR(C0H, _C0H); /// 0000'0000 Input capture 0 high byte + +#define _C1L 0xE6 + SFR(C1L, _C1L); /// 0000'0000 Input capture 1 low byte + +#define _C1H 0xE7 + SFR(C1H, _C1H); /// 0000'0000 Input capture 1 high byte + +#define _ADCCON0 0xE8 + SFR(ADCCON0, _ADCCON0); /// 0000'0000 ADC control 0 + SBIT( ADCHS0, _ADCCON0, 0); /// + SBIT( ADCHS1, _ADCCON0, 1); /// + SBIT( ADCHS2, _ADCCON0, 2); /// + SBIT( ADCHS3, _ADCCON0, 3); /// + SBIT( ETGSEL0, _ADCCON0, 4); /// + SBIT( ETGSEL1, _ADCCON0, 5); /// + SBIT( ADCS, _ADCCON0, 6); /// + SBIT( ADCF, _ADCCON0, 7); /// + +#define _PICON 0xE9 +SFR(PICON, _PICON); /// 0000'0000 Pin interrupt control + #define PIPS 0x03 /// + #define PITO 0x04 /// + #define PIT1 0x08 /// + #define PIT2 0x10 /// + #define PIT3 0x20 /// + #define PIT45 0x40 /// + #define PIT67 0x80 /// + +#define _PINEN 0xEA +SFR(PINEN, _PINEN); /// 0000'0000 Pin interrupt low level/falling edge enable + #define PINEN0 0x01 /// + #define PINEN1 0x02 /// + #define PINEN2 0x04 /// + #define PINEN3 0x08 /// + #define PINEN4 0x10 /// + #define PINEN5 0x20 /// + #define PIN3N6 0x40 /// + #define PINEN7 0x80 /// + +#define _PIPEN 0xEB +SFR(PIPEN, _PIPEN); /// 0000'0000 Pin interrupt high level/rising edge enable + #define PIPEN0 0x01 /// + #define PIPEN1 0x02 /// + #define PIPEN2 0x04 /// + #define PIPEN3 0x08 /// + #define PIPEN4 0x10 /// + #define PIPEN5 0x20 /// + #define PIP3N6 0x40 /// + #define PIPEN7 0x80 /// + +#define _PIF 0xEC + SFR(PIF, _PIF); /// 0000'0000 Pin interrupt flag + #define PIF0 0x01 /// + #define PIF1 0x02 /// + #define PIF2 0x04 /// + #define PIF3 0x08 /// + #define PIF4 0x10 /// + #define PIF5 0x20 /// + #define PIF6 0x40 /// + #define PIF7 0x80 /// + +#define _C2L 0xED + SFR(C2L, _C2L); /// 0000'0000 Input capture 2 low byte + +#define _C2H 0xEE + SFR(C2H, _C2H); /// 0000'0000 Input capture 2 high byte + +#define _EIP 0xEF + SFR(EIP, _EIP); /// 0000'0000 Extensive interrupt priority + #define PI2C 0x01 /// + #define PPI 0x02 /// + #define PCAP 0x04 /// + #define PPWM 0x08 /// + #define PWDT 0x10 /// + #define PFB 0x20 /// + #define PSPI 0x40 /// + #define PT2 0x80 /// + +#define _B 0xF0 + SFR(B, _B); //- 0000'0000 B register + SBIT( B_0, _B, 0); //- + SBIT( B_1, _B, 1); //- + SBIT( B_2, _B, 2); //- + SBIT( B_3, _B, 3); //- + SBIT( B_4, _B, 4); //- + SBIT( B_5, _B, 5); //- + SBIT( B_6, _B, 6); //- + SBIT( B_7, _B, 7); //- + +#define _CAPCON3 0xF1 + SFR(CAPCON3, _CAPCON3); /// 0000'0000 Input capture control 3 + #define CAP00 0x01 /// + #define CAP01 0x02 /// + #define CAP02 0x04 /// + #define CAP03 0x08 /// + #define CAP10 0x10 /// + #define CAP11 0x20 /// + #define CAP12 0x40 /// + #define CAP13 0x80 /// + +#define _CAPCON4 0xF2 + SFR(CAPCON4, _CAPCON4); /// 0000'0000 Input capture control 4 + #define CAP20 0x01 /// + #define CAP21 0x02 /// + #define CAP22 0x04 /// + #define CAP23 0x08 /// + +#define _SPCR 0xF3 + SFR(SPCR, _SPCR); /// 0000'0000 SPI control + #define SPR0 0x01 /// + #define SPR1 0x02 /// + #define CPHA 0x04 /// + #define CPOL 0x08 /// + #define MSTR 0x10 /// + #define LSBFE 0x20 /// + #define SPIEN 0x40 /// + #define SSOE 0x80 /// + +#define _SPCR2 0xF3 + SFR(SPCR2, _SPCR2); ///Page1 0000'0000 SPI control 2 + #define SPIS0 0x01 /// + #define SPIS1 0x02 /// + +#define _SPSR 0xF4 + SFR(SPSR, _SPSR); /// 0000'0000 SPI status + #define TXBUF 0x04 /// + #define DISMODF 0x08 /// + #define MODF 0x10 /// + #define SPIOVF 0x20 /// + #define WCOL 0x40 /// + #define SPIF 0x80 /// + +#define _SPDR 0xF5 + SFR(SPDR, _SPDR); /// 0000'0000 SPI data + +#define _AINDIDS 0xF6 + SFR(AINDIDS, _AINDIDS); /// 0000'0000 ADC channel digital input disable + #define P17DIDS 0x01 /// + #define P30DIDS 0x02 /// + #define P07DIDS 0x04 /// + #define P06DIDS 0x08 /// + #define P05DIDS 0x10 /// + #define P04DIDS 0x20 /// + #define P03DIDS 0x40 /// + #define P11DIDS 0x80 /// + +#define _EIPH 0xF7 + SFR(EIPH, _EIPH); /// 0000'0000 Extensive interrupt priority high + #define PI2CH 0x01 /// + #define PPIH 0x02 /// + #define PCAPH 0x04 /// + #define PPWMH 0x08 /// + #define PWDTH 0x10 /// + #define PFBH 0x20 /// + #define PSPIH 0x40 /// + #define PT2H 0x80 /// + +#define _SCON_1 0xF8 + SFR(SCON_1, _SCON_1); /// 0000'0000 Serial port 1 control + SBIT( RI_1, _SCON_1, 0); /// + SBIT( TI_1, _SCON_1, 1); /// + SBIT( RB8_1, _SCON_1, 2); /// + SBIT( TB8_1, _SCON_1, 3); /// + SBIT( REN_1, _SCON_1, 4); /// + SBIT( SM2_1, _SCON_1, 5); /// + SBIT( SM1_1, _SCON_1, 6); /// + SBIT( SM0_1, _SCON_1, 7); /// Write + SBIT( FE_1, _SCON_1, 7); /// Read + +#define _PDTEN 0xF9 + SFR(PDTEN, _PDTEN); /// TA 0000'0000 PWM dead time enable + #define PDT01N 0x01 /// + #define PDT23N 0x02 /// + #define PDT45N 0x04 /// + #define PDTCNT_8 0x10 /// + +#define _PDTCNT 0xFA + SFR(PDTCNT, _PDTCNT); /// TA 0000'0000 PWM dead-time counter + +#define _PMEN 0xFB + SFR(PMEN, _PMEN); /// 0000'0000 PWM mask enable + #define PMEN0 0x01 /// + #define PMEN1 0x02 /// + #define PMEN2 0x04 /// + #define PMEN3 0x08 /// + #define PMEN4 0x10 /// + #define PMEN5 0x20 /// + +#define _PMD 0xFC + SFR(PMD, _PMD); /// 0000'0000 PWM mask data + #define PMD0 0x01 /// + #define PMD1 0x02 /// + #define PMD2 0x04 /// + #define PMD3 0x08 /// + #define PMD4 0x10 /// + #define PMD5 0x20 /// + +#define _PORDIS 0xFD + SFR(PORDIS, _PORDIS); /// TA 0000'0000 POR disable + +#define _EIP1 0xFE + SFR(EIP1, _EIP1); /// 0000'0000 Extensive interrupt priority 1 + #define PS_1 0x01 /// + #define PT3 0x02 /// + #define PWKT 0x04 /// + +#define _EIPH1 0xFF + SFR(EIPH1, _EIPH1); /// 0000'0000 Extensive interrupt priority high 1 + #define PSH_1 0x01 /// + #define PT3H 0x02 /// + #define PWKTH 0x04 /// + +//Reset vector absolute address declaration +#define RST_VECTOR 0x00 //- 0x00 Reset Vector +//Interrupt numbers: Address = ( Number * 8 ) + 3 +//Vectors are named after their corresponding interrupt +//enable register bit, so that we don't have to make up +//names and can be consisten across different 8051 MCUs +#define EX0_VECTOR 0 //- 0x03 External Interrupt 0 +#define ET0_VECTOR 1 //- 0x0B Timer 0 +#define EX1_VECTOR 2 //- 0x13 External Interrupt 1 +#define ET1_VECTOR 3 //- 0x1B Timer 1 +#define ES_VECTOR 4 //- 0x23 Serial Port 0 +#define ET2_VECTOR 5 //+ 0x2B Timer 2 +#define EI2C_VECTOR 6 /// 0x33 I2C +#define EP1_VECTOR 7 /// 0x3B Pin Interrupt +#define EBOD_VECTOR 8 /// 0x43 Brown-out +#define ESPI_VECTOR 9 /// 0x4B SPI +#define EWDT_VECTOR 10 /// 0x53 Watchdog timer +#define EADC_VECTOR 11 /// 0x5B ADC +#define ECAP_VECTOR 12 /// 0x63 Input Capture +#define EPWM_VECTOR 13 /// 0x6B PWM +#define EFB_VECTOR 14 /// 0x73 Fault Brake Event +#define ES1_VECTOR 15 /// 0x7B Serial Port 1 +#define ET3_VECTOR 16 /// 0x83 Timer 3 +#define EWKT_VECTOR 17 /// 0x8B Self Wake-up Timer + +#endif \ No newline at end of file diff --git a/examples/anymcu-header/src/STC12C20xx.h b/examples/anymcu-header/src/STC12C20xx.h new file mode 100644 index 0000000..d7ef855 --- /dev/null +++ b/examples/anymcu-header/src/STC12C20xx.h @@ -0,0 +1,340 @@ +#ifndef STC12C20xx_H +#define STC12C20xx_H + +#include + +// 适用于 STC12C20xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR or change */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +/* Watchdog Timer Register */ +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +/* ISP_IAP_EEPROM Register */ +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* IDLE, Clock Divider */ +#define _IDLE_CLK 0xc7 +SFR(IDLE_CLK, 0xc7); +#define _WAKE_CLKO 0x8F +SFR(WAKE_CLKO, 0x8F); + +/* I_O Port Mode Set Register */ +#define _P0M0 0x93 +SFR(P0M0, 0x93); +#define _P0M1 0x94 +SFR(P0M1, 0x94); +#define _P1M0 0x91 +SFR(P1M0, 0x91); +#define _P1M1 0x92 +SFR(P1M1, 0x92); +#define _P2M0 0x95 +SFR(P2M0, 0x95); +#define _P2M1 0x96 +SFR(P2M1, 0x96); +#define _P3M0 0xb1 +SFR(P3M0, 0xb1); +#define _P3M1 0xb2 +SFR(P3M1, 0xb2); + +/* SPI Register */ +#define _SPSTAT 0x84 +SFR(SPSTAT, 0x84); +#define _SPCTL 0x85 +SFR(SPCTL, 0x85); +#define _SPDAT 0x86 +SFR(SPDAT, 0x86); + +/* ADC Register */ +#define _ADC_CONTR 0xc5 +SFR(ADC_CONTR, 0xc5); +#define _ADC_DATA 0xc6 +SFR(ADC_DATA, 0xc6); +#define _ADC_LOW2 0xbe +SFR(ADC_LOW2, 0xbe); + +/* PCA SFR */ +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CCAPM5 0xDF +SFR(CCAPM5, 0xDF); + +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CCAP5L 0xEF +SFR(CCAP5L, 0xEF); + +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +#define _CCAP5H 0xFF +SFR(CCAP5H, 0xFF); + +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); +#define _PCA_PWM3 0xF5 +SFR(PCA_PWM3, 0xF5); +#define _PCA_PWM4 0xF6 +SFR(PCA_PWM4, 0xF6); +#define _PCA_PWM5 0xF7 +SFR(PCA_PWM5, 0xF7); + +/* CCON */ +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF5, _CCON, 5); +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); + +/* Above is STC additional SFR or change */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +//#define _AUXR1 0xA2 +//SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* PCA Pin */ +SBIT(CEX3, _P2, 4); +SBIT(CEX2, _P2, 0); +SBIT(CEX1, _P3, 5); +SBIT(CEX0, _P3, 7); +SBIT(ECI, _P3, 4); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EPCA_LVD, _IE, 6); +SBIT(EADC_SPI, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +SBIT(PPCA_LVD, _IP, 6); +SBIT(PADC_SPI, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +#endif diff --git a/examples/anymcu-header/src/STC12C54xx.h b/examples/anymcu-header/src/STC12C54xx.h new file mode 100644 index 0000000..7a1d7c5 --- /dev/null +++ b/examples/anymcu-header/src/STC12C54xx.h @@ -0,0 +1,340 @@ +#ifndef STC12C54xx_H +#define STC12C54xx_H + +#include + +// 适用于 STC12C54xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR or change */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +/* Watchdog Timer Register */ +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +/* ISP_IAP_EEPROM Register */ +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* System Clock Divider */ +#define _CLK_DIV 0xc7 +SFR(CLK_DIV, 0xc7); + +/* I_O Port Mode Set Register */ +#define _P0M0 0x93 +SFR(P0M0, 0x93); +#define _P0M1 0x94 +SFR(P0M1, 0x94); +#define _P1M0 0x91 +SFR(P1M0, 0x91); +#define _P1M1 0x92 +SFR(P1M1, 0x92); +#define _P2M0 0x95 +SFR(P2M0, 0x95); +#define _P2M1 0x96 +SFR(P2M1, 0x96); +#define _P3M0 0xb1 +SFR(P3M0, 0xb1); +#define _P3M1 0xb2 +SFR(P3M1, 0xb2); + +/* SPI Register */ +#define _SPSTAT 0x84 +SFR(SPSTAT, 0x84); +#define _SPCTL 0x85 +SFR(SPCTL, 0x85); +#define _SPDAT 0x86 +SFR(SPDAT, 0x86); + +/* ADC Register */ +#define _ADC_CONTR 0xc5 +SFR(ADC_CONTR, 0xc5); +#define _ADC_DATA 0xc6 +SFR(ADC_DATA, 0xc6); +#define _ADC_LOW2 0xbe +SFR(ADC_LOW2, 0xbe); + +/* PCA SFR */ +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CCAPM5 0xDF +SFR(CCAPM5, 0xDF); + +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CCAP5L 0xEF +SFR(CCAP5L, 0xEF); + +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +#define _CCAP5H 0xFF +SFR(CCAP5H, 0xFF); + +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); +#define _PCA_PWM3 0xF5 +SFR(PCA_PWM3, 0xF5); +#define _PCA_PWM4 0xF6 +SFR(PCA_PWM4, 0xF6); +#define _PCA_PWM5 0xF7 +SFR(PCA_PWM5, 0xF7); + +/* CCON */ +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF5, _CCON, 5); +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); + + +/* Above is STC additional SFR or change */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x99 +SFR(SCON, 0x99); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +//#define _AUXR1 0xA2 +//SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* PCA Pin */ + +SBIT(CEX3, _P2, 4); +SBIT(CEX2, _P2, 0); +SBIT(CEX1, _P3, 5); +SBIT(CEX0, _P3, 7); +SBIT(ECI, _P3, 4); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EPCA_LVD, _IE, 6); +SBIT(EADC_SPI, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +SBIT(PPCA_LVD, _IP, 6); +SBIT(PADC_SPI, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +#endif diff --git a/examples/anymcu-header/src/STC12C56xx.h b/examples/anymcu-header/src/STC12C56xx.h new file mode 100644 index 0000000..70ab5b6 --- /dev/null +++ b/examples/anymcu-header/src/STC12C56xx.h @@ -0,0 +1,339 @@ +#ifndef STC12C56xx_H +#define STC12C56xx_H + +#include + +// 适用于 STC12C56xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR or change */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +/* Watchdog Timer Register */ +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +/* ISP_IAP_EEPROM Register */ +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* System Clock Divider */ +#define _CLK_DIV 0xc7 +SFR(CLK_DIV, 0xc7); + +/* I_O Port Mode Set Register */ +#define _P0M0 0x93 +SFR(P0M0, 0x93); +#define _P0M1 0x94 +SFR(P0M1, 0x94); +#define _P1M0 0x91 +SFR(P1M0, 0x91); +#define _P1M1 0x92 +SFR(P1M1, 0x92); +#define _P2M0 0x95 +SFR(P2M0, 0x95); +#define _P2M1 0x96 +SFR(P2M1, 0x96); +#define _P3M0 0xb1 +SFR(P3M0, 0xb1); +#define _P3M1 0xb2 +SFR(P3M1, 0xb2); + +/* SPI Register */ +#define _SPSTAT 0x84 +SFR(SPSTAT, 0x84); +#define _SPCTL 0x85 +SFR(SPCTL, 0x85); +#define _SPDAT 0x86 +SFR(SPDAT, 0x86); + +/* ADC Register */ +#define _ADC_CONTR 0xc5 +SFR(ADC_CONTR, 0xc5); +#define _ADC_DATA 0xc6 +SFR(ADC_DATA, 0xc6); +#define _ADC_LOW2 0xbe +SFR(ADC_LOW2, 0xbe); + +/* PCA SFR */ +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CCAPM5 0xDF +SFR(CCAPM5, 0xDF); + +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CCAP5L 0xEF +SFR(CCAP5L, 0xEF); + +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +#define _CCAP5H 0xFF +SFR(CCAP5H, 0xFF); + +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); +#define _PCA_PWM3 0xF5 +SFR(PCA_PWM3, 0xF5); +#define _PCA_PWM4 0xF6 +SFR(PCA_PWM4, 0xF6); +#define _PCA_PWM5 0xF7 +SFR(PCA_PWM5, 0xF7); + +/* CCON */ +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF5, _CCON, 5); +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); + + +/* Above is STC additional SFR or change */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +//#define _AUXR1 0xA2 +//SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* PCA Pin */ +SBIT(CEX3, _P2, 4); +SBIT(CEX2, _P2, 0); +SBIT(CEX1, _P3, 5); +SBIT(CEX0, _P3, 7); +SBIT(ECI, _P3, 4); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EPCA_LVD, _IE, 6); +SBIT(EADC_SPI, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +SBIT(PPCA_LVD, _IP, 6); +SBIT(PADC_SPI, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +#endif diff --git a/examples/anymcu-header/src/STC12C5Axx.h b/examples/anymcu-header/src/STC12C5Axx.h new file mode 100644 index 0000000..851ae5b --- /dev/null +++ b/examples/anymcu-header/src/STC12C5Axx.h @@ -0,0 +1,420 @@ +#ifndef STC12C5Axx_H +#define STC12C5Axx_H + +#include + +// 适用于 STC10Fxx / STC11Fxx / STC12C5Axx / STC12C52xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + + //新一代 1T 8051系列 单片机内核特殊功能寄存器 C51 Core SFRs + // 7 6 5 4 3 2 1 0 Reset Value +#define _ACC 0xE0 +SFR(ACC, 0xE0); //Accumulator 0000,0000 +#define _B 0xF0 +SFR(B, 0xF0); //B Register 0000,0000 +#define _PSW 0xD0 +SFR(CCAP0H, 0xFA); //PCA 模块 0 的捕捉/比较寄存器高 8 位。 0000,0000 +SFR(PSW, 0xD0); //Program Status Word CY AC F0 RS1 RS0 OV F1 P 0000,0000 + +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +#define _SP 0x81 +SFR(SP, 0x81); //Stack Pointer 0000,0111 +#define _DPL 0x82 +SFR(DPL, 0x82); //Data Pointer Low Byte 0000,0000 +#define _DPH 0x83 +SFR(DPH, 0x83); //Data Pointer High Byte 0000,0000 + + //新一代 1T 8051系列 单片机系统管理特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _PCON 0x87 +SFR(PCON, 0x87); //Power Control SMOD SMOD0 LVDF POF GF1 GF0 PD IDL 0001,0000 + // 7 6 5 4 3 2 1 0 Reset Value +#define _AUXR 0x8E +SFR(AUXR, 0x8E); //Auxiliary Register T0x12 T1x12 UART_M0x6 BRTR S2SMOD BRTx12 EXTRAM S1BRS 0000,0000 + +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); //Auxiliary Register 1 - PCA_P4 SPI_P4 S2_P4 GF2 ADRJ - DPS 0000,0000 +/* +PCA_P4: + 0, 缺省PCA 在P1 口 + 1，PCA/PWM 从P1 口切换到P4 口: ECI 从P1.2 切换到P4.1 口， + PCA0/PWM0 从P1.3 切换到P4.2 口 + PCA1/PWM1 从P1.4 切换到P4.3 口 +SPI_P4: + 0, 缺省SPI 在P1 口 + 1，SPI 从P1 口切换到P4 口: SPICLK 从P1.7 切换到P4.3 口 + MISO 从P1.6 切换到P4.2 口 + MOSI 从P1.5 切换到P4.1 口 + SS 从P1.4 切换到P4.0 口 +S2_P4: + 0, 缺省UART2 在P1 口 + 1，UART2 从P1 口切换到P4 口: TxD2 从P1.3 切换到P4.3 口 + RxD2 从P1.2 切换到P4.2 口 +GF2: 通用标志位 + +ADRJ: + 0, 10 位A/D 转换结果的高8 位放在ADC_RES 寄存器, 低2 位放在ADC_RESL 寄存器 + 1，10 位A/D 转换结果的最高2 位放在ADC_RES 寄存器的低2 位, 低8 位放在ADC_RESL 寄存器 + +DPS: 0, 使用缺省数据指针DPTR0 + 1，使用另一个数据指针DPTR1 +*/ + +#define _WAKE_CLKO 0x8F +SFR(WAKE_CLKO, 0x8F); //附加的 SFR WAK1_CLKO +/* + 7 6 5 4 3 2 1 0 Reset Value + PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE LVD_WAKE _ T1CLKO T0CLKO 0000,0000B + +b7 - PCAWAKEUP : PCA 中断可唤醒 powerdown。 +b6 - RXD_PIN_IE : 当 P3.0(RXD) 下降沿置位 RI 时可唤醒 powerdown(必须打开相应中断)。 +b5 - T1_PIN_IE : 当 T1 脚下降沿置位 T1 中断标志时可唤醒 powerdown(必须打开相应中断)。 +b4 - T0_PIN_IE : 当 T0 脚下降沿置位 T0 中断标志时可唤醒 powerdown(必须打开相应中断)。 +b3 - LVD_WAKE : 当 CMPIN 脚低电平置位 LVD 中断标志时可唤醒 powerdown(必须打开相应中断)。 +b2 - +b1 - T1CLKO : 允许 T1CKO(P3.5) 脚输出 T1 溢出脉冲，Fck1, 1/2 T1 溢出率 +b0 - T0CLKO : 允许 T0CKO(P3.4) 脚输出 T0 溢出脉冲，Fck0, 1/2 T1 溢出率 +*/ + +#define _CLK_DIV 0x97 +SFR(CLK_DIV, 0x97); //Clock Divder - - - - - CLKS2 CLKS1 CLKS0 xxxx,x000 + +#define _BUS_SPEED 0xA1 +SFR(BUS_SPEED, 0xA1); //Stretch register - - ALES1 ALES0 - RWS2 RWS1 RWS0 xx10,x011 +/* +ALES1 and ALES0: +00 : The P0 address setup time and hold time to ALE negative edge is one clock cycle +01 : The P0 address setup time and hold time to ALE negative edge is two clock cycles. +10 : The P0 address setup time and hold time to ALE negative edge is three clock cycles. (default) +11 : The P0 address setup time and hold time to ALE negative edge is four clock cycles. + +RWS2,RWS1,RWS0: + 000 : The MOVX read/write pulse is 1 clock cycle. + 001 : The MOVX read/write pulse is 2 clock cycles. + 010 : The MOVX read/write pulse is 3 clock cycles. + 011 : The MOVX read/write pulse is 4 clock cycles. (default) + 100 : The MOVX read/write pulse is 5 clock cycles. + 101 : The MOVX read/write pulse is 6 clock cycles. + 110 : The MOVX read/write pulse is 7 clock cycles. + 111 : The MOVX read/write pulse is 8 clock cycles. +*/ + + //新一代 1T 8051系列 单片机中断特殊功能寄存器 + //有的中断控制、中断标志位散布在其它特殊功能寄存器中，这些位在位地址中定义 + //其中有的位无位寻址能力，请参阅 新一代 1T 8051系列 单片机中文指南 + // 7 6 5 4 3 2 1 0 Reset Value +#define _IE 0xA8 +SFR(IE, 0xA8); //中断控制寄存器 EA ELVD EADC ES ET1 EX1 ET0 EX0 0x00,0000 + +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); //低压监测中断允许位 +SBIT(EADC, _IE, 5); //ADC 中断允许位 +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +#define _IE2 0xAF +SFR(IE2, 0xAF); //Auxiliary Interrupt - - - - - - ESPI ES2 0000,0000B + + // 7 6 5 4 3 2 1 0 Reset Value +#define _IP 0xB8 +SFR(IP, 0xB8); //中断优先级低位 PPCA PLVD PADC PS PT1 PX1 PT0 PX0 0000,0000 + +SBIT(PPCA, _IP, 7); //PCA 模块中断优先级 +SBIT(PLVD, _IP, 6); //低压监测中断优先级 +SBIT(PADC, _IP, 5); //ADC 中断优先级 +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + + // 7 6 5 4 3 2 1 0 Reset Value +#define _IPH 0xB7 +SFR(IPH, 0xB7); //中断优先级高位 PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H 0000,0000 +#define _IP2 0xB5 +SFR(IP2, 0xB5); // - - - - - - PSPI PS2 xxxx,xx00 +#define _IPH2 0xB6 +SFR(IPH2, 0xB6); // - - - - - - PSPIH PS2H xxxx,xx00 + + //新一代 1T 8051系列 单片机I/O 口特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _P0 0x80 +SFR(P0, 0x80); //8 bitPort0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 1111,1111 +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P0M0 0x94 +SFR(P0M0, 0x94); // 0000,0000 +#define _P0M1 0x93 +SFR(P0M1, 0x93); // 0000,0000 +#define _P1 0x90 +SFR(P1, 0x90); //8 bitPort1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 1111,1111 +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P1M0 0x92 +SFR(P1M0, 0x92); // 0000,0000 +#define _P1M1 0x91 +SFR(P1M1, 0x91); // 0000,0000 +#define _P1ASF 0x9D +SFR(P1ASF, 0x9D); //P1 analog special function +#define _P2 0xA0 +SFR(P2, 0xA0); //8 bitPort2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 1111,1111 +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P2M0 0x96 +SFR(P2M0, 0x96); // 0000,0000 +#define _P2M1 0x95 +SFR(P2M1, 0x95); // 0000,0000 +#define _P3 0xB0 +SFR(P3, 0xB0); //8 bitPort3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 1111,1111 +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _P3M0 0xB2 +SFR(P3M0, 0xB2); // 0000,0000 +#define _P3M1 0xB1 +SFR(P3M1, 0xB1); // 0000,0000 +#define _P4 0xC0 +SFR(P4, 0xC0); //8 bitPort4 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 1111,1111 +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +#define _P4M0 0xB4 +SFR(P4M0, 0xB4); // 0000,0000 +#define _P4M1 0xB3 +SFR(P4M1, 0xB3); // 0000,0000 + // 7 6 5 4 3 2 1 0 Reset Value +#define _P4SW 0xBB +SFR(P4SW, 0xBB); //Port-4 switch - LVD_P4.6 ALE_P4.5 NA_P4.4 - - - - x000,xxxx + +#define _P5 0xC8 +SFR(P5, 0xC8); //8 bitPort5 - - - - P5.3 P5.2 P5.1 P5.0 xxxx,1111 +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +#define _P5M0 0xCA +SFR(P5M0, 0xCA); // 0000,0000 +#define _P5M1 0xC9 +SFR(P5M1, 0xC9); // 0000,0000 + + //新一代 1T 8051系列 单片机定时器特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _TCON 0x88 +SFR(TCON, 0x88); //T0/T1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0000,0000 + +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +#define _TMOD 0x89 +SFR(TMOD, 0x89); //T0/T1 Modes GATE1 C/T1 M1_1 M1_0 GATE0 C/T0 M0_1 M0_0 0000,0000 +#define _TL0 0x8A +SFR(TL0, 0x8A); //T0 Low Byte 0000,0000 +#define _TH0 0x8C +SFR(TH0, 0x8C); //T0 High Byte 0000,0000 +#define _TL1 0x8B +SFR(TL1, 0x8B); //T1 Low Byte 0000,0000 +#define _TH1 0x8D +SFR(TH1, 0x8D); //T1 High Byte 0000,0000 + + //新一代 1T 8051系列 单片机串行口特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _SCON 0x98 +SFR(SCON, 0x98); //Serial Control SM0/FE SM1 SM2 REN TB8 RB8 TI RI 0000,0000 + +SBIT(SM0, _SCON, 7); //SM0/FE +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +#define _SBUF 0x99 +SFR(SBUF, 0x99); //Serial Data Buffer xxxx,xxxx +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); //Slave Address Mask 0000,0000 +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); //Slave Address 0000,0000 + + // 7 6 5 4 3 2 1 0 Reset Value +#define _S2CON 0x9A +SFR(S2CON, 0x9A); //S2 Control S2SM0 S2SM1 S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B +#define _S2BUF 0x9B +SFR(S2BUF, 0x9B); //S2 Serial Buffer xxxx,xxxx +#define _BRT 0x9C +SFR(BRT, 0x9C); //S2 Baud-Rate Timer 0000,0000 + + //新一代 1T 8051系列 单片机看门狗定时器特殊功能寄存器 +#define _WDT_CONTR 0xC1 +SFR(WDT_CONTR, 0xC1); //Watch-Dog-Timer Control register + // 7 6 5 4 3 2 1 0 Reset Value + // WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0 xx00,0000 + + //新一代 1T 8051系列 单片机PCA/PWM 特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _CCON 0xD8 +SFR(CCON, 0xD8); //PCA 控制寄存器。 CF CR - - - - CCF1 CCF0 00xx,xx00 + +SBIT(CF, _CCON, 7); //PCA计数器溢出标志,由硬件或软件置位,必须由软件清0。 +SBIT(CR, _CCON, 6); //1:允许 PCA 计数器计数, 必须由软件清0。 + +SBIT(CCF1, _CCON, 1); //PCA 模块1 中断标志, 由硬件置位, 必须由软件清0。 +SBIT(CCF0, _CCON, 0); //PCA 模块0 中断标志, 由硬件置位, 必须由软件清0。 + +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); //PCA 工作模式寄存器。 CIDL - - - CPS2 CPS1 CPS0 ECF 0xxx,x000 +/* +CIDL: idle 状态时 PCA 计数器是否继续计数, 0: 继续计数, 1: 停止计数。 + +CPS2: PCA 计数器脉冲源选择位 2。 +CPS1: PCA 计数器脉冲源选择位 1。 +CPS0: PCA 计数器脉冲源选择位 0。 + CPS2 CPS1 CPS0 + 0 0 0 系统时钟频率 fosc/12。 + 0 0 1 系统时钟频率 fosc/2。 + 0 1 0 Timer0 溢出。 + 0 1 1 由 ECI/P3.4 脚输入的外部时钟，最大 fosc/2。 + 1 0 0 系统时钟频率， Fosc/1 + 1 0 1 系统时钟频率/4，Fosc/4 + 1 1 0 系统时钟频率/6，Fosc/6 + 1 1 1 系统时钟频率/8，Fosc/8 + +ECF: PCA计数器溢出中断允许位, 1--允许 CF(CCON.7) 产生中断。 +*/ + +#define _CL 0xE9 +SFR(CL, 0xE9); //PCA 计数器低位 0000,0000 +#define _CH 0xF9 +SFR(CH, 0xF9); //PCA 计数器高位 0000,0000 + + // 7 6 5 4 3 2 1 0 Reset Value +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); //PCA 模块0 PWM 寄存器 - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x000,0000 +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); //PCA 模块1 PWM 寄存器 - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x000,0000 + +//ECOMn, 1:允许比较功能。 +//CAPPn, 1:允许上升沿触发捕捉功能。 +//CAPNn, 1:允许下降沿触发捕捉功能。 +//MATn, 1:当匹配情况发生时, 允许 CCON 中的 CCFn 置位。 +//TOGn, 1:当匹配情况发生时, CEXn 将翻转。 +//PWMn, 1:将 CEXn 设置为 PWM 输出。 +//ECCFn, 1:允许 CCON 中的 CCFn 触发中断。 + +//ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn +// 0 0 0 0 0 0 0 0x00 未启用任何功能。 +// x 1 0 0 0 0 x 0x21 16位CEXn上升沿触发捕捉功能。 +// x 0 1 0 0 0 x 0x11 16位CEXn下降沿触发捕捉功能。 +// x 1 1 0 0 0 x 0x31 16位CEXn边沿(上、下沿)触发捕捉功能。 +// 1 0 0 1 0 0 x 0x49 16位软件定时器。 +// 1 0 0 1 1 0 x 0x4d 16位高速脉冲输出。 +// 1 0 0 0 0 1 0 0x42 8位 PWM。 + +//ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn +// 0 0 0 0 0 0 0 0x00 无此操作 +// 1 0 0 0 0 1 0 0x42 普通8位PWM, 无中断 +// 1 1 0 0 0 1 1 0x63 PWM输出由低变高可产生中断 +// 1 0 1 0 0 1 1 0x53 PWM输出由高变低可产生中断 +// 1 1 1 0 0 1 1 0x73 PWM输出由低变高或由高变低都可产生中断 + + +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); //PCA 模块 0 的捕捉/比较寄存器低 8 位。 0000,0000 +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); //PCA 模块 0 的捕捉/比较寄存器高 8 位。 0000,0000 +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); //PCA 模块 1 的捕捉/比较寄存器低 8 位。 0000,0000 +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); //PCA 模块 1 的捕捉/比较寄存器高 8 位。 0000,0000 + + // 7 6 5 4 3 2 1 0 Reset Value +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); //PCA 模块0 PWM 寄存器。- - - - - - EPC0H EPC0L xxxx,xx00 +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); //PCA 模块1 PWM 寄存器。- - - - - - EPC1H EPC1L xxxx,xx00 + //PCA_PWMn: 7 6 5 4 3 2 1 0 + // - - - - - - EPCnH EPCnL + //B7-B2: 保留 + //B1(EPCnH): 在 PWM 模式下，与 CCAPnH 组成 9 位数。 + //B0(EPCnL): 在 PWM 模式下，与 CCAPnL 组成 9 位数。 + + //新一代 1T 8051系列 单片机 ADC 特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _ADC_CONTR 0xBC +SFR(ADC_CONTR, 0xBC); //A/D 转换控制寄存器 ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000,0000 +#define _ADC_RES 0xBD +SFR(ADC_RES, 0xBD); //A/D 转换结果高8位 ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 0000,0000 +#define _ADC_RESL 0xBE +SFR(ADC_RESL, 0xBE); //A/D 转换结果低2位 - - - - - - ADCV.1 ADCV.0 0000,0000 + + //新一代 1T 8051系列 单片机 SPI 特殊功能寄存器 + // 7 6 5 4 3 2 1 0 Reset Value +#define _SPCTL 0xCE +SFR(SPCTL, 0xCE); //SPI Control Register SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 0000,0100 +#define _SPSTAT 0xCD +SFR(SPSTAT, 0xCD); //SPI Status Register SPIF WCOL - - - - - - 00xx,xxxx +#define _SPDAT 0xCF +SFR(SPDAT, 0xCF); //SPI Data Register 0000,0000 + + //新一代 1T 8051系列 单片机 IAP/ISP 特殊功能寄存器 +#define _IAP_DATA 0xC2 +SFR(IAP_DATA, 0xC2); +#define _IAP_ADDRH 0xC3 +SFR(IAP_ADDRH, 0xC3); +#define _IAP_ADDRL 0xC4 +SFR(IAP_ADDRL, 0xC4); + // 7 6 5 4 3 2 1 0 Reset Value +#define _IAP_CMD 0xC5 +SFR(IAP_CMD, 0xC5); //IAP Mode Table 0 - - - - - MS1 MS0 0xxx,xx00 +#define _IAP_TRIG 0xC6 +SFR(IAP_TRIG, 0xC6); +#define _IAP_CONTR 0xC7 +SFR(IAP_CONTR, 0xC7); //IAP Control Register IAPEN SWBS SWRST CFAIL - WT2 WT1 WT0 0000,x000 + +#endif + diff --git a/examples/anymcu-header/src/STC15.h b/examples/anymcu-header/src/STC15.h new file mode 100644 index 0000000..a929917 --- /dev/null +++ b/examples/anymcu-header/src/STC15.h @@ -0,0 +1,406 @@ +#ifndef STC15_H +#define STC15_H +#include + +// Suitable for use with most STC15x series MCU. +// This header file was verified against the official STC ISP Tool. +// After this file is included you don't have to include "REG51.H" + +// Special Function Register //Reset Value Description +#define _ACC 0xE0 +SFR(ACC, 0xE0); //0000,0000 Accumulator +#define _B 0xF0 +SFR(B, 0xF0); //0000,0000 B Register +#define _PSW 0xD0 +SFR(PSW, 0xD0); //0000,0000 Program status word +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(F1, _PSW, 1); +SBIT(P, _PSW, 0); +#define _SP 0x81 +SFR(SP, 0x81); //0000,0111 Stack Pointer +#define _DPL 0x82 +SFR(DPL, 0x82); //0000,0000 Data Pointer Low Byte +#define _DPH 0x83 +SFR(DPH, 0x83); //0000,0000 Data Pointer High Byte + +// I/O Port Special Function Register +#define _P0 0x80 +SFR(P0, 0x80); //1111,1111 Port 0 +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +SBIT(P0_0, _P0, 0); +SBIT(P0_1, _P0, 1); +SBIT(P0_2, _P0, 2); +SBIT(P0_3, _P0, 3); +SBIT(P0_4, _P0, 4); +SBIT(P0_5, _P0, 5); +SBIT(P0_6, _P0, 6); +SBIT(P0_7, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); //1111,1111 Port 1 +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +SBIT(P1_0, _P1, 0); +SBIT(P1_1, _P1, 1); +SBIT(P1_2, _P1, 2); +SBIT(P1_3, _P1, 3); +SBIT(P1_4, _P1, 4); +SBIT(P1_5, _P1, 5); +SBIT(P1_6, _P1, 6); +SBIT(P1_7, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); //1111,1111 Port 2 +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +SBIT(P2_0, _P2, 0); +SBIT(P2_1, _P2, 1); +SBIT(P2_2, _P2, 2); +SBIT(P2_3, _P2, 3); +SBIT(P2_4, _P2, 4); +SBIT(P2_5, _P2, 5); +SBIT(P2_6, _P2, 6); +SBIT(P2_7, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); //1111,1111 Port 3 +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +SBIT(P3_0, _P3, 0); +SBIT(P3_1, _P3, 1); +SBIT(P3_2, _P3, 2); +SBIT(P3_3, _P3, 3); +SBIT(P3_4, _P3, 4); +SBIT(P3_5, _P3, 5); +SBIT(P3_6, _P3, 6); +SBIT(P3_7, _P3, 7); +#define _P4 0xC0 +SFR(P4, 0xC0); //1111,1111 Port 4 +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +SBIT(P4_0, _P4, 0); +SBIT(P4_1, _P4, 1); +SBIT(P4_2, _P4, 2); +SBIT(P4_3, _P4, 3); +SBIT(P4_4, _P4, 4); +SBIT(P4_5, _P4, 5); +SBIT(P4_6, _P4, 6); +SBIT(P4_7, _P4, 7); +#define _P5 0xC8 +SFR(P5, 0xC8); //xxxx,1111 Port 5 +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +SBIT(P54, _P5, 4); +SBIT(P55, _P5, 5); +SBIT(P56, _P5, 6); +SBIT(P57, _P5, 7); +SBIT(P5_0, _P5, 0); +SBIT(P5_1, _P5, 1); +SBIT(P5_2, _P5, 2); +SBIT(P5_3, _P5, 3); +SBIT(P5_4, _P5, 4); +SBIT(P5_5, _P5, 5); +SBIT(P5_6, _P5, 6); +SBIT(P5_7, _P5, 7); +#define _P6 0xE8 +SFR(P6, 0xE8); //0000,0000 Port 6 +SBIT(P60, _P6, 0); +SBIT(P61, _P6, 1); +SBIT(P62, _P6, 2); +SBIT(P63, _P6, 3); +SBIT(P64, _P6, 4); +SBIT(P65, _P6, 5); +SBIT(P66, _P6, 6); +SBIT(P67, _P6, 7); +SBIT(P6_0, _P6, 0); +SBIT(P6_1, _P6, 1); +SBIT(P6_2, _P6, 2); +SBIT(P6_3, _P6, 3); +SBIT(P6_4, _P6, 4); +SBIT(P6_5, _P6, 5); +SBIT(P6_6, _P6, 6); +SBIT(P6_7, _P6, 7); +#define _P7 0xF8 +SFR(P7, 0xF8); //0000,0000 Port 7 +SBIT(P70, _P7, 0); +SBIT(P71, _P7, 1); +SBIT(P72, _P7, 2); +SBIT(P73, _P7, 3); +SBIT(P74, _P7, 4); +SBIT(P75, _P7, 5); +SBIT(P76, _P7, 6); +SBIT(P77, _P7, 7); +SBIT(P70, _P7, 0); +SBIT(P7_1, _P7, 1); +SBIT(P7_2, _P7, 2); +SBIT(P7_3, _P7, 3); +SBIT(P7_4, _P7, 4); +SBIT(P7_5, _P7, 5); +SBIT(P7_6, _P7, 6); +SBIT(P7_7, _P7, 7); +#define _P0M0 0x94 +SFR(P0M0, 0x94); //0000,0000 Port 0 Mode Register 0 +#define _P0M1 0x93 +SFR(P0M1, 0x93); //0000,0000 Port 0 Mode Register 1 +#define _P1M0 0x92 +SFR(P1M0, 0x92); //0000,0000 Port 1 Mode Register 0 +#define _P1M1 0x91 +SFR(P1M1, 0x91); //0000,0000 Port 1 Mode Register 1 +#define _P2M0 0x96 +SFR(P2M0, 0x96); //0000,0000 Port 2 Mode Register 0 +#define _P2M1 0x95 +SFR(P2M1, 0x95); //0000,0000 Port 2 Mode Register 1 +#define _P3M0 0xB2 +SFR(P3M0, 0xB2); //0000,0000 Port 3 Mode Register 0 +#define _P3M1 0xB1 +SFR(P3M1, 0xB1); //0000,0000 Port 3 Mode Register 1 +#define _P4M0 0xB4 +SFR(P4M0, 0xB4); //0000,0000 Port 4 Mode Register 0 +#define _P4M1 0xB3 +SFR(P4M1, 0xB3); //0000,0000 Port 4 Mode Register 1 +#define _P5M0 0xCA +SFR(P5M0, 0xCA); //0000,0000 Port 5 Mode Register 0 +#define _P5M1 0xC9 +SFR(P5M1, 0xC9); //0000,0000 Port 5 Mode Register 1 +#define _P6M0 0xCC +SFR(P6M0, 0xCC); //0000,0000 Port 6 Mode Register 0 +#define _P6M1 0xCB +SFR(P6M1, 0xCB); //0000,0000 Port 6 Mode Register 1 +#define _P7M0 0xE2 +SFR(P7M0, 0xE2); //0000,0000 Port 7 Mode Register 0 +#define _P7M1 0xE1 +SFR(P7M1, 0xE1); //0000,0000 Port 7 Mode Register 1 + +// System management special function register +#define _PCON 0x87 +SFR(PCON, 0x87); //0001,0000 Power Control Register +#define _AUXR 0x8E +SFR(AUXR, 0x8E); //0000,0000 Auxiliary Register +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); //0000,0000 Auxiliary Register 1 +#define _P_SW1 0xA2 +SFR(P_SW1, 0xA2); //0000,0000 Peripheral Port Switching Register 1 +#define _CLK_DIV 0x97 +SFR(CLK_DIV, 0x97); //xxxx,x000 Clock Division Control Register +#define _BUS_SPEED 0xA1 +SFR(BUS_SPEED, 0xA1); //xx10,x011 Bus Speed Control Register +#define _P1ASF 0x9D +SFR(P1ASF, 0x9D); //0000,0000 Port 1 Analog Function Configuration Register +#define _P_SW2 0xBA +SFR(P_SW2, 0xBA); //0xxx,x000 Peripheral Port Switching Register +#define _IRC_CLKO 0xBB +SFR(IRC_CLKO, 0xBB); //0000,0000 Internal Oscillator Clock Output Control Register + +// Interrupt special function register +#define _IE 0xA8 +SFR(IE, 0xA8); //0000,0000 Interrupt Control Register +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); +SBIT(EADC, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); +#define _IP 0xB8 +SFR(IP, 0xB8); //0000,0000 Interrupt Priority Register +SBIT(PPCA, _IP, 7); +SBIT(PLVD, _IP, 6); +SBIT(PADC, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); +#define _IE2 0xAF +SFR(IE2, 0xAF); //0000,0000 Interrupt Control Register 2 +#define _IP2 0xB5 +SFR(IP2, 0xB5); //xxxx,xx00 Interrupt Priority Register 2 +#define _INT_CLKO 0x8F +SFR(INT_CLKO, 0x8F); //0000,0000 External Interrupt and Clock Output Control Register + +// Timer Special Function Register +#define _TCON 0x88 +SFR(TCON, 0x88); //0000,0000 T0/T1 Control Register +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); +#define _TMOD 0x89 +SFR(TMOD, 0x89); //0000,0000 T0/T1 Mode Register +#define _TL0 0x8A +SFR(TL0, 0x8A); //0000,0000 T0 Low Byte +#define _TL1 0x8B +SFR(TL1, 0x8B); //0000,0000 T1 Low Byte +#define _TH0 0x8C +SFR(TH0, 0x8C); //0000,0000 T0 High Byte +#define _TH1 0x8D +SFR(TH1, 0x8D); //0000,0000 T1 High Byte +#define _T4T3M 0xD1 +SFR(T4T3M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T3T4M 0xD1 +SFR(T3T4M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T4H 0xD2 +SFR(T4H, 0xD2); //0000,0000 T4 High Byte +#define _T4L 0xD3 +SFR(T4L, 0xD3); //0000,0000 T4 Low Byte +#define _T3H 0xD4 +SFR(T3H, 0xD4); //0000,0000 T3 High Byte +#define _T3L 0xD5 +SFR(T3L, 0xD5); //0000,0000 T3 Low Byte +#define _T2H 0xD6 +SFR(T2H, 0xD6); //0000,0000 T2 High Byte +#define _T2L 0xD7 +SFR(T2L, 0xD7); //0000,0000 T2 Low Byte +#define _WKTCL 0xAA +SFR(WKTCL, 0xAA); //0000,0000 Power Down Wakeup Timer Low Byte +#define _WKTCH 0xAB +SFR(WKTCH, 0xAB); //0000,0000 Power Down Wakeup Timer High Byte +#define _WDT_CONTR 0xC1 +SFR(WDT_CONTR, 0xC1); //0000,0000 Watchdog Control Register + +// Serial port special function register +#define _SCON 0x98 +SFR(SCON, 0x98); //0000,0000 Serial Port 1 Control Register +SBIT(SM0, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); +#define _SBUF 0x99 +SFR(SBUF, 0x99); //xxxx,xxxx Serial Port 1 Data Register +#define _S2CON 0x9A +SFR(S2CON, 0x9A); //0000,0000 Serial Port 2 Control Register +#define _S2BUF 0x9B +SFR(S2BUF, 0x9B); //xxxx,xxxx Serial Port 2 Data Register +#define _S3CON 0xAC +SFR(S3CON, 0xAC); //0000,0000 Serial Port 3 Control Register +#define _S3BUF 0xAD +SFR(S3BUF, 0xAD); //xxxx,xxxx Serial Port 3 Data Register +#define _S4CON 0x84 +SFR(S4CON, 0x84); //0000,0000 Serial Port 4 Control Register +#define _S4BUF 0x85 +SFR(S4BUF, 0x85); //xxxx,xxxx Serial Port 4 Data Register +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); //0000,0000 Slave Address Register +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); //0000,0000 Slave Address Mask Register + +// ADC Special Function Register +#define _ADC_CONTR 0xBC +SFR(ADC_CONTR, 0xBC); //0000,0000 A/D Conversion Control Register +#define _ADC_RES 0xBD +SFR(ADC_RES, 0xBD); //0000,0000 A/D Conversion Result High 8 Bits +#define _ADC_RESL 0xBE +SFR(ADC_RESL, 0xBE); //0000,0000 A/D Conversion Result Low 2 Bits + +// SPI Special Function Register +#define _SPSTAT 0xCD +SFR(SPSTAT, 0xCD); //00xx,xxxx SPI Status Register +#define _SPCTL 0xCE +SFR(SPCTL, 0xCE); //0000,0100 SPI Control Register +#define _SPDAT 0xCF +SFR(SPDAT, 0xCF); //0000,0000 SPI Data Register + +// IAP/ISP Special Function Register +#define _IAP_DATA 0xC2 +SFR(IAP_DATA, 0xC2); //0000,0000 EEPROM data register +#define _IAP_ADDRH 0xC3 +SFR(IAP_ADDRH, 0xC3); //0000,0000 EEPROM address high byte +#define _IAP_ADDRL 0xC4 +SFR(IAP_ADDRL, 0xC4); //0000,0000 EEPROM address low byte +#define _IAP_CMD 0xC5 +SFR(IAP_CMD, 0xC5); //xxxx,xx00 EEPROM Command Register +#define _IAP_TRIG 0xC6 +SFR(IAP_TRIG, 0xC6); //0000,0000 EEPRPM Command Trigger +#define _IAP_CONTR 0xC7 +SFR(IAP_CONTR, 0xC7); //0000,x000 EEPROM Control Register + +// PCA/PWM Special Function Register +#define _CCON 0xD8 +SFR(CCON, 0xD8); //00xx,xx00 PCA Control Register +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); //0xxx,x000 PCA Working Mode Register +#define _CL 0xE9 +SFR(CL, 0xE9); //0000,0000 PCA Counter Low Byte +#define _CH 0xF9 +SFR(CH, 0xF9); //0000,0000 PCA Counter High Byte +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); //0000,0000 PCA Module 0 PWM Register +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); //0000,0000 PCA Module 1 PWM Register +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); //0000,0000 PCA Module 2 PWM Register +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); //0000,0000 PCA Module 0 Capture/Compare Register Low Byte +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); //0000,0000 PCA Module 1 Capture/Compare Register Low Byte +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); //0000,0000 PCA Module 2 Capture/Compare Register Low Byte +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); //xxxx,xx00 PCA Module 0 PWM Register +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); //xxxx,xx00 PCA Module 1 PWM Register +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); //xxxx,xx00 PCA Module 2 PWM Register +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); //0000,0000 PCA Module 0 Capture/Compare Register High Byte +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); //0000,0000 PCA Module 1 Capture/Compare Register High Byte +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); //0000,0000 PCA Module 2 Capture/Compare Register High Byte + +// Comparator Special Function Register +#define _CMPCR1 0xE6 +SFR(CMPCR1, 0xE6); //0000,0000 Comparator Control Register 1 +#define _CMPCR2 0xE7 +SFR(CMPCR2, 0xE7); //0000,0000 Comparator Control Register 2 + +#endif diff --git a/examples/anymcu-header/src/STC15W4K.h b/examples/anymcu-header/src/STC15W4K.h new file mode 100644 index 0000000..8287fdb --- /dev/null +++ b/examples/anymcu-header/src/STC15W4K.h @@ -0,0 +1,472 @@ +#ifndef STC15W4K_H +#define STC15W4K_H +#include + +// Suitable for use with STC15W4K series MCU with enhanced PWM. +// This header file was verified against the official STC ISP Tool. +// After this file is included you don't have to include "reg51.h" + +///////////////////////////////////////////////// +// Note regarding STC15W4K32S4 series of chips: +// All IO ports related to PWM are high after power-on and +// need to be set to quasi-two-way or strong push-pull modes: +// P0.6/P0.7/P1.6/P1.7/P2.1/P2.2/P2.3/P2.7/P3.7/P4.2/P4.4/P4.5 +///////////////////////////////////////////////// + +// Special Function Register //Reset Value Description +#define _ACC 0xE0 +SFR(ACC, 0xE0); //0000,0000 Accumulator +#define _B 0xF0 +SFR(B, 0xF0); //0000,0000 B Register +#define _PSW 0xD0 +SFR(PSW, 0xD0); //0000,0000 Program status word +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(F1, _PSW, 1); +SBIT(P, _PSW, 0); +#define _SP 0x81 +SFR(SP, 0x81); //0000,0111 Stack Pointer +#define _DPL 0x82 +SFR(DPL, 0x82); //0000,0000 Data Pointer Low Byte +#define _DPH 0x83 +SFR(DPH, 0x83); //0000,0000 Data Pointer High Byte + +// I/O Port Special Function Register +#define _P0 0x80 +SFR(P0, 0x80); //1111,1111 Port 0 +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +SBIT(P0_0, _P0, 0); +SBIT(P0_1, _P0, 1); +SBIT(P0_2, _P0, 2); +SBIT(P0_3, _P0, 3); +SBIT(P0_4, _P0, 4); +SBIT(P0_5, _P0, 5); +SBIT(P0_6, _P0, 6); +SBIT(P0_7, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); //1111,1111 Port 1 +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +SBIT(P1_0, _P1, 0); +SBIT(P1_1, _P1, 1); +SBIT(P1_2, _P1, 2); +SBIT(P1_3, _P1, 3); +SBIT(P1_4, _P1, 4); +SBIT(P1_5, _P1, 5); +SBIT(P1_6, _P1, 6); +SBIT(P1_7, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); //1111,1111 Port 2 +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +SBIT(P2_0, _P2, 0); +SBIT(P2_1, _P2, 1); +SBIT(P2_2, _P2, 2); +SBIT(P2_3, _P2, 3); +SBIT(P2_4, _P2, 4); +SBIT(P2_5, _P2, 5); +SBIT(P2_6, _P2, 6); +SBIT(P2_7, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); //1111,1111 Port 3 +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +SBIT(P3_0, _P3, 0); +SBIT(P3_1, _P3, 1); +SBIT(P3_2, _P3, 2); +SBIT(P3_3, _P3, 3); +SBIT(P3_4, _P3, 4); +SBIT(P3_5, _P3, 5); +SBIT(P3_6, _P3, 6); +SBIT(P3_7, _P3, 7); +#define _P4 0xC0 +SFR(P4, 0xC0); //1111,1111 Port 4 +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +SBIT(P4_0, _P4, 0); +SBIT(P4_1, _P4, 1); +SBIT(P4_2, _P4, 2); +SBIT(P4_3, _P4, 3); +SBIT(P4_4, _P4, 4); +SBIT(P4_5, _P4, 5); +SBIT(P4_6, _P4, 6); +SBIT(P4_7, _P4, 7); +#define _P5 0xC8 +SFR(P5, 0xC8); //xxxx,1111 Port 5 +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +SBIT(P54, _P5, 4); +SBIT(P55, _P5, 5); +SBIT(P56, _P5, 6); +SBIT(P57, _P5, 7); +SBIT(P5_0, _P5, 0); +SBIT(P5_1, _P5, 1); +SBIT(P5_2, _P5, 2); +SBIT(P5_3, _P5, 3); +SBIT(P5_4, _P5, 4); +SBIT(P5_5, _P5, 5); +SBIT(P5_6, _P5, 6); +SBIT(P5_7, _P5, 7); +#define _P6 0xE8 +SFR(P6, 0xE8); //0000,0000 Port 6 +SBIT(P60, _P6, 0); +SBIT(P61, _P6, 1); +SBIT(P62, _P6, 2); +SBIT(P63, _P6, 3); +SBIT(P64, _P6, 4); +SBIT(P65, _P6, 5); +SBIT(P66, _P6, 6); +SBIT(P67, _P6, 7); +SBIT(P6_0, _P6, 0); +SBIT(P6_1, _P6, 1); +SBIT(P6_2, _P6, 2); +SBIT(P6_3, _P6, 3); +SBIT(P6_4, _P6, 4); +SBIT(P6_5, _P6, 5); +SBIT(P6_6, _P6, 6); +SBIT(P6_7, _P6, 7); +#define _P7 0xF8 +SFR(P7, 0xF8); //0000,0000 Port 7 +SBIT(P70, _P7, 0); +SBIT(P71, _P7, 1); +SBIT(P72, _P7, 2); +SBIT(P73, _P7, 3); +SBIT(P74, _P7, 4); +SBIT(P75, _P7, 5); +SBIT(P76, _P7, 6); +SBIT(P77, _P7, 7); +SBIT(P70, _P7, 0); +SBIT(P7_1, _P7, 1); +SBIT(P7_2, _P7, 2); +SBIT(P7_3, _P7, 3); +SBIT(P7_4, _P7, 4); +SBIT(P7_5, _P7, 5); +SBIT(P7_6, _P7, 6); +SBIT(P7_7, _P7, 7); +#define _P0M0 0x94 +SFR(P0M0, 0x94); //0000,0000 Port 0 Mode Register 0 +#define _P0M1 0x93 +SFR(P0M1, 0x93); //0000,0000 Port 0 Mode Register 1 +#define _P1M0 0x92 +SFR(P1M0, 0x92); //0000,0000 Port 1 Mode Register 0 +#define _P1M1 0x91 +SFR(P1M1, 0x91); //0000,0000 Port 1 Mode Register 1 +#define _P2M0 0x96 +SFR(P2M0, 0x96); //0000,0000 Port 2 Mode Register 0 +#define _P2M1 0x95 +SFR(P2M1, 0x95); //0000,0000 Port 2 Mode Register 1 +#define _P3M0 0xB2 +SFR(P3M0, 0xB2); //0000,0000 Port 3 Mode Register 0 +#define _P3M1 0xB1 +SFR(P3M1, 0xB1); //0000,0000 Port 3 Mode Register 1 +#define _P4M0 0xB4 +SFR(P4M0, 0xB4); //0000,0000 Port 4 Mode Register 0 +#define _P4M1 0xB3 +SFR(P4M1, 0xB3); //0000,0000 Port 4 Mode Register 1 +#define _P5M0 0xCA +SFR(P5M0, 0xCA); //0000,0000 Port 5 Mode Register 0 +#define _P5M1 0xC9 +SFR(P5M1, 0xC9); //0000,0000 Port 5 Mode Register 1 +#define _P6M0 0xCC +SFR(P6M0, 0xCC); //0000,0000 Port 6 Mode Register 0 +#define _P6M1 0xCB +SFR(P6M1, 0xCB); //0000,0000 Port 6 Mode Register 1 +#define _P7M0 0xE2 +SFR(P7M0, 0xE2); //0000,0000 Port 7 Mode Register 0 +#define _P7M1 0xE1 +SFR(P7M1, 0xE1); //0000,0000 Port 7 Mode Register 1 + +// System management special function register +#define _PCON 0x87 +SFR(PCON, 0x87); //0001,0000 Power Control Register +#define _AUXR 0x8E +SFR(AUXR, 0x8E); //0000,0000 Auxiliary Register +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); //0000,0000 Auxiliary Register 1 +#define _P_SW1 0xA2 +SFR(P_SW1, 0xA2); //0000,0000 Peripheral Port Switching Register 1 +#define _CLK_DIV 0x97 +SFR(CLK_DIV, 0x97); //xxxx,x000 Clock Division Control Register +#define _BUS_SPEED 0xA1 +SFR(BUS_SPEED, 0xA1); //xx10,x011 Bus Speed Control Register +#define _P1ASF 0x9D +SFR(P1ASF, 0x9D); //0000,0000 Port 1 Analog Function Configuration Register +#define _P_SW2 0xBA +SFR(P_SW2, 0xBA); //0xxx,x000 Peripheral Port Switching Register +#define _IRC_CLKO 0xBB +SFR(IRC_CLKO, 0xBB); //0000,0000 Internal Oscillator Clock Output Control Register + +// Interrupt special function register +#define _IE 0xA8 +SFR(IE, 0xA8); //0000,0000 Interrupt Control Register +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); +SBIT(EADC, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); +#define _IP 0xB8 +SFR(IP, 0xB8); //0000,0000 Interrupt Priority Register +SBIT(PPCA, _IP, 7); +SBIT(PLVD, _IP, 6); +SBIT(PADC, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); +#define _IE2 0xAF +SFR(IE2, 0xAF); //0000,0000 Interrupt Control Register 2 +#define _IP2 0xB5 +SFR(IP2, 0xB5); //xxxx,xx00 Interrupt Priority Register 2 +#define _INT_CLKO 0x8F +SFR(INT_CLKO, 0x8F); //0000,0000 External Interrupt and Clock Output Control Register + +// Timer Special Function Register +#define _TCON 0x88 +SFR(TCON, 0x88); //0000,0000 T0/T1 Control Register +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); +#define _TMOD 0x89 +SFR(TMOD, 0x89); //0000,0000 T0/T1 Mode Register +#define _TL0 0x8A +SFR(TL0, 0x8A); //0000,0000 T0 Low Byte +#define _TL1 0x8B +SFR(TL1, 0x8B); //0000,0000 T1 Low Byte +#define _TH0 0x8C +SFR(TH0, 0x8C); //0000,0000 T0 High Byte +#define _TH1 0x8D +SFR(TH1, 0x8D); //0000,0000 T1 High Byte +#define _T4T3M 0xD1 +SFR(T4T3M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T3T4M 0xD1 +SFR(T3T4M, 0xD1); //0000,0000 T3/T4 Mode Register +#define _T4H 0xD2 +SFR(T4H, 0xD2); //0000,0000 T4 High Byte +#define _T4L 0xD3 +SFR(T4L, 0xD3); //0000,0000 T4 Low Byte +#define _T3H 0xD4 +SFR(T3H, 0xD4); //0000,0000 T3 High Byte +#define _T3L 0xD5 +SFR(T3L, 0xD5); //0000,0000 T3 Low Byte +#define _T2H 0xD6 +SFR(T2H, 0xD6); //0000,0000 T2 High Byte +#define _T2L 0xD7 +SFR(T2L, 0xD7); //0000,0000 T2 Low Byte +#define _WKTCL 0xAA +SFR(WKTCL, 0xAA); //0000,0000 Power Down Wakeup Timer Low Byte +#define _WKTCH 0xAB +SFR(WKTCH, 0xAB); //0000,0000 Power Down Wakeup Timer High Byte +#define _WDT_CONTR 0xC1 +SFR(WDT_CONTR, 0xC1); //0000,0000 Watchdog Control Register + +// Serial port special function register +#define _SCON 0x98 +SFR(SCON, 0x98); //0000,0000 Serial Port 1 Control Register +SBIT(SM0, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); +#define _SBUF 0x99 +SFR(SBUF, 0x99); //xxxx,xxxx Serial Port 1 Data Register +#define _S2CON 0x9A +SFR(S2CON, 0x9A); //0000,0000 Serial Port 2 Control Register +#define _S2BUF 0x9B +SFR(S2BUF, 0x9B); //xxxx,xxxx Serial Port 2 Data Register +#define _S3CON 0xAC +SFR(S3CON, 0xAC); //0000,0000 Serial Port 3 Control Register +#define _S3BUF 0xAD +SFR(S3BUF, 0xAD); //xxxx,xxxx Serial Port 3 Data Register +#define _S4CON 0x84 +SFR(S4CON, 0x84); //0000,0000 Serial Port 4 Control Register +#define _S4BUF 0x85 +SFR(S4BUF, 0x85); //xxxx,xxxx Serial Port 4 Data Register +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); //0000,0000 Slave Address Register +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); //0000,0000 Slave Address Mask Register + +// ADC Special Function Register +#define _ADC_CONTR 0xBC +SFR(ADC_CONTR, 0xBC); //0000,0000 A/D Conversion Control Register +#define _ADC_RES 0xBD +SFR(ADC_RES, 0xBD); //0000,0000 A/D Conversion Result High 8 Bits +#define _ADC_RESL 0xBE +SFR(ADC_RESL, 0xBE); //0000,0000 A/D Conversion Result Low 2 Bits + +// SPI Special Function Register +#define _SPSTAT 0xCD +SFR(SPSTAT, 0xCD); //00xx,xxxx SPI Status Register +#define _SPCTL 0xCE +SFR(SPCTL, 0xCE); //0000,0100 SPI Control Register +#define _SPDAT 0xCF +SFR(SPDAT, 0xCF); //0000,0000 SPI Data Register + +// IAP/ISP Special Function Register +#define _IAP_DATA 0xC2 +SFR(IAP_DATA, 0xC2); //0000,0000 EEPROM data register +#define _IAP_ADDRH 0xC3 +SFR(IAP_ADDRH, 0xC3); //0000,0000 EEPROM address high byte +#define _IAP_ADDRL 0xC4 +SFR(IAP_ADDRL, 0xC4); //0000,0000 EEPROM address low byte +#define _IAP_CMD 0xC5 +SFR(IAP_CMD, 0xC5); //xxxx,xx00 EEPROM Command Register +#define _IAP_TRIG 0xC6 +SFR(IAP_TRIG, 0xC6); //0000,0000 EEPRPM Command Trigger +#define _IAP_CONTR 0xC7 +SFR(IAP_CONTR, 0xC7); //0000,x000 EEPROM Control Register + +// PCA/PWM Special Function Register +#define _CCON 0xD8 +SFR(CCON, 0xD8); //00xx,xx00 PCA Control Register +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); //0xxx,x000 PCA Working Mode Register +#define _CL 0xE9 +SFR(CL, 0xE9); //0000,0000 PCA Counter Low Byte +#define _CH 0xF9 +SFR(CH, 0xF9); //0000,0000 PCA Counter High Byte +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); //0000,0000 PCA Module 0 PWM Register +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); //0000,0000 PCA Module 1 PWM Register +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); //0000,0000 PCA Module 2 PWM Register +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); //0000,0000 PCA Module 0 Capture/Compare Register Low Byte +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); //0000,0000 PCA Module 1 Capture/Compare Register Low Byte +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); //0000,0000 PCA Module 2 Capture/Compare Register Low Byte +#define _PCA_PWM0 0xF2 +SFR(PCA_PWM0, 0xF2); //xxxx,xx00 PCA Module 0 PWM Register +#define _PCA_PWM1 0xF3 +SFR(PCA_PWM1, 0xF3); //xxxx,xx00 PCA Module 1 PWM Register +#define _PCA_PWM2 0xF4 +SFR(PCA_PWM2, 0xF4); //xxxx,xx00 PCA Module 2 PWM Register +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); //0000,0000 PCA Module 0 Capture/Compare Register High Byte +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); //0000,0000 PCA Module 1 Capture/Compare Register High Byte +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); //0000,0000 PCA Module 2 Capture/Compare Register High Byte + +// Comparator Special Function Register +#define _CMPCR1 0xE6 +SFR(CMPCR1, 0xE6); //0000,0000 Comparator Control Register 1 +#define _CMPCR2 0xE7 +SFR(CMPCR2, 0xE7); //0000,0000 Comparator Control Register 2 + +// Enhanced PWM waveform generator special function register +#define _PWMCFG 0xF1 +SFR(PWMCFG, 0xF1); //x000,0000 PWM Special Function Register +#define _PWMCR 0xF5 +SFR(PWMCR, 0xF5); //0000,0000 PWM Control Register +#define _PWMIF 0xF6 +SFR(PWMIF, 0xF6); //x000,0000 Interrupt Flag Register +#define _PWMFDCR 0xF7 +SFR(PWMFDCR, 0xF7); //xx00,0000 PWM External Exception Detection Control Register + +// The following special function registers are in the extended RAM area. +// You need to set bit7 of P_SW2 to 1 to read and write them normally. +#define PWMC (*(unsigned int volatile xdata *)0xfff0) +#define PWMCH (*(unsigned char volatile xdata *)0xfff0) +#define PWMCL (*(unsigned char volatile xdata *)0xfff1) +#define PWMCKS (*(unsigned char volatile xdata *)0xfff2) +#define PWM2T1 (*(unsigned int volatile xdata *)0xff00) +#define PWM2T1H (*(unsigned char volatile xdata *)0xff00) +#define PWM2T1L (*(unsigned char volatile xdata *)0xff01) +#define PWM2T2 (*(unsigned int volatile xdata *)0xff02) +#define PWM2T2H (*(unsigned char volatile xdata *)0xff02) +#define PWM2T2L (*(unsigned char volatile xdata *)0xff03) +#define PWM2CR (*(unsigned char volatile xdata *)0xff04) +#define PWM3T1 (*(unsigned int volatile xdata *)0xff10) +#define PWM3T1H (*(unsigned char volatile xdata *)0xff10) +#define PWM3T1L (*(unsigned char volatile xdata *)0xff11) +#define PWM3T2 (*(unsigned int volatile xdata *)0xff12) +#define PWM3T2H (*(unsigned char volatile xdata *)0xff12) +#define PWM3T2L (*(unsigned char volatile xdata *)0xff13) +#define PWM3CR (*(unsigned char volatile xdata *)0xff14) +#define PWM4T1 (*(unsigned int volatile xdata *)0xff20) +#define PWM4T1H (*(unsigned char volatile xdata *)0xff20) +#define PWM4T1L (*(unsigned char volatile xdata *)0xff21) +#define PWM4T2 (*(unsigned int volatile xdata *)0xff22) +#define PWM4T2H (*(unsigned char volatile xdata *)0xff22) +#define PWM4T2L (*(unsigned char volatile xdata *)0xff23) +#define PWM4CR (*(unsigned char volatile xdata *)0xff24) +#define PWM5T1 (*(unsigned int volatile xdata *)0xff30) +#define PWM5T1H (*(unsigned char volatile xdata *)0xff30) +#define PWM5T1L (*(unsigned char volatile xdata *)0xff31) +#define PWM5T2 (*(unsigned int volatile xdata *)0xff32) +#define PWM5T2H (*(unsigned char volatile xdata *)0xff32) +#define PWM5T2L (*(unsigned char volatile xdata *)0xff33) +#define PWM5CR (*(unsigned char volatile xdata *)0xff34) +#define PWM6T1 (*(unsigned int volatile xdata *)0xff40) +#define PWM6T1H (*(unsigned char volatile xdata *)0xff40) +#define PWM6T1L (*(unsigned char volatile xdata *)0xff41) +#define PWM6T2 (*(unsigned int volatile xdata *)0xff42) +#define PWM6T2H (*(unsigned char volatile xdata *)0xff42) +#define PWM6T2L (*(unsigned char volatile xdata *)0xff43) +#define PWM6CR (*(unsigned char volatile xdata *)0xff44) +#define PWM7T1 (*(unsigned int volatile xdata *)0xff50) +#define PWM7T1H (*(unsigned char volatile xdata *)0xff50) +#define PWM7T1L (*(unsigned char volatile xdata *)0xff51) +#define PWM7T2 (*(unsigned int volatile xdata *)0xff52) +#define PWM7T2H (*(unsigned char volatile xdata *)0xff52) +#define PWM7T2L (*(unsigned char volatile xdata *)0xff53) +#define PWM7CR (*(unsigned char volatile xdata *)0xff54) + +#endif diff --git a/examples/anymcu-header/src/STC89xx.h b/examples/anymcu-header/src/STC89xx.h new file mode 100644 index 0000000..094667c --- /dev/null +++ b/examples/anymcu-header/src/STC89xx.h @@ -0,0 +1,298 @@ +#ifndef STC89xx_H +#define STC89xx_H + +#include + +// 适用于 STC89xx / STC90xx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR*/ + +/* + * #define _AUXR 0x8e + * SFR(AUXR, 0x8e); + * #define _AUXR1 0xa2 + * SFR(AUXR1, 0xa2); + * #define _IPH 0xb7 + * SFR(IPH, 0xb7); + */ + +#define _P4 0xe8 +SFR(P4, 0xe8); +SBIT(P46, _P4, 6); +SBIT(P45, _P4, 5); //ISP下载需勾选"ALE脚用作P4.5口" +SBIT(P44, _P4, 4); +SBIT(P43, _P4, 3); +SBIT(P42, _P4, 2); +SBIT(P41, _P4, 1); +SBIT(P40, _P4, 0); + +#define _XICON 0xc0 +SFR(XICON, 0xc0); + +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* Above is STC additional SFR */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* PCA SFR +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +*/ + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EC, _IE, 6); +SBIT(ET2, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +/* SBIT(PPC, _IP, 6);*/ +SBIT(PT2, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +/* P1 */ +/* PCA +SBIT(CEX4, _P1, 7); +SBIT(CEX3, _P1, 6); +SBIT(CEX2, _P1, 5); +SBIT(CEX1, _P1, 4); +SBIT(CEX0, _P1, 3); +SBIT(ECI, _P1, 2); +*/ + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* CCON */ +/* PCA +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); + +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +*/ + +#endif diff --git a/examples/anymcu-header/src/STC8Fxx.h b/examples/anymcu-header/src/STC8Fxx.h new file mode 100644 index 0000000..97b9f12 --- /dev/null +++ b/examples/anymcu-header/src/STC8Fxx.h @@ -0,0 +1,715 @@ +#ifndef STC8Fxx_H +#define STC8Fxx_H + +#include + +// 包含本头文件后,不用另外再包含"REG51.H" +// 适用于 STC8Fxx / STC8Axx 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +//内核特殊功能寄存器 +#define _ACC 0xe0 +SFR(ACC, 0xe0); +#define _B 0xf0 +SFR(B, 0xf0); +#define _PSW 0xd0 +SFR(PSW, 0xd0); +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _TA 0xae +SFR(TA, 0xae); +#define _DPS 0xe3 +SFR(DPS, 0xe3); +#define _DPL1 0xe4 +SFR(DPL1, 0xe4); +#define _DPH1 0xe5 +SFR(DPH1, 0xe5); + +//I/O 口特殊功能寄存器 +#define _P0 0x80 +SFR(P0, 0x80); +#define _P1 0x90 +SFR(P1, 0x90); +#define _P2 0xa0 +SFR(P2, 0xa0); +#define _P3 0xb0 +SFR(P3, 0xb0); +#define _P4 0xc0 +SFR(P4, 0xc0); +#define _P5 0xc8 +SFR(P5, 0xc8); +#define _P6 0xe8 +SFR(P6, 0xe8); +#define _P7 0xf8 +SFR(P7, 0xf8); +#define _P0M0 0x94 +SFR(P0M0, 0x94); +#define _P0M1 0x93 +SFR(P0M1, 0x93); +#define _P1M0 0x92 +SFR(P1M0, 0x92); +#define _P1M1 0x91 +SFR(P1M1, 0x91); +#define _P2M0 0x96 +SFR(P2M0, 0x96); +#define _P2M1 0x95 +SFR(P2M1, 0x95); +#define _P3M0 0xb2 +SFR(P3M0, 0xb2); +#define _P3M1 0xb1 +SFR(P3M1, 0xb1); +#define _P4M0 0xb4 +SFR(P4M0, 0xb4); +#define _P4M1 0xb3 +SFR(P4M1, 0xb3); +#define _P5M0 0xca +SFR(P5M0, 0xca); +#define _P5M1 0xc9 +SFR(P5M1, 0xc9); +#define _P6M0 0xcc +SFR(P6M0, 0xcc); +#define _P6M1 0xcb +SFR(P6M1, 0xcb); +#define _P7M0 0xe2 +SFR(P7M0, 0xe2); +#define _P7M1 0xe1 +SFR(P7M1, 0xe1); + +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +SBIT(P40, _P4, 0); +SBIT(P41, _P4, 1); +SBIT(P42, _P4, 2); +SBIT(P43, _P4, 3); +SBIT(P44, _P4, 4); +SBIT(P45, _P4, 5); +SBIT(P46, _P4, 6); +SBIT(P47, _P4, 7); +SBIT(P50, _P5, 0); +SBIT(P51, _P5, 1); +SBIT(P52, _P5, 2); +SBIT(P53, _P5, 3); +SBIT(P54, _P5, 4); +SBIT(P55, _P5, 5); +SBIT(P56, _P5, 6); +SBIT(P57, _P5, 7); +SBIT(P60, _P6, 0); +SBIT(P61, _P6, 1); +SBIT(P62, _P6, 2); +SBIT(P63, _P6, 3); +SBIT(P64, _P6, 4); +SBIT(P65, _P6, 5); +SBIT(P66, _P6, 6); +SBIT(P67, _P6, 7); +SBIT(P70, _P7, 0); +SBIT(P71, _P7, 1); +SBIT(P72, _P7, 2); +SBIT(P73, _P7, 3); +SBIT(P74, _P7, 4); +SBIT(P75, _P7, 5); +SBIT(P76, _P7, 6); +SBIT(P77, _P7, 7); + +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define P0PU (*(unsigned char volatile xdata *)0xfe10) +#define P1PU (*(unsigned char volatile xdata *)0xfe11) +#define P2PU (*(unsigned char volatile xdata *)0xfe12) +#define P3PU (*(unsigned char volatile xdata *)0xfe13) +#define P4PU (*(unsigned char volatile xdata *)0xfe14) +#define P5PU (*(unsigned char volatile xdata *)0xfe15) +#define P6PU (*(unsigned char volatile xdata *)0xfe16) +#define P7PU (*(unsigned char volatile xdata *)0xfe17) +#define P0NCS (*(unsigned char volatile xdata *)0xfe18) +#define P1NCS (*(unsigned char volatile xdata *)0xfe19) +#define P2NCS (*(unsigned char volatile xdata *)0xfe1a) +#define P3NCS (*(unsigned char volatile xdata *)0xfe1b) +#define P4NCS (*(unsigned char volatile xdata *)0xfe1c) +#define P5NCS (*(unsigned char volatile xdata *)0xfe1d) +#define P6NCS (*(unsigned char volatile xdata *)0xfe1e) +#define P7NCS (*(unsigned char volatile xdata *)0xfe1f) + +//系统管理特殊功能寄存器 +#define _PCON 0x87 +SFR(PCON, 0x87); +#define SMOD 0x80 +#define SMOD0 0x40 +#define LVDF 0x20 +#define POF 0x10 +#define GF1 0x08 +#define GF0 0x04 +#define PD 0x02 +#define IDL 0x01 +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define T0x12 0x80 +#define T1x12 0x40 +#define UART_M0x6 0x20 +#define T2R 0x10 +#define T2_CT 0x08 +#define T2x12 0x04 +#define EXTRAM 0x02 +#define S1ST2 0x01 +#define _AUXR2 0x97 +SFR(AUXR2, 0x97); +#define TXLNRX 0x10 +#define _BUS_SPEED 0xa1 +SFR(BUS_SPEED, 0xa1); +#define _P_SW1 0xa2 +SFR(P_SW1, 0xa2); +#define _P_SW2 0xba +SFR(P_SW2, 0xba); +#define EAXFR 0x80 +#define _VOCTRL 0xbb +SFR(VOCTRL, 0xbb); +#define _RSTCFG 0xff +SFR(RSTCFG, 0xff); + +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define CKSEL (*(unsigned char volatile xdata *)0xfe00) +#define CLKDIV (*(unsigned char volatile xdata *)0xfe01) +#define IRC24MCR (*(unsigned char volatile xdata *)0xfe02) +#define XOSCCR (*(unsigned char volatile xdata *)0xfe03) +#define IRC32KCR (*(unsigned char volatile xdata *)0xfe04) + +//中断特殊功能寄存器 +#define _IE 0xa8 +SFR(IE, 0xa8); +SBIT(EA, _IE, 7); +SBIT(ELVD, _IE, 6); +SBIT(EADC, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); +#define _IE2 0xaf +SFR(IE2, 0xaf); +#define ET4 0x40 +#define ET3 0x20 +#define ES4 0x10 +#define ES3 0x08 +#define ET2 0x04 +#define ESPI 0x02 +#define ES2 0x01 +#define _IP 0xb8 +SFR(IP, 0xb8); +SBIT(PPCA, _IP, 7); +SBIT(PLVD, _IP, 6); +SBIT(PADC, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); +#define _IP2 0xb5 +SFR(IP2, 0xb5); +#define PI2C 0x40 +#define PCMP 0x20 +#define PX4 0x10 +#define PPWMFD 0x08 +#define PPWM 0x04 +#define PSPI 0x02 +#define PS2 0x01 +#define _IPH 0xb7 +SFR(IPH, 0xb7); +#define PPCAH 0x80 +#define PLVDH 0x40 +#define PADCH 0x20 +#define PSH 0x10 +#define PT1H 0x08 +#define PX1H 0x04 +#define PT0H 0x02 +#define PX0H 0x01 +#define _IP2H 0xb6 +SFR(IP2H, 0xb6); +#define PI2CH 0x40 +#define PCMPH 0x20 +#define PX4H 0x10 +#define PPWMFDH 0x08 +#define PPWMH 0x04 +#define PSPIH 0x02 +#define PS2H 0x01 +#define _INTCLKO 0x8f +SFR(INTCLKO, 0x8f); +#define EX4 0x40 +#define EX3 0x20 +#define EX2 0x10 +#define T2CLKO 0x04 +#define T1CLKO 0x02 +#define T0CLKO 0x01 +#define _AUXINTIF 0xef +SFR(AUXINTIF, 0xef); +#define INT4IF 0x40 +#define INT3IF 0x20 +#define INT2IF 0x10 +#define T4IF 0x04 +#define T3IF 0x02 +#define T2IF 0x01 + +//定时器特殊功能寄存器 +#define _TCON 0x88 +SFR(TCON, 0x88); +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define T1_GATE 0x80 +#define T1_CT 0x40 +#define T1_M1 0x20 +#define T1_M0 0x10 +#define T0_GATE 0x08 +#define T0_CT 0x04 +#define T0_M1 0x02 +#define T0_M0 0x01 +#define _TL0 0x8a +SFR(TL0, 0x8a); +#define _TL1 0x8b +SFR(TL1, 0x8b); +#define _TH0 0x8c +SFR(TH0, 0x8c); +#define _TH1 0x8d +SFR(TH1, 0x8d); +#define _T4T3M 0xd1 +SFR(T4T3M, 0xd1); +#define T4R 0x80 +#define T4_CT 0x40 +#define T4x12 0x20 +#define T4CLKO 0x10 +#define T3R 0x08 +#define T3_CT 0x04 +#define T3x12 0x02 +#define T3CLKO 0x01 +#define _T4H 0xd2 +SFR(T4H, 0xd2); +#define _T4L 0xd3 +SFR(T4L, 0xd3); +#define _T3H 0xd4 +SFR(T3H, 0xd4); +#define _T3L 0xd5 +SFR(T3L, 0xd5); +#define _T2H 0xd6 +SFR(T2H, 0xd6); +#define _T2L 0xd7 +SFR(T2L, 0xd7); +#define _TH4 0xd2 +SFR(TH4, 0xd2); +#define _TL4 0xd3 +SFR(TL4, 0xd3); +#define _TH3 0xd4 +SFR(TH3, 0xd4); +#define _TL3 0xd5 +SFR(TL3, 0xd5); +#define _TH2 0xd6 +SFR(TH2, 0xd6); +#define _TL2 0xd7 +SFR(TL2, 0xd7); +#define _WKTCL 0xaa +SFR(WKTCL, 0xaa); +#define _WKTCH 0xab +SFR(WKTCH, 0xab); +#define WKTEN 0x80 +#define _WDT_CONTR 0xc1 +SFR(WDT_CONTR, 0xc1); +#define WDT_FLAG 0x80 +#define EN_WDT 0x20 +#define CLR_WDT 0x10 +#define IDL_WDT 0x08 + +//串行口特殊功能寄存器 +#define _SCON 0x98 +SFR(SCON, 0x98); +SBIT(SM0, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); +#define _SBUF 0x99 +SFR(SBUF, 0x99); +#define _S2CON 0x9a +SFR(S2CON, 0x9a); +#define S2SM0 0x80 +#define S2ST4 0x40 +#define S2SM2 0x20 +#define S2REN 0x10 +#define S2TB8 0x08 +#define S2RB8 0x04 +#define S2TI 0x02 +#define S2RI 0x01 +#define _S2BUF 0x9b +SFR(S2BUF, 0x9b); +#define _S3CON 0xac +SFR(S3CON, 0xac); +#define S3SM0 0x80 +#define S3ST4 0x40 +#define S3SM2 0x20 +#define S3REN 0x10 +#define S3TB8 0x08 +#define S3RB8 0x04 +#define S3TI 0x02 +#define S3RI 0x01 +#define _S3BUF 0xad +SFR(S3BUF, 0xad); +#define _S4CON 0x84 +SFR(S4CON, 0x84); +#define S4SM0 0x80 +#define S4ST4 0x40 +#define S4SM2 0x20 +#define S4REN 0x10 +#define S4TB8 0x08 +#define S4RB8 0x04 +#define S4TI 0x02 +#define S4RI 0x01 +#define _S4BUF 0x85 +SFR(S4BUF, 0x85); +#define _SADDR 0xa9 +SFR(SADDR, 0xa9); +#define _SADEN 0xb9 +SFR(SADEN, 0xb9); + +//ADC 特殊功能寄存器 +#define _ADC_CONTR 0xbc +SFR(ADC_CONTR, 0xbc); +#define ADC_POWER 0x80 +#define ADC_START 0x40 +#define ADC_FLAG 0x20 +#define _ADC_RES 0xbd +SFR(ADC_RES, 0xbd); +#define _ADC_RESL 0xbe +SFR(ADC_RESL, 0xbe); +#define _ADCCFG 0xde +SFR(ADCCFG, 0xde); +#define ADC_RESFMT 0x20 + +//SPI 特殊功能寄存器 +#define _SPSTAT 0xcd +SFR(SPSTAT, 0xcd); +#define SPIF 0x80 +#define WCOL 0x40 +#define _SPCTL 0xce +SFR(SPCTL, 0xce); +#define SSIG 0x80 +#define SPEN 0x40 +#define DORD 0x20 +#define MSTR 0x10 +#define CPOL 0x08 +#define CPHA 0x04 +#define _SPDAT 0xcf +SFR(SPDAT, 0xcf); + +//IAP/ISP 特殊功能寄存器 +#define _IAP_DATA 0xc2 +SFR(IAP_DATA, 0xc2); +#define _IAP_ADDRH 0xc3 +SFR(IAP_ADDRH, 0xc3); +#define _IAP_ADDRL 0xc4 +SFR(IAP_ADDRL, 0xc4); +#define _IAP_CMD 0xc5 +SFR(IAP_CMD, 0xc5); +#define IAP_IDL 0x00 +#define IAP_READ 0x01 +#define IAP_WRITE 0x02 +#define IAP_ERASE 0x03 +#define _IAP_TRIG 0xc6 +SFR(IAP_TRIG, 0xc6); +#define _IAP_CONTR 0xc7 +SFR(IAP_CONTR, 0xc7); +#define IAPEN 0x80 +#define SWBS 0x40 +#define SWRST 0x20 +#define CMD_FAIL 0x10 +#define _ISP_DATA 0xc2 +SFR(ISP_DATA, 0xc2); +#define _ISP_ADDRH 0xc3 +SFR(ISP_ADDRH, 0xc3); +#define _ISP_ADDRL 0xc4 +SFR(ISP_ADDRL, 0xc4); +#define _ISP_CMD 0xc5 +SFR(ISP_CMD, 0xc5); +#define _ISP_TRIG 0xc6 +SFR(ISP_TRIG, 0xc6); +#define _ISP_CONTR 0xc7 +SFR(ISP_CONTR, 0xc7); + +//比较器特殊功能寄存器 +#define _CMPCR1 0xe6 +SFR(CMPCR1, 0xe6); +#define CMPEN 0x80 +#define CMPIF 0x40 +#define PIE 0x20 +#define NIE 0x10 +#define PIS 0x08 +#define NIS 0x04 +#define CMPOE 0x02 +#define CMPRES 0x01 +#define _CMPCR2 0xe7 +SFR(CMPCR2, 0xe7); +#define INVCMPO 0x80 +#define DISFLT 0x40 + +//PCA/PWM 特殊功能寄存器 +#define _CCON 0xd8 +SFR(CCON, 0xd8); +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +#define _CMOD 0xd9 +SFR(CMOD, 0xd9); +#define CIDL 0x80 +#define ECF 0x01 +#define _CL 0xe9 +SFR(CL, 0xe9); +#define _CH 0xf9 +SFR(CH, 0xf9); +#define _CCAPM0 0xda +SFR(CCAPM0, 0xda); +#define ECOM0 0x40 +#define CCAPP0 0x20 +#define CCAPN0 0x10 +#define MAT0 0x08 +#define TOG0 0x04 +#define PWM0 0x02 +#define ECCF0 0x01 +#define _CCAPM1 0xdb +SFR(CCAPM1, 0xdb); +#define ECOM1 0x40 +#define CCAPP1 0x20 +#define CCAPN1 0x10 +#define MAT1 0x08 +#define TOG1 0x04 +#define PWM1 0x02 +#define ECCF1 0x01 +#define _CCAPM2 0xdc +SFR(CCAPM2, 0xdc); +#define ECOM2 0x40 +#define CCAPP2 0x20 +#define CCAPN2 0x10 +#define MAT2 0x08 +#define TOG2 0x04 +#define PWM2 0x02 +#define ECCF2 0x01 +#define _CCAPM3 0xdd +SFR(CCAPM3, 0xdd); +#define ECOM3 0x40 +#define CCAPP3 0x20 +#define CCAPN3 0x10 +#define MAT3 0x08 +#define TOG3 0x04 +#define PWM3 0x02 +#define ECCF3 0x01 +#define _CCAP0L 0xea +SFR(CCAP0L, 0xea); +#define _CCAP1L 0xeb +SFR(CCAP1L, 0xeb); +#define _CCAP2L 0xec +SFR(CCAP2L, 0xec); +#define _CCAP3L 0xed +SFR(CCAP3L, 0xed); +#define _CCAP0H 0xfa +SFR(CCAP0H, 0xfa); +#define _CCAP1H 0xfb +SFR(CCAP1H, 0xfb); +#define _CCAP2H 0xfc +SFR(CCAP2H, 0xfc); +#define _CCAP3H 0xfd +SFR(CCAP3H, 0xfd); +#define _PCA_PWM0 0xf2 +SFR(PCA_PWM0, 0xf2); +#define _PCA_PWM1 0xf3 +SFR(PCA_PWM1, 0xf3); +#define _PCA_PWM2 0xf4 +SFR(PCA_PWM2, 0xf4); +#define _PCA_PWM3 0xf5 +SFR(PCA_PWM3, 0xf5); + +//增强型PWM波形发生器特殊功能寄存器 +#define _PWMCFG 0xf1 +SFR(PWMCFG, 0xf1); +#define CBIF 0x80 +#define ETADC 0x40 +#define _PWMIF 0xf6 +SFR(PWMIF, 0xf6); +#define C7IF 0x80 +#define C6IF 0x40 +#define C5IF 0x20 +#define C4IF 0x10 +#define C3IF 0x08 +#define C2IF 0x04 +#define C1IF 0x02 +#define C0IF 0x01 +#define _PWMFDCR 0xf7 +SFR(PWMFDCR, 0xf7); +#define INVCMP 0x80 +#define INVIO 0x40 +#define ENFD 0x20 +#define FLTFLIO 0x10 +#define EFDI 0x08 +#define FDCMP 0x04 +#define FDIO 0x02 +#define FDIF 0x01 +#define _PWMCR 0xfe +SFR(PWMCR, 0xfe); +#define ENPWM 0x80 +#define ECBI 0x40 + +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define PWMC (*(unsigned int volatile xdata *)0xfff0) +#define PWMCH (*(unsigned char volatile xdata *)0xfff0) +#define PWMCL (*(unsigned char volatile xdata *)0xfff1) +#define PWMCKS (*(unsigned char volatile xdata *)0xfff2) +#define TADCP (*(unsigned char volatile xdata *)0xfff3) +#define TADCPH (*(unsigned char volatile xdata *)0xfff3) +#define TADCPL (*(unsigned char volatile xdata *)0xfff4) +#define PWM0T1 (*(unsigned int volatile xdata *)0xff00) +#define PWM0T1H (*(unsigned char volatile xdata *)0xff00) +#define PWM0T1L (*(unsigned char volatile xdata *)0xff01) +#define PWM0T2 (*(unsigned int volatile xdata *)0xff02) +#define PWM0T2H (*(unsigned char volatile xdata *)0xff02) +#define PWM0T2L (*(unsigned char volatile xdata *)0xff03) +#define PWM0CR (*(unsigned char volatile xdata *)0xff04) +#define PWM0HLD (*(unsigned char volatile xdata *)0xff05) +#define PWM1T1 (*(unsigned int volatile xdata *)0xff10) +#define PWM1T1H (*(unsigned char volatile xdata *)0xff10) +#define PWM1T1L (*(unsigned char volatile xdata *)0xff11) +#define PWM1T2 (*(unsigned int volatile xdata *)0xff12) +#define PWM1T2H (*(unsigned char volatile xdata *)0xff12) +#define PWM1T2L (*(unsigned char volatile xdata *)0xff13) +#define PWM1CR (*(unsigned char volatile xdata *)0xff14) +#define PWM1HLD (*(unsigned char volatile xdata *)0xff15) +#define PWM2T1 (*(unsigned int volatile xdata *)0xff20) +#define PWM2T1H (*(unsigned char volatile xdata *)0xff20) +#define PWM2T1L (*(unsigned char volatile xdata *)0xff21) +#define PWM2T2 (*(unsigned int volatile xdata *)0xff22) +#define PWM2T2H (*(unsigned char volatile xdata *)0xff22) +#define PWM2T2L (*(unsigned char volatile xdata *)0xff23) +#define PWM2CR (*(unsigned char volatile xdata *)0xff24) +#define PWM2HLD (*(unsigned char volatile xdata *)0xff25) +#define PWM3T1 (*(unsigned int volatile xdata *)0xff30) +#define PWM3T1H (*(unsigned char volatile xdata *)0xff30) +#define PWM3T1L (*(unsigned char volatile xdata *)0xff31) +#define PWM3T2 (*(unsigned int volatile xdata *)0xff32) +#define PWM3T2H (*(unsigned char volatile xdata *)0xff32) +#define PWM3T2L (*(unsigned char volatile xdata *)0xff33) +#define PWM3CR (*(unsigned char volatile xdata *)0xff34) +#define PWM3HLD (*(unsigned char volatile xdata *)0xff35) +#define PWM4T1 (*(unsigned int volatile xdata *)0xff40) +#define PWM4T1H (*(unsigned char volatile xdata *)0xff40) +#define PWM4T1L (*(unsigned char volatile xdata *)0xff41) +#define PWM4T2 (*(unsigned int volatile xdata *)0xff42) +#define PWM4T2H (*(unsigned char volatile xdata *)0xff42) +#define PWM4T2L (*(unsigned char volatile xdata *)0xff43) +#define PWM4CR (*(unsigned char volatile xdata *)0xff44) +#define PWM4HLD (*(unsigned char volatile xdata *)0xff45) +#define PWM5T1 (*(unsigned int volatile xdata *)0xff50) +#define PWM5T1H (*(unsigned char volatile xdata *)0xff50) +#define PWM5T1L (*(unsigned char volatile xdata *)0xff51) +#define PWM5T2 (*(unsigned int volatile xdata *)0xff52) +#define PWM5T2H (*(unsigned char volatile xdata *)0xff52) +#define PWM5T2L (*(unsigned char volatile xdata *)0xff53) +#define PWM5CR (*(unsigned char volatile xdata *)0xff54) +#define PWM5HLD (*(unsigned char volatile xdata *)0xff55) +#define PWM6T1 (*(unsigned int volatile xdata *)0xff60) +#define PWM6T1H (*(unsigned char volatile xdata *)0xff60) +#define PWM6T1L (*(unsigned char volatile xdata *)0xff61) +#define PWM6T2 (*(unsigned int volatile xdata *)0xff62) +#define PWM6T2H (*(unsigned char volatile xdata *)0xff62) +#define PWM6T2L (*(unsigned char volatile xdata *)0xff63) +#define PWM6CR (*(unsigned char volatile xdata *)0xff64) +#define PWM6HLD (*(unsigned char volatile xdata *)0xff65) +#define PWM7T1 (*(unsigned int volatile xdata *)0xff70) +#define PWM7T1H (*(unsigned char volatile xdata *)0xff70) +#define PWM7T1L (*(unsigned char volatile xdata *)0xff71) +#define PWM7T2 (*(unsigned int volatile xdata *)0xff72) +#define PWM7T2H (*(unsigned char volatile xdata *)0xff72) +#define PWM7T2L (*(unsigned char volatile xdata *)0xff73) +#define PWM7CR (*(unsigned char volatile xdata *)0xff74) +#define PWM7HLD (*(unsigned char volatile xdata *)0xff75) + +//I2C特殊功能寄存器 +//如下特殊功能寄存器位于扩展RAM区域 +//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写 +#define I2CCFG (*(unsigned char volatile xdata *)0xfe80) +#define ENI2C 0x80 +#define MSSL 0x40 +#define I2CMSCR (*(unsigned char volatile xdata *)0xfe81) +#define EMSI 0x80 +#define I2CMSST (*(unsigned char volatile xdata *)0xfe82) +#define MSBUSY 0x80 +#define MSIF 0x40 +#define MSACKI 0x02 +#define MSACKO 0x01 +#define I2CSLCR (*(unsigned char volatile xdata *)0xfe83) +#define ESTAI 0x40 +#define ERXI 0x20 +#define ETXI 0x10 +#define ESTOI 0x08 +#define SLRST 0x01 +#define I2CSLST (*(unsigned char volatile xdata *)0xfe84) +#define SLBUSY 0x80 +#define STAIF 0x40 +#define RXIF 0x20 +#define TXIF 0x10 +#define STOIF 0x08 +#define TXING 0x04 +#define SLACKI 0x02 +#define SLACKO 0x01 +#define I2CSLADR (*(unsigned char volatile xdata *)0xfe85) +#define I2CTXD (*(unsigned char volatile xdata *)0xfe86) +#define I2CRXD (*(unsigned char volatile xdata *)0xfe87) + +#endif diff --git a/examples/anymcu-header/src/STC90C5xAD.h b/examples/anymcu-header/src/STC90C5xAD.h new file mode 100644 index 0000000..0141a22 --- /dev/null +++ b/examples/anymcu-header/src/STC90C5xAD.h @@ -0,0 +1,298 @@ +#ifndef STC90C5xAD_H +#define STC90C5xAD_H + +#include + +// 适用于 STC90C5xAD 系列的芯片 +// Modified based on STC-ISP version by: ZnHoCn + +/* The following is STC additional SFR */ + +/* +#define _AUXR 0x8e +SFR(AUXR, 0x8e); +#define _AUXR1 0xa2 +SFR(AUXR1, 0xa2); +#define _IPH 0xb7 +SFR(IPH, 0xb7); +*/ + +#define _P4 0xc0 +SFR(P4, 0xc0); +SBIT(P46, _P4, 6); +SBIT(P45, _P4, 5); //ISP下载需勾选"ALE脚用作P4.5口" +SBIT(P44, _P4, 4); +SBIT(P43, _P4, 3); +SBIT(P42, _P4, 2); +SBIT(P41, _P4, 1); +SBIT(P40, _P4, 0); + +#define _XICON 0xe8 +SFR(XICON, 0xe8); + +#define _WDT_CONTR 0xe1 +SFR(WDT_CONTR, 0xe1); + +#define _ISP_DATA 0xe2 +SFR(ISP_DATA, 0xe2); +#define _ISP_ADDRH 0xe3 +SFR(ISP_ADDRH, 0xe3); +#define _ISP_ADDRL 0xe4 +SFR(ISP_ADDRL, 0xe4); +#define _ISP_CMD 0xe5 +SFR(ISP_CMD, 0xe5); +#define _ISP_TRIG 0xe6 +SFR(ISP_TRIG, 0xe6); +#define _ISP_CONTR 0xe7 +SFR(ISP_CONTR, 0xe7); + +/* Above is STC additional SFR */ + +/*-------------------------------------------------------------------------- +REG51F.H + +Header file for 8xC31/51, 80C51Fx, 80C51Rx+ +Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc. +All rights reserved. + +Modification according to DataSheet from April 1999 + - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives +--------------------------------------------------------------------------*/ + +/* BYTE Registers */ +#define _P0 0x80 +SFR(P0, 0x80); +SBIT(P00, _P0, 0); +SBIT(P01, _P0, 1); +SBIT(P02, _P0, 2); +SBIT(P03, _P0, 3); +SBIT(P04, _P0, 4); +SBIT(P05, _P0, 5); +SBIT(P06, _P0, 6); +SBIT(P07, _P0, 7); +#define _P1 0x90 +SFR(P1, 0x90); +SBIT(P10, _P1, 0); +SBIT(P11, _P1, 1); +SBIT(P12, _P1, 2); +SBIT(P13, _P1, 3); +SBIT(P14, _P1, 4); +SBIT(P15, _P1, 5); +SBIT(P16, _P1, 6); +SBIT(P17, _P1, 7); +#define _P2 0xA0 +SFR(P2, 0xA0); +SBIT(P20, _P2, 0); +SBIT(P21, _P2, 1); +SBIT(P22, _P2, 2); +SBIT(P23, _P2, 3); +SBIT(P24, _P2, 4); +SBIT(P25, _P2, 5); +SBIT(P26, _P2, 6); +SBIT(P27, _P2, 7); +#define _P3 0xB0 +SFR(P3, 0xB0); +SBIT(P30, _P3, 0); +SBIT(P31, _P3, 1); +SBIT(P32, _P3, 2); +SBIT(P33, _P3, 3); +SBIT(P34, _P3, 4); +SBIT(P35, _P3, 5); +SBIT(P36, _P3, 6); +SBIT(P37, _P3, 7); +#define _PSW 0xD0 +SFR(PSW, 0xD0); +#define _ACC 0xE0 +SFR(ACC, 0xE0); +#define _B 0xF0 +SFR(B, 0xF0); +#define _SP 0x81 +SFR(SP, 0x81); +#define _DPL 0x82 +SFR(DPL, 0x82); +#define _DPH 0x83 +SFR(DPH, 0x83); +#define _PCON 0x87 +SFR(PCON, 0x87); +#define _TCON 0x88 +SFR(TCON, 0x88); +#define _TMOD 0x89 +SFR(TMOD, 0x89); +#define _TL0 0x8A +SFR(TL0, 0x8A); +#define _TL1 0x8B +SFR(TL1, 0x8B); +#define _TH0 0x8C +SFR(TH0, 0x8C); +#define _TH1 0x8D +SFR(TH1, 0x8D); +#define _IE 0xA8 +SFR(IE, 0xA8); +#define _IP 0xB8 +SFR(IP, 0xB8); +#define _SCON 0x98 +SFR(SCON, 0x98); +#define _SBUF 0x99 +SFR(SBUF, 0x99); + +/* 80C51Fx/Rx Extensions */ +#define _AUXR 0x8E +SFR(AUXR, 0x8E); +#define _AUXR1 0xA2 +SFR(AUXR1, 0xA2); +#define _SADDR 0xA9 +SFR(SADDR, 0xA9); +#define _IPH 0xB7 +SFR(IPH, 0xB7); +#define _SADEN 0xB9 +SFR(SADEN, 0xB9); +#define _T2CON 0xC8 +SFR(T2CON, 0xC8); +#define _T2MOD 0xC9 +SFR(T2MOD, 0xC9); +#define _RCAP2L 0xCA +SFR(RCAP2L, 0xCA); +#define _RCAP2H 0xCB +SFR(RCAP2H, 0xCB); +#define _TL2 0xCC +SFR(TL2, 0xCC); +#define _TH2 0xCD +SFR(TH2, 0xCD); + +/* PCA SFR +#define _CCON 0xD8 +SFR(CCON, 0xD8); +#define _CMOD 0xD9 +SFR(CMOD, 0xD9); +#define _CCAPM0 0xDA +SFR(CCAPM0, 0xDA); +#define _CCAPM1 0xDB +SFR(CCAPM1, 0xDB); +#define _CCAPM2 0xDC +SFR(CCAPM2, 0xDC); +#define _CCAPM3 0xDD +SFR(CCAPM3, 0xDD); +#define _CCAPM4 0xDE +SFR(CCAPM4, 0xDE); +#define _CL 0xE9 +SFR(CL, 0xE9); +#define _CCAP0L 0xEA +SFR(CCAP0L, 0xEA); +#define _CCAP1L 0xEB +SFR(CCAP1L, 0xEB); +#define _CCAP2L 0xEC +SFR(CCAP2L, 0xEC); +#define _CCAP3L 0xED +SFR(CCAP3L, 0xED); +#define _CCAP4L 0xEE +SFR(CCAP4L, 0xEE); +#define _CH 0xF9 +SFR(CH, 0xF9); +#define _CCAP0H 0xFA +SFR(CCAP0H, 0xFA); +#define _CCAP1H 0xFB +SFR(CCAP1H, 0xFB); +#define _CCAP2H 0xFC +SFR(CCAP2H, 0xFC); +#define _CCAP3H 0xFD +SFR(CCAP3H, 0xFD); +#define _CCAP4H 0xFE +SFR(CCAP4H, 0xFE); +*/ + +/* BIT Registers */ +/* PSW */ +SBIT(CY, _PSW, 7); +SBIT(AC, _PSW, 6); +SBIT(F0, _PSW, 5); +SBIT(RS1, _PSW, 4); +SBIT(RS0, _PSW, 3); +SBIT(OV, _PSW, 2); +SBIT(P, _PSW, 0); + +/* TCON */ +SBIT(TF1, _TCON, 7); +SBIT(TR1, _TCON, 6); +SBIT(TF0, _TCON, 5); +SBIT(TR0, _TCON, 4); +SBIT(IE1, _TCON, 3); +SBIT(IT1, _TCON, 2); +SBIT(IE0, _TCON, 1); +SBIT(IT0, _TCON, 0); + +/* IE */ +SBIT(EA, _IE, 7); +SBIT(EC, _IE, 6); +SBIT(ET2, _IE, 5); +SBIT(ES, _IE, 4); +SBIT(ET1, _IE, 3); +SBIT(EX1, _IE, 2); +SBIT(ET0, _IE, 1); +SBIT(EX0, _IE, 0); + +/* IP */ +//SBIT(PPC, _IP, 6); +SBIT(PT2, _IP, 5); +SBIT(PS, _IP, 4); +SBIT(PT1, _IP, 3); +SBIT(PX1, _IP, 2); +SBIT(PT0, _IP, 1); +SBIT(PX0, _IP, 0); + +/* P3 */ +SBIT(RD, _P3, 7); +SBIT(WR, _P3, 6); +SBIT(T1, _P3, 5); +SBIT(T0, _P3, 4); +SBIT(INT1, _P3, 3); +SBIT(INT0, _P3, 2); +SBIT(TXD, _P3, 1); +SBIT(RXD, _P3, 0); + +/* SCON */ +SBIT(SM0, _SCON, 7); // alternatively "FE" +SBIT(FE, _SCON, 7); +SBIT(SM1, _SCON, 6); +SBIT(SM2, _SCON, 5); +SBIT(REN, _SCON, 4); +SBIT(TB8, _SCON, 3); +SBIT(RB8, _SCON, 2); +SBIT(TI, _SCON, 1); +SBIT(RI, _SCON, 0); + +/* P1 */ +/* PCA +SBIT(CEX4, _P1, 7); +SBIT(CEX3, _P1, 6); +SBIT(CEX2, _P1, 5); +SBIT(CEX1, _P1, 4); +SBIT(CEX0, _P1, 3); +SBIT(ECI, _P1, 2); +*/ + +SBIT(T2EX, _P1, 1); +SBIT(T2, _P1, 0); + +/* T2CON */ +SBIT(TF2, _T2CON, 7); +SBIT(EXF2, _T2CON, 6); +SBIT(RCLK, _T2CON, 5); +SBIT(TCLK, _T2CON, 4); +SBIT(EXEN2, _T2CON, 3); +SBIT(TR2, _T2CON, 2); +SBIT(C_T2, _T2CON, 1); +SBIT(CP_RL2, _T2CON, 0); + +/* CCON */ +/* PCA +SBIT(CF, _CCON, 7); +SBIT(CR, _CCON, 6); + +SBIT(CCF4, _CCON, 4); +SBIT(CCF3, _CCON, 3); +SBIT(CCF2, _CCON, 2); +SBIT(CCF1, _CCON, 1); +SBIT(CCF0, _CCON, 0); +*/ + +#endif diff --git a/examples/anymcu-header/src/main.c b/examples/anymcu-header/src/main.c new file mode 100644 index 0000000..e245b8e --- /dev/null +++ b/examples/anymcu-header/src/main.c @@ -0,0 +1,36 @@ +// Automatic header selection example for all mcs51 boards +// Your boardname.json should pass the MCU names shown below +// Include files by board name listed in alphabetical order: +#if defined(N76E003) + #include "n76e003.h" +#elif defined(STC15F10XW) + #include "STC15.h" +#elif defined(STC15F20XA) + #include "STC15.h" +#elif defined(STC15F2KXXS2) + #include "STC15.h" +#elif defined(STC15W10X) + #include "STC15.h" +#elif defined(STC15W20XS) + #include "STC15.h" +#elif defined(STC15W40XAS) + #include "STC15.h" +#elif defined(STC12C5AXXS2) + #include +#elif defined(STC89C5XRX) + #include +#elif defined(AT89S51) + #include +#elif defined(AT89S52) + #include +#elif defined(Generic8052) + #include "Generic8052.h" +#else // Assume Generic8051 + #include "Generic8051.h" +#endif + +void main() +{ + /* code */ + // return 0; +} diff --git a/examples/anymcu-header/test/README b/examples/anymcu-header/test/README new file mode 100644 index 0000000..df5066e --- /dev/null +++ b/examples/anymcu-header/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html From ca2e5787e08b6b2f4ddc51dd49dcfed90334ad91 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Mon, 11 Apr 2022 12:56:07 +0300 Subject: [PATCH 16/17] Update tool-stcgal to v1.6 // Resolve #32 --- platform.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/platform.json b/platform.json index bf3b5ac..314f5ad 100644 --- a/platform.json +++ b/platform.json @@ -18,7 +18,7 @@ "type": "git", "url": "https://github.com/platformio/platform-intel_mcs51.git" }, - "version": "1.2.3", + "version": "2.0.0-beta.1", "packages": { "toolchain-sdcc": { "type": "toolchain", @@ -29,7 +29,7 @@ "type": "uploader", "optional": true, "owner": "platformio", - "version": "~1.104.0" + "version": "~1.106.0" }, "tool-vnproch55x": { "type": "uploader", From e10ae55e46aa7ddf18289968aa4714b7f1601add Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Sun, 1 May 2022 19:03:00 +0300 Subject: [PATCH 17/17] Bump version to 2.0.0 --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index 314f5ad..03a1a9d 100644 --- a/platform.json +++ b/platform.json @@ -18,7 +18,7 @@ "type": "git", "url": "https://github.com/platformio/platform-intel_mcs51.git" }, - "version": "2.0.0-beta.1", + "version": "2.0.0", "packages": { "toolchain-sdcc": { "type": "toolchain",