Add LPC checksum in .bin file

[maxgerhardt]

Per this community topic (and related), the .bin file PlatformIO creates does not include the "LPC Image cheksum", as e.g. documented here. The first 7 entries of the vector table, interpreted as 4-byte little-endian integers, must be summed up (modulo 2^32), then the value ~summed_value + 1 must be written at offset 0x1c.

See

• https://github.com/ARMmbed/mbed-os/blob/d147abc3e556c58e5e343d34b729bc2192e18bd3/tools/targets/LPC.py
• https://github.com/basilfx/lpc_checksum/blob/master/lpc_checksum.py
• https://github.com/jxsl13/lpc1768_blinky_example/blob/master/extra_script.py

for code examples.

Without this checksum in the .bin file, if one takes that file and drag-and-drops it unto the virtual USB disk of the microcontroller for flashing, the firmware will refuse to run. It only works via OpenOCD flashing because OpenOCD detects that the checksum is missing and calculates and injects it last-minute before flashing.

Code should be added into the build logic of this platform to calculate and write the checksum into all .bin files for NXP LPC microcontrollers.

Note: This was already noticed in

#6 (comment)

But wasn't fixed in the platform code.

[valeros]

Thanks for pointing it out. Any idea what MCUs (or more generally CPUs) require this checksum? In the links I only found this line:

The reserved Cortex-M3 exception vector location 7

I tried to search for something similar where M0, M4 are mentioned, but to no avail.

[maxgerhardt]

The original source https://www.nxp.com/docs/en/user-guide/UM10360.pdf (page 627) talks about this checksum in reference to "LPC176x/5x Flash memory interface and programming", further in OpenOCD when searching for checksum, it reaveals that there are reference to a flash checksum in lpc2xxx.cfg and lpc1xxx.cfg.

Looking closer at what mbed-os does, it uses the patch() function in this code, where it is invoked for LPC4088 directly, but also referenced in here which thus executes the patch logic for all targets in the targets.json inheriting from LPCTarget, so that is the LPC1114, LPC1768, ARCH_PRO (LPC1768 based), LPC54114.

When I read the first link correctly it states

NXP LPC parts use a word in the vector table of the processor to store a checksum that is examined by the bootloader to identify a valid image. For ARM7/ARM9 based parts this checksum word is stored at offset 0x14, for Cortex-M based parts it is stored at offset 0x1C

So by that I read that as "every NXP LPC" part.

[valeros]

Many thanks for the research. Added as a post action to the final binary image.