The PLCT Lab had harrowing January. Within weeks since the easing of lock-down, PLCT members from all around China contacted COVID-19. Topics of daily conversations were occupied by reports of positive tests and fevers. Luckily, all PLCT and TARSIER members prevailed through this challenging time, as we entered the new normal.
But let's not forget what a fruitful December we've had last year. On December 9th, we held PLCT OpenDay 2022, our 4th open-day event. All recordings of events and presentations has been uploaded to Bilibili for your viewing pleasure. On December 28th and 29th, at the annual openEuler Summit, members of PLCT and TARSIER, who took active roles in building the commercial-targeted EulixOS 2.0-RV, also helped organizing the RISC-V sub-forum.
In related news, Liu Xin (刘鑫) from the TARSIER team also received the 2022 openEuler developer of the year (openEuler 年度之星) award for his long-term contributions. Congratulations to Liu Xin!
Finally, in consideration of the COVID-19 pandemic's impact on our team members, this monthly report was delayed to January 22th. In lieu of a New Year's greeting, let's take this moment to celebrate the Lunar New Year. We wish you happiness in the new year!
- PLCT OpenDay 2022 has concluded successfully. You may find the event recordings here.
- The Institute of Software announced "EulixOS 2.0-RV," built open openEuler community edition for RISC-V, at the Operating Systems Industry Summit (操作系统产业峰会).
- The RISC-V sub-forum was held successfully at the openEuler Summit.
- Qiu Ji, Lu Yahan, et. al.'s SpiderMonkey JIT RISC-V porting patchset was integrated into the Firefox browser shipped with openEuler RISC-V.
- 4128600: [riscv][regalloc] Port the rest part of "Resolve tail-call gap moves" | https://chromium-review.googlesource.com/c/v8/v8/+/4128600
- 4119766: [riscv][centry] Remove the unused SaveFPRegsMode parameter | https://chromium-review.googlesource.com/c/v8/v8/+/4119766
- 4114558: [riscv] Fix qfma test fail | https://chromium-review.googlesource.com/c/v8/v8/+/4114558
- 4074457: Reland "[riscv] Add tracepoint instructions to help simulator debug" | https://chromium-review.googlesource.com/c/v8/v8/+/4074457
- Fix the RFLAGS in riscv32.ad openjdk-riscv/jdk11u#577
- Fix the RegisterImpl::number_of_registers in riscv32.ad openjdk-riscv/jdk11u#578
- Fix the i2c and c2i adapter according arm 32bit openjdk-riscv/jdk11u#579
- Fix the x10/x11 in save/restore_native_result openjdk-riscv/jdk11u#582
- Issue reported: 64-bit data processing with
lfmv_w_x
/fmv_x_w
inrisv32.ad
, openjdk-riscv/jdk11u#580 - Presentation (Chinese):《OpenJDK for RV32G的解释器与C2》 https://github.com/shining1984/talks
- Pull requests to jdk-mainline:
- openjdk/jdk#11310 (8297476: Increase InlineSmallCode default from 1000 to 2500 for RISC-V)
- openjdk/jdk#11406 (8297715: RISC-V: C2: Use single-bit instructions from the Zbs extension)
- openjdk/jdk#11496 (8298055: AArch64: fastdebug build fails after JDK-8247645)
- openjdk/jdk#11631 (8298568: Fastdebug build fails after JDK-8296389)
- openjdk/jdk#11505 (8298088: RISC-V: Make Address a discriminated union internally)
- jdk-mainline pull requests reviewed:
- openjdk/jdk#11239 (8297238: RISC-V: C2: Use Matcher::vector_element_basic_type when checking for vector element type in predicate)
- openjdk/jdk#11276 (8297359: RISC-V: improve performance of floating Max Min intrinsics)
- openjdk/jdk#11344 (8297549: RISC-V: Support vloadcon instruction for Vector API)
- openjdk/jdk#11370 (8297644: RISC-V: Compilation error when shenandoah is disabled)
- openjdk/jdk#11388 (8297697: RISC-V: Add support for SATP mode detection)
- openjdk/jdk#11414 (8297763: Fix missing stub code expansion before align() in shared trampolines)
- openjdk/jdk#11453 (8297953: Fix several C2 IR matching tests for RISC-V)
- openjdk/jdk#11461 (8297967: Make frame::safe_for_sender safer)
- openjdk/jdk#11188 (8297036: Generalize C2 stub mechanism)
- openjdk/jdk#11502 (8298075: RISC-V: Implement post-call NOPs)
- openjdk/jdk#11577 (8298345: Fix another two C2 IR matching tests for RISC-V)
- openjdk/jdk#11432 (8297851: Add devkit for RISC-V)
- openjdk/jdk#11750 (8299168: RISC-V: Fix MachNode size mismatch for MacroAssembler::_verify_oops*)
- openjdk/jdk#11751 (8299172: RISC-V: [TESTBUG] Fix stack alignment logic in jvmci RISCV64TestAssembler.java)
- openjdk/jdk#11749 (8299162: Refactor shared trampoline emission logic)
- RISC-V port for Foreign-API:
- Work-in-progress pull requests rebased against
jdk-master
: openjdk/jdk#11004 (8293841: RISC-V: Implementation of Foreign Function & Memory API (Preview)). - Passed all jtreg foreign tests with fastdebug build on HiFive Unmatched.
- Internal code review in progress, will be ready for public code review at the end of December.
- RISC-V port for Generational-ZGC:
- Basic support contributed by Huawei: openjdk/zgc#10
- Needs rebasing against https://github.com/openjdk/zgc/tree/zgc_generational
- TODO: Add support for RVV extension.
- Upstreamed Changes.
- 8298342: RISC-V: RoundDoubleModeV does not use dynamic rounding mode correctly
- RISC-V: Enable v0 mask in vaddI_masked
- RISC-V: Fix vloadmask in c2
- RISC-V: Add rvv_compare function
- RISC-V: Add vfmerge_vfm and fix vmerge
- RISC-V: Add CMoveVF and CMoveVD
- RISC-V: expand reduce_add patterns into separate instructions
- Upstreamed changes.
- Debugging work for
javac
.
- [Fix a typo in os_linux.cpp] axiangyushanhaijing/powerpoint#233
- [Fix macros about RISCV] axiangyushanhaijing/powerpoint#234
- [Fix index_check and delete condy_helper] axiangyushanhaijing/powerpoint#235
- [Fix CAN_SHOW_REGISTERS_ON_ASSERT by JDK-8004124] axiangyushanhaijing/powerpoint#236
- [Fix MethodHandles::verify_klass by KlassHandle replace with Klass]axiangyushanhaijing/powerpoint#237
- [Fix generate_uncommon_trap_blob and SharedRuntime::generate_native_wrapper]axiangyushanhaijing/powerpoint#238
- [Fix based on pr235]axiangyushanhaijing/powerpoint#239
- [Fix generate_generic_copy]axiangyushanhaijing/powerpoint#240
- [Fix templateInterpreterGenerator_riscv64.cpp]axiangyushanhaijing/powerpoint#241
- [Fix stubGenerator_riscv64.cpp]axiangyushanhaijing/powerpoint#242
- [Fix vtableStubs_riscv64.cpp]axiangyushanhaijing/powerpoint#243
- [Fix .java to support riscv64]axiangyushanhaijing/powerpoint#246
- [Fix HSDB.java to support riscv64]axiangyushanhaijing/powerpoint#247
- [Fix LinuxDebuggerLocal.c & libproc.h]axiangyushanhaijing/powerpoint#249
- [Fix NativeMovConstReg::set_data]axiangyushanhaijing/powerpoint#250
- [debug.cpp help() is missing a riscv64 line for pns]axiangyushanhaijing/powerpoint#251
- [Fix thread_state to support rv64]axiangyushanhaijing/powerpoint#252
- [Delete popframe_move_outgoing_args for rv64]axiangyushanhaijing/powerpoint#255
- [Fix LinuxCDebugger.java to add riscv64]axiangyushanhaijing/powerpoint#256
- [Fix os::Linux::clock_init()/os::Linux::sched_getcpu_syscall(void) by deleting defined(RISCV64)]
- [Add riscv64 for unaligned in ByteArrayAccess.java]axiangyushanhaijing/powerpoint#258
- [Add generate_dtrace_nmethod for riscv64]axiangyushanhaijing/powerpoint#259
- Debugging work for C1 and C2.
- [Delete defined(RISCV64) in LIR_OpVisitState::visit] axiangyushanhaijing/powerpoint#216
- [Fix hotspot/src/share/vm/c1/c1_LinearScan.cpp]axiangyushanhaijing/powerpoint#217
- [Fix CounterOverflowStub::emit_code]axiangyushanhaijing/powerpoint#218
- [Add NO_FLAG_REG for cmp_mem_int]axiangyushanhaijing/powerpoint#223
- [Fix delete_unnecessary_jumps]axiangyushanhaijing/powerpoint#226
- [Fix c1_LIR.hpp to initial rv64g backend support]axiangyushanhaijing/powerpoint#228
- [Fix ideal_reg to add rv64g backend support]axiangyushanhaijing/powerpoint#229
- [Add HAS_FLAGREG_ONLY in LIR_Op2::verify() for rv64 support]axiangyushanhaijing/powerpoint#230
- [Fix __branch]axiangyushanhaijing/powerpoint#232
- Upstreamed patches.
- https://reviews.llvm.org/D139930 [InstCombine] Combine ZExt (B - A) + ZExt(A) to ZExt(B)
- https://reviews.llvm.org/D140405 [CVP] Simplify SRem when constantrange abs(lhs) < abs(rhs)
- https://reviews.llvm.org/D139289 [SCCP] Propagate equality of a not-constant
- https://reviews.llvm.org/D138269 [LoopFusion] Exit early if one of fusion candidate has guarded branch but the another has not
- https://reviews.llvm.org/D138743 [flang] Diagnostic for shape argument in c_f_pointer
- https://reviews.llvm.org/D139272 [RISCV]Keep (select c, 0/-1, X) during PerformDAGCombine
- https://reviews.llvm.org/D139004 [OpenMP][LegacyPM] Remove OpenMPOptCGSCCLegacyPass
- https://reviews.llvm.org/D139294 [LLDB][RISCV] Add RV64F instruction support for EmulateInstructionRISCV
- https://reviews.llvm.org/D139390 [LLDB][RISCV] Add RV32FC instruction support for EmulateInstructionRISCV
- https://reviews.llvm.org/D140092 [NFC][LLDB] Using namespace llvm in EmulateInstructionRISCV
- https://reviews.llvm.org/D140032 [LLDB][RISCV] Add RVD instruction support for EmulateInstructionRISCV
Please stay tuned.
Please stay tuned.
- Helped review and verified implementation of the vector crypto extension, discussed the ZVK extension's relation to the V, ZVE, and K extensions:
- Submitted patch for RV64-ILP32 support, revisions pending:
- Rebase in-progress for the intrinsic components for the scalar crypto extension. This component should be submitted to the upstream when intrinsic naming standards are merged there:
- Helped verifying RVV patches and recorded optimisation issues on Bugzilla:
- Final review pending for psABI changes in the Zcmt extension, credit goes to Lin Sinan (林思南):
- Discussion pending for RISC-V Profiles implementation. Current discussion focuses on the form in which profiles would be implemented in
-march
and how optional extensions should be supported.- We intend to print compiler warnings for potential compatibility issues. Users to resolve issues manually.
- riscv-non-isa/riscv-toolchain-conventions#26
- Slide decks from the last RISC-V GNU Toolchain biweekly meeting.
Please stay tuned.
- Arch Linux RISC-V Porting Status available at the Arch Linux RISC-V page.
- [core] 254 / 261 (97.31%)
- [extra] 2860 / 3081 (92.82%)
- [community] 8842 / 9874 (89.54%)
- Git Repository for Arch Linux RISC-V package patches, archriscv-packages. A total of 63 Pull Requests were submitted or merged for archriscv.
- Upstream:
- Issues:
- Blog:
Stats: 8044/19560, 41.12% (https://whale.plctlab.org/riscv/support-statistics/)
- A total of 35 keywording commits (include non-PLCT team members): https://whale.plctlab.org/riscv/stats/2022_12.txt
- dev-ruby/rails: Keyword 6.1.7 riscv, gentoo/gentoo@7851644
- dev-util/trace-cmd: Keyword 3.1.5 riscv, gentoo/gentoo@0acbe1c
- dev-vcs/stgit: Keyword 2.0.3 riscv, gentoo/gentoo@d6bbd5c
- dev-util/crash-8.0.2: version bump, and add riscv64 support, gentoo/gentoo@79b1ca7
- sys-cluster/mpich: Keyword 3.4.3 riscv, PR created, gentoo/gentoo#28595
- New stage3 image for Lichee RV Dock:
- WIP
- sys-cluster/ceph: fixed the atomic issue, built successfully through qemu-user
- slurp: fix cross compilation NixOS/nixpkgs#205726
- spice-gtk: fix cross compilation NixOS/nixpkgs#205728
- bgpdump: fix cross compilation NixOS/nixpkgs#206342
- iperf2: fix cross compilation NixOS/nixpkgs#206343
- libcgroup: fix cross compilation NixOS/nixpkgs#206344
- ndppd: fix cross compilation NixOS/nixpkgs#206649
- libva1: fix cross compilation NixOS/nixpkgs#206650
- protobufc: fix cross compilation NixOS/nixpkgs#208083
- binutils: gold is not available for riscv target NixOS/nixpkgs#208318
- mpir, gf2x: fix cross compilation NixOS/nixpkgs#208319
- rustPlatform.bindgenHook: use the same clang/libclang as rustc NixOS/nixpkgs#207352
Submitted a patch to the upstream to add riscv64 backend.r=jandem https://phabricator.services.mozilla.com/D161986.
Upstream did not review this change due to the holidays.
Preliminary support for RV64GC is now implemented in DynamoRIO, which will now build on RV64GC (basic decoding is now supported).
Current five-stage road map for DyanmoRIO's RV64GC support:
- Introduce RISC-V platform-specific functions, frameworks, definitions, etc., allowing DynamoRIO to build on RISC-V. (Done)
- Setup RISC-V CI for automated compilation and testing. (In Progress)
- Refine RISC-V platform-specific functions and definitions, make DynamoRIO's built-in example tools functional. (In Progress)
- Refine RISC-V unit- and feature-tests, setup CI for automated testing and instruments for long-term maintenance.
- Continue RISC-V feature enablement for more complex programs, prepare for long-term maintenance.
See https://gist.github.com/bekcpear/7c9e710ee5b674888fcf5e5d8445dc16 for a more detailed to-do list.
OpenCV 4.7.0 was released with a...
New universal intrinsics backend for scalable vector instructions. The first scalable implementation for RISC-V RVV 1.0.
In 2023, we will focus on refactoring and migrating existing unified vector instruction codes. This will materialise in performance improvements for compute-intensive algorithms on RVV-enabled devices. Meanwhile, we will collaborate with the XiangShan processor team to better test and optimise the OpenCV RVV backend.
Other RISC-V related patches:
- Compiled documentation for current simd library implementation, published as the repository's README file.
- Packaged current implementation and submitted a preliminary version to the upstream.
- Refactored and revised code in accordance with suggestions from the LLVM upstream reviewers.
- Added tests for the default constructors.
LuaJIT in the interpreter mode now appears to be functional, passing 301/304 tests of LuaJIT/LuaJIT-test-cleanup@9c27a59. This is on par with other architecture without FFI and JIT support.
- DynASM
- Fix more instruction templates.
- Improve RISC-V ISA/ISE support scheme infiWang/LuaJIT@9a13444.
- LuaJIT.
- Fixed LJVM runtime and library.
- Fixed BC_IS[LT,LE,GT,GE] infiWang/LuaJIT@a10a00e.
- Fixed bit.swap infiWang/LuaJIT@1a7807c.
- Improved LuaJIT runtime.
- Pseudo-GOT for libc linking infiWang/LuaJIT@c32c219
- Fixed LJVM runtime and library.
- RVV
- Submitted patch to upstream. Currently splitting the patches and revising code in accordance with suggestions from the reviewers.
- Fixed the Zc* extensions and variable misa.C.
- Added support for variable XLEN.
- Updated the Zc* extensions to v9.
- Updated ACT support for the CMO extension.
Shi Ninging (史宁宁) continues to work on compiling the OpenArkCompiler Weekly, which just published its 136th issue.
You may find new weekly issues of the OpenArkCompiler Weekly on Sundays on...
- GitHub: https://github.com/isrc-cas/arkcompiler-materials
- Zhihu: https://zhuanlan.zhihu.com/openarkcompiler
- Bilibili: https://www.bilibili.com/read/readlist/rl199373
- Mailing list and other channels: https://gitee.com/openarkcompiler/OpenArkCompiler/issues/I1EWAX
Please stay tuned.
Please stay tuned.
Please stay tuned.
Please stay tuned.
Please stay tuned.
Please stay tuned.
- Added Vim swap files to .gitignore, reference
- Updated debug trigger, added type2 support, endianness support (csr definitions implemented with struct bit-fields caused endianness issues, bit operations were used to workaround this issue), reference
- Synchronize PMP settings with virtual memory system, adding synchronization instructions to
sbi_hart_pmp_configure
, reference - Rewrite
fdt_find_match
withfdt_find_node
infw_platform_lookup_special
to improve code readability, reference - Fixed
fdt_parse_region
to avoid bit shift overflow, reference - Fixed logical errors in error handling in
__fdt_parse_region
, reference - Detects whether the region in fdt is valid through
sbi_is_region_valid
, the original code only detects region->order, reference - Use
env
to invoke Bash in shebang, as Bash in FreeBSD is installed at/usr/local/bin/bash
, reference - Added clint support for T-Head c9xx, also specified c9xx mtime features using a quirk, reference
- Added Zisslpcfi support to opensbi, reference
- Updated core selection method during cold boot, replacing pre-processed behaviours to specifying using fdt, reference
- Split PMP permissions into M and SU modes (PMP lock is effective for M mode, but it also allows for access by lower privilege modes), reference
- Updated PMU property names in documentation, renamed
event-to-mhpmevent
asriscv,event-to-mhpmevent
,reference - Updated documentation to remove the MCOUNTINHIBIT requirement for PMU extension implementations, reference
- Dropped
-N
switch from linker flags. This flag creates singular load segments, resulting in segments with RWX permissions and an error inld
2.39, reference - Allow custom HTIF base address for RV32, reference
- sbi_hsm: Rename
priv
argument toarg1
, reference
Please stay tuned.
Please stay tuned.
Please stay tuned.
- Reported an issue where LAVA jobs could not complete execution using the
hifive-unleashed-a00.jinja2
device type template: kernelci/lava-docker#162- Upstream identified a bug in the
hifive-unleashed-a00.jinja2
device type template, where upon device reboot, the serial port disappears.
- Upstream identified a bug in the
- Learned to use Python module
labgrid
and attempted (unsuccessfully) to control serial communication using this module. - Tested the Cloud-V CI interface and reported an issue to apply for an account: 10x-Engineers/riscv-ci-partners#27
- Learned to use KUnit and compiled notes on the process(Chinese), https://zhuanlan.zhihu.com/p/594717218
- Wrote an Ubuntu 22.10 image for a LicheeRV board, built and ran Unixbench, and compiled notes on the process (Chinese), https://zhuanlan.zhihu.com/p/595281400
New members joined the eBPF team, but most caught COVID.
- (Merged )libbpf-tools: fix uprobe helper possible overflow, reference
- [Draft] Add bcc frontend action to convert BCC style source to libbpf style source, reference
- Discussed project roadmap at OpenEuler, OpenAnolis, and various other places, 0.4.0-draft-roadmap
- Imported
eunomia-bpf
as a user mode development library for Coolbpf (Aliyun's eBPF development framework), reference - Attempted to reimplement a PoC tool for converting
bcc
-type kernel mode code tolibbpf
kernel mode code. This will allow "write once, run everywhere" and AOT features when usingbcc
-type kernel mode code in eunomia-bpf, eunomia-bpf/bcc - Rewrote some
ecli
command line tools in Rust, Add ecli-rs - Wrote the first development tutorial for libbpf-based eBPF tools and attempted to generate an eBPF program using ChatGPT, reference
- Added a few code analysing tools in CI (deepsource and codefactor) to help improve code quality and iron out minor issues discovered in the process.
- Added
codecov
to CI, improving unit test coverage from ~20% to 77%, codecov
- PLCT's 2022 Roadmap, https://github.com/plctlab/PLCT-Weekly/blob/master/PLCT-Roadmap-2022.md
- Open job positions at the PLCT Lab, https://github.com/plctlab/PLCT-Weekly/blob/master/Jobs.md
- Open intern positions at the PLCT Lab, https://github.com/plctlab/weloveinterns/blob/master/open-internships.md
- PLCT Weekly Reports, https://github.com/isrc-cas/PLCT-Weekly
- PLCT Open Reports (incomplete), https://github.com/isrc-cas/PLCT-Open-Reports