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This Month in PLCT: Issue 45 (May 1, 2023)

Preface

April has been a busy month for the PLCT Lab, as we participated in many RISC-V and compiler technology-related conferences. There, we met many old and new friends. Currently, the RVCN Summit has started calling for papers and is shaping up to be the largest and busiest third summit.

On the ecosystem side, Wu Wei 吴伟, the PLCT Lab Supervisor announced the "towards one million RISC-V developers" initiative. A crazy outlook, but one that reflects great optimism. We will continue to go all-in for RISC-V's future.

Featured Items

V8 for RISC-V

OpenJDK Upstreaming (RV64)

OpenJDK Upstreaming (Zhang Dingli [张定立])

OpenJDK Upstreaming (Cao Gui [曹贵])

OpenJDK8 Porting (Zhang Xiang [章翔])

Clang/LLVM RISC-V Porting

gollvm

Four of our patches received reviews, we are working to update them according to the suggestions received.

GNU Toolchain

  • GCC 13 was released on April 26th. You may find a list of RISC-V-related changes on the "RISC-V" section ChangeLog.
  • Submitted a proposal for RISC-V Profiles implementation in the GNU toolchain, see our draft.
  • Continuing maintenance for RVV intrinsic-test-generator, see the code repository.
  • Submitted GCC patch for the ZC extension, currently under review.
  • Drafted documentation to outline RISC-V extension version control implementation in the GNU toolchain.
  • Fixed an issue where --with-isa-spec options are inconsistent in our RISC-V GNU toolchain repository, we have updated the option specification to version 20191213.
  • Continuing to fix errors found in regression testing, see patch.
  • Slides from the bi-weekly RISC-V GNU Toolchain meetings.

Arch Linux for RISC-V

No update this month.

Gentoo for RISC-V

Stats: 7801/18716, 41.68% (https://whale.plctlab.org/riscv/support-statistics/)

Nixpkgs for RISC-V

Firefox (SpiderMonkey) for RV64GCV

DynamoRIO for RV64GC

This month, we focused on implementing and improving basic DynamoRIO instructions to prepare for drrun support.

OpenCV for RISC-V

In the past year, to implement the variable-length RISC-V Vector backend, we introduced incompatible API changes to the OpenCV Universal Intrinsic, leaving about 400 code changes to migrate in the source tree.

Since manual migration would take considerable labor, we are developing an automated Universal Intrinsic code migrator. Last month, we finished its prototype design, see the code repository.

LIBCXX Experimental/simd

LuaJIT for RV64G

This month, we focused on troubleshooting the JIT backend, particularly the IR assembler.

We made preliminary adjustments to the tracing number handler to better fit RISC-V and fixed some IR assembler bugs. Exit number handling scheme is expected to have more changes later.

The LuaJIT/LuaJIT-test-cleanup benchmark suite reveals more anomalies, such as binary-trees is slower than interpreter and nsieve-bit produce wrong result. This would be our focus in May.

gem5

No update this month.

Spike

QEMU

box64

This month, we continued to improve box64's RISC-V JIT dynamic recompiler. At the time of writing, we implemented support for frequently-used instructions, most applications may run as intended with dynamic recompiler. In comparison to the ~1040 instructions supported by the ARM64 backend, the RV64 backend currently supports ~580 instructions.

We tested some games on the VisionFive 2. Some games now runs smoothly on the development board, such as the Mono-based Stardew Valley. Wine64 also runs correctly.

The follows are the pull requests that were merged upstream.

Other Support for RISC-V International

SAIL/ACT

OpenArkCompiler Community

Shi Ninging (史宁宁) continues to work on compiling the OpenArkCompiler Weekly, which just published its 159th issue.

You may find new weekly issues of the OpenArkCompiler Weekly on Sundays on...

MLIR

Upstream Work

  • [WIP] New proposal for Vector Mask and Dynamic VL - we completed performance benchmark for proposal 1 and are currently writing a demo program for proposal 3.
    • Integrate vector length configuration with the current mask operation.
    • Create a standalone vector length operation.
    • Integrate dynamic vector representation into ODS.

Buddy Compiler

buddy-caas

buddy-mlir

Code repository: https://github.com/buddy-compiler/buddy-mlir

buddy-benchmark

Code repository: https://github.com/buddy-compiler/buddy-benchmark

Chisel/FIRRTL（CAAT 小队）

coreboot for riscv

No update this month.

openocd

No update this month.

opensbi

ebpf

u-boot

No update this month.

Aya Theorem Prover

No update this month.

RISC-V Platform Evaluation

In order to profile RISC-V compiler performance, we implemented an automated test script for SPEC CPU2017, which downloads and builds GCC/LLVM, runs the benchmarks, and collects results. You may find the script here.

With this we ran CPU2017 tests using LLVM 17.0.0 and GCC 12.1.0. GCC 12.2.0 failed to build, an issue has thus been reported.

screenshot

Testing and Development

  • Implemented automation scripts which operates and collects OBS data. Script to delete specific packages from OBS projects via API
  • Assembled slides for openEuler community's QA SIG investigation reports on unixbench，stream，fio，netperf，lmbench.
  • Deployed Kernel CI.
    • Periodically build and release kernel images using GitHub Actions, see script and released images.
    • Patched lava-docker source code and deployed Lava.
    • Successfully booted kernel under Qemu riscv64 using Github Actions + Lava, as well as building and running a Hello World program.
    • Added Unmatched to Lava to run jobs. We are currently ironing out issues with running jobs on this device.

RVLab

Under re-organization, no update this month.

Useful Links