From 80e9d17f7e28b67346398a23451b27b7b40682d0 Mon Sep 17 00:00:00 2001 From: M31864 Date: Fri, 20 May 2022 13:48:03 +0100 Subject: [PATCH] Additional configuration fixes Update the clocks and resets used by the streaming demo to point to the update clock configuration used by the design. Re-add the AXI stream demo argument as this was accidentally removed in a previous commit --- MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl | 8 ++++++++ .../AXI4_STREAM_DATA_GENERATOR.tcl | 8 ++++---- .../AXI4_STREAM_DATA_GENERATOR_BFM.tcl | 16 ++++++++-------- script_support/simulation/Test_bench.tcl | 2 +- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl b/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl index 86bbb58..f8abdd7 100644 --- a/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl +++ b/MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl @@ -220,6 +220,14 @@ if {[info exists BFM_SIMULATION]} { source script_support/simulation/Test_bench.tcl } +if {[info exists AXI4_STREAM_DEMO]} { + if {[info exists BFM_SIMULATION]} { + source script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl + } else { + source script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl + } +} + if {[info exists I2C_LOOPBACK]} { if {[file isdirectory $local_dir/script_support/components/MSS_I2C_LOOPBACK]} { file delete -force $local_dir/script_support/components/MSS_I2C_LOOPBACK diff --git a/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl b/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl index 43a5b53..9044e6d 100644 --- a/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl +++ b/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl @@ -47,12 +47,12 @@ sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"DMA_CONTROLL sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"DMA_CONTROLLER:TDEST" "AXI4_STREAM_DATA_GENERATOR_0:TDEST"} # connecting ACLK and reset -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_125MHz" "AXI4_STREAM_DATA_GENERATOR_0:ACLK"} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_CLK_125MHz" "AXI4_STREAM_DATA_GENERATOR_0:RSTN"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"DMA_CONTROLLER:CLOCK" "AXI4_STREAM_DATA_GENERATOR_0:ACLK"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"DMA_CONTROLLER:RESETN" "AXI4_STREAM_DATA_GENERATOR_0:RSTN"} # connecting the PCLK and PRESET_n -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_62_5MHz" "AXI4_STREAM_DATA_GENERATOR_0:PCLK"} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_CLK_62_5MHz" "AXI4_STREAM_DATA_GENERATOR_0:PRESETN"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:FIC_3_CLK" "AXI4_STREAM_DATA_GENERATOR_0:PCLK"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_FIC_3_CLK" "AXI4_STREAM_DATA_GENERATOR_0:PRESETN"} save_smartdesign -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} generate_component -component_name {MPFS_ICICLE_KIT_BASE_DESIGN} -recursive 0 build_design_hierarchy diff --git a/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl b/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl index b28b52b..daa63a6 100644 --- a/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl +++ b/script_support/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl @@ -27,14 +27,14 @@ sd_update_instance -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -instance_name {FIC0_I # Instantiate the AXI interconnect create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -component_name {COREAXI4INTERCONNECT_C0} -params {"ADDR_WIDTH:32" "CROSSBAR_MODE:0" "DATA_WIDTH:32" "DWC_ADDR_FIFO_DEPTH_CEILING:10" "ID_WIDTH:8" "MASTER0_CHAN_RS:true" "MASTER0_CLOCK_DOMAIN_CROSSING:false" "MASTER0_DATA_WIDTH:32" "MASTER0_DWC_DATA_FIFO_DEPTH:16" "MASTER0_READ_INTERLEAVE:false" "MASTER0_READ_SLAVE0:true" "MASTER0_READ_SLAVE10:true" "MASTER0_READ_SLAVE11:true" "MASTER0_READ_SLAVE12:true" "MASTER0_READ_SLAVE13:true" "MASTER0_READ_SLAVE14:true" "MASTER0_READ_SLAVE15:true" "MASTER0_READ_SLAVE16:true" "MASTER0_READ_SLAVE17:true" "MASTER0_READ_SLAVE18:true" "MASTER0_READ_SLAVE19:true" "MASTER0_READ_SLAVE1:true" "MASTER0_READ_SLAVE20:true" "MASTER0_READ_SLAVE21:true" "MASTER0_READ_SLAVE22:true" "MASTER0_READ_SLAVE23:true" "MASTER0_READ_SLAVE24:true" "MASTER0_READ_SLAVE25:true" "MASTER0_READ_SLAVE26:true" "MASTER0_READ_SLAVE27:true" "MASTER0_READ_SLAVE28:true" "MASTER0_READ_SLAVE29:true" "MASTER0_READ_SLAVE2:true" "MASTER0_READ_SLAVE30:true" "MASTER0_READ_SLAVE31:true" "MASTER0_READ_SLAVE3:true" "MASTER0_READ_SLAVE4:true" "MASTER0_READ_SLAVE5:true" "MASTER0_READ_SLAVE6:true" "MASTER0_READ_SLAVE7:true" "MASTER0_READ_SLAVE8:true" "MASTER0_READ_SLAVE9:true" "MASTER0_TYPE:0" "MASTER0_WRITE_SLAVE0:true" "MASTER0_WRITE_SLAVE10:true" "MASTER0_WRITE_SLAVE11:true" "MASTER0_WRITE_SLAVE12:true" "MASTER0_WRITE_SLAVE13:true" "MASTER0_WRITE_SLAVE14:true" "MASTER0_WRITE_SLAVE15:true" "MASTER0_WRITE_SLAVE16:true" "MASTER0_WRITE_SLAVE17:true" "MASTER0_WRITE_SLAVE18:true" "MASTER0_WRITE_SLAVE19:true" "MASTER0_WRITE_SLAVE1:true" "MASTER0_WRITE_SLAVE20:true" "MASTER0_WRITE_SLAVE21:true" "MASTER0_WRITE_SLAVE22:true" "MASTER0_WRITE_SLAVE23:true" "MASTER0_WRITE_SLAVE24:true" "MASTER0_WRITE_SLAVE25:true" "MASTER0_WRITE_SLAVE26:true" "MASTER0_WRITE_SLAVE27:true" "MASTER0_WRITE_SLAVE28:true" "MASTER0_WRITE_SLAVE29:true" "MASTER0_WRITE_SLAVE2:true" "MASTER0_WRITE_SLAVE30:true" "MASTER0_WRITE_SLAVE31:true" "MASTER0_WRITE_SLAVE3:true" "MASTER0_WRITE_SLAVE4:true" "MASTER0_WRITE_SLAVE5:true" "MASTER0_WRITE_SLAVE6:true" "MASTER0_WRITE_SLAVE7:true" "MASTER0_WRITE_SLAVE8:true" "MASTER0_WRITE_SLAVE9:true" "MASTER10_CHAN_RS:true" "MASTER10_CLOCK_DOMAIN_CROSSING:false" "MASTER10_DATA_WIDTH:32" "MASTER10_DWC_DATA_FIFO_DEPTH:16" "MASTER10_READ_INTERLEAVE:false" "MASTER10_READ_SLAVE0:true" "MASTER10_READ_SLAVE10:true" "MASTER10_READ_SLAVE11:true" "MASTER10_READ_SLAVE12:true" "MASTER10_READ_SLAVE13:true" "MASTER10_READ_SLAVE14:true" "MASTER10_READ_SLAVE15:true" "MASTER10_READ_SLAVE16:true" "MASTER10_READ_SLAVE17:true" "MASTER10_READ_SLAVE18:true" "MASTER10_READ_SLAVE19:true" "MASTER10_READ_SLAVE1:true" "MASTER10_READ_SLAVE20:true" "MASTER10_READ_SLAVE21:true" "MASTER10_READ_SLAVE22:true" "MASTER10_READ_SLAVE23:true" "MASTER10_READ_SLAVE24:true" "MASTER10_READ_SLAVE25:true" "MASTER10_READ_SLAVE26:true" "MASTER10_READ_SLAVE27:true" "MASTER10_READ_SLAVE28:true" "MASTER10_READ_SLAVE29:true" "MASTER10_READ_SLAVE2:true" "MASTER10_READ_SLAVE30:true" "MASTER10_READ_SLAVE31:true" "MASTER10_READ_SLAVE3:true" "MASTER10_READ_SLAVE4:true" "MASTER10_READ_SLAVE5:true" "MASTER10_READ_SLAVE6:true" "MASTER10_READ_SLAVE7:true" "MASTER10_READ_SLAVE8:true" "MASTER10_READ_SLAVE9:true" "MASTER10_TYPE:0" "MASTER10_WRITE_SLAVE0:true" "MASTER10_WRITE_SLAVE10:true" "MASTER10_WRITE_SLAVE11:true" "MASTER10_WRITE_SLAVE12:true" "MASTER10_WRITE_SLAVE13:true" "MASTER10_WRITE_SLAVE14:true" "MASTER10_WRITE_SLAVE15:true" "MASTER10_WRITE_SLAVE16:true" "MASTER10_WRITE_SLAVE17:true" "MASTER10_WRITE_SLAVE18:true" "MASTER10_WRITE_SLAVE19:true" "MASTER10_WRITE_SLAVE1:true" "MASTER10_WRITE_SLAVE20:true" "MASTER10_WRITE_SLAVE21:true" "MASTER10_WRITE_SLAVE22:true" "MASTER10_WRITE_SLAVE23:true" "MASTER10_WRITE_SLAVE24:true" "MASTER10_WRITE_SLAVE25:true" "MASTER10_WRITE_SLAVE26:true" "MASTER10_WRITE_SLAVE27:true" "MASTER10_WRITE_SLAVE28:true" "MASTER10_WRITE_SLAVE29:true" "MASTER10_WRITE_SLAVE2:true" "MASTER10_WRITE_SLAVE30:true" "MASTER10_WRITE_SLAVE31:true" "MASTER10_WRITE_SLAVE3:true" "MASTER10_WRITE_SLAVE4:true" "MASTER10_WRITE_SLAVE5:true" "MASTER10_WRITE_SLAVE6:true" "MASTER10_WRITE_SLAVE7:true" "MASTER10_WRITE_SLAVE8:true" "MASTER10_WRITE_SLAVE9:true" "MASTER11_CHAN_RS:true" "MASTER11_CLOCK_DOMAIN_CROSSING:false" "MASTER11_DATA_WIDTH:32" "MASTER11_DWC_DATA_FIFO_DEPTH:16" "MASTER11_READ_INTERLEAVE:false" "MASTER11_READ_SLAVE0:true" "MASTER11_READ_SLAVE10:true" "MASTER11_READ_SLAVE11:true" "MASTER11_READ_SLAVE12:true" "MASTER11_READ_SLAVE13:true" "MASTER11_READ_SLAVE14:true" "MASTER11_READ_SLAVE15:true" "MASTER11_READ_SLAVE16:true" "MASTER11_READ_SLAVE17:true" "MASTER11_READ_SLAVE18:true" "MASTER11_READ_SLAVE19:true" "MASTER11_READ_SLAVE1:true" "MASTER11_READ_SLAVE20:true" "MASTER11_READ_SLAVE21:true" "MASTER11_READ_SLAVE22:true" "MASTER11_READ_SLAVE23:true" "MASTER11_READ_SLAVE24:true" "MASTER11_READ_SLAVE25:true" "MASTER11_READ_SLAVE26:true" "MASTER11_READ_SLAVE27:true" "MASTER11_READ_SLAVE28:true" "MASTER11_READ_SLAVE29:true" "MASTER11_READ_SLAVE2:true" "MASTER11_READ_SLAVE30:true" "MASTER11_READ_SLAVE31:true" "MASTER11_READ_SLAVE3:true" "MASTER11_READ_SLAVE4:true" "MASTER11_READ_SLAVE5:true" "MASTER11_READ_SLAVE6:true" "MASTER11_READ_SLAVE7:true" "MASTER11_READ_SLAVE8:true" "MASTER11_READ_SLAVE9:true" "MASTER11_TYPE:0" "MASTER11_WRITE_SLAVE0:true" "MASTER11_WRITE_SLAVE10:true" "MASTER11_WRITE_SLAVE11:true" "MASTER11_WRITE_SLAVE12:true" "MASTER11_WRITE_SLAVE13:true" "MASTER11_WRITE_SLAVE14:true" "MASTER11_WRITE_SLAVE15:true" "MASTER11_WRITE_SLAVE16:true" "MASTER11_WRITE_SLAVE17:true" "MASTER11_WRITE_SLAVE18:true" "MASTER11_WRITE_SLAVE19:true" "MASTER11_WRITE_SLAVE1:true" "MASTER11_WRITE_SLAVE20:true" "MASTER11_WRITE_SLAVE21:true" "MASTER11_WRITE_SLAVE22:true" "MASTER11_WRITE_SLAVE23:true" "MASTER11_WRITE_SLAVE24:true" "MASTER11_WRITE_SLAVE25:true" "MASTER11_WRITE_SLAVE26:true" "MASTER11_WRITE_SLAVE27:true" "MASTER11_WRITE_SLAVE28:true" "MASTER11_WRITE_SLAVE29:true" "MASTER11_WRITE_SLAVE2:true" "MASTER11_WRITE_SLAVE30:true" "MASTER11_WRITE_SLAVE31:true" "MASTER11_WRITE_SLAVE3:true" "MASTER11_WRITE_SLAVE4:true" "MASTER11_WRITE_SLAVE5:true" "MASTER11_WRITE_SLAVE6:true" "MASTER11_WRITE_SLAVE7:true" "MASTER11_WRITE_SLAVE8:true" "MASTER11_WRITE_SLAVE9:true" "MASTER12_CHAN_RS:true" "MASTER12_CLOCK_DOMAIN_CROSSING:false" "MASTER12_DATA_WIDTH:32" "MASTER12_DWC_DATA_FIFO_DEPTH:16" "MASTER12_READ_INTERLEAVE:false" "MASTER12_READ_SLAVE0:true" "MASTER12_READ_SLAVE10:true" "MASTER12_READ_SLAVE11:true" "MASTER12_READ_SLAVE12:true" "MASTER12_READ_SLAVE13:true" "MASTER12_READ_SLAVE14:true" "MASTER12_READ_SLAVE15:true" "MASTER12_READ_SLAVE16:true" "MASTER12_READ_SLAVE17:true" "MASTER12_READ_SLAVE18:true" "MASTER12_READ_SLAVE19:true" "MASTER12_READ_SLAVE1:true" "MASTER12_READ_SLAVE20:true" "MASTER12_READ_SLAVE21:true" "MASTER12_READ_SLAVE22:true" "MASTER12_READ_SLAVE23:true" "MASTER12_READ_SLAVE24:true" "MASTER12_READ_SLAVE25:true" "MASTER12_READ_SLAVE26:true" "MASTER12_READ_SLAVE27:true" "MASTER12_READ_SLAVE28:true" "MASTER12_READ_SLAVE29:true" "MASTER12_READ_SLAVE2:true" "MASTER12_READ_SLAVE30:true" "MASTER12_READ_SLAVE31:true" "MASTER12_READ_SLAVE3:true" "MASTER12_READ_SLAVE4:true" "MASTER12_READ_SLAVE5:true" "MASTER12_READ_SLAVE6:true" "MASTER12_READ_SLAVE7:true" "MASTER12_READ_SLAVE8:true" "MASTER12_READ_SLAVE9:true" "MASTER12_TYPE:0" "MASTER12_WRITE_SLAVE0:true" "MASTER12_WRITE_SLAVE10:true" "MASTER12_WRITE_SLAVE11:true" "MASTER12_WRITE_SLAVE12:true" "MASTER12_WRITE_SLAVE13:true" "MASTER12_WRITE_SLAVE14:true" "MASTER12_WRITE_SLAVE15:true" "MASTER12_WRITE_SLAVE16:true" "MASTER12_WRITE_SLAVE17:true" "MASTER12_WRITE_SLAVE18:true" "MASTER12_WRITE_SLAVE19:true" "MASTER12_WRITE_SLAVE1:true" "MASTER12_WRITE_SLAVE20:true" "MASTER12_WRITE_SLAVE21:true" "MASTER12_WRITE_SLAVE22:true" "MASTER12_WRITE_SLAVE23:true" "MASTER12_WRITE_SLAVE24:true" "MASTER12_WRITE_SLAVE25:true" "MASTER12_WRITE_SLAVE26:true" "MASTER12_WRITE_SLAVE27:true" "MASTER12_WRITE_SLAVE28:true" "MASTER12_WRITE_SLAVE29:true" "MASTER12_WRITE_SLAVE2:true" "MASTER12_WRITE_SLAVE30:true" "MASTER12_WRITE_SLAVE31:true" "MASTER12_WRITE_SLAVE3:true" "MASTER12_WRITE_SLAVE4:true" "MASTER12_WRITE_SLAVE5:true" "MASTER12_WRITE_SLAVE6:true" "MASTER12_WRITE_SLAVE7:true" "MASTER12_WRITE_SLAVE8:true" "MASTER12_WRITE_SLAVE9:true" "MASTER13_CHAN_RS:true" "MASTER13_CLOCK_DOMAIN_CROSSING:false" "MASTER13_DATA_WIDTH:32" "MASTER13_DWC_DATA_FIFO_DEPTH:16" "MASTER13_READ_INTERLEAVE:false" "MASTER13_READ_SLAVE0:true" "MASTER13_READ_SLAVE10:true" "MASTER13_READ_SLAVE11:true" "MASTER13_READ_SLAVE12:true" "MASTER13_READ_SLAVE13:true" "MASTER13_READ_SLAVE14:true" "MASTER13_READ_SLAVE15:true" "MASTER13_READ_SLAVE16:true" "MASTER13_READ_SLAVE17:true" "MASTER13_READ_SLAVE18:true" "MASTER13_READ_SLAVE19:true" "MASTER13_READ_SLAVE1:true" "MASTER13_READ_SLAVE20:true" "MASTER13_READ_SLAVE21:true" "MASTER13_READ_SLAVE22:true" "MASTER13_READ_SLAVE23:true" "MASTER13_READ_SLAVE24:true" "MASTER13_READ_SLAVE25:true" "MASTER13_READ_SLAVE26:true" "MASTER13_READ_SLAVE27:true" "MASTER13_READ_SLAVE28:true" "MASTER13_READ_SLAVE29:true" "MASTER13_READ_SLAVE2:true" "MASTER13_READ_SLAVE30:true" "MASTER13_READ_SLAVE31:true" "MASTER13_READ_SLAVE3:true" "MASTER13_READ_SLAVE4:true" "MASTER13_READ_SLAVE5:true" "MASTER13_READ_SLAVE6:true" "MASTER13_READ_SLAVE7:true" "MASTER13_READ_SLAVE8:true" "MASTER13_READ_SLAVE9:true" "MASTER13_TYPE:0" "MASTER13_WRITE_SLAVE0:true" "MASTER13_WRITE_SLAVE10:true" "MASTER13_WRITE_SLAVE11:true" "MASTER13_WRITE_SLAVE12:true" "MASTER13_WRITE_SLAVE13:true" "MASTER13_WRITE_SLAVE14:true" "MASTER13_WRITE_SLAVE15:true" "MASTER13_WRITE_SLAVE16:true" "MASTER13_WRITE_SLAVE17:true" "MASTER13_WRITE_SLAVE18:true" "MASTER13_WRITE_SLAVE19:true" "MASTER13_WRITE_SLAVE1:true" "MASTER13_WRITE_SLAVE20:true" "MASTER13_WRITE_SLAVE21:true" "MASTER13_WRITE_SLAVE22:true" "MASTER13_WRITE_SLAVE23:true" "MASTER13_WRITE_SLAVE24:true" "MASTER13_WRITE_SLAVE25:true" "MASTER13_WRITE_SLAVE26:true" "MASTER13_WRITE_SLAVE27:true" "MASTER13_WRITE_SLAVE28:true" "MASTER13_WRITE_SLAVE29:true" "MASTER13_WRITE_SLAVE2:true" "MASTER13_WRITE_SLAVE30:true" "MASTER13_WRITE_SLAVE31:true" "MASTER13_WRITE_SLAVE3:true" "MASTER13_WRITE_SLAVE4:true" "MASTER13_WRITE_SLAVE5:true" "MASTER13_WRITE_SLAVE6:true" "MASTER13_WRITE_SLAVE7:true" "MASTER13_WRITE_SLAVE8:true" "MASTER13_WRITE_SLAVE9:true" "MASTER14_CHAN_RS:true" "MASTER14_CLOCK_DOMAIN_CROSSING:false" "MASTER14_DATA_WIDTH:32" "MASTER14_DWC_DATA_FIFO_DEPTH:16" "MASTER14_READ_INTERLEAVE:false" "MASTER14_READ_SLAVE0:true" "MASTER14_READ_SLAVE10:true" "MASTER14_READ_SLAVE11:true" "MASTER14_READ_SLAVE12:true" "MASTER14_READ_SLAVE13:true" "MASTER14_READ_SLAVE14:true" "MASTER14_READ_SLAVE15:true" "MASTER14_READ_SLAVE16:true" "MASTER14_READ_SLAVE17:true" "MASTER14_READ_SLAVE18:true" "MASTER14_READ_SLAVE19:true" "MASTER14_READ_SLAVE1:true" "MASTER14_READ_SLAVE20:true" "MASTER14_READ_SLAVE21:true" "MASTER14_READ_SLAVE22:true" "MASTER14_READ_SLAVE23:true" "MASTER14_READ_SLAVE24:true" "MASTER14_READ_SLAVE25:true" "MASTER14_READ_SLAVE26:true" "MASTER14_READ_SLAVE27:true" "MASTER14_READ_SLAVE28:true" "MASTER14_READ_SLAVE29:true" "MASTER14_READ_SLAVE2:true" "MASTER14_READ_SLAVE30:true" "MASTER14_READ_SLAVE31:true" "MASTER14_READ_SLAVE3:true" "MASTER14_READ_SLAVE4:true" "MASTER14_READ_SLAVE5:true" "MASTER14_READ_SLAVE6:true" "MASTER14_READ_SLAVE7:true" "MASTER14_READ_SLAVE8:true" "MASTER14_READ_SLAVE9:true" "MASTER14_TYPE:0" "MASTER14_WRITE_SLAVE0:true" "MASTER14_WRITE_SLAVE10:true" "MASTER14_WRITE_SLAVE11:true" "MASTER14_WRITE_SLAVE12:true" "MASTER14_WRITE_SLAVE13:true" "MASTER14_WRITE_SLAVE14:true" "MASTER14_WRITE_SLAVE15:true" "MASTER14_WRITE_SLAVE16:true" "MASTER14_WRITE_SLAVE17:true" "MASTER14_WRITE_SLAVE18:true" "MASTER14_WRITE_SLAVE19:true" "MASTER14_WRITE_SLAVE1:true" "MASTER14_WRITE_SLAVE20:true" "MASTER14_WRITE_SLAVE21:true" "MASTER14_WRITE_SLAVE22:true" "MASTER14_WRITE_SLAVE23:true" "MASTER14_WRITE_SLAVE24:true" "MASTER14_WRITE_SLAVE25:true" "MASTER14_WRITE_SLAVE26:true" "MASTER14_WRITE_SLAVE27:true" "MASTER14_WRITE_SLAVE28:true" "MASTER14_WRITE_SLAVE29:true" "MASTER14_WRITE_SLAVE2:true" "MASTER14_WRITE_SLAVE30:true" "MASTER14_WRITE_SLAVE31:true" "MASTER14_WRITE_SLAVE3:true" "MASTER14_WRITE_SLAVE4:true" "MASTER14_WRITE_SLAVE5:true" "MASTER14_WRITE_SLAVE6:true" "MASTER14_WRITE_SLAVE7:true" "MASTER14_WRITE_SLAVE8:true" "MASTER14_WRITE_SLAVE9:true" "MASTER15_CHAN_RS:true" "MASTER15_CLOCK_DOMAIN_CROSSING:false" "MASTER15_DATA_WIDTH:32" "MASTER15_DWC_DATA_FIFO_DEPTH:16" "MASTER15_READ_INTERLEAVE:false" "MASTER15_READ_SLAVE0:true" "MASTER15_READ_SLAVE10:true" "MASTER15_READ_SLAVE11:true" "MASTER15_READ_SLAVE12:true" "MASTER15_READ_SLAVE13:true" "MASTER15_READ_SLAVE14:true" "MASTER15_READ_SLAVE15:true" "MASTER15_READ_SLAVE16:true" "MASTER15_READ_SLAVE17:true" "MASTER15_READ_SLAVE18:true" "MASTER15_READ_SLAVE19:true" "MASTER15_READ_SLAVE1:true" "MASTER15_READ_SLAVE20:true" "MASTER15_READ_SLAVE21:true" "MASTER15_READ_SLAVE22:true" "MASTER15_READ_SLAVE23:true" "MASTER15_READ_SLAVE24:true" "MASTER15_READ_SLAVE25:true" "MASTER15_READ_SLAVE26:true" "MASTER15_READ_SLAVE27:true" "MASTER15_READ_SLAVE28:true" "MASTER15_READ_SLAVE29:true" "MASTER15_READ_SLAVE2:true" "MASTER15_READ_SLAVE30:true" "MASTER15_READ_SLAVE31:true" "MASTER15_READ_SLAVE3:true" "MASTER15_READ_SLAVE4:true" "MASTER15_READ_SLAVE5:true" "MASTER15_READ_SLAVE6:true" "MASTER15_READ_SLAVE7:true" "MASTER15_READ_SLAVE8:true" "MASTER15_READ_SLAVE9:true" "MASTER15_TYPE:0" "MASTER15_WRITE_SLAVE0:true" "MASTER15_WRITE_SLAVE10:true" "MASTER15_WRITE_SLAVE11:true" "MASTER15_WRITE_SLAVE12:true" "MASTER15_WRITE_SLAVE13:true" "MASTER15_WRITE_SLAVE14:true" "MASTER15_WRITE_SLAVE15:true" "MASTER15_WRITE_SLAVE16:true" "MASTER15_WRITE_SLAVE17:true" "MASTER15_WRITE_SLAVE18:true" "MASTER15_WRITE_SLAVE19:true" "MASTER15_WRITE_SLAVE1:true" "MASTER15_WRITE_SLAVE20:true" "MASTER15_WRITE_SLAVE21:true" "MASTER15_WRITE_SLAVE22:true" "MASTER15_WRITE_SLAVE23:true" "MASTER15_WRITE_SLAVE24:true" "MASTER15_WRITE_SLAVE25:true" "MASTER15_WRITE_SLAVE26:true" "MASTER15_WRITE_SLAVE27:true" "MASTER15_WRITE_SLAVE28:true" "MASTER15_WRITE_SLAVE29:true" "MASTER15_WRITE_SLAVE2:true" "MASTER15_WRITE_SLAVE30:true" "MASTER15_WRITE_SLAVE31:true" "MASTER15_WRITE_SLAVE3:true" "MASTER15_WRITE_SLAVE4:true" "MASTER15_WRITE_SLAVE5:true" "MASTER15_WRITE_SLAVE6:true" "MASTER15_WRITE_SLAVE7:true" "MASTER15_WRITE_SLAVE8:true" "MASTER15_WRITE_SLAVE9:true" "MASTER1_CHAN_RS:true" "MASTER1_CLOCK_DOMAIN_CROSSING:false" "MASTER1_DATA_WIDTH:32" "MASTER1_DWC_DATA_FIFO_DEPTH:16" "MASTER1_READ_INTERLEAVE:false" "MASTER1_READ_SLAVE0:true" "MASTER1_READ_SLAVE10:true" "MASTER1_READ_SLAVE11:true" "MASTER1_READ_SLAVE12:true" "MASTER1_READ_SLAVE13:true" "MASTER1_READ_SLAVE14:true" "MASTER1_READ_SLAVE15:true" "MASTER1_READ_SLAVE16:true" "MASTER1_READ_SLAVE17:true" "MASTER1_READ_SLAVE18:true" "MASTER1_READ_SLAVE19:true" "MASTER1_READ_SLAVE1:true" "MASTER1_READ_SLAVE20:true" "MASTER1_READ_SLAVE21:true" "MASTER1_READ_SLAVE22:true" "MASTER1_READ_SLAVE23:true" "MASTER1_READ_SLAVE24:true" "MASTER1_READ_SLAVE25:true" "MASTER1_READ_SLAVE26:true" "MASTER1_READ_SLAVE27:true" "MASTER1_READ_SLAVE28:true" "MASTER1_READ_SLAVE29:true" "MASTER1_READ_SLAVE2:true" "MASTER1_READ_SLAVE30:true" "MASTER1_READ_SLAVE31:true" "MASTER1_READ_SLAVE3:true" "MASTER1_READ_SLAVE4:true" "MASTER1_READ_SLAVE5:true" "MASTER1_READ_SLAVE6:true" "MASTER1_READ_SLAVE7:true" "MASTER1_READ_SLAVE8:true" "MASTER1_READ_SLAVE9:true" "MASTER1_TYPE:0" "MASTER1_WRITE_SLAVE0:true" "MASTER1_WRITE_SLAVE10:true" "MASTER1_WRITE_SLAVE11:true" "MASTER1_WRITE_SLAVE12:true" "MASTER1_WRITE_SLAVE13:true" "MASTER1_WRITE_SLAVE14:true" "MASTER1_WRITE_SLAVE15:true" "MASTER1_WRITE_SLAVE16:true" "MASTER1_WRITE_SLAVE17:true" "MASTER1_WRITE_SLAVE18:true" "MASTER1_WRITE_SLAVE19:true" "MASTER1_WRITE_SLAVE1:true" "MASTER1_WRITE_SLAVE20:true" "MASTER1_WRITE_SLAVE21:true" "MASTER1_WRITE_SLAVE22:true" "MASTER1_WRITE_SLAVE23:true" "MASTER1_WRITE_SLAVE24:true" "MASTER1_WRITE_SLAVE25:true" "MASTER1_WRITE_SLAVE26:true" "MASTER1_WRITE_SLAVE27:true" "MASTER1_WRITE_SLAVE28:true" "MASTER1_WRITE_SLAVE29:true" "MASTER1_WRITE_SLAVE2:true" "MASTER1_WRITE_SLAVE30:true" "MASTER1_WRITE_SLAVE31:true" "MASTER1_WRITE_SLAVE3:true" "MASTER1_WRITE_SLAVE4:true" "MASTER1_WRITE_SLAVE5:true" "MASTER1_WRITE_SLAVE6:true" "MASTER1_WRITE_SLAVE7:true" "MASTER1_WRITE_SLAVE8:true" "MASTER1_WRITE_SLAVE9:true" "MASTER2_CHAN_RS:true" "MASTER2_CLOCK_DOMAIN_CROSSING:false" "MASTER2_DATA_WIDTH:32" "MASTER2_DWC_DATA_FIFO_DEPTH:16" "MASTER2_READ_INTERLEAVE:false" "MASTER2_READ_SLAVE0:true" "MASTER2_READ_SLAVE10:true" "MASTER2_READ_SLAVE11:true" "MASTER2_READ_SLAVE12:true" "MASTER2_READ_SLAVE13:true" "MASTER2_READ_SLAVE14:true" "MASTER2_READ_SLAVE15:true" "MASTER2_READ_SLAVE16:true" "MASTER2_READ_SLAVE17:true" "MASTER2_READ_SLAVE18:true" "MASTER2_READ_SLAVE19:true" "MASTER2_READ_SLAVE1:true" "MASTER2_READ_SLAVE20:true" "MASTER2_READ_SLAVE21:true" "MASTER2_READ_SLAVE22:true" "MASTER2_READ_SLAVE23:true" "MASTER2_READ_SLAVE24:true" "MASTER2_READ_SLAVE25:true" "MASTER2_READ_SLAVE26:true" "MASTER2_READ_SLAVE27:true" "MASTER2_READ_SLAVE28:true" "MASTER2_READ_SLAVE29:true" "MASTER2_READ_SLAVE2:true" "MASTER2_READ_SLAVE30:true" "MASTER2_READ_SLAVE31:true" "MASTER2_READ_SLAVE3:true" "MASTER2_READ_SLAVE4:true" "MASTER2_READ_SLAVE5:true" "MASTER2_READ_SLAVE6:true" "MASTER2_READ_SLAVE7:true" "MASTER2_READ_SLAVE8:true" "MASTER2_READ_SLAVE9:true" "MASTER2_TYPE:0" "MASTER2_WRITE_SLAVE0:true" "MASTER2_WRITE_SLAVE10:true" "MASTER2_WRITE_SLAVE11:true" "MASTER2_WRITE_SLAVE12:true" "MASTER2_WRITE_SLAVE13:true" "MASTER2_WRITE_SLAVE14:true" "MASTER2_WRITE_SLAVE15:true" "MASTER2_WRITE_SLAVE16:true" "MASTER2_WRITE_SLAVE17:true" "MASTER2_WRITE_SLAVE18:true" "MASTER2_WRITE_SLAVE19:true" "MASTER2_WRITE_SLAVE1:true" "MASTER2_WRITE_SLAVE20:true" "MASTER2_WRITE_SLAVE21:true" "MASTER2_WRITE_SLAVE22:true" "MASTER2_WRITE_SLAVE23:true" "MASTER2_WRITE_SLAVE24:true" "MASTER2_WRITE_SLAVE25:true" "MASTER2_WRITE_SLAVE26:true" "MASTER2_WRITE_SLAVE27:true" "MASTER2_WRITE_SLAVE28:true" "MASTER2_WRITE_SLAVE29:true" "MASTER2_WRITE_SLAVE2:true" "MASTER2_WRITE_SLAVE30:true" "MASTER2_WRITE_SLAVE31:true" "MASTER2_WRITE_SLAVE3:true" "MASTER2_WRITE_SLAVE4:true" "MASTER2_WRITE_SLAVE5:true" "MASTER2_WRITE_SLAVE6:true" "MASTER2_WRITE_SLAVE7:true" "MASTER2_WRITE_SLAVE8:true" "MASTER2_WRITE_SLAVE9:true" "MASTER3_CHAN_RS:true" "MASTER3_CLOCK_DOMAIN_CROSSING:false" "MASTER3_DATA_WIDTH:32" "MASTER3_DWC_DATA_FIFO_DEPTH:16" "MASTER3_READ_INTERLEAVE:false" "MASTER3_READ_SLAVE0:true" "MASTER3_READ_SLAVE10:true" "MASTER3_READ_SLAVE11:true" "MASTER3_READ_SLAVE12:true" "MASTER3_READ_SLAVE13:true" "MASTER3_READ_SLAVE14:true" "MASTER3_READ_SLAVE15:true" "MASTER3_READ_SLAVE16:true" "MASTER3_READ_SLAVE17:true" "MASTER3_READ_SLAVE18:true" "MASTER3_READ_SLAVE19:true" "MASTER3_READ_SLAVE1:true" "MASTER3_READ_SLAVE20:true" "MASTER3_READ_SLAVE21:true" "MASTER3_READ_SLAVE22:true" "MASTER3_READ_SLAVE23:true" "MASTER3_READ_SLAVE24:true" "MASTER3_READ_SLAVE25:true" "MASTER3_READ_SLAVE26:true" "MASTER3_READ_SLAVE27:true" "MASTER3_READ_SLAVE28:true" "MASTER3_READ_SLAVE29:true" "MASTER3_READ_SLAVE2:true" "MASTER3_READ_SLAVE30:true" "MASTER3_READ_SLAVE31:true" "MASTER3_READ_SLAVE3:true" "MASTER3_READ_SLAVE4:true" "MASTER3_READ_SLAVE5:true" "MASTER3_READ_SLAVE6:true" "MASTER3_READ_SLAVE7:true" "MASTER3_READ_SLAVE8:true" "MASTER3_READ_SLAVE9:true" "MASTER3_TYPE:0" "MASTER3_WRITE_SLAVE0:true" "MASTER3_WRITE_SLAVE10:true" "MASTER3_WRITE_SLAVE11:true" "MASTER3_WRITE_SLAVE12:true" "MASTER3_WRITE_SLAVE13:true" "MASTER3_WRITE_SLAVE14:true" "MASTER3_WRITE_SLAVE15:true" "MASTER3_WRITE_SLAVE16:true" "MASTER3_WRITE_SLAVE17:true" "MASTER3_WRITE_SLAVE18:true" "MASTER3_WRITE_SLAVE19:true" "MASTER3_WRITE_SLAVE1:true" "MASTER3_WRITE_SLAVE20:true" "MASTER3_WRITE_SLAVE21:true" "MASTER3_WRITE_SLAVE22:true" "MASTER3_WRITE_SLAVE23:true" "MASTER3_WRITE_SLAVE24:true" "MASTER3_WRITE_SLAVE25:true" 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"MASTER4_READ_SLAVE24:true" "MASTER4_READ_SLAVE25:true" "MASTER4_READ_SLAVE26:true" "MASTER4_READ_SLAVE27:true" "MASTER4_READ_SLAVE28:true" "MASTER4_READ_SLAVE29:true" "MASTER4_READ_SLAVE2:true" "MASTER4_READ_SLAVE30:true" "MASTER4_READ_SLAVE31:true" "MASTER4_READ_SLAVE3:true" "MASTER4_READ_SLAVE4:true" "MASTER4_READ_SLAVE5:true" "MASTER4_READ_SLAVE6:true" "MASTER4_READ_SLAVE7:true" "MASTER4_READ_SLAVE8:true" "MASTER4_READ_SLAVE9:true" "MASTER4_TYPE:0" "MASTER4_WRITE_SLAVE0:true" "MASTER4_WRITE_SLAVE10:true" "MASTER4_WRITE_SLAVE11:true" "MASTER4_WRITE_SLAVE12:true" "MASTER4_WRITE_SLAVE13:true" "MASTER4_WRITE_SLAVE14:true" "MASTER4_WRITE_SLAVE15:true" "MASTER4_WRITE_SLAVE16:true" "MASTER4_WRITE_SLAVE17:true" "MASTER4_WRITE_SLAVE18:true" "MASTER4_WRITE_SLAVE19:true" "MASTER4_WRITE_SLAVE1:true" "MASTER4_WRITE_SLAVE20:true" "MASTER4_WRITE_SLAVE21:true" "MASTER4_WRITE_SLAVE22:true" "MASTER4_WRITE_SLAVE23:true" "MASTER4_WRITE_SLAVE24:true" "MASTER4_WRITE_SLAVE25:true" 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"MASTER9_READ_SLAVE24:true" "MASTER9_READ_SLAVE25:true" "MASTER9_READ_SLAVE26:true" "MASTER9_READ_SLAVE27:true" "MASTER9_READ_SLAVE28:true" "MASTER9_READ_SLAVE29:true" "MASTER9_READ_SLAVE2:true" "MASTER9_READ_SLAVE30:true" "MASTER9_READ_SLAVE31:true" "MASTER9_READ_SLAVE3:true" "MASTER9_READ_SLAVE4:true" "MASTER9_READ_SLAVE5:true" "MASTER9_READ_SLAVE6:true" "MASTER9_READ_SLAVE7:true" "MASTER9_READ_SLAVE8:true" "MASTER9_READ_SLAVE9:true" "MASTER9_TYPE:0" "MASTER9_WRITE_SLAVE0:true" "MASTER9_WRITE_SLAVE10:true" "MASTER9_WRITE_SLAVE11:true" "MASTER9_WRITE_SLAVE12:true" "MASTER9_WRITE_SLAVE13:true" "MASTER9_WRITE_SLAVE14:true" "MASTER9_WRITE_SLAVE15:true" "MASTER9_WRITE_SLAVE16:true" "MASTER9_WRITE_SLAVE17:true" "MASTER9_WRITE_SLAVE18:true" "MASTER9_WRITE_SLAVE19:true" "MASTER9_WRITE_SLAVE1:true" "MASTER9_WRITE_SLAVE20:true" "MASTER9_WRITE_SLAVE21:true" "MASTER9_WRITE_SLAVE22:true" "MASTER9_WRITE_SLAVE23:true" "MASTER9_WRITE_SLAVE24:true" "MASTER9_WRITE_SLAVE25:true" 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"SLAVE2_CLOCK_DOMAIN_CROSSING:false" "SLAVE2_DATA_WIDTH:32" "SLAVE2_DWC_DATA_FIFO_DEPTH:16" "SLAVE2_END_ADDR:0x17ffffff" "SLAVE2_END_ADDR_UPPER:0x0" "SLAVE2_READ_INTERLEAVE:false" "SLAVE2_START_ADDR:0x10000000" "SLAVE2_START_ADDR_UPPER:0x0" "SLAVE2_TYPE:0" "SLAVE30_CHAN_RS:true" "SLAVE30_CLOCK_DOMAIN_CROSSING:false" "SLAVE30_DATA_WIDTH:32" "SLAVE30_DWC_DATA_FIFO_DEPTH:16" "SLAVE30_END_ADDR:0x938fffff" "SLAVE30_END_ADDR_UPPER:0x0" "SLAVE30_READ_INTERLEAVE:false" "SLAVE30_START_ADDR:0x93600000" "SLAVE30_START_ADDR_UPPER:0x0" "SLAVE30_TYPE:0" "SLAVE31_CHAN_RS:true" "SLAVE31_CLOCK_DOMAIN_CROSSING:false" "SLAVE31_DATA_WIDTH:32" "SLAVE31_DWC_DATA_FIFO_DEPTH:16" "SLAVE31_END_ADDR:0x93bfffff" "SLAVE31_END_ADDR_UPPER:0x0" "SLAVE31_READ_INTERLEAVE:false" "SLAVE31_START_ADDR:0x93900000" "SLAVE31_START_ADDR_UPPER:0x0" "SLAVE31_TYPE:0" "SLAVE3_CHAN_RS:true" "SLAVE3_CLOCK_DOMAIN_CROSSING:false" "SLAVE3_DATA_WIDTH:32" "SLAVE3_DWC_DATA_FIFO_DEPTH:16" "SLAVE3_END_ADDR:0x1fffffff" "SLAVE3_END_ADDR_UPPER:0x0" "SLAVE3_READ_INTERLEAVE:false" "SLAVE3_START_ADDR:0x18000000" "SLAVE3_START_ADDR_UPPER:0x0" "SLAVE3_TYPE:0" "SLAVE4_CHAN_RS:true" "SLAVE4_CLOCK_DOMAIN_CROSSING:false" "SLAVE4_DATA_WIDTH:32" "SLAVE4_DWC_DATA_FIFO_DEPTH:16" "SLAVE4_END_ADDR:0x27ffffff" "SLAVE4_END_ADDR_UPPER:0x0" "SLAVE4_READ_INTERLEAVE:false" "SLAVE4_START_ADDR:0x20000000" "SLAVE4_START_ADDR_UPPER:0x0" "SLAVE4_TYPE:0" "SLAVE5_CHAN_RS:true" "SLAVE5_CLOCK_DOMAIN_CROSSING:false" "SLAVE5_DATA_WIDTH:32" "SLAVE5_DWC_DATA_FIFO_DEPTH:16" "SLAVE5_END_ADDR:0x2fffffff" "SLAVE5_END_ADDR_UPPER:0x0" "SLAVE5_READ_INTERLEAVE:false" "SLAVE5_START_ADDR:0x28000000" "SLAVE5_START_ADDR_UPPER:0x0" "SLAVE5_TYPE:0" "SLAVE6_CHAN_RS:true" "SLAVE6_CLOCK_DOMAIN_CROSSING:false" "SLAVE6_DATA_WIDTH:32" "SLAVE6_DWC_DATA_FIFO_DEPTH:16" "SLAVE6_END_ADDR:0x37ffffff" "SLAVE6_END_ADDR_UPPER:0x0" "SLAVE6_READ_INTERLEAVE:false" "SLAVE6_START_ADDR:0x30000000" "SLAVE6_START_ADDR_UPPER:0x0" "SLAVE6_TYPE:0" "SLAVE7_CHAN_RS:true" "SLAVE7_CLOCK_DOMAIN_CROSSING:false" "SLAVE7_DATA_WIDTH:32" "SLAVE7_DWC_DATA_FIFO_DEPTH:16" "SLAVE7_END_ADDR:0x3fffffff" "SLAVE7_END_ADDR_UPPER:0x0" "SLAVE7_READ_INTERLEAVE:false" "SLAVE7_START_ADDR:0x38000000" "SLAVE7_START_ADDR_UPPER:0x0" "SLAVE7_TYPE:0" "SLAVE8_CHAN_RS:true" "SLAVE8_CLOCK_DOMAIN_CROSSING:false" "SLAVE8_DATA_WIDTH:32" "SLAVE8_DWC_DATA_FIFO_DEPTH:16" "SLAVE8_END_ADDR:0x47ffffff" "SLAVE8_END_ADDR_UPPER:0x0" "SLAVE8_READ_INTERLEAVE:false" "SLAVE8_START_ADDR:0x40000000" "SLAVE8_START_ADDR_UPPER:0x0" "SLAVE8_TYPE:0" "SLAVE9_CHAN_RS:true" "SLAVE9_CLOCK_DOMAIN_CROSSING:false" "SLAVE9_DATA_WIDTH:32" "SLAVE9_DWC_DATA_FIFO_DEPTH:16" "SLAVE9_END_ADDR:0x4fffffff" "SLAVE9_END_ADDR_UPPER:0x0" "SLAVE9_READ_INTERLEAVE:false" "SLAVE9_START_ADDR:0x48000000" "SLAVE9_START_ADDR_UPPER:0x0" "SLAVE9_TYPE:0" "SLV_AXI4PRT_ADDRDEPTH:4" "SLV_AXI4PRT_DATADEPTH:4" "USER_WIDTH:1"} sd_instantiate_component -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -component_name {COREAXI4INTERCONNECT_C0} -instance_name {} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_125MHz" "COREAXI4INTERCONNECT_C0_0:ACLK"} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_CLK_125MHz" "COREAXI4INTERCONNECT_C0_0:ARESETN"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:FIC_0_CLK" "COREAXI4INTERCONNECT_C0_0:ACLK"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_FIC_0_CLK" "COREAXI4INTERCONNECT_C0_0:ARESETN"} # Instantiate the SRAM create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.108} -component_name {PF_SRAM_AHBL_AXI_C0} -params {"AXI4_AWIDTH:32" "AXI4_DWIDTH:32" "AXI4_IDWIDTH:8" "AXI4_IFTYPE_RD:T" "AXI4_IFTYPE_WR:T" "AXI4_WRAP_SUPPORT:F" "BYTEENABLES:1" "BYTE_ENABLE_WIDTH:8" "B_REN_POLARITY:2" "CASCADE:1" "ECC_OPTIONS:0" "FABRIC_INTERFACE_TYPE:1" "IMPORT_FILE:" "INIT_RAM:F" "LPM_HINT:0" "PIPELINE_OPTIONS:1" "RDEPTH:2048" "RWIDTH:80" "USE_NATIVE_INTERFACE:F" "WDEPTH:2048" "WWIDTH:80"} sd_instantiate_component -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -component_name {PF_SRAM_AHBL_AXI_C0} -instance_name {} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_125MHz" "PF_SRAM_AHBL_AXI_C0_0:ACLK"} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_CLK_125MHz" "PF_SRAM_AHBL_AXI_C0_0:ARESETN"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:FIC_0_CLK" "PF_SRAM_AHBL_AXI_C0_0:ACLK"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_FIC_0_CLK" "PF_SRAM_AHBL_AXI_C0_0:ARESETN"} # Connect the master of the interconnect the the slave of the SRAM sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"COREAXI4INTERCONNECT_C0_0:AXI4mslave0" "PF_SRAM_AHBL_AXI_C0_0:AXI4_Slave"} @@ -73,12 +73,12 @@ sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"DMA_CONTROLL sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"DMA_CONTROLLER:TDEST" "AXI4_STREAM_DATA_GENERATOR_0:TDEST"} # connecting ACLK and RSTN to the data generator -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_125MHz" "AXI4_STREAM_DATA_GENERATOR_0:ACLK"} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_CLK_125MHz" "AXI4_STREAM_DATA_GENERATOR_0:RSTN"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:FIC_0_CLK" "AXI4_STREAM_DATA_GENERATOR_0:ACLK"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_FIC_0_CLK" "AXI4_STREAM_DATA_GENERATOR_0:RSTN"} # connecting the PCLK and PRESET_n -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_62_5MHz" "AXI4_STREAM_DATA_GENERATOR_0:PCLK"} -sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_CLK_62_5MHz" "AXI4_STREAM_DATA_GENERATOR_0:PRESETN"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:FIC_3_CLK" "AXI4_STREAM_DATA_GENERATOR_0:PCLK"} +sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:RESETN_FIC_3_CLK" "AXI4_STREAM_DATA_GENERATOR_0:PRESETN"} sd_show_bif_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -bif_pin_name {COREAXI4INTERCONNECT_C0_0:AXI4mmaster1} -pin_names {COREAXI4INTERCONNECT_C0_0:MASTER1_AWID} sd_show_bif_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -bif_pin_name {COREAXI4INTERCONNECT_C0_0:AXI4mmaster1} -pin_names {COREAXI4INTERCONNECT_C0_0:MASTER1_AWADDR} diff --git a/script_support/simulation/Test_bench.tcl b/script_support/simulation/Test_bench.tcl index 6bf5261..1ae4443 100644 --- a/script_support/simulation/Test_bench.tcl +++ b/script_support/simulation/Test_bench.tcl @@ -9,7 +9,6 @@ create_and_configure_core -core_vlnv {Actel:Simulation:RESET_GEN:1.0.1} -compone sd_instantiate_component -sd_name ${sd_tb_name} -component_name {RESET_GEN_C0} -instance_name {} # Make connections -sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"RESET_GEN_C0_0:RESET" "MPFS_ICICLE_KIT_BASE_DESIGN_0:PCIE_1_PERST_N"} sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"RESET_GEN_C0_0:RESET" "MPFS_ICICLE_KIT_BASE_DESIGN_0:SW4"} sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"CLK_GEN_C0_0:CLK" "MPFS_ICICLE_KIT_BASE_DESIGN_0:REFCLK"} sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"CLK_GEN_C0_0:CLK" "MPFS_ICICLE_KIT_BASE_DESIGN_0:REFCLK_N"} @@ -159,6 +158,7 @@ sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {MPFS_ICICLE_KIT_BASE_DESI sd_mark_pins_unused -sd_name {Test_bench} -pin_names {MPFS_ICICLE_KIT_BASE_DESIGN_0:COREUART_TX} sd_mark_pins_unused -sd_name {Test_bench} -pin_names {MPFS_ICICLE_KIT_BASE_DESIGN_0:mBUS_PWM} sd_mark_pins_unused -sd_name {Test_bench} -pin_names {MPFS_ICICLE_KIT_BASE_DESIGN_0:SPI_1_DO} +sd_mark_pins_unused -sd_name {Test_bench} -pin_names {MPFS_ICICLE_KIT_BASE_DESIGN_0:PCIE_1_PERST_N} sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {MPFS_ICICLE_KIT_BASE_DESIGN_0:SD_CD_EMMC_STRB} -value {GND} sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {MPFS_ICICLE_KIT_BASE_DESIGN_0:SD_WP_EMMC_RSTN} -value {GND}