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ledcubelab.qsf
executable file
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ledcubelab.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 19:10:08 March 29, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ledcubelab_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY ledcubelab
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:10:08 MARCH 29, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE clock_divider.v
set_global_assignment -name VERILOG_FILE ledcubelab.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_B13 -to GPIO0_pin_2_vert_pwr_1
set_location_assignment PIN_B14 -to GPIO0_pin_4_vert_pwr_2
set_location_assignment PIN_B15 -to GPIO0_pin_6_vert_pwr_3
set_location_assignment PIN_B16 -to GPIO0_pin_8_R1_Bot
set_location_assignment PIN_B17 -to GPIO0_pin_10_R2_Bot
set_location_assignment PIN_B18 -to GPIO0_pin_14_R3_Bot
set_location_assignment PIN_B19 -to GPIO0_pin_16_R1_Mid
set_location_assignment PIN_B20 -to GPIO0_pin_18_R2_Mid
set_location_assignment PIN_C22 -to GPIO0_pin_20_R3_Mid
set_location_assignment PIN_D22 -to GPIO0_pin_22_R1_Top
set_location_assignment PIN_E22 -to GPIO0_pin_24_R2_Top
set_location_assignment PIN_F22 -to GPIO0_pin_26_R3_Top
set_location_assignment PIN_G22 -to GPIO0_pin_28_unused1
set_location_assignment PIN_L1 -to clock
set_location_assignment PIN_T21 -to key_n[3]
set_location_assignment PIN_T22 -to key_n[2]
set_location_assignment PIN_R21 -to key_n[1]
set_location_assignment PIN_R22 -to key_n[0]
set_location_assignment PIN_Y21 -to ledg[7]
set_location_assignment PIN_Y22 -to ledg[6]
set_location_assignment PIN_W21 -to ledg[5]
set_location_assignment PIN_W22 -to ledg[4]
set_location_assignment PIN_V21 -to ledg[3]
set_location_assignment PIN_V22 -to ledg[2]
set_location_assignment PIN_U21 -to ledg[1]
set_location_assignment PIN_U22 -to ledg[0]
set_location_assignment PIN_R17 -to ledr[9]
set_location_assignment PIN_R18 -to ledr[8]
set_location_assignment PIN_U18 -to ledr[7]
set_location_assignment PIN_Y18 -to ledr[6]
set_location_assignment PIN_V19 -to ledr[5]
set_location_assignment PIN_T18 -to ledr[4]
set_location_assignment PIN_Y19 -to ledr[3]
set_location_assignment PIN_U19 -to ledr[2]
set_location_assignment PIN_R19 -to ledr[1]
set_location_assignment PIN_R20 -to ledr[0]
set_location_assignment PIN_L2 -to sw[9]
set_location_assignment PIN_M1 -to sw[8]
set_location_assignment PIN_M2 -to sw[7]
set_location_assignment PIN_U11 -to sw[6]
set_location_assignment PIN_U12 -to sw[5]
set_location_assignment PIN_W12 -to sw[4]
set_location_assignment PIN_V12 -to sw[3]
set_location_assignment PIN_M22 -to sw[2]
set_location_assignment PIN_L21 -to sw[1]
set_location_assignment PIN_L22 -to sw[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top