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schematic_basic_morse_readout.sch
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<wire x1="2.9972" y1="-2.3622" x2="2.9972" y2="-2.0574" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="-2.0574" x2="1.9558" y2="-2.0828" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="-1.4224" x2="1.9558" y2="-1.7272" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="-1.7272" x2="2.9972" y2="-1.7272" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="-1.7272" x2="2.9972" y2="-1.4224" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="-1.4224" x2="1.9558" y2="-1.4224" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="-0.8128" x2="1.9558" y2="-1.1176" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="-1.1176" x2="2.9972" y2="-1.0922" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="-1.0922" x2="2.9972" y2="-0.7874" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="-0.7874" x2="1.9558" y2="-0.8128" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="-0.1524" x2="1.9558" y2="-0.4572" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="-0.4572" x2="2.9972" y2="-0.4572" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="-0.4572" x2="2.9972" y2="-0.1524" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="-0.1524" x2="1.9558" y2="-0.1524" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="0.4572" x2="1.9558" y2="0.1524" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="0.1524" x2="2.9972" y2="0.1778" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="0.1778" x2="2.9972" y2="0.4826" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="0.4826" x2="1.9558" y2="0.4572" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="1.1176" x2="1.9558" y2="0.8128" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="0.8128" x2="2.9972" y2="0.8128" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="0.8128" x2="2.9972" y2="1.1176" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="1.1176" x2="1.9558" y2="1.1176" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="1.7272" x2="1.9558" y2="1.4224" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="1.4224" x2="2.9972" y2="1.4478" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="1.4478" x2="2.9972" y2="1.7526" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="1.7526" x2="1.9558" y2="1.7272" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="2.3876" x2="1.9558" y2="2.0828" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="2.0828" x2="2.9972" y2="2.0828" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="2.0828" x2="2.9972" y2="2.3876" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="2.3876" x2="1.9558" y2="2.3876" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="2.9972" x2="1.9558" y2="2.6924" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="2.6924" x2="2.9972" y2="2.7178" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="2.7178" x2="2.9972" y2="3.0226" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="3.0226" x2="1.9558" y2="2.9972" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="3.6576" x2="1.9558" y2="3.3528" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="3.3528" x2="2.9972" y2="3.3528" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="3.3528" x2="2.9972" y2="3.6576" width="0.1524" layer="51"/>
<wire x1="2.9972" y1="3.6576" x2="1.9558" y2="3.6576" width="0.1524" layer="51"/>
<wire x1="-1.9558" y1="-4.318" x2="1.9558" y2="-4.318" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="-4.318" x2="1.9558" y2="4.318" width="0.1524" layer="51"/>
<wire x1="1.9558" y1="4.318" x2="-0.3048" y2="4.318" width="0.1524" layer="51"/>
<wire x1="-0.3048" y1="4.318" x2="-1.9558" y2="4.318" width="0.1524" layer="51"/>
<wire x1="-1.9558" y1="4.318" x2="-1.9558" y2="-4.318" width="0.1524" layer="51"/>
<wire x1="0.3048" y1="4.3434" x2="-0.3048" y2="4.318" width="0.1524" layer="51" curve="-180"/>
<text x="-2.159" y="2.9972" size="1.27" layer="51" ratio="6" rot="SR0">*</text>
<text x="-3.2766" y="-0.635" size="1.27" layer="25" ratio="6" rot="SR0">>Name</text>
</package>
</packages>
<symbols>
<symbol name="SI4735-D60-GU">
<pin name="DOUT" x="2.54" y="0" length="middle" direction="out"/>
<pin name="DFS" x="2.54" y="-2.54" length="middle" direction="in"/>
<pin name="GPO3/[DCLK]" x="2.54" y="-5.08" length="middle"/>
<pin name="GPO2/[INT]" x="2.54" y="-7.62" length="middle"/>
<pin name="GPO1" x="2.54" y="-10.16" length="middle" direction="out"/>
<pin name="NC_2" x="2.54" y="-12.7" length="middle" direction="nc"/>
<pin name="NC_3" x="2.54" y="-15.24" length="middle" direction="nc"/>
<pin name="FMI" x="2.54" y="-17.78" length="middle" direction="in"/>
<pin name="RFGND" x="2.54" y="-20.32" length="middle" direction="pas"/>
<pin name="NC_4" x="2.54" y="-22.86" length="middle" direction="nc"/>
<pin name="NC" x="2.54" y="-25.4" length="middle" direction="nc"/>
<pin name="AMI" x="2.54" y="-27.94" length="middle" direction="in"/>
<pin name="GND_2" x="68.58" y="-27.94" length="middle" direction="pas" rot="R180"/>
<pin name="GND" x="68.58" y="-25.4" length="middle" direction="pas" rot="R180"/>
<pin name="!RST" x="68.58" y="-22.86" length="middle" direction="in" rot="R180"/>
<pin name="!SEN" x="68.58" y="-20.32" length="middle" direction="in" rot="R180"/>
<pin name="SCLK" x="68.58" y="-17.78" length="middle" direction="in" rot="R180"/>
<pin name="SDIO" x="68.58" y="-15.24" length="middle" rot="R180"/>
<pin name="RCLK" x="68.58" y="-12.7" length="middle" direction="in" rot="R180"/>
<pin name="VD" x="68.58" y="-10.16" length="middle" direction="pwr" rot="R180"/>
<pin name="VA" x="68.58" y="-7.62" length="middle" direction="pwr" rot="R180"/>
<pin name="DBYP" x="68.58" y="-5.08" length="middle" direction="pas" rot="R180"/>
<pin name="ROUT/[DOUT]" x="68.58" y="-2.54" length="middle" direction="out" rot="R180"/>
<pin name="LOUT/[DFS]" x="68.58" y="0" length="middle" direction="out" rot="R180"/>
<wire x1="7.62" y1="5.08" x2="7.62" y2="-33.02" width="0.1524" layer="94"/>
<wire x1="7.62" y1="-33.02" x2="63.5" y2="-33.02" width="0.1524" layer="94"/>
<wire x1="63.5" y1="-33.02" x2="63.5" y2="5.08" width="0.1524" layer="94"/>
<wire x1="63.5" y1="5.08" x2="7.62" y2="5.08" width="0.1524" layer="94"/>
<text x="30.8356" y="9.1186" size="2.0828" layer="95" ratio="6" rot="SR0">>Name</text>
<text x="30.2006" y="6.5786" size="2.0828" layer="96" ratio="6" rot="SR0">>Value</text>
</symbol>
</symbols>
<devicesets>
<deviceset name="SI4735-D60-GU" prefix="U">
<gates>
<gate name="A" symbol="SI4735-D60-GU" x="0" y="0"/>
</gates>
<devices>
<device name="" package="SSOP24_SIL">
<connects>
<connect gate="A" pin="!RST" pad="15"/>
<connect gate="A" pin="!SEN" pad="16"/>
<connect gate="A" pin="AMI" pad="12"/>
<connect gate="A" pin="DBYP" pad="22"/>
<connect gate="A" pin="DFS" pad="2"/>
<connect gate="A" pin="DOUT" pad="1"/>
<connect gate="A" pin="FMI" pad="8"/>
<connect gate="A" pin="GND" pad="14"/>
<connect gate="A" pin="GND_2" pad="13"/>
<connect gate="A" pin="GPO1" pad="5"/>
<connect gate="A" pin="GPO2/[INT]" pad="4"/>
<connect gate="A" pin="GPO3/[DCLK]" pad="3"/>
<connect gate="A" pin="LOUT/[DFS]" pad="24"/>
<connect gate="A" pin="NC" pad="11"/>
<connect gate="A" pin="NC_2" pad="6"/>
<connect gate="A" pin="NC_3" pad="7"/>
<connect gate="A" pin="NC_4" pad="10"/>
<connect gate="A" pin="RCLK" pad="19"/>
<connect gate="A" pin="RFGND" pad="9"/>
<connect gate="A" pin="ROUT/[DOUT]" pad="23"/>
<connect gate="A" pin="SCLK" pad="17"/>
<connect gate="A" pin="SDIO" pad="18"/>
<connect gate="A" pin="VA" pad="21"/>
<connect gate="A" pin="VD" pad="20"/>
</connects>
<technologies>
<technology name="">
<attribute name="BUILT_BY" value="EMA_Cory" constant="no"/>
<attribute name="COPYRIGHT" value="Copyright (C) 2018 Accelerated Designs. All rights reserved" constant="no"/>
<attribute name="DATASHEET" value="https://www.silabs.com/documents/public/data-sheets/Si4730-31-34-35-D60.pdf" constant="no"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="SI4735-D60-GU" constant="no"/>
<attribute name="SOURCELIBRARY" value="Silicon_Labs_2020-04-23" constant="no"/>
<attribute name="VENDOR" value="Silicon Labs" constant="no"/>
</technology>
</technologies>
</device>
<device name="SSOP24_SIL-M" package="SSOP24_SIL-M">
<connects>
<connect gate="A" pin="!RST" pad="15"/>
<connect gate="A" pin="!SEN" pad="16"/>
<connect gate="A" pin="AMI" pad="12"/>
<connect gate="A" pin="DBYP" pad="22"/>
<connect gate="A" pin="DFS" pad="2"/>
<connect gate="A" pin="DOUT" pad="1"/>
<connect gate="A" pin="FMI" pad="8"/>
<connect gate="A" pin="GND" pad="14"/>
<connect gate="A" pin="GND_2" pad="13"/>
<connect gate="A" pin="GPO1" pad="5"/>
<connect gate="A" pin="GPO2/[INT]" pad="4"/>
<connect gate="A" pin="GPO3/[DCLK]" pad="3"/>
<connect gate="A" pin="LOUT/[DFS]" pad="24"/>
<connect gate="A" pin="NC" pad="11"/>
<connect gate="A" pin="NC_2" pad="6"/>
<connect gate="A" pin="NC_3" pad="7"/>
<connect gate="A" pin="NC_4" pad="10"/>
<connect gate="A" pin="RCLK" pad="19"/>
<connect gate="A" pin="RFGND" pad="9"/>
<connect gate="A" pin="ROUT/[DOUT]" pad="23"/>
<connect gate="A" pin="SCLK" pad="17"/>
<connect gate="A" pin="SDIO" pad="18"/>
<connect gate="A" pin="VA" pad="21"/>
<connect gate="A" pin="VD" pad="20"/>
</connects>
<technologies>
<technology name="">
<attribute name="BUILT_BY" value="EMA_Cory" constant="no"/>
<attribute name="COPYRIGHT" value="Copyright (C) 2018 Accelerated Designs. All rights reserved" constant="no"/>
<attribute name="DATASHEET" value="https://www.silabs.com/documents/public/data-sheets/Si4730-31-34-35-D60.pdf" constant="no"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="SI4735-D60-GU" constant="no"/>
<attribute name="SOURCELIBRARY" value="Silicon_Labs_2020-04-23" constant="no"/>
<attribute name="VENDOR" value="Silicon Labs" constant="no"/>
</technology>
</technologies>
</device>
<device name="SSOP24_SIL-L" package="SSOP24_SIL-L">
<connects>
<connect gate="A" pin="!RST" pad="15"/>
<connect gate="A" pin="!SEN" pad="16"/>
<connect gate="A" pin="AMI" pad="12"/>
<connect gate="A" pin="DBYP" pad="22"/>
<connect gate="A" pin="DFS" pad="2"/>
<connect gate="A" pin="DOUT" pad="1"/>
<connect gate="A" pin="FMI" pad="8"/>
<connect gate="A" pin="GND" pad="14"/>
<connect gate="A" pin="GND_2" pad="13"/>
<connect gate="A" pin="GPO1" pad="5"/>
<connect gate="A" pin="GPO2/[INT]" pad="4"/>
<connect gate="A" pin="GPO3/[DCLK]" pad="3"/>
<connect gate="A" pin="LOUT/[DFS]" pad="24"/>
<connect gate="A" pin="NC" pad="11"/>
<connect gate="A" pin="NC_2" pad="6"/>
<connect gate="A" pin="NC_3" pad="7"/>
<connect gate="A" pin="NC_4" pad="10"/>
<connect gate="A" pin="RCLK" pad="19"/>
<connect gate="A" pin="RFGND" pad="9"/>
<connect gate="A" pin="ROUT/[DOUT]" pad="23"/>
<connect gate="A" pin="SCLK" pad="17"/>
<connect gate="A" pin="SDIO" pad="18"/>
<connect gate="A" pin="VA" pad="21"/>
<connect gate="A" pin="VD" pad="20"/>
</connects>
<technologies>
<technology name="">
<attribute name="BUILT_BY" value="EMA_Cory" constant="no"/>
<attribute name="COPYRIGHT" value="Copyright (C) 2018 Accelerated Designs. All rights reserved" constant="no"/>
<attribute name="DATASHEET" value="https://www.silabs.com/documents/public/data-sheets/Si4730-31-34-35-D60.pdf" constant="no"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="SI4735-D60-GU" constant="no"/>
<attribute name="SOURCELIBRARY" value="Silicon_Labs_2020-04-23" constant="no"/>
<attribute name="VENDOR" value="Silicon Labs" constant="no"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="supply1" urn="urn:adsk.eagle:library:371">
<description><b>Supply Symbols</b><p>
GND, VCC, 0V, +5V, -5V, etc.<p>
Please keep in mind, that these devices are necessary for the
automatic wiring of the supply signals.<p>
The pin name defined in the symbol is identical to the net which is to be wired automatically.<p>
In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p>
<author>Created by librarian@cadsoft.de</author></description>
<packages>
</packages>
<symbols>
<symbol name="GND" urn="urn:adsk.eagle:symbol:26925/1" library_version="1">
<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text>
<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="GND" urn="urn:adsk.eagle:component:26954/1" prefix="GND" library_version="1">
<description><b>SUPPLY SYMBOL</b></description>
<gates>
<gate name="1" symbol="GND" x="0" y="0"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="SparkFun-Resistors" urn="urn:adsk.eagle:library:532">
<description><h3>SparkFun Resistors</h3>
This library contains resistors. Reference designator:R.
<br>
<br>
We've spent an enormous amount of time creating and checking these footprints and parts, but it is <b> the end user's responsibility</b> to ensure correctness and suitablity for a given componet or application.
<br>
<br>If you enjoy using this library, please buy one of our products at <a href=" www.sparkfun.com">SparkFun.com</a>.
<br>
<br>
<b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/
<br>
<br>
You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage.</description>
<packages>
<package name="0603" urn="urn:adsk.eagle:footprint:39615/1" library_version="1">
<description><p><b>Generic 1608 (0603) package</b></p>
<p>0.2mm courtyard excess rounded to nearest 0.05mm.</p></description>
<wire x1="-1.6" y1="0.7" x2="1.6" y2="0.7" width="0.0508" layer="39"/>
<wire x1="1.6" y1="0.7" x2="1.6" y2="-0.7" width="0.0508" layer="39"/>
<wire x1="1.6" y1="-0.7" x2="-1.6" y2="-0.7" width="0.0508" layer="39"/>
<wire x1="-1.6" y1="-0.7" x2="-1.6" y2="0.7" width="0.0508" layer="39"/>
<wire x1="-0.356" y1="0.432" x2="0.356" y2="0.432" width="0.1016" layer="51"/>
<wire x1="-0.356" y1="-0.419" x2="0.356" y2="-0.419" width="0.1016" layer="51"/>
<smd name="1" x="-0.85" y="0" dx="1.1" dy="1" layer="1"/>
<smd name="2" x="0.85" y="0" dx="1.1" dy="1" layer="1"/>
<text x="0" y="0.762" size="0.6096" layer="25" font="vector" ratio="20" align="bottom-center">>NAME</text>
<text x="0" y="-0.762" size="0.6096" layer="27" font="vector" ratio="20" align="top-center">>VALUE</text>
<rectangle x1="-0.8382" y1="-0.4699" x2="-0.3381" y2="0.4801" layer="51"/>
<rectangle x1="0.3302" y1="-0.4699" x2="0.8303" y2="0.4801" layer="51"/>
<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/>
</package>
</packages>
<packages3d>
<package3d name="0603" urn="urn:adsk.eagle:package:39650/1" type="box" library_version="1">
<description>Generic 1608 (0603) package
0.2mm courtyard excess rounded to nearest 0.05mm.</description>
<packageinstances>
<packageinstance name="0603"/>
</packageinstances>
</package3d>
</packages3d>
<symbols>
<symbol name="RESISTOR" urn="urn:adsk.eagle:symbol:39614/1" library_version="1">
<wire x1="-2.54" y1="0" x2="-2.159" y2="1.016" width="0.1524" layer="94"/>
<wire x1="-2.159" y1="1.016" x2="-1.524" y2="-1.016" width="0.1524" layer="94"/>
<wire x1="-1.524" y1="-1.016" x2="-0.889" y2="1.016" width="0.1524" layer="94"/>
<wire x1="-0.889" y1="1.016" x2="-0.254" y2="-1.016" width="0.1524" layer="94"/>
<wire x1="-0.254" y1="-1.016" x2="0.381" y2="1.016" width="0.1524" layer="94"/>
<wire x1="0.381" y1="1.016" x2="1.016" y2="-1.016" width="0.1524" layer="94"/>
<wire x1="1.016" y1="-1.016" x2="1.651" y2="1.016" width="0.1524" layer="94"/>
<wire x1="1.651" y1="1.016" x2="2.286" y2="-1.016" width="0.1524" layer="94"/>
<wire x1="2.286" y1="-1.016" x2="2.54" y2="0" width="0.1524" layer="94"/>
<text x="0" y="1.524" size="1.778" layer="95" font="vector" align="bottom-center">>NAME</text>
<text x="0" y="-1.524" size="1.778" layer="96" font="vector" align="top-center">>VALUE</text>
<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="2.2KOHM" urn="urn:adsk.eagle:component:39698/1" prefix="R" library_version="1">
<description><h3>2.2kΩ resistor</h3>
<p>A resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element. Resistors act to reduce current flow, and, at the same time, act to lower voltage levels within circuits. - Wikipedia</p></description>
<gates>
<gate name="G$1" symbol="RESISTOR" x="0" y="0"/>
</gates>
<devices>
<device name="-0603-1/10W-1%" package="0603">
<connects>
<connect gate="G$1" pin="1" pad="1"/>
<connect gate="G$1" pin="2" pad="2"/>
</connects>
<package3dinstances>
<package3dinstance package3d_urn="urn:adsk.eagle:package:39650/1"/>
</package3dinstances>
<technologies>
<technology name="">
<attribute name="PROD_ID" value="RES-08272"/>
<attribute name="VALUE" value="2.2k"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="3.3KOHM" urn="urn:adsk.eagle:component:39713/1" prefix="R" library_version="1">
<description><h3>3.3kΩ resistor</h3>
<p>A resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element. Resistors act to reduce current flow, and, at the same time, act to lower voltage levels within circuits. - Wikipedia</p></description>
<gates>
<gate name="G$1" symbol="RESISTOR" x="0" y="0"/>
</gates>
<devices>
<device name="-0603-1/10W-1%" package="0603">
<connects>
<connect gate="G$1" pin="1" pad="1"/>
<connect gate="G$1" pin="2" pad="2"/>
</connects>
<package3dinstances>
<package3dinstance package3d_urn="urn:adsk.eagle:package:39650/1"/>
</package3dinstances>
<technologies>
<technology name="">
<attribute name="PROD_ID" value="RES-07851"/>
<attribute name="VALUE" value="3.3k"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="1.5KOHM" urn="urn:adsk.eagle:component:39684/1" prefix="R" library_version="1">
<description><h3>1.5kΩ resistor</h3>
<p>A resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element. Resistors act to reduce current flow, and, at the same time, act to lower voltage levels within circuits. - Wikipedia</p></description>
<gates>
<gate name="G$1" symbol="RESISTOR" x="0" y="0"/>
</gates>
<devices>
<device name="-0603-1/10W-1%" package="0603">
<connects>
<connect gate="G$1" pin="1" pad="1"/>
<connect gate="G$1" pin="2" pad="2"/>
</connects>
<package3dinstances>
<package3dinstance package3d_urn="urn:adsk.eagle:package:39650/1"/>
</package3dinstances>
<technologies>
<technology name="">
<attribute name="PROD_ID" value="RES-08306"/>
<attribute name="VALUE" value="1.5k"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="supply2" urn="urn:adsk.eagle:library:372">
<description><b>Supply Symbols</b><p>
GND, VCC, 0V, +5V, -5V, etc.<p>
Please keep in mind, that these devices are necessary for the
automatic wiring of the supply signals.<p>
The pin name defined in the symbol is identical to the net which is to be wired automatically.<p>
In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p>
<author>Created by librarian@cadsoft.de</author></description>
<packages>
</packages>
<symbols>
<symbol name="VCC" urn="urn:adsk.eagle:symbol:26997/1" library_version="2">
<circle x="0" y="1.27" radius="1.27" width="0.254" layer="94"/>
<text x="-1.905" y="3.175" size="1.778" layer="96">>VALUE</text>
<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="VCC" urn="urn:adsk.eagle:component:27060/1" prefix="SUPPLY" library_version="2">
<description><b>SUPPLY SYMBOL</b></description>
<gates>
<gate name="G$1" symbol="VCC" x="0" y="0"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="SparkFun-Capacitors" urn="urn:adsk.eagle:library:510">
<description><h3>SparkFun Capacitors</h3>
This library contains capacitors.
<br>
<br>
We've spent an enormous amount of time creating and checking these footprints and parts, but it is <b> the end user's responsibility</b> to ensure correctness and suitablity for a given componet or application.
<br>
<br>If you enjoy using this library, please buy one of our products at <a href=" www.sparkfun.com">SparkFun.com</a>.
<br>
<br>
<b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/
<br>
<br>
You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage.</description>
<packages>
<package name="0603" urn="urn:adsk.eagle:footprint:37386/1" library_version="1">
<description><p><b>Generic 1608 (0603) package</b></p>
<p>0.2mm courtyard excess rounded to nearest 0.05mm.</p></description>
<wire x1="-1.6" y1="0.7" x2="1.6" y2="0.7" width="0.0508" layer="39"/>
<wire x1="1.6" y1="0.7" x2="1.6" y2="-0.7" width="0.0508" layer="39"/>
<wire x1="1.6" y1="-0.7" x2="-1.6" y2="-0.7" width="0.0508" layer="39"/>
<wire x1="-1.6" y1="-0.7" x2="-1.6" y2="0.7" width="0.0508" layer="39"/>
<wire x1="-0.356" y1="0.432" x2="0.356" y2="0.432" width="0.1016" layer="51"/>
<wire x1="-0.356" y1="-0.419" x2="0.356" y2="-0.419" width="0.1016" layer="51"/>
<smd name="1" x="-0.85" y="0" dx="1.1" dy="1" layer="1"/>
<smd name="2" x="0.85" y="0" dx="1.1" dy="1" layer="1"/>
<text x="0" y="0.762" size="0.6096" layer="25" font="vector" ratio="20" align="bottom-center">>NAME</text>
<text x="0" y="-0.762" size="0.6096" layer="27" font="vector" ratio="20" align="top-center">>VALUE</text>
<rectangle x1="-0.8382" y1="-0.4699" x2="-0.3381" y2="0.4801" layer="51"/>
<rectangle x1="0.3302" y1="-0.4699" x2="0.8303" y2="0.4801" layer="51"/>
<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/>
</package>
<package name="CAP-PTH-2.54" urn="urn:adsk.eagle:footprint:37402/1" library_version="1">
<description>2 PTH spaced 0.1" apart</description>
<wire x1="0" y1="0.635" x2="0" y2="-0.635" width="0.2032" layer="21"/>
<pad name="1" x="-1.27" y="0" drill="0.7" diameter="1.651"/>
<pad name="2" x="1.27" y="0" drill="0.7" diameter="1.651"/>
<text x="0" y="1.016" size="0.6096" layer="25" font="vector" ratio="20" align="bottom-center">>Name</text>
<text x="0" y="-1.016" size="0.6096" layer="27" font="vector" ratio="20" align="top-center">>Value</text>
</package>
<package name="1206" urn="urn:adsk.eagle:footprint:37399/1" library_version="1">
<description><p><b>Generic 3216 (1206) package</b></p>
<p>0.2mm courtyard excess rounded to nearest 0.05mm.</p></description>