From 1c7bdf271d6c386645206a366a2d6ba63dbc0027 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 3 Jul 2024 15:32:06 +0200 Subject: [PATCH] axi_xbar_unmuxed: add to Readme, fusesoc, src_files --- README.md | 1 + axi.core | 4 +++- src_files.yml | 4 +++- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 83c37e32e..6f798139e 100644 --- a/README.md +++ b/README.md @@ -67,6 +67,7 @@ In addition to the documents linked in the following table, we are setting up [d | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv) | AXI4 to AXI4-Lite protocol converter. | | | [`axi_to_mem`](src/axi_to_mem.sv) | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked, interleaved, split variant. | | | [`axi_xbar`](src/axi_xbar.sv) | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) | +| [`axi_xbar_unmuxed`](src/axi_xbar_unmuxed.sv) | Demux side of fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) | | [`axi_xp`](src/axi_xp.sv) | AXI Crosspoint (XP) with homomorphous slave and master ports. | | | [`axi_zero_mem`](src/axi_zero_mem.sv) | AXI-attached /dev/zero. All reads will be zero, writes are absorbed. | | diff --git a/axi.core b/axi.core index a68f7648c..5c60a6969 100644 --- a/axi.core +++ b/axi.core @@ -64,7 +64,7 @@ filesets: - src/axi_interleaved_xbar.sv - src/axi_iw_converter.sv - src/axi_lite_xbar.sv - - src/axi_xbar.sv + - src/axi_xbar_unmuxed.sv - src/axi_to_mem_banked.sv - src/axi_to_mem_interleaved.sv - src/axi_to_mem_split.sv @@ -73,6 +73,8 @@ filesets: - src/axi_sim_mem.sv - src/axi_test.sv # Level 5 + - src/axi_xbar.sv + # Level 6 - src/axi_xp.sv file_type : systemVerilogSource depend : diff --git a/src_files.yml b/src_files.yml index ae79a8d43..451c85658 100644 --- a/src_files.yml +++ b/src_files.yml @@ -63,11 +63,13 @@ axi: - src/axi_interleaved_xbar.sv - src/axi_iw_converter.sv - src/axi_lite_xbar.sv - - src/axi_xbar.sv + - src/axi_xbar_unmuxed.sv - src/axi_to_mem_banked.sv - src/axi_to_mem_interleaved.sv - src/axi_to_mem_split.sv # Level 5 + - src/axi_xbar.sv + # Level 6 - src/axi_xp.sv axi_sim: