diff --git a/src/axi_bus_compare.sv b/src/axi_bus_compare.sv
index 803b593e5..e1a3426ee 100644
--- a/src/axi_bus_compare.sv
+++ b/src/axi_bus_compare.sv
@@ -355,7 +355,7 @@ module axi_bus_compare #(
             .flush_i   ( 1'b0 ),
             .usage_o   (),
             .data_i    ( {axi_a_req_i.aw.addr[$clog2(DataWidth/8)-1:0], axi_a_req_i.aw.size} ),
-            .valid_i   ( fifo_valid_aw_a [id] & fifo_ready_aw_a [id] ),
+            .valid_i   ( axi_a_req_i.aw_valid & axi_a_rsp_o.aw_ready ),
             .ready_o   (),
             .data_o    ( {w_offset, w_size} ),
             .valid_o   (),
diff --git a/src/axi_to_detailed_mem.sv b/src/axi_to_detailed_mem.sv
index d66c4d143..2ea01f3bf 100644
--- a/src/axi_to_detailed_mem.sv
+++ b/src/axi_to_detailed_mem.sv
@@ -533,9 +533,9 @@ module axi_to_detailed_mem #(
                                      ((i*NumBytesPerBank) < ((meta_buf.addr % DataWidth/8) + 1<<meta_buf.size));
   end
   assign resp_b_err    = |(m2s_resp.err    &  meta_buf_bank_strb);   // Ensure only active banks are used (strobe)
-  assign resp_b_exokay = &(m2s_resp.exokay | ~meta_buf_bank_strb);   // Ensure only active banks are used (strobe)
+  assign resp_b_exokay = &(m2s_resp.exokay | ~meta_buf_bank_strb) & meta_buf.lock;   // Ensure only active banks are used (strobe)
   assign resp_r_err    = |(m2s_resp.err    &  meta_buf_size_enable); // Ensure only active banks are used (size & addr offset)
-  assign resp_r_exokay = &(m2s_resp.exokay | ~meta_buf_size_enable); // Ensure only active banks are used (size & addr offset)
+  assign resp_r_exokay = &(m2s_resp.exokay | ~meta_buf_size_enable) & meta_buf.lock; // Ensure only active banks are used (size & addr offset)
 
   logic collect_b_err_d, collect_b_err_q;
   logic collect_b_exokay_d, collect_b_exokay_q;