.gitlab-ci.yml

# Copyright 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Paul Scheffler <paulsc@iis.ee.ethz.ch>
# Robert Balas <balasr@iis.ee.ethz.ch>

# We initialize the nonfree repo, then spawn a sub-pipeline from it for the
# nonfree jobs. Regular jobs will be spawned here

variables:
  GIT_SUBMODULE_STRATEGY: recursive
  GIT_SUBMODULE_DEPTH: 5
  RISCV: "/home/balasr/.riscv-10.2"
  PULP_RUNTIME_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0"
  CPULP_INSTALL: "/home/balasr/.aarch64-8.3.0"
  VERILATOR: "/home/balasr/.local/bin/verilator"
  BENDER: "/home/balasr/.local/bin/bender"
  QUESTA: "questa-2022.3"
  VCSSIM: "vcs-2020.12"

stages:
  - prepare
  - build
  - test

# nonfree subpipline

init-nonfree:
  stage: prepare
  tags: [ tech ]
  script: make nonfree-init
  artifacts:
    paths: [ nonfree/ ]

nonfree:
  stage: test
  needs: [ init-nonfree ]
  trigger:
    include:
      - artifact: nonfree/ci.yml
        job: init-nonfree
    strategy: depend

# free jobs
.base:
  artifacts:
    when: always
    expire_in: 18 weeks

prepare:
  extends: .base
  stage: prepare
  script:
    - echo "Fetch submodule dependencies (skipping)"
    - echo "Fetch VIPs"
    - ./tb/vip/get-vips.sh --yes #--gitlab
    - echo "Generate scripts with DPI and VIP support"
    - $QUESTA make gen-with-vip

  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - sim/flist/*
      - tb/vip/*

questa_rtl:
  extends: .base
  needs: [ prepare ]
  stage: build
  before_script:
  script:
    - echo "Compiling RTL model and DPI libraries"
    - $QUESTA make SIM_TOP=tb_sw build
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - sim/*
      - tb/*

vcs_rtl:
  extends: .base
  needs: [ prepare ]
  stage: build
  before_script:
  script:
    - echo "Compiling RTL model"
    - $VCSSIM make vcsify
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - sim/simv

verilator_rtl:
  extends: .base
  needs: [ prepare ]
  stage: build
  before_script:
  script:
    - echo "Compiling RTL model"
    - make verilate
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
      - sim/vpms

.sim-vsim-runtime-tpl:
  stage: test
  before_script:
   - echo "Generate scripts with DPI and VIP support"
   - $QUESTA make gen-with-vip
   - echo "Compiling RTL model and DPI libraries"
   - $QUESTA make SIM_TOP=tb_sw build

.sim-vsim-freertos-tpl:
  stage: test
  before_script:
    - echo "Generate scripts with DPI and VIP support"
    - $QUESTA make gen-with-vip
    - echo "Compiling RTL model and DPI libraries"
    - $QUESTA make all SIM_TOP=${TOP}

.sim-vsim-junit-report-tpl:
  artifacts:
   name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
   paths:
     - sw/tests/${XML_DIR}/*.html
     - sw/tests/${XML_DIR}/*.xml
   reports:
     junit: sw/tests/${XML_DIR}/*.xml

# Use simplified pulp-runtime to run a subset of tests
rt_periph:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-periph

rt_ml:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-ml

rt_riscv:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-riscv

rt_seq:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-seq-bare

rt_par:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-par-bare

rt_perfcounters:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-perfcounters

rt_control_pulp:
  variables: { XML_DIR: "control-pulp-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-control-pulp

#rt_sensors_rx:
#  stage: test
#  before_script:
#    - echo "Compiling RTL model and DPI libraries"
#    - $QUESTA make SIM_TOP=tb_sw build
#  script:
#    - echo "Running software test"
#    - $QUESTA make test-rx-mchan
#  artifacts:
#    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
#    paths:
#      - sw/tests/control-pulp-tests/sensors_transfers/*.html
#      - sw/tests/control-pulp-tests/sensors_transfers/*.xml
#    reports:
#      junit: sw/tests/control-pulp-tests/sensors_transfers/*.xml

pvt_sensors_idma_cl:
  variables: { XML_DIR: "control-pulp-tests/sensor_transfers" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  before_script:
    - echo "Compiling RTL model and DPI libraries"
    - $QUESTA make SIM_TOP=tb_sw build
  script:
    - echo "Running software test"
    - $QUESTA make test-rx-idma

rt_tcdm:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-tcdm

rt_soc_interconnect:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-soc-interconnect

#rt_mchan:
#  stage: test
#  before_script:
#    - echo "Compiling RTL model and DPI libraries"
#    - $QUESTA make SIM_TOP=tb_sw build
#  script:
#    - echo "Running software test"
#    - $QUESTA make test-rt-mchan
#  artifacts:
#    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
#    paths:
#      - sw/tests/runtime-tests/*.html
#      - sw/tests/runtime-tests/*.xml
#    reports:
#      junit: sw/tests/runtime-tests/*.xml

rt_idma:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-idma

rt_coremark:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-rt-coremark

rt_avs:
  variables: { XML_DIR: "runtime-tests" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-avs

rt_i2c_slv_irq:
  variables: { XML_DIR: "runtime-tests", TOP: "tb_i2c_slv_irq_fpga" }
#  needs: [ build ]
  extends: [ .base, .sim-vsim-runtime-tpl, .sim-vsim-junit-report-tpl ]
  stage: test
  script:
    - echo "Running software test"
    - $QUESTA make test-i2c-slv-irq

# Freertos
freertos_semaphore:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  script:
    - source env/env.sh
    - cd sw/freertos/tests/semaphore
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/semaphore

freertos_queue:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/queue
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/queue

freertos_streambufferisr:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/streambufferisr
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/streambufferisr

freertos_uart:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/uart
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/uart

# TODO: figure out why the testbench regressed (DPI library load issue)
# freertos_spi:
#   stage: test
#   before_script:
#     - echo "Generate scripts with DPI and VIP support"
#     - $QUESTA make gen-with-vip
#     - echo "Compiling RTL model and DPI libraries"
#     - $QUESTA make all SIM_TOP=tb_sw
#     - echo "Installing freertos"
#   script:
#     - source env/env.sh
#     - cd sw/freertos/tests/spi
#     - $QUESTA make SIM_TOP=tb_sw all run DPI=yes
#   artifacts:
#     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
#     paths:
#      - sw/freertos/tests/spi

freertos_i2c_eeprom:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/i2c_eeprom
    - $QUESTA make SIM_TOP=tb_sw all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/i2c_eeprom

freertos_i2c_scan:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/i2c_scan
    - $QUESTA make SIM_TOP=tb_sw all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/i2c_scan

freertos_hello_world:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/hello_world_pmsis
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/hello_world_pmsis

freertos_cluster_offload_sync:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/cluster/cluster_fork_sync
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" clean all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/cluster/cluster_fork_sync

freertos_cluster_offload_async:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/cluster/cluster_fork_async
    - $QUESTA make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" clean all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/cluster/cluster_fork_async

freertos_cluster_idma_basic:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/cluster/dma/idma/idma_basic
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" clean all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/cluster/dma/idma/idma_basic

freertos_cluster_idma_basic_8cores:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/cluster/dma/idma/idma_basic_8cores
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" clean all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/cluster/dma/idma/idma_basic_8cores

# freertos_pms_fw_noio:
#   extends: .sim-vsim-freertos-tpl
#   variables: { TOP: "tb_sw" }
#   stage: test
#   script:
#     - source env/env.sh
#     - cd fw
#     - $QUESTA make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" MAKE_FLAGS="-DUSE_INSTRUCTIONS_COMPOSITION -DTASKS_PERIOD_MULTIPLIER=5 -DCI_TEST -DCI_TEST_ITERATION=20 -UMEASURE_ACTIVE -DPRINTF_ACTIVE -DPCF_FREERTOS_TICK_RATE_HZ=1000 -DDEFAULT_SYSTEM_CLOCK=100000000u" all run
#   artifacts:
#     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
#     paths:
#      - fw
# 
# freertos_pms_fw_io:
#   extends: .sim-vsim-freertos-tpl
#   variables: { TOP: "tb_fw" }
#   stage: test
#   before_script:
#     - echo "Installing PMS firmware"
#     - make firmware
#     - export PCF_PLATFORM=DATE_PAPER
#   script:
#     - source env/env.sh
#     - cd fw
#     - $QUESTA make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" MAKE_FLAGS="-DTASKS_PERIOD_MULTIPLIER=5 -UCI_TEST -DMEASURE_ACTIVE=1 -DMEASURE_N_ITERATION=20 -DMEASURE_N_OUTPUTS=64 -DPRINTF_ACTIVE -DPCF_FREERTOS_TICK_RATE_HZ=1000 -DDEFAULT_SYSTEM_CLOCK=100000000u" all run
#   artifacts:
#     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
#     paths:
#      - fw
# 
# freertos_pms_fw_io_cluster_sync_offload:
#   extends: .sim-vsim-freertos-tpl
#   variables: { TOP: "tb_fw" }
#   stage: test
#   before_script:
#     - echo "Installing PMS firmware"
#     - make firmware
#     - export PCF_PLATFORM=DATE_PAPER
#   script:
#     - source env/env.sh
#     - cd fw
#     - $QUESTA make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" MAKE_FLAGS="-DTASKS_PERIOD_MULTIPLIER=5 -UCI_TEST -DMEASURE_ACTIVE=1 -DMEASURE_N_ITERATION=10 -DMEASURE_N_OUTPUTS=72 -DPRINTF_ACTIVE -DPCF_FREERTOS_TICK_RATE_HZ=1000 -DDEFAULT_SYSTEM_CLOCK=100000000u -DPCF_USE_CLUSTER -DPCF_USE_CLUSTER_PARALL" clean all run gui=1
#   artifacts:
#     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
#     paths:
#      - fw
# 
# freertos_pms_fw_io_cluster_async_offload:
#   extends: .sim-vsim-freertos-tpl
#   variables: { TOP: "tb_fw" }
#   stage: test
#   before_script:
#     - echo "Installing PMS firmware"
#     - make firmware
#     - export PCF_PLATFORM=DATE_PAPER
#   script:
#     - source env/env.sh
#     - cd fw
#     - $QUESTA make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" CFLAGS="-Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG" ASFLAGS="-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32" MAKE_FLAGS="-DTASKS_PERIOD_MULTIPLIER=5 -UCI_TEST -DMEASURE_ACTIVE=1 -DMEASURE_N_ITERATION=10 -DMEASURE_N_OUTPUTS=72 -DPRINTF_ACTIVE -DPCF_FREERTOS_TICK_RATE_HZ=1000 -DDEFAULT_SYSTEM_CLOCK=100000000u -DPCF_USE_CLUSTER -DPCF_USE_CLUSTER_PARALL -DPCF_ASYNC" clean all run gui=1
#   artifacts:
#     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
#     paths:
#      - fw

freertos_i2c_slv_dump:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_i2c_slv_dump" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/tests/runtime-tests/peripherals/i2c_slv_dump_freertos
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/tests/runtime-tests/peripherals/i2c_slv_dump_freertos

freertos_acpi_pwr_startup:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_acpi" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/tests/control-pulp-tests/gpio
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/tests/control-pulp-tests/gpio

freertos_mbox_agent_agent:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_sw_fpga" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/tests/control-pulp-tests/clic/clic-mbox-freertos
    - $QUESTA make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/tests/control-pulp-tests/clic/clic-mbox-freertos

freertos_mbox_platform_agent:
  extends: .sim-vsim-freertos-tpl
  variables: { TOP: "tb_mbox_fpga" }
  stage: test
  script:
    - source env/env.sh
    - cd sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos
    - $QUESTA make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos

pms_minimal:
  variables: { TOP: "tb_pms_minimal" }
  stage: test
  script:
    - echo "(Re)generating scripts with DPI disabled"
    - make gen
    - echo "Setting up vsim path"
    - source env/env.sh
    - echo "Compiling RTL model"
    - $QUESTA make all SIM_TOP=${TOP}
    - echo "Running minimal testbench (stim.txt is int main(void) { return 0; })"
    - $QUESTA make simc VSIM_FLAGS=+stimuli=../tb/simvectors/minimal/stim.txt

dm:
  variables: { TOP: "tb_dm" }
  stage: test
  before_script:
  script:
    - echo "Environment"
    - env
    - echo "(Re)generating scripts"
    - make gen
    - echo "Setting up vsim path"
    - source env/env.sh
    - echo "Running debug module testbench"
    - $QUESTA make all simc SIM_TOP=${TOP}


uart_boot:
  variables: { TOP: "tb_uart_boot" }
  stage: test
  before_script:
  script:
    - echo "(Re)generating scripts with DPI disabled"
    - make gen
    - echo "Setting up vsim path"
    - source env/env.sh
    - echo "Running uart boot"
    - $QUESTA make all simc SIM_TOP=${TOP}

boot_fallback:
  variables: { TOP: "tb_bootrom" }
  stage: test
  before_script:
  script:
    - echo "(Re)generating scripts with DPI disabled"
    - make gen
    - echo "Setting up vsim path"
    - source env/env.sh
    - echo "Running boot fallback testbench"
    - $QUESTA make all simc SIM_TOP=${TOP}

jtag_hello_world:
  variables: { TOP: "tb_sw_jtag" }
  extends: .sim-vsim-freertos-tpl
  stage: test
  script:
    - source env/env.sh
    - cd sw/freertos/tests/hello_world_pmsis
    - $QUESTA make RISCV="$PULP_RUNTIME_GCC_TOOLCHAIN" CFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" ASFLAGS="-Os -g3 -march=rv32imc_zfinx_xcorev -mabi=ilp32 -mno-pulp-hwloop" all run
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    paths:
     - sw/freertos/tests/hello_world_pmsis

axi_slv:
  stage: test
  before_script:
  script:
    - echo "(Re)generating scripts with DPI disabled"
    - make gen
    - echo "Setting up vsim path"
    - source env/env.sh
    - echo "Running axi slave testbench"
    - $QUESTA make test-axislv

fpga_synth_linux_zcu102:
  stage: test
  before_script:
  script:
    - echo "Patching unsupported github remote addresses"
    - git config --global url."https://github.com/".insteadOf git://github.com/
    - echo "(Re)generating scripts" # because paths might have changed
    - make gen
    - echo "Starting synthesis with vivado"
    - cd fpga/
    - make zcu102-bitstream VIVADO='vitis-2019.2 vivado'
    - echo "Starting to build linux image"
    - make zcu102-boot-images zcu102-buildroot
  artifacts:
    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
    when: always
    paths:
      - fpga/output/pms.bit
      - fpga/output/pms.hdf
      - fpga/output/BOOT.BIN
      - fpga/output/image.ub
      - fpga/output/rootfs.tar
      - fpga/control_pulp-txilzu9eg/control_pulp-exilzcu102.runs/impl_1/control_pulp_exilzcu102_wrapper.bit
      - fpga/control_pulp-txilzu9eg/control_pulp-txilzu9eg/control_pulp-txilzu9eg.sdk/control_pulp-txilzu9eg_wrapper.hdf
      - fpga/control_pulp-txilzu9eg/control_pulp-exilzcu102.xpr
      - fpga/control_pulp-txilzu9eg/fpga-settings.mk
      - fpga/control_pulp-txilzu9eg/*.jou
      - fpga/control_pulp-txilzu9eg/*.log
      - fpga/control_pulp-txilzu9eg/rtl
      - fpga/control_pulp-txilzu9eg/tcl
      - fpga/control_pulp-txilzu9eg/ips/control_pulp_txilzu9eg/control_pulp-txilzu9eg.xpr
      - fpga/control_pulp-txilzu9eg/ips/control_pulp_txilzu9eg/*.log
      - fpga/control_pulp-txilzu9eg/ips/control_pulp_txilzu9eg/*.jou