QuestaSim fatal error on build

[jenniferhellar]

Recreate:
git clone --recursive https://github.com/pulp-platform/control-pulp.git
source env/env.sh
make all

QuestaSim vlog 2020.3 Compiler 2020.07 Jul 12 2020

-- Loading module FanInPrimitive_Req_FPU
** Warning: This clock divider is deprecated and not reccomended since  the generated output clock has a very unbalanced duty cycle  (1/RATIO). For new designs we reccomend using the at-runtime configurable clk_int_div module which always generates 50%  duty cycle clock. If you don't need at runtime configuration support, you can instantiate clk_int_div as follows to       obtain a module with roughly the same behavior (except for   the 50 % duty cycle):
                                     
                                                             clk_int_div #(
                                               .DIV_VALUE_WIDTH($clog2(RATIO+1)),
                         .DEFAULT_DIV_VALUE(RATIO)
                                ) i_clk_int_div(
                                             .clk_i,
                                                    .rst_ni,
                                                   .test_mode_en_i(testmode_i),
                               .en_i,
                                                     .div_i('1), // Ignored, used default value
                 .div_valid_i(1'b0),
                                        .div_ready_o(),
                                            .clk_o
                                                   );                                                         
                                                           If you know what your are doing and want to disable this     warning message, you can disable it by overriding the new    optional clk_div parameter SHOW_WARNING to 1'b0.
   Scope: tb_sw.fixt_pms.i_dut.i_system_clk_rst_gen.i_clk_div_timer.gen_elab_warning File: /design/ip/riscv/workareas/jhellar1/trunk/riscv/control-pulp/hw/ips/common_cells/src/deprecated/clk_div.sv Line: 46
# vopt_stacktrace.vstf written
** Fatal: Unexpected signal: 11.
/design/ip/riscv/workareas/jhellar1/trunk/riscv/control-pulp/hw/ips/fpu_interco/RTL/FanInPrimitive_Req_FPU.sv(1): Vopt Compiler exiting
End time: 10:05:49 on Jul 10,2023, Elapsed time: 0:00:02
Errors: 1, Warnings: 1
make: *** [build] Error 232