diff --git a/.coveragerc b/.coveragerc index 655e30949..a1eebd0a4 100644 --- a/.coveragerc +++ b/.coveragerc @@ -10,3 +10,12 @@ equiv_source = [report] skip_empty = true precision = 1 +exclude_lines = + pragma: no cover + def __repr__ + def [a-z_]*dump + assert False + raise AssertionError + raise NotImplementedError + if __name__ == .__main__.: + if TYPE_CHECKING: diff --git a/.github/workflows/basic_test.yaml b/.github/workflows/basic_test.yaml index 45b72fc81..5419e9f91 100644 --- a/.github/workflows/basic_test.yaml +++ b/.github/workflows/basic_test.yaml @@ -44,8 +44,8 @@ jobs: with: python-version: ${{ matrix.python-version }} - # This requires pip 20.1+. The current ubuntu-latest as of 28 Feb 2021 has pip 21.0.1 by default - # for all Python versions 3.6-3.9. + # This requires pip 20.1+. As of 28 Feb 2021 this condition is met for all supported + # Python versions on all OSes. - name: Get pip cache dir id: pip-cache run: | diff --git a/README.md b/README.md index 97b452276..126fc9f80 100644 --- a/README.md +++ b/README.md @@ -76,6 +76,7 @@ Requirements - Keil ULINKplus - NXP LPC-LinkII - NXP MCU-Link + - WCH-Link (1a86:8011, 2a86:8011 and others) - [PE Micro](https://pemicro.com/) Cyclone and Multilink - Raspberry Pi Picoprobe - SEGGER J-Link diff --git a/docs/builtin-targets.md b/docs/builtin-targets.md index f0f15edcf..3e7515034 100644 --- a/docs/builtin-targets.md +++ b/docs/builtin-targets.md @@ -461,6 +461,11 @@ title: Built-in targets LPC5526 + lpc55s16 + NXP + LPC55S16 + + lpc55s28 NXP LPC55S28 @@ -761,6 +766,26 @@ title: Built-in targets W7500 + ytm32b1ld0 + Yuntu Microelectronics + YTM32B1LD0 + + + ytm32b1le0 + Yuntu Microelectronics + YTM32B1LE0 + + + ytm32b1md1 + Yuntu Microelectronics + YTM32B1MD1 + + + ytm32b1me0 + YTMicro + YTM32B1ME0 + + diff --git a/docs/command_reference.md b/docs/command_reference.md index a35353eed..fea90fc10 100644 --- a/docs/command_reference.md +++ b/docs/command_reference.md @@ -15,7 +15,10 @@ that ambiguous because it matches multiple commands, an error will be reported s command names. In addition, commonly used commands often have a short alias. The alias takes precedence even when it is a prefix of multiple other commands. - + All commands ------------ @@ -128,9 +131,9 @@ Resume execution of the target. core -[NUM] +[NUMBER | NAME] -Select CPU core by number or print selected core. +Select CPU core by number or name, or print selected core. @@ -195,7 +198,7 @@ Write DP register. [halt|-halt|-h] [TYPE] -Reset the target, optionally specifying the reset type. +Reset the target, optionally with halt and/or specifying the reset type. @@ -403,6 +406,16 @@ Print core or peripheral register(s). Set the value of a core or peripheral register. +Rtt + + +rtt + +rtt {setup,start,stop,channels,server} + +Control SEGGER RTT compatible interface. + + Semihosting @@ -469,6 +482,16 @@ Show the target's current state. Control thread awareness. +Utility + + +sleep + +MILLISECONDS + +Sleep for a number of milliseconds before continuing. + + Values @@ -502,6 +525,14 @@ command can be read, written, or both. ValueAccessDescription + +accessible-pins + +read-write + +Display which debug probe pins can be read and written with the 'pins' value. + + aps @@ -518,6 +549,14 @@ read-only Information about CPU cores in the target. + +debug-sequences + +read-only + +Show the available debug sequences from the target's DFP. + + fault @@ -615,6 +654,14 @@ read-only List of target peripheral instances. + +pins + +read-write + +Current debug probe protocol I/O pin states. + + probe-uid, uid @@ -632,6 +679,14 @@ read-only Display available register groups for the selected core. + +reset-type + +read-write + +Show reset configuration and all available reset types for each core. Set current reset type. + + step-into-interrupts, si @@ -750,8 +805,8 @@ Resume execution of the target. The target's state is read back after resuming. ##### `core` -**Usage**: core [NUM] \ -Select CPU core by number or print selected core. +**Usage**: core [NUMBER | NAME] \ +Select CPU core by number or name, or print selected core. ##### `halt` @@ -803,7 +858,7 @@ Write DP register. ##### `reset` **Usage**: reset [halt|-halt|-h] [TYPE] \ -Reset the target, optionally specifying the reset type. The reset type must be one of 'default', 'hw', 'sw', 'hardware', 'software', 'sw_sysresetreq', 'sw_vectreset', 'sw_emulated', 'sysresetreq', 'vectreset', or 'emulated'. +Reset the target, optionally with halt and/or specifying the reset type. The reset type must be one of 'default', 'hw', 'sw', 'hardware', 'software', 'system', 'core', 'emulated', 'sw_system', 'sw_core', 'sw_sysresetreq', 'sw_vectreset', 'sw_emulated', 'sysresetreq', or 'vectreset'. ##### `unlock` @@ -969,6 +1024,14 @@ Print core or peripheral register(s). If no arguments are provided, the 'general Set the value of a core or peripheral register. The REG parameter must be a core register name or a peripheral.register. When a peripheral register is written, if the -r option is passed then it is read back and the updated value printed. The -p option forces evaluating the register name as a peripheral register name. If the -f option is passed, then individual fields of peripheral registers will be printed in addition to the full value. +### Rtt + +##### `rtt` + +**Usage**: rtt rtt {setup,start,stop,channels,server} \ +Control SEGGER RTT compatible interface. + + ### Semihosting ##### `arm` @@ -1023,6 +1086,14 @@ Show the target's current state. Control thread awareness. +### Utility + +##### `sleep` + +**Usage**: sleep MILLISECONDS \ +Sleep for a number of milliseconds before continuing. + + ### Values ##### `set` @@ -1041,6 +1112,12 @@ Display a value. Value details ------------- +##### `accessible-pins` + +**Access**: read-write \ +**Usage**: show accessible-pins, set accessible-pins VALUE \ +Display which debug probe pins can be read and written with the 'pins' value. + ##### `aps` **Access**: read-only \ @@ -1053,6 +1130,12 @@ List discovered Access Ports. **Usage**: show cores \ Information about CPU cores in the target. +##### `debug-sequences` + +**Access**: read-only \ +**Usage**: show debug-sequences \ +Show the available debug sequences from the target's DFP. Only available for CMSIS-Pack based targets. + ##### `fault` **Access**: read-only \ @@ -1130,6 +1213,12 @@ The current value of one or more session options. When setting, each argument sh **Usage**: show peripherals \ List of target peripheral instances. +##### `pins` + +**Access**: read-write \ +**Usage**: show pins, set pins VALUE \ +Current debug probe protocol I/O pin states. The pins value is a mask containing the state of all accessible protocol pins. See the `accessible-pins` value for protocol pins that can be read and written by the connected debug probe. + ##### `probe-uid` **Aliases**: `uid` \ @@ -1143,6 +1232,12 @@ Target's unique ID. **Usage**: show register-groups \ Display available register groups for the selected core. +##### `reset-type` + +**Access**: read-write \ +**Usage**: show reset-type, set reset-type VALUE \ +Show reset configuration and all available reset types for each core. Set current reset type. + ##### `step-into-interrupts` **Aliases**: `si` \ diff --git a/docs/configuring_logging.md b/docs/configuring_logging.md index 5ab164f63..00f352379 100644 --- a/docs/configuring_logging.md +++ b/docs/configuring_logging.md @@ -83,6 +83,8 @@ Trace logger | Trace output `pyocd.coresight.ap.trace` | AP memory transfers `pyocd.coresight.dap.trace` | AP and DP register accesses `pyocd.debug.semihost.trace` | Semihost file operations +`pyocd.debug.sequences.scope.trace` | Open-CMSIS-Pack debug sequence variable read/write +`pyocd.debug.sequences.sequences.trace` | Open-CMSIS-Pack debug sequence statements `pyocd.flash.flash.trace` | Flash algorithm operations `pyocd.probe.cmsis_dap_probe.trace` | CMSIS-DAP probe API calls `pyocd.probe.jlink_probe.trace` | Log output from JLink library diff --git a/docs/multicore_debug.md b/docs/multicore_debug.md index 20cbb43ce..b7a231811 100644 --- a/docs/multicore_debug.md +++ b/docs/multicore_debug.md @@ -3,29 +3,27 @@ title: Multicore debug --- pyOCD supports debugging multicore devices. It does this by serving one gdb server per core, to which -you connect independant gdb instances. This is the most reliable method of debugging multicore -embedded devices using gdb. +independent gdb instances are connected. This is the most reliable method of debugging asymmetric multicore +devices using gdb. -`pyocd gdbserver` automatically creates one `GDBServer` instance per core. The first core is given the -user-specified port number. Additional cores have port numbers incremented from there. +`pyocd gdbserver` automatically creates one gdb server instance per core by default. The primary core is given the user-specified port number. Additional cores have port numbers incremented from there. If a gdb server for only one or a subset of cores is desired, the `--core` command line argument can be used with a list of core numbers. -To prevent reset requests from multiple connected gdb instances causing havoc, secondary cores have -their default reset type set to core-only reset (VECTRESET), which will fall back to an emulated -reset for non-v7-M architectures. This feature can be disabled by setting the -`enable_multicore_debug` session option to false. +By default, the primary core is core number 0. For Arm CoreSight based devices, this will be the core with the lowest associated access port address. Use the `primary_core` session option to change the primary core. + +When performing multicore debug where multiple gdb instances are connected simultaneously, it is important to set the `enable_multicore_debug` session option to true. This changes secondary cores to have their default reset type set to core-only reset (`sw_core`). This prevents competing reset requests from the multiple gdb instances causing havoc. On v7-M architecture cores, VECTRESET is used. However, VECTRESET is not supported on other core architecture, so non-v7-M architectures will fall back to an emulated core reset. To debug a multicore device, run `pyocd gdbserver` as usual. This will connect to the device, detect the cores, and create the gdb server instances on separate ports. Next, start up two gdb instances and connect to the two gdb server ports. For instance, on a dual core device if you pass 3333 for -the port, connect to port 3333 for the first core and port 3334 for the second core. +the port (or leave it set to default), connect to port 3333 for the first core and port 3334 for the second core. On many devices, secondary cores are by default held in reset until released by the primary core. Because gdb does not have a concept of a core held in reset, pyOCD will report a core held in reset -by telling gdb that there is a single thread with the name "Reset". This is visible if you run the -show threads gdb command, and will appear in the Eclipe Debug view's list of threads. All register +by telling gdb that there is a single thread with the name “Reset”. This is visible if you run the +show threads gdb command, and will appear in the VSCode or Eclipse Debug view's list of threads. All register values will be reported as 0 until the core is released from reset. -Usually you want to have the primary core load code for the secondary core, so configure the second -core's gdb to not load any code to the target. This is highly device-specific, though, and may +Usually you want to have the primary core load code and/or configure the reset vector for secondary cores prior to releasing those cores from reset. For this situation, configure the second +core's gdb to not load any code to the target. This usage is highly device-specific, though, and may depend on whether the secondary core's code is running out of flash or RAM. diff --git a/docs/open_cmsis_pack_support.md b/docs/open_cmsis_pack_support.md new file mode 100644 index 000000000..202917c06 --- /dev/null +++ b/docs/open_cmsis_pack_support.md @@ -0,0 +1,163 @@ +--- +title: Open-CMSIS-Pack support +--- + +PyOCD uses device descriptions from [Open-CMSIS-Pack](https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/index.html) Device Family Packs (DFPs) as a primary method for supporting target types. See the [target support documentation]({% link _docs/target_support.md %}) for how to install and select target types from DFPs. + +There are three main components to DFP device descriptions used by pyOCD: + +- Memory regions +- Debug description +- Debug access sequences + + +## Memory regions + +A Device Family Pack lists memory regions and contains the algorithms used to program flash memories. + +### Flash algorithms + +DFPs can specify whether a flash algorithm is default, that is, whether it should be used without user intervention. Some DFPs use the default flag to include more than one flash algorithm for a given memory region, usually multiple part numbers for external memories such as Quad or Octal SPI flash. PyOCD honours this flag, and only loads flash algorithms marked as default. It currently does not have a standard way to list and enable non-default flash algorithms. If required, a [user script]({% link _docs/user_scripts.md %}) can be used to add additional flash algorithms manually extracted from the DFP. + +### Limitations + +- DFPs can specify a memory region or flash algorithm to apply only to a specific CPU. However, pyOCD currently only supports a single system memory map for all CPUs. This can result in issues if conflicting or overlapping memory regions are defined for more than one CPU. +- PyOCD always runs flash algorithms from the first CPU, even if the DFP says the algorithm should apply to another CPU. On certain devices, this can result in the algorithm failing to run correctly. +- Flash algorithms are handled as a separate list in CMSIS-Packs, while in pyOCD the flash algorithms are associated with flash memory regions. If a DFP defines multiple algorithms with address ranges corresponding to a single region, only the first listed algorithm will be used. (At the time of this writing, there are no known DFPs with such a configuration.) + + +## Debug description + +A Device Family Pack contains a [description](https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/debug_description.html) of the device's debug architecture. In pyOCD, this is used primarily to support debug access sequences. For its own use, pyOCD automatically discovers the device's debug architecture via the Arm CoreSight discovery process (e.g., reading ROM tables) since this is usually more reliable and also works for devices without debug descriptions. + +### Reset types + +The debug description can set a target's default reset type and disable certain reset types. + + +## Debug access sequences + +Debug access sequences, simply called "debug sequences" below, contain a set of instructions to tell the debugger how to perform different debug related activities such as connect, reset, configuring the device for trace, and so on. Silicon vendors can provide debug sequences for cases where their device has special control requirements or nonstandard behaviours. Many devices do not need debug sequences, and they are entirely optional. + +A set of standard debug sequences is defined by the [Open-CMSIS-Pack](https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec) specification to be executed by the debugger when performing certain activities. Some of these standard sequences have pre-defined behaviour performed by the debugger if the DFP does not override that sequence. Others sequences exist only to allow the DFP to insert custom actions. + +In addition to the standard debug sequences, a DFP can define its own custom sequences. These can be called like subroutines by other sequences. + +Any debug sequence can be customised per CPU core. + + +### Debug variables + +Debug sequences frequently make use of configurable variables called debug variables, or debugvars for short. Depending on the debug sequence, these variables can be modified to change the values written into registers, adjust timeouts, or for other, similar purposes. In other debuggers such as Keil MDK, debugvars are read from a `.dbgconf` file. In pyOCD, this is handled through the `pack.debug_sequences.debugvars` session option described below. + +The `pack.debug_sequences.debugvars` session option must be set to a string containing C-style variable assignment statements. C-compatible integer expressions are allowed, and can refer to previously defined variables. Only those debug variables whose value is being changed need to be assigned a value; others will retain their default value. This option is one that you'd normally set in a yaml config file rather than the command line. + +All debugvars defined by the CMSIS-Pack and their configured value are logged (at the Info log level) during target connection. + +This is an example of output for an ST Microelectronics STM32H750 MCU (target type name `stm32h750ibtx`) from the Keil.STM32H7_DFP pack: + +``` +0001360 I debugvar 'DbgMCU_APB1L_Fz1' = 0xffffffff (4294967295) [pack_target] +0001360 I debugvar 'DbgMCU_APB2_Fz1' = 0xffffffff (4294967295) [pack_target] +0001360 I debugvar 'DbgMCU_APB3_Fz1' = 0xffffffff (4294967295) [pack_target] +0001360 I debugvar 'DbgMCU_APB4_Fz1' = 0xffffffff (4294967295) [pack_target] +0001361 I debugvar 'DbgMCU_CR' = 0x7 (7) [pack_target] +0001361 I debugvar 'TraceClk_Pin' = 0x40002 (262146) [pack_target] +0001361 I debugvar 'TraceD0_Pin' = 0x40003 (262147) [pack_target] +0001361 I debugvar 'TraceD1_Pin' = 0x40004 (262148) [pack_target] +0001361 I debugvar 'TraceD2_Pin' = 0x40005 (262149) [pack_target] +0001361 I debugvar 'TraceD3_Pin' = 0x40006 (262150) [pack_target] +``` + +To override some `DBGMCU` register values configured by the above target, this could be added to the `pyocd.yaml` [configuration file]({% link _docs/configuration.md %}): + +```yaml +pack.debug_sequences.debugvars: | + DbgMCU_APB1L_Fz1 = 0xffffffff; + DbgMCU_APB2_Fz1 = 0xffffffff; + DbgMCU_APB3_Fz1 = 0xffffffff; + DbgMCU_APB4_Fz1 = 0xffffffff; +``` + +If the `pack.debug_sequences.debugvars` session option is modified during a connection, the new debugvar values will be used for any further debug sequence invocations. However, changes to a configuration file on disk will not be reloaded at runtime. + + +### Disabling debug sequences + +Like any software, DFPs and any contained debug sequences can have bugs. There may also be other cases where disabling a debug sequence is useful. PyOCD can be configured to disable debug sequences either as a whole or individually by using the following session options. + +#### `pack.debug_sequences.enable` + +This boolean session option globally controls debug sequence support. It defaults to True; setting to False will disable running of all debug sequences defined by the DFP for the chosen target. + +#### `pack.debug_sequences.disabled_sequences` + +If specific debug sequences need to be disabled, they can be specified with this option. From the command line, the value must be a comma-separated list of sequence names. When set in a YAML config file, the value must be a YAML list of sequence names (instead of a single comma-separated string value). + +Disabled sequences can be restricted to a given core by appending a colon and processor name to the sequence's name (e.g., "ResetProcessor:cm4"). + +Only top-level sequences can be disabled individually. If a debug sequence is called from another sequence it will always be executed even if listed in this option. + + + +## PyOCD's debug sequence implementation + +This section documents details of the debug sequence engine provided by pyOCD, supported features, and any notable differences with other debuggers (primarily Keil MDK, which provided the first implementation and against which Packs are generally most thoroughly tested by their authors). + + +### CPU-specific DebugPort sequences + +Like all other debug sequences, `DebugPortSetup`, `DebugPortStart`, and `DebugPortStop` can be customised per CPU core. If a DFP has multiple CPU-specific instances of these sequences, they may behave differently in pyOCD than other debuggers. Many debuggers only "connect" to a single CPU chosen by the user when debugging or running a project. PyOCD is somewhat different in that it connects to the device as a whole, and then debugs a chosen core after the connection is established (which more closely reflects the hardware situation). + + +### Custom default reset sequences + +The DFP specification allows the definition of custom (nonstandard) reset sequences, and these can be selected as the default reset sequence for a core. The purpose of this is to keep the standard sequences unmodified and available for user selection. Because pyOCD does not currently support a custom reset type, this DFP feature is not supported. A custom default reset sequence will be replaced with `ResetSystem` and the custom behaviour not performed. + + +### Debug sequences and delegate functions + +Effectively, debug sequences are handled as pre-defined [delegate functions]({% link _docs/user_scripts.md %}#delegate-functions). For most standard debug sequence, there is a corresponding delegate function. This means that a delegate function in a user script (or delegate class, if using the Python API) will override the corresponding debug sequence provided by the target's DFP. + + +### Supported debug sequences + +The following standard debug sequences are supported and will by called by pyOCD. The corresponding delegate function is listed for each. + +Sequence name | Delegate function | Description +----------------------|---------------------|------------------------------------------------------ +`DebugPortSetup` | - | SWJ-DP switch; reading `DPIDR`; writing `TARGETSEL`. +`DebugPortStart` | - | Connect to the target debug port and power it up. +`DebugPortStop` | - | Power down and disconnect from target debug port. +`DebugDeviceUnlock` | `unlock_device` | Ensure the device is accessible. +`DebugCoreStart` | `start_debug_core` | Initialize core debug. +`DebugCoreStop` | `stop_debug_core` | Uninitialized core debug. +`ResetSystem` | `will_reset` | System-wide reset without debug domain via software mechanisms. +`ResetProcessor` | `will_reset` | Local processor reset without peripherals and debug domains. +`ResetHardware` | `will_reset` | System-wide reset without debug domain via the dedicated debugger reset line, e.g. nRST. +`ResetCatchSet` | `set_reset_catch` | Configure the vector catch to stop code execution after the reset. +`ResetCatchClear` | `clear_reset_catch` | Free hardware resources allocated by `ResetCatchSet`. +`TraceStart` | `trace_start` | Enable target trace capture. +`TraceStop` | `trace_stop` | Disable target trace capture. + +Standard debug sequences not currently supported: + +Sequence name | Description +----------------------|------------------------------------------------------ +`DebugCodeMemRemap` | Remap memory to execution location. +`ResetHardwareAssert` | Assert a system-wide reset via the dedicated debugger reset line, e.g. nRST. +`ResetHardwareDeassert` | De-assert a system-wide reset via the dedicated debugger reset line, e.g. nRST. +`FlashInit` | Flash programming +`FlashUninit` | Flash programming +`FlashEraseSector` | Flash programming +`FlashEraseChip` | Flash programming +`FlashEraseDone` | Flash programming +`FlashProgramPage` | Flash programming +`FlashProgramDone` | Flash programming +`RecoverySupportStart` | Before step or run command to support recovery from a lost target connection. +`RecoverySupportStop` | After step or run command in context of the `RecoverySupportStart`. +`RecoveryAcknowledge` | Debugger acknowledge after recovering from a lost target connection. + + + + diff --git a/docs/options.md b/docs/options.md index b31c187f8..5bbf79aa6 100644 --- a/docs/options.md +++ b/docs/options.md @@ -2,7 +2,7 @@ title: Session options list --- -_**Note:** The names of these options are expected to change before the 1.0 release of pyOCD, so +_**Note:** The names of these options are expected to change with the 1.0 release of pyOCD, so they will be better normalized and grouped._ ## General options @@ -27,7 +27,7 @@ takes precedence over this option if set. bool False -Prevents raising an error if no core were found after CoreSight discovery. +Prevents raising an error if no cores were found after CoreSight discovery. auto_unlock @@ -38,6 +38,22 @@ If the target is locked, it will by default be automatically mass erased in orde access. Set this option to False to disable auto unlock. +cache.enable_memory +bool +True + +Enable the memory read cache. Affects memory accesses made through the target debug context, including the +gdbserver. + + +cache.enable_register +bool +True + +Enable the core register cache. Affects core register accesses made through the target debug context, +including the gdbserver. + + cache.read_code_from_elf bool True @@ -136,9 +152,11 @@ Log details of loaded .FLM flash algos. debug.traceback bool -True +False -Print tracebacks for exceptions. +Print tracebacks for exceptions, including errors that are only logged as well as critical errors that cause pyocd to terminate. + +Disabled by default, unless the log level is raised to Debug. enable_multicore_debug @@ -146,8 +164,9 @@ Print tracebacks for exceptions. False Whether to put pyOCD into multicore debug mode. The primary effect is to modify the default software -reset type for secondary cores to use VECTRESET, which will fall back to emulated reset if the -secondary core is not v7-M. +reset type for secondary cores to use VECTRESET, which will fall back to emulated reset for +secondary cores that are not v7-M architecture (VECTRESET is only supported on v7-M). The core that is +considered the primary core is selected by the `primary_core` option. fast_program @@ -239,6 +258,47 @@ Path or list of paths to CMSIS Device Family Packs. Devices defined in the pack( list of available targets. +pack.debug_sequences.debugvars +str +No default + +Variable definition statements to change configurable variables defined by and used in the target's debug sequences. +Should be set to a string containing C-style variable assignment statements. C-compatible integer expressions +are allowed, and can refer to previously defined variables. Only those debug variables whose value is being +changed need to be assigned a value; others will retain their default value. + + +pack.debug_sequences.disabled_sequences +str, list of str +No default + +Comma-separated list of names of debug sequences to disable for a CMSIS-Pack based target. +Disabled sequences can be restricted to a given core by appending a colon and processor +name to the sequence's name. If set in a YAML config file, the value must be a list of sequence +names instead of using a single comma-separated value. + +Only top-level sequences can be disabled. If a sequence is called from another sequence it will +always be executed even if listed in this option. + +Ignored for builtin targets. + + +pack.debug_sequences.enable +bool +True + +Global enable for debug sequences for CMSIS-Pack based targets. Ignored for builtin targets. + + +primary_core +int +0 + +Core number for the primary/boot core of an asymmetric multicore target. Becomes the default selected +core in the commander and the `SoCTarget` class. Also the core that will control system reset when +`enable_multicore_debug` is set. + + probeserver.port int 5555 @@ -258,8 +318,11 @@ executed. str 'sw' -Which type of reset to use by default (one of 'default', 'hw', 'sw', 'sw_sysresetreq', -'sw_vectreset', 'sw_emulated'). +Which type of reset to use by default. Must be one of `default`, `hw`, `sw`, `sw_system`, `sw_core`, +`sw_sysresetreq`, `sw_vectreset`, `sw_emulated`, `system`, `core`, `sysresetreq`, `vectreset`, +`emulated`). The default is `sw`, which itself defaults to `sw_system`. `default` causes the target type's +default reset type to be used; this is usually `sw`. If `enable_multicore_debug` is +set to true, then `sw` for secondary cores will default to `sw_core`. reset.hold_time @@ -304,7 +367,11 @@ Timeout in seconds for waiting for the core to halt after a reset and halt. bool True -Whether to resume a halted target when disconnecting. +Whether to disable debug control and resume the target when disconnecting. + +When True, then upon disconnect all CPUs are resumed, and DWT and other trace related blocks are disabled (`DEMCR` system register is cleared). +If False, the target CPU states are left unchanged and any enabled debug hardware (DWT, ITM) remains enabled. +In all cases, breakpoints and watchpoints are removed prior to disconnect. scan_all_aps @@ -450,6 +517,13 @@ Whether to use GDB syscalls for semihosting file access operations, or to have p operations. This is most useful if GDB is running on a remote system. +semihost.commandline +str +Empty + +Program command line string, used for the SYS_GET_CMDLINE semihosting request. + + step_into_interrupt bool False diff --git a/docs/semihosting.md b/docs/semihosting.md index 7e6db0613..a5735c034 100644 --- a/docs/semihosting.md +++ b/docs/semihosting.md @@ -123,6 +123,7 @@ These are the session options that control semihosting: - `enable_semihosting` - Set to true to handle semihosting requests. - `semihost_console_type` - If set to 'telnet' then the semihosting telnet server will be started. If set to 'console' then semihosting will print to pyOCD's console. +- `semihost.commandline` - Command line string return to the target for the `SYS_GET_CMDLINE` request. - `semihost_use_syscalls` - Whether to use GDB syscalls for semihosting file access operations, or to have pyOCD perform the operations.) - `telnet_port` - Base TCP port number for the semihosting telnet server. The core number, which will be 0 for the primary core, is added to this value. @@ -135,6 +136,10 @@ The majority of standard Arm-defined semihosting requests are supported by pyOCD - The special file name `:tt` is used to open standard I/O files, per the Arm semihosting specification. The open mode selects which standard I/O file is opened. "r" (0) is stdin, "w" (4) is stdout, "a" (8) is stderr. With pyOCD's implementation, explicitly opening the standard I/O files is not required. + - The special file name `:semihosting-features` will open the semihosting feature bits file. Supported + feature bits are: + - `SH_EXT_EXIT_EXTENDED` (byte 0 bit 0): =0, meaning `SYS_EXIT_EXTENDED` is not supported + - `SH_EXT_STDOUT_STDERR` (byte 0 bit 1): =1, meaning both stdout and stderr are supported - Standard I/O files opened via this request are only accessible when not routing console to the telnet server. - `SYS_CLOSE` (0x02): syscall - `SYS_WRITEC` (0x03): console @@ -151,6 +156,9 @@ The majority of standard Arm-defined semihosting requests are supported by pyOCD object was created, so this will not line up with timestamps in pyOCD's log output) - `SYS_TIME` (0x11): returns the number of seconds since midnight, January 1, 1970 - `SYS_ERRNO` (0x13): syscall +- `SYS_GET_CMDLINE` (0x15): returns the value of the `semihost.commandline` session option. If that option + is not set, the request fails (returns -1). +- `SYS_HEAPINFO` (0x16): stubbed to return all 0 values The following semihosting requests are not supported. If invoked, the return code is -1 and pyOCD logs a @@ -159,10 +167,9 @@ warning message, such as "Semihost: unimplemented request pc=\ r0=\ r1=\ None **Result** \ Ignored. +### unlock_device + +Hook to perform any required unlock sequence. +``` +unlock_device(target: SoCTarget) -> None +``` + +**Parameters** \ +*target* - An `SoCTarget` object. \ +**Result** \ +Ignored. + +Called after the DP is initialised but prior to discovery. This hook delegate can be used to unlock debug +access to the target. It can also be used to perform other pre-discovery actions. + +Note that because this hoook is called prior to discovery, APs and cores are not yet created. This means +that any register accesses must be performed through the DP's methods. (However, it's possible to create +a temporary instance of 'AccessPort' or one of its subclasses, such as `MEM_AP`.) + ### will_start_debug_core Notification hook for before core debug is enabled. @@ -299,6 +320,10 @@ stop_debug_core(core: CoreTarget) -> Optional[bool] *True* Do not perform the normal procedure to disable core debug. \ *False/None* Continue with normal behaviour. +This delegate is only called if resuming the core on disconnect, e.g. the `resume_on_disconnect` session +option is True. Therefore, the delegate should ensure that the core has properly resumed execution if it +returns True. + ### did_stop_debug_core Post core disconnect notification hook for the core. diff --git a/pyocd/board/board.py b/pyocd/board/board.py index 3eea5c01e..9754f3b48 100644 --- a/pyocd/board/board.py +++ b/pyocd/board/board.py @@ -123,6 +123,9 @@ def __init__(self, else f"Generic {self.target_type} board" self._vendor = board_info.vendor if (board_info and board_info.vendor) else "" + # Standard graph node name. + self.node_name = 'board' + self.add_child(self.target) def init(self) -> None: diff --git a/pyocd/commands/commander.py b/pyocd/commands/commander.py index 3fb72f58a..1e8079615 100755 --- a/pyocd/commands/commander.py +++ b/pyocd/commands/commander.py @@ -214,10 +214,11 @@ def connect(self) -> bool: connect_mode=connect_mode, frequency=self.args.frequency, options=options, - option_defaults=dict( - auto_unlock=False, - resume_on_disconnect=False, - ) + option_defaults={ + 'auto_unlock': False, + 'resume_on_disconnect': False, + 'debug.traceback': logging.getLogger('pyocd').isEnabledFor(logging.DEBUG), + } ) if not self._post_connect(): @@ -250,14 +251,10 @@ def _post_connect(self) -> bool: self.session.open(init_board=not self.args.no_init) except exceptions.TransferFaultError as e: if not self.session.target.is_locked(): - self.context.writei("Transfer fault while initing board: %s", e) - if self.session.log_tracebacks: - self.context.write(traceback.format_exc()) + LOG.error("Transfer fault while initing board: %s", e, exc_info=self.session.log_tracebacks) return False except exceptions.Error as e: - self.context.writei("Exception while initing board: %s", e) - if self.session.log_tracebacks: - self.context.write(traceback.format_exc()) + LOG.error("Error while initing target: %s", e, exc_info=self.session.log_tracebacks) return False # Set elf file if provided. diff --git a/pyocd/commands/commands.py b/pyocd/commands/commands.py index 3de925489..a520df775 100755 --- a/pyocd/commands/commands.py +++ b/pyocd/commands/commands.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # Copyright (c) 2022 David Runge # Copyright (c) 2022 Toshiba Electronic Devices & Storage Corporation # SPDX-License-Identifier: Apache-2.0 @@ -17,12 +17,16 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging import os +import time from natsort import natsorted import textwrap from time import sleep from shutil import get_terminal_size +from typing import TYPE_CHECKING from .. import coresight from ..core.helpers import ConnectHelper @@ -49,6 +53,9 @@ ) from .base import CommandBase +if TYPE_CHECKING: + from ..core.core_target import CoreTarget + # Make disasm optional. try: import capstone @@ -109,7 +116,7 @@ def execute(self): for i, c in enumerate(self.context.target.cores): core = self.context.target.cores[c] state_desc = core.get_state().name.capitalize() - desc = "Core %d: %s" % (i, state_desc) + desc = f"Core {i} ({core.node_name}): {state_desc}" if len(core.supported_security_states) > 1: desc += " [%s]" % core.get_security_state().name.capitalize() self.context.write(desc) @@ -356,10 +363,10 @@ class ResetCommand(CommandBase): 'category': 'device', 'nargs': [0, 1, 2], 'usage': "[halt|-halt|-h] [TYPE]", - 'help': "Reset the target, optionally specifying the reset type.", + 'help': "Reset the target, optionally with halt and/or specifying the reset type.", 'extra_help': "The reset type must be one of 'default', 'hw', 'sw', 'hardware', 'software', " - "'sw_sysresetreq', 'sw_vectreset', 'sw_emulated', 'sysresetreq', 'vectreset', " - "or 'emulated'.", + "'system', 'core', 'emulated', 'sw_system', 'sw_core', 'sw_sysresetreq', " + "'sw_vectreset', 'sw_emulated', 'sysresetreq', or 'vectreset'.", } @@ -1197,8 +1204,8 @@ class SelectCoreCommand(CommandBase): 'group': 'standard', 'category': 'core', 'nargs': [0, 1], - 'usage': "[NUM]", - 'help': "Select CPU core by number or print selected core.", + 'usage': "[NUMBER | NAME]", + 'help': "Select CPU core by number or name, or print selected core.", } def parse(self, args): @@ -1207,16 +1214,36 @@ def parse(self, args): self.core_num = None else: self.show_core = False - self.core_num = int(args[0], base=0) + + # Attempt to parse the core ID as an int. + try: + self.core_num = int(args[0], base=0) + except ValueError: + # Try to look up the argument as a core name (case-insensitive). + core = self._find_core_by_name(args[0]) + self.core_num = core.core_number + + def _find_core_by_name(self, name: str) -> CoreTarget: + assert self.context.session.target + for core in self.context.session.target.cores.values(): + if core.node_name is None: + continue + if core.node_name.casefold() == name.casefold(): + return core + else: + raise exceptions.CommandError(f"no core matching name '{name}'") def execute(self): + assert self.context.selected_core + assert self.context.session.target if self.show_core: - self.context.writei("Core %d is selected", self.context.selected_core.core_number) + self.context.write(f"Core {self.context.selected_core.core_number} " + f"({self.context.selected_core.node_name}) is selected") return self.context.selected_core = self.context.session.target.cores[self.core_num] core_ap = self.context.selected_core.ap self.context.selected_ap_address = core_ap.address - self.context.writef("Selected core {} ({})", self.core_num, core_ap.short_description) + self.context.write(f"Selected core {self.core_num} ({self.context.selected_core.node_name}) ({core_ap.short_description})") class ReadDpCommand(CommandBase): INFO = { @@ -1361,6 +1388,7 @@ class ReinitCommand(CommandBase): def execute(self): self.context.target.init() + self.context.set_context_defaults() class WhereCommand(CommandBase): INFO = { @@ -1513,6 +1541,22 @@ def execute(self): else: self.context.write("probe server is not running") +class SleepCommand(CommandBase): + INFO = { + 'names': ['sleep'], + 'group': 'standard', + 'category': 'utility', + 'nargs': 1, + 'usage': "MILLISECONDS", + 'help': "Sleep for a number of milliseconds before continuing.", + } + + def parse(self, args): + self.delay_secs = self._convert_value(args[0]) / 1000.0 + + def execute(self): + time.sleep(self.delay_secs) + class ShowCommand(CommandBase): INFO = { 'names': ['show'], diff --git a/pyocd/commands/execution_context.py b/pyocd/commands/execution_context.py index 90a2a11f6..adc0695a1 100755 --- a/pyocd/commands/execution_context.py +++ b/pyocd/commands/execution_context.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,9 +15,12 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging import sys -from typing import (IO, Any, Callable, Dict, Iterator, List, NamedTuple, Optional, Sequence, TYPE_CHECKING) +from typing import (Any, Callable, cast, Dict, IO, Iterator, List, NamedTuple, Optional, Sequence, + TYPE_CHECKING) import six import pprint import subprocess @@ -30,6 +33,13 @@ if TYPE_CHECKING: from ..debug.svd.model import SVDPeripheral + from ..core.session import Session + from ..core.core_target import CoreTarget + from ..core.soc_target import SoCTarget + from ..board.board import Board + from ..coresight.ap import (APAddressBase, AccessPort) + from ..coresight.coresight_target import CoreSightTarget + from ..probe.debug_probe import DebugProbe LOG = logging.getLogger(__name__) @@ -127,6 +137,12 @@ class CommandExecutionContext: commands and command lines. """ + _session: Optional[Session] + _selected_core: Optional[CoreTarget] + _selected_ap_address: Optional[APAddressBase] + _peripherals: Dict[str, SVDPeripheral] + _python_namespace: Dict[str, Any] + def __init__(self, no_init: bool = False, output_stream: Optional[IO[str]] = None): """@brief Constructor. @param self This object. @@ -138,14 +154,14 @@ def __init__(self, no_init: bool = False, output_stream: Optional[IO[str]] = Non """ self._no_init = no_init self._output = output_stream or sys.stdout - self._python_namespace: Dict[str, Any] = {} + self._python_namespace = {} self._command_set = CommandSet() # State attributes. self._session = None self._selected_core = None self._selected_ap_address = None - self._peripherals: Dict[str, "SVDPeripheral"] = {} + self._peripherals = {} self._loaded_peripherals = False # Add in the standard commands. @@ -213,44 +229,60 @@ def attach_session(self, session): # Select the first core's MEM-AP by default. if not self._no_init: - try: - # Selected core defaults to the target's default selected core. - if self.selected_core is None: - self.selected_core = self.target.selected_core - - # Get the AP for the selected core. - if self.selected_core is not None: - self.selected_ap_address = self.selected_core.ap.address - except IndexError: - pass - - # Fall back to the first MEM-AP. - if self.selected_ap_address is None: - for ap_num in sorted(self.target.aps.keys()): - if isinstance(self.target.aps[ap_num], MEM_AP): - self.selected_ap_address = ap_num - break + self.set_context_defaults() + + # Allow the target to add its own commands. + self.target.add_target_command_groups(self.command_set) # Add user-defined commands once we know we have a session created. self.command_set.add_command_group('user') return True + def set_context_defaults(self) -> None: + """@brief Sets context attributes to their default values. + + Sets the selected core and selected MEM-AP to the default values. + """ + assert self.target + + try: + # Selected core defaults to the target's default selected core. + if (self.selected_core is None) and (self.target.selected_core): + self.selected_core = self.target.selected_core + + # Get the AP for the selected core. + if self.selected_core is not None: + self.selected_ap_address = self.selected_core.ap.address + except IndexError: + pass + + # Fall back to the first MEM-AP. + if self.selected_ap_address is None: + for ap_num in sorted(self.target.aps.keys()): + if isinstance(self.target.aps[ap_num], MEM_AP): + self.selected_ap_address = ap_num + break + @property - def session(self): + def session(self) -> Session: + assert self._session return self._session @property - def board(self): - return self._session and self._session.board + def board(self) -> Board: + assert self._session and self._session.board + return self._session.board @property - def target(self): - return self._session and self._session.target + def target(self) -> SoCTarget: + assert self._session and self._session.target + return self._session.target @property - def probe(self): - return self._session and self._session.probe + def probe(self) -> DebugProbe: + assert self._session and self._session.probe + return self._session.probe @property def elf(self): @@ -272,37 +304,41 @@ def peripherals(self): return self._peripherals @property - def output_stream(self): + def output_stream(self) -> IO[str]: return self._output @output_stream.setter - def output_stream(self, stream): + def output_stream(self, stream: IO[str]) -> None: self._output = stream @property - def selected_core(self): + def selected_core(self) -> Optional[CoreTarget]: """@brief The Target instance for the selected core.""" return self._selected_core @selected_core.setter - def selected_core(self, value): + def selected_core(self, value: CoreTarget) -> None: self._selected_core = value @property - def selected_ap_address(self): + def selected_ap_address(self) -> Optional[APAddressBase]: return self._selected_ap_address @selected_ap_address.setter - def selected_ap_address(self, value): + def selected_ap_address(self, value: APAddressBase) -> None: self._selected_ap_address = value @property - def selected_ap(self): + def selected_ap(self) -> Optional[AccessPort]: if self.selected_ap_address is None: return None else: + from ..coresight.coresight_target import CoreSightTarget assert self.target - return self.target.aps[self.selected_ap_address] + if isinstance(self.target, CoreSightTarget): + return cast(CoreSightTarget, self.target).aps[self.selected_ap_address] + else: + raise exceptions.CommandError("target is not CoreSight based") def process_command_line(self, line: str) -> None: """@brief Run a command line consisting of one or more semicolon-separated commands. diff --git a/pyocd/commands/values.py b/pyocd/commands/values.py index d4e31dc7c..8c555234e 100755 --- a/pyocd/commands/values.py +++ b/pyocd/commands/values.py @@ -15,21 +15,30 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging import prettytable +from typing import (cast, TYPE_CHECKING) from .. import coresight from ..core import exceptions from ..probe.debug_probe import DebugProbe from ..coresight.ap import MEM_AP from ..core.target import Target +from ..core.core_target import CoreTarget from ..utility.cmdline import ( convert_one_session_option, convert_frequency, convert_vector_catch, + convert_reset_type, ) from .base import ValueBase +if TYPE_CHECKING: + from ..core.memory_map import MemoryMap + from ..utility.graph import GraphNode + LOG = logging.getLogger(__name__) VC_NAMES_MAP = { @@ -76,8 +85,10 @@ class TargetValue(ValueBase): } def display(self, args): - self.context.writei("Target: %s", self.context.target.part_number) - self.context.writei("DAP IDCODE: 0x%08x", self.context.target.dp.dpidr.idr) + self.context.write(f"Target type: {self.context.session.options.get('target_override')}") + self.context.write(f"Vendor: {self.context.target.vendor}") + self.context.write(f"Part number: {self.context.target.part_number}") + self.context.write(f"DAP IDCODE: {self.context.target.dp.dpidr.idr:#010x}") class CoresValue(ValueBase): INFO = { @@ -92,12 +103,24 @@ def display(self, args): if self.context.target.is_locked(): self.context.write("Target is locked") else: - self.context.writei("Cores: %d", len(self.context.target.cores)) + pt = prettytable.PrettyTable(["Number", "Name", "Type"]) + pt.align = 'l' + pt.border = False + for i, core in self.context.target.cores.items(): - self.context.writei("Core %d type: %s%s", i, - core.name, - " (selected)" if ((self.context.selected_core is not None) \ - and (self.context.selected_core.core_number == i)) else "") + pt.add_row([ + ( + ("*" if ((self.context.selected_core is not None) + and (self.context.selected_core.core_number == i)) + else " ") + + str(i) + ), + cast(CoreTarget, core).node_name, + core.name, + ]) + + self.context.write(str(pt)) + self.context.write("(Currently selected core is marked with a '*'.)") class APsValue(ValueBase): INFO = { @@ -134,18 +157,25 @@ def display(self, args): pt = prettytable.PrettyTable(["Region", "Type", "Start", "End", "Size", "Access", "Sector", "Page"]) pt.align = 'l' pt.border = False - for region in self.context.selected_core.get_memory_map(): - pt.add_row([ - region.name, - region.type.name.capitalize(), - "0x%08x" % region.start, - "0x%08x" % region.end, - "0x%08x" % region.length, - region.access, - ("0x%08x" % region.sector_size) if region.is_flash else '-', - ("0x%08x" % region.page_size) if region.is_flash else '-', - ]) - self.context.write(pt) + + def add_rows(indent: int, pt: prettytable.PrettyTable, map: "MemoryMap") -> None: + for region in map: + pt.add_row([ + (' ' * indent) + region.name, + region.type.name.capitalize(), + "0x%08x" % region.start, + "0x%08x" % region.end, + "0x%08x" % region.length, + region.access, + ("0x%08x" % region.sector_size) if region.is_flash else '-', + ("0x%08x" % region.page_size) if region.is_flash else '-', + ]) + if region.has_subregions: + add_rows(indent + 2, pt, region.submap) + + add_rows(0, pt, self.context.selected_core.memory_map) + + self.context.write(str(pt)) class PeripheralsValue(ValueBase): INFO = { @@ -278,6 +308,83 @@ def modify(self, args): else: self.context.target.dp.assert_reset((state == 0)) +class AccessiblePinsValue(ValueBase): + INFO = { + 'names': ['accessible-pins'], + 'group': 'standard', + 'category': 'probe', + 'access': 'rw', + 'help': "Display which debug probe pins can be read and written with the 'pins' value.", + } + + def display(self, args): + if DebugProbe.Capability.PIN_ACCESS not in self.context.probe.capabilities: + raise exceptions.CommandError("debug probe does not support pin access") + + r_pins, w_pins = self.context.probe.get_accessible_pins() + + def pin_desc(mask: int) -> str: + desc = "" + if r_pins & mask: + desc += "r" + if w_pins & mask: + desc += "w" + if desc == "": + desc = "n/a" + return desc + + self.context.write(f"Protocol pins:") + self.context.write(f" SWCLK/TCK = {pin_desc(DebugProbe.ProtocolPin.SWCLK_TCK)}") + self.context.write(f" SWDIO/TMS = {pin_desc(DebugProbe.ProtocolPin.SWDIO_TMS)}") + self.context.write(f" TDI = {pin_desc(DebugProbe.ProtocolPin.TDI)}") + self.context.write(f" TDO = {pin_desc(DebugProbe.ProtocolPin.TDO)}") + self.context.write(f" nRESET = {pin_desc(DebugProbe.ProtocolPin.nRESET)}") + self.context.write(f" nTRST = {pin_desc(DebugProbe.ProtocolPin.nTRST)}") + +class PinsValue(ValueBase): + INFO = { + 'names': ['pins'], + 'group': 'standard', + 'category': 'probe', + 'access': 'rw', + 'help': "Current debug probe protocol I/O pin states.", + 'extra_help': + "The pins value is a mask containing the state of all accessible protocol pins. " + "See the `accessible-pins` value for protocol pins that can be read and written by " + "the connected debug probe.", + } + + def display(self, args): + if DebugProbe.Capability.PIN_ACCESS not in self.context.probe.capabilities: + raise exceptions.CommandError("debug probe does not support pin access") + self.print_current_pin_values() + + def print_current_pin_values(self): + pins = self.context.probe.read_pins(DebugProbe.PinGroup.PROTOCOL_PINS, + DebugProbe.ProtocolPin.ALL_PINS) + + def pin_desc(mask: int) -> str: + v = int(pins & mask != 0) + return f"{v} (mask {mask:#x})" + + self.context.write(f"Pins mask = {pins:#x}") + self.context.write(f"SWCLK/TCK = {pin_desc(DebugProbe.ProtocolPin.SWCLK_TCK)}") + self.context.write(f"SWDIO/TMS = {pin_desc(DebugProbe.ProtocolPin.SWDIO_TMS)}") + self.context.write(f"TDI = {pin_desc(DebugProbe.ProtocolPin.TDI)}") + self.context.write(f"TDO = {pin_desc(DebugProbe.ProtocolPin.TDO)}") + self.context.write(f"nRESET = {pin_desc(DebugProbe.ProtocolPin.nRESET)}") + self.context.write(f"nTRST = {pin_desc(DebugProbe.ProtocolPin.nTRST)}") + + def modify(self, args): + if DebugProbe.Capability.PIN_ACCESS not in self.context.probe.capabilities: + raise exceptions.CommandError("debug probe does not support pin access") + if len(args) != 1: + raise exceptions.CommandError("missing pins mask") + state = int(args[0], base=0) + self.context.probe.write_pins(DebugProbe.PinGroup.PROTOCOL_PINS, + DebugProbe.ProtocolPin.ALL_PINS, state) + self.print_current_pin_values() + class SessionOptionValue(ValueBase): INFO = { 'names': ['option'], @@ -437,7 +544,19 @@ class TargetGraphValue(ValueBase): } def display(self, args): - self.context.board.dump() + def _node_desc(node: GraphNode) -> str: + desc = node.__class__.__name__ + if node.node_name: + desc = f'"{node.node_name}": ' + desc + return desc + + def _dump(node: GraphNode, level: int) -> None: + desc = (" " * level) + "- " + _node_desc(node) + self.context.write(desc) + for child in node.children: + _dump(child, level + 1) + + _dump(self.context.board, 0) class LockedValue(ValueBase): INFO = { @@ -613,3 +732,99 @@ def modify(self, args): self.context.writei("Changed %s frequency to %s", swd_jtag, nice_freq) +class DebugSequencesValue(ValueBase): + INFO = { + 'names': ['debug-sequences'], + 'group': 'pack-target', + 'category': 'cmsis-pack', + 'access': 'r', + 'help': "Show the available debug sequences from the target's DFP.", + 'extra_help': "Only available for CMSIS-Pack based targets.", + } + + # Names of debug sequences that are both standard and supported by pyocd. + STANDARD_SEQUENCE_NAMES = [ + "DebugPortSetup", + "DebugPortStart", + "DebugPortStop", + "DebugDeviceUnlock", + "DebugCoreStart", + "DebugCoreStop", + "ResetSystem", + "ResetProcessor", + "ResetHardware", + "ResetCatchSet", + "ResetCatchClear", + "TraceStart", + "TraceStop", + ] + + def display(self, args): + assert self.context.target + + if self.context.target.debug_sequence_delegate is None: + self.context.write("Target does not use debug sequences") + return + + pt = prettytable.PrettyTable(["Name", "Processor", "Standard", "Enabled"]) + pt.align = 'l' + pt.border = False + + for seq in sorted(self.context.target.debug_sequence_delegate.all_sequences, + key=lambda i: (i.name, i.pname)): + is_standard = seq.name in self.STANDARD_SEQUENCE_NAMES + pt.add_row([ + seq.name, + seq.pname if seq.pname else "all", + str(is_standard), + seq.is_enabled, + ]) + + self.context.write(str(pt)) + +class ResetTypeValue(ValueBase): + INFO = { + 'names': ['reset-type'], + 'group': 'standard', + 'category': 'target', + 'access': 'rw', + 'help': "Show reset configuration and all available reset types for each core. Set current reset type.", + } + + def display(self, args): + from ..coresight.cortex_m import CortexM + + assert self.context.target + + current_reset_type_option = self.context.session.options.get('reset_type') + current_reset_type = convert_reset_type(current_reset_type_option) + reset_type_desc = current_reset_type_option + if current_reset_type is not None: + reset_type_desc += f" ({current_reset_type.name})" + self.context.write(f"Selected reset type ('reset_type' option): {reset_type_desc}") + + for core in self.context.target.cores.values(): + # Only handle Cortex-M cores for now. + if not isinstance(core, CortexM): + continue + cm_core = cast(CortexM, core) + + actual_reset_type = cm_core._get_actual_reset_type(None) + + self.context.write(f"\nCore {cm_core.core_number} ({cm_core.node_name}):") + self.context.write(f" Effective: {actual_reset_type.name}") + self.context.write(f" Default: {cm_core.default_reset_type.name}") + self.context.write(f" Default SW: {cm_core.default_software_reset_type.name}") + self.context.write(" Available: " + ", ".join(r.name for r in cm_core.supported_reset_types)) + + def modify(self, args): + from ..utility.cmdline import RESET_TYPE_MAP + if len(args) != 1: + raise exceptions.CommandError("invalid arguments") + + new_reset_type = args[0] + if new_reset_type.lower() not in RESET_TYPE_MAP: + raise exceptions.CommandError("invalid reset type") + + self.context.session.options['reset_type'] = new_reset_type + diff --git a/pyocd/core/core_target.py b/pyocd/core/core_target.py index 4a42dae6f..3b7a1946a 100644 --- a/pyocd/core/core_target.py +++ b/pyocd/core/core_target.py @@ -50,3 +50,6 @@ def clear_reset_catch(self, reset_type: Target.ResetType) -> None: def set_target_context(self, context: "DebugContext") -> None: raise NotImplementedError() + + def exception_number_to_name(self, exc_num: int) -> Optional[str]: + raise NotImplementedError() diff --git a/pyocd/core/exceptions.py b/pyocd/core/exceptions.py index ad9194674..971b80a69 100644 --- a/pyocd/core/exceptions.py +++ b/pyocd/core/exceptions.py @@ -158,3 +158,7 @@ class CommandError(Error): """@brief Raised when a command encounters an error.""" pass +class RTTError(Error): + """@brief Error encountered when transfering data through RTT.""" + pass + diff --git a/pyocd/core/memory_map.py b/pyocd/core/memory_map.py index 760d7c494..7bc4a2258 100644 --- a/pyocd/core/memory_map.py +++ b/pyocd/core/memory_map.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2019 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,7 +19,9 @@ import collections.abc import copy from functools import total_ordering -from typing import (Any, Dict, Iterable, Iterator, List, Optional, TYPE_CHECKING, Sequence, Tuple, Type, Union) +from typing import (Any, Callable, Dict, Iterable, Iterator, List, Optional, TYPE_CHECKING, + Sequence, Tuple, Type, Union) +from typing_extensions import Self from ..utility.strings import uniquify_name @@ -36,20 +38,21 @@ class MemoryType(Enum): DEVICE = 4 def check_range( - start: Union[int, "MemoryRangeBase"], + start: Union[int, "MemoryRangeBase", None] = None, end: Optional[int] = None, length: Optional[int] = None, range: Optional["MemoryRangeBase"] = None ) -> Tuple[int, int]: - assert (start is not None) and ((isinstance(start, MemoryRangeBase) or range is not None) or - ((end is not None) ^ (length is not None))) + assert ((range is not None) + or ((start is not None) and (isinstance(start, MemoryRangeBase) + or ((end is not None) ^ (length is not None))))) if isinstance(start, MemoryRangeBase): range = start if range is not None: actual_start = range.start actual_end = range.end else: - assert not isinstance(start, MemoryRangeBase) + assert isinstance(start, int) actual_start = start if end is None: assert length is not None @@ -85,12 +88,17 @@ def end(self) -> int: def length(self) -> int: return self._end - self._start + 1 + @property + def is_empty(self) -> bool: + """@brief Whether the range has a zero size.""" + return self.length == 0 + def contains_address(self, address: int) -> bool: return (address >= self.start) and (address <= self.end) def contains_range( self, - start: Union[int, "MemoryRangeBase"], + start: Union[int, "MemoryRangeBase", None] = None, end: Optional[int] = None, length: Optional[int] = None, range: Optional["MemoryRangeBase"] = None @@ -101,7 +109,7 @@ def contains_range( def contained_by_range( self, - start: Union[int, "MemoryRangeBase"], + start: Union[int, "MemoryRangeBase", None] = None, end: Optional[int] = None, length: Optional[int] = None, range: Optional["MemoryRangeBase"] = None @@ -112,7 +120,7 @@ def contained_by_range( def intersects_range( self, - start: Union[int, "MemoryRangeBase"], + start: Union[int, "MemoryRangeBase", None] = None, end: Optional[int] = None, length: Optional[int] = None, range: Optional["MemoryRangeBase"] = None @@ -122,6 +130,39 @@ def intersects_range( return (start <= self.start and end >= self.start) or (start <= self.end and end >= self.end) \ or (start >= self.start and end <= self.end) + def iter_split_by_address(self, addresses: Iterable[int]) -> Iterator["MemoryRange"]: + """@brief Yield ranges by splitting the object at the given addresses. + + The values in _addresses_ are points at which _self_'s bounds are split. Each value in _addresses_ + which is contained by _self_ becomes the start address of a yielded MemoryRange object, as well as + the end + 1 of the previous yielded range. + + If a value in _addresses_ is not contained by _self_, it is ignored. If _addresses_ is empty or + contains only out of bounds values, a MemoryRange with the same bounds as _self_ is yielded, unless + _self_ has zero length. + + @param self + @param addresses Iterable of int addresses by which _self_ is split. Can be in any order, can be, + empty and can contain values outside the bounds of _self_. + """ + prev = self.start + for a in sorted(a for a in addresses if self.contains_address(a)): + if a > prev: + yield MemoryRange(start=prev, end=(a - 1)) + prev = a + if prev <= self.end: + yield MemoryRange(start=prev, end=self.end) + + def iter_split_by_range(self, other: "MemoryRangeBase") -> Iterator["MemoryRange"]: + """@brief Yield a list of ranges before, containing, and after the provided range. + + Up to three MemoryRange objects are yielded. No yielded range will have bounds outside those of + self's. + - If _self_ and _other_ do not intersect, no ranges are yielded. + - If _other_ starts after _self_, a range + """ + yield from self.iter_split_by_address([other.start, other.end + 1]) + def __hash__(self) -> int: return hash("%08x%08x%08x" % (self.start, self.end, self.length)) @@ -181,6 +222,7 @@ class MemoryRegion(MemoryRangeBase): as memory-mapped OTP or configuration flash. - `is_testable`: Whether pyOCD should consider the region in its functional tests. - `is_external`: If true, the region is backed by an external memory device such as SDRAM or QSPI. + - `has_subregions`: True if the region has nested subregions, accessible through the `.map` property. Several attributes are available whose values are computed from other attributes. These should not be set when creating the region. @@ -193,6 +235,10 @@ class MemoryRegion(MemoryRangeBase): - `is_executable` - `is_secure` - `is_nonsecure` + + Memory regions can contain nested subregions. Any subregions must be fulled contained within the parent + region's address range. Subregions must also have the same memory type, except that a parent region + of type `MemoryType.OTHER` can contain any type of subregions. """ ## Default attribute values for all memory region types. @@ -207,10 +253,10 @@ class MemoryRegion(MemoryRangeBase): 'invalidate_cache_on_run': True, 'is_testable': True, 'is_external': False, - 'is_ram': lambda r: r.type == MemoryType.RAM, - 'is_rom': lambda r: r.type == MemoryType.ROM, - 'is_flash': lambda r: r.type == MemoryType.FLASH, - 'is_device': lambda r: r.type == MemoryType.DEVICE, + 'is_ram': lambda r: r.type is MemoryType.RAM, + 'is_rom': lambda r: r.type is MemoryType.ROM, + 'is_flash': lambda r: r.type is MemoryType.FLASH, + 'is_device': lambda r: r.type is MemoryType.DEVICE, 'is_readable': lambda r: 'r' in r.access, 'is_writable': lambda r: 'w' in r.access, 'is_executable': lambda r: 'x' in r.access, @@ -244,6 +290,11 @@ def __init__( self._map: Optional[MemoryMap] = None self._type = type self._attributes = attrs + self._submap = MemoryMap( + start=self.start, + end=self.end, + region_validator=lambda r: (r.type == self._type) or (self._type is MemoryType.OTHER), + ) # Assign default values to any attributes missing from kw args. for k, v in self.DEFAULT_ATTRS.items(): @@ -258,6 +309,15 @@ def map(self) -> Optional["MemoryMap"]: def map(self, the_map: Optional["MemoryMap"]) -> None: self._map = the_map + @property + def submap(self) -> "MemoryMap": + """@brief Memory map containing nested regions.""" + return self._submap + + @property + def has_subregions(self) -> bool: + return not self.submap.is_empty + @property def type(self) -> MemoryType: return self._type @@ -290,6 +350,25 @@ def __getattr__(self, name: str) -> Any: v = v(self) return v + def __setattr__(self, name: str, value: Any) -> None: + """@brief Set an instance attribute. + + Overridden to handle region attributes contained in the ._attributes dict. + """ + # Get our ._attributes dict instance attribute without going through our own __getattr__(). + # This can fail if called before ._attributes has been set the first time. + try: + attrs = super().__getattribute__('_attributes') + except AttributeError: + return super().__setattr__(name, value) + + # If the named attribute is contained in the ._attributes dict, set it there, otherwise + # pass on to the super implementation. + if name in attrs: + attrs[name] = value + else: + return super().__setattr__(name, value) + def _get_attributes_for_clone(self) -> Dict[str, Any]: """@brief Return a dict containing all the attributes of this region. @@ -298,7 +377,7 @@ def _get_attributes_for_clone(self) -> Dict[str, Any]: """ return dict(start=self.start, length=self.length, **self._attributes) - def clone_with_changes(self, **modified_attrs: Any) -> Any: # Have to return Any because Self isn't available yet. + def clone_with_changes(self, **modified_attrs: Any) -> Self: """@brief Create a duplicate this region with some of its attributes modified.""" new_attrs = self._get_attributes_for_clone() new_attrs.update(modified_attrs) @@ -370,7 +449,7 @@ class FlashRegion(MemoryRegion): - `erased_byte_value`: The value of an erased byte of this flash. Most flash technologies erase to all 1s, which would be an `erased_byte_value` of 0xff. - `algo`: The flash algorithm dictionary. - - `flm`: Path to an FLM flash algorithm. + - `flm`: Path to an FLM flash algorithm, either a str or Path, or a PackFlashAlgo instance. - `flash_class`: The class that manages individual flash algorithm operations. Must be either @ref pyocd.flash.flash.Flash "Flash", which is the default, or a subclass. - `flash`: After connection, this attribute holds the instance of `flash_class` for this region. @@ -540,7 +619,7 @@ def __init__( MemoryType.DEVICE: DeviceRegion, } -class MemoryMap(collections.abc.Sequence): +class MemoryMap(MemoryRangeBase, collections.abc.Sequence): """@brief Memory map consisting of memory regions. The normal way to create a memory map is to instantiate regions directly in the call to the @@ -567,8 +646,13 @@ class MemoryMap(collections.abc.Sequence): """ _regions: List[MemoryRegion] + _region_validator: Callable[[MemoryRegion], bool] - def __init__(self, *more_regions: Union[Sequence[MemoryRegion], MemoryRegion]) -> None: + def __init__( + self, + *more_regions: Union[Sequence[MemoryRegion], MemoryRegion], + **kwargs: Any, + ) -> None: """@brief Constructor. All parameters passed to the constructor are assumed to be MemoryRegion instances, and @@ -576,8 +660,23 @@ def __init__(self, *more_regions: Union[Sequence[MemoryRegion], MemoryRegion]) - @param self @param more_regions Zero or more MemoryRegion objects passed as separate parameters. + + Keyword arguments: + - `start` + - `end` + - `length` + - `region_validator`: Callable of the form `(MemoryRegion) -> bool`. Called with each region added to the map. If False is returned, a ValueError is raised rather than add the region. + + @exception ValueError The region validator returned false. """ + MemoryRangeBase.__init__( + self, + start=kwargs.get('start', 0), + end=kwargs.get('end', 0xffffffff), + length=kwargs.get('length') + ) self._regions = [] + self._region_validator = kwargs.get('region_validator', lambda r: True) self.add_regions(*more_regions) @property @@ -593,6 +692,11 @@ def region_count(self) -> int: """@brief Number of memory regions in the map.""" return len(self._regions) + @property + def is_empty(self) -> bool: + """@brief Whether the map has zero regions.""" + return len(self._regions) == 0 + def clone(self) -> "MemoryMap": """@brief Create a duplicate of the memory map. @@ -612,8 +716,10 @@ def add_regions(self, *more_regions: Union[Sequence[MemoryRegion], MemoryRegion] The region list is kept sorted. If no regions are provided, the call is a no-op. @param self - @param more_regions Either a single tuple or list, or one or more MemoryRegion objects - passed as separate parameters. + @param more_regions Either a single sequence of MemoryRegion objects, or one or more MemoryRegion + objects passed as separate parameters. + + @exception ValueError The region is out of bounds or the validator returned false. """ if len(more_regions): if isinstance(more_regions[0], collections.abc.Sequence): @@ -632,13 +738,22 @@ def add_region(self, new_region: MemoryRegion) -> None: @param self @param new_region An instance of MemoryRegion to add. A new instance that is a copy of this argument - may be added to the memory map in order to guarantee unique region names. + may be added to the memory map in order to guarantee unique region names (if the region has a + name). The region must fall completely within the map's address bounds. + + @exception ValueError The region is out of bounds or the validator returned false. """ # Check for an existing region with the same name. Multiple unnamed regions are allowed. existing_names = [r.name for r in self._regions if r] if new_region.name and (new_region.name in existing_names): new_region = new_region.clone_with_changes(name=uniquify_name(new_region.name, existing_names)) + # Validate the region. + if not self.contains_range(new_region): + raise ValueError(f"attempt add region {new_region} failed because it is out of bounds") + if not self._region_validator(new_region): + raise ValueError(f"attempt add region {new_region} failed because validator returned False") + new_region.map = self self._regions.append(new_region) self._regions.sort() diff --git a/pyocd/core/options.py b/pyocd/core/options.py index d9c639cb1..1e4b3b0f6 100644 --- a/pyocd/core/options.py +++ b/pyocd/core/options.py @@ -32,9 +32,13 @@ class OptionInfo(NamedTuple): "If this number of invalid APs is found in a row, then AP scanning will stop. The 'scan_all_aps' option " "takes precedence over this option if set."), OptionInfo('allow_no_cores', bool, False, - "Prevents raising an error if no core were found after CoreSight discovery."), + "Prevents raising an error if no cores were found after CoreSight discovery."), OptionInfo('auto_unlock', bool, True, "Whether to unlock secured target by erasing."), + OptionInfo('cache.enable_memory', bool, True, + "Enable the memory read cache. Default is enabled."), + OptionInfo('cache.enable_register', bool, True, + "Enable the core register cache. Default is enabled."), OptionInfo('cache.read_code_from_elf', bool, True, "Controls whether reads of code sections will be taken from an attached ELF file instead of the " "target memory."), @@ -60,10 +64,11 @@ class OptionInfo(NamedTuple): "When switching between SWD and JTAG, use the SWJ sequence from ADIv5.2 that utilizes a new dormant state."), OptionInfo('debug.log_flm_info', bool, False, "Log details of loaded .FLM flash algos."), - OptionInfo('debug.traceback', bool, True, + OptionInfo('debug.traceback', bool, False, "Print tracebacks for exceptions."), OptionInfo('enable_multicore_debug', bool, False, - "Whether to put pyOCD into multicore debug mode."), + "Whether to put pyOCD into multicore debug mode. Doing so changes the default software reset type of " + "secondary cores to VECTRESET, or emulated reset if that is not supported (i.e., non-v7-M cores)."), OptionInfo('fast_program', bool, False, "Setting this option to True will use CRC checks of existing flash sector contents to " "determine whether pages need to be programmed."), @@ -91,14 +96,27 @@ class OptionInfo(NamedTuple): OptionInfo('pack', (str, list), None, "Path or list of paths to CMSIS Device Family Packs. Devices defined in the pack(s) are " "added to the list of available targets."), + OptionInfo('pack.debug_sequences.debugvars', str, None, + "Variable definition statements to change configurable debug sequence variables."), + OptionInfo('pack.debug_sequences.disabled_sequences', (str, list), None, + "Comma-separated list of names of debug sequences to disable for a CMSIS-Pack based target. " + "Disabled sequences can be restricted to a given core by appending a colon and processor " + "name to the sequence's name. Only top-level debug sequences can be disabled. " + "Ignored for builtin targets."), + OptionInfo('pack.debug_sequences.enable', bool, True, + "Global enable for debug sequences for CMSIS-Pack based targets. Ignored for builtin targets."), + OptionInfo('primary_core', int, 0, + "Core number for the primary/boot core of an asymmetric multicore target. This is the core that " + "will control system reset when 'enable_multicore' is set."), OptionInfo('probeserver.port', int, 5555, "TCP port for the debug probe server."), OptionInfo('project_dir', str, None, "Path to the session's project directory. Defaults to the working directory when the pyocd " "tool was executed."), OptionInfo('reset_type', str, 'default', - "Which type of reset to use by default ('default', 'hw', 'sw', 'sw_sysresetreq', " - "'sw_vectreset', 'sw_emulated'). The default is 'sw'."), + "Which type of reset to use by default ('default', 'hw', 'sw', 'sw_system', 'sw_core', " + "'sw_sysresetreq', 'sw_vectreset', 'sw_emulated', 'system', 'core', 'sysresetreq', 'vectreset', " + "'emulated'). The default is 'sw', which itself defaults to 'sw_system'."), OptionInfo('reset.hold_time', float, 0.1, "Number of seconds to hold hardware reset asserted. Default is 0.1 s (100 ms)."), OptionInfo('reset.post_delay', float, 0.1, @@ -158,6 +176,8 @@ class OptionInfo(NamedTuple): "semihosting will print to the console."), OptionInfo('semihost_use_syscalls', bool, False, "Whether to use GDB syscalls for semihosting file access operations."), + OptionInfo('semihost.commandline', str, "", + "Program command line string, used for the SYS_GET_CMDLINE semihosting request."), OptionInfo('step_into_interrupt', bool, False, "Enable interrupts when performing step operations."), OptionInfo('swv_clock', int, 1000000, diff --git a/pyocd/core/plugin.py b/pyocd/core/plugin.py index d86ad1155..7408e4a65 100644 --- a/pyocd/core/plugin.py +++ b/pyocd/core/plugin.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,8 +15,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -import pkg_resources import logging +from importlib_metadata import entry_points from typing import ( Any, Dict, @@ -92,7 +92,7 @@ class must be derived from `base_class`. @param plugin_dict Dictionary to fill with loaded plugin classes. @param base_class The required superclass for plugin implementation classes. """ - for entry_point in pkg_resources.iter_entry_points(plugin_group): + for entry_point in entry_points(group=plugin_group): # Instantiate the plugin class. plugin = entry_point.load()() if not isinstance(plugin, Plugin): diff --git a/pyocd/core/session.py b/pyocd/core/session.py index 393f1a67b..4618be9b6 100644 --- a/pyocd/core/session.py +++ b/pyocd/core/session.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2018-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ from pathlib import Path import weakref from inspect import (getfullargspec, signature) +from types import SimpleNamespace from typing import (Any, Callable, Generator, Sequence, Union, cast, Dict, List, Mapping, Optional, TYPE_CHECKING) from . import exceptions @@ -160,6 +161,7 @@ def __init__( self._options = OptionsManager() self._gdbservers: Dict[int, "GDBServer"] = {} self._probeserver: Optional["DebugProbeServer"] = None + self._context_state = SimpleNamespace() # Set this session on the probe, if we were given a probe. if probe is not None: @@ -384,6 +386,15 @@ def log_tracebacks(self) -> bool: """@brief Quick access to debug.traceback option since it is widely used.""" return cast(bool, self.options.get('debug.traceback')) + @property + def context_state(self) -> SimpleNamespace: + """@brief Global session state namespace. + + The returned object is a namespace object on which arbitrary attributes can be read and written + to store context relevant state information between separate components. + """ + return self._context_state + def __enter__(self) -> "Session": assert self._probe is not None if self._auto_open: diff --git a/pyocd/core/soc_target.py b/pyocd/core/soc_target.py index b73682b3e..8aad90312 100644 --- a/pyocd/core/soc_target.py +++ b/pyocd/core/soc_target.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ from .core_target import CoreTarget from ..flash.eraser import FlashEraser from ..debug.cache import CachingDebugContext +from ..debug.context import DebugContext from ..debug.elf.elf import ELFBinaryFile from ..debug.elf.elf_reader import ElfReaderContext from ..utility.sequencer import CallSequence @@ -33,6 +34,7 @@ from .core_registers import (CoreRegistersIndex, CoreRegisterNameOrNumberType, CoreRegisterValueType) from ..debug.context import DebugContext from ..debug.breakpoints.provider import Breakpoint + from ..commands.execution_context import CommandSet LOG = logging.getLogger(__name__) @@ -67,6 +69,9 @@ def __init__(self, session: "Session", memory_map: Optional["MemoryMap"] = None) self._new_core_num = 0 self._elf = None + # Set our graph node name. + self.node_name = 'soc' + @property def cores(self) -> Dict[int, CoreTarget]: return self._cores @@ -98,6 +103,15 @@ def selected_core_or_raise(self) -> CoreTarget: raise KeyError("SoCTarget has no selected core") return self.cores[self._selected_core] + @property + def primary_core(self) -> CoreTarget: + """@brief Return the core for the `primary_core` session option. + + @exception KeyError The `primary_core` option is invalid. + """ + primary_core_number = self.session.options.get('primary_core') + return self.cores[primary_core_number] + @property def elf(self) -> Optional[ELFBinaryFile]: return self._elf @@ -124,13 +138,24 @@ def core_registers(self) -> "CoreRegistersIndex": def add_core(self, core: CoreTarget) -> None: core.delegate = self.delegate - core.set_target_context(CachingDebugContext(core)) + if self.debug_sequence_delegate: + core.debug_sequence_delegate = self.debug_sequence_delegate + ctx = CachingDebugContext( + core, + enable_memory=self.session.options['cache.enable_memory'], + enable_register=self.session.options['cache.enable_register'], + ) + core.set_target_context(ctx) self.cores[core.core_number] = core self.add_child(core) - # Select first added core. + # Always select first added core to ensure some core is selected. if self.selected_core is None: self.selected_core = core.core_number + # Otherwise, when the chosen primary core is added, select it. This assumes that cores are only + # added at init/discovery time. + elif core.core_number == self.session.options.get('primary_core'): + self.selected_core = core.core_number def create_init_sequence(self) -> CallSequence: # Return an empty call sequence. The subclass must override this. @@ -293,4 +318,7 @@ def trace_start(self): def trace_stop(self): self.call_delegate('trace_stop', target=self, mode=0) + def add_target_command_groups(self, command_set: "CommandSet"): + """@brief Hook for adding target-specific commands to a command set.""" + self.call_delegate('add_target_command_groups', target=self, command_set=command_set) diff --git a/pyocd/core/target.py b/pyocd/core/target.py index fb675382c..0b2331200 100644 --- a/pyocd/core/target.py +++ b/pyocd/core/target.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2006-2019 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,10 +16,11 @@ # limitations under the License. from enum import Enum -from typing import (Any, Callable, List, Optional, Sequence, TYPE_CHECKING) +from typing import (Any, Callable, List, Optional, Sequence, TYPE_CHECKING, Set) from .memory_interface import MemoryInterface from .memory_map import MemoryMap +from .target_delegate import DelegateHavingMixIn from ..utility.graph import GraphNode if TYPE_CHECKING: @@ -31,7 +32,7 @@ from ..debug.svd.model import SVDDevice from ..utility.sequencer import CallSequence -class Target(MemoryInterface): +class Target(MemoryInterface, DelegateHavingMixIn): class State(Enum): """@brief States a target processor can be in.""" @@ -59,16 +60,17 @@ class ResetType(Enum): HW = 1 ## Software reset using the core's default software reset method. SW = 2 - ## Software reset using the AIRCR.SYSRESETREQ bit. - SW_SYSRESETREQ = 3 - ## Software reset the entire system (alias of #SW_SYSRESETREQ). - SW_SYSTEM = SW_SYSRESETREQ - ## Software reset using the AIRCR.VECTRESET bit. + ## Software reset the entire system . + SW_SYSTEM = 3 + ## Software reset using the AIRCR.SYSRESETREQ bit (alias of #SW_SYSTEM). + SW_SYSRESETREQ = SW_SYSTEM + ## Software reset the core only. + SW_CORE = 4 + ## Software reset using the AIRCR.VECTRESET bit (alias of #SW_CORE). # - # v6-M and v8-M targets do not support VECTRESET, so they will fall back to SW_EMULATED. - SW_VECTRESET = 4 - ## Software reset the core only (alias of #SW_VECTRESET). - SW_CORE = SW_VECTRESET + # v6-M and v8-M targets do not support VECTRESET, so they will fall back to SW_EMULATED, + # unless a target-specific core reset method is made available. + SW_VECTRESET = SW_CORE ## Emulated software reset. SW_EMULATED = 5 @@ -187,7 +189,6 @@ class HaltReason(Enum): def __init__(self, session: "Session", memory_map: Optional[MemoryMap] = None) -> None: self._session = session - self._delegate: Any = None # Make a target-specific copy of the memory map. This is safe to do without locking # because the memory map may not be mutated until target initialization. self.memory_map = memory_map.clone() if memory_map else MemoryMap() @@ -198,24 +199,6 @@ def __init__(self, session: "Session", memory_map: Optional[MemoryMap] = None) - def session(self) -> "Session": return self._session - @property - def delegate(self) -> Any: - return self._delegate - - @delegate.setter - def delegate(self, the_delegate: Any) -> None: - self._delegate = the_delegate - - def delegate_implements(self, method_name: str) -> bool: - return (self._delegate is not None) and (hasattr(self._delegate, method_name)) - - def call_delegate(self, method_name: str, *args, **kwargs) -> None: - if self.delegate_implements(method_name): - return getattr(self._delegate, method_name)(*args, **kwargs) - else: - # The default action is always taken if None is returned. - return None - @property def svd_device(self) -> Optional["SVDDevice"]: return self._svd_device @@ -228,6 +211,11 @@ def supported_security_states(self) -> Sequence[SecurityState]: def core_registers(self) -> "CoreRegistersIndex": raise NotImplementedError() + @property + def supported_reset_types(self) -> Set[ResetType]: + """@brief Set of reset types that can be used with this target.""" + raise NotImplementedError() + def is_locked(self) -> bool: return False diff --git a/pyocd/core/target_delegate.py b/pyocd/core/target_delegate.py index 2d085cf18..827cb1826 100644 --- a/pyocd/core/target_delegate.py +++ b/pyocd/core/target_delegate.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2019 Arm Limited -# COpyright (c) 2021 Chris Reed +# COpyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,7 +15,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -from typing import (Optional, TYPE_CHECKING) +from typing import (Any, Optional, TYPE_CHECKING) if TYPE_CHECKING: from .session import Session @@ -24,6 +24,8 @@ from .target import Target from ..board.board import Board from ..utility.sequencer import CallSequence + from ..debug.sequences.delegates import DebugSequenceDelegate + from ..commands.execution_context import CommandSet ## @brief Return type for some delegate methods. # @@ -32,6 +34,49 @@ # processing. DelegateResult = Optional[bool] + +class DelegateHavingMixIn: + """! @brief Mix-in class adding delegate support. + + There are two types of delegates: + - Debug sequence delegates + - Arbitrary delegate classes + """ + + _delegate: Any = None + _debug_sequence_delegate: Optional["DebugSequenceDelegate"] = None + + @property + def delegate(self) -> Any: + return self._delegate + + @delegate.setter + def delegate(self, the_delegate: Any) -> None: + self._delegate = the_delegate + + @property + def debug_sequence_delegate(self) -> Optional["DebugSequenceDelegate"]: + return self._debug_sequence_delegate + + @debug_sequence_delegate.setter + def debug_sequence_delegate(self, the_delegate: "DebugSequenceDelegate") -> None: + self._debug_sequence_delegate = the_delegate + + def delegate_implements(self, method_name: str) -> bool: + return (self._delegate is not None) and (hasattr(self._delegate, method_name)) + + def call_delegate(self, method_name: str, *args: Any, **kwargs: Any) -> Optional[bool]: + if self.delegate_implements(method_name): + return getattr(self._delegate, method_name)(*args, **kwargs) + else: + # The default action is always taken if None is returned. + return None + + def has_debug_sequence(self, name: str, pname: Optional[str] = None) -> bool: + seq_delegate = self.debug_sequence_delegate + return seq_delegate.has_sequence_with_name(name, pname) if seq_delegate else False + + class TargetDelegateInterface: """@brief Abstract class defining the delegate interface for targets. @@ -43,6 +88,17 @@ class TargetDelegateInterface: def __init__(self, session: "Session") -> None: self._session = session + def unlock_device(self, target: "SoCTarget") -> None: + """! @brief Hook to perform any required unlock sequence. + + Called after the DP is initialised but prior to discovery. + + @param self + @param target An SoCTarget object about to be initialized. + @return Ignored. + """ + pass + def will_connect(self, board: "Board") -> None: """@brief Pre-init hook for the board. @param self @@ -219,4 +275,11 @@ def trace_stop(self, target: "SoCTarget", mode: int) -> None: """ pass + def add_target_command_groups(self, target: "SoCTarget", command_set: "CommandSet"): + """@brief Hook for adding target-specific commands to a command set. + @param self + @param target A `SoCTarget` object. + @param command_set The `CommandSet` object to which commands may be added. + """ + pass diff --git a/pyocd/coresight/ap.py b/pyocd/coresight/ap.py index 6f48f954d..8a37ef064 100644 --- a/pyocd/coresight/ap.py +++ b/pyocd/coresight/ap.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -195,15 +195,19 @@ class APAddressBase: version-specific subclasses. This is the value used by the DP hardware and passed to the DebugPort's read_ap() and write_ap() methods. + AP addresses include the index of the DP to which the AP is connected. On most systems there is only + one DP with index 0. + The class also indicates which version of AP is targeted: either APv1 or APv2. The _ap_version_ property reports this version number, though it is also encoded by the subclass. The AP version is coupled with the address because the two are intrinsically connected; the version defines the address format. """ - def __init__(self, address: int) -> None: + def __init__(self, address: int, dp: int = 0) -> None: """@brief Constructor accepting the nominal address.""" self._nominal_address = address + self._dp = dp @property def ap_version(self) -> APVersion: @@ -230,22 +234,42 @@ def idr_address(self) -> int: """@brief Address of the IDR register.""" raise NotImplementedError() + @property + def dp_index(self) -> int: + """@brief Index of the DP to which this AP is attached.""" + return self._dp + def __hash__(self) -> int: - return hash(self.nominal_address) + return hash(self.nominal_address | (self._dp << 64)) def __eq__(self, other: Any) -> bool: - return (self.nominal_address == other.nominal_address) \ - if isinstance(other, APAddressBase) else (self.nominal_address == other) + """Equality tests against other APAddressBase or subclass instances also compare the DP index. + Supports comparing against raw (int) nominal addresses, in which case the DP index is ignored. + """ + if isinstance(other, APAddressBase): + return (self.nominal_address == other.nominal_address) and (self.dp_index == other.dp_index) + elif isinstance(other, int): + return (self.nominal_address == other) + else: + return False def __lt__(self, other: Any) -> bool: - return (self.nominal_address < other.nominal_address) \ - if isinstance(other, APAddressBase) else (self.nominal_address < other) + """Ordering tests against other APAddressBase or subclass instances include the DP index, such that + instances with equal nominal addresses but different DP indices will be ordered by DP index. + Supports comparing against raw (int) nominal addresses, in which case the DP index is ignored. + """ + if isinstance(other, APAddressBase): + return (self.nominal_address < other.nominal_address) and (self.dp_index < other.dp_index) + elif isinstance(other, int): + return (self.nominal_address < other) + else: + return False def __str__(self) -> str: raise NotImplementedError() def __repr__(self) -> str: - return "<{}@{:#x} {}>".format(self.__class__.__name__, id(self), str(self)) + return "<{}@{:#x} {} dp={}>".format(self.__class__.__name__, id(self), str(self), self.dp_index) class APv1Address(APAddressBase): """@brief Represents the address for an APv1. @@ -389,6 +413,10 @@ def __init__( self.address = ap_address self._ap_version = ap_address.ap_version self.idr = idr + self.variant = 0 + self.revision = 0 + self.ap_class = 0 + self.ap_type = 0 self.type_name = name or "AP" self.rom_addr = 0 self.has_rom_table = False @@ -397,8 +425,23 @@ def __init__( self._flags = flags self._cmpid = cmpid + @property + def description(self): + """ @brief The AP's type and version description. + + If the AP is an unknown proprietary type, then only the string "proprietary" is returned. + + This property should only be read after init() has be called. + """ + if self.type_name is not None: + return f"{self.type_name} var{self.variant} rev{self.revision}" + else: + return "proprietary" + + @property def short_description(self) -> str: + """ @brief The AP's name and address.""" return self.type_name + str(self.address) @property @@ -421,12 +464,6 @@ def init(self) -> None: # Get the type name for this AP. self.ap_class = (self.idr & AP_IDR_CLASS_MASK) >> AP_IDR_CLASS_SHIFT self.ap_type = self.idr & AP_IDR_TYPE_MASK - if self.type_name is not None: - desc = "{} var{} rev{}".format(self.type_name, self.variant, self.revision) - else: - desc = "proprietary" - - LOG.info("%s IDR = 0x%08x (%s)", self.short_description, self.idr, desc) def find_components(self) -> None: """@brief Find CoreSight components attached to this AP.""" diff --git a/pyocd/coresight/component_ids.py b/pyocd/coresight/component_ids.py index 7fc71f56e..6f03edb4b 100644 --- a/pyocd/coresight/component_ids.py +++ b/pyocd/coresight/component_ids.py @@ -118,11 +118,14 @@ class CmpInfo(NamedTuple): # Full ID entries # Designer|Component Class |Part |Type |Archid |Name |Product |Factory (ARM_ID, CORESIGHT_CLASS, 0x193, 0x00, 0x0a57) : CmpInfo('TSGEN', 'CS-600', None ), - (ARM_ID, CORESIGHT_CLASS, 0x906, 0x14, 0) : CmpInfo('CTI', None, None ), - (ARM_ID, CORESIGHT_CLASS, 0x907, 0x21, 0) : CmpInfo('ETB', None, None ), - (ARM_ID, CORESIGHT_CLASS, 0x908, 0x12, 0) : CmpInfo('CSTF', None, None ), - (ARM_ID, CORESIGHT_CLASS, 0x912, 0x11, 0) : CmpInfo('TPIU', None, TPIU.factory ), + (ARM_ID, CORESIGHT_CLASS, 0x906, 0x14, 0) : CmpInfo('CTI', 'CS-400', None ), + (ARM_ID, CORESIGHT_CLASS, 0x907, 0x21, 0) : CmpInfo('ETB', 'CS-400', None ), + (ARM_ID, CORESIGHT_CLASS, 0x908, 0x12, 0) : CmpInfo('Trace Funnel', 'CS-400', None ), + (ARM_ID, CORESIGHT_CLASS, 0x909, 0x22, 0) : CmpInfo('Trace Replicator',None, None ), + (ARM_ID, CORESIGHT_CLASS, 0x912, 0x11, 0) : CmpInfo('TPIU', 'CS-400', TPIU.factory ), + (ARM_ID, CORESIGHT_CLASS, 0x913, 0x43, 0) : CmpInfo('ITM', 'CS-400', None ), (ARM_ID, CORESIGHT_CLASS, 0x914, 0x11, 0) : CmpInfo('SWO', 'CS-400', TPIU.factory ), + (ARM_ID, CORESIGHT_CLASS, 0x917, 0x43, 0) : CmpInfo('HTM', 'CS-400', None ), (ARM_ID, CORESIGHT_CLASS, 0x923, 0x11, 0) : CmpInfo('TPIU', 'M3', TPIU.factory ), (ARM_ID, CORESIGHT_CLASS, 0x924, 0x13, 0) : CmpInfo('ETM', 'M3', None ), (ARM_ID, CORESIGHT_CLASS, 0x925, 0x13, 0) : CmpInfo('ETM', 'M4', None ), @@ -132,6 +135,7 @@ class CmpInfo(NamedTuple): (ARM_ID, CORESIGHT_CLASS, 0x950, 0x13, 0) : CmpInfo('PTM', 'A9', None ), (ARM_ID, CORESIGHT_CLASS, 0x961, 0x32, 0) : CmpInfo('ETF', None, None ), # Trace Memory Controller ETF (ARM_ID, CORESIGHT_CLASS, 0x962, 0x63, 0x0a63) : CmpInfo('STM', None, None ), # System Trace Macrocell + (ARM_ID, CORESIGHT_CLASS, 0x962, 0x63, 0) : CmpInfo('STM', None, None ), # System Trace Macrocell (archid=0) (ARM_ID, CORESIGHT_CLASS, 0x963, 0x63, 0x0a63) : CmpInfo('STM-500', None, None ), # System Trace Macrocell (ARM_ID, CORESIGHT_CLASS, 0x975, 0x13, 0x4a13) : CmpInfo('ETM', 'M7', None ), (ARM_ID, CORESIGHT_CLASS, 0x9a0, 0x16, 0) : CmpInfo('PMU', 'A9', None ), diff --git a/pyocd/coresight/coresight_target.py b/pyocd/coresight/coresight_target.py index 83936ea85..a98eeeb60 100644 --- a/pyocd/coresight/coresight_target.py +++ b/pyocd/coresight/coresight_target.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,7 +17,6 @@ import logging from inspect import getfullargspec -from pathlib import PurePath from typing import (Callable, Dict, Optional, TYPE_CHECKING, cast) from ..core.target import Target @@ -27,7 +26,7 @@ from . import (dap, discovery) from ..debug.svd.loader import SVDLoader from ..utility.sequencer import CallSequence -from ..target.pack.flash_algo import PackFlashAlgo +from ..target.pack.flm_region_builder import FlmFlashRegionBuilder if TYPE_CHECKING: from ..core.session import Session @@ -56,6 +55,8 @@ def __init__(self, session: "Session", memory_map: Optional["MemoryMap"] = None) self._irq_table: Optional[Dict[int, str]] = None self._discoverer: Optional[Callable] = None + self.session.context_state.is_performing_pre_reset = False + @property def aps(self) -> Dict["APAddressBase", "AccessPort"]: return self.dp.aps @@ -96,6 +97,7 @@ def create_init_sequence(self) -> CallSequence: ('load_svd', self.load_svd), ('pre_connect', self.pre_connect), ('dp_init', self.dp.create_connect_sequence), + ('unlock_device', self.unlock_device), ('create_discoverer', self.create_discoverer), ('discovery', lambda : self._discoverer.discover() if self._discoverer else None), ('check_for_cores', self.check_for_cores), @@ -108,6 +110,18 @@ def create_init_sequence(self) -> CallSequence: return seq + def init(self) -> None: + """@brief CoreSight specific target init. + + Connects this object's delegates, including a debug sequence delegate, to the DP. + """ + # Set delegates on the DP. + self.dp.delegate = self.delegate + if self.debug_sequence_delegate: + self.dp.debug_sequence_delegate = self.debug_sequence_delegate + + super().init() + def disconnect(self, resume: bool = True) -> None: """@brief Disconnect from the target. @@ -117,12 +131,69 @@ def disconnect(self, resume: bool = True) -> None: self.call_delegate('will_disconnect', target=self, resume=resume) for core in self.cores.values(): core.disconnect(resume) - # Only disconnect the DP if resuming; otherwise it will power down debug and potentially - # let the core continue running. + # Only disconnect the DP if resuming; if not resuming we need to keep debug powered up so + # the core can stay halted. if resume: self.dp.disconnect() self.call_delegate('did_disconnect', target=self, resume=resume) + @property + def primary_core_pname(self) -> str: + """@brief Returns the pname for the `primary_core` option. + + This property is expected to be used prior to discovery. After discovery is complete, the + node name of the `.primary_core` property can be used. + + This property is used rarely, so is not cached. + + @exception KeyError if `primary_core` is invalid. + @exception AssertionError The device is not DFP based. + """ + # The `primary_core` is an index into available cores, not necessarily the same as the AP + # address and always different in the case of ADIv6. So we must use the DFP's list of APs + # and processors to reconstruct the core order we will find during discovery. + assert self.debug_sequence_delegate + pack_device = self.debug_sequence_delegate.cmsis_pack_device + ap_map = pack_device.processors_ap_map + primary_core = self.session.options.get('primary_core') + for i, proc_info in enumerate(sorted(ap_map.values(), key=lambda p: p.ap_address)): + if i == primary_core: + return proc_info.name + else: + raise exceptions.Error(f"invalid 'primary_core' session option '{primary_core}' " + f"(valid values are {', '.join(str(i) for i, _ in enumerate(ap_map.values()))})") + + def _call_pre_discovery_debug_sequence(self, sequence: str) -> bool: + """@brief Run a debug sequence before discovery has been performed. + + The primary core's pname cannot be looked up via the `node_name` property of the core + object because that core object doesn't yet exist at the time this method is called. + """ + if self.debug_sequence_delegate: + # Try to get the pname to use. + try: + pcore_pname = self.primary_core_pname + except exceptions.Error as err: + LOG.warning("%s", err) + else: + if self.has_debug_sequence(sequence, pname=pcore_pname): + self.debug_sequence_delegate.run_sequence(sequence, pname=pcore_pname) + return True + + # Sequence wasn't run. + return False + + def unlock_device(self) -> None: + """@brief Hook to unlock the debug. + + The default implementation of this hook calls the delegate `unlock_device()` method or `DebugDeviceUnlock` + debug sequence, if they exist, checked in this order. + """ + if self.delegate_implements('unlock_device'): + self.call_delegate('unlock_device') + else: + self._call_pre_discovery_debug_sequence('DebugDeviceUnlock') + def create_discoverer(self) -> None: """@brief Init task to create the discovery object. @@ -140,7 +211,14 @@ def pre_connect(self) -> None: mode = self.session.options.get('connect_mode') if mode == 'pre-reset': LOG.info("Performing connect pre-reset") - self.dp.reset() + try: + # Set the state variable indicating we're running ResetHardware for pre-reset, used + # by the debug sequence delegate's get_connection_type() method. + self.session.context_state.is_performing_pre_reset = True + if not self._call_pre_discovery_debug_sequence('ResetHardware'): + self.dp.reset() + finally: + self.session.context_state.is_performing_pre_reset = False elif mode == 'under-reset': LOG.info("Asserting reset prior to connect") self.dp.assert_reset(True) @@ -188,43 +266,18 @@ def post_connect(self) -> None: def create_flash(self) -> None: """@brief Instantiates flash objects for memory regions. - This init task iterates over flash memory regions and for each one creates the Flash - instance. It uses the flash_algo and flash_class properties of the region to know how + This init task iterates over flash memory regions and for each one finishes its setup and creates + the Flash instance. It uses the flash_algo and flash_class properties of the region to know how to construct the flash object. """ + flm_builder = FlmFlashRegionBuilder(self, self.memory_map) for region in self.memory_map.iter_matching_regions(type=MemoryType.FLASH): region = cast(FlashRegion, region) - # If the region doesn't have an algo dict but does have an FLM file, try to load - # the FLM and create the algo dict. - if (region.algo is None) and (region.flm is not None): - if isinstance(region.flm, (str, PurePath)): - flm_path = self.session.find_user_file(None, [str(region.flm)]) - if flm_path is not None: - LOG.info("creating flash algo for region %s from: %s", region.name, flm_path) - pack_algo = PackFlashAlgo(flm_path) - else: - LOG.warning("Failed to find FLM file: %s", region.flm) - break - elif isinstance(region.flm, PackFlashAlgo): - pack_algo = region.flm - else: - LOG.warning("flash region flm attribute is unexpected type") - break - - # Create the algo dict from the FLM. - if self.session.options.get("debug.log_flm_info"): - LOG.debug("Flash algo info: %s", pack_algo.flash_info) - page_size = pack_algo.page_size - if page_size <= 32: - page_size = min(s[1] for s in pack_algo.sector_sizes) - algo = pack_algo.get_pyocd_flash_algo( - page_size, - self.memory_map.get_default_region_of_type(MemoryType.RAM)) - - # If we got a valid algo from the FLM, set it on the region. This will then - # be used below. - if algo is not None: - region.algo = algo + + # Load FLM file if needed, and create subregions for sector sizes. + if not flm_builder.finalise_region(region): + # Some error occurred, skip this region. + continue # If the constructor of the region's flash class takes the flash_algo arg, then we # need the region to have a flash algo dict to pass to it. Otherwise we assume the @@ -246,6 +299,10 @@ def create_flash(self) -> None: # Store the flash object back into the memory region. region.flash = obj + # Update the memory map in each core. + for core in self.cores.values(): + core.memory_map = self.memory_map + def check_for_cores(self) -> None: """@brief Init task: verify that at least one core was discovered.""" if not len(self.cores): @@ -282,4 +339,27 @@ def reset(self, reset_type=None): else: super().reset(reset_type) + @property + def first_ap(self) -> Optional["AccessPort"]: + if len(self.aps) == 0: + return None + return sorted(self.aps.values(), key=lambda v: v.address)[0] + + def trace_start(self): + result = self.call_delegate('trace_start', target=self, mode=0) + if not result and self.has_debug_sequence('TraceStart', pname=self.selected_core_or_raise.node_name): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('TraceStart', + pname=self.selected_core_or_raise.node_name) + result = True + return result + + def trace_stop(self): + result = self.call_delegate('trace_stop', target=self, mode=0) + if not result and self.has_debug_sequence('TraceStop', pname=self.selected_core_or_raise.node_name): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('TraceStop', + pname=self.selected_core_or_raise.node_name) + result = True + return result diff --git a/pyocd/coresight/cortex_m.py b/pyocd/coresight/cortex_m.py index 018686d03..f779235c9 100644 --- a/pyocd/coresight/cortex_m.py +++ b/pyocd/coresight/cortex_m.py @@ -17,7 +17,7 @@ import logging from time import sleep -from typing import (Any, Callable, List, Optional, overload, Sequence, TYPE_CHECKING, Union, cast) +from typing import (Any, Callable, List, Optional, Set, overload, Sequence, TYPE_CHECKING, Union, cast) from typing_extensions import Literal from ..core.target import Target @@ -230,9 +230,14 @@ def __init__(self, self._elf = None self.target_xml = None self._core_registers = CoreRegistersIndex() - self._supports_vectreset: bool = False - self._reset_catch_delegate_result: DelegateResult = False - self._reset_catch_saved_demcr: int = 0 + self._supported_reset_types: Set[Target.ResetType] = { + Target.ResetType.HW, + Target.ResetType.SW, + Target.ResetType.SW_EMULATED, + Target.ResetType.SW_SYSTEM, + Target.ResetType.SW_CORE, # May be removed since only v7-M cores support SW_VECTRESET + } + self._last_vector_catch: int = 0 self.fpb: Optional[FPB] = None self.dwt: Optional[DWT] = None @@ -241,9 +246,10 @@ def __init__(self, # Select default sw reset type based on whether multicore debug is enabled and which core # this is. - self._default_software_reset_type = Target.ResetType.SW_SYSRESETREQ \ - if (not self.session.options.get('enable_multicore_debug')) or (self.core_number == 0) \ - else Target.ResetType.SW_VECTRESET + self._default_software_reset_type = Target.ResetType.SW_SYSTEM \ + if (not self.session.options.get('enable_multicore_debug')) \ + or (self.core_number == self.session.options.get('primary_core')) \ + else Target.ResetType.SW_CORE # Set up breakpoints manager. self.sw_bp = SoftwareBreakpointProvider(self) @@ -286,6 +292,11 @@ def core_registers(self) -> CoreRegistersIndex: """ return self._core_registers + @property + def supported_reset_types(self) -> Set[Target.ResetType]: + """@brief Set of reset types that can be used with this target.""" + return self._supported_reset_types + @property def elf(self) -> Optional["ELFBinaryFile"]: return self._elf @@ -300,7 +311,16 @@ def default_reset_type(self) -> Target.ResetType: @default_reset_type.setter def default_reset_type(self, reset_type: Target.ResetType) -> None: + """@brief Modify the default software reset method. + @param self + @param reset_type One of the Target.ResetType enums, and must be in the `.supported_reset_types` + property. + @exception ValueError The provided reset type is not supported for this target; see + `.supported_reset_types` property. + """ assert isinstance(reset_type, Target.ResetType) + if reset_type not in self._supported_reset_types: + raise ValueError(f"{reset_type.name} reset type not supported") self._default_reset_type = reset_type @property @@ -312,11 +332,16 @@ def default_software_reset_type(self, reset_type: Target.ResetType) -> None: """@brief Modify the default software reset method. @param self @param reset_type Must be one of the software reset types: Target.ResetType.SW_SYSRESETREQ, - Target.ResetType.SW_VECTRESET, or Target.ResetType.SW_EMULATED. + Target.ResetType.SW_VECTRESET, or Target.ResetType.SW_EMULATED. Must also be in the + `.supported_reset_types` property. + @exception ValueError The provided reset type is not supported for this target; see + `.supported_reset_types` property. """ assert isinstance(reset_type, Target.ResetType) assert reset_type in (Target.ResetType.SW_SYSRESETREQ, Target.ResetType.SW_VECTRESET, Target.ResetType.SW_EMULATED) + if reset_type not in self._supported_reset_types: + raise ValueError(f"{reset_type.name} reset type not supported") self._default_software_reset_type = reset_type @property @@ -336,14 +361,15 @@ def init(self) -> None: self.call_delegate('will_start_debug_core', core=self) # Enable debug, preserving any current debug state. - if not self.call_delegate('start_debug_core', core=self): + if not self.start_debug_core_hook(): self.write32(self.DHCSR, (self.read32(self.DHCSR) & 0xffff) | self.DBGKEY | self.C_DEBUGEN) # Examine this CPU. self._read_core_type() self._check_for_fpu() + self._init_reset_types() self._build_registers() - + self.get_vector_catch() # Cache the current vector cache settings. self.sw_bp.init() self.call_delegate('did_start_debug_core', core=self) @@ -356,17 +382,37 @@ def disconnect(self, resume: bool = True) -> None: if self.dwt is not None: self.dwt.remove_all_watchpoints() - if not self.call_delegate('stop_debug_core', core=self): + # Disable core debug if resuming. Note that we don't call the 'stop_core_debug' hook + # (stop_debug_core delegate or DebugCoreStop sequence) if not resuming, as these will + # normally resume the core and disable debug logic. + if resume and not self.stop_debug_core_hook(): + # Call .resume() even though we clear DHCSR just below, so that notifications get sent. + self.resume() + + # Clear debug controls. + self.write32(CortexM.DHCSR, CortexM.DBGKEY | 0x0000) + # Disable other debug blocks. self.write32(CortexM.DEMCR, 0) - # Disable core debug. - if resume: - self.resume() - self.write32(CortexM.DHCSR, CortexM.DBGKEY | 0x0000) - self.call_delegate('did_stop_debug_core', core=self) + def start_debug_core_hook(self): + result = self.call_delegate('start_debug_core', core=self) + if not result and self.has_debug_sequence('DebugCoreStart', pname=self.node_name): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('DebugCoreStart', pname=self.node_name) + result = True + return result + + def stop_debug_core_hook(self): + result = self.call_delegate('stop_debug_core', core=self) + if not result and self.has_debug_sequence('DebugCoreStop', pname=self.node_name): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('DebugCoreStop', pname=self.node_name) + result = True + return result + def _build_registers(self) -> None: """@brief Build set of core registers available on this code. @@ -394,10 +440,9 @@ def _read_core_type(self) -> None: self.cpu_revision = (cpuid & CortexM.CPUID_VARIANT_MASK) >> CortexM.CPUID_VARIANT_POS self.cpu_patch = (cpuid & CortexM.CPUID_REVISION_MASK) >> CortexM.CPUID_REVISION_POS - # Only v7-M supports VECTRESET. + # Set the arch version. if arch == CortexM.ARMv7M: self._architecture = CoreArchitecture.ARMv7M - self._supports_vectreset = True else: self._architecture = CoreArchitecture.ARMv6M @@ -449,6 +494,19 @@ def _check_for_fpu(self) -> None: fpu_type = "FPv4-SP-D16-M" LOG.info("FPU present: " + fpu_type) + def _init_reset_types(self) -> None: + """@brief Adjust supported reset types based on the architecture.""" + # Only v7-M supports VECTRESET. + if self._architecture != CoreArchitecture.ARMv7M: + self._supported_reset_types.remove(Target.ResetType.SW_CORE) + + # Adjust the default reset types to fall back to emulated if they were set + # to core/vectreset. + if self._default_reset_type == Target.ResetType.SW_CORE: + self._default_reset_type = Target.ResetType.SW_EMULATED + if self._default_software_reset_type == Target.ResetType.SW_CORE: + self._default_software_reset_type = Target.ResetType.SW_EMULATED + def write_memory(self, addr: int, data: int, transfer_size: int = 32) -> None: """@brief Write a single memory location. @@ -744,9 +802,30 @@ def _get_actual_reset_type(self, reset_type): if reset_type is Target.ResetType.SW: reset_type = self.default_software_reset_type - # Fall back to emulated sw reset if the vectreset is specified and the core doesn't support it. - if (reset_type is Target.ResetType.SW_VECTRESET) and (not self._supports_vectreset): - reset_type = Target.ResetType.SW_EMULATED + # Choose fallback if the selected reset type is not available. + if reset_type not in self._supported_reset_types: + # Fall back to emulated sw reset if the vectreset is specified and the core doesn't support it. + # Note: at the time of writing, SW_VECTRESET==SW_CORE and SW_SYSRESETREQ==SW_SYSTEM, but this + # will probably be changed, thus the asserts to make sure this code is updated when that changes. + assert Target.ResetType.SW_VECTRESET is Target.ResetType.SW_CORE + assert Target.ResetType.SW_SYSRESETREQ is Target.ResetType.SW_SYSTEM + if reset_type is Target.ResetType.SW_VECTRESET: + LOG.warning("%s reset type is selected but not available; falling back to emulated core reset", + reset_type.name, + ) + reset_type = Target.ResetType.SW_EMULATED + elif reset_type is Target.ResetType.SW_SYSRESETREQ: + if Target.ResetType.HW in self._supported_reset_types: + LOG.warning("%s reset type is selected but not available; falling back to HW reset", + reset_type.name, + ) + reset_type = Target.ResetType.HW + else: + LOG.warning("%s reset type is selected but not available; falling back to emulated " + "core reset because HW reset is not available either", + reset_type.name, + ) + reset_type = Target.ResetType.SW_EMULATED return reset_type @@ -808,20 +887,37 @@ def _post_reset_core_accessibility_test(self): else: LOG.debug("Core #%d did not come out of reset within timeout", self.core_number) - def reset(self, reset_type=None): - """@brief Reset the core. + def reset_hook(self, reset_type: Target.ResetType) -> Optional[bool]: + # Must import here to prevent an import cycle. + from ..target.pack.reset_sequence_maps import RESET_TYPE_TO_SEQUENCE_MAP + + result = self.call_delegate('will_reset', core=self, reset_type=reset_type) + if not result and (self.debug_sequence_delegate is not None): + # Map our reset type to a reset sequence name. + if reset_type is Target.ResetType.SW_EMULATED: + # Emulated reset isn't supported by standard debug sequences, so don't attempt + # to run any sequence. + return False + else: + try: + reset_sequence_name = RESET_TYPE_TO_SEQUENCE_MAP[reset_type] + except KeyError: + # Unhandled reset type. + raise exceptions.InternalError( + f"CortexM.reset_hook(): unhandled reset type {reset_type.name}") + + if self.has_debug_sequence(reset_sequence_name, pname=self.node_name): + assert self.debug_sequence_delegate + + # Run the reset sequence. + self.debug_sequence_delegate.run_sequence(reset_sequence_name, pname=self.node_name) + result = True + return result - The reset method is selectable via the reset_type parameter as well as the reset_type - session option. If the reset_type parameter is not specified or None, then the reset_type - option will be used. If the option is not set, or if it is set to a value of 'default', the - the core's default_reset_type property value is used. So, the session option overrides the - core's default, while the parameter overrides everything. + def _inner_reset(self, reset_type: Optional[Target.ResetType], is_halting: bool) -> None: + """@brief Internal routine for resetting the core. - Note that only v7-M cores support the `VECTRESET` software reset method. If this method - is chosen but the core doesn't support it, the the reset method will fall back to an - emulated software reset. - - After a call to this function, the core is running. + Shared by both normal and halting reset. """ reset_type = self._get_actual_reset_type(reset_type) @@ -833,7 +929,7 @@ def reset(self, reset_type=None): # Give the delegate a chance to overide reset. If the delegate returns True, then it # handled the reset on its own. - if not self.call_delegate('will_reset', core=self, reset_type=reset_type): + if not self.reset_hook(reset_type): self._perform_reset(reset_type) # Post reset recovery tests. @@ -847,37 +943,85 @@ def reset(self, reset_type=None): # Now run the core accessibility test. self._post_reset_core_accessibility_test() + # Unless this is a halting reset, make sure the core is not halted. Some DFP debug sequences + # (or user scripts) can leave the core halted after a reset. + if not is_halting: + if self.get_state() == Target.State.HALTED: + LOG.debug("reset: core was halted after non-halting reset; now resuming") + self.resume() + self.call_delegate('did_reset', core=self, reset_type=reset_type) self.session.notify(Target.Event.POST_RESET, self) - def set_reset_catch(self, reset_type): - """@brief Prepare to halt core on reset.""" + def reset(self, reset_type=None): + """@brief Reset the core. + + The reset method is selectable via the reset_type parameter as well as the reset_type + session option. If the reset_type parameter is not specified or None, then the reset_type + option will be used. If the option is not set, or if it is set to a value of 'default', the + the core's default_reset_type property value is used. So, the session option overrides the + core's default, while the parameter overrides everything. + + Note that only v7-M cores support the `VECTRESET` software reset method. If this method + is chosen but the core doesn't support it, the the reset method will fall back to an + emulated software reset. + + After a call to this function, the core is running. + """ + self._inner_reset(reset_type, is_halting=False) + + def set_reset_catch(self, reset_type=None): + """@brief Prepare to halt core on reset. + + This method nominally configures vector catch to stop code execution after the reset for the + core on which it is called. The delegate object and debug sequence delegate are both given a + chance to override the behaviour, in that order. + """ LOG.debug("set reset catch, core %d", self.core_number) - self._reset_catch_delegate_result = self.call_delegate('set_reset_catch', core=self, reset_type=reset_type) + # First let the delegate object have a chance. + delegate_result = self.call_delegate('set_reset_catch', core=self, reset_type=reset_type) + + # Next in line is a debug sequence. + if not delegate_result and self.has_debug_sequence('ResetCatchSet', pname=self.node_name): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('ResetCatchSet', pname=self.node_name) + delegate_result = True - # Default behaviour if the delegate didn't handle it. - if not self._reset_catch_delegate_result: + # Default behaviour if delegates didn't handle it. + if not delegate_result: # Halt the target. self.halt() - # Save CortexM.DEMCR. - self._reset_catch_saved_demcr = self.read_memory(CortexM.DEMCR) - # Enable reset vector catch if needed. - if (self._reset_catch_saved_demcr & CortexM.DEMCR_VC_CORERESET) == 0: - self.write_memory(CortexM.DEMCR, self._reset_catch_saved_demcr | CortexM.DEMCR_VC_CORERESET) + demcr = self.read_memory(CortexM.DEMCR) + if (demcr & CortexM.DEMCR_VC_CORERESET) == 0: + self.write_memory(CortexM.DEMCR, demcr | CortexM.DEMCR_VC_CORERESET) + + def clear_reset_catch(self, reset_type=None): + """@brief Disable halt on reset. - def clear_reset_catch(self, reset_type): - """@brief Disable halt on reset.""" + Free hardware resources allocated by set_reset_catch(), primarily meaning clearing the DEMCR.VC_CORERESET + bit if it was not previously set. The delegate object and debug sequence delegate are both given a + chance to override the behaviour, in that order. + """ LOG.debug("clear reset catch, core %d", self.core_number) - self.call_delegate('clear_reset_catch', core=self, reset_type=reset_type) + delegate_result = self.call_delegate('clear_reset_catch', core=self, reset_type=reset_type) + + # Check for a debug sequence. + if not delegate_result and self.has_debug_sequence('ResetCatchClear', pname=self.node_name): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('ResetCatchClear', pname=self.node_name) + delegate_result = True - if not self._reset_catch_delegate_result: - # restore vector catch setting - self.write_memory(CortexM.DEMCR, self._reset_catch_saved_demcr) + # Default behaviour if the delegates didn't handle it. + if not delegate_result and not (self._last_vector_catch & Target.VectorCatch.CORE_RESET): + # Clear VC_CORERESET in DEMCR. + demcr = self.read_memory(CortexM.DEMCR) + if (demcr & CortexM.DEMCR_VC_CORERESET) != 0: + self.write_memory(CortexM.DEMCR, demcr & ~CortexM.DEMCR_VC_CORERESET) def reset_and_halt(self, reset_type=None): """@brief Perform a reset and stop the core on the reset handler.""" @@ -887,7 +1031,7 @@ def reset_and_halt(self, reset_type=None): self.set_reset_catch(reset_type) # Perform the reset. - self.reset(reset_type) + self._inner_reset(reset_type, is_halting=True) # Wait until the unit resets. If emulated reset is used then it will have already halted # for us. @@ -951,8 +1095,9 @@ def is_halted(self): def resume(self): """@brief Resume execution of the core. """ - if self.get_state() != Target.State.HALTED: - LOG.debug('cannot resume: target not halted') + state = self.get_state() + if state != Target.State.HALTED: + LOG.debug('cannot resume core %d: core is %s', self.core_number, state.name) return LOG.debug("resuming core %d", self.core_number) self.session.notify(Target.Event.PRE_RUN, self, Target.RunType.RESUME) @@ -1344,16 +1489,19 @@ def _map_from_vector_catch_mask(mask): result |= Target.VectorCatch.SECURE_FAULT return result - def set_vector_catch(self, enableMask): + def set_vector_catch(self, enable_mask): + self._last_vector_catch = enable_mask demcr = self.read_memory(CortexM.DEMCR) - demcr |= CortexM._map_to_vector_catch_mask(enableMask) - demcr &= ~CortexM._map_to_vector_catch_mask(~enableMask) - LOG.debug("Setting vector catch to 0x%08x", enableMask) + demcr |= CortexM._map_to_vector_catch_mask(enable_mask) + demcr &= ~CortexM._map_to_vector_catch_mask(~enable_mask) + LOG.debug("Setting vector catch to 0x%08x", enable_mask) self.write_memory(CortexM.DEMCR, demcr) def get_vector_catch(self): demcr = self.read_memory(CortexM.DEMCR) - return CortexM._map_from_vector_catch_mask(demcr) + mask = CortexM._map_from_vector_catch_mask(demcr) + self._last_vector_catch = mask + return mask def is_debug_trap(self): debugEvents = self.read_memory(CortexM.DFSR) & (CortexM.DFSR_DWTTRAP | CortexM.DFSR_BKPT | CortexM.DFSR_HALTED) @@ -1408,12 +1556,9 @@ def set_target_context(self, context): "SysTick", ] - def exception_number_to_name(self, exc_num: int, name_thread: bool = False) -> Optional[str]: + def exception_number_to_name(self, exc_num: int) -> Optional[str]: if exc_num < len(self.CORE_EXCEPTION): - if exc_num == 0 and not name_thread: - return None - else: - return self.CORE_EXCEPTION[exc_num] + return self.CORE_EXCEPTION[exc_num] else: irq_num = exc_num - len(self.CORE_EXCEPTION) name = None diff --git a/pyocd/coresight/cortex_m_v8m.py b/pyocd/coresight/cortex_m_v8m.py index 1002cf792..27f77ed34 100644 --- a/pyocd/coresight/cortex_m_v8m.py +++ b/pyocd/coresight/cortex_m_v8m.py @@ -57,9 +57,6 @@ class CortexM_v8M(CortexM): def __init__(self, rootTarget, ap, memory_map=None, core_num=0, cmpid=None, address=None): super().__init__(rootTarget, ap, memory_map, core_num, cmpid, address) - # Only v7-M supports VECTRESET. - self._supports_vectreset = False - @property def supported_security_states(self): """@brief Tuple of security states supported by the processor. diff --git a/pyocd/coresight/dap.py b/pyocd/coresight/dap.py index 48e8cca33..37fbe7218 100644 --- a/pyocd/coresight/dap.py +++ b/pyocd/coresight/dap.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # Copyright (c) 2022 Clay McClure # Copyright (c) 2022 Toshiba Electronic Devices & Storage Corporation # SPDX-License-Identifier: Apache-2.0 @@ -24,6 +24,7 @@ from ..core import (exceptions, memory_interface) from ..core.target import Target +from ..core.target_delegate import DelegateHavingMixIn from ..probe.debug_probe import DebugProbe from ..probe.swj import SWJSequenceSender from .ap import APSEL_APBANKSEL @@ -201,8 +202,9 @@ class DPConnector: DP IDR register. The probe must be already connected for the desired wire protocol. """ - def __init__(self, probe: DebugProbe) -> None: + def __init__(self, probe: DebugProbe, dp: "DebugPort") -> None: self._probe = probe + self._dp = dp self._idr = DPIDR(0, 0, 0, 0, 0) # Make sure we have a session, since we get the session from the probe and probes have their session set @@ -231,13 +233,15 @@ def connect(self) -> None: # Create object to send SWJ sequences. swj = SWJSequenceSender(self._probe, use_dormant) + def jtag_enter_run_test_idle(): + self._probe.jtag_sequence(6, 1, False, 0x3f) + self._probe.jtag_sequence(1, 0, False, 0x1) + if protocol == DebugProbe.Protocol.JTAG \ and DebugProbe.Capability.JTAG_SEQUENCE in self._probe.capabilities: - def jtag_enter_run_test_idle(): - self._probe.jtag_sequence(6, 1, 0, 0x3f) - self._probe.jtag_sequence(1, 0, 0, 0x1) + use_jtag_enter_run_test_idle = True else: - jtag_enter_run_test_idle = None + use_jtag_enter_run_test_idle = False # Multiple attempts to select protocol and read DP IDR. for attempt in range(4): @@ -245,7 +249,7 @@ def jtag_enter_run_test_idle(): if send_swj: swj.select_protocol(protocol) - if jtag_enter_run_test_idle: + if use_jtag_enter_run_test_idle: jtag_enter_run_test_idle() # Attempt to read the DP IDR register. @@ -278,14 +282,14 @@ def jtag_enter_run_test_idle(): def read_idr(self) -> DPIDR: """@brief Read IDR register and get DP version""" - dpidr = self._probe.read_dp(DP_IDR, now=True) + dpidr = self._dp.read_dp(DP_IDR, now=True) dp_partno = (dpidr & DPIDR_PARTNO_MASK) >> DPIDR_PARTNO_SHIFT dp_version = (dpidr & DPIDR_VERSION_MASK) >> DPIDR_VERSION_SHIFT dp_revision = (dpidr & DPIDR_REVISION_MASK) >> DPIDR_REVISION_SHIFT is_mindp = (dpidr & DPIDR_MIN_MASK) != 0 return DPIDR(dpidr, dp_partno, dp_version, dp_revision, is_mindp) -class DebugPort: +class DebugPort(DelegateHavingMixIn): """@brief Represents the Arm Debug Interface (ADI) Debug Port (DP).""" ## Sleep for 50 ms between connection tests and reconnect attempts after a reset. @@ -433,17 +437,40 @@ def _get_probe_capabilities(self) -> None: self._probe_supports_apv2_addresses = (DebugProbe.Capability.APv2_ADDRESSES in caps) self._have_probe_capabilities = True + def connect_debug_port_hook(self) -> Optional[bool]: + if self.has_debug_sequence('DebugPortSetup'): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('DebugPortSetup') + return True + + def enable_debug_port_hook(self) -> Optional[bool]: + if self.has_debug_sequence('DebugPortStart'): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('DebugPortStart') + return True + + def disable_debug_port_hook(self) -> Optional[bool]: + if self.has_debug_sequence('DebugPortStop'): + assert self.debug_sequence_delegate + self.debug_sequence_delegate.run_sequence('DebugPortStop') + return True + def _connect(self) -> None: # Connect the probe. probe_conn = ProbeConnector(self.probe) probe_conn.connect(self._protocol) # Attempt to connect DP. - connector = DPConnector(self.probe) - connector.connect() + connector = DPConnector(self.probe, self) + if not self.connect_debug_port_hook(): + connector.connect() + self.dpidr = connector.idr + else: + # We still need to read the IDR for our own use. + self.dpidr = connector.read_idr() + assert self.dpidr # Report on DP version. - self.dpidr = connector.idr LOG.log(logging.INFO if self._log_dp_info else logging.DEBUG, "DP IDR = 0x%08x (v%d%s rev%d)", self.dpidr.idr, self.dpidr.version, " MINDP" if self.dpidr.mindp else "", self.dpidr.revision) @@ -518,6 +545,9 @@ def power_up_debug(self) -> bool: @return Boolean indicating whether the power up request succeeded. """ + if self.enable_debug_port_hook(): + return True + # Send power up request for system and debug. self.write_reg(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | MASKLANE | TRNNORMAL) @@ -541,6 +571,9 @@ def power_down_debug(self) -> bool: @return Boolean indicating whether the power down request succeeded. """ + if self.disable_debug_port_hook(): + return True + # Power down system first. self.write_reg(DP_CTRL_STAT, CDBGPWRUPREQ | MASKLANE | TRNNORMAL) diff --git a/pyocd/coresight/discovery.py b/pyocd/coresight/discovery.py index fe040960d..923cb59b3 100644 --- a/pyocd/coresight/discovery.py +++ b/pyocd/coresight/discovery.py @@ -136,7 +136,6 @@ def _find_aps(self): except exceptions.Error as e: LOG.error("Error probing AP#%d: %s", apsel, e, exc_info=self.session.log_tracebacks) - break apsel += 1 # Update the AP list once we know it's complete. @@ -161,6 +160,8 @@ def _create_1_ap(self, apsel): ap_address = APv1Address(apsel) ap = AccessPort.create(self.dp, ap_address) self.dp.aps[ap_address] = ap + + LOG.info("%s IDR = 0x%08x (%s)", ap.short_description, ap.idr, ap.description) except exceptions.Error as e: LOG.error("Error reading AP#%d IDR: %s", apsel, e, exc_info=self.session.log_tracebacks) @@ -241,6 +242,8 @@ def _create_1_ap(self, cmpid): ap_address = APv2Address(cmpid.address) ap = AccessPort.create(self.dp, ap_address, cmpid=cmpid) self.dp.aps[ap_address] = ap + + LOG.info("%s IDR = 0x%08x (%s)", ap.short_description, ap.idr, ap.description) except exceptions.Error as e: LOG.error("Error reading AP@0x%08x IDR: %s", cmpid.address, e, exc_info=self.session.log_tracebacks) diff --git a/pyocd/debug/cache.py b/pyocd/debug/cache.py index 2a3364a82..bcec2dcd0 100644 --- a/pyocd/debug/cache.py +++ b/pyocd/debug/cache.py @@ -1,5 +1,6 @@ # pyOCD debugger # Copyright (c) 2016-2019 Arm Limited +# Copyright (c) 2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,10 +22,12 @@ class CachingDebugContext(DebugContext): """@brief Debug context combining register and memory caches.""" - def __init__(self, parent): - super(CachingDebugContext, self).__init__(parent) - self._regcache = RegisterCache(parent, self.core) - self._memcache = MemoryCache(parent, self.core) + def __init__(self, parent, enable_memory: bool = True, enable_register: bool = True) -> None: + super().__init__(parent) + self._enable_memory = enable_memory + self._enable_register = enable_register + self._regcache = RegisterCache(parent, self.core) if enable_register else parent + self._memcache = MemoryCache(parent, self.core) if enable_memory else parent def write_memory(self, addr, value, transfer_size=32): return self._memcache.write_memory(addr, value, transfer_size) @@ -51,8 +54,10 @@ def write_core_registers_raw(self, reg_list, data_list): return self._regcache.write_core_registers_raw(reg_list, data_list) def invalidate(self): - self._regcache.invalidate() - self._memcache.invalidate() + if self._enable_register: + self._regcache.invalidate() + if self._enable_memory: + self._memcache.invalidate() diff --git a/pyocd/debug/rtt.py b/pyocd/debug/rtt.py new file mode 100644 index 000000000..4dae5f583 --- /dev/null +++ b/pyocd/debug/rtt.py @@ -0,0 +1,488 @@ +# pyOCD debugger +# Copyright (c) 2021 mikisama +# Copyright (C) 2021 Ciro Cattuto +# Copyright (C) 2021 Simon D. Levy +# Copyright (C) 2022 Johan Carlsson +# Copyright (c) 2022 Samuel Dewan +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from abc import ABC, abstractmethod +from ctypes import Structure, c_char, c_int32, c_uint32, sizeof +import struct +from typing import Optional, Sequence + +from ..core.memory_map import MemoryMap, MemoryRegion, MemoryType +from ..core.soc_target import SoCTarget +from ..core import exceptions + + +class SEGGER_RTT_BUFFER_UP(Structure): + """@brief `SEGGER RTT Ring Buffer` target to host.""" + + _fields_ = [ + ("sName", c_uint32), + ("pBuffer", c_uint32), + ("SizeOfBuffer", c_uint32), + ("WrOff", c_uint32), + ("RdOff", c_uint32), + ("Flags", c_uint32), + ] + +class SEGGER_RTT_BUFFER_DOWN(Structure): + """@brief `SEGGER RTT Ring Buffer` host to target.""" + + _fields_ = [ + ("sName", c_uint32), + ("pBuffer", c_uint32), + ("SizeOfBuffer", c_uint32), + ("WrOff", c_uint32), + ("RdOff", c_uint32), + ("Flags", c_uint32), + ] + +class SEGGER_RTT_CB(Structure): + """@brief `SEGGER RTT control block` structure. """ + + _fields_ = [ + ("acID", c_char * 16), + ("MaxNumUpBuffers", c_int32), + ("MaxNumDownBuffers", c_int32) + ] + + + +class RTTUpChannel(ABC): + """@brief Wrapper for an RTT up channel for target to host data transfer. """ + + name: Optional[str] + size: int + + @abstractmethod + def read(self) -> bytes: + """@brief Read all available data from RTT channel. """ + + +class RTTDownChannel(ABC): + """@brief Wrapper for an RTT down channel for host to target data transfer. """ + + name: Optional[str] + size: int + + @abstractmethod + def write(self, data: bytes, blocking = False) -> int: + """@brief Write data to RTT channel. + + Write as much of the provided data as possible to an the RTT down + channel. + + @param data The data to be written. + @param blocking If true will block until all data is sent. + + @return The number of bytes written to the target. + """ + + +class RTTControlBlock(ABC): + """@brief Represents an RTT control block. + + This helper class can be used to search for and parse an RTT control block. + Once the control block is found and parsed (using the start() method) + RTTUpChannel and RTTDownChannel objects will be created to facilitate + communication with the target. + """ + + up_channels: Sequence[RTTUpChannel] + down_channels: Sequence[RTTDownChannel] + + @abstractmethod + def start(self): + """@brief Find the RTT control block on the target. + + Searches for the RTT control block. Once found, the up_channels and + down_channels lists are populated with RTTUpChannel and RTTDownChannel + objects that can be used to communicate with the target. + """ + pass + + @classmethod + def from_target(cls, target: SoCTarget, address: int = None, + size: int = None, control_block_id: bytes = b'SEGGER RTT'): + """@brief Create an RTTControlBlock object using a given target. + + This function creates an instance of an appropriate RTTControlBlock + subclass depending on the provided target. + + @param target The target with which RTT communication is desired. + @param address Base address for control block search range. + @param size Control block search range. If 0 the control block will be + expected to be located at the provided address. + @param control_block_id The control block ID string to search for. Must + be at most 16 bytes long. Will be padded with + zeroes if less than 16 bytes. + + @return An instance of an appropriate RTTControlBlock subclass. + """ + # TODO: Handle targets connected with jlink differently + return GenericRTTControlBlock(target, address = address, size = size, + control_block_id = control_block_id) + + + + +class GenericRTTUpChannel(RTTUpChannel): + """@brief Software implementation of RTT up channel. Does not require any + support from interface. + """ + + _target: SoCTarget + name: Optional[str] + _buffer_address: int + size: int + _offsets_addr: int + _desc_addr: int + + def __init__(self, target: SoCTarget, desc_addr: int): + """ + @param target Target to communicate with. + @param desc_addr Address of up buffer descriptor. + """ + self._target = target + self._desc_addr = desc_addr + self._offsets_addr = self._desc_addr + SEGGER_RTT_BUFFER_UP.WrOff.offset + + self._read_descriptor() + + def _read_descriptor(self): + # Get buffer descriptor + up_buffer_words = sizeof(SEGGER_RTT_BUFFER_UP) // 4 + data = self._target.read_memory_block32(self._desc_addr, up_buffer_words) + descriptor: SEGGER_RTT_BUFFER_UP = SEGGER_RTT_BUFFER_UP(*data) + + # Get name if there is one + if descriptor.sName != 0: + data = b'' + while True: + data += bytes(self._target.read_memory_block8(descriptor.sName, 32)) + name_length = data.find(b'\0') + if name_length != -1: + self.name = data[:name_length].decode("utf-8", "backslashreplace") + break + elif len(data) >= 512: + # Give up, this probably isn't a valid string + self.name = data.decode("utf-8", "backslashreplace") + break + else: + self.name = None + + self._buffer_address = descriptor.pBuffer + self.size = descriptor.SizeOfBuffer + + @property + def bytes_available(self) -> int: + """@brief Number of bytes available to be read from up channel. """ + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is not yet populated + self._read_descriptor() + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is still not populated + return 0 + + # Get offsets + write_off, read_off = self.target.read_memory_block32(self._offsets_addr, 2) + + if (write_off >= self.size) or (read_off >= self.size): + raise exceptions.RTTError("Invalid up buffer") + elif write_off == self.read_off: + return 0 + elif write_off > read_off: + return write_off - read_off + else: + return (self.size - read_off) + write_off + + def read(self) -> bytes: + """@brief Read all available data from RTT channel. """ + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is not yet populated + self._read_descriptor() + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is still not populated + return b'' + + # Get offsets + write_off, read_off = self._target.read_memory_block32(self._offsets_addr, 2) + + if (write_off >= self.size) or (read_off >= self.size): + raise exceptions.RTTError("Invalid up buffer") + elif write_off == read_off: + # empty + return b'' + elif write_off > read_off: + """ + |oooooo|xxxxxxxxxxxx|oooooo| + 0 rdOff WrOff SizeOfBuffer + """ + data = self._target.read_memory_block8(self._buffer_address + read_off, + write_off - read_off) + else: + """ + |xxxxxx|oooooooooooo|xxxxxx| + 0 WrOff RdOff SizeOfBuffer + """ + data = self._target.read_memory_block8(self._buffer_address + read_off, + self.size - read_off) + data += self._target.read_memory_block8(self._buffer_address, write_off) + + # Update read offset + self._target.write32(self._offsets_addr + 4, write_off) + return bytes(data) + + +class GenericRTTDownChannel(RTTDownChannel): + """@brief Software implementation of RTT down channel. Does not require any + support from interface. + """ + + _target: SoCTarget + name: Optional[str] + _buffer_address: int + size: int + _offsets_addr: int + _desc_addr: int + + def __init__(self, target: SoCTarget, desc_addr: int): + """ + @param target Target to communicate with. + @param desc_addr Address of down buffer descriptor. + """ + self._target = target + self._desc_addr = desc_addr + self._offsets_addr = self._desc_addr + SEGGER_RTT_BUFFER_DOWN.WrOff.offset + + self._read_descriptor() + + def _read_descriptor(self): + # Get buffer descriptor + up_buffer_words = sizeof(SEGGER_RTT_BUFFER_DOWN) // 4 + data = self._target.read_memory_block32(self._desc_addr, up_buffer_words) + descriptor: SEGGER_RTT_BUFFER_DOWN = SEGGER_RTT_BUFFER_DOWN(*data) + + # Get name if there is one + if descriptor.sName != 0: + data = b'' + while True: + data += bytes(self._target.read_memory_block8(descriptor.sName, 64)) + name_length = data.find(b'\0') + if name_length != -1: + self.name = data[:name_length].decode("utf-8", "backslashreplace") + break + elif len(data) > 512: + # Give up, this probably isn't a valid string + self.name = data.decode("utf-8", "backslashreplace") + break + else: + self.name = None + + self._buffer_address = descriptor.pBuffer + self.size = descriptor.SizeOfBuffer + + @property + def bytes_free(self) -> int: + """@brief Number of bytes free in RTT down channel ring buffer.""" + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is not yet populated + self._read_descriptor() + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is still not populated + return 0 + + # Get offsets + write_off, read_off = self._target.read_memory_block32(self._offsets_addr, 2) + + if (write_off >= self.size) or (read_off >= self.size): + raise exceptions.RTTError("Invalid down buffer") + elif write_off == self.read_off: + return self.size + elif write_off > read_off: + return (self.size - write_off) + (read_off - 1) + else: + return read_off - write_off - 1 + + def write(self, data: bytes, blocking = False) -> int: + """@brief Write data to RTT channel. + + Write as much of the provided data as possible to an the RTT down + channel. + + @param data The data to be written. + @param blocking If true will block until all data is sent. + + @return The number of bytes written to the target. + """ + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is not yet populated + self._read_descriptor() + if (self.size == 0) or (self._buffer_address == 0): + # descriptor is still not populated + return 0 + + if blocking: + # Call non-blocking version until all data is written + while data: + bytes_sent: int = self.write(data, blocking = False) + data = data[bytes_sent:] + return + + # Get offsets + write_off, read_off = self._target.read_memory_block32(self._offsets_addr, 2) + + if (write_off >= self.size) or (read_off >= self.size): + raise exceptions.RTTError("Invalid down buffer") + + + bytes_written: int = 0 + if write_off >= read_off: + # There is some space to fill at the top of the buffer + free_space: int = self.size - write_off + if read_off == 0: + # Can't use the last element in the buffer + free_space -= 1 + data_to_write: bytes = data[:free_space] + self._target.write_memory_block8(self._buffer_address + write_off, + data_to_write) + bytes_written = len(data_to_write) + data = data[bytes_written:] + write_off = (write_off + bytes_written) % self.size + + free_space: int = read_off - write_off - 1 + if free_space < 0: + free_space = 0 + + bytes_to_write: int = min(free_space, len(data)) + self._target.write_memory_block8(self._buffer_address + write_off, + data[:bytes_to_write]) + bytes_written += bytes_to_write + write_off += bytes_to_write + + # Store new write offset + self._target.write32(self._offsets_addr, write_off) + return bytes_written + + +class GenericRTTControlBlock(RTTControlBlock): + """@brief Software implementation of RTT control block helper. Does not + require any support from interface. + """ + + target: SoCTarget + _cb_search_address: int + _cb_search_size_words: int + _control_block_id: Sequence[int] + + def __init__(self, target: SoCTarget, address: int = None, + size: int = None, control_block_id: bytes = b'SEGGER RTT'): + """ + @param target The target with which RTT communication is desired. + @param address Base address for control block search range. + @param size Control block search range. If 0 the control block will be + expected to be located at the provided address. + @param control_block_id The control block ID string to search for. Must + be at most 16 bytes long. Will be padded with + zeroes if less than 16 bytes. + """ + self.target = target + self.up_channels = list() + self.down_channels = list() + + if address is None: + memory_map: MemoryMap = self.target.get_memory_map() + ram_region: MemoryRegion = memory_map.get_default_region_of_type(MemoryType.RAM) + + self._cb_search_address = ram_region.start + if size is None: + size = ram_region.length + else: + self._cb_search_address = address + + if size is None: + # Address was specified, but size was not. Assume that the control + # block is located exactly at the provided address. + self._cb_search_size_words = 0 + else: + self._cb_search_size_words = size // 4 + + extra_id_bytes = SEGGER_RTT_CB.acID.size - len(control_block_id) + control_block_bytes = control_block_id + b'\0' * extra_id_bytes + self._control_block_id = struct.unpack(" Optional[int]: + addr: int = self._cb_search_address & ~0x3 + search_size: int = self._cb_search_size_words + if search_size < len(self._control_block_id): + search_size = len(self._control_block_id) + + id_len = len(self._control_block_id) + offset: int = 0 + + while search_size: + read_size = min(search_size, 32) + data = self.target.read_memory_block32(addr, read_size) + + if not data: + break + + for word in data: + if word == self._control_block_id[offset]: + offset += 1 + if offset == id_len: + break + else: + num_skip_words = (offset + 1) + addr += (num_skip_words * 4) + search_size -= num_skip_words + offset = 0 + + if offset == id_len: + break + + return addr if offset == id_len else None + + def start(self): + """@brief Find the RTT control block on the target. + + Searches for the RTT control block. Once found, the up_channels and + down_channels lists are populated with RTTUpChannel and RTTDownChannel + objects that can be used to communicate with the target. + """ + + cb_addr = self._find_control_block() + + if cb_addr is None: + raise exceptions.RTTError("Control block not found") + + # Get control block info + num_up_buffs = self.target.read32(cb_addr + SEGGER_RTT_CB.MaxNumUpBuffers.offset) + num_down_buffs = self.target.read32(cb_addr + SEGGER_RTT_CB.MaxNumDownBuffers.offset) + + # Setup up channels + up_base = cb_addr + sizeof(SEGGER_RTT_CB) + for i in range(num_up_buffs): + addr = up_base + (i * sizeof(SEGGER_RTT_BUFFER_UP)) + self.up_channels.append(GenericRTTUpChannel(self.target, addr)) + + # Setup down channels + down_base = up_base + num_up_buffs * sizeof(SEGGER_RTT_BUFFER_UP) + for i in range(num_down_buffs): + addr = down_base + (i * sizeof(SEGGER_RTT_BUFFER_DOWN)) + self.down_channels.append(GenericRTTDownChannel(self.target, addr)) diff --git a/pyocd/debug/semihost.py b/pyocd/debug/semihost.py index a6933b467..998d3ae7a 100644 --- a/pyocd/debug/semihost.py +++ b/pyocd/debug/semihost.py @@ -1,6 +1,7 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited # Copyright (c) 2022 NXP +# Copyright (c) 2022-2023 Chris Reed # Copyright (c) 2023 Hardy Griech # SPDX-License-Identifier: Apache-2.0 # @@ -23,11 +24,16 @@ import time import datetime import pathlib -import six +from enum import (Enum, IntEnum) +from typing import (IO, TYPE_CHECKING, Callable, Dict, List, Optional, Tuple, Union, cast, overload) +from typing_extensions import Literal from ..coresight.cortex_m import CortexM from ..core import (exceptions, session) +if TYPE_CHECKING: + from .context import DebugContext + LOG = logging.getLogger(__name__) TRACE = LOG.getChild("trace") @@ -36,31 +42,33 @@ ## bkpt #0xab instruction BKPT_INSTR = 0xbeab -# ARM semihosting request numbers. -TARGET_SYS_OPEN = 0x01 -TARGET_SYS_CLOSE = 0x02 -TARGET_SYS_WRITEC = 0x03 -TARGET_SYS_WRITE0 = 0x04 -TARGET_SYS_WRITE = 0x05 -TARGET_SYS_READ = 0x06 -TARGET_SYS_READC = 0x07 -TARGET_SYS_ISERROR = 0x08 -TARGET_SYS_ISTTY = 0x09 -TARGET_SYS_SEEK = 0x0a -TARGET_SYS_FLEN = 0x0c -TARGET_SYS_TMPNAM = 0x0d -TARGET_SYS_REMOVE = 0x0e -TARGET_SYS_RENAME = 0x0f -TARGET_SYS_CLOCK = 0x10 -TARGET_SYS_TIME = 0x11 -TARGET_SYS_SYSTEM = 0x12 -TARGET_SYS_ERRNO = 0x13 -TARGET_SYS_GET_CMDLINE = 0x15 -TARGET_SYS_HEAPINFO = 0x16 -angel_SWIreason_EnterSVC = 0x17 # pylint: disable=invalid-name -TARGET_SYS_EXIT = 0x18 # Also called angel_SWIreason_ReportException -TARGET_SYS_ELAPSED = 0x30 -TARGET_SYS_TICKFREQ = 0x31 +class SemihostingRequests(IntEnum): + """@brief Arm semihosting request numbers.""" + SYS_OPEN = 0x01 + SYS_CLOSE = 0x02 + SYS_WRITEC = 0x03 + SYS_WRITE0 = 0x04 + SYS_WRITE = 0x05 + SYS_READ = 0x06 + SYS_READC = 0x07 + SYS_ISERROR = 0x08 + SYS_ISTTY = 0x09 + SYS_SEEK = 0x0a + SYS_FLEN = 0x0c + SYS_TMPNAM = 0x0d + SYS_REMOVE = 0x0e + SYS_RENAME = 0x0f + SYS_CLOCK = 0x10 + SYS_TIME = 0x11 + SYS_SYSTEM = 0x12 + SYS_ERRNO = 0x13 + SYS_GET_CMDLINE = 0x15 + SYS_HEAPINFO = 0x16 + angel_SWIreason_EnterSVC = 0x17 # pylint: disable=invalid-name + SYS_EXIT = 0x18 # Also called angel_SWIreason_ReportException + SYS_EXIT_EXTENDED = 0x20 + SYS_ELAPSED = 0x30 + SYS_TICKFREQ = 0x31 # Pseudo-file descriptor numbers. # Note: According to Arm semihosting spec, the fds must be non-zero. But to achive POSIX compatibility @@ -76,39 +84,55 @@ # @see SemihostAgent::get_data() MAX_STRING_LENGTH = 2048 -class SemihostIOHandler(object): +## Enumsused for the file ID to indicate a special file was opened. +class SpecialFile(Enum): + # ":semihosting-features" + SEMIHOSTING_FEATURES_FILE = object() + +class SemihostIOHandler: """@brief Interface for semihosting file I/O handlers. This class is also used as the default I/O handler if none is provided to SemihostAgent. In this case, all file I/O requests are rejected. """ - def __init__(self): + agent: Optional["SemihostAgent"] + _errno: int + + def __init__(self) -> None: self.agent = None self._errno = 0 - def cleanup(self): + def cleanup(self) -> None: pass @property - def errno(self): + def errno(self) -> int: return self._errno - def _std_open(self, fnptr, fnlen, mode): + def _std_open(self, fnptr: int, fnlen: int, mode: str) -> Tuple[Optional[Union[int, SpecialFile]], str]: """@brief Helper for standard I/O open requests. - In the ARM semihosting spec, standard I/O files are opened using a filename of ":tt" + In the Arm semihosting spec, standard I/O files are opened using a filename of ":tt" with the open mode specifying which standard I/O file to open. This method takes care of these special open requests, and is intended to be used by concrete I/O handler subclasses. + Another special file is the ":semihosting-features" file used for semihosting feature bit + reporting. This method recognised this file name, checks the requested file mode against + allowed modes, and returns `SpecialFile.SEMIHOSTING_FEATURES_FILE` as the file ID. + @return A 2-tuple of the file descriptor and filename. The filename is returned so it only has to be read from target memory once if the request is not for standard I/O. The returned file descriptor may be one of 0, 1, or 2 for the standard I/O files, -1 if an invalid combination was requested, or None if the request was not for a standard I/O file (i.e., the filename was not ":tt"). If None is returned for the file descriptor, the caller must handle the open request. + SpecialFile.SEMIHOSTING_FEATURES_FILE can also be returned as the file ID in case + the special ":semihosting-features" file is opened. + @exception IOError Raised if an invalid file mode is used for a special file. """ + assert self.agent filename = self.agent.get_data(fnptr, fnlen).decode() LOG.debug("Semihost: open '%s' mode %s", filename, mode) @@ -124,36 +148,43 @@ def _std_open(self, fnptr, fnlen, mode): LOG.warning("Unrecognized semihosting console open file combination: mode=%s", mode) return -1, filename return fd, filename + # Semihosting features file, not currently supported. + elif filename == ':semihosting-features': + # All modes other than 'r' and 'rb' must fail. + if mode not in ('r', 'rb'): + raise IOError("attempt to open :semihosting-features with invalid mode " + "(only r and rb are allowed)") + return SpecialFile.SEMIHOSTING_FEATURES_FILE, filename return None, filename - def open(self, fnptr, fnlen, mode): + def open(self, fnptr: int, fnlen: int, mode: str) -> int: raise NotImplementedError() - def close(self, fd): + def close(self, fd: int) -> int: raise NotImplementedError() - def write(self, fd, ptr, length): + def write(self, fd: int, ptr: int, length: int) -> int: raise NotImplementedError() - def read(self, fd, ptr, length): + def read(self, fd: int, ptr: int, length: int) -> int: raise NotImplementedError() - def readc(self): + def readc(self) -> int: raise NotImplementedError() - def istty(self, fd): + def istty(self, fd: int) -> int: raise NotImplementedError() - def seek(self, fd, pos): + def seek(self, fd: int, pos: int) -> int: raise NotImplementedError() - def flen(self, fd): + def flen(self, fd: int) -> int: raise NotImplementedError() - def remove(self, ptr, length): + def remove(self, ptr: int, length: int) -> int: raise NotImplementedError() - def rename(self, oldptr, oldlength, newptr, newlength): + def rename(self, oldptr: int, oldlength: int, newptr: int, newlength: int) -> int: raise NotImplementedError() class InternalSemihostIOHandler(SemihostIOHandler): @@ -165,11 +196,11 @@ class InternalSemihostIOHandler(SemihostIOHandler): """ def __init__(self): - super(InternalSemihostIOHandler, self).__init__() + super().__init__() self.next_fd = STDERR_FD + 1 # Go ahead and connect standard I/O. - self.open_files = { + self.open_files: Dict[int, Union[IO[str], IO[bytes]]] = { STDIN_FD : sys.stdin, STDOUT_FD : sys.stdout, STDERR_FD : sys.stderr @@ -183,26 +214,39 @@ def cleanup(self): f.close() def open(self, fnptr, fnlen, mode): - fd, filename = self._std_open(fnptr, fnlen, mode) - if fd is not None: - return fd + special_fd, filename = self._std_open(fnptr, fnlen, mode) + # if special_fd is not None: + # return special_fd + if (special_fd is not None) and (special_fd is not SpecialFile.SEMIHOSTING_FEATURES_FILE): + return special_fd try: - # ensure directories are exists if mode is write/appened - if ('w' in mode) or ('a' in mode): - pathlib.Path(filename).parent.mkdir(parents=True, exist_ok=True) + # Handle semihosting features. + if special_fd is SpecialFile.SEMIHOSTING_FEATURES_FILE: + # Features bits: + # - Byte 0, bit 0 = 0: SH_EXT_EXIT_EXTENDED, whether SYS_EXIT_EXTENDED is supported + # - Byte 0, bit 1 = 1: SH_EXT_STDOUT_STDERR, whether both stdout and stderr are supported + f = io.BytesIO(b"SHFB\x02") + else: + # Expand user directory. + filepath = pathlib.Path(filename).expanduser() + + # ensure directories are exists if mode is write/appened + if ('w' in mode) or ('a' in mode): + filepath.parent.mkdir(parents=True, exist_ok=True) + + f = io.open(filepath, mode) fd = self.next_fd self.next_fd += 1 - f = io.open(filename, mode) - self.open_files[fd] = f return fd - except IOError as e: + except OSError as e: self._errno = e.errno - LOG.error("Semihost: failed to open file '%s'", filename, exc_info=session.Session.get_current().log_tracebacks) + LOG.error("Semihost: failed to open file '%s'", filename, + exc_info=(self.agent.context.session.log_tracebacks if self.agent else True)) return -1 def close(self, fd): @@ -221,46 +265,51 @@ def write(self, fd, ptr, length): if not self._is_valid_fd(fd): # Return byte count not written. return length + + assert self.agent data = self.agent.get_data(ptr, length) + f = self.open_files[fd] try: - f = self.open_files[fd] if 'b' in f.mode: - data = six.ensure_binary(data) + cast(IO[bytes], f).write(data) else: - data = six.ensure_str(data) - f.write(data) + cast(IO[str], f).write(data.decode(errors='ignore')) f.flush() return 0 - except IOError as e: + except OSError as e: self._errno = e.errno LOG.debug("Semihost: exception: %s", e) return -1 def read(self, fd, ptr, length): + assert self.agent + if not self._is_valid_fd(fd): # Return byte count not read. return length + try: f = self.open_files[fd] data = f.read(length) - if 'b' not in f.mode: - data = data.encode() - except IOError as e: + except OSError as e: self._errno = e.errno LOG.debug("Semihost: exception: %s", e) return -1 - data = bytearray(data) - self.agent.context.write_memory_block8(ptr, data) - return length - len(data) + + if isinstance(data, str): + data = data.encode() + + ba = bytearray(data) + self.agent.context.write_memory_block8(ptr, ba) + return length - len(ba) def readc(self): try: f = self.open_files[STDIN_FD] if f is not None: data = f.read(1) - if 'b' not in f.mode: - data = data.encode() - return data + c = ord(data[0:1]) + return c else: return 0 except OSError as e: @@ -279,16 +328,24 @@ def seek(self, fd, pos): try: self.open_files[fd].seek(pos) return 0 - except IOError as e: + except OSError as e: self._errno = e.errno return -1 def flen(self, fd): if not self._is_valid_fd(fd): return -1 + f = self.open_files[fd] try: - info = os.fstat(self.open_files[fd].fileno()) + info = os.fstat(f.fileno()) return info.st_size + except io.UnsupportedOperation: + # Try seeking to end to get size. + saved_pos = f.tell() + f.seek(0, os.SEEK_END) + size = f.tell() + f.seek(saved_pos, os.SEEK_SET) + return size except OSError as e: self._errno = e.errno return -1 @@ -297,16 +354,18 @@ class ConsoleIOHandler(SemihostIOHandler): """@brief Simple IO handler for console.""" def __init__(self, stdin_file, stdout_file=None): - super(ConsoleIOHandler, self).__init__() + super().__init__() self._stdin_file = stdin_file self._stdout_file = stdout_file or stdin_file def write(self, fd, ptr, length): + assert self.agent data = self.agent.get_data(ptr, length) self._stdout_file.write(data) return 0 def read(self, fd, ptr, length): + assert self.agent data = self._stdin_file.read(length) # Stuff data into provided buffer. @@ -323,12 +382,12 @@ def readc(self): data = self._stdin_file.read(1) if data: - return data[0] + return ord(data) else: return -1 -class SemihostAgent(object): - """@brief Handler for ARM semihosting requests. +class SemihostAgent: + """@brief Handler for Arm semihosting requests. Semihosting requests are made by the target by executing a 'bkpt #0xab' instruction. The requested operation is specified by R0 and any arguments by R1. Many requests use a block @@ -336,14 +395,14 @@ class SemihostAgent(object): in R0. This class does not handle any file-related requests by itself. It uses I/O handler objects - passed in to the constructor. The requests handled directly by this class are #TARGET_SYS_CLOCK - and #TARGET_SYS_TIME. + passed in to the constructor. The requests handled directly by this class are SYS_CLOCK and + SYS_TIME. There are two types of I/O handlers used by this class. The main I/O handler, set with the constructor's @i io_handler parameter, is used for most file operations. You may optionally pass another I/O handler for the @i console constructor parameter. The console handler is used solely for standard I/O and debug console I/O requests. If no console - handler is provided, the main handler is used instead. TARGET_SYS_OPEN requests are not + handler is provided, the main handler is used instead. SYS_OPEN requests are not passed to the console handler in any event, they are always passed to the main handler. If no main I/O handler is provided, the class will use SemihostIOHandler, which causes all @@ -355,21 +414,26 @@ class SemihostAgent(object): numbers for standard I/O open requests (those with a file name of ":tt"). Not all semihosting requests are supported. Those that are not implemented are: - - TARGET_SYS_TMPNAM - - TARGET_SYS_SYSTEM - - TARGET_SYS_GET_CMDLINE - - TARGET_SYS_HEAPINFO - - TARGET_SYS_EXIT - - TARGET_SYS_ELAPSED - - TARGET_SYS_TICKFREQ + - SYS_TMPNAM + - SYS_SYSTEM + - SYS_GET_CMDLINE + - SYS_HEAPINFO + - SYS_EXIT + - SYS_ELAPSED + - SYS_TICKFREQ """ - ## Index into this array is the file open mode argument to TARGET_SYS_OPEN. + ## Index into this array is the file open mode argument to SYS_OPEN. OPEN_MODES = ['r', 'rb', 'r+', 'r+b', 'w', 'wb', 'w+', 'w+b', 'a', 'ab', 'a+', 'a+b'] EPOCH = datetime.datetime(1970, 1, 1) - def __init__(self, context, io_handler=None, console=None): + def __init__( + self, + context: "DebugContext", + io_handler: Optional[SemihostIOHandler] = None, + console: Optional[SemihostIOHandler] = None + ) -> None: self.context = context self.start_time = time.time() self.io_handler = io_handler or SemihostIOHandler() @@ -377,33 +441,7 @@ def __init__(self, context, io_handler=None, console=None): self.console = console or self.io_handler self.console.agent = self - self.request_map = { - TARGET_SYS_OPEN : self.handle_sys_open, - TARGET_SYS_CLOSE : self.handle_sys_close, - TARGET_SYS_WRITEC : self.handle_sys_writec, - TARGET_SYS_WRITE0 : self.handle_sys_write0, - TARGET_SYS_WRITE : self.handle_sys_write, - TARGET_SYS_READ : self.handle_sys_read, - TARGET_SYS_READC : self.handle_sys_readc, - TARGET_SYS_ISERROR : self.handle_sys_iserror, - TARGET_SYS_ISTTY : self.handle_sys_istty, - TARGET_SYS_SEEK : self.handle_sys_seek, - TARGET_SYS_FLEN : self.handle_sys_flen, - TARGET_SYS_TMPNAM : self.handle_sys_tmpnam, - TARGET_SYS_REMOVE : self.handle_sys_remove, - TARGET_SYS_RENAME : self.handle_sys_rename, - TARGET_SYS_CLOCK : self.handle_sys_clock, - TARGET_SYS_TIME : self.handle_sys_time, - TARGET_SYS_SYSTEM : self.handle_sys_system, - TARGET_SYS_ERRNO : self.handle_sys_errno, - TARGET_SYS_GET_CMDLINE : self.handle_sys_get_cmdline, - TARGET_SYS_HEAPINFO : self.handle_sys_heapinfo, - TARGET_SYS_EXIT : self.handle_sys_exit, - TARGET_SYS_ELAPSED : self.handle_sys_elapsed, - TARGET_SYS_TICKFREQ : self.handle_sys_tickfreq - } - - def check_and_handle_semihost_request(self): + def check_and_handle_semihost_request(self) -> bool: """@brief Handle a semihosting request. This method should be called after the target has halted, to check if the halt was @@ -424,8 +462,10 @@ def check_and_handle_semihost_request(self): return False pc = self.context.read_core_register('pc') + assert isinstance(pc, int) # Are we stopped due to one of our own breakpoints? + # TODO check against watchpoints too!? bp = self.context.core.find_breakpoint(pc) if bp: return False @@ -443,18 +483,20 @@ def check_and_handle_semihost_request(self): # Get args op = self.context.read_core_register('r0') args = self.context.read_core_register('r1') + assert isinstance(op, int) + assert isinstance(args, int) # Handle request - handler = self.request_map.get(op, None) + handler = self._REQUEST_MAP.get(op, None) if handler: try: - result = handler(args) + result = handler(self, args) except NotImplementedError: LOG.warning("Semihost: unimplemented request pc=%x r0=%x r1=%x", pc, op, args) result = -1 - except (exceptions.Error, IOError) as e: + except (exceptions.Error, OSError) as e: LOG.error("Error while handling semihost request: %s", e, - exc_info=session.Session.get_current().log_tracebacks) + exc_info=self.context.session.log_tracebacks) result = -1 else: result = -1 @@ -464,7 +506,7 @@ def check_and_handle_semihost_request(self): return True - def cleanup(self): + def cleanup(self) -> None: """@brief Clean up any resources allocated by semihost requests. @note May be called more than once. @@ -473,19 +515,28 @@ def cleanup(self): if self.console is not self.io_handler: self.console.cleanup() - def _get_args(self, args, count): - args = self.context.read_memory_block32(args, count) + @overload + def _get_args(self, args_address: int, count: Literal[1]) -> int: + ... + + @overload + def _get_args(self, args_address: int, count: int) -> List[int]: + ... + + def _get_args(self, args_address: int, count): + args = self.context.read_memory_block32(args_address, count) if count == 1: return args[0] else: return args - def get_data(self, ptr, length=None): + def get_data(self, ptr: int, length: Optional[int] = None) -> bytes: if length is not None: data = self.context.read_memory_block8(ptr, length) return bytes(data) target_data = b'' + data = b'' # TODO - use memory map to make sure we don't try to read off the end of memory # Limit string size in case it isn't terminated. while len(target_data) < MAX_STRING_LENGTH: @@ -507,7 +558,7 @@ def get_data(self, ptr, length=None): ptr += 32 return target_data - def handle_sys_open(self, args): + def handle_sys_open(self, args: int) -> int: fnptr, mode, fnlen = self._get_args(args, 3) if mode >= len(self.OPEN_MODES): return -1 @@ -516,21 +567,21 @@ def handle_sys_open(self, args): TRACE.debug("Semihost: open %x/%x, mode %s", fnptr, fnlen, mode) return self.io_handler.open(fnptr, fnlen, mode) - def handle_sys_close(self, args): + def handle_sys_close(self, args: int) -> int: fd = self._get_args(args, 1) TRACE.debug("Semihost: close fd=%d", fd) return self.io_handler.close(fd) - def handle_sys_writec(self, args): + def handle_sys_writec(self, args: int) -> int: TRACE.debug("Semihost: writec %x", args) return self.console.write(STDOUT_FD, args, 1) - def handle_sys_write0(self, args): + def handle_sys_write0(self, args: int) -> int: msg = self.get_data(args) TRACE.debug("Semihost: write0 msg='%s'", msg) return self.console.write(STDOUT_FD, args, len(msg)) - def handle_sys_write(self, args): + def handle_sys_write(self, args: int) -> int: fd, data_ptr, length = self._get_args(args, 3) TRACE.debug("Semihost: write fd=%d ptr=%x len=%d", fd, data_ptr, length) if fd in (STDOUT_FD, STDERR_FD): @@ -538,7 +589,7 @@ def handle_sys_write(self, args): else: return self.io_handler.write(fd, data_ptr, length) - def handle_sys_read(self, args): + def handle_sys_read(self, args: int) -> int: fd, ptr, length = self._get_args(args, 3) TRACE.debug("Semihost: read fd=%d ptr=%x len=%d", fd, ptr, length) if fd == STDIN_FD: @@ -546,67 +597,127 @@ def handle_sys_read(self, args): else: return self.io_handler.read(fd, ptr, length) - def handle_sys_readc(self, args): + def handle_sys_readc(self, args: int) -> int: TRACE.debug("Semihost: readc") return self.console.readc() - def handle_sys_iserror(self, args): + def handle_sys_iserror(self, args: int) -> int: raise NotImplementedError() - def handle_sys_istty(self, args): + def handle_sys_istty(self, args: int) -> int: fd = self._get_args(args, 1) TRACE.debug("Semihost: istty fd=%d", fd) return self.io_handler.istty(fd) - def handle_sys_seek(self, args): + def handle_sys_seek(self, args: int) -> int: fd, pos = self._get_args(args, 2) TRACE.debug("Semihost: seek fd=%d pos=%d", fd, pos) return self.io_handler.seek(fd, pos) - def handle_sys_flen(self, args): + def handle_sys_flen(self, args: int) -> int: fd = self._get_args(args, 1) TRACE.debug("Semihost: flen fd=%d", fd) return self.io_handler.flen(fd) - def handle_sys_tmpnam(self, args): + def handle_sys_tmpnam(self, args: int) -> int: raise NotImplementedError() - def handle_sys_remove(self, args): + def handle_sys_remove(self, args: int) -> int: ptr, length = self._get_args(args, 2) return self.io_handler.remove(ptr, length) - def handle_sys_rename(self, args): + def handle_sys_rename(self, args: int) -> int: oldptr, oldlength, newptr, newlength = self._get_args(args, 4) return self.io_handler.rename(oldptr, oldlength, newptr, newlength) - def handle_sys_clock(self, args): + def handle_sys_clock(self, args: int) -> int: now = time.time() delta = now - self.start_time return int(delta * 100) - def handle_sys_time(self, args): + def handle_sys_time(self, args: int) -> int: now = datetime.datetime.now() delta = now - self.EPOCH seconds = (delta.days * 86400) + delta.seconds return seconds - def handle_sys_system(self, args): + def handle_sys_system(self, args: int) -> int: raise NotImplementedError() - def handle_sys_errno(self, args): + def handle_sys_errno(self, args: int) -> int: return self.io_handler.errno - def handle_sys_get_cmdline(self, args): - raise NotImplementedError() + def handle_sys_get_cmdline(self, args: int) -> int: + cmdline = cast(str, self.context.session.options.get('semihost.commandline')) + if not cmdline: + return -1 - def handle_sys_heapinfo(self, args): + ptr, length = self._get_args(args, 2) + cmdline_write_length = min(length - 1, len(cmdline)) # Ensure room for null byte. + cmdline_bytes = cmdline.encode()[:cmdline_write_length] + b'\x00' + self.context.write_memory_block8(ptr, cmdline_bytes) + self.context.write32(args + 4, cmdline_write_length - 1) # TODO resume assumption about pointer size! + return 0 + + def handle_sys_heapinfo(self, args: int) -> int: + """@brief Stub implementation of SYS_HEAPINFO. + + The args (r1) value is the address of a pointer to a four-word data block, to be filled in + by the host. + + ```c + struct block { + int heap_base; + int heap_limit; + int stack_base; + int stack_limit; + }; + ``` + + This implementation simply fills in the value 0 for each field. Zero is legal, and tells the + caller that the host was unable to determine the value. + """ + info_block = self._get_args(args, 1) + self.context.write_memory_block32(info_block, [0, 0, 0, 0]) + return 0 + + def handle_sys_exit(self, args: int) -> int: + # TODO handle SYS_EXIT for a 'pyocd run' subcommand raise NotImplementedError() - def handle_sys_exit(self, args): + def handle_sys_exit_extended(self, args: int) -> int: raise NotImplementedError() - def handle_sys_elapsed(self, args): + def handle_sys_elapsed(self, args: int) -> int: raise NotImplementedError() - def handle_sys_tickfreq(self, args): + def handle_sys_tickfreq(self, args: int) -> int: raise NotImplementedError() + + _REQUEST_MAP: Dict[int, Callable[["SemihostAgent", int], int]] = { + SemihostingRequests.SYS_OPEN: handle_sys_open, + SemihostingRequests.SYS_CLOSE: handle_sys_close, + SemihostingRequests.SYS_WRITEC: handle_sys_writec, + SemihostingRequests.SYS_WRITE0: handle_sys_write0, + SemihostingRequests.SYS_WRITE: handle_sys_write, + SemihostingRequests.SYS_READ: handle_sys_read, + SemihostingRequests.SYS_READC: handle_sys_readc, + SemihostingRequests.SYS_ISERROR: handle_sys_iserror, + SemihostingRequests.SYS_ISTTY: handle_sys_istty, + SemihostingRequests.SYS_SEEK: handle_sys_seek, + SemihostingRequests.SYS_FLEN: handle_sys_flen, + SemihostingRequests.SYS_TMPNAM: handle_sys_tmpnam, + SemihostingRequests.SYS_REMOVE: handle_sys_remove, + SemihostingRequests.SYS_RENAME: handle_sys_rename, + SemihostingRequests.SYS_CLOCK: handle_sys_clock, + SemihostingRequests.SYS_TIME: handle_sys_time, + SemihostingRequests.SYS_SYSTEM: handle_sys_system, + SemihostingRequests.SYS_ERRNO: handle_sys_errno, + SemihostingRequests.SYS_GET_CMDLINE: handle_sys_get_cmdline, + SemihostingRequests.SYS_HEAPINFO: handle_sys_heapinfo, + SemihostingRequests.SYS_EXIT: handle_sys_exit, + SemihostingRequests.SYS_EXIT_EXTENDED: handle_sys_exit_extended, + SemihostingRequests.SYS_ELAPSED: handle_sys_elapsed, + SemihostingRequests.SYS_TICKFREQ: handle_sys_tickfreq + } + diff --git a/pyocd/debug/sequences/__init__.py b/pyocd/debug/sequences/__init__.py new file mode 100644 index 000000000..06b0e6153 --- /dev/null +++ b/pyocd/debug/sequences/__init__.py @@ -0,0 +1,15 @@ +# pyOCD debugger +# Copyright (c) 2021 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. diff --git a/pyocd/debug/sequences/delegates.py b/pyocd/debug/sequences/delegates.py new file mode 100644 index 000000000..167a34110 --- /dev/null +++ b/pyocd/debug/sequences/delegates.py @@ -0,0 +1,118 @@ +# pyOCD debugger +# Copyright (c) 2021-2022 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from __future__ import annotations + +import logging +from typing import (TYPE_CHECKING, Optional, Set) + +from .scope import Scope + +LOG = logging.getLogger(__name__) + +if TYPE_CHECKING: + from .sequences import (DebugSequence, DebugSequenceExecutionContext) + from ...target.pack.cmsis_pack import CmsisPackDevice + +class DebugSequenceDelegate: + """@brief Delegate interface for handling sequence operations.""" + + @property + def all_sequences(self) -> Set[DebugSequence]: + """@brief Returns a set containing all defined debug sequence objects.""" + raise NotImplementedError() + + @property + def cmsis_pack_device(self) -> CmsisPackDevice: + """@brief Accessor for the pack device that contains the sequences.""" + raise NotImplementedError() + + def get_root_scope(self, context: DebugSequenceExecutionContext) -> Scope: + """@brief Return a scope that will be used as the parent of sequences. + + Normally the delegate will return the debugvars scope from this method. It's also possible to + simply return an empty scope. + """ + raise NotImplementedError() + + def run_sequence(self, name: str, pname: Optional[str] = None) -> Optional[Scope]: + """@brief Execute the debug sequence with the specified name. + @exception NameError No sequence with the given name is defined. + """ + raise NotImplementedError() + + def has_sequence_with_name(self, name: str, pname: Optional[str] = None) -> bool: + """@brief Return whether there is a debug sequence with the specified name.""" + raise NotImplementedError() + + def get_sequence_with_name(self, name: str, pname: Optional[str] = None) -> DebugSequence: + """@brief Return the named debug sequence object. + + Expected to raise if the sequence isn't available. + """ + raise NotImplementedError() + + def get_protocol(self) -> int: + """@brief Return the value for the __protocol variable. + __protocol fields: + - [15:0] 0=error, 1=JTAG, 2=SWD, 3=cJTAG + - [16] SWJ-DP present? + - [17] switch through dormant state? + """ + raise NotImplementedError() + + def get_connection_type(self) -> int: + """@brief Return the value for the __connection variable. + __connection fields: + - [7:0] connection type: 0=error/disconnected, 1=for debug, 2=for flashing + - [15:8] reset type: 0=error, 1=hw, 2=SYSRESETREQ, 3=VECTRESET + - [16] connect under reset? + - [17] pre-connect reset? + """ + raise NotImplementedError() + + def get_traceout(self) -> int: + """@brief Return the value for the __traceout variable. + __traceout fields: + - [0] SWO enabled? + - [1] parallel trace enabled? + - [2] trace buffer enabled? + - [21:16] selected parallel trace port size + """ + raise NotImplementedError() + + def get_sequence_functions(self) -> DebugSequenceFunctionsDelegate: + """@brief Return an instance of the sequence function implementations delegate. + + This method lets the delegate determine the set of built-in sequence functions. + """ + raise NotImplementedError() + +class DebugSequenceFunctionsDelegate: + """@brief Implements functions provided by the debug sequence environment. + + All defined functions must have type annotations. Any function that has a fixed return value of 0 + should return None. This will be converted to 0 by the interpreter. + + The function names must be all lower-case in order to support case-insensitive symbol lookup. + Whether this is actually correct debug sequence behaviour is unknown since it's not documented + in the Open-CMSIS-Pack specification (version 1.7.15) as of late December 2022. + """ + + @property + def context(self) -> DebugSequenceExecutionContext: + from .sequences import DebugSequenceExecutionContext + return DebugSequenceExecutionContext.get_active_context() diff --git a/pyocd/debug/sequences/functions.py b/pyocd/debug/sequences/functions.py new file mode 100644 index 000000000..b3d93db90 --- /dev/null +++ b/pyocd/debug/sequences/functions.py @@ -0,0 +1,416 @@ +# pyOCD debugger +# Copyright (c) 2021-2022 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from __future__ import annotations + +import logging +from time import sleep +from typing import (cast, Dict, TYPE_CHECKING) + +from ...core import exceptions +from ...coresight.coresight_target import CoreSightTarget +from ...coresight.ap import (APAddressBase, APv1Address, AccessPort, MEM_AP) +from ...probe.debug_probe import DebugProbe +from .delegates import DebugSequenceFunctionsDelegate +from .sequences import DebugSequenceRuntimeError + +if TYPE_CHECKING: + from ...coresight.dap import DebugPort + +LOG = logging.getLogger(__name__) + +# Disable warnings for the non-standard methods names we use to match the sequences function +# names, since introspection is used to look up functions. +# pylint: disable=invalid_name + +class DebugSequenceCommonFunctions(DebugSequenceFunctionsDelegate): + """@brief Implements functions provided by the debug sequence environment.""" + + APSEL_SHIFT = 24 + + DP_ABORT = 0x00 + + def __init__(self) -> None: + self._ap_cache: Dict[APAddressBase, MEM_AP] = {} + + @property + def target(self) -> CoreSightTarget: + return cast(CoreSightTarget, self.context.session.target) + + def _get_ap_addr(self) -> APAddressBase: + """@brief Return the AP address selected by __ap or __apid variables. + + If the DFP uses apids then the `__apid` variable takes precedence. Otherwise the `__ap` variable + is used. + """ + pack_device = self.context.delegate.cmsis_pack_device + + if pack_device.uses_apid: + apid = self.context.get_variable('__apid') + try: + ap_addr = pack_device.apid_map[apid] + except KeyError: + raise DebugSequenceRuntimeError(f"__apid has invalid value ({apid})") + else: + # The __ap variable is only used to reference v1 APs. + # TODO handle __dp being non-zero, when we support multiple DPs. + ap_addr = APv1Address(self.context.get_variable('__ap')) + + dp_num = self.context.get_variable('__dp') + if dp_num != 0: + raise DebugSequenceRuntimeError(f"currently only __dp==0 is supported ({dp_num} specified)") + + return ap_addr + + def _get_mem_ap(self) -> MEM_AP: + """@brief Return the current MEM_AP object. + + Normally, the AP object created during discovery is returned from the target's dict of APs. However, + sequences can be run prior to discovery, and are allowed to perform memory acceses. Therefore we must + handle the case of there not being a readily available AP object by creating a temporary one here. + + A cache dict is used to prevent repeatedly recreating the same AP when multiple memory transfers + appear in a sequence. The cache is _only_ used for temporary AP objects; the target's AP dict always + takes priority and is checked first. + """ + ap_addr = self._get_ap_addr() + + # Try to get an existing AP from the target. + try: + ap = self.target.aps[ap_addr] + if not isinstance(ap, MEM_AP): + raise DebugSequenceRuntimeError(f"AP at address {ap_addr} is not a MEM-AP") + return ap + except KeyError: + pass + + # The AP doesn't exist or we haven't performed discovery yet, but we still need to support memory + # transfers for debug sequences. So attempt to create a temporary one. + # TODO can this only be done prior to discovery? + + # Check if we have already created and cached this AP. + try: + return self._ap_cache[ap_addr] + except KeyError: + pass + + # Haven't encountered this AP yet. Create and cache it. + # This call will raise exceptions.TargetError if there is no AP with the requested address. + ap = AccessPort.create(self.target.dp, ap_addr) + + # Make sure this is a MEM-AP. + if not isinstance(ap, MEM_AP): + raise DebugSequenceRuntimeError(f"AP at address {ap_addr} is not a MEM-AP") + + # Save in the cache. + self._ap_cache[ap_addr] = ap + + return ap + + def _get_dp(self, ignore_apid: bool = False) -> DebugPort: + """@brief Get the DebugPort object specified by the __dp or __apid variable.""" + pack_device = self.context.delegate.cmsis_pack_device + if not pack_device.uses_apid or ignore_apid: + dp_num = self.context.get_variable('__dp') + else: + apid = self.context.get_variable('__apid') + try: + ap_addr = pack_device.apid_map[apid] + except KeyError: + raise DebugSequenceRuntimeError(f"__apid has invalid value ({apid})") + else: + dp_num = ap_addr.dp_index + + if dp_num != 0: + raise DebugSequenceRuntimeError(f"currently only __dp==0 is supported ({dp_num} specified)") + + # In any case, for now we always return the only DebugPort object we have. + return self.target.dp + + def _get_ignore_errors(self) -> bool: + """@brief Whether the debug sequence has set __errorcontrol to ignore faults.""" + errcontrol = self.context.get_variable('__errorcontrol') + return (errcontrol & 1) == 1 + + def sequence(self, name: str) -> None: + # This call will raise if the named sequence is invalid. However, we should have already + # verified the sequence name is valid during semantic checking. + # + # The pname from the current context is passed in order to match a pname-specific + # sequence; a matching sequence with no pname will also be found. + seq = self.context.delegate.get_sequence_with_name(name, pname=self.context.pname) + + if self.context.pname: + LOG.debug("Running debug sub-sequence '%s' (%s)", name, self.context.pname) + else: + LOG.debug("Running debug sub-sequence '%s'", name) + + # Run the sequence. + subsequence_scope = seq.execute(self.context) + + # Copy the result to parent sequence. + if subsequence_scope is not None: + result_value = subsequence_scope.get('__Result') + LOG.debug("Sub-sequence '%s' result = %d", name, result_value) + self.context.current_scope.set('__Result', result_value) + + def read8(self, addr: int) -> int: + try: + return self._get_mem_ap().read8(addr) + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Read8(%#010x) ignored %r because __errorcontrol is set", addr, err) + return 0 + else: + raise + + def read16(self, addr: int) -> int: + try: + return self._get_mem_ap().read16(addr) + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Read16(%#010x) ignored %r because __errorcontrol is set", addr, err) + return 0 + else: + raise + + def read32(self, addr: int) -> int: + try: + return self._get_mem_ap().read32(addr) + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Read32(%#010x) ignored %r because __errorcontrol is set", addr, err) + return 0 + else: + raise + + def read64(self, addr: int) -> int: + try: + return self._get_mem_ap().read64(addr) + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Read64(%#010x) ignored %r because __errorcontrol is set", addr, err) + return 0 + else: + raise + + def readap(self, addr: int) -> int: + try: + ap_addr = self._get_ap_addr() + reg_addr = ap_addr.address | addr + return self._get_dp().read_ap(reg_addr) + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("ReadAP(%#010x) ignored %r because __errorcontrol is set", addr, err) + return 0 + else: + raise + + def readaccessap(self, addr: int) -> int: + try: + dp = self._get_dp(True) + apacc = dp.apacc_memory_interface + return apacc.read32(addr) + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("ReadAccessAP(%#010x) ignored %r because __errorcontrol is set", addr, err) + return 0 + else: + raise + + def readdp(self, addr: int) -> int: + try: + return self._get_dp(True).read_dp(addr) + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("ReadDP(%#010x) ignored %r because __errorcontrol is set", addr, err) + return 0 + else: + raise + + def write8(self, addr: int, val: int) -> None: + try: + self._get_mem_ap().write8(addr, val) + self.target.flush() + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Write8(%#010x) ignored %r because __errorcontrol is set", addr, err) + else: + raise + + def write16(self, addr: int, val: int) -> None: + try: + self._get_mem_ap().write16(addr, val) + self.target.flush() + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Write16(%#010x) ignored %r because __errorcontrol is set", addr, err) + else: + raise + + def write32(self, addr: int, val: int) -> None: + try: + self._get_mem_ap().write32(addr, val) + self.target.flush() + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Write32(%#010x) ignored %r because __errorcontrol is set", addr, err) + else: + raise + + def write64(self, addr: int, val: int) -> None: + try: + self._get_mem_ap().write64(addr, val) + self.target.flush() + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("Write64(%#010x) ignored %r because __errorcontrol is set", addr, err) + else: + raise + + def writeap(self, addr: int, val: int) -> None: + try: + ap_addr = self._get_ap_addr() + reg_addr = ap_addr.address | addr + self._get_dp().write_ap(reg_addr, val) + self.target.flush() + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("WriteAP(%#010x) ignored %r because __errorcontrol is set", addr, err) + else: + raise + + def writeaccessap(self, addr: int, val: int) -> None: + try: + dp = self._get_dp(True) + apacc = dp.apacc_memory_interface + apacc.write32(addr, val) + self.target.flush() + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("WriteAccessAP(%#010x) ignored %r because __errorcontrol is set", addr, err) + else: + raise + + def writedp(self, addr: int, val: int) -> None: + try: + self._get_dp(True).write_dp(addr, val) + self.target.flush() + except exceptions.TransferError as err: + if self._get_ignore_errors(): + LOG.debug("WriteDP(%#010x) ignored %r because __errorcontrol is set", addr, err) + else: + raise + + def flashbufferwrite(self, addr: int, offset: int, length: int, mode: int) -> None: + raise NotImplementedError() + + def dap_delay(self, delay: int) -> None: + # Flush before sleeping, in case there are any outstanding transactions. + self.target.flush() + + # TODO This is really expected to be sent to the target via the CMSIS-DAP command, but for most + # cases this will work fine. However, it would fail for atomic sequences. + sleep(delay / 1e6) + + def dap_writeabort(self, value: int) -> None: + assert self.context.session.probe + mode = self.context.session.probe.wire_protocol + if mode == DebugProbe.Protocol.SWD: + self._get_dp().write_reg(self.DP_ABORT, value) + elif mode == DebugProbe.Protocol.JTAG: + # TODO support jtag abort + self._get_dp().write_reg(self.DP_ABORT, value) + self.target.flush() + + def dap_swj_pins(self, pinout: int, pinselect: int, pinwait: int) -> int: + """ + Pin bits: + - Bit 0: SWCLK/TCK + - Bit 1: SWDIO/TMS + - Bit 2: TDI + - Bit 3: TDO + - Bit 5: nTRST + - Bit 7: nRESET + + Must return 0xFFFFFFFF if the pins cannot be read. + """ + from ...probe.cmsis_dap_probe import CMSISDAPProbe + + probe = self.context.session.probe + assert probe + if DebugProbe.Capability.PIN_ACCESS not in probe.capabilities: + return 0xFFFFFFFF + + # Write pins if any were selected to be modified, wait if needed, then read + # all available pins. + if pinselect != 0: + probe.write_pins(DebugProbe.PinGroup.PROTOCOL_PINS, + CMSISDAPProbe.from_cmsis_dap_pins(pinselect), + CMSISDAPProbe.from_cmsis_dap_pins(pinout)) + if pinwait > 0: + sleep(pinwait / 1e9) + result = CMSISDAPProbe.to_cmsis_dap_pins( + probe.read_pins(DebugProbe.PinGroup.PROTOCOL_PINS, + DebugProbe.ProtocolPin.ALL_PINS)) + + return result + + def dap_swj_clock(self, val: int) -> None: + assert self.context.session.probe + self.context.session.probe.set_clock(val) + + def dap_swj_sequence(self, cnt: int, val: int) -> None: + probe = self.context.session.probe + assert probe + if DebugProbe.Capability.SWJ_SEQUENCE not in probe.capabilities: + raise DebugSequenceRuntimeError( + "debug sequence called DAP_SWJ_Sequence, but debug probe does not support this operation") + probe.swj_sequence(cnt, val) + + def dap_jtag_sequence(self, cnt: int, tms: int, tdi: int) -> int: + probe = self.context.session.probe + assert probe + if DebugProbe.Capability.JTAG_SEQUENCE not in probe.capabilities: + raise DebugSequenceRuntimeError( + "debug sequence called DAP_JTAG_Sequence, but debug probe does not support this operation") + tdo = probe.jtag_sequence(cnt, tms, True, tdi) + return tdo or 0 + + def query(self, type: int, message: str, default: int) -> int: + LOG.info(f"Query({type}): {message} [{default}]") + # Just return the default value since we're running in "batch" mode. + return default + + def queryvalue(self, message: str, default: int) -> int: + LOG.info(f"QueryValue: {message} [{default}]") + # Just return the default value since we're running in "batch" mode. + return default + + _MESSAGE_LEVEL_MAP = { + 0: logging.INFO, + 1: logging.WARNING, + 2: logging.ERROR, + } + def message(self, type: int, format: str, *args: int) -> None: + level = self._MESSAGE_LEVEL_MAP.get(type, 2) # default to error for invalid type + LOG.log(level, format % args) + + def loaddebuginfo(self, file: str) -> int: + # Return 1 to indicate failure. + return 1 + +# pylint: enable=invalid_name diff --git a/pyocd/debug/sequences/scope.py b/pyocd/debug/sequences/scope.py new file mode 100644 index 000000000..54561bb96 --- /dev/null +++ b/pyocd/debug/sequences/scope.py @@ -0,0 +1,190 @@ +# pyOCD debugger +# Copyright (c) 2020 Arm Limited +# Copyright (c) 2021-2022 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from __future__ import annotations + +import logging +from typing import (Dict, Iterable, Optional, Set) + +LOG = logging.getLogger(__name__) +TRACE = LOG.getChild("trace") +TRACE.setLevel(logging.CRITICAL) + +class Scope: + """@brief Debug sequence execution scope. + + Scopes have both a link to a parent scope. The former is used to read regular variables defined in + super-scopes. Writing a variable always sets it in the scope to in which it was defined, unless the + variable hasn't been set before in which case it is set in the scope that was called. + """ + + def __init__( + self, + parent: Optional["Scope"] = None, + name: str = "" + ) -> None: + """@brief Constructor. + @param self The Scope object. + @param parent Optional parent scope reference. If not provided or set to None, the new scope + becomes a root. + @param specials Optional specials scope reference. If not provided or set to None, and a + parent was provided, then the specials scope from the parent is used. + @param name Optional name for the scope. + """ + self._name = name + self._parent = parent + self._variables: Dict[str, int] = {} # Map from name: value. + # A variable is read-only if its name is in this set. Start off with + self._ro_variables: Set[str] = set() + + @property + def name(self) -> str: + """@brief The scope's name.""" + return self._name + + @property + def parent(self) -> Optional[Scope]: + """@brief Parent scope. + + The parent of the root scope is None. + """ + return self._parent + + @property + def variables(self) -> Set[str]: + """@brief Set of the names of all variables defined in this scope. + + Does not include any variables from parent scopes. + """ + return set(self._variables.keys()) + + def get(self, name: str) -> int: + """@brief Read a variable.""" + try: + value = self._variables[name] + except KeyError: + if self._parent is not None: + value = self._parent.get(name) + else: + raise + TRACE.debug("get '%s' -> 0x%016x", name, value) + return value + + def set(self, name: str, value: int, readonly: bool = False) -> None: + """@brief Write a variable. + + The variable is set in the scope in which it is defined (following the parent links). The first + time a variable is set, it can be marked as read-only via the `readonly` parameter. + + @param self + @param name Name of the variable. + @param value Integer value of the variable. Limited to 64-bit. + @param readonly If the variable has not been previously defined, this parameter determines if it + is writable. Primarily used for debugvars and other predefined variables. + """ + TRACE.debug("set '%s' <- 0x%016x", name, value) + + # Catch attempt to rewrite a read-only variable. + if self.is_read_only(name): + raise RuntimeError("attempt to modify read-only variable '%s'" % name) + + scope = self + while scope is not None: + if name in scope._variables: + # Found a scope with the variable definition. + scope._variables[name] = value + return + scope = scope.parent + + # An existing definition of the variable wasn't found, so add it to the this scope. + self._variables[name] = value + if readonly: + self._ro_variables.add(name) + + def copy_variables(self, from_scope: Scope, variables: Iterable[str]) -> None: + """@brief Copy a set of variables from another scope into this one. + + @param self + @param from_scope Scope to copy from. This scope must not be connected via parent links to the + called scope, or the behaviour is undefined. + @param variables Iterable of variable names which will be copied. If a variable is not defined + in the `from_scope`, it will not be copied. + """ + for name in variables: + if from_scope.is_defined(name): + self.set(name, from_scope.get(name)) + + def is_defined(self, name: str, recurse_parents: bool = True) -> bool: + """@brief Returns whether a variable has been set in this or any linked scope. + + @param self + @param name Name of the variable to query. + @param recurse_parents Whether parent scopes should also be queried if this scope doesn't contain the specified + variable. + @return Boolean of whether the named variable has been defined. + """ + if name in self._variables: + return True + elif recurse_parents and (self._parent is not None): + return self._parent.is_defined(name, recurse_parents) + else: + return False + + def freeze(self) -> None: + """@brief Make all variables defined in the scope read-only.""" + self._ro_variables = set(self._variables.keys()) + + def is_read_only(self, name: str) -> bool: + """@brief Returns a boolean for whether the named variable is read-only. + + First checks the called scope. If the variable isn't found to be read-only, it asks the + parent. Thus, once a variable is marked as read-only, it remains read-only in all child + scopes. + """ + if name in self._ro_variables: + return True + elif self.parent is not None: + return self.parent.is_read_only(name) + else: + return False + + def _build_dump(self, indent: str) -> str: + """@brief Construct a scope dump with a given ident level.""" + s = f"<{type(self).__name__}@{id(self):x} {self.name}\n" + if self.parent: + parent_str = self.parent._build_dump(indent + ' ') + else: + parent_str = "None" + s += f"{indent}parent={parent_str}\n" + s += f"{indent}variables=[\n" + for n, v in self._variables.items(): + s += f"{indent} '{n}'={v:#x} {'(RO)' if n in self._ro_variables else '(RW)'}\n" + s += f"{indent}]>" + return s + + def dump(self) -> str: + """@brief Return a string detailing the scope, its parents, and all variable values.""" + return self._build_dump(indent=" ") + + def __len__(self) -> int: + """@brief Return the number of variables in this scope (not including parents).""" + return len(self._variables) + + def __repr__(self) -> str: + """@brief Shortened representation of the scope without variable values.""" + return f"<{type(self).__name__}@{id(self):x} {self.name} "\ + f"parent={self._parent!r} [{', '.join(self._variables.keys())}]>" diff --git a/pyocd/debug/sequences/sequences.lark b/pyocd/debug/sequences/sequences.lark new file mode 100644 index 000000000..51e71c38f --- /dev/null +++ b/pyocd/debug/sequences/sequences.lark @@ -0,0 +1,126 @@ +// Lark grammar for debug sequence expressions +// +// Copyright (c) 2020-2021 Chris Reed +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Precedence from high to low: +// 1. function call, parentheses +// 2. unary ! ~ +// 3. * / % +// 4. + - +// 5. << >> +// 6. < <= > >= +// 7. == != +// 8. & +// 9. ^ +// 10. | +// 11. && +// 12. || +// 13. ?: + +start: statement* + +?statement: decl_stmt ";"? + | assign_stmt ";"? + | expr_stmt ";"? + +// Allow __var declarations with no initialiser expression even though this is disallowed +// by the specification, for greater compatibility. +decl_stmt: "__var" IDENT ["=" expr] + +assign_stmt: IDENT _compound_assign_op expr + +// This creates a tree node for expression statements that is easy to identify. +expr_stmt: expr + +?expr: logical_or_expr + | ternary_expr + | STRLIT + +ternary_expr: expr "?" expr ":" expr + +?logical_or_expr: logical_and_expr + | logical_or_expr _logor_op logical_and_expr -> binary_expr + +?logical_and_expr: bitwise_or_expr + | logical_and_expr _logand_op bitwise_or_expr -> binary_expr + +?bitwise_or_expr: bitwise_xor_expr + | bitwise_or_expr _bitor_op bitwise_xor_expr -> binary_expr + +?bitwise_xor_expr: bitwise_and_expr + | bitwise_xor_expr _bitxor_op bitwise_and_expr -> binary_expr + +?bitwise_and_expr: equality_expr + | bitwise_and_expr _bitand_op equality_expr -> binary_expr + +?equality_expr: relational_expr + | equality_expr _eq_op relational_expr -> binary_expr + +?relational_expr: bitwise_shift_expr + | relational_expr _compare_op bitwise_shift_expr -> binary_expr + +?bitwise_shift_expr: add_expr + | bitwise_shift_expr _shift_op add_expr -> binary_expr + +?add_expr: multiply_expr + | add_expr _add_op multiply_expr -> binary_expr + +?multiply_expr: atom + | multiply_expr _mul_op atom -> binary_expr + +?atom: IDENT + | INTLIT + | fncall + | "(" expr ")" + | unary_expr + +unary_expr: _unary_op atom + +fncall: IDENT "(" ")" + | IDENT "(" expr ( "," expr )* ")" + +// The ! prefix forces all literals to be included in the tree. +// Underscore prefix merges the rule into its parent. +!_logor_op: "||" +!_logand_op: "&&" +!_bitor_op: "|" +!_bitxor_op: "^" +!_bitand_op: "&" +!_eq_op: "==" | "!=" +!_shift_op: "<<" | ">>" +!_compare_op: "<=" | "<" | ">=" | ">" +!_add_op: "+" | "-" +!_mul_op: "*" | "/" | "%" +!_unary_op: "!" | "~" | "-" | "+" +!_compound_assign_op: "+=" | "-=" | "*=" | "/=" | "%=" | "&=" | "|=" | "^=" | "<<=" | ">>=" | "=" + +BINDIGIT: "0".."1" +INTLIT: "0x" HEXDIGIT+ | "0b" BINDIGIT+ | DIGIT+ + +STRLIT: ESCAPED_STRING + +IDENT: CNAME + +COMMENT: /\s*/ "//" /[^\n]*/ + +%import common.DIGIT +%import common.HEXDIGIT +%import common.ESCAPED_STRING +%import common.WS +%import common.CNAME + +%ignore WS +%ignore COMMENT diff --git a/pyocd/debug/sequences/sequences.py b/pyocd/debug/sequences/sequences.py new file mode 100644 index 000000000..06e8a25f8 --- /dev/null +++ b/pyocd/debug/sequences/sequences.py @@ -0,0 +1,991 @@ +# pyOCD debugger +# Copyright (c) 2020 Arm Limited +# Copyright (c) 2021-2022 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from __future__ import annotations + +from contextlib import contextmanager +import lark.lark +import lark.exceptions +import lark.visitors +import logging +import threading +from dataclasses import dataclass +from enum import Enum +from inspect import signature +from lark.lexer import Token as LarkToken +from lark.tree import Tree as LarkTree +from typing import (Any, Iterator, cast, List, Optional, Union, TYPE_CHECKING) +from typing_extensions import Self + +from ...core import exceptions +from ...coresight.ap import (APv1Address, APv2Address) +from ...utility.graph import GraphNode +from ...utility.mask import bit_invert +from ...utility.timeout import Timeout +from .scope import Scope + +if TYPE_CHECKING: + # Only import Session when type checking to avoid complex import cycles. + from ...core.session import Session + from ...coresight.ap import APAddressBase + from .delegates import DebugSequenceDelegate + +LOG = logging.getLogger(__name__) +TRACE = LOG.getChild("trace") +TRACE.setLevel(logging.CRITICAL) + +NodeType = Union[LarkTree, LarkToken, int] + +class DebugSequenceError(exceptions.Error): + pass + +class DebugSequenceSemanticError(DebugSequenceError): + pass + +class DebugSequenceRuntimeError(exceptions.Error): + pass + +def _is_token(tok: Any, typename: str) -> bool: + """@brief Test whether a node is a specific type of token.""" + return isinstance(tok, LarkToken) and tok.type == typename + +class _ConvertLiterals(lark.visitors.Transformer): + """@brief Transformer to convert integer literal tokens to integers. + + Running this transformer during the parse is more efficient than handling it post-parse + such as during optimization. + """ + def INTLIT(self, tok: LarkToken) -> int: # pylint: disable=invalid-name + return int(tok.value, base=0) + + def STRLIT(self, tok: LarkToken) -> LarkToken: + tok.value = tok.value.strip('"') + return tok + +class Parser: + """@brief Debug sequence statement parser.""" + + ## Shared parser object. + _parser = lark.lark.Lark.open("sequences.lark", + rel_to=__file__, + parser="lalr", + maybe_placeholders=True, + propagate_positions=True, + transformer=_ConvertLiterals()) + + @classmethod + def parse(cls, data: str) -> LarkTree: + try: + # Parse the input. + tree = cls._parser.parse(data) + + # Return the resulting tree. + return tree + except lark.exceptions.UnexpectedInput as e: + message = str(e) + "\n\nContext: " + e.get_context(data, 40) + raise exceptions.Error(message) from e + +class DebugSequenceExecutionContext: + """@brief Context for running debug sequences. + + Instances of this class contain state for running a call stack of sequences. There is a stack + of sequence node and scope pairs. This stack is also used to get the current running sequence. + + Context objects can be used as context managers, which will set the context as the current + thread's active context. The class method get_active_context() returns the currently active + context for the current thread. There is no stack of active contexts; the assumption is that + only one call stack of debug sequences can be run at any time on a given thread. + """ + + _thread_local_contexts = threading.local() + + @dataclass + class _NodeScopeStackItem: + node: DebugSequenceNode + scope: Scope + + @classmethod + def get_active_context(cls) -> DebugSequenceExecutionContext: + """@brief Return the active context for the current thread. + @exception AttributeError There is no active context for this thread. + """ + return cls._thread_local_contexts.context + + def __init__(self, session: Session, delegate: DebugSequenceDelegate, pname: Optional[str]) -> None: + """@brief Constructor. + + @param self + @param session Session for the target connection. + @param delegate Debug sequence delegate that owns the running sequences. + @param pname Pname under which sequences are being run. + """ + self._session = session + self._delegate = delegate + self._default_ap_address = APv1Address(0) + self._pname = pname + self._stack: List[DebugSequenceExecutionContext._NodeScopeStackItem] = [] + + @property + def session(self) -> Session: + return self._session + + @property + def delegate(self) -> DebugSequenceDelegate: + return self._delegate + + @property + def default_ap(self) -> APAddressBase: + """@brief Return the AP address from which the __ap and __apid variables should be inited. + + The initial AP address is the one defined for the element corresponding to the active + processor. + + This is contained in the context rather than returned by the sequence delegate because it can + differ for each execution of a debug sequence. Compare with the delegate methods for getting + `__protocol`, `__connection`, and `__traceout`, which should be static for an entire session. + """ + return self._default_ap_address + + @default_ap.setter + def default_ap(self, address: APAddressBase) -> None: + """@brief Set the default AP adddress.""" + self._default_ap_address = address + + @property + def pname(self) -> Optional[str]: + """@brief Pname for which sequences are executing in this context. + + The Pname for this context is set when the context is created. + Only debug sequences with this Pname or an empty Pname can be run in this context. + """ + return self._pname + + @property + def current_scope(self) -> Scope: + """@brief Topmost scope of the scope stack. + @exception AssertionError Raised if an attempt is made to get the current scope without a + currently running debug sequence. If needed, this can be checked before accessing this + property by getting the `.has_current_sequence` property. + """ + assert self._stack, "current_scope accessed from outside a running sequence" + return self._stack[-1].scope + + @property + def has_current_sequence(self) -> bool: + """@brief Whether there is a debug sequence running on this context. + + By definition, there must be a debug sequence on the stack if the stack is not empty, + with one exception for when the debugvars block is run to create the the root scope. + """ + return bool(self._stack) + + @property + def current_sequence(self) -> DebugSequence: + """@brief Currently executing debug sequence.""" + assert self._stack, "current_sequence accessed without a running debug sequence" + + # Walk the stack to find the most recent DebugSequence. + for elem in reversed(self._stack): + if isinstance(elem.node, DebugSequence): + return elem.node + + # Ooh, not good.. + assert False, "invalid state: no debug sequence on active debug sequence execute context stack" + + def _push(self, node: DebugSequenceNode, scope: Scope) -> None: + """@brief Context stack push operation. + + Separated even though it's tiny so it can be used manually for unit testing. + """ + self._stack.append(self._NodeScopeStackItem(node, scope)) + + def _pop(self) -> None: + """@brief Context stack pop operation. + + Separated even though it's tiny so it can be used manually for unit testing. + """ + self._stack.pop() + + @contextmanager + def push(self, node: DebugSequenceNode, scope: Scope) -> Iterator[None]: + """@brief Context manager to push/pop a sequence node and scope pair on the context stack. + + A node/scope pair is pushed prior to that node (and its children) being executed. + + Scopes in the stack do not automatically or necessarily have parent links between them. This + allows for unlinked scopes from the call stack of sequences to be placed on the stack, without + causing issues with variable access. + + Blocks are not normally pushed, since they do not define scopes. The sole exception to this is when + the debugvars block is executed to create the root scope, but this is done by the code that + creates the root scope and not the Block itself. + + When the context manager exits, the scope is popped. + """ + try: + self._push(node, scope) + yield + finally: + self._pop() + + def get_variable(self, name: str) -> int: + """@brief Return the value of a variable from the current scope.""" + assert self.current_scope is not None + try: + return self.current_scope.get(name) + except KeyError as err: + LOG.debug("debug sequence reference to undefined variable %s... %s", name, self.current_scope.dump()) + raise DebugSequenceRuntimeError(f"reference to undefined variable {name}") from err + + def __enter__(self) -> Self: + """@brief Make this context the active one for the current thread.""" + self._thread_local_contexts.context = self + return self + + def __exit__(self, exc_type, value, traceback) -> None: + """@brief Clear the current thread's active context.""" + assert self._thread_local_contexts.context == self + del self._thread_local_contexts.context + +class DebugSequenceNode(GraphNode): + """@brief Common base class for debug sequence nodes.""" + + def __init__(self, info: str = "") -> None: + super().__init__() + self._info = info + + @property + def info(self) -> str: + return self._info + + def execute(self, context: DebugSequenceExecutionContext) -> Optional[Scope]: + """@brief Execute the sequence node. + + @return If a scope was created in order to execute the sequence node, that scope is returned + to the caller so any variables can be accessed. + """ + raise NotImplementedError() + + def _execute_children(self, context: DebugSequenceExecutionContext) -> None: + """@brief Execute all child nodes.""" + for node in self.children: + cast(DebugSequenceNode, node).execute(context) + +class DebugSequence(DebugSequenceNode): + """@brief Named debug sequence. + + Variable scoping: + - Sequences and control elements create new scopes. + - Scope extends to child control elements. + - Block elements do not create a new scope. + - Variables in a parent scope can be modified. + - Leaving a scope destroys contained variables. + - Variables are not passed to sub-sequences. + + Special read-write variables: + - __dp, __ap, __apid, __errorcontrol + - Propagates to another sequence called via the Sequence() function. + - Restored to previous values when sub-sequence returns. + - __Result + - Not pushed when calling another sequence. + - 0=success + + Special read-only variables: + - __protocol + - [15:0] 0=error, 1=JTAG, 2=SWD, 3=cJTAG + - [16] SWJ-DP present? + - [17] switch through dormant state? + - __connection + - [7:0] connection type: 0=error/disconnected, 1=for debug, 2=for flashing + - [15:8] reset type: 0=error, 1=hw, 2=SYSRESETREQ, 3=VECTRESET + - [16] connect under reset? + - [17] pre-connect reset? + - __traceout + - [0] SWO enabled? + - [1] parallel trace enabled? + - [2] trace buffer enabled? + - [21:16] selected parallel trace port size + - __FlashOp + - 0=no op, 1=erase full chip, 2=erase sector, 3=program + - __FlashAddr + - __FlashLen + - __FlashArg + """ + + ## Special predefined variables that are read-write and propagate to sub-sequences. + _SPECIAL_VARS = ['__dp', '__ap', '__apid', '__errorcontrol'] + + ## Predefined variables that are read-write, but do not propagate. + _WRITABLE_PREDEFINED = ['__Result'] + + def __init__( + self, + name: str, + is_enabled: bool = True, + pname: Optional[str] = None, + info: str = "" + ) -> None: + super().__init__(info) + self._name = name + self._is_enabled = is_enabled + self._pname = pname + + @property + def name(self) -> str: + return self._name + + @property + def pname(self) -> Optional[str]: + return self._pname + + @property + def is_enabled(self) -> bool: + return self._is_enabled + + def _create_scope(self, context: DebugSequenceExecutionContext) -> Scope: + """@brief Create a new variables scope with predefined variables filled in.""" + delegate = context.delegate + + # Create the new scope using the delegate's root scope as parent. + scope = Scope(parent=context.delegate.get_root_scope(context), name=self.name) + + # Writable result. + scope.set('__Result', 0) + + # Propagate specials if there is a sequence that called us. + if context.has_current_sequence: + scope.copy_variables(context.current_scope, self._SPECIAL_VARS) + # Otherwise just fill in the defaults. + else: + scope.set('__errorcontrol', 0) + + # Convert the default AP address to __ap and __apid variables. If the AP is v1 then + # __ap is set, for v2 __apid is set. The other variable gets set to 0. + default_ap_address = context.default_ap + scope.set('__dp', default_ap_address.dp_index) # We still only support one DP. + scope.set('__ap', default_ap_address.nominal_address + if isinstance(default_ap_address, APv1Address) + else 0) + scope.set('__apid', default_ap_address.nominal_address + if isinstance(default_ap_address, APv2Address) + else 0) + + # Generate __protocol value. + protocol = delegate.get_protocol() + scope.set('__protocol', protocol, readonly=True) + + # Generate __connection value. + connection = delegate.get_connection_type() + scope.set('__connection', connection, readonly=True) + + # Generate __traceout value. + traceout = delegate.get_traceout() + scope.set('__traceout', traceout, readonly=True) + + # Flash algorithm sequence parameters. + scope.set('__FlashOp', 0, readonly=True) + scope.set('__FlashAddr', 0, readonly=True) + scope.set('__FlashLen', 0, readonly=True) + scope.set('__FlashArg', 0, readonly=True) + return scope + + def execute(self, context: DebugSequenceExecutionContext) -> Optional[Scope]: + """@brief Run the sequence.""" + scope = self._create_scope(context) + + # Make this the active sequence. + with context.push(self, scope): + self._execute_children(context) + + return scope + + def __eq__(self, o: object) -> bool: + return (isinstance(o, DebugSequence) + and self.name == o.name + and self.pname == o.pname + and self.is_enabled == o.is_enabled) + + def __hash__(self) -> int: + return hash((self.name, self.pname, self.is_enabled)) + + def __repr__(self): + return f"<{type(self).__name__}@{id(self):x} {self.name} enabled={self.is_enabled} pname={self.pname}>" + +class Control(DebugSequenceNode): + """@brief Base class for control nodes of debug sequences. + + Control elements create new scopes. + """ + + class ControlType(Enum): + IF = 1 + WHILE = 2 + + def __init__(self, control_type: ControlType, predicate: str, info: str = "", timeout_µs: int = 0) -> None: + """@brief Constructor. + @param self The control object. + @param control_type One of the #ControlType enums that selects between if- and while-type. + @param predicate String of the predicate expression. + @param info Optional descriptive string. + @param timeout_µs Integer timeout in microseconds. A value of zero means an infinite timeout. + """ + super().__init__(info) + self._type = control_type + # Convert µs to seconds, and 0 to None. + self._timeout = (timeout_µs / 1000000) if timeout_µs else None + self._predicate = predicate + self._ast = Parser.parse(predicate) + + def execute(self, context: DebugSequenceExecutionContext) -> Optional[Scope]: + """@brief Run the sequence.""" + # Get our scope and interpreter objects. + parent_scope = context.current_scope + scope = Scope( + parent_scope, + name=f"{parent_scope.name}.{self._type.name}" + ) + interp = Interpreter(self._ast, scope, context) + + # Push our new scope. + with context.push(self, scope): + # Start the timeout counting. + timeout = Timeout(self._timeout) + timeout.start() + + # Execute the predicate a first time. + result = interp.execute() + TRACE.debug("%s(%s): pred=%s", self._type.name, self._predicate, result) + + while result and timeout.check(): + # Execute all child nodes. + self._execute_children(context) + + # For an if control, we're done. + if self._type == self.ControlType.IF: + break + # For a while control, re-evaluate the predicate. + elif self._type == self.ControlType.WHILE: + result = interp.execute() + TRACE.debug("%s(%s): pred=%d", self._type.name, self._predicate, result) + + return scope + + def __repr__(self): + return f"<{type(self).__name__}@{id(self):x} {self._ast.pretty()}>" + +class WhileControl(Control): + """@brief Looping debug sequence node.""" + + def __init__(self, predicate: str, info: str = "", timeout: int = 0) -> None: + super().__init__(self.ControlType.WHILE, predicate, info, timeout) + +class IfControl(Control): + """@brief Conditional debug sequence node.""" + + def __init__(self, predicate: str, info: str = "", timeout: int = 0) -> None: + super().__init__(self.ControlType.IF, predicate, info, timeout) + +class Block(DebugSequenceNode): + """@brief Block of debug sequence statements. + + Block elements do not create a new scope. + """ + + def __init__(self, code: str, is_atomic: bool = False, info: str = "") -> None: + super().__init__(info) + self._ast = Parser.parse(code) + self._is_atomic = is_atomic + + def execute(self, context: DebugSequenceExecutionContext) -> Optional[Scope]: + """@brief Run the sequence.""" + assert context.session.probe + + try: + # If the block is atomic, hold the probe lock while it is executed. + if self._is_atomic: + context.session.probe.lock() + + interp = Interpreter(self._ast, context.current_scope, context) + interp.execute() + finally: + if self._is_atomic: + context.session.probe.unlock() + + def __repr__(self): + atomic_str = " atomic" if self._is_atomic else "" + return f"<{type(self).__name__}@{id(self):x}{atomic_str} {self._ast.pretty()}>" + +# Using Any type for the methods of this class is a workaround for LarkToken not being +# handled or inferred correctly, since Lark doesn't have annotations. +class _ConstantFolder(lark.visitors.Transformer): + """@brief Performs basic constant folding on expressions.""" + + def _is_intlit(self, node: Any) -> bool: + return isinstance(node, int) + + def ternary_expr(self, children: Any) -> Any: + predicate = children[0] + true_expr = children[1] + false_expr = children[2] + + # Fold ternaries to either true or false branch when the predicate is an integer constant. + if self._is_intlit(predicate): + if predicate != 0: + return true_expr + elif predicate == 0: + return false_expr + + return LarkTree('ternary_expr', children) + + def binary_expr(self, children: Any) -> Any: + left = children[0] + op = children[1].value + right = children[2] + + # Fold binary expressions on literals. + if self._is_intlit(left) and self._is_intlit(right): + result = _BINARY_OPS[op](left, right) + # TRACE.debug("opt: %#x %s %#x -> %#x", left, op, right, result) + return result + + # Fold binary expressions with a left operand of zero. + elif self._is_intlit(right) and right == 0: + # Operators whose result will be the left operand unmodified. + if op in ('+', '-', '|', '^', '<<', '>>', '||'): + # TRACE.debug("opt: x %s 0 -> x", op) + return left + # Operators whose result will be zero. + elif op in ('*', '/', '%', '&', '&&'): + # TRACE.debug("opt: x %s 0 -> 0", op) + return 0 + + # Fold binary expression with a right operand of zero. + elif self._is_intlit(left) and left == 0: + # Operators whose result will be the right operand unmodified. + if op in ('+', '-', '|', '^', '||'): + # TRACE.debug("opt: 0 %s x -> x", op) + return right + # Operators whose result will be zero. + elif op in ('*', '/', '%', '&', '<<', '>>', '&&'): + # TRACE.debug("opt: 0 %s x -> 0", op) + return 0 + + # Fold binary expressions with a left operand of 1. + elif self._is_intlit(right) and right == 1: + # Operators whose result will be the left operand unmodified. + if op in ('*', '/'): + # TRACE.debug("opt: x %s 1 -> x", op) + return left + # Operators whose result will be one. + elif op in ('||',): + # TRACE.debug("opt: x %s 1 -> 1", op) + return 1 + # Operators whose result will be zero. + elif op in ('%',): + # TRACE.debug("opt: x %s 1 -> 0", op) + return 0 + + return LarkTree('binary_expr', children) + + def unary_expr(self, children: Any) -> Any: + op = children[0].value + arg = children[1] + + # Fold unary expressions on a literal. + if self._is_intlit(arg): + result = _UNARY_OPS[op](arg) + # TRACE.debug("opt: %s %#x -> %#x", op, arg, result) + return result + + return LarkTree('unary_expr', children) + +## Lambdas for evaluating binary operators. +# +# Note that divide and modulo by 0 just results in 0 rather than an exception. +_BINARY_OPS = { + '+': lambda l, r: l + r, + '-': lambda l, r: l - r, + '*': lambda l, r: l * r, + '/': lambda l, r: 0 if (r == 0) else (l // r), + '%': lambda l, r: 0 if (r == 0) else (l % r), + '&': lambda l, r: l & r, + '|': lambda l, r: l | r, + '^': lambda l, r: l ^ r, + '<<': lambda l, r: l << r, + '>>': lambda l, r: l >> r, + '&&': lambda l, r: int(bool(l) & bool(r)), # implement C-style AND + '||': lambda l, r: int(bool(l) | bool(r)), # implement C-style OR + '==': lambda l, r: int(l == r), + '!=': lambda l, r: int(l != r), + '>': lambda l, r: int(l > r), + '>=': lambda l, r: int(l >= r), + '<': lambda l, r: int(l < r), + '<=': lambda l, r: int(l <= r), + } + +## Lambdas for evaluating unary operators. +_UNARY_OPS = { + '~': lambda v: bit_invert(v, width=64), + '!': lambda v: int(not v), + '+': lambda v: v, + '-': lambda v: (-v) & 0xffffffffffffffff, # Mask to get unsigned two's complement. + } + +class SemanticChecker: + """@brief Check the semantics of debug sequence statements.""" + + class _SemanticsVisitor(lark.visitors.Visitor): + """@brief Visitor for performing semantic checks of debug sequence statements.""" + + def __init__(self, scope: Scope, context: DebugSequenceExecutionContext) -> None: + super().__init__() + self._scope = scope + self._context = context + self._fns = self._context.delegate.get_sequence_functions() + self._declared_variables = set() + + def decl_stmt(self, tree: LarkTree) -> None: + # Record the declared variable name. + assert _is_token(tree.children[0], 'IDENT') + assert isinstance(tree.children[0], LarkToken) + name = tree.children[0].value + self._declared_variables.add(name) + + # Disallow assigning expressions consisting of only a string. + if _is_token(tree.children[1], 'STRLIT'): + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: cannot store a string to variable '{name}'") + + def assign_stmt(self, tree: LarkTree) -> None: + # Assigned variable must have been previously declared. + # TODO disabled until declarations are fully tracked in scopes. + assert _is_token(tree.children[0], 'IDENT') + assert isinstance(tree.children[0], LarkToken) + name = tree.children[0].value +# if name not in self._declared_variables: +# raise DebugSequenceSemanticError( +# f"line {tree.meta.line}: attempt to set undeclared variable '{name}'") + + # Disallow assigning expressions consisting of only a string. + if _is_token(tree.children[2], 'STRLIT'): + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: cannot store a string to variable '{name}'") + + def expr_stmt(self, tree: LarkTree) -> None: + # Disallow statements consisting of only a string. + if _is_token(tree.children[0], 'STRLIT'): + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: expression statements consisting of only a string are invalid") + + def fncall(self, tree: LarkTree) -> None: + fn_name = tree.children[0] + assert isinstance(fn_name, str) + # TRACE.debug("checking %s (%s)", fn_name, tree.children[1:]) + + # Case-insensitive match. + fn_name = fn_name.lower() + + # Look up the function on the delegate. + try: + impl = getattr(self._fns, fn_name) + except AttributeError: + raise DebugSequenceSemanticError(f"line {tree.meta.line}: call to unknown function '{fn_name}'") + + # Get the function's signature. + sig = signature(impl) + + arg_count = len(tree.children[1:]) + param_count = 0 + has_varargs = False + + # Note that the 'self' parameter should not be present due to getting the signature from the + # bound method of the functions delegate instance. + for param in sig.parameters.values(): + if param.kind == param.VAR_POSITIONAL: + # Don't need to check past a varargs parameter. + has_varargs = True + break + else: + param_count += 1 + + # Check arg count. + if param_count > arg_count: + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: function '{fn_name}' is passed too few arguments") + + # Check argument types. + # + # The type of the argument is only checked if a type annotation is present. Type annotations + # must be stringified, eg using 'from __future__ import annotations' or Python 3.10. Only + # explicit 'str' and 'int' annotation types are currently supported; subclasses of these + # types are not (which is why empty annotations are allowed, as a workaround). + arg_node = tree.children[param_count] + + # str params require a literal string arg. + if param.annotation == 'str' and not _is_token(arg_node, 'STRLIT'): + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: function '{fn_name}' parameter '{param.name}' " + "requires a string argument") + # int params require either a literal int or an expression tree. + elif param.annotation == 'int' and not \ + (isinstance(arg_node, int) or _is_token(arg_node, 'IDENT') or isinstance(arg_node, LarkTree)): + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: function '{fn_name}' parameter '{param.name}' " + "requires an integer argument") + + # Check for more args than parameters. + if (param_count < arg_count) and not has_varargs: + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: function '{fn_name}' is passed too many arguments") + + # Function-specific checks. + if fn_name == "Sequence": + # From above, we know the correct number of arguments is present, and that the arg is a string. + assert isinstance(tree.children[1], LarkToken) + name = tree.children[1].value + + # Look for a sequence with the given name. + if not self._context.delegate.has_sequence_with_name(name, self._context.pname): + raise DebugSequenceSemanticError( + f"line {tree.meta.line}: attempt to call undefined sequence '{name}'") + + def __init__(self, tree: LarkTree, scope: Scope, context: DebugSequenceExecutionContext) -> None: + """@brief Constructor. + + @param self This object. + @param tree The abstract syntax tree that will be checked. + @param scope Scope within which the AST will execute. + @param delegate Delegate providing debug sequence function implementations. + """ + super().__init__() + self._tree = tree + self._scope = scope + self._context = context + + def check(self) -> None: + """@brief Performs the semantic checks and raises for any errors. + @exception DebugSequenceSemanticError A semantic error was discovered in the provided code. + """ + visitor = self._SemanticsVisitor(self._scope, self._context) + visitor.visit(self._tree) + +class Interpreter: + """@brief Interpreting for debug sequence ASTs. + + This class interprets the AST from only a single block or control node. The user of this class + is required to handle crossing block/control boundaries. + + An Interpreter instance can be used to execute the AST more than once. + """ + + class _InterpreterVisitor(lark.visitors.Interpreter): + """@brief Visitor for interpreting sequence trees.""" + + def __init__(self, scope: Scope, context: DebugSequenceExecutionContext) -> None: + super().__init__() + self._scope = scope + self._context = context + self._fns = self._context.delegate.get_sequence_functions() + + def start(self, tree: LarkTree) -> Optional[int]: + # Interpret the tree. + values = self.visit_children(tree) + return values.pop() if len(values) else None + + def _log_children(self, name: str, children: List) -> None: # pragma: no cover + LOG.info('%s: %s', name, [(("Node: %s" % c.data) if hasattr(c, 'data') else ("%s=%s" % (c.type, c.value))) for c in children]) + + def decl_stmt(self, tree: LarkTree) -> None: + values = self.visit_children(tree) + + assert _is_token(values[0], 'IDENT') + name = values[0].value + # Handle __var declarations with no initialiser expression. Even though this is disallowed + # by the specification, it appears in some DFPs, including some of NXP's. + if values[1] is None: + value = 0 + + TRACE.debug("(line %d): decl %s = 0", getattr(tree.meta, 'line', 0), name) + else: + value = self._get_atom(values[1]) + + TRACE.debug("(line %d): decl %s = %s", getattr(tree.meta, 'line', 0), name, self._format_atom(values[1])) + + self._scope.set(name, value) + + def assign_stmt(self, tree: LarkTree) -> None: + values = self.visit_children(tree) + + name = values[0].value + op = values[1].value + value = self._get_atom(values[2]) + + TRACE.debug("(line %d): %s %s %s", getattr(tree.meta, 'line', 0), name, op, self._format_atom(values[2])) + + # Handle compound assignment operators. + if op != '=': + left = self._scope.get(name) + op = op.rstrip('=') + value = _BINARY_OPS[op](left, value) + + self._scope.set(name, value) + + def expr_stmt(self, tree: LarkTree) -> int: + values = self.visit_children(tree) + expr_value = values.pop() + TRACE.debug("(line %d): expr stmt = %s", getattr(tree.meta, 'line', 0), self._format_atom(expr_value)) + return self._get_atom(expr_value) + + def ternary_expr(self, tree: LarkTree) -> int: + values = self.visit_children(tree) + + predicate = self._get_atom(values[0]) + + if not isinstance(predicate, int): + raise DebugSequenceSemanticError("ternary expression predicate is not an integer") + + if predicate != 0: + result = self._get_atom(values[1]) + else: + result = self._get_atom(values[2]) + + TRACE.debug("(line %s): %s ? %s : %s -> %s", + getattr(tree.meta, 'line', 0), + self._format_atom(values[0]), + self._format_atom(values[1]), + self._format_atom(values[2]), + hex(result)) + + return result + + def binary_expr(self, tree: LarkTree) -> int: + values = self.visit_children(tree) + + left = self._get_atom(values[0]) + op = values[1].value + right = self._get_atom(values[2]) + + result = _BINARY_OPS[op](left, right) + + TRACE.debug("(line %s): %s %s %s -> %s", getattr(tree.meta, 'line', 0), + self._format_atom(values[0]), op, self._format_atom(values[2]), hex(result)) + return result + + def unary_expr(self, tree: LarkTree) -> int: + values = self.visit_children(tree) + + op = values[0].value + value = self._get_atom(values[1]) + + result = _UNARY_OPS[op](value) + + TRACE.debug("(line %s): %s %s -> %s", getattr(tree.meta, 'line', 0), op, self._format_atom(values[1]), + hex(result)) + + return result + + def fncall(self, tree: LarkTree) -> int: + values = self.visit_children(tree) + fn_name = values[0] + fn_args = [self._get_atom(a) for a in values[1:]] + + # Case-insensitive match. + fn_name = fn_name.lower() + + TRACE.debug("(line %d): fn %s (%s) ...", getattr(tree.meta, 'line', 0), fn_name, + ", ".join(self._format_atom(a) for a in values[1:])) + + # Should have already verified the function name. + impl = getattr(self._fns, fn_name) + result = impl(*fn_args) + if result is None: + result = 0 + + TRACE.debug("(line %d): fn %s () returned %s", getattr(tree.meta, 'line', 0), fn_name, hex(result)) + return result + + def _get_atom(self, node: NodeType) -> int: + if isinstance(node, LarkTree): + raise DebugSequenceSemanticError(f"expected atom but found an expression tree of type {node.data}") + elif isinstance(node, LarkToken): + if node.type == 'IDENT': + try: + return self._scope.get(node.value) + except KeyError as err: + LOG.debug("debug sequence reference to undefined variable %s... %s", + node.value, self._scope.dump()) + raise DebugSequenceSemanticError(f"reference to undefined variable {node.value}") from err + elif node.type in ('INTLIT', 'STRLIT'): + return node.value + else: + raise DebugSequenceSemanticError(f"unexpected literal type {node.type}") + elif isinstance(node, int): + return node + else: + raise DebugSequenceSemanticError("unexpected node type when expecting atom") + + def _format_atom(self, node: NodeType) -> str: + """@brief Format an atom for trace logging.""" + if isinstance(node, LarkToken): + if node.type == 'IDENT': + try: + return node.value + "{" + hex(self._scope.get(node.value)) + "}" + except KeyError: + TRACE.debug("reference to undefined variable %s... %s", node.value, self._scope.dump()) + return node.value + "{undefined}" + elif node.type == 'INTLIT': + return hex(node.value) + elif node.type == 'STRLIT': + return f"'{node.value}'" + else: + raise DebugSequenceSemanticError(f"unexpected literal type {node.type}") + elif isinstance(node, int): + return hex(node) + else: + return f"?<{type(node).__class__}>?" + + def __init__(self, tree: LarkTree, scope: Scope, context: DebugSequenceExecutionContext) -> None: + """@brief Constructor. + + The provided AST is semantically checked and optimized. + + @param self This interpreter. + @param tree The abstract syntax tree to interpret. + @param scope Scope within which the AST will execute. + @param delegate Delegate providing debug sequence function implementations. + + @exception DebugSequenceSemanticError A semantic error was discovered in the provided code. + """ + super().__init__() + self._scope = scope + self._context = context + + # First run the semantic checker, so semantic errors are raised prior to actually + # performing any actions. + checker = SemanticChecker(tree, self._scope, context) + checker.check() + + # Do some optimization. + self._tree = _ConstantFolder().transform(tree) + + def execute(self) -> int: + """@brief Runs the statements in the AST passed to the constructor. + @return The value of the last statement is returned to the caller. + """ + visitor = self._InterpreterVisitor(self._scope, self._context) + return visitor.visit(self._tree) + diff --git a/pyocd/debug/svd/data/LPC55S16.xml b/pyocd/debug/svd/data/LPC55S16.xml new file mode 100644 index 000000000..4a704c073 --- /dev/null +++ b/pyocd/debug/svd/data/LPC55S16.xml @@ -0,0 +1,86741 @@ + + + nxp.com + LPC55S16 + 1.0 + LPC55S16JBD100,LPC55S16JBD64,LPC55S16JEV98 + +Copyright 2016-2021 NXP +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r2p0 + little + true + true + true + 3 + false + + 8 + 32 + + + FLASH_CFPA0 + FLASH_CFPA + FLASH_CFPA + FLASH_CFPA + 0x3E000 + + 0 + 0x200 + registers + + + + HEADER + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + VERSION + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + S_FW_Version + Secure firmware version (Monotonic counter) + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + NS_FW_Version + Non-Secure firmware version (Monotonic counter) + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + IMAGE_KEY_REVOKE + Image key revocation ID (Monotonic counter) + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + ROTKH_REVOKE + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RoTK0_EN + RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 0 + 2 + read-write + + + RoTK1_EN + RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 2 + 2 + read-write + + + RoTK2_EN + RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 4 + 2 + read-write + + + RoTK3_EN + RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 6 + 2 + read-write + + + + + VENDOR_USAGE + no description available + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_VENDOR_USAGE + DBG_VENDOR_USAGE. + 0 + 16 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_PIN + With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug enable + 0 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + DBGEN + Non Secure debug enable + 1 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + SPNIDEN + Secure non-invasive debug enable + 2 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + SPIDEN + Secure invasive debug enable + 3 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + TAPEN + JTAG TAP enable + 4 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command enable + 6 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + FA_ME_CMD_EN + FA Command enable + 7 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + UUID_CHECK + Enforce UUID match during Debug authentication. + 15 + 1 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_DFLT + With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug fixed state + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DBGEN + Non Secure debug fixed state + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPNIDEN + Secure non-invasive debug fixed state + 2 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPIDEN + Secure invasive debug fixed state + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TAPEN + JTAG TAP fixed state + 4 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command fixed state + 6 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FA_ME_CMD_EN + FA Command fixed state + 7 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + ENABLE_FA_MODE + Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + CMPA_PROG_IN_PROGRESS + CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE0 + no description available + PRINCE_REGION0_IV_CODE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_HEADER0 + no description available + PRINCE_REGION0_IV_CODE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE1 + no description available + PRINCE_REGION0_IV_CODE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_HEADER1 + no description available + PRINCE_REGION0_IV_CODE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + no description available + 0 + 2 + read-write + + + INDEX + no description available + 8 + 4 + read-write + + + SIZE + no description available + 24 + 6 + read-write + + + + + PRINCE_REGION0_IV_BODY0 + no description available + PRINCE_REGION0_IV_CODE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE2 + no description available + PRINCE_REGION0_IV_CODE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY1 + no description available + PRINCE_REGION0_IV_CODE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE3 + no description available + PRINCE_REGION0_IV_CODE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY2 + no description available + PRINCE_REGION0_IV_CODE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE4 + no description available + PRINCE_REGION0_IV_CODE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY3 + no description available + PRINCE_REGION0_IV_CODE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE5 + no description available + PRINCE_REGION0_IV_CODE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY4 + no description available + PRINCE_REGION0_IV_CODE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE6 + no description available + PRINCE_REGION0_IV_CODE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY5 + no description available + PRINCE_REGION0_IV_CODE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE7 + no description available + PRINCE_REGION0_IV_CODE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY6 + no description available + PRINCE_REGION0_IV_CODE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE8 + no description available + PRINCE_REGION0_IV_CODE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY7 + no description available + PRINCE_REGION0_IV_CODE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE9 + no description available + PRINCE_REGION0_IV_CODE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY8 + no description available + PRINCE_REGION0_IV_CODE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE10 + no description available + PRINCE_REGION0_IV_CODE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY9 + no description available + PRINCE_REGION0_IV_CODE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE11 + no description available + PRINCE_REGION0_IV_CODE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY10 + no description available + PRINCE_REGION0_IV_CODE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE12 + no description available + PRINCE_REGION0_IV_CODE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY11 + no description available + PRINCE_REGION0_IV_CODE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE13 + no description available + PRINCE_REGION0_IV_CODE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE0 + no description available + PRINCE_REGION1_IV_CODE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_HEADER0 + no description available + PRINCE_REGION1_IV_CODE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE1 + no description available + PRINCE_REGION1_IV_CODE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_HEADER1 + no description available + PRINCE_REGION1_IV_CODE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + no description available + 0 + 2 + read-write + + + INDEX + no description available + 8 + 4 + read-write + + + SIZE + no description available + 24 + 6 + read-write + + + + + PRINCE_REGION1_IV_BODY0 + no description available + PRINCE_REGION1_IV_CODE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE2 + no description available + PRINCE_REGION1_IV_CODE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY1 + no description available + PRINCE_REGION1_IV_CODE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE3 + no description available + PRINCE_REGION1_IV_CODE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY2 + no description available + PRINCE_REGION1_IV_CODE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE4 + no description available + PRINCE_REGION1_IV_CODE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY3 + no description available + PRINCE_REGION1_IV_CODE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE5 + no description available + PRINCE_REGION1_IV_CODE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY4 + no description available + PRINCE_REGION1_IV_CODE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE6 + no description available + PRINCE_REGION1_IV_CODE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY5 + no description available + PRINCE_REGION1_IV_CODE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE7 + no description available + PRINCE_REGION1_IV_CODE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY6 + no description available + PRINCE_REGION1_IV_CODE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE8 + no description available + PRINCE_REGION1_IV_CODE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY7 + no description available + PRINCE_REGION1_IV_CODE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE9 + no description available + PRINCE_REGION1_IV_CODE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY8 + no description available + PRINCE_REGION1_IV_CODE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE10 + no description available + PRINCE_REGION1_IV_CODE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY9 + no description available + PRINCE_REGION1_IV_CODE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE11 + no description available + PRINCE_REGION1_IV_CODE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY10 + no description available + PRINCE_REGION1_IV_CODE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE12 + no description available + PRINCE_REGION1_IV_CODE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY11 + no description available + PRINCE_REGION1_IV_CODE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE13 + no description available + PRINCE_REGION1_IV_CODE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE0 + no description available + PRINCE_REGION2_IV_CODE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_HEADER0 + no description available + PRINCE_REGION2_IV_CODE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE1 + no description available + PRINCE_REGION2_IV_CODE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_HEADER1 + no description available + PRINCE_REGION2_IV_CODE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + no description available + 0 + 2 + read-write + + + INDEX + no description available + 8 + 4 + read-write + + + SIZE + no description available + 24 + 6 + read-write + + + + + PRINCE_REGION2_IV_BODY0 + no description available + PRINCE_REGION2_IV_CODE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE2 + no description available + PRINCE_REGION2_IV_CODE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY1 + no description available + PRINCE_REGION2_IV_CODE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE3 + no description available + PRINCE_REGION2_IV_CODE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY2 + no description available + PRINCE_REGION2_IV_CODE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE4 + no description available + PRINCE_REGION2_IV_CODE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY3 + no description available + PRINCE_REGION2_IV_CODE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE5 + no description available + PRINCE_REGION2_IV_CODE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY4 + no description available + PRINCE_REGION2_IV_CODE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE6 + no description available + PRINCE_REGION2_IV_CODE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY5 + no description available + PRINCE_REGION2_IV_CODE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE7 + no description available + PRINCE_REGION2_IV_CODE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY6 + no description available + PRINCE_REGION2_IV_CODE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE8 + no description available + PRINCE_REGION2_IV_CODE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY7 + no description available + PRINCE_REGION2_IV_CODE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE9 + no description available + PRINCE_REGION2_IV_CODE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY8 + no description available + PRINCE_REGION2_IV_CODE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE10 + no description available + PRINCE_REGION2_IV_CODE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY9 + no description available + PRINCE_REGION2_IV_CODE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE11 + no description available + PRINCE_REGION2_IV_CODE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY10 + no description available + PRINCE_REGION2_IV_CODE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE12 + no description available + PRINCE_REGION2_IV_CODE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY11 + no description available + PRINCE_REGION2_IV_CODE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE13 + no description available + PRINCE_REGION2_IV_CODE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 56 + 0x4 + CUSTOMER_DEFINED[%s] + Customer Defined (Programable through ROM API) + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 8 + 0x4 + SHA256_DIGEST[%s] + SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + + + FLASH_CFPA_SCRATCH + FLASH_CFPA + FLASH_CFPA + 0x3DE00 + + 0 + 0x200 + registers + + + + FLASH_CFPA1 + FLASH_CFPA + FLASH_CFPA + 0x3E200 + + 0 + 0x200 + registers + + + + FLASH_CMPA + FLASH_CMPA + FLASH_CMPA + 0x3E400 + + 0 + 0x200 + registers + + + + BOOT_CFG + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEFAULT_ISP_MODE + Default ISP mode: + 4 + 3 + read-write + + + AUTO_ISP + Auto ISP + 0 + + + USB_HID_ISP + USB_HID_ISP + 0x1 + + + UART_ISP + UART ISP + 0x2 + + + SPI_ISP + SPI Slave ISP + 0x3 + + + I2C_ISP + I2C Slave ISP + 0x4 + + + DISABLE + Disable ISP fall through + 0x7 + + + + + BOOT_SPEED + Core clock: + 7 + 2 + read-write + + + VALUE_0 + Defined by NMPA.SYSTEM_SPEED_CODE + 0 + + + VALUE_2 + 48MHz FRO + 0x2 + + + + + BOOT_FAILURE_PIN + GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin + 24 + 8 + read-write + + + + + SPI_FLASH_CFG + no description available + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPI_RECOVERY_BOOT_EN + SPI flash recovery boot is enabled, if non-zero value is written to this field. + 0 + 5 + read-write + + + + + USB_ID + no description available + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + USB_VENDOR_ID + no description available + 0 + 16 + read-write + + + USB_PRODUCT_ID + no description available + 16 + 16 + read-write + + + + + SDIO_CFG + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + CC_SOCU_PIN + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug enable + 0 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + DBGEN + Non Secure debug enable + 1 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + SPNIDEN + Secure non-invasive debug enable + 2 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + SPIDEN + Secure invasive debug enable + 3 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + TAPEN + JTAG TAP enable + 4 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command enable + 6 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + FA_ME_CMD_EN + FA Command enable + 7 + 1 + read-write + + + ENABLE + Use DAP to enable + 0 + + + DISABLE + Fixed state + 0x1 + + + + + UUID_CHECK + Enforce UUID match during Debug authentication. + 15 + 1 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + CC_SOCU_DFLT + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug fixed state + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DBGEN + Non Secure debug fixed state + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPNIDEN + Secure non-invasive debug fixed state + 2 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPIDEN + Secure invasive debug fixed state + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TAPEN + JTAG TAP fixed state + 4 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command fixed state + 6 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FA_ME_CMD_EN + FA Command fixed state + 7 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + VENDOR_USAGE + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + VENDOR_USAGE + Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + 16 + 16 + read-write + + + + + SECURE_BOOT_CFG + Secure boot configuration flags. + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + RSA4K + Use RSA4096 keys only. + 0 + 2 + read-write + + + VALUE_0 + Allow RSA2048 and higher + 0 + + + VALUE_1 + RSA4096 only + 0x1 + + + VALUE_2 + RSA4096 only + 0x2 + + + VALUE_3 + RSA4096 only + 0x3 + + + + + DICE_INC_NXP_CFG + Include NXP area in DICE computation. + 2 + 2 + read-write + + + NOT_INCLUD + not included + 0 + + + INCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + + + + DICE_CUST_CFG + Include Customer factory area (including keys) in DICE computation. + 4 + 2 + read-write + + + NOT_INCLUD + not included + 0 + + + UNCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + + + + SKIP_DICE + Skip DICE computation + 6 + 2 + read-write + + + ENABLE + Enable DICE + 0 + + + DISABLE + Disable DICE + 0x1 + + + VALUE_2 + Disable DICE + 0x2 + + + VALUE_3 + Disable DICE + 0x3 + + + + + TZM_IMAGE_TYPE + TrustZone-M mode + 8 + 2 + read-write + + + VALUE_0 + TZ-M image mode is taken from application image header + 0 + + + VALUE_1 + TZ-M disabled image, boots to non-secure mode + 0x1 + + + VALUE_2 + TZ-M enabled image, boots to secure mode + 0x2 + + + VALUE_3 + TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + 0x3 + + + + + BLOCK_SET_KEY + Block PUF key code generation + 10 + 2 + read-write + + + ALLOW + Allow PUF Key Code generation + 0 + + + DISABLE + Disable PUF Key Code generation + 0x1 + + + VALUE_2 + Disable PUF Key Code generation + 0x2 + + + VALUE_3 + Disable PUF Key Code generation + 0x3 + + + + + BLOCK_ENROLL + Block PUF enrollement + 12 + 2 + read-write + + + ALLOW + Allow PUF enroll operation + 0 + + + DISABLE + Disable PUF enroll operation + 0x1 + + + VALUE_2 + Disable PUF enroll operation + 0x2 + + + VALUE_3 + Disable PUF enroll operation + 0x3 + + + + + DICE_INC_SEC_EPOCH + Include security EPOCH in DICE + 14 + 2 + read-write + + + NOT_INCLUD + not included + 0 + + + INCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + + + + SKIP_BOOT_SEED + Skip boot seed computation + 16 + 2 + read-write + + + ENABLE + Enable BOOT_SEED + 0 + + + DISABLE + Disable BOOT_SEED + 0x1 + + + VALUE_2 + Disable BOOT_SEED + 0x2 + + + VALUE_3 + Disable BOOT_SEED + 0x3 + + + + + BOOT_SEED_INC_NXP_CFG + Include NXP area in BOOT SEED computation + 18 + 2 + read-write + + + NOT_INCLUD + not included + 0 + + + INCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + + + + BOOT_SEED_CUST_CFG + Include CMPA area in BOOT SEED computation + 20 + 2 + read-write + + + NOT_INCLUD + not included + 0 + + + INCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + + + + BOOT_SEED_INC_EPOCH + Include security epoch area in BOOT_SEED computation. + 22 + 2 + read-write + + + NOT_INCLUD + not included + 0 + + + INCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + + + + SEC_BOOT_EN + Secure boot enable + 30 + 2 + read-write + + + DISABLE + Plain image (internal flash with or without CRC) + 0 + + + ENABLE + Boot signed images. (internal flash, RSA signed) + 0x1 + + + VALUE_2 + Boot signed images. (internal flash, RSA signed) + 0x2 + + + VALUE_3 + Boot signed images. (internal flash, RSA signed) + 0x3 + + + + + + + PRINCE_BASE_ADDR + no description available + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0_PRG + Programmable portion of the base address of region 0 + 0 + 4 + read-write + + + ADDR1_PRG + Programmable portion of the base address of region 1 + 4 + 4 + read-write + + + ADDR2_PRG + Programmable portion of the base address of region 2 + 8 + 4 + read-write + + + LOCK_REG0 + Lock PRINCE region0 settings + 18 + 2 + read-write + + + UNLOCK + Region is not locked + 0 + + + LOCK + Region is locked + 0x1 + + + VALUE_2 + Region is locked + 0x2 + + + VALUE_3 + Region is locked + 0x3 + + + + + LOCK_REG1 + Lock PRINCE region1 settings + 20 + 2 + read-write + + + UNLOCK + Region is not locked + 0 + + + LOCK + Region is locked + 0x1 + + + VALUE_2 + Region is locked + 0x2 + + + VALUE_3 + Region is locked + 0x3 + + + + + REG0_ERASE_CHECK_EN + For PRINCE region0 enable checking whether all encrypted pages are erased together + 24 + 2 + read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + + + + REG1_ERASE_CHECK_EN + For PRINCE region1 enable checking whether all encrypted pages are erased together + 26 + 2 + read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + + + + REG2_ERASE_CHECK_EN + For PRINCE region2 enable checking whether all encrypted pages are erased together + 28 + 2 + read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + + + + + + PRINCE_SR_0 + Region 0, sub-region enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_SR_1 + Region 1, sub-region enable + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PRINCE_SR_2 + Region 2, sub-region enable + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + XTAL_32KHZ_CAPABANK_TRIM + Xtal 32kHz capabank triming. + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIM_VALID + XTAL 32kHz capa bank trimmings + 0 + 1 + read-write + + + NOT_TRIM + Capa Bank trimmings not valid. Default trimmings value are used + 0 + + + VALID + Capa Bank trimmings valid + 0x1 + + + + + XTAL_LOAD_CAP_IEC_PF_X100 + Load capacitance, pF x 100. For example, 6pF becomes 600. + 1 + 10 + read-write + + + PCB_XIN_PARA_CAP_PF_X100 + PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 11 + 10 + read-write + + + PCB_XOUT_PARA_CAP_PF_X100 + PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 21 + 10 + read-write + + + + + XTAL_16MHZ_CAPABANK_TRIM + Xtal 16MHz capabank triming. + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIM_VALID + XTAL 16MHz capa bank trimmings + 0 + 1 + read-write + + + NOT_TRIM + Capa Bank trimmings not valid. Default trimmings value are used + 0 + + + VALID + Capa Bank trimmings valid + 0x1 + + + + + XTAL_LOAD_CAP_IEC_PF_X100 + Load capacitance, pF x 100. For example, 6pF becomes 600. + 1 + 10 + read-write + + + PCB_XIN_PARA_CAP_PF_X100 + PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 11 + 10 + read-write + + + PCB_XOUT_PARA_CAP_PF_X100 + PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 21 + 10 + read-write + + + + + FLASH_REMAP_SIZE + This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FLASH_REMAP_OFFSET + This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 8 + 0x4 + ROTKH[%s] + ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index) * 32)] + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 56 + 0x4 + CUSTOMER_DEFINED[%s] + Customer Defined (Programable through ROM API) + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 8 + 0x4 + SHA256_DIGEST[%s] + SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + + + FLASH_KEY_STORE + FLASH_KEY_STORE + FLASH_KEY_STORE + 0x3E600 + + 0 + 0x600 + registers + + + + HEADER + Valid Key Sore Header : 0x95959595 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + puf_discharge_time_in_ms + puf discharge time in ms. + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 298 + 0x4 + ACTIVATION_CODE[%s] + . + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_HEADER0 + . + SBKEY_KEY_CODE + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE0 + . + SBKEY_KEY_CODE + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_HEADER1 + . + SBKEY_KEY_CODE + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + SBKEY_KEY_CODE1 + . + SBKEY_KEY_CODE + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY0 + . + SBKEY_KEY_CODE + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE2 + . + SBKEY_KEY_CODE + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY1 + . + SBKEY_KEY_CODE + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE3 + . + SBKEY_KEY_CODE + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY2 + . + SBKEY_KEY_CODE + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE4 + . + SBKEY_KEY_CODE + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY3 + . + SBKEY_KEY_CODE + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE5 + . + SBKEY_KEY_CODE + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY4 + . + SBKEY_KEY_CODE + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE6 + . + SBKEY_KEY_CODE + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY5 + . + SBKEY_KEY_CODE + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE7 + . + SBKEY_KEY_CODE + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY6 + . + SBKEY_KEY_CODE + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE8 + . + SBKEY_KEY_CODE + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY7 + . + SBKEY_KEY_CODE + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE9 + . + SBKEY_KEY_CODE + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY8 + . + SBKEY_KEY_CODE + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE10 + . + SBKEY_KEY_CODE + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY9 + . + SBKEY_KEY_CODE + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE11 + . + SBKEY_KEY_CODE + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY10 + . + SBKEY_KEY_CODE + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE12 + . + SBKEY_KEY_CODE + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY11 + . + SBKEY_KEY_CODE + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE13 + . + SBKEY_KEY_CODE + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_HEADER0 + . + USER_KEK_KEY_CODE + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE0 + . + USER_KEK_KEY_CODE + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_HEADER1 + . + USER_KEK_KEY_CODE + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + USER_KEK_KEY_CODE1 + . + USER_KEK_KEY_CODE + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY0 + . + USER_KEK_KEY_CODE + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE2 + . + USER_KEK_KEY_CODE + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY1 + . + USER_KEK_KEY_CODE + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE3 + . + USER_KEK_KEY_CODE + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY2 + . + USER_KEK_KEY_CODE + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE4 + . + USER_KEK_KEY_CODE + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY3 + . + USER_KEK_KEY_CODE + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE5 + . + USER_KEK_KEY_CODE + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY4 + . + USER_KEK_KEY_CODE + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE6 + . + USER_KEK_KEY_CODE + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY5 + . + USER_KEK_KEY_CODE + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE7 + . + USER_KEK_KEY_CODE + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY6 + . + USER_KEK_KEY_CODE + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE8 + . + USER_KEK_KEY_CODE + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY7 + . + USER_KEK_KEY_CODE + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE9 + . + USER_KEK_KEY_CODE + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY8 + . + USER_KEK_KEY_CODE + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE10 + . + USER_KEK_KEY_CODE + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY9 + . + USER_KEK_KEY_CODE + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE11 + . + USER_KEK_KEY_CODE + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY10 + . + USER_KEK_KEY_CODE + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE12 + . + USER_KEK_KEY_CODE + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY11 + . + USER_KEK_KEY_CODE + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE13 + . + USER_KEK_KEY_CODE + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_HEADER0 + . + UDS_KEY_CODE + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE0 + . + UDS_KEY_CODE + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_HEADER1 + . + UDS_KEY_CODE + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + UDS_KEY_CODE1 + . + UDS_KEY_CODE + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY0 + . + UDS_KEY_CODE + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE2 + . + UDS_KEY_CODE + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY1 + . + UDS_KEY_CODE + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE3 + . + UDS_KEY_CODE + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY2 + . + UDS_KEY_CODE + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE4 + . + UDS_KEY_CODE + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + 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+ 0 + 32 + read-write + + + + + + + FLASH_NMPA + FLASH_NMPA + FLASH_NMPA + 0x3FC00 + + 0 + 0xCC0 + registers + + + + GPO0_0 + GPO0 register 0 description + GPO0 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRO_TRIM_VALID + no description available + 0 + 1 + read-write + + + FRO32K_NTAT + no description available + 1 + 3 + read-write + + + FRO32K_PTAT + no description available + 4 + 3 + read-write + + + FRO32K_CAPCAL + no description available + 7 + 9 + read-write + + + FIELD + no description available + 16 + 16 + read-write + + + + + GPO0_ARRAY0 + GPO0 array description + GPO0 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO0_1 + GPO0 register 1 description + GPO0 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO0_ARRAY1 + GPO0 array description + GPO0 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO0_2 + GPO0 register 2 description + GPO0 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SYSTEM_SPEED_CODE + 00 : FRO12MHz 01 : FRO24MHz 10 : FRO48MHz 11 : FRO96MHz + 0 + 2 + read-write + + + FLASH_CTRL_OPMODE + 00 : Delay Line 01 : RCLK (back up clock) 10 : PCLK (back up clock) + 2 + 2 + read-write + + + FIELD + no description available + 4 + 28 + read-write + + + + + GPO0_ARRAY2 + GPO0 array description + GPO0 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO0_3 + GPO0 register 3 description + GPO0 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO0_ARRAY3 + GPO0 array description + GPO0 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO1_0 + GPO1 register 0 description + GPO1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FINAL_TEST_NOT_DONE + FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. + 0 + 4 + read-write + + + PARTCONFIG + Device type number. (E.g : LPC5569 stored as 69 decimal) + 4 + 7 + read-write + + + DEVICE_TYPE_SEC + Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) + 11 + 1 + read-write + + + SRAM_SIZE + SRAM_SIZE[3:0]: (For Niobe4) 0000 : 320 KB 0001 : 256 KB 0010 : 144 KB 0011 : 80 KB (For Niobe4 Mini) 0100 : 96 KB 0101 : 80 KB 0110 : 64 KB 0111 : 48 KB All others : RESERVED + 12 + 4 + read-write + + + CPU0_SECURITY_EXTENSION_DISABLE + CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security Extension is disabled. All Other values: CPU0 Security Extension is enabled. + 16 + 4 + read-write + + + FIELD + no description available + 20 + 4 + read-write + + + ROM_REVISION_MINOR + ROM Revision-Minor [3:0] + 24 + 4 + read-write + + + METAL_REVISION_ID + METAL REVISION ID[3:0] + 28 + 4 + read-write + + + + + GPO1_ARRAY0 + GPO1 array description + GPO1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO1_1 + GPO1 register 1 description + GPO1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROM_PATCH_VERSION + ROM Patch Version [3:0] + 0 + 4 + read-write + + + CUSTOMER_REVISION_ID + CUSTOMER REVISION ID[3:0] + 4 + 4 + read-write + + + FIELD + no description available + 8 + 24 + read-write + + + + + GPO1_ARRAY1 + GPO1 array description + GPO1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO1_2 + GPO1 register 2 description + GPO1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + HVST + High Voltage Stress: 0=not done; 1=done. + 0 + 1 + read-write + + + FIELD + no description available + 1 + 31 + read-write + + + + + GPO1_ARRAY2 + GPO1 array description + GPO1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO1_3 + GPO1 register 3 description + GPO1 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO1_ARRAY3 + GPO1 array description + GPO1 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO2_0 + GPO2 register 0 description + GPO2 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + USBHS_PHY_TRIM_VALID + no description available + 0 + 1 + read-write + + + TRIM_USB_REG_ENV_TAIL_ADJ_VD + no description available + 1 + 2 + read-write + + + TRIM_USBPHY_TX_D_CAL + no description available + 3 + 4 + read-write + + + TRIM_USBPHY_TX_CAL45DP + no description available + 7 + 5 + read-write + + + TRIM_USBPHY_TX_CAL45DN + no description available + 12 + 5 + read-write + + + TRIM_USB2_REFBIAS_TST + no description available + 17 + 2 + read-write + + + TRIM_USB2_REFBIAS_VBGADJ + no description available + 19 + 3 + read-write + + + TRIM_PLL_CTRL0_DIV_SEL + no description available + 22 + 3 + read-write + + + FLASH_SIZE + (For Niobe4) 000 : 640 KB 001 : 512 KB 010 : 256 KB 011 : 128 KB 100 : 0 KB All others : RESERVED (For Niobe4 Mini) FLASH_SIZE[2:0] 000 : 256 KB 001 : 128 KB 010 : 80 KB (reserved) 011 : 64 KB 100 : 0 kB (reserved) All others : RESERVED + 25 + 3 + read-write + + + CPU0_SECURITY_EXTENSION_DISABLE + CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security Extension is disabled. All Other values: CPU0 Security Extension is enabled. + 28 + 4 + read-write + + + + + GPO2_ARRAY0 + GPO2 array description + GPO2 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO2_1 + GPO2 register 1 description + GPO2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO2_ARRAY1 + GPO2 array description + GPO2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO2_2 + GPO2 register 2 description + GPO2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO2_ARRAY2 + GPO2 array description + GPO2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO2_3 + GPO2 register 3 description + GPO2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO2_ARRAY3 + GPO2 array description + GPO2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO3_0 + GPO3 register 0 description + GPO3 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUX_BIAS_TRIM_VALID + no description available + 0 + 1 + read-write + + + AUX_BIAS_ITRIM + no description available + 1 + 5 + read-write + + + AUX_BIAS_PTAT_ITRIM + no description available + 6 + 5 + read-write + + + AUX_BIAS_VREF1_VTRIM + no description available + 11 + 5 + read-write + + + AUX_BIAS_VREF1_VCURVE_TRIM + no description available + 16 + 3 + read-write + + + FIELD + no description available + 19 + 6 + read-write + + + MODELNUM_EXTENSION + ModelNumber extension[2:0] + 25 + 3 + read-write + + + FINAL_TEST_NOT_DONE + FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. + 28 + 4 + read-write + + + + + GPO3_ARRAY0 + GPO3 array description + GPO3 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO3_1 + GPO3 register 1 description + GPO3 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO3_ARRAY1 + GPO3 array description + GPO3 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO3_2 + GPO3 register 2 description + GPO3 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO3_ARRAY2 + GPO3 array description + GPO3 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO3_3 + GPO3 register 3 description + GPO3 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO3_ARRAY3 + GPO3 array description + GPO3 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_0 + checksum of the GPO data in words 0 + GPO_CHECKSUM + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_ARRAY0 + checksum of the GPO data in words [3:0] + GPO_CHECKSUM + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_1 + checksum of the GPO data in words 1 + GPO_CHECKSUM + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_ARRAY1 + checksum of the GPO data in words [3:0] + GPO_CHECKSUM + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_2 + checksum of the GPO data in words 2 + GPO_CHECKSUM + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_ARRAY2 + checksum of the GPO data in words [3:0] + GPO_CHECKSUM + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_3 + checksum of the GPO data in words 3 + GPO_CHECKSUM + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + GPO_CHECKSUM_ARRAY3 + checksum of the GPO data in words [3:0] + GPO_CHECKSUM + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_0 + no description available + FINAL_TEST_BATCH_ID + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_ARRAY0 + no description available + FINAL_TEST_BATCH_ID + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_1 + no description available + FINAL_TEST_BATCH_ID + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_ARRAY1 + no description available + FINAL_TEST_BATCH_ID + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_2 + no description available + FINAL_TEST_BATCH_ID + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_ARRAY2 + no description available + FINAL_TEST_BATCH_ID + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_3 + no description available + FINAL_TEST_BATCH_ID + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + FINAL_TEST_BATCH_ID_ARRAY3 + no description available + FINAL_TEST_BATCH_ID + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + DEVICE_TYPE + no description available + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEVICE_TYPE_NUM + Device type number. (E.g : LPC5569 stored as 5569 decimal) + 0 + 16 + read-write + + + DEVICE_TYPE_SEC + Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) + 16 + 1 + read-write + + + DEVICE_TYPE_PKG + Device package type: 0000 : HLQFP 0001 : HTQFP 0010 : HVQFN 0100 : VFBGA 1000 : WLCSP + 20 + 4 + read-write + + + DEVICE_TYPE_PIN + Number of pins on the package. + 24 + 8 + read-write + + + + + FINAL_TEST_PROGRAM_VERSION + no description available + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROGRAM_VERSION + PROGRAM_VERSION [xx.yy stored as : 100*x+y] + 0 + 32 + read-write + + + + + FINAL_TEST_DATE + no description available + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATE + DATE [stored as : year*10000+month*100+day] + 0 + 32 + read-write + + + + + FINAL_TEST_TIME + no description available + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME + TIME [stored as : hour*10000+minute*100+seconde] + 0 + 32 + read-write + + + + + UUID_0 + no description available + UUID + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + UUID_ARRAY0 + no description available + UUID + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + UUID_1 + no description available + UUID + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + UUID_ARRAY1 + no description available + UUID + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + UUID_2 + no description available + UUID + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + UUID_ARRAY2 + no description available + UUID + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + UUID_3 + no description available + UUID + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + UUID_ARRAY3 + no description available + UUID + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + WAFER_TEST1_PROGRAM_VERSION + no description available + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + WT1_PROGRAM_VERSION + WT1_PROGRAM_VERSION [xx.yy stored as : 100*x+y] + 0 + 32 + read-write + + + + + WAFER_TEST1_DATE + no description available + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + WT1_DATE + WT1_DATE [stored as : year*10000+month*100+day] + 0 + 32 + read-write + + + + + WAFER_TEST1_TIME + no description available + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + WT1_TIME + WT1_TIME [stored as : hour*10000+minute*100+seconde] + 0 + 32 + read-write + + + + + WAFER_TEST2_PROGRAM_VERSION + no description available + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + WT2_PROGRAM_VERSION + WT2_PROGRAM_VERSION [xx.yy stored as : 100*x+y] + 0 + 32 + read-write + + + + + WAFER_TEST2_DATE + no description available + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WT2_DATE + WT2_DATE [stored as : year*10000+month*100+day] + 0 + 32 + read-write + + + + + WAFER_TEST2_TIME + no description available + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + WT2_TIME + WT2_TIME [stored as : hour*10000+minute*100+seconde] + 0 + 32 + read-write + + + + + USBCFG + no description available + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + XO32M_READY_TIME_OUT_MS + no description available + 0 + 8 + read-write + + + USB_SPEED + USB_SPEED[7:0]= 0x00 : USB High Speed Module used for ISP 0x01 : USB Full SPeed Module used for ISP 0x02 : Neither USB High Speed module nor USB Full Speed module used for ISP 0x03 - 0xFF : RESERVED + 8 + 8 + read-write + + + USB_USE_XO32M_CAPA_BANKS + Enable the use of Crystal 32 MHz internal Capa Banks during the configuration of the High Speed USB for ISP: 0: Disable Crystal 32 MHz CapaBanks. 1: Enable Crystal 32 MHz CapaBanks. + 16 + 1 + read-write + + + + + PERIPHENCFG + no description available + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERIPHERAL_CONFIGURATION + no description available + 0 + 16 + read-write + + + CPU1_ENABLE + no description available + 31 + 1 + read-write + + + + + RAMSIZECFG + no description available + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRAM_CONFIGURATION + no description available + 0 + 32 + read-write + + + + + FLASHSIZECFG + no description available + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASH_CONFIGURATION + no description available + 0 + 32 + read-write + + + + + RINGO_0 + no description available + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RINGO_0_CTRL_VALID + 1: RINGO_0_CTRL is valid. + 0 + 1 + read-write + + + RINGO_0_CTRL + To copy RINGO_0_CTRL = ANACTRL->RINGO0_CTRL[30:0] + 1 + 31 + read-write + + + + + RINGO_1 + no description available + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RINGO_1_CTRL_VALID + 1: RINGO_1_CTRL is valid. + 0 + 1 + read-write + + + RINGO_1_CTRL + To copy RINGO_1_CTRL = ANACTRL->RINGO1_CTRL[30:0] + 1 + 31 + read-write + + + + + RINGO_2 + no description available + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RINGO_2_CTRL_VALID + 1: RINGO_2_CTRL is valid. + 0 + 1 + read-write + + + RINGO_2_CTRL + To copy RINGO_2_CTRL = ANACTRL->RINGO2_CTRL[30:0] + 1 + 31 + read-write + + + + + FRO_192MHZ + no description available + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRO192M_TRIM_VALID + no description available + 0 + 1 + read-write + + + FRO192M_BIASTRIM + FRO192M_BIASTRIM[5:0]. + 1 + 6 + read-write + + + FRO192M_TEMPTRIM + FRO192M_TEMPTRIM[6:0]. + 8 + 7 + read-write + + + FRO192M_DACTRIM + FRO192M_DACTRIM[7:0]. + 17 + 8 + read-write + + + + + XO_32MHZ + no description available + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + XO32M_XIN_TRIM_VALID + no description available + 0 + 1 + read-write + + + XO32M_XIN_CAPCAL_6PF + no description available + 1 + 7 + read-write + + + XO32M_XIN_CAPCAL_8PF + no description available + 8 + 7 + read-write + + + XO32M_XOUT_TRIM_VALID + no description available + 15 + 1 + read-write + + + XO32M_XOUT_CAPCAL_6PF + no description available + 16 + 7 + read-write + + + XO32M_XOUT_CAPCAL_8PF + no description available + 23 + 7 + read-write + + + XO32M_XO_SLAVE_STATUS + no description available + 30 + 1 + read-write + + + XO32M_XO_AC_BUF_STATUS + no description available + 31 + 1 + read-write + + + + + XO_32KHZ + no description available + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + XO32K_XIN_TRIM_VALID + no description available + 0 + 1 + read-write + + + XO32K_XIN_CAPCAL_6PF + no description available + 1 + 7 + read-write + + + XO32K_XIN_CAPCAL_8PF + no description available + 8 + 7 + read-write + + + XO32K_XOUT_TRIM_VALID + no description available + 15 + 1 + read-write + + + XO32K_XOUT_CAPCAL_6PF + no description available + 16 + 7 + read-write + + + XO32K_XOUT_CAPCAL_8PF + no description available + 23 + 7 + read-write + + + + + FRO_1MHZ + no description available + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRO1M_TRIM_VALID + no description available + 0 + 1 + read-write + + + FRO1M_FREQSEL + Frequency trimming bits. + 1 + 7 + read-write + + + + + DCDC_POWER_PROFILE_HIGH_0 + no description available + DCDC_POWER_PROFILE_HIGH + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCDC_TRIM_VALID + DCDC is trimed. + 0 + 1 + read-write + + + RC + Constant On-Time calibration. + 1 + 6 + read-write + + + ICOMP + Select the type of ZCD comparator. + 7 + 2 + read-write + + + ISEL + Alter Internal biasing currents. + 9 + 2 + read-write + + + ICENABLE + Selection of auto scaling of COT period with variations in VDD. + 11 + 1 + read-write + + + TMOS + One-shot generator reference current trimming signal. + 12 + 5 + read-write + + + DISABLEISENSE + Disable Current sensing. + 17 + 1 + read-write + + + VOUT + Set output regulation voltage. + 18 + 4 + read-write + + + SLICINGENABLE + Enable staggered switching of power switches. + 22 + 1 + read-write + + + INDUCTORCLAMPENABLE + Enable shorting of Inductor during PFM idle time. + 23 + 1 + read-write + + + VOUT_PWD + Set output regulation voltage during Deep Sleep. + 24 + 4 + read-write + + + + + DCDC_POWER_PROFILE_HIGH_ARRAY0 + no description available + DCDC_POWER_PROFILE_HIGH + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + DCDC_POWER_PROFILE_HIGH_1 + no description available + DCDC_POWER_PROFILE_HIGH + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + RTRIMOFFET + Adjust the offset voltage of BJT based comparator. + 0 + 4 + read-write + + + RSENSETRIM + Adjust Max inductor peak current limiting. + 4 + 4 + read-write + + + DTESTENABLE + Enable Digital test signals. + 8 + 1 + read-write + + + SETCURVE + Bandgap calibration parameter. + 9 + 2 + read-write + + + SETDC + Bandgap calibration parameter. + 11 + 4 + read-write + + + DTESTSEL + Select the output signal for test. + 15 + 3 + read-write + + + ISCALEENABLE + Modify COT behavior. + 18 + 1 + read-write + + + FORCEBYPASS + Force bypass mode. + 19 + 1 + read-write + + + TRIMAUTOCOT + Change the scaling ratio of the feedforward compensation. + 20 + 4 + read-write + + + FORCEFULLCYCLE + Force full PFM PMOS and NMOS cycle. + 24 + 1 + read-write + + + LCENABLE + Change the range of the peak detector of current inside the inductor. + 25 + 1 + read-write + + + TOFF + Constant Off-Time calibration input. + 26 + 5 + read-write + + + TOFFENABLE + Enable Constant Off-Time feature. + 31 + 1 + read-write + + + + + DCDC_POWER_PROFILE_HIGH_ARRAY1 + no description available + DCDC_POWER_PROFILE_HIGH + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + DCDC_POWER_PROFILE_LOW_0 + no description available + DCDC_POWER_PROFILE_LOW + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCDC_TRIM_VALID + DCDC is trimed. + 0 + 1 + read-write + + + RC + Constant On-Time calibration. + 1 + 6 + read-write + + + ICOMP + Select the type of ZCD comparator. + 7 + 2 + read-write + + + ISEL + Alter Internal biasing currents. + 9 + 2 + read-write + + + ICENABLE + Selection of auto scaling of COT period with variations in VDD. + 11 + 1 + read-write + + + TMOS + One-shot generator reference current trimming signal. + 12 + 5 + read-write + + + DISABLEISENSE + Disable Current sensing. + 17 + 1 + read-write + + + VOUT + Set output regulation voltage. + 18 + 4 + read-write + + + SLICINGENABLE + Enable staggered switching of power switches. + 22 + 1 + read-write + + + INDUCTORCLAMPENABLE + Enable shorting of Inductor during PFM idle time. + 23 + 1 + read-write + + + VOUT_PWD + Set output regulation voltage during Deep Sleep. + 24 + 4 + read-write + + + + + DCDC_POWER_PROFILE_LOW_ARRAY0 + no description available + DCDC_POWER_PROFILE_LOW + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + DCDC_POWER_PROFILE_LOW_1 + no description available + DCDC_POWER_PROFILE_LOW + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTRIMOFFET + Adjust the offset voltage of BJT based comparator. + 0 + 4 + read-write + + + RSENSETRIM + Adjust Max inductor peak current limiting. + 4 + 4 + read-write + + + DTESTENABLE + Enable Digital test signals. + 8 + 1 + read-write + + + SETCURVE + Bandgap calibration parameter. + 9 + 2 + read-write + + + SETDC + Bandgap calibration parameter. + 11 + 4 + read-write + + + DTESTSEL + Select the output signal for test. + 15 + 3 + read-write + + + ISCALEENABLE + Modify COT behavior. + 18 + 1 + read-write + + + FORCEBYPASS + Force bypass mode. + 19 + 1 + read-write + + + TRIMAUTOCOT + Change the scaling ratio of the feedforward compensation. + 20 + 4 + read-write + + + FORCEFULLCYCLE + Force full PFM PMOS and NMOS cycle. + 24 + 1 + read-write + + + LCENABLE + Change the range of the peak detector of current inside the inductor. + 25 + 1 + read-write + + + TOFF + Constant Off-Time calibration input. + 26 + 5 + read-write + + + TOFFENABLE + Enable Constant Off-Time feature. + 31 + 1 + read-write + + + + + DCDC_POWER_PROFILE_LOW_ARRAY1 + no description available + DCDC_POWER_PROFILE_LOW + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + DCDC_POWER_PROFILE_MEDIUM_0 + no description available + DCDC_POWER_PROFILE_MEDIUM + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCDC_TRIM_VALID + DCDC is trimed. + 0 + 1 + read-write + + + RC + Constant On-Time calibration. + 1 + 6 + read-write + + + ICOMP + Select the type of ZCD comparator. + 7 + 2 + read-write + + + ISEL + Alter Internal biasing currents. + 9 + 2 + read-write + + + ICENABLE + Selection of auto scaling of COT period with variations in VDD. + 11 + 1 + read-write + + + TMOS + One-shot generator reference current trimming signal. + 12 + 5 + read-write + + + DISABLEISENSE + Disable Current sensing. + 17 + 1 + read-write + + + VOUT + Set output regulation voltage. + 18 + 4 + read-write + + + SLICINGENABLE + Enable staggered switching of power switches. + 22 + 1 + read-write + + + INDUCTORCLAMPENABLE + Enable shorting of Inductor during PFM idle time. + 23 + 1 + read-write + + + VOUT_PWD + Set output regulation voltage during Deep Sleep. + 24 + 4 + read-write + + + + + DCDC_POWER_PROFILE_MEDIUM_ARRAY0 + no description available + DCDC_POWER_PROFILE_MEDIUM + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + DCDC_POWER_PROFILE_MEDIUM_1 + no description available + DCDC_POWER_PROFILE_MEDIUM + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + RTRIMOFFET + Adjust the offset voltage of BJT based comparator. + 0 + 4 + read-write + + + RSENSETRIM + Adjust Max inductor peak current limiting. + 4 + 4 + read-write + + + DTESTENABLE + Enable Digital test signals. + 8 + 1 + read-write + + + SETCURVE + Bandgap calibration parameter. + 9 + 2 + read-write + + + SETDC + Bandgap calibration parameter. + 11 + 4 + read-write + + + DTESTSEL + Select the output signal for test. + 15 + 3 + read-write + + + ISCALEENABLE + Modify COT behavior. + 18 + 1 + read-write + + + FORCEBYPASS + Force bypass mode. + 19 + 1 + read-write + + + TRIMAUTOCOT + Change the scaling ratio of the feedforward compensation. + 20 + 4 + read-write + + + FORCEFULLCYCLE + Force full PFM PMOS and NMOS cycle. + 24 + 1 + read-write + + + LCENABLE + Change the range of the peak detector of current inside the inductor. + 25 + 1 + read-write + + + TOFF + Constant Off-Time calibration input. + 26 + 5 + read-write + + + TOFFENABLE + Enable Constant Off-Time feature. + 31 + 1 + read-write + + + + + DCDC_POWER_PROFILE_MEDIUM_ARRAY1 + no description available + DCDC_POWER_PROFILE_MEDIUM + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + BOD + no description available + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BOD_VBAT_TRIM_VALID + no description available + 0 + 1 + read-write + + + BOD_VBAT_TRIGLVL + no description available + 1 + 5 + read-write + + + BOD_VBAT_HYST + no description available + 6 + 2 + read-write + + + BOD_CORE_TRIM_VALID + no description available + 16 + 1 + read-write + + + BOD_CORE_TRIGLVL + no description available + 17 + 3 + read-write + + + BOD_CORE_HYST + no description available + 21 + 2 + read-write + + + + + LDO_AO + no description available + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_TRIM_VALID + no description available + 0 + 1 + read-write + + + ACTIVE_TRIM + no description available + 1 + 5 + read-write + + + DSLP_TRIM_VALID + no description available + 8 + 1 + read-write + + + DSLP_TRIM + no description available + 9 + 5 + read-write + + + PDWN_TRIM_VALID + no description available + 16 + 1 + read-write + + + PDWN_TRIM + no description available + 17 + 5 + read-write + + + DPDW_TRIM_VALID + no description available + 24 + 1 + read-write + + + DPDW_TRIM + no description available + 25 + 5 + read-write + + + + + SDIO_DELAY + no description available + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDIO_0_VALID + no description available + 0 + 1 + read-write + + + SDIO_0_DELAY + SDIO_0_DELAY (unit: 100 ps). + 1 + 10 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_0 + no description available + AUX_BIAS_CURVE_AMBIENT + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_0 + VREF1VCURVETRIM_0 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_1 + VREF1VCURVETRIM_1 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_ARRAY0 + Aux Bias Curve Ambient (30degC) + AUX_BIAS_CURVE_AMBIENT + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_1 + no description available + AUX_BIAS_CURVE_AMBIENT + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_2 + VREF1VCURVETRIM_2 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_3 + VREF1VCURVETRIM_3 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_ARRAY1 + Aux Bias Curve Ambient (30degC) + AUX_BIAS_CURVE_AMBIENT + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_2 + no description available + AUX_BIAS_CURVE_AMBIENT + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_4 + VREF1VCURVETRIM_4 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_5 + VREF1VCURVETRIM_5 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_ARRAY2 + Aux Bias Curve Ambient (30degC) + AUX_BIAS_CURVE_AMBIENT + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_3 + no description available + AUX_BIAS_CURVE_AMBIENT + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_6 + VREF1VCURVETRIM_6 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_7 + VREF1VCURVETRIM_7 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_AMBIENT_ARRAY3 + Aux Bias Curve Ambient (30degC) + AUX_BIAS_CURVE_AMBIENT + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + AUX_BIAS_CURVE_TEMP_0 + no description available + AUX_BIAS_CURVE_TEMP + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_0 + VREF1VCURVETRIM_0 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_1 + VREF1VCURVETRIM_1 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_TEMP_ARRAY0 + Aux Bias Curve TEMP (105degC) + AUX_BIAS_CURVE_TEMP + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + AUX_BIAS_CURVE_TEMP_1 + no description available + AUX_BIAS_CURVE_TEMP + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_2 + VREF1VCURVETRIM_2 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_3 + VREF1VCURVETRIM_3 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_TEMP_ARRAY1 + Aux Bias Curve TEMP (105degC) + AUX_BIAS_CURVE_TEMP + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + AUX_BIAS_CURVE_TEMP_2 + no description available + AUX_BIAS_CURVE_TEMP + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_4 + VREF1VCURVETRIM_4 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_5 + VREF1VCURVETRIM_5 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_TEMP_ARRAY2 + Aux Bias Curve TEMP (105degC) + AUX_BIAS_CURVE_TEMP + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + AUX_BIAS_CURVE_TEMP_3 + no description available + AUX_BIAS_CURVE_TEMP + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + VREF1VCURVETRIM_6 + VREF1VCURVETRIM_6 (unit: 100uV) + 0 + 16 + read-write + + + VREF1VCURVETRIM_7 + VREF1VCURVETRIM_7 (unit: 100uV) + 16 + 16 + read-write + + + + + AUX_BIAS_CURVE_TEMP_ARRAY3 + Aux Bias Curve TEMP (105degC) + AUX_BIAS_CURVE_TEMP + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + TEMP_SENS_VBE1VBE8_REF_1 + no description available + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + VBE1 + no description available + 0 + 16 + read-write + + + VBE8 + no description available + 16 + 16 + read-write + + + + + TEMP_SENS_VBE1VBE8_REF_2 + no description available + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + VBE1 + no description available + 0 + 16 + read-write + + + VBE8 + no description available + 16 + 16 + read-write + + + + + TEMP_SENS_SLOPE + no description available + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + VALID + no description available + 0 + 1 + read-write + + + SLOPE_x1024 + SLOPE_x1024[30:0] + 1 + 31 + read-write + + + + + TEMP_SENS_OFFSET + no description available + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + VALID + no description available + 0 + 1 + read-write + + + OFFSET_x1024 + OFFSET_x1024[30:0] + 1 + 31 + read-write + + + + + PVT_MONITOR_0_ARRAY0 + no description available + PVT_MONITOR_0 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PVT_MONITOR_0_RINGO + no description available + PVT_MONITOR_0 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + RINGO_VALID + no description available + 0 + 1 + read-write + + + RINGO_FREQ_HZ + no description available + 1 + 31 + read-write + + + + + PVT_MONITOR_0_ARRAY1 + no description available + PVT_MONITOR_0 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PVT_MONITOR_0_DELAYS_LSB + no description available + PVT_MONITOR_0 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAY_VALID + no description available + 0 + 1 + read-write + + + DELAY_0 + Delay in us. + 1 + 10 + read-write + + + DELAY_1 + Delay in us. + 11 + 10 + read-write + + + DELAY_2 + Delay in us. + 21 + 10 + read-write + + + + + PVT_MONITOR_0_ARRAY2 + no description available + PVT_MONITOR_0 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PVT_MONITOR_0_DELAYS_MSB + no description available + PVT_MONITOR_0 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAY_3 + Delay in us. + 0 + 10 + read-write + + + DELAY_4 + Delay in us. + 10 + 10 + read-write + + + DELAY_5 + Delay in us. + 20 + 10 + read-write + + + + + PVT_MONITOR_1_ARRAY0 + no description available + PVT_MONITOR_1 + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PVT_MONITOR_1_RINGO + no description available + PVT_MONITOR_1 + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + RINGO_VALID + no description available + 0 + 1 + read-write + + + RINGO_FREQ_HZ + no description available + 1 + 31 + read-write + + + + + PVT_MONITOR_1_ARRAY1 + no description available + PVT_MONITOR_1 + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PVT_MONITOR_1_DELAYS_LSB + no description available + PVT_MONITOR_1 + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAY_VALID + no description available + 0 + 1 + read-write + + + DELAY_0 + Delay in us. + 1 + 10 + read-write + + + DELAY_1 + Delay in us. + 11 + 10 + read-write + + + DELAY_2 + Delay in us. + 21 + 10 + read-write + + + + + PVT_MONITOR_1_ARRAY2 + no description available + PVT_MONITOR_1 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + PVT_MONITOR_1_DELAYS_MSB + no description available + PVT_MONITOR_1 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAY_3 + Delay in us. + 0 + 10 + read-write + + + DELAY_4 + Delay in us. + 10 + 10 + read-write + + + DELAY_5 + Delay in us. + 20 + 10 + read-write + + + + + 13 + 0x4 + NXP_DEVICE_PRIVATE_KEY[%s] + no description available + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 4 + 0x4 + NXP_DEVICE_CERTIFICATE_0[%s] + NXP Device Certificate (ECDSA_sign - r[255:128]) + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 4 + 0x4 + NXP_DEVICE_CERTIFICATE_1[%s] + NXP Device Certificate (ECDSA_sign - r[127:0]) + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 4 + 0x4 + NXP_DEVICE_CERTIFICATE_2[%s] + NXP Device Certificate (ECDSA_sign - s[255:128]) + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 4 + 0x4 + NXP_DEVICE_CERTIFICATE_3[%s] + NXP Device Certificate (ECDSA_sign - s[127:0]) + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 8 + 0x4 + SHA256_DIGEST[%s] + SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + ECID_BACKUP_0 + no description available + ECID_BACKUP + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + COORD_Y + no description available + 0 + 16 + read-write + + + COORD_X + no description available + 16 + 16 + read-write + + + + + ECID_BACKUP_ARRAY0 + ECID backup (the original is in page n-1) + ECID_BACKUP + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + ECID_BACKUP_1 + no description available + ECID_BACKUP + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAFER + no description available + 0 + 8 + read-write + + + + + ECID_BACKUP_ARRAY1 + ECID backup (the original is in page n-1) + ECID_BACKUP + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + ECID_BACKUP_2 + no description available + ECID_BACKUP + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOTID_LSB + no description available + 0 + 32 + read-write + + + + + ECID_BACKUP_ARRAY2 + ECID backup (the original is in page n-1) + ECID_BACKUP + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + ECID_BACKUP_3 + no description available + ECID_BACKUP + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + LOTID_MSB + no description available + 0 + 32 + read-write + + + + + ECID_BACKUP_ARRAY3 + ECID backup (the original is in page n-1) + ECID_BACKUP + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + no description available + 0 + 32 + read-write + + + + + 4 + 0x4 + CHECKSUM[%s] + Checksum of the whole page + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIS_ROM_HIDING + no description available + 0xCAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DIS_ROM_HIDING + When 0x3CC35AA5 ROM hiding feture is disabled. All other values critical ROM is hidden. + 0 + 32 + read-write + + + + + PUF_SRAM + no description available + 0xCBC + 32 + read-write + 0 + 0xFFFFFFFF + + + PUF_SRAM_VALID + 1: PUF_SRAM is valid. + 0 + 1 + read-write + + + mode + PUF SRAM Controller operating mode + 1 + 1 + read-write + + + ckgating + PUF SRAM Clock Gating control + 2 + 1 + read-write + + + SMB + Source Biasing voltage. + 8 + 2 + read-write + + + LOW + Low leakage. + 0 + + + MEDIUM + Medium leakage. + 0x1 + + + HIGHEST + Highest leakage. + 0x2 + + + DISABLE + Disable. + 0x3 + + + + + RM + Read Margin control settings. + 10 + 3 + read-write + + + WM + Write Margin control settings. + 13 + 3 + read-write + + + WRME + Write read margin enable. + 16 + 1 + read-write + + + RAEN + SRAM Read Assist Enable + 17 + 1 + read-write + + + RAM + SRAM Read Assist settings + 18 + 4 + read-write + + + WAEN + SRAM Write Assist Enable + 22 + 1 + read-write + + + WAM + SRAM Write Assist settings + 23 + 2 + read-write + + + STBP + STBP + 25 + 1 + read-write + + + + + + + SYSCON + SYSCON + SYSCON + 0x40000000 + + 0 + 0x1000 + registers + + + + MEMORYREMAP + Memory Remap control register + 0 + 32 + read-write + 0 + 0x3 + + + MAP + Select the location of the vector table :. + 0 + 2 + read-write + + + ROM0 + Vector Table in ROM. + 0 + + + RAM1 + Vector Table in RAM. + 0x1 + + + FLASH0 + Vector Table in Flash. + 0x2 + + + FLASH1 + Vector Table in Flash. + 0x3 + + + + + + + AHBMATPRIO + AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest + 0x10 + 32 + read-write + 0 + 0x3FFFFFF + + + PRI_CPU0_CBUS + CPU0 C-AHB bus. + 0 + 2 + read-write + + + PRI_CPU0_SBUS + CPU0 S-AHB bus. + 2 + 2 + read-write + + + PRI_SDMA0 + DMA0 controller priority. + 4 + 2 + read-write + + + PRI_SDMA1 + DMA1 controller priority. + 6 + 2 + read-write + + + PRI_USB_FSD + USB0-FS Device.(USB0) + 8 + 2 + read-write + + + PRI_USB_FSH + USB0-FS host.(USB0) + 10 + 2 + read-write + + + PRI_HASH_AES + HASH_AES. + 16 + 2 + read-write + + + PRI_CANFD + CANFD. + 18 + 2 + read-write + + + + + CPU0STCKCAL + System tick calibration for secure part of CPU0 + 0x38 + 32 + read-write + 0 + 0x3FFFFFF + + + TENMS + Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. + 0 + 24 + read-write + + + SKEW + Initial value for the Systick timer. + 24 + 1 + read-write + + + NOREF + Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. + 25 + 1 + read-write + + + + + CPU0NSTCKCAL + System tick calibration for non-secure part of CPU0 + 0x3C + 32 + read-write + 0 + 0x3FFFFFF + + + TENMS + Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. + 0 + 24 + read-write + + + SKEW + Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + 24 + 1 + read-write + + + NOREF + Initial value for the Systick timer. + 25 + 1 + read-write + + + + + NMISRC + NMI Source Select + 0x48 + 32 + read-write + 0 + 0xC0003F3F + + + IRQCPU0 + The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + 0 + 6 + read-write + + + NMIENCPU0 + Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + 31 + 1 + read-write + + + + + PRESETCTRL0 + Peripheral reset control 0 + PRESETCTRL + 0x100 + 32 + read-write + 0 + 0xCFFE9FA + + + ROM_RST + ROM reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL1_RST + SRAM Controller 1 reset control. + 3 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL2_RST + SRAM Controller 2 reset control. + 4 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FLASH_RST + Flash controller reset control. + 7 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FMC_RST + FMC controller reset control. + 8 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MUX_RST + Input Mux reset control. + 11 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + IOCON_RST + I/O controller reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO0_RST + GPIO0 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO1_RST + GPIO1 reset control. + 15 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PINT_RST + Pin interrupt (PINT) reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GINT_RST + Group interrupt (GINT) reset control. + 19 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + DMA0_RST + DMA0 reset control. + 20 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CRCGEN_RST + CRCGEN reset control. + 21 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + WWDT_RST + Watchdog Timer reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + RTC_RST + Real Time Clock (RTC) reset control. + 23 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MAILBOX_RST + Inter CPU communication Mailbox reset control. + 26 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + ADC_RST + ADC reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX0 + Peripheral reset control register + PRESETCTRL + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + PRESETCTRL1 + Peripheral reset control 1 + PRESETCTRL + 0x104 + 32 + read-write + 0 + 0xDE57FC47 + + + MRT_RST + MRT reset control. + 0 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + OSTIMER_RST + OS Event Timer reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SCT_RST + SCT reset control. + 2 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CAN_RST + CAN reset control. + 7 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + UTICK_RST + UTICK reset control. + 10 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC0_RST + FC0 reset control. + 11 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC1_RST + FC1 reset control. + 12 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC2_RST + FC2 reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC3_RST + FC3 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC4_RST + FC4 reset control. + 15 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC5_RST + FC5 reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC6_RST + FC6 reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC7_RST + FC7 reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER2_RST + Timer 2 reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_DEV_RST + USB0-FS DEV reset control. + 25 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER0_RST + Timer 0 reset control. + 26 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER1_RST + Timer 1 reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX1 + Peripheral reset control register + PRESETCTRL + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + PRESETCTRL2 + Peripheral reset control 2 + PRESETCTRL + 0x108 + 32 + read-write + 0 + 0x7FFF77FE + + + DMA1_RST + DMA1 reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + COMP_RST + Comparator reset control. + 2 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_HOST_RST + USB1-HS Host reset control. + 4 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_DEV_RST + USB1-HS dev reset control. + 5 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_RAM_RST + USB1-HS RAM reset control. + 6 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_PHY_RST + USB1-HS PHY reset control. + 7 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FREQME_RST + Frequency meter reset control. + 8 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CDOG_RST + Code Watchdog reset control. + 11 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + RNG_RST + RNG reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SYSCTL_RST + SYSCTL Block reset. + 15 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_HOSTM_RST + USB0-FS Host Master reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_HOSTS_RST + USB0-FS Host Slave reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + HASH_AES_RST + HASH_AES reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PLULUT_RST + PLU LUT reset control. + 20 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER3_RST + Timer 3 reset control. + 21 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER4_RST + Timer 4 reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PUF_RST + PUF reset control reset control. + 23 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CASPER_RST + Casper reset control. + 24 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + ANALOG_CTRL_RST + analog control reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + HS_LSPI_RST + HS LSPI reset control. + 28 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO_SEC_RST + GPIO secure reset control. + 29 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO_SEC_INT_RST + GPIO secure int reset control. + 30 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX2 + Peripheral reset control register + PRESETCTRL + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + PRESETCTRLSET[%s] + Peripheral reset control set register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + PRESETCTRLCLR[%s] + Peripheral reset control clear register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SWR_RESET + generate a software_reset + 0x160 + 32 + write-only + 0 + 0xFFFFFFFF + + + SWR_RESET + Write 0x5A00_0001 to generate a software_reset. + 0 + 32 + write-only + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Generate a software reset. + 0x5A000001 + + + + + + + AHBCLKCTRL0 + AHB Clock control 0 + AHBCLKCTRL + 0x200 + 32 + read-write + 0x180 + 0xCFFE9FA + + + ROM + Enables the clock for the ROM. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL1 + Enables the clock for the SRAM Controller 1. + 3 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL2 + Enables the clock for the SRAM Controller 2. + 4 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FLASH + Enables the clock for the Flash controller. + 7 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FMC + Enables the clock for the FMC controller. + 8 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MUX + Enables the clock for the Input Mux. + 11 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + IOCON + Enables the clock for the I/O controller. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO0 + Enables the clock for the GPIO0. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO1 + Enables the clock for the GPIO1. + 15 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PINT + Enables the clock for the Pin interrupt (PINT). + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GINT + Enables the clock for the Group interrupt (GINT). + 19 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + DMA0 + Enables the clock for the DMA0. + 20 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CRCGEN + Enables the clock for the CRCGEN. + 21 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + WWDT + Enables the clock for the Watchdog Timer. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + RTC + Enables the clock for the Real Time Clock (RTC). + 23 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MAILBOX + Enables the clock for the Inter CPU communication Mailbox. + 26 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + ADC + Enables the clock for the ADC. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX0 + Peripheral reset control register + AHBCLKCTRL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKCTRL1 + AHB Clock control 1 + AHBCLKCTRL + 0x204 + 32 + read-write + 0 + 0xDE57FC47 + + + MRT + Enables the clock for the MRT. + 0 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + OSTIMER + Enables the clock for the OS Event Timer. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SCT + Enables the clock for the SCT. + 2 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CAN + Enables the clock for the CAN. + 7 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + UTICK + Enables the clock for the UTICK. + 10 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC0 + Enables the clock for the FC0. + 11 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC1 + Enables the clock for the FC1. + 12 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC2 + Enables the clock for the FC2. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC3 + Enables the clock for the FC3. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC4 + Enables the clock for the FC4. + 15 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC5 + Enables the clock for the FC5. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC6 + Enables the clock for the FC6. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC7 + Enables the clock for the FC7. + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER2 + Enables the clock for the Timer 2. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_DEV + Enables the clock for the USB0-FS device. + 25 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER0 + Enables the clock for the Timer 0. + 26 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER1 + Enables the clock for the Timer 1. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX1 + Peripheral reset control register + AHBCLKCTRL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKCTRL2 + AHB Clock control 2 + AHBCLKCTRL + 0x208 + 32 + read-write + 0 + 0x7FFF77FE + + + DMA1 + Enables the clock for the DMA1. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + COMP + Enables the clock for the Comparator. + 2 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_HOST + Enables the clock for the USB1-HS Host. + 4 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_DEV + Enables the clock for the USB1-HS device. + 5 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_RAM + Enables the clock for the USB1-HS RAM. + 6 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_PHY + Enables the clock for the USB1-HS PHY. + 7 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FREQME + Enables the clock for the Frequency meter. + 8 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CDOG + Enables the clock for the code watchdog. + 11 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + RNG + Enables the clock for the RNG. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SYSCTL + SYSCTL block clock. + 15 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_HOSTM + Enables the clock for the USB0-FS Host Master. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_HOSTS + Enables the clock for the USB0-FS Host Slave. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + HASH_AES + Enables the clock for the HASH_AES. + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PLULUT + Enables the clock for the PLU LUT. + 20 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER3 + Enables the clock for the Timer 3. + 21 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER4 + Enables the clock for the Timer 4. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PUF + Enables the clock for the PUF reset control. + 23 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CASPER + Enables the clock for the Casper. + 24 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + ANALOG_CTRL + Enables the clock for the analog control. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + HS_LSPI + Enables the clock for the HS LSPI. + 28 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO_SEC + Enables the clock for the GPIO secure. + 29 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO_SEC_INT + Enables the clock for the GPIO secure int. + 30 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX2 + Peripheral reset control register + AHBCLKCTRL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + AHBCLKCTRLSET[%s] + Peripheral reset control register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + AHBCLKCTRLCLR[%s] + Peripheral reset control register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SYSTICKCLKSEL0 + System Tick Timer for CPU0 source select + SYSTICKCLKSEL + 0x260 + 32 + read-write + 0x7 + 0x7 + + + SEL + System Tick Timer for CPU0 source select. + 0 + 3 + read-write + + + ENUM_0x0 + System Tick 0 divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKSELX0 + Peripheral reset control register + SYSTICKCLKSEL + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + TRACECLKSEL + Trace clock source select + 0x268 + 32 + read-write + 0x7 + 0x7 + + + SEL + Trace clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Trace divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSEL0 + CTimer 0 clock source select + CTIMERCLKSEL + 0x26C + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 0 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX0 + Peripheral reset control register + CTIMERCLKSEL + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL1 + CTimer 1 clock source select + CTIMERCLKSEL + 0x270 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 1 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX1 + Peripheral reset control register + CTIMERCLKSEL + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL2 + CTimer 2 clock source select + CTIMERCLKSEL + 0x274 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 2 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX2 + Peripheral reset control register + CTIMERCLKSEL + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL3 + CTimer 3 clock source select + CTIMERCLKSEL + 0x278 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 3 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX3 + Peripheral reset control register + CTIMERCLKSEL + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL4 + CTimer 4 clock source select + CTIMERCLKSEL + 0x27C + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 4 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX4 + Peripheral reset control register + CTIMERCLKSEL + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + MAINCLKSELA + Main clock A source select + 0x280 + 32 + read-write + 0 + 0x7 + + + SEL + Main clock A source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + + + + + MAINCLKSELB + Main clock source select + 0x284 + 32 + read-write + 0 + 0x7 + + + SEL + Main clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main Clock A. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + PLL1 clock. + 0x2 + + + ENUM_0x3 + Oscillator 32 kHz clock. + 0x3 + + + + + + + CLKOUTSEL + CLKOUT clock source select + 0x288 + 32 + read-write + 0xF + 0xF + + + SEL + CLKOUT clock source select. + 0 + 4 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + ENUM_0xC + No clock. + 0xC + + + ENUM_0xD + No clock. + 0xD + + + ENUM_0xE + No clock. + 0xE + + + ENUM_0xF + No clock. + 0xF + + + + + + + PLL0CLKSEL + PLL0 clock source select + 0x290 + 32 + read-write + 0x7 + 0x7 + + + SEL + PLL0 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + Oscillator 32kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + PLL1CLKSEL + PLL1 clock source select + 0x294 + 32 + read-write + 0x7 + 0x7 + + + SEL + PLL1 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + Oscillator 32kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CANCLKSEL + CAN clock source select + 0x2A0 + 32 + read-write + 0x7 + 0x7 + + + SEL + CAN clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + CAN divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + ADCCLKSEL + ADC clock source select + 0x2A4 + 32 + read-write + 0x7 + 0x7 + + + SEL + ADC clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + FRO 96 MHz clock. + 0x2 + + + ENUM_0x4 + Xtal clock coming directly. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + USB0CLKSEL + FS USB clock source select + 0x2A8 + 32 + read-write + 0x7 + 0x7 + + + SEL + FS USB clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CLK32KCLKSEL + clock low speed source select for HS USB. + 0x2AC + 32 + read-write + 0 + 0x8 + + + SEL + clock low speed source select for HS USB. + 3 + 1 + read-write + + + ENUM_0x0 + Oscillator 32 kHz clock. + 0 + + + ENUM_0x1 + FRO1MHz_divided clock. + 0x1 + + + + + + + FCCLKSEL0 + Flexcomm Interface 0 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B0 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 0 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX0 + Peripheral reset control register + FCCLKSEL + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL1 + Flexcomm Interface 1 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B4 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 1 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX1 + Peripheral reset control register + FCCLKSEL + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL2 + Flexcomm Interface 2 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B8 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 2 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX2 + Peripheral reset control register + FCCLKSEL + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL3 + Flexcomm Interface 3 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2BC + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 3 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX3 + Peripheral reset control register + FCCLKSEL + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL4 + Flexcomm Interface 4 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C0 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 4 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX4 + Peripheral reset control register + FCCLKSEL + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL5 + Flexcomm Interface 5 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C4 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 5 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX5 + Peripheral reset control register + FCCLKSEL + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL6 + Flexcomm Interface 6 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C8 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 6 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX6 + Peripheral reset control register + FCCLKSEL + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL7 + Flexcomm Interface 7 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2CC + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 7 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX7 + Peripheral reset control register + FCCLKSEL + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + HSLSPICLKSEL + HS LSPI clock source select + 0x2D0 + 32 + read-write + 0x7 + 0x7 + + + SEL + HS LSPI clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + MCLKCLKSEL + MCLK clock source select + 0x2E0 + 32 + read-write + 0x7 + 0x7 + + + SEL + MCLK clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 96 MHz clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SCTCLKSEL + SCTimer/PWM clock source select + 0x2F0 + 32 + read-write + 0x7 + 0x7 + + + SEL + SCTimer/PWM clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKDIV0 + System Tick Timer divider for CPU0 + 0x300 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + TRACECLKDIV + TRACE clock divider + 0x308 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + CANCLKDIV + CAN clock divider + 0x30C + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + FLEXFRG0CTRL + Fractional rate divider for flexcomm 0 + FLEXFRGCTRL + 0x320 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL0 + Peripheral reset control register + FLEXFRGCTRL + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG1CTRL + Fractional rate divider for flexcomm 1 + FLEXFRGCTRL + 0x324 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL1 + Peripheral reset control register + FLEXFRGCTRL + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG2CTRL + Fractional rate divider for flexcomm 2 + FLEXFRGCTRL + 0x328 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL2 + Peripheral reset control register + FLEXFRGCTRL + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG3CTRL + Fractional rate divider for flexcomm 3 + FLEXFRGCTRL + 0x32C + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL3 + Peripheral reset control register + FLEXFRGCTRL + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG4CTRL + Fractional rate divider for flexcomm 4 + FLEXFRGCTRL + 0x330 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL4 + Peripheral reset control register + FLEXFRGCTRL + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG5CTRL + Fractional rate divider for flexcomm 5 + FLEXFRGCTRL + 0x334 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL5 + Peripheral reset control register + FLEXFRGCTRL + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG6CTRL + Fractional rate divider for flexcomm 6 + FLEXFRGCTRL + 0x338 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL6 + Peripheral reset control register + FLEXFRGCTRL + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG7CTRL + Fractional rate divider for flexcomm 7 + FLEXFRGCTRL + 0x33C + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL7 + Peripheral reset control register + FLEXFRGCTRL + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKDIV + System clock divider + 0x380 + 32 + read-write + 0 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + CLKOUTDIV + CLKOUT clock divider + 0x384 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + FROHFDIV + FRO_HF (96MHz) clock divider + 0x388 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + WDTCLKDIV + WDT clock divider + 0x38C + 32 + read-write + 0x40000000 + 0xE000003F + + + DIV + Clock divider value. + 0 + 6 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + ADCCLKDIV + ADC clock divider + 0x394 + 32 + read-write + 0x40000000 + 0xE0000007 + + + DIV + Clock divider value. + 0 + 3 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + USB0CLKDIV + USB0-FS Clock divider + 0x398 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + FRO1MCLKDIV + FRO1MHz Clock divider (FRO1M_divided) + 0x3A0 + 32 + read-write + 0x4000001F + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + MCLKDIV + I2S MCLK clock divider + 0x3AC + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + SCTCLKDIV + SCT/PWM clock divider + 0x3B4 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + PLL0CLKDIV + PLL0 clock divider + 0x3C4 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + CLOCKGENUPDATELOCKOUT + Control clock configuration registers access (like xxxDIV, xxxSEL) + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + CLOCKGENUPDATELOCKOUT + Control clock configuration registers access (for example, xxxDIV, xxxSEL). + 0 + 32 + read-write + + + FREEZE + all hardware clock configruration are freeze. + 0 + + + ENABLE + update all clock configuration. + 0x1 + + + + + + + FMCCR + FMC configuration register + 0x400 + 32 + read-write + 0x2000 + 0xFFFFFFFF + + + FETCHCFG + Instruction fetch configuration. + 0 + 2 + read-write + + + NOBUF + Instruction fetches from flash are not buffered. + 0 + + + ONEBUF + One buffer is used for all instruction fetches. + 0x1 + + + ALLBUF + All buffers may be used for instruction fetches. + 0x2 + + + + + DATACFG + Data read configuration. + 2 + 2 + read-write + + + NOBUF + Data accesses from flash are not buffered. + 0 + + + ONEBUF + One buffer is used for all data accesses. + 0x1 + + + ALLBUF + All buffers can be used for data accesses. + 0x2 + + + + + ACCEL + Acceleration enable. + 4 + 1 + read-write + + + DISABLE + Flash acceleration is disabled. + 0 + + + ENABLE + Flash acceleration is enabled. + 0x1 + + + + + PREFEN + Prefetch enable. + 5 + 1 + read-write + + + DISABLE + No instruction prefetch is performed. + 0 + + + ENABLE + Instruction prefetch is enabled. + 0x1 + + + + + PREFOVR + Prefetch override. + 6 + 1 + read-write + + + NORMAL + Any previously initiated prefetch will be completed. + 0 + + + OVERRIDE + Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. + 0x1 + + + + + FLASHTIM + Flash memory access time. + 12 + 4 + read-write + + + FLASHTIM0 + 1 system clock flash access time (for system clock rates up to 11 MHz). + 0 + + + FLASHTIM1 + 2 system clocks flash access time (for system clock rates up to 22 MHz). + 0x1 + + + FLASHTIM2 + 3 system clocks flash access time (for system clock rates up to 33 MHz). + 0x2 + + + FLASHTIM3 + 4 system clocks flash access time (for system clock rates up to 44 MHz). + 0x3 + + + FLASHTIM4 + 5 system clocks flash access time (for system clock rates up to 55 MHz). + 0x4 + + + FLASHTIM5 + 6 system clocks flash access time (for system clock rates up to 66 MHz). + 0x5 + + + FLASHTIM6 + 7 system clocks flash access time (for system clock rates up to 84 MHz). + 0x6 + + + FLASHTIM7 + 8 system clocks flash access time (for system clock rates up to 104 MHz). + 0x7 + + + FLASHTIM8 + 9 system clocks flash access time (for system clock rates up to 119 MHz). + 0x8 + + + FLASHTIM9 + 10 system clocks flash access time (for system clock rates up to 129 MHz). + 0x9 + + + FLASHTIM10 + 11 system clocks flash access time (for system clock rates up to 144 MHz). + 0xA + + + FLASHTIM11 + 12 system clocks flash access time (for system clock rates up to 150 MHz). + 0xB + + + + + + + USB0NEEDCLKCTRL + USB0-FS need clock control + 0x40C + 32 + read-write + 0 + 0x1F + + + AP_FS_DEV_NEEDCLK + USB0-FS Device USB0_NEEDCLK signal control:. + 0 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_FS_DEV_NEEDCLK + USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. + 1 + 1 + read-write + + + FALLING + Falling edge of device USB0_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of device USB0_NEEDCLK triggers wake-up. + 0x1 + + + + + AP_FS_HOST_NEEDCLK + USB0-FS Host USB0_NEEDCLK signal control:. + 2 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_FS_HOST_NEEDCLK + USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. + 3 + 1 + read-write + + + FALLING + Falling edge of device USB0_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of device USB0_NEEDCLK triggers wake-up. + 0x1 + + + + + + + USB0NEEDCLKSTAT + USB0-FS need clock status + 0x410 + 32 + read-write + 0 + 0x3 + + + DEV_NEEDCLK + USB0-FS Device USB0_NEEDCLK signal status:. + 0 + 1 + read-only + + + LOW + USB0-FS Device clock is low. + 0 + + + HIGH + USB0-FS Device clock is high. + 0x1 + + + + + HOST_NEEDCLK + USB0-FS Host USB0_NEEDCLK signal status:. + 1 + 1 + read-only + + + LOW + USB0-FS Host clock is low. + 0 + + + HIGH + USB0-FS Host clock is high. + 0x1 + + + + + + + FMCFLUSH + FMCflush control + 0x41C + 32 + write-only + 0 + 0xFFFFFFFF + + + FLUSH + Flush control + 0 + 1 + write-only + + + NO_FLUSH + No action is performed. + 0 + + + FLUSH + Flush the FMC buffer contents. + 0x1 + + + + + + + MCLKIO + MCLK control + 0x420 + 32 + read-write + 0 + 0x1 + + + MCLKIO + MCLK control. + 0 + 1 + read-write + + + INPUT + input mode. + 0 + + + OUTPUT + output mode. + 0x1 + + + + + + + USB1NEEDCLKCTRL + USB1-HS need clock control + 0x424 + 32 + read-write + 0x10 + 0x1F + + + AP_HS_DEV_NEEDCLK + USB1-HS Device need_clock signal control: + 0 + 1 + read-write + + + HW_CTRL + HOST_NEEDCLK is under hardware control. + 0 + + + FORCED + HOST_NEEDCLK is forced high. + 0x1 + + + + + POL_HS_DEV_NEEDCLK + USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + 1 + 1 + read-write + + + FALLING + Falling edge of DEV_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of DEV_NEEDCLK triggers wake-up. + 0x1 + + + + + AP_HS_HOST_NEEDCLK + USB1-HS Host need clock signal control: + 2 + 1 + read-write + + + HW_CTRL + HOST_NEEDCLK is under hardware control. + 0 + + + FORCED + HOST_NEEDCLK is forced high. + 0x1 + + + + + POL_HS_HOST_NEEDCLK + USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + 3 + 1 + read-write + + + FALLING + Falling edge of HOST_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of HOST_NEEDCLK triggers wake-up. + 0x1 + + + + + HS_DEV_WAKEUP_N + Software override of device controller PHY wake up logic. + 4 + 1 + read-write + + + FORCE_WUP + Forces USB1_PHY to wake-up. + 0 + + + NORMAL_WUP + Normal USB1_PHY behavior. + 0x1 + + + + + + + USB1NEEDCLKSTAT + USB1-HS need clock status + 0x428 + 32 + read-write + 0 + 0x3 + + + DEV_NEEDCLK + USB1-HS Device need_clock signal status:. + 0 + 1 + read-only + + + LOW + DEV_NEEDCLK is low. + 0 + + + HIGH + DEV_NEEDCLK is high. + 0x1 + + + + + HOST_NEEDCLK + USB1-HS Host need_clock signal status:. + 1 + 1 + read-only + + + LOW + HOST_NEEDCLK is low. + 0 + + + HIGH + HOST_NEEDCLK is high. + 0x1 + + + + + + + FLASHREMAP_SIZE + This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASHREMAP_SIZE + no description available + 0 + 32 + read-write + + + + + FLASHREMAP_SIZE_DP + This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security. + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASHREMAP_SIZE + no description available + 0 + 32 + read-write + + + + + FLASHREMAP_OFFSET + This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASHREMAP_OFFSET + no description available + 0 + 32 + read-write + + + + + FLASHREMAP_OFFSET_DP + This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security. + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASHREMAP_OFFSET + no description available + 0 + 32 + read-write + + + + + FLASHREMAP_LOCK + Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. + 0x45C + 32 + read-write + 0xC33CA55A + 0xFFFFFFFF + + + LOCK + Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. Any value other than 0xC33CA55A and 0x3CC35AA5 does not modify the state. + 0 + 32 + read-write + + + UNLOCK + Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is unlocked. + 0x3CC35AA5 + + + LOCK + Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is locked. + 0xC33CA55A + + + + + + + CASPER_CTRL + Control CASPER integration. + 0x470 + 32 + read-write + 0 + 0x1 + + + INTERLEAVE + Control RAM access for RAMX0 and RAMX1. + 0 + 1 + read-write + + + NORMAL + RAM access to RAMX0 and RAMX1 is consecutive. + 0 + + + INTERLEAVE + RAM access to RAMX0 and RAMX1 is interleaved. + 0x1 + + + + + + + PLL1CTRL + PLL1 550m control + 0x560 + 32 + read-write + 0 + 0x1FFFFFF + + + SELR + Bandwidth select R value. + 0 + 4 + read-write + + + SELI + Bandwidth select I value. + 4 + 6 + read-write + + + SELP + Bandwidth select P value. + 10 + 5 + read-write + + + BYPASSPLL + Bypass PLL input clock is sent directly to the PLL output (default). + 15 + 1 + read-write + + + USED + use PLL. + 0 + + + BYPASSED + PLL input clock is sent directly to the PLL output. + 0x1 + + + + + BYPASSPOSTDIV2 + bypass of the divide-by-2 divider in the post-divider. + 16 + 1 + read-write + + + USED + use the divide-by-2 divider in the post-divider. + 0 + + + BYPASSED + bypass of the divide-by-2 divider in the post-divider. + 0x1 + + + + + LIMUPOFF + limup_off = 1 in spread spectrum and fractional PLL applications. + 17 + 1 + read-write + + + BWDIRECT + control of the bandwidth of the PLL. + 18 + 1 + read-write + + + SYNC + the bandwidth is changed synchronously with the feedback-divider. + 0 + + + DIRECT + modify the bandwidth of the PLL directly. + 0x1 + + + + + BYPASSPREDIV + bypass of the pre-divider. + 19 + 1 + read-write + + + USED + use the pre-divider. + 0 + + + BYPASSED + bypass of the pre-divider. + 0x1 + + + + + BYPASSPOSTDIV + bypass of the post-divider. + 20 + 1 + read-write + + + USED + use the post-divider. + 0 + + + BYPASSED + bypass of the post-divider. + 0x1 + + + + + CLKEN + enable the output clock. + 21 + 1 + read-write + + + DISABLE + Disable the output clock. + 0 + + + ENABLE + Enable the output clock. + 0x1 + + + + + FRMEN + 1: free running mode. + 22 + 1 + read-write + + + FRMCLKSTABLE + free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + 23 + 1 + read-write + + + SKEWEN + Skew mode. + 24 + 1 + read-write + + + DISABLE + skewmode is disable. + 0 + + + ENABLE + skewmode is enable. + 0x1 + + + + + + + PLL1STAT + PLL1 550m status + 0x564 + 32 + read-write + 0 + 0x1F + + + LOCK + lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + 0 + 1 + read-only + + + PREDIVACK + pre-divider ratio change acknowledge. + 1 + 1 + read-only + + + FEEDDIVACK + feedback divider ratio change acknowledge. + 2 + 1 + read-only + + + POSTDIVACK + post-divider ratio change acknowledge. + 3 + 1 + read-only + + + FRMDET + free running detector output (active high). + 4 + 1 + read-only + + + + + PLL1NDEC + PLL1 550m N divider + 0x568 + 32 + read-write + 0 + 0x1FF + + + NDIV + pre-divider divider ratio (N-divider). + 0 + 8 + read-write + + + NREQ + pre-divider ratio change request. + 8 + 1 + read-write + + + + + PLL1MDEC + PLL1 550m M divider + 0x56C + 32 + read-write + 0 + 0x1FFFF + + + MDIV + feedback divider divider ratio (M-divider). + 0 + 16 + read-write + + + MREQ + feedback ratio change request. + 16 + 1 + read-write + + + + + PLL1PDEC + PLL1 550m P divider + 0x570 + 32 + read-write + 0 + 0x3F + + + PDIV + post-divider divider ratio (P-divider) + 0 + 5 + read-write + + + PREQ + feedback ratio change request. + 5 + 1 + read-write + + + + + PLL0CTRL + PLL0 550m control + 0x580 + 32 + read-write + 0 + 0x1FFFFFF + + + SELR + Bandwidth select R value. + 0 + 4 + read-write + + + SELI + Bandwidth select I value. + 4 + 6 + read-write + + + SELP + Bandwidth select P value. + 10 + 5 + read-write + + + BYPASSPLL + Bypass PLL input clock is sent directly to the PLL output (default). + 15 + 1 + read-write + + + USED + use PLL. + 0 + + + BYPASSED + Bypass PLL input clock is sent directly to the PLL output. + 0x1 + + + + + BYPASSPOSTDIV2 + bypass of the divide-by-2 divider in the post-divider. + 16 + 1 + read-write + + + USED + use the divide-by-2 divider in the post-divider. + 0 + + + BYPASSED + bypass of the divide-by-2 divider in the post-divider. + 0x1 + + + + + LIMUPOFF + limup_off = 1 in spread spectrum and fractional PLL applications. + 17 + 1 + read-write + + + BWDIRECT + Control of the bandwidth of the PLL. + 18 + 1 + read-write + + + SYNC + the bandwidth is changed synchronously with the feedback-divider. + 0 + + + DIRECT + modify the bandwidth of the PLL directly. + 0x1 + + + + + BYPASSPREDIV + bypass of the pre-divider. + 19 + 1 + read-write + + + USED + use the pre-divider. + 0 + + + BYPASSED + bypass of the pre-divider. + 0x1 + + + + + BYPASSPOSTDIV + bypass of the post-divider. + 20 + 1 + read-write + + + USED + use the post-divider. + 0 + + + BYPASSED + bypass of the post-divider. + 0x1 + + + + + CLKEN + enable the output clock. + 21 + 1 + read-write + + + DISABLE + disable the output clock. + 0 + + + ENABLE + enable the output clock. + 0x1 + + + + + FRMEN + free running mode. + 22 + 1 + read-write + + + DISABLE + free running mode is disable. + 0 + + + ENABLE + free running mode is enable. + 0x1 + + + + + FRMCLKSTABLE + free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + 23 + 1 + read-write + + + SKEWEN + skew mode. + 24 + 1 + read-write + + + DISABLE + skew mode is disable. + 0 + + + ENABLE + skew mode is enable. + 0x1 + + + + + + + PLL0STAT + PLL0 550m status + 0x584 + 32 + read-write + 0 + 0x1F + + + LOCK + lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + 0 + 1 + read-only + + + PREDIVACK + pre-divider ratio change acknowledge. + 1 + 1 + read-only + + + FEEDDIVACK + feedback divider ratio change acknowledge. + 2 + 1 + read-only + + + POSTDIVACK + post-divider ratio change acknowledge. + 3 + 1 + read-only + + + FRMDET + free running detector output (active high). + 4 + 1 + read-only + + + + + PLL0NDEC + PLL0 550m N divider + 0x588 + 32 + read-write + 0 + 0x1FF + + + NDIV + pre-divider divider ratio (N-divider). + 0 + 8 + read-write + + + NREQ + pre-divider ratio change request. + 8 + 1 + read-write + + + + + PLL0PDEC + PLL0 550m P divider + 0x58C + 32 + read-write + 0 + 0x3F + + + PDIV + post-divider divider ratio (P-divider) + 0 + 5 + read-write + + + PREQ + feedback ratio change request. + 5 + 1 + read-write + + + + + PLL0SSCG0 + PLL0 Spread Spectrum Wrapper control register 0 + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_LBS + input word of the wrapper bit 31 to 0. + 0 + 32 + read-write + + + + + PLL0SSCG1 + PLL0 Spread Spectrum Wrapper control register 1 + 0x594 + 32 + read-write + 0 + 0x1FFFFFFF + + + MD_MBS + input word of the wrapper bit 32. + 0 + 1 + read-write + + + MD_REQ + md change request. + 1 + 1 + read-write + + + MF + programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + 2 + 3 + read-write + + + MR + programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + 5 + 3 + read-write + + + MC + modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. + 8 + 2 + read-write + + + MDIV_EXT + to select an external mdiv value. + 10 + 16 + read-write + + + MREQ + to select an external mreq value. + 26 + 1 + read-write + + + DITHER + dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen. + 27 + 1 + read-write + + + SEL_EXT + to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + 28 + 1 + read-write + + + + + FUNCRETENTIONCTRL + Functional retention control register + 0x704 + 32 + read-write + 0x50C000 + 0xFFFFFF + + + FUNCRETENA + functional retention in power down only. + 0 + 1 + read-write + + + DISABLE + disable functional retention. + 0 + + + ENABLE + enable functional retention. + 0x1 + + + + + RET_START + Start address divided by 4 inside SRAMX bank. + 1 + 13 + read-write + + + RET_LENTH + lenth of Scan chains to save. + 14 + 10 + read-write + + + + + CPSTAT + CPU Status + 0x80C + 32 + read-write + 0 + 0xF + + + CPU0SLEEPING + The CPU0 sleeping state. + 0 + 1 + read-only + + + AWAKE + the CPU is not sleeping. + 0 + + + SLEEPING + the CPU is sleeping. + 0x1 + + + + + CPU0LOCKUP + The CPU0 lockup state. + 2 + 1 + read-only + + + AWAKE + the CPU is not in lockup. + 0 + + + SLEEPING + the CPU is in lockup. + 0x1 + + + + + + + BOOT_SEED_REG0 + boot seed (256-bit random value) + 0x920 + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG0 + no description available + 0 + 32 + read-write + + + + + BOOT_SEED_REG1 + boot seed (256-bit random value) + 0x924 + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG1 + no description available + 0 + 32 + read-write + + + + + BOOT_SEED_REG2 + boot seed (256-bit random value) + 0x928 + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG2 + no description available + 0 + 32 + read-write + + + + + BOOT_SEED_REG3 + boot seed (256-bit random value) + 0x92C + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG3 + no description available + 0 + 32 + read-write + + + + + BOOT_SEED_REG4 + boot seed (256-bit random value) + 0x930 + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG4 + no description available + 0 + 32 + read-write + + + + + BOOT_SEED_REG5 + boot seed (256-bit random value) + 0x934 + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG5 + no description available + 0 + 32 + read-write + + + + + BOOT_SEED_REG6 + boot seed (256-bit random value) + 0x938 + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG6 + no description available + 0 + 32 + read-write + + + + + BOOT_SEED_REG7 + boot seed (256-bit random value) + 0x93C + 32 + read-write + 0 + 0xFFFFFFFF + + + BOOT_SEED_REG7 + no description available + 0 + 32 + read-write + + + + + HMAC_REG0 + HMAC + 0x940 + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG0 + no description available + 0 + 32 + read-write + + + + + HMAC_REG1 + HMAC + 0x944 + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG1 + no description available + 0 + 32 + read-write + + + + + HMAC_REG2 + HMAC + 0x948 + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG2 + no description available + 0 + 32 + read-write + + + + + HMAC_REG3 + HMAC + 0x94C + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG3 + no description available + 0 + 32 + read-write + + + + + HMAC_REG4 + HMAC + 0x950 + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG4 + no description available + 0 + 32 + read-write + + + + + HMAC_REG5 + HMAC + 0x954 + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG5 + no description available + 0 + 32 + read-write + + + + + HMAC_REG6 + HMAC + 0x958 + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG6 + no description available + 0 + 32 + read-write + + + + + HMAC_REG7 + HMAC + 0x95C + 32 + read-write + 0 + 0xFFFFFFFF + + + HMAC_REG7 + no description available + 0 + 32 + read-write + + + + + BOOT_LOCK + Control write access to boot seed security registers. + 0x960 + 32 + read-write + 0 + 0x3 + + + LOCK_BOOT_SEED + Control write access to BOOT_SEED_REG registers. + 0 + 1 + read-write + + + LOCK + write access to all 8 registers BOOT_SEED_REG is locked. This register is write once. + 0x1 + + + + + LOCK_HMAC + Control write access to HMAC_REG registers. + 1 + 1 + read-write + + + LOCK + write access to all 8 registers HMAC_REG is locked. This register is write once. + 0x1 + + + + + + + CLOCK_CTRL + Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures + 0xA18 + 32 + read-write + 0x1 + 0x3FF + + + XTAL32MHZ_FREQM_ENA + Enable XTAL32MHz clock for Frequency Measure module. + 1 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO1MHZ_UTICK_ENA + Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + 2 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO12MHZ_FREQM_ENA + Enable FRO 12MHz clock for Frequency Measure module. + 3 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO_HF_FREQM_ENA + Enable FRO 96MHz clock for Frequency Measure module. + 4 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + CLKIN_ENA + Enable clock_in clock for clock module. + 5 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO1MHZ_CLK_ENA + Enable FRO 1MHz clock for clock muxing in clock gen. + 6 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + ANA_FRO12M_CLK_ENA + Enable FRO 12MHz clock for analog control of the FRO 192MHz. + 7 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + XO_CAL_CLK_ENA + Enable clock for cristal oscilator calibration. + 8 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + PLU_DEGLITCH_CLK_ENA + Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + 9 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + + + COMP_INT_CTRL + Comparator Interrupt control + 0xB10 + 32 + read-write + 0 + 0x3F + + + INT_ENABLE + Analog Comparator interrupt enable control:. + 0 + 1 + read-write + + + INT_DISABLE + interrupt disable. + 0 + + + INT_ENABLE + interrupt enable. + 0x1 + + + + + INT_CLEAR + Analog Comparator interrupt clear. + 1 + 1 + read-write + + + NONE + No effect. + 0 + + + CLEAR + Clear the interrupt. Self-cleared bit. + 0x1 + + + + + INT_CTRL + Comparator interrupt type selector:. + 2 + 3 + read-write + + + EDGE_DISABLE + The analog comparator interrupt edge sensitive is disabled. + 0 + + + LVL_DISABLE + The analog comparator interrupt level sensitive is disabled. + 0x1 + + + EDGE_RISING + analog comparator interrupt is rising edge sensitive. + 0x2 + + + LVL_HIGH + Analog Comparator interrupt is high level sensitive. + 0x3 + + + EDGE_FALLING + analog comparator interrupt is falling edge sensitive. + 0x4 + + + LVL_LOW + Analog Comparator interrupt is low level sensitive. + 0x5 + + + EDGE_BOTH + analog comparator interrupt is rising and falling edge sensitive. + 0x6 + + + LVL_DIS2 + The analog comparator interrupt level sensitive is disabled. + 0x7 + + + + + INT_SOURCE + Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + 5 + 1 + read-write + + + FILTER_INT + Select Analog Comparator filtered output as input for interrupt detection. + 0 + + + RAW_INT + Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. + 0x1 + + + + + + + COMP_INT_STATUS + Comparator Interrupt status + 0xB14 + 32 + read-write + 0 + 0x7 + + + STATUS + Interrupt status BEFORE Interrupt Enable. + 0 + 1 + read-only + + + NO_INT + no interrupt pending. + 0 + + + PENDING + interrupt pending. + 0x1 + + + + + INT_STATUS + Interrupt status AFTER Interrupt Enable. + 1 + 1 + read-only + + + NO_INT + no interrupt pending. + 0 + + + PENDING + interrupt pending. + 0x1 + + + + + VAL + comparator analog output. + 2 + 1 + read-only + + + SMALLER + P+ is smaller than P-. + 0 + + + GREATER + P+ is greater than P-. + 0x1 + + + + + + + AUTOCLKGATEOVERRIDE + Control automatic clock gating + 0xE04 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ROM + Control automatic clock gating of ROM controller. + 0 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAMX_CTRL + Control automatic clock gating of RAMX controller. + 1 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM0_CTRL + Control automatic clock gating of RAM0 controller. + 2 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM1_CTRL + Control automatic clock gating of RAM1 controller. + 3 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM2_CTRL + Control automatic clock gating of RAM2 controller. + 4 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYNC0_APB + Control automatic clock gating of synchronous bridge controller 0. + 7 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYNC1_APB + Control automatic clock gating of synchronous bridge controller 1. + 8 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + CRCGEN + Control automatic clock gating of CRCGEN controller. + 11 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SDMA0 + Control automatic clock gating of DMA0 controller. + 12 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SDMA1 + Control automatic clock gating of DMA1 controller. + 13 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + USB0 + Control automatic clock gating of USB controller. + 14 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYSCON + Control automatic clock gating of synchronous system controller registers bank. + 15 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + ENABLEUPDATE + The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + 16 + 16 + write-only + + + DISABLE + Bit Fields 0 - 15 of this register are not updated + 0 + + + ENABLE + Bit Fields 0 - 15 of this register are updated + 0xC0DE + + + + + + + GPIOPSYNC + Enable bypass of the first stage of synchonization inside GPIO_INT module + 0xE08 + 32 + read-write + 0 + 0x1 + + + PSYNC + Enable bypass of the first stage of synchonization inside GPIO_INT module. + 0 + 1 + read-write + + + USED + use the first stage of synchonization inside GPIO_INT module. + 0 + + + BYPASS + bypass of the first stage of synchonization inside GPIO_INT module. + 0x1 + + + + + + + HASHRESTHWKEY + Controls whether the HASH AES hardware secret key is restricted to use by secure code + 0xF88 + 32 + read-writeOnce + 0 + 0xFFFFFFFF + + + UNLOCKCODE + Code value that controls whether HASH AES hardware secret key is unlocked + 0 + 32 + read-writeOnce + + + UNLOCK + HASH AES hardware secret key is unlocked for use by non-secure code. Any other value means that the hardware secret key is restricted to use by secure code only. + 0xC33CA55A + + + + + + + DEBUG_LOCK_EN + Control write access to security registers. + 0xFA0 + 32 + read-write + 0x5 + 0xF + + + LOCK_ALL + Control write access to security registers. + 0 + 4 + read-write + + + DISABLE + Any other value than b1010: disable write access to all registers. + 0 + + + ENABLE + 1010: Enable write access to all registers. + 0xA + + + + + + + DEBUG_FEATURES + Cortex debug features control. + 0xFA4 + 32 + read-write + 0 + 0xFFF + + + CPU0_DBGEN + CPU0 Invasive debug control:. + 0 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CPU0_NIDEN + CPU0 Non Invasive debug control:. + 2 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CPU0_SPIDEN + CPU0 Secure Invasive debug control:. + 4 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CPU0_SPNIDEN + CPU0 Secure Non Invasive debug control:. + 6 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + + + DEBUG_FEATURES_DP + Cortex debug features control. (duplicate) + 0xFA8 + 32 + read-write + 0x555 + 0xFFF + + + CPU0_DBGEN + CPU0 (CPU0) Invasive debug control:. + 0 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CPU0_NIDEN + CPU0 Non Invasive debug control:. + 2 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CPU0_SPIDEN + CPU0 Secure Invasive debug control:. + 4 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CPU0_SPNIDEN + CPU0 Secure Non Invasive debug control:. + 6 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + + + SWD_ACCESS_CPU0 + This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0. + 0xFB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEC_CODE + CPU0 SWD-AP: 0x12345678. + 0 + 32 + read-write + + + DISABLE + CPU0 DAP is not allowed. Reading back register will be read as 0x5. + 0 + + + ENABLE + Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA. + 0x12345678 + + + + + + + KEY_BLOCK + block quiddikey/PUF all index. + 0xFBC + 32 + write-only + 0x3CC35AA5 + 0xFFFFFFFF + + + KEY_BLOCK + Write a value to block quiddikey/PUF all index. + 0 + 32 + write-only + + + + + DEBUG_AUTH_BEACON + Debug authentication BEACON register + 0xFC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BEACON + Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. + 0 + 32 + read-write + + + + + DEVICE_ID0 + Device ID + 0xFF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROM_REV_MINOR + ROM revision. + 20 + 4 + read-only + + + + + DIEID + Chip revision ID and Number + 0xFFC + 32 + read-only + 0x426B0 + 0xFFFFFF + + + REV_ID + Chip Metal Revision ID. + 0 + 4 + read-only + + + MCO_NUM_IN_DIE_ID + Chip Number 0x426B. + 4 + 20 + read-only + + + + + + + IOCON + I/O pin configuration (IOCON) + IOCON + 0x40001000 + + 0 + 0x100 + registers + + + + PIO0_0 + Digital I/O control for port 0 pins PIO0_0 + 0 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_1 + Digital I/O control for port 0 pins PIO0_1 + 0x4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_2 + Digital I/O control for port 0 pins PIO0_2 + 0x8 + 32 + read-write + 0x110 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_3 + Digital I/O control for port 0 pins PIO0_3 + 0xC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_4 + Digital I/O control for port 0 pins PIO0_4 + 0x10 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_5 + Digital I/O control for port 0 pins PIO0_5 + 0x14 + 32 + read-write + 0x120 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_6 + Digital I/O control for port 0 pins PIO0_6 + 0x18 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_7 + Digital I/O control for port 0 pins PIO0_7 + 0x1C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_8 + Digital I/O control for port 0 pins PIO0_8 + 0x20 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_9 + Digital I/O control for port 0 pins PIO0_9 + 0x24 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_10 + Digital I/O control for port 0 pins PIO0_10 + 0x28 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_11 + Digital I/O control for port 0 pins PIO0_11 + 0x2C + 32 + read-write + 0x116 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_12 + Digital I/O control for port 0 pins PIO0_12 + 0x30 + 32 + read-write + 0x126 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_13 + Digital I/O control for port 0 pins PIO0_13 + 0x34 + 32 + read-write + 0x5000 + 0xFFFF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + SSEL + Supply Selection bit. + 11 + 1 + read-write + + + SEL3V3 + 3V3 Signaling in I2C Mode. + 0 + + + SEL1V8 + 1V8 Signaling in I2C Mode. + 0x1 + + + + + FILTEROFF + Controls input glitch filter. + 12 + 1 + read-write + + + ENABLED + Filter enabled. + 0 + + + DISABLED + Filter disabled. + 0x1 + + + + + ECS + Pull-up current source enable in I2C mode. + 13 + 1 + read-write + + + DISABLED + Disabled. IO is in open drain cell. + 0 + + + ENABLED + Enabled. Pull resistor is conencted. + 0x1 + + + + + EGP + Switch between GPIO mode and I2C mode. + 14 + 1 + read-write + + + I2C_MODE + I2C mode. + 0 + + + GPIO_MODE + GPIO mode. + 0x1 + + + + + I2CFILTER + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + 15 + 1 + read-write + + + FAST_MODE + I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + 0 + + + STANDARD_MODE + I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + 0x1 + + + + + + + PIO0_14 + Digital I/O control for port 0 pins PIO0_14 + 0x38 + 32 + read-write + 0x5000 + 0xFFFF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + SSEL + Supply Selection bit. + 11 + 1 + read-write + + + SEL3V3 + 3V3 Signaling in I2C Mode. + 0 + + + SEL1V8 + 1V8 Signaling in I2C Mode. + 0x1 + + + + + FILTEROFF + Controls input glitch filter. + 12 + 1 + read-write + + + ENABLED + Filter enabled. + 0 + + + DISABLED + Filter disabled. + 0x1 + + + + + ECS + Pull-up current source enable in I2C mode. + 13 + 1 + read-write + + + DISABLED + Disabled. IO is in open drain cell. + 0 + + + ENABLED + Enabled. Pull resistor is conencted. + 0x1 + + + + + EGP + Switch between GPIO mode and I2C mode. + 14 + 1 + read-write + + + I2C_MODE + I2C mode. + 0 + + + GPIO_MODE + GPIO mode. + 0x1 + + + + + I2CFILTER + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + 15 + 1 + read-write + + + FAST_MODE + I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + 0 + + + STANDARD_MODE + I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + 0x1 + + + + + + + PIO0_15 + Digital I/O control for port 0 pins PIO0_15 + 0x3C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_16 + Digital I/O control for port 0 pins PIO0_16 + 0x40 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_17 + Digital I/O control for port 0 pins PIO0_17 + 0x44 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_18 + Digital I/O control for port 0 pins PIO0_18 + 0x48 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_19 + Digital I/O control for port 0 pins PIO0_19 + 0x4C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_20 + Digital I/O control for port 0 pins PIO0_20 + 0x50 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_21 + Digital I/O control for port 0 pins PIO0_21 + 0x54 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_22 + Digital I/O control for port 0 pins PIO0_22 + 0x58 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_23 + Digital I/O control for port 0 pins PIO0_23 + 0x5C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO0_24 + Digital I/O control for port 0 pins PIO0_24 + 0x60 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_25 + Digital I/O control for port 0 pins PIO0_25 + 0x64 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_26 + Digital I/O control for port 0 pins PIO0_26 + 0x68 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_27 + Digital I/O control for port 0 pins PIO0_27 + 0x6C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_28 + Digital I/O control for port 0 pins PIO0_28 + 0x70 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_29 + Digital I/O control for port 0 pins PIO0_29 + 0x74 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_30 + Digital I/O control for port 0 pins PIO0_30 + 0x78 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_31 + Digital I/O control for port 0 pins PIO0_31 + 0x7C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO1_0 + Digital I/O control for port 1 pins PIO1_0 + 0x80 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO1_1 + Digital I/O control for port 1 pins PIO1_1 + 0x84 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_2 + Digital I/O control for port 1 pins PIO1_2 + 0x88 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_3 + Digital I/O control for port 1 pins PIO1_3 + 0x8C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_4 + Digital I/O control for port 1 pins PIO1_4 + 0x90 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_5 + Digital I/O control for port 1 pins PIO1_5 + 0x94 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_6 + Digital I/O control for port 1 pins PIO1_6 + 0x98 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_7 + Digital I/O control for port 1 pins PIO1_7 + 0x9C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_8 + Digital I/O control for port 1 pins PIO1_8 + 0xA0 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO1_9 + Digital I/O control for port 1 pins PIO1_9 + 0xA4 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO1_10 + Digital I/O control for port 1 pins PIO1_10 + 0xA8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_11 + Digital I/O control for port 1 pins PIO1_11 + 0xAC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_12 + Digital I/O control for port 1 pins PIO1_12 + 0xB0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_13 + Digital I/O control for port 1 pins PIO1_13 + 0xB4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_14 + Digital I/O control for port 1 pins PIO1_14 + 0xB8 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO1_15 + Digital I/O control for port 1 pins PIO1_15 + 0xBC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_16 + Digital I/O control for port 1 pins PIO1_16 + 0xC0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_17 + Digital I/O control for port 1 pins PIO1_17 + 0xC4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_18 + Digital I/O control for port 1 pins PIO1_18 + 0xC8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_19 + Digital I/O control for port 1 pins PIO1_19 + 0xCC + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. + 10 + 1 + read-write + + + DISABLE + Analog switch is open. (disable) + 0 + + + ENABLE + Analog switch is closed. (enable) + 0x1 + + + + + + + PIO1_20 + Digital I/O control for port 1 pins PIO1_20 + 0xD0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_21 + Digital I/O control for port 1 pins PIO1_21 + 0xD4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_22 + Digital I/O control for port 1 pins PIO1_22 + 0xD8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_23 + Digital I/O control for port 1 pins PIO1_23 + 0xDC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_24 + Digital I/O control for port 1 pins PIO1_24 + 0xE0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_25 + Digital I/O control for port 1 pins PIO1_25 + 0xE4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_26 + Digital I/O control for port 1 pins PIO1_26 + 0xE8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_27 + Digital I/O control for port 1 pins PIO1_27 + 0xEC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_28 + Digital I/O control for port 1 pins PIO1_28 + 0xF0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_29 + Digital I/O control for port 1 pins PIO1_29 + 0xF4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_30 + Digital I/O control for port 1 pins PIO1_30 + 0xF8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_31 + Digital I/O control for port 1 pins PIO1_31 + 0xFC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + 0 + + + FAST + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Disable digital mode. Digital input set to 0. + 0 + + + DIGITAL + Enable Digital mode. Digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + + + GINT0 + Group GPIO input interrupt (GINT0/1) + GINT + GINT + 0x40002000 + + 0 + 0x48 + registers + + + GINT0 + 2 + + + + CTRL + GPIO grouped interrupt control register + 0 + 32 + read-write + 0 + 0x7 + + + INT + Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + 0 + 1 + read-write + + + NO_REQUEST + No request. No interrupt request is pending. + 0 + + + REQUEST_ACTIVE + Request active. Interrupt request is active. + 0x1 + + + + + COMB + Combine enabled inputs for group interrupt + 1 + 1 + read-write + + + OR + Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + 0 + + + AND + And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + 0x1 + + + + + TRIG + Group interrupt trigger + 2 + 1 + read-write + + + EDGE_TRIGGERED + Edge-triggered. + 0 + + + LEVEL_TRIGGERED + Level-triggered. + 0x1 + + + + + + + 2 + 0x4 + PORT_POL[%s] + GPIO grouped interrupt port 0 polarity register + 0x20 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + POL + Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. + 0 + 32 + read-write + + + + + 2 + 0x4 + PORT_ENA[%s] + GPIO grouped interrupt port 0 enable register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENA + Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. + 0 + 32 + read-write + + + + + + + GINT1 + Group GPIO input interrupt (GINT0/1) + GINT + 0x40003000 + + 0 + 0x48 + registers + + + GINT1 + 3 + + + + PINT + Pin interrupt and pattern match (PINT) + PINT + PINT + 0x40004000 + + 0 + 0x34 + registers + + + PIN_INT0 + 4 + + + PIN_INT1 + 5 + + + PIN_INT2 + 6 + + + PIN_INT3 + 7 + + + PIN_INT4 + 32 + + + PIN_INT5 + 33 + + + PIN_INT6 + 34 + + + PIN_INT7 + 35 + + + + ISEL + Pin Interrupt Mode register + 0 + 32 + read-write + 0 + 0xFF + + + PMODE + Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + 0 + 8 + read-write + + + + + IENR + Pin interrupt level or rising edge interrupt enable register + 0x4 + 32 + read-write + 0 + 0xFF + + + ENRL + Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. + 0 + 8 + read-write + + + + + SIENR + Pin interrupt level or rising edge interrupt set register + 0x8 + 32 + write-only + 0 + 0 + + + SETENRL + Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + 0 + 8 + write-only + + + + + CIENR + Pin interrupt level (rising edge interrupt) clear register + 0xC + 32 + write-only + 0 + 0 + + + CENRL + Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. + 0 + 8 + write-only + + + + + IENF + Pin interrupt active level or falling edge interrupt enable register + 0x10 + 32 + read-write + 0 + 0xFF + + + ENAF + Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. + 0 + 8 + read-write + + + + + SIENF + Pin interrupt active level or falling edge interrupt set register + 0x14 + 32 + write-only + 0 + 0 + + + SETENAF + Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. + 0 + 8 + write-only + + + + + CIENF + Pin interrupt active level or falling edge interrupt clear register + 0x18 + 32 + write-only + 0 + 0 + + + CENAF + Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. + 0 + 8 + write-only + + + + + RISE + Pin interrupt rising edge register + 0x1C + 32 + read-write + 0 + 0xFF + + + RDET + Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + 0 + 8 + read-write + + + + + FALL + Pin interrupt falling edge register + 0x20 + 32 + read-write + 0 + 0xFF + + + FDET + Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. + 0 + 8 + read-write + + + + + IST + Pin interrupt status register + 0x24 + 32 + read-write + 0 + 0xFF + + + PSTAT + Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + 0 + 8 + read-write + + + + + PMCTRL + Pattern match interrupt control register + 0x28 + 32 + read-write + 0 + 0xFF000003 + + + SEL_PMATCH + Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + 0 + 1 + read-write + + + PIN_INTERRUPT + Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + 0 + + + PATTERN_MATCH + Pattern match. Interrupts are driven in response to pattern matches. + 0x1 + + + + + ENA_RXEV + Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + 1 + 1 + read-write + + + DISABLED + Disabled. RXEV output to the CPU is disabled. + 0 + + + ENABLED + Enabled. RXEV output to the CPU is enabled. + 0x1 + + + + + PMAT + This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. + 24 + 8 + read-write + + + + + PMSRC + Pattern match interrupt bit-slice source register + 0x2C + 32 + read-write + 0 + 0xFFFFFF00 + + + SRC0 + Selects the input source for bit slice 0 + 8 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + 0x7 + + + + + SRC1 + Selects the input source for bit slice 1 + 11 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + 0x7 + + + + + SRC2 + Selects the input source for bit slice 2 + 14 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + 0x7 + + + + + SRC3 + Selects the input source for bit slice 3 + 17 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + 0x7 + + + + + SRC4 + Selects the input source for bit slice 4 + 20 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + 0x7 + + + + + SRC5 + Selects the input source for bit slice 5 + 23 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + 0x7 + + + + + SRC6 + Selects the input source for bit slice 6 + 26 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + 0x7 + + + + + SRC7 + Selects the input source for bit slice 7 + 29 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + 0x7 + + + + + + + PMCFG + Pattern match interrupt bit slice configuration register + 0x30 + 32 + read-write + 0 + 0xFFFFFF7F + + + PROD_ENDPTS0 + Determines whether slice 0 is an endpoint. + 0 + 1 + read-write + + + NO_EFFECT + No effect. Slice 0 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS1 + Determines whether slice 1 is an endpoint. + 1 + 1 + read-write + + + NO_EFFECT + No effect. Slice 1 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS2 + Determines whether slice 2 is an endpoint. + 2 + 1 + read-write + + + NO_EFFECT + No effect. Slice 2 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS3 + Determines whether slice 3 is an endpoint. + 3 + 1 + read-write + + + NO_EFFECT + No effect. Slice 3 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS4 + Determines whether slice 4 is an endpoint. + 4 + 1 + read-write + + + NO_EFFECT + No effect. Slice 4 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS5 + Determines whether slice 5 is an endpoint. + 5 + 1 + read-write + + + NO_EFFECT + No effect. Slice 5 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS6 + Determines whether slice 6 is an endpoint. + 6 + 1 + read-write + + + NO_EFFECT + No effect. Slice 6 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + CFG0 + Specifies the match contribution condition for bit slice 0. + 8 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG1 + Specifies the match contribution condition for bit slice 1. + 11 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG2 + Specifies the match contribution condition for bit slice 2. + 14 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG3 + Specifies the match contribution condition for bit slice 3. + 17 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG4 + Specifies the match contribution condition for bit slice 4. + 20 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG5 + Specifies the match contribution condition for bit slice 5. + 23 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG6 + Specifies the match contribution condition for bit slice 6. + 26 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG7 + Specifies the match contribution condition for bit slice 7. + 29 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + + + + + SECPINT + Pin interrupt and pattern match (PINT) + PINT + 0x40005000 + + 0 + 0x34 + registers + + + SEC_HYPERVISOR_CALL + 49 + + + SEC_GPIO_INT0_IRQ0 + 50 + + + SEC_GPIO_INT0_IRQ1 + 51 + + + SEC_VIO + 53 + + + + INPUTMUX + Input multiplexing (INPUT MUX) + INPUTMUX + 0x40006000 + + 0 + 0x7B4 + registers + + + + 7 + 0x4 + SCT0_INMUX[%s] + Input mux register for SCT0 input + 0 + 32 + read-write + 0x1F + 0x1F + + + INP_N + Input number to SCT0 inputs 0 to 6.. + 0 + 5 + read-write + + + val0 + SCT_GPI0 function selected from IOCON register + 0 + + + val1 + SCT_GPI1 function selected from IOCON register + 0x1 + + + val2 + SCT_GPI2 function selected from IOCON register + 0x2 + + + val3 + SCT_GPI3 function selected from IOCON register + 0x3 + + + val4 + SCT_GPI4 function selected from IOCON register + 0x4 + + + val5 + SCT_GPI5 function selected from IOCON register + 0x5 + + + val6 + SCT_GPI6 function selected from IOCON register + 0x6 + + + val7 + SCT_GPI7 function selected from IOCON register + 0x7 + + + val8 + T0_OUT0 ctimer 0 match[0] output + 0x8 + + + val9 + T1_OUT0 ctimer 1 match[0] output + 0x9 + + + val10 + T2_OUT0 ctimer 2 match[0] output + 0xA + + + val11 + T3_OUT0 ctimer 3 match[0] output + 0xB + + + val12 + T4_OUT0 ctimer 4 match[0] output + 0xC + + + val13 + ADC_IRQ interrupt request from ADC + 0xD + + + val14 + GPIOINT_BMATCH + 0xE + + + val15 + USB0_FRAME_TOGGLE + 0xF + + + val16 + USB1_FRAME_TOGGLE + 0x10 + + + val17 + COMP_OUTPUT output from analog comparator + 0x11 + + + val18 + I2S_SHARED_SCK[0] output from I2S pin sharing + 0x12 + + + val19 + I2S_SHARED_SCK[1] output from I2S pin sharing + 0x13 + + + val20 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x14 + + + val21 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x15 + + + val22 + ARM_TXEV interrupt event from cpu0 or cpu1 + 0x16 + + + val23 + DEBUG_HALTED from cpu0 or cpu1 + 0x17 + + + val24 + None + 0x18 + + + val24 + None + 0x19 + + + val24 + None + 0x1A + + + val24 + None + 0x1B + + + val24 + None + 0x1C + + + val24 + None + 0x1D + + + val24 + None + 0x1E + + + val24 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER0CAPTSEL[%s] + Capture select registers for TIMER0 inputs + 0x20 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER0 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + None + 0x11 + + + val18 + None + 0x12 + + + val19 + None + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER1CAPTSEL[%s] + Capture select registers for TIMER1 inputs + 0x40 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER1 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + None + 0x11 + + + val18 + None + 0x12 + + + val19 + None + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER2CAPTSEL[%s] + Capture select registers for TIMER2 inputs + 0x60 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER2 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + None + 0x11 + + + val18 + None + 0x12 + + + val19 + None + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 8 + 0x4 + PINTSEL[%s] + Pin interrupt select register + 0xC0 + 32 + read-write + 0x7F + 0x7F + + + INTPIN + Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + 0 + 7 + read-write + + + + + 23 + 0x4 + DMA0_ITRIG_INMUX[%s] + Trigger select register for DMA0 channel + 0xE0 + 32 + read-write + 0x1F + 0x1F + + + INP + Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + 0 + 5 + read-write + + + val0 + Pin interrupt 0 + 0 + + + val1 + Pin interrupt 1 + 0x1 + + + val2 + Pin interrupt 2 + 0x2 + + + val3 + Pin interrupt 3 + 0x3 + + + val4 + Timer CTIMER0 Match 0 + 0x4 + + + val5 + Timer CTIMER0 Match 1 + 0x5 + + + val6 + Timer CTIMER1 Match 0 + 0x6 + + + val7 + Timer CTIMER1 Match 1 + 0x7 + + + val8 + Timer CTIMER2 Match 0 + 0x8 + + + val9 + Timer CTIMER2 Match 1 + 0x9 + + + val10 + Timer CTIMER3 Match 0 + 0xA + + + val11 + Timer CTIMER3 Match 1 + 0xB + + + val12 + Timer CTIMER4 Match 0 + 0xC + + + val13 + Timer CTIMER4 Match 1 + 0xD + + + val14 + COMP_OUTPUT + 0xE + + + val15 + DMA0 output trigger mux 0 + 0xF + + + val16 + DMA0 output trigger mux 1 + 0x10 + + + val17 + DMA0 output trigger mux 1 + 0x11 + + + val18 + DMA0 output trigger mux 3 + 0x12 + + + val19 + SCT0 DMA request 0 + 0x13 + + + val20 + SCT0 DMA request 1 + 0x14 + + + val21 + HASH DMA RX trigger + 0x15 + + + val22 + None + 0x16 + + + val22 + None + 0x17 + + + val22 + None + 0x18 + + + val22 + None + 0x19 + + + val22 + None + 0x1A + + + val22 + None + 0x1B + + + val22 + None + 0x1C + + + val22 + None + 0x1D + + + val22 + None + 0x1E + + + val22 + None + 0x1F + + + + + + + 4 + 0x4 + DMA0_OTRIG_INMUX[%s] + DMA0 output trigger selection to become DMA0 trigger + 0x160 + 32 + read-write + 0x1F + 0x1F + + + INP + DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + 0 + 5 + read-write + + + + + FREQMEAS_REF + Selection for frequency measurement reference clock + 0x180 + 32 + read-write + 0x1F + 0x1F + + + CLKIN + Clock source number (decimal value) for frequency measure function reference clock: + 0 + 5 + read-write + + + VALUE0 + External main crystal oscilator (Clock_in). + 0 + + + VALUE1 + FRO 12MHz clock. + 0x1 + + + VALUE2 + FRO 96MHz clock. + 0x2 + + + VALUE3 + Watchdog oscillator / FRO1MHz clock. + 0x3 + + + VALUE4 + 32 kHz oscillator (32k_clk) clock. + 0x4 + + + VALUE5 + main clock (main_clock). + 0x5 + + + VALUE6 + FREQME_GPIO_CLK_A. + 0x6 + + + VALUE7 + FREQME_GPIO_CLK_B. + 0x7 + + + + + + + FREQMEAS_TARGET + Selection for frequency measurement target clock + 0x184 + 32 + read-write + 0x1F + 0x1F + + + CLKIN + Clock source number (decimal value) for frequency measure function target clock: + 0 + 5 + read-write + + + VALUE0 + External main crystal oscilator (Clock_in). + 0 + + + VALUE1 + FRO 12MHz clock. + 0x1 + + + VALUE2 + FRO 96MHz clock. + 0x2 + + + VALUE3 + Watchdog oscillator / FRO1MHz clock. + 0x3 + + + VALUE4 + 32 kHz oscillator (32k_clk) clock. + 0x4 + + + VALUE5 + main clock (main_clock). + 0x5 + + + VALUE6 + FREQME_GPIO_CLK_A. + 0x6 + + + VALUE7 + FREQME_GPIO_CLK_B. + 0x7 + + + + + + + 4 + 0x4 + TIMER3CAPTSEL[%s] + Capture select registers for TIMER3 inputs + 0x1A0 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER3 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + None + 0x11 + + + val18 + None + 0x12 + + + val19 + None + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER4CAPTSEL[%s] + Capture select registers for TIMER4 inputs + 0x1C0 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER4 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + None + 0x11 + + + val18 + None + 0x12 + + + val19 + None + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 2 + 0x4 + PINTSECSEL[%s] + Pin interrupt secure select register + 0x1E0 + 32 + read-write + 0x3F + 0x3F + + + INTPIN + Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + 0 + 6 + read-write + + + + + 10 + 0x4 + DMA1_ITRIG_INMUX[%s] + Trigger select register for DMA1 channel + 0x200 + 32 + read-write + 0xF + 0xF + + + INP + Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + 0 + 4 + read-write + + + val0 + Pin interrupt 0 + 0 + + + val1 + Pin interrupt 1 + 0x1 + + + val2 + Pin interrupt 2 + 0x2 + + + val3 + Pin interrupt 3 + 0x3 + + + val4 + Timer CTIMER0 Match 0 + 0x4 + + + val5 + Timer CTIMER0 Match 1 + 0x5 + + + val6 + Timer CTIMER2 Match 0 + 0x6 + + + val7 + Timer CTIMER4 Match 0 + 0x7 + + + val8 + DMA1 output trigger mux 0 + 0x8 + + + val9 + DMA1 output trigger mux 1 + 0x9 + + + val10 + DMA1 output trigger mux 2 + 0xA + + + val11 + DMA1 output trigger mux 3 + 0xB + + + val12 + SCT0 DMA request 0 + 0xC + + + val13 + SCT0 DMA request 1 + 0xD + + + val14 + HASH DMA RX trigger + 0xE + + + val15 + None + 0xF + + + + + + + 4 + 0x4 + DMA1_OTRIG_INMUX[%s] + DMA1 output trigger selection to become DMA1 trigger + 0x240 + 32 + read-write + 0xF + 0xF + + + INP + DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + 0 + 4 + read-write + + + + + DMA0_REQ_ENA + Enable DMA0 requests + 0x740 + 32 + read-write + 0x7FFFFF + 0x7FFFFF + + + REQ_ENA + Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + 0 + 23 + read-write + + + + + DMA0_REQ_ENA_SET + Set one or several bits in DMA0_REQ_ENA register + 0x748 + 32 + write-only + 0 + 0x7FFFFF + + + SET + Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + 0 + 23 + write-only + + + + + DMA0_REQ_ENA_CLR + Clear one or several bits in DMA0_REQ_ENA register + 0x750 + 32 + write-only + 0 + 0x7FFFFF + + + CLR + Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + 0 + 23 + write-only + + + + + DMA1_REQ_ENA + Enable DMA1 requests + 0x760 + 32 + read-write + 0x3FF + 0x3FF + + + REQ_ENA + Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + 0 + 10 + read-write + + + + + DMA1_REQ_ENA_SET + Set one or several bits in DMA1_REQ_ENA register + 0x768 + 32 + write-only + 0 + 0x3FF + + + SET + Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + 0 + 10 + write-only + + + + + DMA1_REQ_ENA_CLR + Clear one or several bits in DMA1_REQ_ENA register + 0x770 + 32 + write-only + 0 + 0x3FF + + + CLR + Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + 0 + 10 + write-only + + + + + DMA0_ITRIG_ENA + Enable DMA0 triggers + 0x780 + 32 + read-write + 0x3FFFFF + 0x3FFFFF + + + ITRIG_ENA + Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + 0 + 22 + read-write + + + + + DMA0_ITRIG_ENA_SET + Set one or several bits in DMA0_ITRIG_ENA register + 0x788 + 32 + write-only + 0 + 0x3FFFFF + + + SET + Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register + 0 + 22 + write-only + + + + + DMA0_ITRIG_ENA_CLR + Clear one or several bits in DMA0_ITRIG_ENA register + 0x790 + 32 + write-only + 0 + 0x3FFFFF + + + CLR + Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register + 0 + 22 + write-only + + + + + DMA1_ITRIG_ENA + Enable DMA1 triggers + 0x7A0 + 32 + read-write + 0x7FFF + 0x7FFF + + + ITRIG_ENA + Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + 0 + 15 + read-write + + + + + DMA1_ITRIG_ENA_SET + Set one or several bits in DMA1_ITRIG_ENA register + 0x7A8 + 32 + write-only + 0 + 0x7FFF + + + SET + Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register + 0 + 15 + write-only + + + + + DMA1_ITRIG_ENA_CLR + Clear one or several bits in DMA1_ITRIG_ENA register + 0x7B0 + 32 + write-only + 0 + 0x7FFF + + + CLR + Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register + 0 + 15 + write-only + + + + + + + CTIMER0 + Standard counter/timers (CTIMER0 to 4) + CTIMER + CTIMER + 0x40008000 + + 0 + 0x88 + registers + + + CTIMER0 + 10 + + + + IR + Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. + 0 + 32 + read-write + 0 + 0xFF + + + MR0INT + Interrupt flag for match channel 0. + 0 + 1 + read-write + + + MR1INT + Interrupt flag for match channel 1. + 1 + 1 + read-write + + + MR2INT + Interrupt flag for match channel 2. + 2 + 1 + read-write + + + MR3INT + Interrupt flag for match channel 3. + 3 + 1 + read-write + + + CR0INT + Interrupt flag for capture channel 0 event. + 4 + 1 + read-write + + + CR1INT + Interrupt flag for capture channel 1 event. + 5 + 1 + read-write + + + CR2INT + Interrupt flag for capture channel 2 event. + 6 + 1 + read-write + + + CR3INT + Interrupt flag for capture channel 3 event. + 7 + 1 + read-write + + + + + TCR + Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + 0x4 + 32 + read-write + 0 + 0x3 + + + CEN + Counter enable. + 0 + 1 + read-write + + + DISABLED + Disabled.The counters are disabled. + 0 + + + ENABLED + Enabled. The Timer Counter and Prescale Counter are enabled. + 0x1 + + + + + CRST + Counter reset. + 1 + 1 + read-write + + + DISABLED + Disabled. Do nothing. + 0 + + + ENABLED + Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + 0x1 + + + + + + + TC + Timer Counter + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCVAL + Timer counter value. + 0 + 32 + read-write + + + + + PR + Prescale Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRVAL + Prescale counter value. + 0 + 32 + read-write + + + + + PC + Prescale Counter + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCVAL + Prescale counter value. + 0 + 32 + read-write + + + + + MCR + Match Control Register + 0x14 + 32 + read-write + 0 + 0xF000FFF + + + MR0I + Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + 0 + 1 + read-write + + + MR0R + Reset on MR0: the TC will be reset if MR0 matches it. + 1 + 1 + read-write + + + MR0S + Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + 2 + 1 + read-write + + + MR1I + Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + 3 + 1 + read-write + + + MR1R + Reset on MR1: the TC will be reset if MR1 matches it. + 4 + 1 + read-write + + + MR1S + Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + 5 + 1 + read-write + + + MR2I + Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + 6 + 1 + read-write + + + MR2R + Reset on MR2: the TC will be reset if MR2 matches it. + 7 + 1 + read-write + + + MR2S + Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + 8 + 1 + read-write + + + MR3I + Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + 9 + 1 + read-write + + + MR3R + Reset on MR3: the TC will be reset if MR3 matches it. + 10 + 1 + read-write + + + MR3S + Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + 11 + 1 + read-write + + + MR0RL + Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 24 + 1 + read-write + + + MR1RL + Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 25 + 1 + read-write + + + MR2RL + Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 26 + 1 + read-write + + + MR3RL + Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 27 + 1 + read-write + + + + + 4 + 0x4 + MR[%s] + Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH + Timer counter match value. + 0 + 32 + read-write + + + + + CCR + Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + 0x28 + 32 + read-write + 0 + 0xFFF + + + CAP0RE + Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 0 + 1 + read-write + + + CAP0FE + Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 1 + 1 + read-write + + + CAP0I + Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + 2 + 1 + read-write + + + CAP1RE + Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 3 + 1 + read-write + + + CAP1FE + Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 4 + 1 + read-write + + + CAP1I + Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + 5 + 1 + read-write + + + CAP2RE + Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 6 + 1 + read-write + + + CAP2FE + Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 7 + 1 + read-write + + + CAP2I + Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + 8 + 1 + read-write + + + CAP3RE + Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 9 + 1 + read-write + + + CAP3FE + Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 10 + 1 + read-write + + + CAP3I + Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + 11 + 1 + read-write + + + + + 4 + 0x4 + CR[%s] + Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAP + Timer counter capture value. + 0 + 32 + read-only + + + + + EMR + External Match Register. The EMR controls the match function and the external match pins. + 0x3C + 32 + read-write + 0 + 0xFFF + + + EM0 + External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 0 + 1 + read-write + + + EM1 + External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 1 + 1 + read-write + + + EM2 + External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 2 + 1 + read-write + + + EM3 + External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 3 + 1 + read-write + + + EMC0 + External Match Control 0. Determines the functionality of External Match 0. + 4 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC1 + External Match Control 1. Determines the functionality of External Match 1. + 6 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC2 + External Match Control 2. Determines the functionality of External Match 2. + 8 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC3 + External Match Control 3. Determines the functionality of External Match 3. + 10 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + + + CTCR + Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + 0x70 + 32 + read-write + 0 + 0xFF + + + CTMODE + Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + 0 + 2 + read-write + + + TIMER + Timer Mode. Incremented every rising APB bus clock edge. + 0 + + + COUNTER_RISING_EDGE + Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + 0x1 + + + COUNTER_FALLING_EDGE + Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + 0x2 + + + COUNTER_DUAL_EDGE + Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + 0x3 + + + + + CINSEL + Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + 2 + 2 + read-write + + + CHANNEL_0 + Channel 0. CAPn.0 for CTIMERn + 0 + + + CHANNEL_1 + Channel 1. CAPn.1 for CTIMERn + 0x1 + + + CHANNEL_2 + Channel 2. CAPn.2 for CTIMERn + 0x2 + + + CHANNEL_3 + Channel 3. CAPn.3 for CTIMERn + 0x3 + + + + + ENCC + Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. + 4 + 1 + read-write + + + SELCC + Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. + 5 + 3 + read-write + + + CHANNEL_0_RISING + Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + 0 + + + CHANNEL_0_FALLING + Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + 0x1 + + + CHANNEL_1_RISING + Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + 0x2 + + + CHANNEL_1_FALLING + Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + 0x3 + + + CHANNEL_2_RISING + Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + 0x4 + + + CHANNEL_2_FALLING + Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + 0x5 + + + + + + + PWMC + PWM Control Register. This register enables PWM mode for the external match pins. + 0x74 + 32 + read-write + 0 + 0xF + + + PWMEN0 + PWM mode enable for channel0. + 0 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT0 is controlled by EM0. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT0. + 0x1 + + + + + PWMEN1 + PWM mode enable for channel1. + 1 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT01 is controlled by EM1. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT1. + 0x1 + + + + + PWMEN2 + PWM mode enable for channel2. + 2 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT2 is controlled by EM2. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT2. + 0x1 + + + + + PWMEN3 + PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + 3 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT3 is controlled by EM3. + 0 + + + PWM + PWM. PWM mode is enabled for CT132Bn_MAT3. + 0x1 + + + + + + + 4 + 0x4 + MSR[%s] + Match Shadow Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHADOW + Timer counter match shadow value. + 0 + 32 + read-write + + + + + + + CTIMER1 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40009000 + + 0 + 0x88 + registers + + + CTIMER1 + 11 + + + + CTIMER2 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40028000 + + 0 + 0x88 + registers + + + CTIMER2 + 36 + + + + CTIMER3 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40029000 + + 0 + 0x88 + registers + + + CTIMER3 + 13 + + + + CTIMER4 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x4002A000 + + 0 + 0x88 + registers + + + CTIMER4 + 37 + + + + WWDT + Windowed Watchdog Timer (WWDT) + WWDT + 0x4000C000 + + 0 + 0x1C + registers + + + WDT_BOD + 0 + + + + MOD + Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. + 0 + 32 + read-write + 0 + 0x3F + + + WDEN + Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. + 0 + 1 + read-write + + + STOP + Stop. The watchdog timer is stopped. + 0 + + + RUN + Run. The watchdog timer is running. + 0x1 + + + + + WDRESET + Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + 1 + 1 + read-write + + + INTERRUPT + Interrupt. A watchdog time-out will not cause a chip reset. + 0 + + + RESET + Reset. A watchdog time-out will cause a chip reset. + 0x1 + + + + + WDTOF + Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. + 2 + 1 + read-write + + + WDINT + Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + 3 + 1 + read-write + + + WDPROTECT + Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + 4 + 1 + read-write + + + FLEXIBLE + Flexible. The watchdog time-out value (TC) can be changed at any time. + 0 + + + THRESHOLD + Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + 0x1 + + + + + + + TC + Watchdog timer constant register. This 24-bit register determines the time-out value. + 0x4 + 32 + read-write + 0xFF + 0xFFFFFF + + + COUNT + Watchdog time-out value. + 0 + 24 + read-write + + + + + FEED + Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. + 0x8 + 32 + write-only + 0 + 0 + + + FEED + Feed value should be 0xAA followed by 0x55. + 0 + 8 + write-only + + + + + TV + Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. + 0xC + 32 + read-only + 0xFF + 0xFFFFFF + + + COUNT + Counter timer value. + 0 + 24 + read-only + + + + + WARNINT + Watchdog Warning Interrupt compare value. + 0x14 + 32 + read-write + 0 + 0x3FF + + + WARNINT + Watchdog warning interrupt compare value. + 0 + 10 + read-write + + + + + WINDOW + Watchdog Window compare value. + 0x18 + 32 + read-write + 0xFFFFFF + 0xFFFFFF + + + WINDOW + Watchdog window value. + 0 + 24 + read-write + + + + + + + MRT0 + Multi-Rate Timer (MRT) + MRT + 0x4000D000 + + 0 + 0xFC + registers + + + MRT0 + 9 + + + + 4 + 0x10 + CHANNEL[%s] + no description available + 0 + + INTVAL + MRT Time interval value register. This value is loaded into the TIMER register. + 0 + 32 + read-write + 0 + 0x80FFFFFF + + + IVALUE + Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. + 0 + 24 + read-write + + + LOAD + Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. + 31 + 1 + read-write + + + NO_FORCE_LOAD + No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. + 0 + + + FORCE_LOAD + Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + 0x1 + + + + + + + TIMER + MRT Timer register. This register reads the value of the down-counter. + 0x4 + 32 + read-only + 0xFFFFFF + 0xFFFFFF + + + VALUE + Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). + 0 + 24 + read-only + + + + + CTRL + MRT Control register. This register controls the MRT modes. + 0x8 + 32 + read-write + 0 + 0x7 + + + INTEN + Enable the TIMERn interrupt. + 0 + 1 + read-write + + + DISABLED + Disabled. TIMERn interrupt is disabled. + 0 + + + ENABLED + Enabled. TIMERn interrupt is enabled. + 0x1 + + + + + MODE + Selects timer mode. + 1 + 2 + read-write + + + REPEAT_INTERRUPT_MODE + Repeat interrupt mode. + 0 + + + ONE_SHOT_INTERRUPT_MODE + One-shot interrupt mode. + 0x1 + + + ONE_SHOT_STALL_MODE + One-shot stall mode. + 0x2 + + + + + + + STAT + MRT Status register. + 0xC + 32 + read-write + 0 + 0x7 + + + INTFLAG + Monitors the interrupt flag. + 0 + 1 + read-write + + + NO_PENDING_INTERRUPT + No pending interrupt. Writing a zero is equivalent to no operation. + 0 + + + PENDING_INTERRUPT + Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + 0x1 + + + + + RUN + Indicates the state of TIMERn. This bit is read-only. + 1 + 1 + read-write + + + IDLE_STATE + Idle state. TIMERn is stopped. + 0 + + + RUNNING + Running. TIMERn is running. + 0x1 + + + + + INUSE + Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. + 2 + 1 + read-write + + + NO + This channel is not in use. + 0 + + + YES + This channel is in use. + 0x1 + + + + + + + + MODCFG + Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. + 0xF0 + 32 + read-write + 0x184 + 0x800001FF + + + NOC + Identifies the number of channels in this MRT.(4 channels on this device.) + 0 + 4 + read-write + + + NOB + Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + 4 + 5 + read-write + + + MULTITASK + Selects the operating mode for the INUSE flags and the IDLE_CH register. + 31 + 1 + read-write + + + HARDWARE_STATUS_MODE + Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + 0 + + + MULTI_TASK_MODE + Multi-task mode. + 0x1 + + + + + + + IDLE_CH + Idle channel register. This register returns the number of the first idle channel. + 0xF4 + 32 + read-only + 0 + 0xF0 + + + CHAN + Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. + 4 + 4 + read-only + + + + + IRQ_FLAG + Global interrupt flag register + 0xF8 + 32 + read-write + 0 + 0xF + + + GFLAG0 + Monitors the interrupt flag of TIMER0. + 0 + 1 + read-write + + + NO_PENDING_INTERRUPT + No pending interrupt. Writing a zero is equivalent to no operation. + 0 + + + PENDING_INTERRUPT + Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + 0x1 + + + + + GFLAG1 + Monitors the interrupt flag of TIMER1. See description of channel 0. + 1 + 1 + read-write + + + GFLAG2 + Monitors the interrupt flag of TIMER2. See description of channel 0. + 2 + 1 + read-write + + + GFLAG3 + Monitors the interrupt flag of TIMER3. See description of channel 0. + 3 + 1 + read-write + + + + + + + UTICK0 + Micro-tick Timer (UTICK) + UTICK + 0x4000E000 + + 0 + 0x20 + registers + + + UTICK0 + 8 + + + + CTRL + Control register. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAYVAL + Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + 0 + 31 + read-write + + + REPEAT + Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + 31 + 1 + read-write + + + + + STAT + Status register. + 0x4 + 32 + read-write + 0 + 0x3 + + + INTR + Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. + 0 + 1 + read-write + + + ACTIVE + Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + 1 + 1 + read-write + + + + + CFG + Capture configuration register. + 0x8 + 32 + read-write + 0 + 0xF0F + + + CAPEN0 + Enable Capture 0. 1 = Enabled, 0 = Disabled. + 0 + 1 + read-write + + + CAPEN1 + Enable Capture 1. 1 = Enabled, 0 = Disabled. + 1 + 1 + read-write + + + CAPEN2 + Enable Capture 2. 1 = Enabled, 0 = Disabled. + 2 + 1 + read-write + + + CAPEN3 + Enable Capture 3. 1 = Enabled, 0 = Disabled. + 3 + 1 + read-write + + + CAPPOL0 + Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + 8 + 1 + read-write + + + CAPPOL1 + Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + 9 + 1 + read-write + + + CAPPOL2 + Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + 10 + 1 + read-write + + + CAPPOL3 + Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + 11 + 1 + read-write + + + + + CAPCLR + Capture clear register. + 0xC + 32 + write-only + 0 + 0 + + + CAPCLR0 + Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + 0 + 1 + write-only + + + CAPCLR1 + Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + 1 + 1 + write-only + + + CAPCLR2 + Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + 2 + 1 + write-only + + + CAPCLR3 + Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + 3 + 1 + write-only + + + + + 4 + 0x4 + CAP[%s] + Capture register . + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAP_VALUE + Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. + 0 + 31 + read-only + + + VALID + Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + 31 + 1 + read-only + + + + + + + ANACTRL + ANALOGCTRL + ANACTRL + 0x40013000 + + 0 + 0x108 + registers + + + + ANALOG_CTRL_CFG + Various Analog blocks configuration (like FRO 192MHz trimmings source ...) + 0 + 32 + read-write + 0 + 0x1 + + + FRO192M_TRIM_SRC + FRO192M trimming and 'Enable' source. + 0 + 1 + read-write + + + EFUSE + FRO192M trimming and 'Enable' comes from eFUSE. + 0 + + + FRO192MCTRL + FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + 0x1 + + + + + + + ANALOG_CTRL_STATUS + Analog Macroblock Identity registers, Flash Status registers + 0x4 + 32 + read-only + 0x50000000 + 0xF0003FFF + + + FLASH_PWRDWN + Flash Power Down status. + 12 + 1 + read-only + + + PWRUP + Flash is not in power down mode. + 0 + + + PWRDWN + Flash is in power down mode. + 0x1 + + + + + FLASH_INIT_ERROR + Flash initialization error status. + 13 + 1 + read-only + + + NOERROR + No error. + 0 + + + ERROR + At least one error occured during flash initialization.. + 0x1 + + + + + + + FREQ_ME_CTRL + Frequency Measure function control register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPVAL_SCALE + Frequency measure result /Frequency measur scale + 0 + 31 + read-write + + + PROG + Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0). + 31 + 1 + read-write + + + + + FRO192M_CTRL + 192MHz Free Running OScillator (FRO) Control register + 0x10 + 32 + read-write + 0x80D01A + 0xF3FFFFBF + + + ENA_12MHZCLK + 12 MHz clock control. + 14 + 1 + read-write + + + DISABLE + 12 MHz clock is disabled. + 0 + + + ENABLE + 12 MHz clock is enabled. + 0x1 + + + + + DAC_TRIM + Frequency trim. + 16 + 8 + read-write + + + USBCLKADJ + If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets. + 24 + 1 + read-write + + + USBMODCHG + If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. + 25 + 1 + read-only + + + ENA_96MHZCLK + 96 MHz clock control. + 30 + 1 + read-write + + + DISABLE + 96 MHz clock is disabled. + 0 + + + ENABLE + 96 MHz clock is enabled. + 0x1 + + + + + WRTRIM + This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + 31 + 1 + write-only + + + + + FRO192M_STATUS + 192MHz Free Running OScillator (FRO) Status register + 0x14 + 32 + read-write + 0x3 + 0x3 + + + CLK_VALID + Output clock valid signal. Indicates that CCO clock has settled. + 0 + 1 + read-only + + + NOCLKOUT + No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + 0 + + + CLKOUT + Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + 0x1 + + + + + ATB_VCTRL + CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal. + 1 + 1 + read-only + + + + + ADC_CTRL + General Purpose ADC VBAT Divider branch control + 0x18 + 32 + read-write + 0 + 0x1 + + + VBATDIVENABLE + Switch On/Off VBAT divider branch. + 0 + 1 + read-write + + + DISABLE + VBAT divider branch is disabled. + 0 + + + ENABLE + VBAT divider branch is enabled. + 0x1 + + + + + + + XO32M_CTRL + High speed Crystal Oscillator Control register + 0x20 + 32 + read-write + 0x21428A + 0x1FFFFFFE + + + SLAVE + Xo in slave mode. + 4 + 1 + read-write + + + OSC_CAP_IN + Tune capa banks of High speed Crystal Oscillator input pin + 8 + 7 + read-write + + + OSC_CAP_OUT + Tune capa banks of High speed Crystal Oscillator output pin + 15 + 7 + read-write + + + ACBUF_PASS_ENABLE + Bypass enable of XO AC buffer enable in pll and top level. + 22 + 1 + read-write + + + DISABLE + XO AC buffer bypass is disabled. + 0 + + + ENABLE + XO AC buffer bypass is enabled. + 0x1 + + + + + ENABLE_PLL_USB_OUT + Enable High speed Crystal oscillator output to USB HS PLL. + 23 + 1 + read-write + + + DISABLE + High speed Crystal oscillator output to USB HS PLL is disabled. + 0 + + + ENABLE + High speed Crystal oscillator output to USB HS PLL is enabled. + 0x1 + + + + + ENABLE_SYSTEM_CLK_OUT + Enable High speed Crystal oscillator output to CPU system. + 24 + 1 + read-write + + + DISABLE + High speed Crystal oscillator output to CPU system is disabled. + 0 + + + ENABLE + High speed Crystal oscillator output to CPU system is enabled. + 0x1 + + + + + + + XO32M_STATUS + High speed Crystal Oscillator Status register + 0x24 + 32 + read-only + 0 + 0x1 + + + XO_READY + Indicates XO out frequency statibilty. + 0 + 1 + read-only + + + NOT_STABLE + XO output frequency is not yet stable. + 0 + + + STABLE + XO output frequency is stable. + 0x1 + + + + + + + BOD_DCDC_INT_CTRL + Brown Out Detectors (BoDs) & DCDC interrupts generation control register + 0x30 + 32 + read-write + 0 + 0x3F + + + BODVBAT_INT_ENABLE + BOD VBAT interrupt control. + 0 + 1 + read-write + + + DISABLE + BOD VBAT interrupt is disabled. + 0 + + + ENABLE + BOD VBAT interrupt is enabled. + 0x1 + + + + + BODVBAT_INT_CLEAR + BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + 1 + 1 + read-write + + + BODCORE_INT_ENABLE + BOD CORE interrupt control. + 2 + 1 + read-write + + + DISABLE + BOD CORE interrupt is disabled. + 0 + + + ENABLE + BOD CORE interrupt is enabled. + 0x1 + + + + + BODCORE_INT_CLEAR + BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + 3 + 1 + read-write + + + DCDC_INT_ENABLE + DCDC interrupt control. + 4 + 1 + read-write + + + DISABLE + DCDC interrupt is disabled. + 0 + + + ENABLE + DCDC interrupt is enabled. + 0x1 + + + + + DCDC_INT_CLEAR + DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + 5 + 1 + read-write + + + + + BOD_DCDC_INT_STATUS + BoDs & DCDC interrupts status register + 0x34 + 32 + read-only + 0x12D + 0x1FF + + + BODVBAT_STATUS + BOD VBAT Interrupt status before Interrupt Enable. + 0 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODVBAT_INT_STATUS + BOD VBAT Interrupt status after Interrupt Enable. + 1 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODVBAT_VAL + Current value of BOD VBAT power status output. + 2 + 1 + read-only + + + NOT_OK + VBAT voltage level is below the threshold. + 0 + + + OK + VBAT voltage level is above the threshold. + 0x1 + + + + + BODCORE_STATUS + BOD CORE Interrupt status before Interrupt Enable. + 3 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODCORE_INT_STATUS + BOD CORE Interrupt status after Interrupt Enable. + 4 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODCORE_VAL + Current value of BOD CORE power status output. + 5 + 1 + read-only + + + NOT_OK + CORE voltage level is below the threshold. + 0 + + + OK + CORE voltage level is above the threshold. + 0x1 + + + + + DCDC_STATUS + DCDC Interrupt status before Interrupt Enable. + 6 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + DCDC_INT_STATUS + DCDC Interrupt status after Interrupt Enable. + 7 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + DCDC_VAL + Current value of DCDC power status output. + 8 + 1 + read-only + + + NOT_OK + DCDC output Voltage is below the targeted regulation level. + 0 + + + OK + DCDC output Voltage is above the targeted regulation level. + 0x1 + + + + + + + RINGO0_CTRL + First Ring Oscillator module control register. + 0x40 + 32 + read-write + 0x40 + 0x803F1FFF + + + SL + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + SWN_SWP + PN-Ringos (P-Transistor and N-Transistor processing) control. + 2 + 2 + read-write + + + NORMAL + Normal mode. + 0 + + + P_MONITOR + P-Monitor mode. Measure with weak P transistor. + 0x1 + + + N_MONITOR + P-Monitor mode. Measure with weak N transistor. + 0x2 + + + FORBIDDEN + Don't use. + 0x3 + + + + + PD + Ringo module Power control. + 4 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_ND0 + First NAND2-based ringo control. + 5 + 1 + read-write + + + DISABLE + First NAND2-based ringo is disabled. + 0 + + + ENABLE + First NAND2-based ringo is enabled. + 0x1 + + + + + E_ND1 + Second NAND2-based ringo control. + 6 + 1 + read-write + + + DISABLE + Second NAND2-based ringo is disabled. + 0 + + + ENABLE + Second NAND2-based ringo is enabled. + 0x1 + + + + + E_NR0 + First NOR2-based ringo control. + 7 + 1 + read-write + + + DISABLE + First NOR2-based ringo is disabled. + 0 + + + ENABLE + First NOR2-based ringo is enabled. + 0x1 + + + + + E_NR1 + Second NOR2-based ringo control. + 8 + 1 + read-write + + + DISABLE + Second NORD2-based ringo is disabled. + 0 + + + ENABLE + Second NORD2-based ringo is enabled. + 0x1 + + + + + E_IV0 + First Inverter-based ringo control. + 9 + 1 + read-write + + + DISABLE + First INV-based ringo is disabled. + 0 + + + ENABLE + First INV-based ringo is enabled. + 0x1 + + + + + E_IV1 + Second Inverter-based ringo control. + 10 + 1 + read-write + + + DISABLE + Second INV-based ringo is disabled. + 0 + + + ENABLE + Second INV-based ringo is enabled. + 0x1 + + + + + E_PN0 + First PN (P-Transistor and N-Transistor processing) monitor control. + 11 + 1 + read-write + + + DISABLE + First PN-based ringo is disabled. + 0 + + + ENABLE + First PN-based ringo is enabled. + 0x1 + + + + + E_PN1 + Second PN (P-Transistor and N-Transistor processing) monitor control. + 12 + 1 + read-write + + + DISABLE + Second PN-based ringo is disabled. + 0 + + + ENABLE + Second PN-based ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + RINGO1_CTRL + Second Ring Oscillator module control register. + 0x44 + 32 + read-write + 0x40 + 0x803F01FF + + + S + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + PD + Ringo module Power control. + 2 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_R24 + . + 3 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_R35 + . + 4 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M2 + Metal 2 (M2) monitor control. + 5 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M3 + Metal 3 (M3) monitor control. + 6 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M4 + Metal 4 (M4) monitor control. + 7 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M5 + Metal 5 (M5) monitor control. + 8 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + RINGO2_CTRL + Third Ring Oscillator module control register. + 0x48 + 32 + read-write + 0x40 + 0x803F01FF + + + S + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + PD + Ringo module Power control. + 2 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_R24 + . + 3 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_R35 + . + 4 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M2 + Metal 2 (M2) monitor control. + 5 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M3 + Metal 3 (M3) monitor control. + 6 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M4 + Metal 4 (M4) monitor control. + 7 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M5 + Metal 5 (M5) monitor control. + 8 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + LDO_XO32M + High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register + 0xB0 + 32 + read-write + 0x3A0 + 0x3FE + + + BYPASS + Activate LDO bypass. + 1 + 1 + read-write + + + DISABLE + Disable bypass mode (for normal operations). + 0 + + + ENABLE + Activate LDO bypass. + 0x1 + + + + + HIGHZ + . + 2 + 1 + read-write + + + NORMALMPEDANCE + Output in High normal state. + 0 + + + HIGHIMPEDANCE + Output in High Impedance state. + 0x1 + + + + + VOUT + Sets the LDO output level. + 3 + 3 + read-write + + + V_0P750 + 0.750 V. + 0 + + + V_0P775 + 0.775 V. + 0x1 + + + V_0P800 + 0.800 V. + 0x2 + + + V_0P825 + 0.825 V. + 0x3 + + + V_0P850 + 0.850 V. + 0x4 + + + V_0P875 + 0.875 V. + 0x5 + + + V_0P900 + 0.900 V. + 0x6 + + + V_0P925 + 0.925 V. + 0x7 + + + + + IBIAS + Adjust the biasing current. + 6 + 2 + read-write + + + STABMODE + Stability configuration. + 8 + 2 + read-write + + + + + AUX_BIAS + AUX_BIAS + 0xB4 + 32 + read-write + 0x703A0 + 0x3FFFFE + + + VREF1VENABLE + Control output of 1V reference voltage. + 1 + 1 + read-write + + + DISABLE + Output of 1V reference voltage buffer is bypassed. + 0 + + + ENABLE + Output of 1V reference voltage is enabled. + 0x1 + + + + + ITRIM + current trimming control word. + 2 + 5 + read-write + + + PTATITRIM + current trimming control word for ptat current. + 7 + 5 + read-write + + + VREF1VTRIM + voltage trimming control word. + 12 + 5 + read-write + + + VREF1VCURVETRIM + Control bit to configure trimming state of mirror. + 17 + 3 + read-write + + + ITRIMCTRL0 + Control bit to configure trimming state of mirror. + 20 + 1 + read-write + + + ITRIMCTRL1 + Control bit to configure trimming state of mirror. + 21 + 1 + read-write + + + + + DUMMY_CTRL + Dummy Control bus to analog modules + 0xF8 + 32 + read-write + 0 + 0xFF7 + + + XO32M_ADC_CLK_MODE + Control High speed Crystal oscillator mode of the ADC clock. + 10 + 2 + read-write + + + DISABLE + High speed Crystal oscillator output to ADC is disabled. + 0 + + + XO_ADC_ENABLE + High speed Crystal oscillator output to ADC is enable. + 0x1 + + + + + + + USBHS_PHY_CTRL + USB High Speed Phy Control + 0x100 + 32 + read-write + 0x8 + 0xF + + + usb_vbusvalid_ext + Override value for Vbus if using external detectors. + 0 + 1 + read-write + + + usb_id_ext + Override value for ID if using external detectors. + 1 + 1 + read-write + + + iso_atx + . + 3 + 1 + read-write + + + + + USBHS_PHY_TRIM + USB High Speed Phy Trim values + 0x104 + 32 + read-write + 0 + 0xFFFFFF + + + trim_usb_reg_env_tail_adj_vd + Adjusts time constant of HS RX squelch (envelope) comparator. + 0 + 2 + read-write + + + trim_usbphy_tx_d_cal + . + 2 + 4 + read-write + + + trim_usbphy_tx_cal45dp + . + 6 + 5 + read-write + + + trim_usbphy_tx_cal45dm + . + 11 + 5 + read-write + + + trim_usb2_refbias_tst + . + 16 + 2 + read-write + + + trim_usb2_refbias_vbgadj + . + 18 + 3 + read-write + + + trim_pll_ctrl0_div_sel + . + 21 + 3 + read-write + + + + + + + PMC + PMC + PMC + 0x40020000 + + 0 + 0xD8 + registers + + + ACMP + 24 + + + + STATUS + Power Management Controller FSM (Finite State Machines) status + 0x4 + 32 + read-write + 0 + 0xF00FFFFF + + + FSMMAIN + Power Management Controller Main Finite State Machine (FSM) status. + 0 + 3 + read-only + + + FSMMAIN_POWERUP + POWER UP : The IC is powering up. + 0 + + + FSMMAIN_ACTIVE + ACTIVE : Power up is completed. The IC is in normal functional operation mode. + 0x1 + + + FSMMAIN_POWERDOWN + POWER DOWN : the IC has entered POWER DOWN mode. + 0x2 + + + FSMMAIN_DEEPSLEEP + DEEP SLEEP: The IC has entered DEEP SLEEP mode. + 0x3 + + + FSMMAIN_DEEPPOWERDOWN + DEEP POWER DOWN : The IC entred DEEP POWER DOWN mode. + 0x6 + + + FSMMAIN_DFT_ACTIVE + IC Structural TEST Mode : The IC has entered in IC Test mode. + 0x7 + + + + + FSMPWUP + POWER UP Finite State Machine (FSM) status. + 3 + 4 + read-only + + + FSMDSLP + DEEP SLEEP Finite State Machine (FSM) status. + 7 + 4 + read-only + + + FSMPWDN + POWER DOWN Finite State Machine (FSM) status. + 11 + 4 + read-only + + + FSMDPWD + DEEP POWER DOWN Finite State Machine (FSM) status. + 15 + 3 + read-only + + + BOOTMODE + Latest IC Boot cause:. + 18 + 2 + read-only + + + POWERUP + Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + 0 + + + DEEPSLEEP + Latest IC boot was from DEEP SLEEP low power mode.. + 0x1 + + + POWERDOWN + Latest IC boot was from POWER DOWN low power mode.. + 0x2 + + + DEEPPOWERDOWN + Latest IC boot was from DEEP POWER DOWN low power mode.. + 0x3 + + + + + WAFERTESTDONEVECT + Indicates cuurent status of wafer test level. + 28 + 4 + read-only + + + + + RESETCTRL + Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x8 + 32 + read-write + 0x50000050 + 0xF00000F9 + + + DPDWAKEUPRESETENABLE + Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + 0 + 1 + read-write + + + DISABLE + Reset event from DEEP POWER DOWN mode is disable. + 0 + + + ENABLE + Reset event from DEEP POWER DOWN mode is enable. + 0x1 + + + + + SWRRESETENABLE + Software reset enable. + 3 + 1 + read-write + + + DISABLE + Software reset is disable. + 0 + + + ENABLE + Software reset is enable. + 0x1 + + + + + BODVBATRESETENA_SECURE + BOD VBAT reset enable. + 4 + 2 + read-write + + + ENABLE + Any other value than b10, BOD VBAT reset is enable. + 0x1 + + + DISABLE + BOD VBAT reset is disable. + 0x2 + + + + + BODCORERESETENA_SECURE + BOD Core reset enable. + 6 + 2 + read-write + + + ENABLE + Any other value than b10, BOD Core reset is enable. + 0x1 + + + DISABLE + BOD Core reset is disable. + 0x2 + + + + + BODVBATRESETENA_SECURE_DP + BOD VBAT reset enable. + 28 + 2 + read-write + + + ENABLE + Any other value than b10, BOD VBAT reset is enable. + 0x1 + + + DISABLE + BOD VBAT reset is disable. + 0x2 + + + + + BODCORERESETENA_SECURE_DP + BOD Core reset enable. + 30 + 2 + read-write + + + ENABLE + Any other value than b10, BOD Core reset is enable. + 0x1 + + + DISABLE + BOD Core reset is disable. + 0x2 + + + + + + + DCDC0 + DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x10 + 32 + read-write + 0x10C4E68 + 0x7FFFFFF + + + RC + Constant On-Time calibration. + 0 + 6 + read-write + + + ICOMP + Select the type of ZCD comparator. + 6 + 2 + read-write + + + ISEL + Alter Internal biasing currents. + 8 + 2 + read-write + + + ICENABLE + Selection of auto scaling of COT period with variations in VDD. + 10 + 1 + read-write + + + TMOS + One-shot generator reference current trimming signal. + 11 + 5 + read-write + + + DISABLEISENSE + Disable Current sensing. + 16 + 1 + read-write + + + VOUT + Set output regulation voltage. + 17 + 4 + read-write + + + V_DCDC_0P950 + 0.95 V. + 0 + + + V_DCDC_0P975 + 0.975 V. + 0x1 + + + V_DCDC_1P000 + 1 V. + 0x2 + + + V_DCDC_1P025 + 1.025 V. + 0x3 + + + V_DCDC_1P050 + 1.05 V. + 0x4 + + + V_DCDC_1P075 + 1.075 V. + 0x5 + + + V_DCDC_1P100 + 1.1 V. + 0x6 + + + V_DCDC_1P125 + 1.125 V. + 0x7 + + + V_DCDC_1P150 + 1.15 V. + 0x8 + + + V_DCDC_1P175 + 1.175 V. + 0x9 + + + V_DCDC_1P200 + 1.2 V. + 0xA + + + + + SLICINGENABLE + Enable staggered switching of power switches. + 21 + 1 + read-write + + + INDUCTORCLAMPENABLE + Enable shorting of Inductor during PFM idle time. + 22 + 1 + read-write + + + VOUT_PWD + Set output regulation voltage during Deep Sleep. + 23 + 4 + read-write + + + + + DCDC1 + DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x14 + 32 + read-write + 0x1803A98 + 0xFFFFFFFF + + + RTRIMOFFET + Adjust the offset voltage of BJT based comparator. + 0 + 4 + read-write + + + RSENSETRIM + Adjust Max inductor peak current limiting. + 4 + 4 + read-write + + + DTESTENABLE + Enable Digital test signals. + 8 + 1 + read-write + + + SETCURVE + Bandgap calibration parameter. + 9 + 2 + read-write + + + SETDC + Bandgap calibration parameter. + 11 + 4 + read-write + + + DTESTSEL + Select the output signal for test. + 15 + 3 + read-write + + + ISCALEENABLE + Modify COT behavior. + 18 + 1 + read-write + + + FORCEBYPASS + Force bypass mode. + 19 + 1 + read-write + + + TRIMAUTOCOT + Change the scaling ratio of the feedforward compensation. + 20 + 4 + read-write + + + FORCEFULLCYCLE + Force full PFM PMOS and NMOS cycle. + 24 + 1 + read-write + + + LCENABLE + Change the range of the peak detector of current inside the inductor. + 25 + 1 + read-write + + + TOFF + Constant Off-Time calibration input. + 26 + 5 + read-write + + + TOFFENABLE + Enable Constant Off-Time feature. + 31 + 1 + read-write + + + + + LDOPMU + Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x1C + 32 + read-write + 0x10EF718 + 0x31FFFFF + + + VADJ + Sets the Always-On domain LDO output level. + 0 + 5 + read-write + + + V_1P220 + 1.22 V. + 0 + + + V_0P700 + 0.7 V. + 0x1 + + + V_0P725 + 0.725 V. + 0x2 + + + V_0P750 + 0.75 V. + 0x3 + + + V_0P775 + 0.775 V. + 0x4 + + + V_0P800 + 0.8 V. + 0x5 + + + V_0P825 + 0.825 V. + 0x6 + + + V_0P850 + 0.85 V. + 0x7 + + + V_0P875 + 0.875 V. + 0x8 + + + V_0P900 + 0.9 V. + 0x9 + + + V_0P960 + 0.96 V. + 0xA + + + V_0P970 + 0.97 V. + 0xB + + + V_0P980 + 0.98 V. + 0xC + + + V_0P990 + 0.99 V. + 0xD + + + V_1P000 + 1 V. + 0xE + + + V_1P010 + 1.01 V. + 0xF + + + V_1P020 + 1.02 V. + 0x10 + + + V_1P030 + 1.03 V. + 0x11 + + + V_1P040 + 1.04 V. + 0x12 + + + V_1P050 + 1.05 V. + 0x13 + + + V_1P060 + 1.06 V. + 0x14 + + + V_1P070 + 1.07 V. + 0x15 + + + V_1P080 + 1.08 V. + 0x16 + + + V_1P090 + 1.09 V. + 0x17 + + + V_1P100 + 1.1 V. + 0x18 + + + V_1P110 + 1.11 V. + 0x19 + + + V_1P120 + 1.12 V. + 0x1A + + + V_1P130 + 1.13 V. + 0x1B + + + V_1P140 + 1.14 V. + 0x1C + + + V_1P150 + 1.15 V. + 0x1D + + + V_1P160 + 1.16 V. + 0x1E + + + V_1P220_1 + 1.22 V. + 0x1F + + + + + VADJ_PWD + Sets the Always-On domain LDO output level in all power down modes. + 5 + 5 + read-write + + + VADJ_BOOST + Sets the Always-On domain LDO Boost output level. + 10 + 5 + read-write + + + VADJ_BOOST_PWD + Sets the Always-On domain LDO Boost output level in all power down modes. + 15 + 5 + read-write + + + BLEED + Controls LDOMEM bleed current. + 20 + 1 + read-write + + + DISABLE + Bleed current is disable. + 0 + + + ENABLE + Bleed current is enable. + 0x1 + + + + + BOOST_ENA + Control the LDO AO boost mode in ACTIVE mode. + 24 + 1 + read-write + + + DISABLE + LDO AO Boost Mode is disable. + 0 + + + ENABLE + LDO AO Boost Mode is enable. + 0x1 + + + + + BOOST_ENA_PWD + Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + 25 + 1 + read-write + + + DISABLE + LDO AO Boost Mode is disable. + 0 + + + ENABLE + LDO AO Boost Mode is enable. + 0x1 + + + + + + + BODVBAT + VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] + 0x30 + 32 + read-write + 0x47 + 0x7F + + + TRIGLVL + BoD trigger level. + 0 + 5 + read-write + + + V_1P00 + 1.00 V. + 0 + + + V_1P10 + 1.10 V. + 0x1 + + + V_1P20 + 1.20 V. + 0x2 + + + V_1P30 + 1.30 V. + 0x3 + + + V_1P40 + 1.40 V. + 0x4 + + + V_1P50 + 1.50 V. + 0x5 + + + V_1P60 + 1.60 V. + 0x6 + + + V_1P65 + 1.65 V. + 0x7 + + + V_1P70 + 1.70 V. + 0x8 + + + V_1P75 + 1.75 V. + 0x9 + + + V_1P80 + 1.80 V. + 0xA + + + V_1P90 + 1.90 V. + 0xB + + + V_2P00 + 2.00 V. + 0xC + + + V_2P10 + 2.10 V. + 0xD + + + V_2P20 + 2.20 V. + 0xE + + + V_2P30 + 2.30 V. + 0xF + + + V_2P40 + 2.40 V. + 0x10 + + + V_2P50 + 2.50 V. + 0x11 + + + V_2P60 + 2.60 V. + 0x12 + + + V_2P70 + 2.70 V. + 0x13 + + + V_2P80 + 2.806 V. + 0x14 + + + V_2P90 + 2.90 V. + 0x15 + + + V_3P00 + 3.00 V. + 0x16 + + + V_3P10 + 3.10 V. + 0x17 + + + V_3P20 + 3.20 V. + 0x18 + + + V_3P30_2 + 3.30 V. + 0x19 + + + V_3P30_3 + 3.30 V. + 0x1A + + + V_3P30_4 + 3.30 V. + 0x1B + + + V_3P30_5 + 3.30 V. + 0x1C + + + V_3P30_6 + 3.30 V. + 0x1D + + + V_3P30_7 + 3.30 V. + 0x1E + + + V_3P30_8 + 3.30 V. + 0x1F + + + + + HYST + BoD Hysteresis control. + 5 + 2 + read-write + + + HYST_25MV + 25 mV. + 0 + + + HYST_50MV + 50 mV. + 0x1 + + + HYST_75MV + 75 mV. + 0x2 + + + HYST_100MV + 100 mV. + 0x3 + + + + + + + REFFASTWKUP + Analog References fast wake-up Control register [Reset by: PoR] + 0x40 + 32 + read-write + 0x1 + 0x3 + + + LPWKUP + Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . + 0 + 1 + read-write + + + DISABLE + Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + 0 + + + ENABLE + Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. + 0x1 + + + + + HWWKUP + Analog References fast wake-up in case of Hardware Pin reset: . + 1 + 1 + read-write + + + DISABLE + Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + 0 + + + ENABLE + Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + 0x1 + + + + + + + XTAL32K + 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] + 0x4C + 32 + read-write + 0x204052 + 0x3FFFFFE + + + IREF + reference output current selection inputs. + 1 + 2 + read-write + + + TEST + Oscillator Test Mode. + 3 + 1 + read-write + + + IBIAS + bias current selection inputs. + 4 + 2 + read-write + + + AMPL + oscillator amplitude selection inputs. + 6 + 2 + read-write + + + CAPBANKIN + Capa bank setting input. + 8 + 7 + read-write + + + CAPBANKOUT + Capa bank setting output. + 15 + 7 + read-write + + + CAPTESTSTARTSRCSEL + Source selection for xo32k_captest_start_ao_set. + 22 + 1 + read-write + + + CAPSTART + Sourced from CAPTESTSTART. + 0 + + + CALIB + Sourced from calibration. + 0x1 + + + + + CAPTESTSTART + Start test. + 23 + 1 + read-write + + + CAPTESTENABLE + Enable signal for cap test. + 24 + 1 + read-write + + + CAPTESTOSCINSEL + Select the input for test. + 25 + 1 + read-write + + + OSCOUT + Oscillator output pin (osc_out). + 0 + + + OSCIN + Oscillator input pin (osc_in). + 0x1 + + + + + + + COMP + Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x50 + 32 + read-write + 0xA + 0xFF7FFE + + + HYST + Hysteris when hyst = '1'. + 1 + 1 + read-write + + + DISABLE + Hysteresis is disable. + 0 + + + ENABLE + Hysteresis is enable. + 0x1 + + + + + VREFINPUT + Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + 2 + 1 + read-write + + + INTERNALREF + Select internal VREF. + 0 + + + VDDA + Select VDDA. + 0x1 + + + + + LOWPOWER + Low power mode. + 3 + 1 + read-write + + + HIGHSPEED + High speed mode. + 0 + + + LOWSPEED + Low power mode (Low speed). + 0x1 + + + + + PMUX + Control word for P multiplexer:. + 4 + 3 + read-write + + + VREF + VREF (See fiedl VREFINPUT). + 0 + + + CMP0_A + Pin P0_0. + 0x1 + + + CMP0_B + Pin P0_9. + 0x2 + + + CMP0_C + Pin P0_18. + 0x3 + + + CMP0_D + Pin P1_14. + 0x4 + + + CMP0_E + Pin P2_23. + 0x5 + + + + + NMUX + Control word for N multiplexer:. + 7 + 3 + read-write + + + VREF + VREF (See field VREFINPUT). + 0 + + + CMP0_A + Pin P0_0. + 0x1 + + + CMP0_B + Pin P0_9. + 0x2 + + + CMP0_C + Pin P0_18. + 0x3 + + + CMP0_D + Pin P1_14. + 0x4 + + + CMP0_E + Pin P2_23. + 0x5 + + + + + VREF + Control reference voltage step, per steps of (VREFINPUT/31). + 10 + 5 + read-write + + + FILTERCGF_SAMPLEMODE + Control the filtering of the Analog Comparator output. + 16 + 2 + read-write + + + BYPASS + Bypass mode. + 0 + + + FILTER1CLK + Filter 1 clock period. + 0x1 + + + FILTER2CLK + Filter 2 clock period. + 0x2 + + + FILTER3CLK + Filter 3 clock period. + 0x3 + + + + + FILTERCGF_CLKDIV + Filter Clock divider. + 18 + 3 + read-write + + + FILTER_1CLK_PERIOD + Filter clock period duration equals 1 Analog Comparator clock period. + 0 + + + FILTER_2CLK_PERIOD + Filter clock period duration equals 2 Analog Comparator clock period. + 0x1 + + + FILTER_4CLK_PERIOD + Filter clock period duration equals 4 Analog Comparator clock period. + 0x2 + + + FILTER_8CLK_PERIOD + Filter clock period duration equals 8 Analog Comparator clock period. + 0x3 + + + FILTER_16CLK_PERIOD + Filter clock period duration equals 16 Analog Comparator clock period. + 0x4 + + + FILTER_32CLK_PERIOD + Filter clock period duration equals 32 Analog Comparator clock period. + 0x5 + + + FILTER_64CLK_PERIOD + Filter clock period duration equals 64 Analog Comparator clock period. + 0x6 + + + FILTER_128CLK_PERIOD + Filter clock period duration equals 128 Analog Comparator clock period. + 0x7 + + + + + + + WAKEUPIOCTRL + Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] + 0x64 + 32 + read-write + 0x200000 + 0x3FF0FF + + + RISINGEDGEWAKEUP0 + Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + 0 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP0 + Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + 1 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP1 + Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + 2 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP1 + Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + 3 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP2 + Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + 4 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP2 + Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + 5 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP3 + Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + 6 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP3 + Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + 7 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + MODEWAKEUPIOPAD0 + Selects function mode (on-chip pull-up/pull-down resistor control). + 12 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + MODEWAKEUPIOPAD1 + Selects function mode (on-chip pull-up/pull-down resistor control). + 14 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + MODEWAKEUPIOPAD2 + Selects function mode (on-chip pull-up/pull-down resistor control). + 16 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + MODEWAKEUPIOPAD3 + Selects function mode (on-chip pull-up/pull-down resistor control). + 18 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + WAKEUPIO_ENABLE_CTRL + Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 12 to 19). + 20 + 1 + read-write + + + DISABLE + WAKEUP IO PAD mode control comes from IOCON. + 0 + + + ENABLE + WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 12 to 19). + 0x1 + + + + + WAKEUPIO_RSTN + WAKEUP IO event detector reset control. + 21 + 1 + read-write + + + ASSERTED + Bloc is reset. + 0 + + + RELEASED + Bloc is not reset. + 0x1 + + + + + + + WAKEIOCAUSE + Allows to identify the Wake-up I/O source from Deep Power Down mode + 0x68 + 32 + read-write + 0 + 0xF + + + WAKEUP0 + Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + 0 + 1 + read-only + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 0. + 0x1 + + + + + WAKEUP1 + Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + 1 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 1. + 0x1 + + + + + WAKEUP2 + Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + 2 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 2. + 0x1 + + + + + WAKEUP3 + Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + 3 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 3. + 0x1 + + + + + + + STATUSCLK + FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] + 0x74 + 32 + read-write + 0x6 + 0x7 + + + XTAL32KOK + XTAL oscillator 32 K OK signal. + 0 + 1 + read-only + + + XTAL32KOSCFAILURE + XTAL32 KHZ oscillator oscillation failure detection indicator. + 2 + 1 + read-write + + + NOFAIL + No oscillation failure has been detetced since the last time this bit has been cleared. + 0 + + + FAILURE + At least one oscillation failure has been detetced since the last time this bit has been cleared. + 0x1 + + + + + + + AOREG1 + General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + POR + The last chip reset was caused by a Power On Reset. + 4 + 1 + read-write + + + PADRESET + The last chip reset was caused by a Pin Reset. + 5 + 1 + read-write + + + BODRESET + The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + 6 + 1 + read-write + + + SYSTEMRESET + The last chip reset was caused by a System Reset requested by the ARM CPU. + 7 + 1 + read-write + + + WDTRESET + The last chip reset was caused by the Watchdog Timer. + 8 + 1 + read-write + + + SWRRESET + The last chip reset was caused by a Software event. + 9 + 1 + read-write + + + DPDRESET_WAKEUPIO + The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + 10 + 1 + read-write + + + DPDRESET_RTC + The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + 11 + 1 + read-write + + + DPDRESET_OSTIMER + The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + 12 + 1 + read-write + + + CDOGRESET + The last chip reset was caused by the code Watchdog. + 13 + 1 + read-write + + + BOOTERRORCOUNTER + ROM Boot Fatal Error Counter. + 16 + 4 + read-write + + + + + MISCCTRL + Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x90 + 32 + read-write + 0 + 0xFFFF + + + LDODEEPSLEEPREF + Select LDO Deep Sleep reference source. + 0 + 1 + read-write + + + FLASHBUFFER + LDO DEEP Sleep uses Flash buffer biasing as reference. + 0 + + + BGP0P8V + LDO DEEP Sleep uses Band Gap 0.8V as reference. + 0x1 + + + + + LDOMEMHIGHZMODE + Control the activation of LDO MEM High Z mode. + 1 + 1 + read-write + + + DISABLE + LDO MEM High Z mode is disabled. + 0 + + + ENABLE + LDO MEM High Z mode is enabled. + 0x1 + + + + + LOWPWR_FLASH_BUF + no description available + 2 + 1 + read-write + + + MISCCTRL_3_11 + Reserved. + 3 + 9 + read-write + + + DISABLE_BLEED + Controls LDO MEM bleed current. This field is expected to be controlled by the Low Power Software only in DEEP SLEEP low power mode. + 12 + 1 + read-write + + + BLEED_ENABLE + LDO_MEM bleed current is enabled. + 0 + + + BLEED_DISABLE + LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared after wake up from Deep SLeep low power mode. + 0x1 + + + + + MISCCTRL_13_15 + Reserved. + 13 + 3 + read-write + + + + + RTCOSC32K + RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] + 0x98 + 32 + read-write + 0x3FF0008 + 0xC7FF800F + + + SEL + Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + 0 + 1 + read-write + + + FRO32K + FRO 32 KHz. + 0 + + + XTAL32K + XTAL 32KHz. + 0x1 + + + + + CLK1KHZDIV + Actual division ratio is : 28 + CLK1KHZDIV. + 1 + 3 + read-write + + + CLK1KHZDIVUPDATEREQ + RTC 1KHz clock Divider status flag. + 15 + 1 + read-write + + + CLK1HZDIV + Actual division ratio is : 31744 + CLK1HZDIV. + 16 + 11 + read-write + + + CLK1HZDIVHALT + Halts the divider counter. + 30 + 1 + read-write + + + CLK1HZDIVUPDATEREQ + RTC 1Hz Divider status flag. + 31 + 1 + read-write + + + + + OSTIMER + OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] + 0x9C + 32 + read-write + 0x8 + 0x3F + + + SOFTRESET + Active high reset. + 0 + 1 + read-write + + + CLOCKENABLE + Enable OS event timer clock. + 1 + 1 + read-write + + + DPDWAKEUPENABLE + Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + 2 + 1 + read-write + + + OSC32KPD + Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + 3 + 1 + read-write + + + OSTIMERCLKSEL + OS event timer clock select. + 4 + 2 + read-write + + + ENUM_0x0 + Oscillator 32 kHz clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Main clock for OS timer. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + + + + + PDRUNCFG0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xB8 + 32 + read-write + 0xDEFFC0 + 0xFFFFEF + + + PDEN_BODVBAT + Controls power to VBAT Brown Out Detector (BOD). + 3 + 1 + read-write + + + POWEREDON + BOD VBAT is powered. + 0 + + + POWEREDOFF + BOD VBAT is powered down. + 0x1 + + + + + PDEN_FRO32K + Controls power to the Free Running Oscillator (FRO) 32 KHz. + 6 + 1 + read-write + + + POWEREDON + FRO32KHz is powered. + 0 + + + POWEREDOFF + FRO32KHz is powered down. + 0x1 + + + + + PDEN_XTAL32K + Controls power to crystal 32 KHz. + 7 + 1 + read-write + + + POWEREDON + Crystal 32KHz is powered. + 0 + + + POWEREDOFF + Crystal 32KHz is powered down. + 0x1 + + + + + PDEN_XTAL32M + Controls power to high speed crystal. + 8 + 1 + read-write + + + POWEREDON + High speed crystal is powered. + 0 + + + POWEREDOFF + High speed crystal is powered down. + 0x1 + + + + + PDEN_PLL0 + Controls power to System PLL (also refered as PLL0). + 9 + 1 + read-write + + + POWEREDON + PLL0 is powered. + 0 + + + POWEREDOFF + PLL0 is powered down. + 0x1 + + + + + PDEN_PLL1 + Controls power to USB PLL (also refered as PLL1). + 10 + 1 + read-write + + + POWEREDON + PLL1 is powered. + 0 + + + POWEREDOFF + PLL1 is powered down. + 0x1 + + + + + PDEN_USBFSPHY + Controls power to USB Full Speed phy. + 11 + 1 + read-write + + + POWEREDON + USB Full Speed phy is powered. + 0 + + + POWEREDOFF + USB Full Speed phy is powered down. + 0x1 + + + + + PDEN_USBHSPHY + Controls power to USB High Speed Phy. + 12 + 1 + read-write + + + POWEREDON + USB HS phy is powered. + 0 + + + POWEREDOFF + USB HS phy is powered down. + 0x1 + + + + + PDEN_COMP + Controls power to Analog Comparator. + 13 + 1 + read-write + + + POWEREDON + Analog Comparator is powered. + 0 + + + POWEREDOFF + Analog Comparator is powered down. + 0x1 + + + + + PDEN_LDOUSBHS + Controls power to USB high speed LDO. + 18 + 1 + read-write + + + POWEREDON + USB high speed LDO is powered. + 0 + + + POWEREDOFF + USB high speed LDO is powered down. + 0x1 + + + + + PDEN_AUXBIAS + Controls power to auxiliary biasing (AUXBIAS) + 19 + 1 + read-write + + + POWEREDON + auxiliary biasing is powered. + 0 + + + POWEREDOFF + auxiliary biasing is powered down. + 0x1 + + + + + PDEN_LDOXO32M + Controls power to high speed crystal LDO. + 20 + 1 + read-write + + + POWEREDON + High speed crystal LDO is powered. + 0 + + + POWEREDOFF + High speed crystal LDO is powered down. + 0x1 + + + + + PDEN_RNG + Controls power to all True Random Number Genetaor (TRNG) clock sources. + 22 + 1 + read-write + + + POWEREDON + TRNG clocks are powered. + 0 + + + POWEREDOFF + TRNG clocks are powered down. + 0x1 + + + + + PDEN_PLL0_SSCG + Controls power to System PLL (PLL0) Spread Spectrum module. + 23 + 1 + read-write + + + POWEREDON + PLL0 Sread spectrum module is powered. + 0 + + + POWEREDOFF + PLL0 Sread spectrum module is powered down. + 0x1 + + + + + + + PDRUNCFGSET0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xC0 + 32 + write-only + 0 + 0xFFFFFFFF + + + PDRUNCFGSET0 + Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + 0 + 32 + write-only + + + + + PDRUNCFGCLR0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xC8 + 32 + write-only + 0 + 0xFFFFFFFF + + + PDRUNCFGCLR0 + Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + 0 + 32 + write-only + + + + + SRAMCTRL + All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] + 0xD4 + 32 + read-write + 0x1 + 0x1FF + + + SMB + Source Biasing voltage. + 0 + 2 + read-write + + + LOW + Low leakage. + 0 + + + MEDIUM + Medium leakage. + 0x1 + + + HIGHEST + Highest leakage. + 0x2 + + + DISABLE + Disable. + 0x3 + + + + + RM + Read Margin control settings. + 2 + 3 + read-write + + + WM + Write Margin control settings. + 5 + 3 + read-write + + + WRME + Write read margin enable. + 8 + 1 + read-write + + + + + + + SYSCTL + system controller + SYSCTL + 0x40023000 + + 0 + 0x190 + registers + + + + UPDATELCKOUT + update lock out control + 0 + 32 + read-write + 0 + 0x1 + + + UPDATELCKOUT + All Registers + 0 + 1 + read-write + + + NORMAL_MODE + Normal Mode. Can be written to. + 0 + + + PROTECTED_MODE + Protected Mode. Cannot be written to. + 0x1 + + + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + FCCTRLSEL%s + Selects the source for SCK going into Flexcomm index + 0x40 + 32 + read-write + 0 + 0x3030303 + + + SCKINSEL + Selects the source for SCK going into this Flexcomm. + 0 + 2 + read-writeOnce + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_SCK function for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + WSINSEL + Selects the source for WS going into this Flexcomm. + 8 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + DATAINSEL + Selects the source for DATA input to this Flexcomm. + 16 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + DATAOUTSEL + Selects the source for DATA output from this Flexcomm. + 24 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + + + 2 + 0x4 + 0,1 + SHAREDCTRLSET%s + Selects sources and data combinations for shared signal set index. + 0x80 + 32 + read-write + 0 + 0xFF0777 + + + SHAREDSCKSEL + Selects the source for SCK of this shared signal set. + 0 + 3 + read-write + + + FLEXCOMM0 + SCK for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + SCK for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + SCK for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + SCK for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + SCK for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + SCK for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + SCK for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + SCK for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + SHAREDWSSEL + Selects the source for WS of this shared signal set. + 4 + 3 + read-write + + + FLEXCOMM0 + WS for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + WS for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + WS for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + WS for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + WS for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + WS for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + WS for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + WS for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + SHAREDDATASEL + Selects the source for DATA input for this shared signal set. + 8 + 3 + read-write + + + FLEXCOMM0 + DATA input for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + DATA input for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + DATA input for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + DATA input for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + DATA input for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + DATA input for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + DATA input for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + DATA input for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + FC0DATAOUTEN + Controls FC0 contribution to SHAREDDATAOUT for this shared set. + 16 + 1 + read-write + + + INPUT + Data output from FC0 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC0 does contribute to this shared set. + 0x1 + + + + + FC1DATAOUTEN + Controls FC1 contribution to SHAREDDATAOUT for this shared set. + 17 + 1 + read-write + + + INPUT + Data output from FC1 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC1 does contribute to this shared set. + 0x1 + + + + + FC2DATAOUTEN + Controls FC2 contribution to SHAREDDATAOUT for this shared set. + 18 + 1 + read-write + + + INPUT + Data output from FC2 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC2 does contribute to this shared set. + 0x1 + + + + + FC4DATAOUTEN + Controls FC4 contribution to SHAREDDATAOUT for this shared set. + 20 + 1 + read-write + + + INPUT + Data output from FC4 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC4 does contribute to this shared set. + 0x1 + + + + + FC5DATAOUTEN + Controls FC5 contribution to SHAREDDATAOUT for this shared set. + 21 + 1 + read-write + + + INPUT + Data output from FC5 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC5 does contribute to this shared set. + 0x1 + + + + + FC6DATAOUTEN + Controls FC6 contribution to SHAREDDATAOUT for this shared set. + 22 + 1 + read-write + + + INPUT + Data output from FC6 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC6 does contribute to this shared set. + 0x1 + + + + + FC7DATAOUTEN + Controls FC7 contribution to SHAREDDATAOUT for this shared set. + 23 + 1 + read-write + + + INPUT + Data output from FC7 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC7 does contribute to this shared set. + 0x1 + + + + + + + USB_HS_STATUS + Status register for USB HS + 0x100 + 32 + read-only + 0 + 0x1C0FF00 + + + USBHS_3V_NOK + USB_HS: Low voltage detection on 3.3V supply. + 0 + 1 + read-only + + + SUPPLY_3V_OK + 3v3 supply is good. + 0 + + + SUPPLY_3V_LOW + 3v3 supply is too low. + 0x1 + + + + + + + CODE_GRAY_LSB + CODE_GRAY LSB input Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CODE_GRAY_LSB + Gray code (42bits) to be converted back to binary + 0 + 32 + read-write + + + + + CODE_GRAY_MSB + CODE_GRAY MSB input Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CODE_GRAY_MSB + Gray code (42bits) to be converted back to binary + 0 + 10 + read-write + + + + + CODE_BIN_LSB + CODE_BIN LSB output Register + 0x188 + 32 + read-only + 0 + 0xFFFFFFFF + + + CODE_BIN_LSB + Binary converted code (42bits) + 0 + 32 + read-only + + + + + CODE_BIN_MSB + CODE_BIN MSB output Register + 0x18C + 32 + read-only + 0 + 0xFFFFFFFF + + + CODE_BIN_MSB + Binary converted code (42bits) + 0 + 10 + read-only + + + + + + + RTC + Real-Time Clock (RTC) + RTC + 0x4002C000 + + 0 + 0x60 + registers + + + RTC + 29 + + + + CTRL + RTC control register + 0 + 32 + read-write + 0x1 + 0x7FD + + + SWRESET + Software reset control + 0 + 1 + read-write + + + NOT_IN_RESET + Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + 0 + + + IN_RESET + In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. + 0x1 + + + + + ALARM1HZ + RTC 1 Hz timer alarm flag status. + 2 + 1 + read-write + + + NO_MATCH + No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + 0 + + + MATCH + Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + 0x1 + + + + + WAKE1KHZ + RTC 1 kHz timer wake-up flag status. + 3 + 1 + read-write + + + RUN + Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + 0 + + + TIMEOUT + Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + 0x1 + + + + + ALARMDPD_EN + RTC 1 Hz timer alarm enable for Deep power-down. + 4 + 1 + read-write + + + DISABLE + Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + 0x1 + + + + + WAKEDPD_EN + RTC 1 kHz timer wake-up enable for Deep power-down. + 5 + 1 + read-write + + + DISABLE + Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + 0x1 + + + + + RTC1KHZ_EN + RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + 6 + 1 + read-write + + + DISABLE + Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. The 1 kHz RTC timer is enabled. + 0x1 + + + + + RTC_EN + RTC enable. + 7 + 1 + read-write + + + DISABLE + Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. + 0 + + + ENABLE + Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. + 0x1 + + + + + RTC_OSC_PD + RTC oscillator power-down control. + 8 + 1 + read-write + + + POWER_UP + See RTC_OSC_BYPASS + 0 + + + POWERED_DOWN + RTC oscillator is powered-down. + 0x1 + + + + + RTC_OSC_BYPASS + RTC oscillator bypass control. + 9 + 1 + read-write + + + USED + The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + 0 + + + BYPASS + The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + 0x1 + + + + + RTC_SUBSEC_ENA + RTC Sub-second counter control. + 10 + 1 + read-write + + + POWER_UP + The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. + 0 + + + POWERED_DOWN + The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. + 0x1 + + + + + + + MATCH + RTC match register + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MATVAL + Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + 0 + 32 + read-write + + + + + COUNT + RTC counter register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. + 0 + 32 + read-write + + + + + WAKE + High-resolution/wake-up timer control register + 0xC + 32 + read-write + 0 + 0xFFFF + + + VAL + A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. + 0 + 16 + read-write + + + + + SUBSEC + Sub-second counter register + 0x10 + 32 + read-write + 0 + 0xFFFF + + + SUBSEC + A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. + 0 + 15 + read-only + + + + + 8 + 0x4 + GPREG[%s] + General Purpose register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPDATA + Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + 0 + 32 + read-write + + + + + + + OSTIMER + Synchronous OS/Event timer with Wakeup Timer + OSTIMER + 0x4002D000 + + 0 + 0x20 + registers + + + OS_EVENT + 38 + + + + EVTIMERL + EVTIMER Low Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVTIMER_COUNT_VALUE + A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER. Note there is only one EVTIMER, readable from all domains. + 0 + 32 + read-only + + + + + EVTIMERH + EVTIMER High Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EVTIMER_COUNT_VALUE + A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER. Note there is only one EVTIMER, readable from all domains. + 0 + 10 + read-only + + + + + CAPTURE_L + Capture Low Register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPTURE_VALUE + A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + 0 + 32 + read-only + + + + + CAPTURE_H + Capture High Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPTURE_VALUE + A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + 0 + 10 + read-only + + + + + MATCH_L + Match Low Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MATCH_VALUE + The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + 0 + 32 + read-write + + + + + MATCH_H + Match High Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MATCH_VALUE + The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + 0 + 10 + read-write + + + + + OSEVENT_CTRL + OS_EVENT TIMER Control Register + 0x1C + 32 + read-write + 0 + 0x7 + + + OSTIMER_INTRFLAG + This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. It should be done before a new match value is written into the MATCH_L/H registers. + 0 + 1 + read-write + + + OSTIMER_INTENA + When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked. + 1 + 1 + read-write + + + MATCH_WR_RDY + This bit will be low when it is safe to write to reload the Match Registers. In typical applications it should not be necessary to test this bit. [1] + 2 + 1 + read-only + + + + + + + FLASH + FLASH + FLASH + 0x40034000 + + 0 + 0x1000 + registers + + + + CMD + command register + 0 + 32 + write-only + 0 + 0xFFFFFFFF + + + CMD + command register. + 0 + 32 + write-only + + + + + EVENT + event register + 0x4 + 32 + write-only + 0 + 0x7 + + + RST + When bit is set, the controller and flash are reset. + 0 + 1 + write-only + + + WAKEUP + When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + 1 + 1 + write-only + + + ABORT + When bit is set, a running program/erase command is aborted. + 2 + 1 + write-only + + + + + STARTA + start (or only) address for next flash command + 0x10 + 32 + read-write + 0 + 0x3FFFF + + + STARTA + Address / Start address for commands that take an address (range) as a parameter. + 0 + 18 + read-write + + + + + STOPA + end address for next flash command, if command operates on address ranges + 0x14 + 32 + read-write + 0 + 0x3FFFF + + + STOPA + Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). + 0 + 18 + read-write + + + + + 4 + 0x4 + DATAW[%s] + data register, word 0-7; Memory data, or command parameter, or command result. + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAW + no description available + 0 + 32 + read-write + + + + + INT_CLR_ENABLE + Clear interrupt enable bits + 0xFD8 + 32 + write-only + 0 + 0xF + + + FAIL + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 0 + 1 + write-only + + + ERR + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 1 + 1 + write-only + + + DONE + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 2 + 1 + write-only + + + ECC_ERR + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 3 + 1 + write-only + + + + + INT_SET_ENABLE + Set interrupt enable bits + 0xFDC + 32 + write-only + 0 + 0xF + + + FAIL + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 0 + 1 + write-only + + + ERR + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 1 + 1 + write-only + + + DONE + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 2 + 1 + write-only + + + ECC_ERR + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 3 + 1 + write-only + + + + + INT_STATUS + Interrupt status bits + 0xFE0 + 32 + read-write + 0 + 0xF + + + FAIL + This status bit is set if execution of a (legal) command failed. + 0 + 1 + read-only + + + ERR + This status bit is set if execution of an illegal command is detected. + 1 + 1 + read-only + + + DONE + This status bit is set at the end of command execution. + 2 + 1 + read-only + + + ECC_ERR + This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic. + 3 + 1 + read-only + + + + + INT_ENABLE + Interrupt enable bits + 0xFE4 + 32 + read-write + 0 + 0xF + + + FAIL + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 0 + 1 + read-only + + + ERR + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 1 + 1 + read-only + + + DONE + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 2 + 1 + read-only + + + ECC_ERR + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 3 + 1 + read-only + + + + + INT_CLR_STATUS + Clear interrupt status bits + 0xFE8 + 32 + write-only + 0 + 0xF + + + FAIL + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 0 + 1 + write-only + + + ERR + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 1 + 1 + write-only + + + DONE + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 2 + 1 + write-only + + + ECC_ERR + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 3 + 1 + write-only + + + + + INT_SET_STATUS + Set interrupt status bits + 0xFEC + 32 + write-only + 0 + 0xF + + + FAIL + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 0 + 1 + write-only + + + ERR + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 1 + 1 + write-only + + + DONE + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 2 + 1 + write-only + + + ECC_ERR + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 3 + 1 + write-only + + + + + MODULE_ID + Controller+Memory module identification + 0xFFC + 32 + read-only + 0xC40A0B00 + 0xFFFFFFFF + + + APERTURE + Aperture i. + 0 + 8 + read-only + + + MINOR_REV + Minor revision i. + 8 + 4 + read-only + + + MAJOR_REV + Major revision i. + 12 + 4 + read-only + + + ID + Identifier. + 16 + 16 + read-only + + + + + + + PRINCE + PRINCE + PRINCE + 0x40035000 + + 0 + 0x94 + registers + + + + ENC_ENABLE + Encryption Enable register + 0 + 32 + read-write + 0 + 0x1 + + + EN + Enables PRINCE encryption for flash programming. + 0 + 1 + read-write + + + DISABLED + Encryption of writes to the flash controller DATAW* registers is disabled. + 0 + + + ENABLED + Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled. + 0x1 + + + + + + + MASK_LSB + Data Mask register, 32 Least Significant Bits + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + MASKVAL + Value of the 32 Least Significant Bits of the 64-bit data mask. + 0 + 32 + write-only + + + + + MASK_MSB + Data Mask register, 32 Most Significant Bits + 0x8 + 32 + write-only + 0 + 0xFFFFFFFF + + + MASKVAL + Value of the 32 Most Significant Bits of the 64-bit data mask. + 0 + 32 + write-only + + + + + LOCK + Lock register + 0xC + 32 + read-write + 0 + 0x107 + + + LOCKREG0 + Lock Region 0 registers. + 0 + 1 + read-write + + + DISABLED + Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + 0x1 + + + + + LOCKREG1 + Lock Region 1 registers. + 1 + 1 + read-write + + + DISABLED + Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + 0x1 + + + + + LOCKREG2 + Lock Region 2 registers. + 2 + 1 + read-write + + + DISABLED + Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + 0x1 + + + + + LOCKMASK + Lock the Mask registers. + 8 + 1 + read-write + + + DISABLED + Disabled. MASK_LSB, and MASK_MSB are writable.. + 0 + + + ENABLED + Enabled. MASK_LSB, and MASK_MSB are not writable.. + 0x1 + + + + + + + IV_LSB0 + Initial Vector register for region 0, Least Significant Bits + 0x10 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB0 + Initial Vector register for region 0, Most Significant Bits + 0x14 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR0 + Base Address for region 0 register + 0x18 + 32 + read-write + 0 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 0. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 0. + 18 + 2 + read-write + + + + + SR_ENABLE0 + Sub-Region Enable register for region 0 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + 0 + 32 + read-write + + + + + IV_LSB1 + Initial Vector register for region 1, Least Significant Bits + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB1 + Initial Vector register for region 1, Most Significant Bits + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR1 + Base Address for region 1 register + 0x28 + 32 + read-write + 0x40000 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 1. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 1. + 18 + 2 + read-write + + + + + SR_ENABLE1 + Sub-Region Enable register for region 1 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + 0 + 32 + read-write + + + + + IV_LSB2 + Initial Vector register for region 2, Least Significant Bits + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB2 + Initial Vector register for region 2, Most Significant Bits + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR2 + Base Address for region 2 register + 0x38 + 32 + read-write + 0x80000 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 2. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 2. + 18 + 2 + read-write + + + + + SR_ENABLE2 + Sub-Region Enable register for region 2 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + 0 + 32 + read-write + + + + + ERR + Error status register + 0x90 + 32 + read-write + 0 + 0x1 + + + ERRSTAT + PRINCE Error Status. This bit is write-1 to clear. + 0 + 1 + read-write + + + NO_ERROR + No PRINCE error. + 0 + + + ERROR + Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE.EN=1. + 0x1 + + + + + + + + + USBPHY + Universal System Bus Physical Layer + USBPHY + 0x40038000 + + 0 + 0x110 + registers + + + USB1_PHY + 46 + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 + 1 + read-write + + + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 + 1 + read-write + + + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 + 1 + read-write + + + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 + 1 + read-write + + + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + OK_STATUS_3V + Indicates the USB 3v power rails are in range. + 0 + 1 + read-only + + + HOSTDISCONDETECT_STATUS + Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode + 3 + 1 + read-only + + + value0 + USB cable disconnect has not been detected at the local host + 0 + + + value1 + USB cable disconnect has been detected at the local host + 0x1 + + + + + DEVPLUGIN_STATUS + Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] + 6 + 1 + read-only + + + value0 + No attachment to a USB host is detected + 0 + + + value1 + Cable attachment to a USB host is detected + 0x1 + + + + + RESUME_STATUS + Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. + 10 + 1 + read-only + + + + + PLL_SIC + USB PHY PLL Control/Status Register + 0xA0 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-only + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_SET + USB PHY PLL Control/Status Register + 0xA4 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-only + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_CLR + USB PHY PLL Control/Status Register + 0xA8 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-only + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_TOG + USB PHY PLL Control/Status Register + 0xAC + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-only + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + USB1_VBUS_DETECT + USB PHY VBUS Detect Control Register + 0xC0 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pinmuxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x7 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + + + USB1_VBUS_DETECT_SET + USB PHY VBUS Detect Control Register + 0xC4 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pinmuxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x7 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + + + USB1_VBUS_DETECT_CLR + USB PHY VBUS Detect Control Register + 0xC8 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pin muxed value. + 14 + 1 + read-write + + + value0 + Select the muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x7 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + + + USB1_VBUS_DETECT_TOG + USB PHY VBUS Detect Control Register + 0xCC + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pin muxed value. + 13 + 1 + read-write + + + value0 + Select the muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pin muxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x7 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + + + USB1_VBUS_DET_STAT + USB PHY VBUS Detector Status Register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End indicator Session End status, value inverted from Session Valid comparator + 0 + 1 + read-only + + + value0 + The VBUS voltage is above the Session Valid threshold + 0 + + + value1 + The VBUS voltage is below the Session Valid threshold + 0x1 + + + + + BVALID + B-Device Session Valid status B-Device Session Valid status, determined by the Session Valid comparator + 1 + 1 + read-only + + + value0 + The VBUS voltage is below the Session Valid threshold + 0 + + + value1 + The VBUS voltage is above the Session Valid threshold + 0x1 + + + + + AVALID + A-Device Session Valid status A-Device Session Valid status, determined by the Session Valid comparator + 2 + 1 + read-only + + + value0 + The VBUS voltage is below the Session Valid threshold + 0 + + + value1 + The VBUS voltage is above the Session Valid threshold + 0x1 + + + + + VBUS_VALID + VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin + 3 + 1 + read-only + + + value0 + VBUS is below the comparator threshold + 0 + + + value1 + VBUS is above the comparator threshold + 0x1 + + + + + VBUS_VALID_3V + VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on the USB1_VBUS pin than either the Session Valid or VBUS_VALID comparators + 4 + 1 + read-only + + + value0 + VBUS voltage is below VBUS_VALID_3V threshold + 0 + + + value1 + VBUS voltage is above VBUS_VALID_3V threshold + 0x1 + + + + + + + ANACTRL + USB PHY Analog Control Register + 0x100 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_SET + USB PHY Analog Control Register + 0x104 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_CLR + USB PHY Analog Control Register + 0x108 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_TOG + USB PHY Analog Control Register + 0x10C + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + + + RNG + RNG + RNG + 0x4003A000 + + 0 + 0x1000 + registers + + + + RANDOM_NUMBER + This register contains a random 32 bit number which is computed on demand, at each time it is read + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RANDOM_NUMBER + This register contains a random 32 bit number which is computed on demand, at each time it is read. + 0 + 32 + read-only + + + + + ENCRYPTED_NUMBER + This register contains a random 32 bit number which is pre-computed + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENCRYPTED_NUMBER + This register contains a random 32 bit number which is pre-computed. + 0 + 32 + read-write + + + + + COUNTER_VAL + no description available + 0x8 + 32 + read-write + 0 + 0x1FFF + + + CLK_RATIO + Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. + 0 + 8 + read-only + + + REFRESH_CNT + Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + 8 + 14 + read-only + + + + + COUNTER_CFG + no description available + 0xC + 32 + read-write + 0 + 0x3FF + + + MODE + 00: disabled 01: update once. + 0 + 2 + read-write + + + CLOCK_SEL + Selects the internal clock on which to compute statistics. + 2 + 3 + read-write + + + SHIFT4X + To be used to add precision to clock_ratio and determine 'entropy refill'. + 5 + 3 + read-write + + + + + ONLINE_TEST_CFG + no description available + 0x10 + 32 + read-write + 0 + 0x7 + + + ACTIVATE + 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + 0 + 1 + read-write + + + DATA_SEL + Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field. + 1 + 2 + read-write + + + + + ONLINE_TEST_VAL + no description available + 0x14 + 32 + read-write + 0 + 0xFFF + + + LIVE_CHI_SQUARED + This value is updated as described in field 'activate'. + 0 + 4 + read-only + + + MIN_CHI_SQUARED + This field is reset when 'activate'==0. + 4 + 4 + read-only + + + MAX_CHI_SQUARED + This field is reset when 'activate'==0. + 8 + 4 + read-only + + + + + ENTROPY_INJECT + no description available + 0x18 + 32 + read-write + 0 + 0x3 + + + ENTROPY + Use this register to inject or restore entropy 32 bits at a time. Writing is blocking thus see to it to have analog clocks activated. Injection can be usefull to add contribution from an external source of entropy, like for example LSBs of an ADC or of a temperature sensor. Restore can be usefull to store N random numbers in central memory before going powerdown then restore this entropy to RNG IP after power-up. It is useless to inject or restore more than 1*(number of RNGs) 32b words consecutively. Recommendation is to inject 1*(number of RNGs) words, and possibly later (2*32 clock cycles of slowest analog clock) inject again 1*(number of RNGs) words. Then maximum capacity of restoration is reached: about 44 bits per RNG (not to be mistaken with maximum capacity of entropy accumulation which is about 100 bits per RNG). You can inject less than 32 bits words (let unused bits to 0). Injection cannot degrade overall performance due to the fact that some internal PRNGs are excluded on purpose from this external action. + 0 + 32 + read-write + + + + + MISC_CFG + no description available + 0x1C + 32 + read-write + 0 + 0x3 + + + AES_RESEED + If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and current internal state are known: independant from entropy source. + 0 + 1 + read-write + + + AES_DT_CFG + Set this bit to re-seed AES. + 1 + 1 + read-write + + + + + POWERDOWN + Powerdown mode (standard but certainly useless here) + 0xFF4 + 32 + read-write + 0 + 0x80000003 + + + SOFT_RESET + Request softreset that will go low automaticaly after acknowledge from CORE. + 0 + 1 + read-write + + + FORCE_SOFT_RESET + When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. + 1 + 1 + read-write + + + POWERDOWN + When set all accesses to standard registers are blocked. + 31 + 1 + read-write + + + + + MODULEID + IP identifier + 0xFFC + 32 + read-only + 0xA0B84000 + 0xFFFFFFFF + + + APERTURE + Aperture i. + 0 + 8 + read-only + + + MIN_REV + Minor revision i. + 8 + 4 + read-only + + + MAJ_REV + Major revision i. + 12 + 4 + read-only + + + ID + Identifier. + 16 + 16 + read-only + + + + + + + PUF + PUFCTRL + PUF + 0x4003B000 + + 0 + 0x25C + registers + + + PUF + 56 + + + + CTRL + PUF Control register + 0 + 32 + read-write + 0 + 0x5F + + + zeroize + Begin Zeroize operation for PUF and go to Error state + 0 + 1 + read-write + + + enroll + Begin Enroll operation + 1 + 1 + read-write + + + start + Begin Start operation + 2 + 1 + read-write + + + GENERATEKEY + Begin Set Intrinsic Key operation + 3 + 1 + read-write + + + SETKEY + Begin Set User Key operation + 4 + 1 + read-write + + + GETKEY + Begin Get Key operation + 6 + 1 + read-write + + + + + KEYINDEX + PUF Key Index register + 0x4 + 32 + read-write + 0 + 0xF + + + KEYIDX + Key index for Set Key operations + 0 + 4 + read-write + + + + + KEYSIZE + PUF Key Size register + 0x8 + 32 + read-write + 0 + 0x3F + + + KEYSIZE + Key size for Set Key operations + 0 + 6 + read-write + + + + + STAT + PUF Status register + 0x20 + 32 + read-only + 0x1 + 0xF7 + + + busy + Indicates that operation is in progress + 0 + 1 + read-only + + + SUCCESS + Last operation was successful + 1 + 1 + read-only + + + error + PUF is in the Error state and no operations can be performed + 2 + 1 + read-only + + + KEYINREQ + Request for next part of key + 4 + 1 + read-only + + + KEYOUTAVAIL + Next part of key is available + 5 + 1 + read-only + + + CODEINREQ + Request for next part of AC/KC + 6 + 1 + read-only + + + CODEOUTAVAIL + Next part of AC/KC is available + 7 + 1 + read-only + + + + + ALLOW + PUF Allow register + 0x28 + 32 + read-write + 0 + 0x8F + + + ALLOWENROLL + Enroll operation is allowed + 0 + 1 + read-only + + + ALLOWSTART + Start operation is allowed + 1 + 1 + read-only + + + ALLOWSETKEY + Set Key operations are allowed + 2 + 1 + read-only + + + ALLOWGETKEY + Get Key operation is allowed + 3 + 1 + read-only + + + + + KEYINPUT + PUF Key Input register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEYIN + Key input data + 0 + 32 + write-only + + + + + CODEINPUT + PUF Code Input register + 0x44 + 32 + write-only + 0 + 0xFFFFFFFF + + + CODEIN + AC/KC input data + 0 + 32 + write-only + + + + + CODEOUTPUT + PUF Code Output register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + CODEOUT + AC/KC output data + 0 + 32 + read-only + + + + + KEYOUTINDEX + PUF Key Output Index register + 0x60 + 32 + read-only + 0 + 0xF + + + KEYOUTIDX + Key index for the key that is currently output via the Key Output register + 0 + 4 + read-only + + + + + KEYOUTPUT + PUF Key Output register + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + KEYOUT + Key output data + 0 + 32 + read-only + + + + + IFSTAT + PUF Interface Status and clear register + 0xDC + 32 + read-write + 0 + 0x1 + + + ERROR + Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + 0 + 1 + read-write + + + + + INTEN + PUF Interrupt Enable + 0x100 + 32 + read-write + 0 + 0xF7 + + + READYEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 0 + 1 + read-write + + + SUCCESEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 1 + 1 + read-write + + + ERROREN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 2 + 1 + read-write + + + KEYINREQEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 4 + 1 + read-write + + + KEYOUTAVAILEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 5 + 1 + read-write + + + CODEINREQEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 6 + 1 + read-write + + + CODEOUTAVAILEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 7 + 1 + read-write + + + + + INTSTAT + PUF interrupt status + 0x104 + 32 + read-write + 0 + 0xF7 + + + READY + Triggers on falling edge of busy, write 1 to clear + 0 + 1 + read-write + + + SUCCESS + Level sensitive interrupt, cleared when interrupt source clears + 1 + 1 + read-write + + + ERROR + Level sensitive interrupt, cleared when interrupt source clears + 2 + 1 + read-write + + + KEYINREQ + Level sensitive interrupt, cleared when interrupt source clears + 4 + 1 + read-write + + + KEYOUTAVAIL + Level sensitive interrupt, cleared when interrupt source clears + 5 + 1 + read-write + + + CODEINREQ + Level sensitive interrupt, cleared when interrupt source clears + 6 + 1 + read-write + + + CODEOUTAVAIL + Level sensitive interrupt, cleared when interrupt source clears + 7 + 1 + read-write + + + + + CFG + PUF config register for block bits + 0x10C + 32 + read-write + 0 + 0x3 + + + BLOCKENROLL_SETKEY + Block enroll operation. Write 1 to set, cleared on reset. + 0 + 1 + read-write + + + BLOCKKEYOUTPUT + Block set key operation. Write 1 to set, cleared on reset. + 1 + 1 + read-write + + + + + KEYLOCK + Only reset in case of full IC reset + 0x200 + 32 + read-write + 0xAA + 0xFF + + + KEY0 + "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 0 + 2 + read-write + + + KEY1 + "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 2 + 2 + read-write + + + KEY2 + "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 4 + 2 + read-write + + + KEY3 + "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 6 + 2 + read-write + + + + + KEYENABLE + no description available + 0x204 + 32 + read-write + 0x55 + 0xFF + + + KEY0 + "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + 0 + 2 + read-write + + + KEY1 + "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + 2 + 2 + read-write + + + KEY2 + "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + 4 + 2 + read-write + + + KEY3 + "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + 6 + 2 + read-write + + + + + KEYRESET + Reinitialize Keys shift registers counters + 0x208 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEY0 + 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + 0 + 2 + write-only + + + KEY1 + 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + 2 + 2 + write-only + + + KEY2 + 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + 4 + 2 + write-only + + + KEY3 + 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + 6 + 2 + write-only + + + + + IDXBLK + no description available + 0x20C + 32 + write-only + 0xAAAAAAAA + 0xFFFFFFFF + + + IDX0 + Use to block PUF index 0 + 0 + 2 + write-only + + + IDX1 + Use to block PUF index 1 + 2 + 2 + write-only + + + IDX2 + Use to block PUF index 2 + 4 + 2 + write-only + + + IDX3 + Use to block PUF index 3 + 6 + 2 + write-only + + + IDX4 + Use to block PUF index 4 + 8 + 2 + write-only + + + IDX5 + Use to block PUF index 5 + 10 + 2 + write-only + + + IDX6 + Use to block PUF index 6 + 12 + 2 + write-only + + + IDX7 + Use to block PUF index 7 + 14 + 2 + write-only + + + IDX8 + Use to block PUF index 8 + 16 + 2 + write-only + + + IDX9 + Use to block PUF index 9 + 18 + 2 + write-only + + + IDX10 + Use to block PUF index 10 + 20 + 2 + write-only + + + IDX11 + Use to block PUF index 11 + 22 + 2 + write-only + + + IDX12 + Use to block PUF index 12 + 24 + 2 + write-only + + + IDX13 + Use to block PUF index 13 + 26 + 2 + write-only + + + IDX14 + Use to block PUF index 14 + 28 + 2 + write-only + + + IDX15 + Use to block PUF index 15 + 30 + 2 + write-only + + + + + IDXBLK_DP + no description available + 0x210 + 32 + write-only + 0xAAAAAAAA + 0xFFFFFFFF + + + IDX0 + Use to block PUF index 0 + 0 + 2 + write-only + + + IDX1 + Use to block PUF index 1 + 2 + 2 + write-only + + + IDX2 + Use to block PUF index 2 + 4 + 2 + write-only + + + IDX3 + Use to block PUF index 3 + 6 + 2 + write-only + + + IDX4 + Use to block PUF index 4 + 8 + 2 + write-only + + + IDX5 + Use to block PUF index 5 + 10 + 2 + write-only + + + IDX6 + Use to block PUF index 6 + 12 + 2 + write-only + + + IDX7 + Use to block PUF index 7 + 14 + 2 + write-only + + + IDX8 + Use to block PUF index 8 + 16 + 2 + write-only + + + IDX9 + Use to block PUF index 9 + 18 + 2 + write-only + + + IDX10 + Use to block PUF index 10 + 20 + 2 + write-only + + + IDX11 + Use to block PUF index 11 + 22 + 2 + write-only + + + IDX12 + Use to block PUF index 12 + 24 + 2 + write-only + + + IDX13 + Use to block PUF index 13 + 26 + 2 + write-only + + + IDX14 + Use to block PUF index 14 + 28 + 2 + write-only + + + IDX15 + Use to block PUF index 15 + 30 + 2 + write-only + + + + + 4 + 0x4 + KEYMASK[%s] + Only reset in case of full IC reset + 0x214 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEYMASK + no description available + 0 + 32 + write-only + + + + + IDXBLK_STATUS + Index block status + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + IDX0 + Status block index 0 + 0 + 2 + read-only + + + IDX1 + Status block index 1 + 2 + 2 + read-only + + + IDX2 + Status block index 2 + 4 + 2 + read-only + + + IDX3 + Status block index 3 + 6 + 2 + read-only + + + IDX4 + Status block index 4 + 8 + 2 + read-only + + + IDX5 + Status block index 5 + 10 + 2 + read-only + + + IDX6 + Status block index 6 + 12 + 2 + read-only + + + IDX7 + Status block index 7 + 14 + 2 + read-only + + + IDX8 + Status block index 8 + 16 + 2 + read-only + + + IDX9 + Status block index 9 + 18 + 2 + read-only + + + IDX10 + Status block index 10 + 20 + 2 + read-only + + + IDX11 + Status block index 11 + 22 + 2 + read-only + + + IDX12 + Status block index 12 + 24 + 2 + read-only + + + IDX13 + Status block index 13 + 26 + 2 + read-only + + + IDX14 + Status block index 14 + 28 + 2 + read-only + + + IDX15 + Status block index 15 + 30 + 2 + read-only + + + + + SHIFT_STATUS + no description available + 0x258 + 32 + read-only + 0 + 0xFFFF + + + KEY0 + Index counter from key 0 shift register + 0 + 4 + read-only + + + KEY1 + Index counter from key 1 shift register + 4 + 4 + read-only + + + KEY2 + Index counter from key 2 shift register + 8 + 4 + read-only + + + KEY3 + Index counter from key 3 shift register + 12 + 4 + read-only + + + + + + + PUF_SRAM_CTRL + PUF SRAM Control + PUF + PUF_SRAM_CTRL + 0x4003B000 + + 0 + 0x3F0 + registers + + + + CFG + Configuration Register + 0x300 + 32 + read-write + 0 + 0x5F + + + enable + PUF SRAM Controller activation + 0 + 1 + read-write + + + ckgating + PUF SRAM Clock Gating control + 2 + 1 + read-write + + + + + STATUS + Status Register + 0x304 + 32 + read-write + 0 + 0xF + + + READY + PUF SRAM Controller State + 0 + 1 + read-only + + + + + INT_CLR_ENABLE + Interrupt Enable Clear Register + 0x3D8 + 32 + write-only + 0 + 0xF7 + + + READY + READY Interrupt Enable clear + 0 + 1 + write-only + + + APB_ERR + APB_ERR Interrupt Enable clear + 1 + 1 + write-only + + + + + INT_SET_ENABLE + Interrupt Enable Set Register + 0x3DC + 32 + write-only + 0 + 0xF7 + + + READY + READY Interrupt Enable set + 0 + 1 + write-only + + + APB_ERR + APB_ERR Interrupt Enable set + 1 + 1 + write-only + + + + + INT_STATUS + Interrupt Status Register + 0x3E0 + 32 + read-write + 0 + 0xF7 + + + READY + READY Interrupt Status + 0 + 1 + read-only + + + APB_ERR + APB_ERR Interrupt Status + 1 + 1 + read-only + + + + + INT_ENABLE + Interrupt Enable Register + 0x3E4 + 32 + read-write + 0 + 0xF7 + + + READY + READY Interrupt Enable + 0 + 1 + read-only + + + APB_ERR + APB_ERR Interrupt Enable + 1 + 1 + read-only + + + + + INT_CLR_STATUS + Interrupt Status Clear Register + 0x3E8 + 32 + write-only + 0 + 0xF7 + + + READY + READY Interrupt Status clear + 0 + 1 + write-only + + + APB_ERR + APB_ERR Interrupt Status Clear + 1 + 1 + write-only + + + + + INT_SET_STATUS + Interrupt Status set + 0x3EC + 32 + write-only + 0 + 0xF7 + + + READY + READY Interrupt Status set + 0 + 1 + write-only + + + APB_ERR + APB_ERR Interrupt Status Set + 1 + 1 + write-only + + + + + + + PLU + LPC80X Programmable Logic Unit (PLU) + PLU + 0x4003D000 + + 0 + 0xC20 + registers + + + PLU + 52 + + + + 26 + 0x20 + LUT[%s] + no description available + 0 + + 5 + 0x4 + 0,1,2,3,4 + LUT_INP_MUX%s + LUTn input x MUX + 0 + 32 + read-write + 0 + 0x3F + + + LUTn_INPx + Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low. + 0 + 6 + read-write + + + plu_inputs0 + The PLU primary inputs 0. + 0 + + + plu_inputs1 + The PLU primary inputs 1. + 0x1 + + + plu_inputs2 + The PLU primary inputs 2. + 0x2 + + + plu_inputs3 + The PLU primary inputs 3. + 0x3 + + + plu_inputs4 + The PLU primary inputs 4. + 0x4 + + + plu_inputs5 + The PLU primary inputs 5. + 0x5 + + + lut_outputs0 + The output of LUT0. + 0x6 + + + lut_outputs1 + The output of LUT1. + 0x7 + + + lut_outputs2 + The output of LUT2. + 0x8 + + + lut_outputs3 + The output of LUT3. + 0x9 + + + lut_outputs4 + The output of LUT4. + 0xA + + + lut_outputs5 + The output of LUT5. + 0xB + + + lut_outputs6 + The output of LUT6. + 0xC + + + lut_outputs7 + The output of LUT7. + 0xD + + + lut_outputs8 + The output of LUT8. + 0xE + + + lut_outputs9 + The output of LUT9. + 0xF + + + lut_outputs10 + The output of LUT10. + 0x10 + + + lut_outputs11 + The output of LUT11. + 0x11 + + + lut_outputs12 + The output of LUT12. + 0x12 + + + lut_outputs13 + The output of LUT13. + 0x13 + + + lut_outputs14 + The output of LUT14. + 0x14 + + + lut_outputs15 + The output of LUT15. + 0x15 + + + lut_outputs16 + The output of LUT16. + 0x16 + + + lut_outputs17 + The output of LUT17. + 0x17 + + + lut_outputs18 + The output of LUT18. + 0x18 + + + lut_outputs19 + The output of LUT19. + 0x19 + + + lut_outputs20 + The output of LUT20. + 0x1A + + + lut_outputs21 + The output of LUT21. + 0x1B + + + lut_outputs22 + The output of LUT22. + 0x1C + + + lut_outputs23 + The output of LUT23. + 0x1D + + + lut_outputs24 + The output of LUT24. + 0x1E + + + lut_outputs25 + The output of LUT25. + 0x1F + + + state0 + state(0). + 0x20 + + + state1 + state(1). + 0x21 + + + state2 + state(2). + 0x22 + + + state3 + state(3). + 0x23 + + + + + + + + 26 + 0x4 + LUT_TRUTH[%s] + Specifies the Truth Table contents for LUTLUTn + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTn_TRUTH + Specifies the Truth Table contents for LUT0.. + 0 + 32 + read-write + + + + + OUTPUTS + Provides the current state of the 8 designated PLU Outputs. + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTPUT_STATE + Provides the current state of the 8 designated PLU Outputs.. + 0 + 8 + read-only + + + + + WAKEINT_CTRL + Wakeup interrupt control for PLU + 0x904 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + 0 + 8 + read-write + + + FILTER_MODE + control input of the PLU, add filtering for glitch. + 8 + 2 + read-write + + + BYPASS + Bypass mode. + 0 + + + FILTER1CLK + Filter 1 clock period. + 0x1 + + + FILTER2CLK + Filter 2 clock period. + 0x2 + + + FILTER3CLK + Filter 3 clock period. + 0x3 + + + + + FILTER_CLKSEL + hclk is divided by 2**filter_clksel. + 10 + 2 + read-write + + + FRO1MHZ + Selects the 1 MHz low-power oscillator as the filter clock. + 0 + + + FRO12MHZ + Selects the 12 Mhz FRO as the filter clock. + 0x1 + + + OTHER_CLOCK + Selects a third filter clock source, if provided. + 0x2 + + + + + LATCH_ENABLE + latch the interrupt , then can be cleared with next bit INTR_CLEAR + 12 + 1 + read-write + + + INTR_CLEAR + Write to clear wakeint_latched + 13 + 1 + read-write + oneToClear + + + + + 8 + 0x4 + OUTPUT_MUX[%s] + Selects the source to be connected to PLU Output OUTPUT_n + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTPUTn + Selects the source to be connected to PLU Output 0. + 0 + 5 + read-write + + + plu_output0 + The PLU output 0. + 0 + + + plu_output1 + The PLU output 1. + 0x1 + + + plu_output2 + The PLU output 2. + 0x2 + + + plu_output3 + The PLU output 3. + 0x3 + + + plu_output4 + The PLU output 4. + 0x4 + + + plu_output5 + The PLU output 5. + 0x5 + + + plu_output6 + The PLU output 6. + 0x6 + + + plu_output7 + The PLU output 7. + 0x7 + + + plu_output8 + The PLU output 8. + 0x8 + + + plu_output9 + The PLU output 9. + 0x9 + + + plu_output10 + The PLU output 10. + 0xA + + + plu_output11 + The PLU output 11. + 0xB + + + plu_output12 + The PLU output 12. + 0xC + + + plu_output13 + The PLU output 13. + 0xD + + + plu_output14 + The PLU output 14. + 0xE + + + plu_output15 + The PLU output 15. + 0xF + + + plu_output16 + The PLU output 16. + 0x10 + + + plu_output17 + The PLU output 17. + 0x11 + + + plu_output18 + The PLU output 18. + 0x12 + + + plu_output19 + The PLU output 19. + 0x13 + + + plu_output20 + The PLU output 20. + 0x14 + + + plu_output21 + The PLU output 21. + 0x15 + + + plu_output22 + The PLU output 22. + 0x16 + + + plu_output23 + The PLU output 23. + 0x17 + + + plu_output24 + The PLU output 24. + 0x18 + + + plu_output25 + The PLU output 25. + 0x19 + + + state0 + state(0). + 0x1A + + + state1 + state(1). + 0x1B + + + state2 + state(2). + 0x1C + + + state3 + state(3). + 0x1D + + + + + + + + + DMA0 + DMA controller + DMA + DMA + 0x40082000 + + 0 + 0x56C + registers + + + DMA0 + 1 + + + + CTRL + DMA control. + 0 + 32 + read-write + 0 + 0x1 + + + ENABLE + DMA controller master enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + 0 + + + ENABLED + Enabled. The DMA controller is enabled. + 0x1 + + + + + + + INTSTAT + Interrupt status. + 0x4 + 32 + read-only + 0 + 0x6 + + + ACTIVEINT + Summarizes whether any enabled interrupts (other than error interrupts) are pending. + 1 + 1 + read-only + + + NOT_PENDING + Not pending. No enabled interrupts are pending. + 0 + + + PENDING + Pending. At least one enabled interrupt is pending. + 0x1 + + + + + ACTIVEERRINT + Summarizes whether any error interrupts are pending. + 2 + 1 + read-only + + + NOT_PENDING + Not pending. No error interrupts are pending. + 0 + + + PENDING + Pending. At least one error interrupt is pending. + 0x1 + + + + + + + SRAMBASE + SRAM address of the channel configuration table. + 0x8 + 32 + read-write + 0 + 0xFFFFFE00 + + + OFFSET + Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. + 9 + 23 + read-write + + + + + ENABLESET0 + Channel Enable read and Set for all DMA channels. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENA + Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + 0 + 32 + read-write + + + + + ENABLECLR0 + Channel Enable Clear for all DMA channels. + 0x28 + 32 + write-only + 0 + 0 + + + CLR + Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. + 0 + 32 + write-only + + + + + ACTIVE0 + Channel Active status for all DMA channels. + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + ACT + Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + 0 + 32 + read-only + + + + + BUSY0 + Channel Busy status for all DMA channels. + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + BSY + Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + 0 + 32 + read-only + + + + + ERRINT0 + Error Interrupt status for all DMA channels. + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR + Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. + 0 + 32 + read-write + + + + + INTENSET0 + Interrupt Enable read and Set for all DMA channels. + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTEN + Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + 0 + 32 + read-write + + + + + INTENCLR0 + Interrupt Enable Clear for all DMA channels. + 0x50 + 32 + write-only + 0 + 0 + + + CLR + Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. + 0 + 32 + write-only + + + + + INTA0 + Interrupt A status for all DMA channels. + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + IA + Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. + 0 + 32 + read-write + + + + + INTB0 + Interrupt B status for all DMA channels. + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + IB + Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. + 0 + 32 + read-write + + + + + SETVALID0 + Set ValidPending control bits for all DMA channels. + 0x68 + 32 + write-only + 0 + 0 + + + SV + SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n + 0 + 32 + write-only + + + + + SETTRIG0 + Set Trigger control bits for all DMA channels. + 0x70 + 32 + write-only + 0 + 0 + + + TRIG + Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. + 0 + 32 + write-only + + + + + ABORT0 + Channel Abort control for all DMA channels. + 0x78 + 32 + write-only + 0 + 0 + + + ABORTCTRL + Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. + 0 + 32 + write-only + + + + + 23 + 0x10 + CHANNEL[%s] + no description available + 0x400 + + CFG + Configuration register for DMA channel . + 0 + 32 + read-write + 0 + 0x7CF73 + + + PERIPHREQEN + Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. + 0 + 1 + read-write + + + DISABLED + Disabled. Peripheral DMA requests are disabled. + 0 + + + ENABLED + Enabled. Peripheral DMA requests are enabled. + 0x1 + + + + + HWTRIGEN + Hardware Triggering Enable for this channel. + 1 + 1 + read-write + + + DISABLED + Disabled. Hardware triggering is not used. + 0 + + + ENABLED + Enabled. Use hardware triggering. + 0x1 + + + + + TRIGPOL + Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + 4 + 1 + read-write + + + ACTIVE_LOW_FALLING + Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + 0 + + + ACTIVE_HIGH_RISING + Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + 0x1 + + + + + TRIGTYPE + Trigger Type. Selects hardware trigger as edge triggered or level triggered. + 5 + 1 + read-write + + + EDGE + Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + 0 + + + LEVEL + Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. + 0x1 + + + + + TRIGBURST + Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + 6 + 1 + read-write + + + SINGLE + Single transfer. Hardware trigger causes a single transfer. + 0 + + + BURST + Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. + 0x1 + + + + + BURSTPOWER + Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. + 8 + 4 + read-write + + + SRCBURSTWRAP + Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. + 14 + 1 + read-write + + + DISABLED + Disabled. Source burst wrapping is not enabled for this DMA channel. + 0 + + + ENABLED + Enabled. Source burst wrapping is enabled for this DMA channel. + 0x1 + + + + + DSTBURSTWRAP + Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. + 15 + 1 + read-write + + + DISABLED + Disabled. Destination burst wrapping is not enabled for this DMA channel. + 0 + + + ENABLED + Enabled. Destination burst wrapping is enabled for this DMA channel. + 0x1 + + + + + CHPRIORITY + Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + 16 + 3 + read-write + + + + + CTLSTAT + Control and status register for DMA channel . + 0x4 + 32 + read-only + 0 + 0x5 + + + VALIDPENDING + Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + 0 + 1 + read-only + + + NO_EFFECT + No effect. No effect on DMA operation. + 0 + + + VALID_PENDING + Valid pending. + 0x1 + + + + + TRIG + Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + 2 + 1 + read-only + + + NOT_TRIGGERED + Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + 0 + + + TRIGGERED + Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + 0x1 + + + + + + + XFERCFG + Transfer configuration register for DMA channel . + 0x8 + 32 + read-write + 0 + 0x3FFF33F + + + CFGVALID + Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + 0 + 1 + read-write + + + NOT_VALID + Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + 0 + + + VALID + Valid. The current channel descriptor is considered valid. + 0x1 + + + + + RELOAD + Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. + 1 + 1 + read-write + + + DISABLED + Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + 0 + + + ENABLED + Enabled. Reload the channels' control structure when the current descriptor is exhausted. + 0x1 + + + + + SWTRIG + Software Trigger. + 2 + 1 + read-write + + + NOT_SET + Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + 0 + + + SET + Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. + 0x1 + + + + + CLRTRIG + Clear Trigger. + 3 + 1 + read-write + + + NOT_CLEARED + Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + 0 + + + CLEARED + Cleared. The trigger is cleared when this descriptor is exhausted + 0x1 + + + + + SETINTA + Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + 4 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + SET + Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + 0x1 + + + + + SETINTB + Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + 5 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + SET + Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + 0x1 + + + + + WIDTH + Transfer width used for this DMA channel. + 8 + 2 + read-write + + + BIT_8 + 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + 0 + + + BIT_16 + 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + 0x1 + + + BIT_32 + 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + 0x2 + + + + + SRCINC + Determines whether the source address is incremented for each DMA transfer. + 12 + 2 + read-write + + + NO_INCREMENT + No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + 0 + + + WIDTH_X_1 + 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. + 0x1 + + + WIDTH_X_2 + 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + 0x2 + + + WIDTH_X_4 + 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + 0x3 + + + + + DSTINC + Determines whether the destination address is incremented for each DMA transfer. + 14 + 2 + read-write + + + NO_INCREMENT + No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. + 0 + + + WIDTH_X_1 + 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. + 0x1 + + + WIDTH_X_2 + 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + 0x2 + + + WIDTH_X_4 + 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + 0x3 + + + + + XFERCOUNT + Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. + 16 + 10 + read-write + + + + + + + + DMA1 + DMA controller + DMA + 0x400A7000 + + 0 + 0x49C + registers + + + DMA1 + 58 + + + + USB0 + USB 2.0 Device Controller + USB + 0x40084000 + + 0 + 0x38 + registers + + + USB0_NEEDCLK + 27 + + + USB0 + 28 + + + + DEVCMDSTAT + USB Device Command/Status register + 0 + 32 + read-write + 0x800 + 0x171BFBFF + + + DEV_ADDR + USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. + 0 + 7 + read-write + + + DEV_EN + USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + 7 + 1 + read-write + + + SETUP + SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + 8 + 1 + read-write + + + FORCE_NEEDCLK + Forces the NEEDCLK output to always be on: + 9 + 1 + read-write + + + NORMAL + USB_NEEDCLK has normal function. + 0 + + + ALWAYS_ON + USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + 0x1 + + + + + LPM_SUP + LPM Supported: + 11 + 1 + read-write + + + NO + LPM not supported. + 0 + + + YES + LPM supported. + 0x1 + + + + + INTONNAK_AO + Interrupt on NAK for interrupt and bulk OUT EP + 12 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_AI + Interrupt on NAK for interrupt and bulk IN EP + 13 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_CO + Interrupt on NAK for control OUT EP + 14 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_CI + Interrupt on NAK for control IN EP + 15 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + DCON + Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. + 16 + 1 + read-write + + + DSUS + Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + 17 + 1 + read-write + + + LPM_SUS + Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. + 19 + 1 + read-write + + + LPM_REWP + LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. + 20 + 1 + read-only + + + DCON_C + Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + 24 + 1 + read-write + + + DSUS_C + Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. + 25 + 1 + read-write + + + DRES_C + Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. + 26 + 1 + read-write + + + VBUSDEBOUNCED + This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + 28 + 1 + read-only + + + + + INFO + USB Info register + 0x4 + 32 + read-write + 0 + 0x7FFF + + + FRAME_NR + Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. + 0 + 11 + read-only + + + ERR_CODE + The error code which last occurred: + 11 + 4 + read-write + + + NO_ERROR + No error + 0 + + + PID_ENCODING_ERROR + PID encoding error + 0x1 + + + PID_UNKNOWN + PID unknown + 0x2 + + + PACKET_UNEXPECTED + Packet unexpected + 0x3 + + + TOKEN_CRC_ERROR + Token CRC error + 0x4 + + + DATA_CRC_ERROR + Data CRC error + 0x5 + + + TIMEOUT + Time out + 0x6 + + + BABBLE + Babble + 0x7 + + + TRUNCATED_EOP + Truncated EOP + 0x8 + + + SENT_RECEIVED_NAK + Sent/Received NAK + 0x9 + + + SENT_STALL + Sent Stall + 0xA + + + OVERRUN + Overrun + 0xB + + + SENT_EMPTY_PACKET + Sent empty packet + 0xC + + + BITSTUFF_ERROR + Bitstuff error + 0xD + + + SYNC_ERROR + Sync error + 0xE + + + WRONG_DATA_TOGGLE + Wrong data toggle + 0xF + + + + + MINREV + Minor Revision. + 16 + 8 + read-only + + + MAJREV + Major Revision. + 24 + 8 + read-only + + + + + EPLISTSTART + USB EP Command/Status List start address + 0x8 + 32 + read-write + 0 + 0xFFFFFF00 + + + EP_LIST + Start address of the USB EP Command/Status List. + 8 + 24 + read-write + + + + + DATABUFSTART + USB Data buffer start address + 0xC + 32 + read-write + 0 + 0xFFC00000 + + + DA_BUF + Start address of the buffer pointer page where all endpoint data buffers are located. + 22 + 10 + read-write + + + + + LPM + USB Link Power Management register + 0x10 + 32 + read-write + 0 + 0x1FF + + + HIRD_HW + Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + 0 + 4 + read-only + + + HIRD_SW + Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + 4 + 4 + read-write + + + DATA_PENDING + As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. + 8 + 1 + read-write + + + + + EPSKIP + USB Endpoint skip + 0x14 + 32 + read-write + 0 + 0x3FFFFFFF + + + SKIP + Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + 0 + 10 + read-write + + + + + EPINUSE + USB Endpoint Buffer in use + 0x18 + 32 + read-write + 0 + 0x3FC + + + BUF + Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. + 2 + 8 + read-write + + + + + EPBUFCFG + USB Endpoint Buffer Configuration register + 0x1C + 32 + read-write + 0 + 0x3FC + + + BUF_SB + Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. + 2 + 8 + read-write + + + + + INTSTAT + USB interrupt status register + 0x20 + 32 + read-write + 0 + 0xC00003FF + + + EP0OUT + Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. + 0 + 1 + read-write + + + EP0IN + Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. + 1 + 1 + read-write + + + EP1OUT + Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. + 2 + 1 + read-write + + + EP1IN + Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. + 3 + 1 + read-write + + + EP2OUT + Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. + 4 + 1 + read-write + + + EP2IN + Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. + 5 + 1 + read-write + + + EP3OUT + Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. + 6 + 1 + read-write + + + EP3IN + Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. + 7 + 1 + read-write + + + EP4OUT + Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. + 8 + 1 + read-write + + + EP4IN + Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. + 9 + 1 + read-write + + + FRAME_INT + Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. + 30 + 1 + read-write + + + DEV_INT + Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. + 31 + 1 + read-write + + + + + INTEN + USB interrupt enable register + 0x24 + 32 + read-write + 0 + 0xC00003FF + + + EP_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 0 + 10 + read-write + + + FRAME_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 30 + 1 + read-write + + + DEV_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 31 + 1 + read-write + + + + + INTSETSTAT + USB set interrupt status register + 0x28 + 32 + read-write + 0 + 0xC00003FF + + + EP_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 0 + 10 + read-write + + + FRAME_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 30 + 1 + read-write + + + DEV_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 31 + 1 + read-write + + + + + EPTOGGLE + USB Endpoint toggle register + 0x34 + 32 + read-write + 0 + 0x3FF + + + TOGGLE + Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + 0 + 10 + read-write + + + + + + + SCT0 + SCTimer/PWM (SCT) + SCT + 0x40085000 + + 0 + 0x550 + registers + + + SCT0 + 12 + + + + CONFIG + SCT configuration register + 0 + 32 + read-write + 0x1E00 + 0x61FFF + + + UNIFY + SCT operation + 0 + 1 + read-write + + + DUAL_COUNTER + The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + 0 + + + UNIFIED_COUNTER + The SCT operates as a unified 32-bit counter. + 0x1 + + + + + CLKMODE + SCT clock mode + 1 + 2 + read-write + + + SYSTEM_CLOCK_MODE + System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + 0 + + + SAMPLED_SYSTEM_CLOCK_MODE + Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. + 0x1 + + + SCT_INPUT_CLOCK_MODE + SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + 0x2 + + + ASYNCHRONOUS_MODE + Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. + 0x3 + + + + + CKSEL + SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. + 3 + 4 + read-write + + + INPUT_0_RISING_EDGES + Rising edges on input 0. + 0 + + + INPUT_0_FALLING_EDGE + Falling edges on input 0. + 0x1 + + + INPUT_1_RISING_EDGES + Rising edges on input 1. + 0x2 + + + INPUT_1_FALLING_EDGE + Falling edges on input 1. + 0x3 + + + INPUT_2_RISING_EDGES + Rising edges on input 2. + 0x4 + + + INPUT_2_FALLING_EDGE + Falling edges on input 2. + 0x5 + + + INPUT_3_RISING_EDGES + Rising edges on input 3. + 0x6 + + + INPUT_3_FALLING_EDGE + Falling edges on input 3. + 0x7 + + + INPUT_4_RISING_EDGES + Rising edges on input 4. + 0x8 + + + INPUT_4_FALLING_EDGE + Falling edges on input 4. + 0x9 + + + INPUT_5_RISING_EDGES + Rising edges on input 5. + 0xA + + + INPUT_5_FALLING_EDGE + Falling edges on input 5. + 0xB + + + INPUT_6_RISING_EDGES + Rising edges on input 6. + 0xC + + + INPUT_6_FALLING_EDGE + Falling edges on input 6. + 0xD + + + INPUT_7_RISING_EDGES + Rising edges on input 7. + 0xE + + + INPUT_7_FALLING_EDGE + Falling edges on input 7. + 0xF + + + + + NORELOAD_L + A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + 7 + 1 + read-write + + + NORELOAD_H + A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. + 8 + 1 + read-write + + + INSYNC + Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. + 9 + 4 + read-write + + + AUTOLIMIT_L + A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + 17 + 1 + read-write + + + AUTOLIMIT_H + A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. + 18 + 1 + read-write + + + + + CTRL + SCT control register + 0x4 + 32 + read-write + 0x40004 + 0x1FFF1FFF + + + DOWN_L + This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. + 0 + 1 + read-write + + + STOP_L + When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. + 1 + 1 + read-write + + + HALT_L + When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. + 2 + 1 + read-write + + + CLRCTR_L + Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + 3 + 1 + read-write + + + BIDIR_L + L or unified counter direction select + 4 + 1 + read-write + + + UP + Up. The counter counts up to a limit condition, then is cleared to zero. + 0 + + + UP_DOWN + Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + 0x1 + + + + + PRE_L + Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + 5 + 8 + read-write + + + DOWN_H + This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. + 16 + 1 + read-write + + + STOP_H + When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. + 17 + 1 + read-write + + + HALT_H + When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. + 18 + 1 + read-write + + + CLRCTR_H + Writing a 1 to this bit clears the H counter. This bit always reads as 0. + 19 + 1 + read-write + + + BIDIR_H + Direction select + 20 + 1 + read-write + + + UP + The H counter counts up to its limit condition, then is cleared to zero. + 0 + + + UP_DOWN + The H counter counts up to its limit, then counts down to a limit condition or to 0. + 0x1 + + + + + PRE_H + Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + 21 + 8 + read-write + + + + + LIMIT + SCT limit event select register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LIMMSK_L + If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + LIMMSK_H + If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + HALT + SCT halt event select register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTMSK_L + If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + HALTMSK_H + If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + STOP + SCT stop event select register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + STOPMSK_L + If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + STOPMSK_H + If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + START + SCT start event select register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + STARTMSK_L + If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + STARTMSK_H + If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + COUNT + SCT counter register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTR_L + When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. + 0 + 16 + read-write + + + CTR_H + When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. + 16 + 16 + read-write + + + + + STATE + SCT state register + 0x44 + 32 + read-write + 0 + 0x1F001F + + + STATE_L + State variable. + 0 + 5 + read-write + + + STATE_H + State variable. + 16 + 5 + read-write + + + + + INPUT + SCT input register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + AIN0 + Input 0 state. Input 0 state on the last SCT clock edge. + 0 + 1 + read-only + + + AIN1 + Input 1 state. Input 1 state on the last SCT clock edge. + 1 + 1 + read-only + + + AIN2 + Input 2 state. Input 2 state on the last SCT clock edge. + 2 + 1 + read-only + + + AIN3 + Input 3 state. Input 3 state on the last SCT clock edge. + 3 + 1 + read-only + + + AIN4 + Input 4 state. Input 4 state on the last SCT clock edge. + 4 + 1 + read-only + + + AIN5 + Input 5 state. Input 5 state on the last SCT clock edge. + 5 + 1 + read-only + + + AIN6 + Input 6 state. Input 6 state on the last SCT clock edge. + 6 + 1 + read-only + + + AIN7 + Input 7 state. Input 7 state on the last SCT clock edge. + 7 + 1 + read-only + + + AIN8 + Input 8 state. Input 8 state on the last SCT clock edge. + 8 + 1 + read-only + + + AIN9 + Input 9 state. Input 9 state on the last SCT clock edge. + 9 + 1 + read-only + + + AIN10 + Input 10 state. Input 10 state on the last SCT clock edge. + 10 + 1 + read-only + + + AIN11 + Input 11 state. Input 11 state on the last SCT clock edge. + 11 + 1 + read-only + + + AIN12 + Input 12 state. Input 12 state on the last SCT clock edge. + 12 + 1 + read-only + + + AIN13 + Input 13 state. Input 13 state on the last SCT clock edge. + 13 + 1 + read-only + + + AIN14 + Input 14 state. Input 14 state on the last SCT clock edge. + 14 + 1 + read-only + + + AIN15 + Input 15 state. Input 15 state on the last SCT clock edge. + 15 + 1 + read-only + + + SIN0 + Input 0 state. Input 0 state following the synchronization specified by INSYNC. + 16 + 1 + read-only + + + SIN1 + Input 1 state. Input 1 state following the synchronization specified by INSYNC. + 17 + 1 + read-only + + + SIN2 + Input 2 state. Input 2 state following the synchronization specified by INSYNC. + 18 + 1 + read-only + + + SIN3 + Input 3 state. Input 3 state following the synchronization specified by INSYNC. + 19 + 1 + read-only + + + SIN4 + Input 4 state. Input 4 state following the synchronization specified by INSYNC. + 20 + 1 + read-only + + + SIN5 + Input 5 state. Input 5 state following the synchronization specified by INSYNC. + 21 + 1 + read-only + + + SIN6 + Input 6 state. Input 6 state following the synchronization specified by INSYNC. + 22 + 1 + read-only + + + SIN7 + Input 7 state. Input 7 state following the synchronization specified by INSYNC. + 23 + 1 + read-only + + + SIN8 + Input 8 state. Input 8 state following the synchronization specified by INSYNC. + 24 + 1 + read-only + + + SIN9 + Input 9 state. Input 9 state following the synchronization specified by INSYNC. + 25 + 1 + read-only + + + SIN10 + Input 10 state. Input 10 state following the synchronization specified by INSYNC. + 26 + 1 + read-only + + + SIN11 + Input 11 state. Input 11 state following the synchronization specified by INSYNC. + 27 + 1 + read-only + + + SIN12 + Input 12 state. Input 12 state following the synchronization specified by INSYNC. + 28 + 1 + read-only + + + SIN13 + Input 13 state. Input 13 state following the synchronization specified by INSYNC. + 29 + 1 + read-only + + + SIN14 + Input 14 state. Input 14 state following the synchronization specified by INSYNC. + 30 + 1 + read-only + + + SIN15 + Input 15 state. Input 15 state following the synchronization specified by INSYNC. + 31 + 1 + read-only + + + + + REGMODE + SCT match/capture mode register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + REGMOD_L + Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. + 0 + 16 + read-write + + + REGMOD_H + Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. + 16 + 16 + read-write + + + + + OUTPUT + SCT output register + 0x50 + 32 + read-write + 0 + 0xFFFF + + + OUT + Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + + + OUTPUTDIRCTRL + SCT output counter direction control register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETCLR0 + Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + 0 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR1 + Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + 2 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR2 + Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + 4 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR3 + Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + 6 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR4 + Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + 8 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR5 + Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + 10 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR6 + Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + 12 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR7 + Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + 14 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR8 + Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + 16 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR9 + Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + 18 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR10 + Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + 20 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR11 + Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + 22 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR12 + Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + 24 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR13 + Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + 26 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR14 + Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + 28 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR15 + Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + 30 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + + + RES + SCT conflict resolution register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + O0RES + Effect of simultaneous set and clear on output 0. + 0 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR0 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O1RES + Effect of simultaneous set and clear on output 1. + 2 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR1 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O2RES + Effect of simultaneous set and clear on output 2. + 4 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output n (or set based on the SETCLR2 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O3RES + Effect of simultaneous set and clear on output 3. + 6 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR3 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O4RES + Effect of simultaneous set and clear on output 4. + 8 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR4 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O5RES + Effect of simultaneous set and clear on output 5. + 10 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR5 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O6RES + Effect of simultaneous set and clear on output 6. + 12 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR6 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O7RES + Effect of simultaneous set and clear on output 7. + 14 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output n (or set based on the SETCLR7 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O8RES + Effect of simultaneous set and clear on output 8. + 16 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR8 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O9RES + Effect of simultaneous set and clear on output 9. + 18 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR9 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O10RES + Effect of simultaneous set and clear on output 10. + 20 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR10 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O11RES + Effect of simultaneous set and clear on output 11. + 22 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR11 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O12RES + Effect of simultaneous set and clear on output 12. + 24 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR12 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O13RES + Effect of simultaneous set and clear on output 13. + 26 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR13 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O14RES + Effect of simultaneous set and clear on output 14. + 28 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR14 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O15RES + Effect of simultaneous set and clear on output 15. + 30 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR15 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + + + DMAREQ0 + SCT DMA request 0 register + 0x5C + 32 + read-write + 0 + 0xC000FFFF + + + DEV_0 + If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + DRL0 + A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + 30 + 1 + read-write + + + DRQ0 + This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. + 31 + 1 + read-write + + + + + DMAREQ1 + SCT DMA request 1 register + 0x60 + 32 + read-write + 0 + 0xC000FFFF + + + DEV_1 + If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + DRL1 + A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + 30 + 1 + read-write + + + DRQ1 + This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. + 31 + 1 + read-write + + + + + EVEN + SCT event interrupt enable register + 0xF0 + 32 + read-write + 0 + 0xFFFF + + + IEN + The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + + + EVFLAG + SCT event flag register + 0xF4 + 32 + read-write + 0 + 0xFFFF + + + FLAG + Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + + + CONEN + SCT conflict interrupt enable register + 0xF8 + 32 + read-write + 0 + 0xFFFF + + + NCEN + The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + + + CONFLAG + SCT conflict flag register + 0xFC + 32 + read-write + 0 + 0xC000FFFF + + + NCFLAG + Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + BUSERRL + The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. + 30 + 1 + read-write + + + BUSERRH + The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. + 31 + 1 + read-write + + + + + CAP0 + SCT capture register of capture channel + CAP_MATCH + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH0 + SCT match value register of match channels + CAP_MATCH + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP1 + SCT capture register of capture channel + CAP_MATCH + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH1 + SCT match value register of match channels + CAP_MATCH + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP2 + SCT capture register of capture channel + CAP_MATCH + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH2 + SCT match value register of match channels + CAP_MATCH + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP3 + SCT capture register of capture channel + CAP_MATCH + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH3 + SCT match value register of match channels + CAP_MATCH + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP4 + SCT capture register of capture channel + CAP_MATCH + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH4 + SCT match value register of match channels + CAP_MATCH + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP5 + SCT capture register of capture channel + CAP_MATCH + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH5 + SCT match value register of match channels + CAP_MATCH + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP6 + SCT capture register of capture channel + CAP_MATCH + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH6 + SCT match value register of match channels + CAP_MATCH + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP7 + SCT capture register of capture channel + CAP_MATCH + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH7 + SCT match value register of match channels + CAP_MATCH + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP8 + SCT capture register of capture channel + CAP_MATCH + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH8 + SCT match value register of match channels + CAP_MATCH + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP9 + SCT capture register of capture channel + CAP_MATCH + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH9 + SCT match value register of match channels + CAP_MATCH + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP10 + SCT capture register of capture channel + CAP_MATCH + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH10 + SCT match value register of match channels + CAP_MATCH + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP11 + SCT capture register of capture channel + CAP_MATCH + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH11 + SCT match value register of match channels + CAP_MATCH + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP12 + SCT capture register of capture channel + CAP_MATCH + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH12 + SCT match value register of match channels + CAP_MATCH + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP13 + SCT capture register of capture channel + CAP_MATCH + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH13 + SCT match value register of match channels + CAP_MATCH + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP14 + SCT capture register of capture channel + CAP_MATCH + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH14 + SCT match value register of match channels + CAP_MATCH + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAP15 + SCT capture register of capture channel + CAP_MATCH + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + MATCH15 + SCT match value register of match channels + CAP_MATCH + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + CAPCTRL0 + SCT capture control register + CAPCTRL_MATCHREL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL0 + SCT match reload value register + CAPCTRL_MATCHREL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL1 + SCT capture control register + CAPCTRL_MATCHREL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL1 + SCT match reload value register + CAPCTRL_MATCHREL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL2 + SCT capture control register + CAPCTRL_MATCHREL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL2 + SCT match reload value register + CAPCTRL_MATCHREL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL3 + SCT capture control register + CAPCTRL_MATCHREL + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL3 + SCT match reload value register + CAPCTRL_MATCHREL + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL4 + SCT capture control register + CAPCTRL_MATCHREL + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL4 + SCT match reload value register + CAPCTRL_MATCHREL + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL5 + SCT capture control register + CAPCTRL_MATCHREL + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL5 + SCT match reload value register + CAPCTRL_MATCHREL + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL6 + SCT capture control register + CAPCTRL_MATCHREL + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL6 + SCT match reload value register + CAPCTRL_MATCHREL + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL7 + SCT capture control register + CAPCTRL_MATCHREL + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL7 + SCT match reload value register + CAPCTRL_MATCHREL + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL8 + SCT capture control register + CAPCTRL_MATCHREL + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL8 + SCT match reload value register + CAPCTRL_MATCHREL + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL9 + SCT capture control register + CAPCTRL_MATCHREL + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL9 + SCT match reload value register + CAPCTRL_MATCHREL + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL10 + SCT capture control register + CAPCTRL_MATCHREL + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL10 + SCT match reload value register + CAPCTRL_MATCHREL + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL11 + SCT capture control register + CAPCTRL_MATCHREL + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL11 + SCT match reload value register + CAPCTRL_MATCHREL + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL12 + SCT capture control register + CAPCTRL_MATCHREL + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL12 + SCT match reload value register + CAPCTRL_MATCHREL + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL13 + SCT capture control register + CAPCTRL_MATCHREL + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL13 + SCT match reload value register + CAPCTRL_MATCHREL + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL14 + SCT capture control register + CAPCTRL_MATCHREL + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL14 + SCT match reload value register + CAPCTRL_MATCHREL + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + CAPCTRL15 + SCT capture control register + CAPCTRL_MATCHREL + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + MATCHREL15 + SCT match reload value register + CAPCTRL_MATCHREL + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + 16 + 0x8 + EV[%s] + no description available + 0x300 + + EV_STATE + SCT event state register 0 + 0 + 32 + read-write + 0 + 0xFFFF + + + STATEMSKn + If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. + 0 + 16 + read-write + + + + + EV_CTRL + SCT event control register 0 + 0x4 + 32 + read-write + 0 + 0x7FFFFF + + + MATCHSEL + Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. + 0 + 4 + read-write + + + HEVENT + Select L/H counter. Do not set this bit if UNIFY = 1. + 4 + 1 + read-write + + + L_COUNTER + Selects the L state and the L match register selected by MATCHSEL. + 0 + + + H_COUNTER + Selects the H state and the H match register selected by MATCHSEL. + 0x1 + + + + + OUTSEL + Input/output select + 5 + 1 + read-write + + + INPUT + Selects the inputs selected by IOSEL. + 0 + + + OUTPUT + Selects the outputs selected by IOSEL. + 0x1 + + + + + IOSEL + Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. + 6 + 4 + read-write + + + IOCOND + Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . + 10 + 2 + read-write + + + LOW + LOW + 0 + + + RISE + Rise + 0x1 + + + FALL + Fall + 0x2 + + + HIGH + HIGH + 0x3 + + + + + COMBMODE + Selects how the specified match and I/O condition are used and combined. + 12 + 2 + read-write + + + OR + OR. The event occurs when either the specified match or I/O condition occurs. + 0 + + + MATCH + MATCH. Uses the specified match only. + 0x1 + + + IO + IO. Uses the specified I/O condition only. + 0x2 + + + AND + AND. The event occurs when the specified match and I/O condition occur simultaneously. + 0x3 + + + + + STATELD + This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. + 14 + 1 + read-write + + + ADD + STATEV value is added into STATE (the carry-out is ignored). + 0 + + + LOAD + STATEV value is loaded into STATE. + 0x1 + + + + + STATEV + This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. + 15 + 5 + read-write + + + MATCHMEM + If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. + 20 + 1 + read-write + + + DIRECTION + Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + 21 + 2 + read-write + + + DIRECTION_INDEPENDENT + Direction independent. This event is triggered regardless of the count direction. + 0 + + + COUNTING_UP + Counting up. This event is triggered only during up-counting when BIDIR = 1. + 0x1 + + + COUNTING_DOWN + Counting down. This event is triggered only during down-counting when BIDIR = 1. + 0x2 + + + + + + + + 10 + 0x8 + OUT[%s] + no description available + 0x500 + + OUT_SET + SCT output 0 set register + 0 + 32 + read-write + 0 + 0xFFFF + + + SET + A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. + 0 + 16 + read-write + + + + + OUT_CLR + SCT output 0 clear register + 0x4 + 32 + read-write + 0 + 0xFFFF + + + CLR + A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. + 0 + 16 + read-write + + + + + + + + FLEXCOMM0 + Flexcomm serial communication + FLEXCOMM + FLEXCOMM + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + PSELID + Peripheral Select and Flexcomm ID register. + 0xFF8 + 32 + read-write + 0x101000 + 0xFFFFF0FF + + + PERSEL + Peripheral Select. This field is writable by software. + 0 + 3 + read-write + + + NO_PERIPH_SELECTED + No peripheral selected. + 0 + + + USART + USART function selected. + 0x1 + + + SPI + SPI function selected. + 0x2 + + + I2C + I2C function selected. + 0x3 + + + I2S_TRANSMIT + I2S transmit function selected. + 0x4 + + + I2S_RECEIVE + I2S receive function selected. + 0x5 + + + + + LOCK + Lock the peripheral select. This field is writable by software. + 3 + 1 + read-write + + + UNLOCKED + Peripheral select can be changed by software. + 0 + + + LOCKED + Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + 0x1 + + + + + USARTPRESENT + USART present indicator. This field is Read-only. + 4 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the USART function. + 0 + + + PRESENT + This Flexcomm includes the USART function. + 0x1 + + + + + SPIPRESENT + SPI present indicator. This field is Read-only. + 5 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the SPI function. + 0 + + + PRESENT + This Flexcomm includes the SPI function. + 0x1 + + + + + I2CPRESENT + I2C present indicator. This field is Read-only. + 6 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the I2C function. + 0 + + + PRESENT + This Flexcomm includes the I2C function. + 0x1 + + + + + I2SPRESENT + I 2S present indicator. This field is Read-only. + 7 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the I2S function. + 0 + + + PRESENT + This Flexcomm includes the I2S function. + 0x1 + + + + + ID + Flexcomm ID. + 12 + 20 + read-only + + + + + PID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + size aperture for the register port on the bus (APB or AHB). + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + FLEXCOMM1 + Flexcomm serial communication + FLEXCOMM + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + FLEXCOMM2 + Flexcomm serial communication + FLEXCOMM + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + FLEXCOMM3 + Flexcomm serial communication + FLEXCOMM + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + FLEXCOMM4 + Flexcomm serial communication + FLEXCOMM + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + FLEXCOMM5 + Flexcomm serial communication + FLEXCOMM + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + FLEXCOMM6 + Flexcomm serial communication + FLEXCOMM + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + FLEXCOMM7 + Flexcomm serial communication + FLEXCOMM + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + FLEXCOMM8 + Flexcomm serial communication + FLEXCOMM + 0x4009F000 + + 0 + 0x1000 + registers + + + FLEXCOMM8 + 59 + + + + I2C0 + I2C-bus interfaces + FLEXCOMM0 + I2C + I2C + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + Configuration for shared functions. + 0x800 + 32 + read-write + 0 + 0x3F + + + MSTEN + Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. + 0 + 1 + read-write + + + DISABLED + Disabled. The I2C Master function is disabled. + 0 + + + ENABLED + Enabled. The I2C Master function is enabled. + 0x1 + + + + + SLVEN + Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. + 1 + 1 + read-write + + + DISABLED + Disabled. The I2C slave function is disabled. + 0 + + + ENABLED + Enabled. The I2C slave function is enabled. + 0x1 + + + + + MONEN + Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. + 2 + 1 + read-write + + + DISABLED + Disabled. The I2C Monitor function is disabled. + 0 + + + ENABLED + Enabled. The I2C Monitor function is enabled. + 0x1 + + + + + TIMEOUTEN + I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + 3 + 1 + read-write + + + DISABLED + Disabled. Time-out function is disabled. + 0 + + + ENABLED + Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. + 0x1 + + + + + MONCLKSTR + Monitor function Clock Stretching. + 4 + 1 + read-write + + + DISABLED + Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. + 0 + + + ENABLED + Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. + 0x1 + + + + + HSCAPABLE + High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. + 5 + 1 + read-write + + + FAST_MODE_PLUS + Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, + 0 + + + HIGH_SPEED + High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. + 0x1 + + + + + + + STAT + Status register for Master, Slave, and Monitor functions. + 0x804 + 32 + read-write + 0x801 + 0x30FFF5F + + + MSTPENDING + Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. + 0 + 1 + read-only + + + IN_PROGRESS + In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + 0 + + + PENDING + Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. + 0x1 + + + + + MSTSTATE + Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. + 1 + 3 + read-only + + + IDLE + Idle. The Master function is available to be used for a new transaction. + 0 + + + RECEIVE_READY + Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + 0x1 + + + TRANSMIT_READY + Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + 0x2 + + + NACK_ADDRESS + NACK Address. Slave NACKed address. + 0x3 + + + NACK_DATA + NACK Data. Slave NACKed transmitted data. + 0x4 + + + + + MSTARBLOSS + Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + 4 + 1 + read-write + + + NO_LOSS + No Arbitration Loss has occurred. + 0 + + + ARBITRATION_LOSS + Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + 0x1 + + + + + MSTSTSTPERR + Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + 6 + 1 + read-write + + + NO_ERROR + No Start/Stop Error has occurred. + 0 + + + ERROR + The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. + 0x1 + + + + + SLVPENDING + Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. + 8 + 1 + read-only + + + IN_PROGRESS + In progress. The Slave function does not currently need service. + 0 + + + PENDING + Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + 0x1 + + + + + SLVSTATE + Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. + 9 + 2 + read-only + + + SLAVE_ADDRESS + Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + 0 + + + SLAVE_RECEIVE + Slave receive. Received data is available (Slave Receiver mode). + 0x1 + + + SLAVE_TRANSMIT + Slave transmit. Data can be transmitted (Slave Transmitter mode). + 0x2 + + + + + SLVNOTSTR + Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. + 11 + 1 + read-only + + + STRETCHING + Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + 0 + + + NOT_STRETCHING + Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. + 0x1 + + + + + SLVIDX + Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. + 12 + 2 + read-only + + + ADDRESS0 + Address 0. Slave address 0 was matched. + 0 + + + ADDRESS1 + Address 1. Slave address 1 was matched. + 0x1 + + + ADDRESS2 + Address 2. Slave address 2 was matched. + 0x2 + + + ADDRESS3 + Address 3. Slave address 3 was matched. + 0x3 + + + + + SLVSEL + Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. + 14 + 1 + read-only + + + NOT_SELECTED + Not selected. The Slave function is not currently selected. + 0 + + + SELECTED + Selected. The Slave function is currently selected. + 0x1 + + + + + SLVDESEL + Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. + 15 + 1 + read-write + + + NOT_DESELECTED + Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. + 0 + + + DESELECTED + Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + 0x1 + + + + + MONRDY + Monitor Ready. This flag is cleared when the MONRXDAT register is read. + 16 + 1 + read-only + + + NO_DATA + No data. The Monitor function does not currently have data available. + 0 + + + DATA_WAITING + Data waiting. The Monitor function has data waiting to be read. + 0x1 + + + + + MONOV + Monitor Overflow flag. + 17 + 1 + read-write + + + NO_OVERRUN + No overrun. Monitor data has not overrun. + 0 + + + OVERRUN + Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + 0x1 + + + + + MONACTIVE + Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. + 18 + 1 + read-only + + + INACTIVE + Inactive. The Monitor function considers the I2C bus to be inactive. + 0 + + + ACTIVE + Active. The Monitor function considers the I2C bus to be active. + 0x1 + + + + + MONIDLE + Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. + 19 + 1 + read-write + + + NOT_IDLE + Not idle. The I2C bus is not idle, or this flag has been cleared by software. + 0 + + + IDLE + Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + 0x1 + + + + + EVENTTIMEOUT + Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. + 24 + 1 + read-write + + + NO_TIMEOUT + No time-out. I2C bus events have not caused a time-out. + 0 + + + EVEN_TIMEOUT + Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + 0x1 + + + + + SCLTIMEOUT + SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + 25 + 1 + read-write + + + NO_TIMEOUT + No time-out. SCL low time has not caused a time-out. + 0 + + + TIMEOUT + Time-out. SCL low time has caused a time-out. + 0x1 + + + + + + + INTENSET + Interrupt Enable Set and read register. + 0x808 + 32 + read-write + 0 + 0x30B8951 + + + MSTPENDINGEN + Master Pending interrupt Enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The MstPending interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstPending interrupt is enabled. + 0x1 + + + + + MSTARBLOSSEN + Master Arbitration Loss interrupt Enable. + 4 + 1 + read-write + + + DISABLED + Disabled. The MstArbLoss interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstArbLoss interrupt is enabled. + 0x1 + + + + + MSTSTSTPERREN + Master Start/Stop Error interrupt Enable. + 6 + 1 + read-write + + + DISABLED + Disabled. The MstStStpErr interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstStStpErr interrupt is enabled. + 0x1 + + + + + SLVPENDINGEN + Slave Pending interrupt Enable. + 8 + 1 + read-write + + + DISABLED + Disabled. The SlvPending interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvPending interrupt is enabled. + 0x1 + + + + + SLVNOTSTREN + Slave Not Stretching interrupt Enable. + 11 + 1 + read-write + + + DISABLED + Disabled. The SlvNotStr interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvNotStr interrupt is enabled. + 0x1 + + + + + SLVDESELEN + Slave Deselect interrupt Enable. + 15 + 1 + read-write + + + DISABLED + Disabled. The SlvDeSel interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvDeSel interrupt is enabled. + 0x1 + + + + + MONRDYEN + Monitor data Ready interrupt Enable. + 16 + 1 + read-write + + + DISABLED + Disabled. The MonRdy interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonRdy interrupt is enabled. + 0x1 + + + + + MONOVEN + Monitor Overrun interrupt Enable. + 17 + 1 + read-write + + + DISABLED + Disabled. The MonOv interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonOv interrupt is enabled. + 0x1 + + + + + MONIDLEEN + Monitor Idle interrupt Enable. + 19 + 1 + read-write + + + DISABLED + Disabled. The MonIdle interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonIdle interrupt is enabled. + 0x1 + + + + + EVENTTIMEOUTEN + Event time-out interrupt Enable. + 24 + 1 + read-write + + + DISABLED + Disabled. The Event time-out interrupt is disabled. + 0 + + + ENABLED + Enabled. The Event time-out interrupt is enabled. + 0x1 + + + + + SCLTIMEOUTEN + SCL time-out interrupt Enable. + 25 + 1 + read-write + + + DISABLED + Disabled. The SCL time-out interrupt is disabled. + 0 + + + ENABLED + Enabled. The SCL time-out interrupt is enabled. + 0x1 + + + + + + + INTENCLR + Interrupt Enable Clear register. + 0x80C + 32 + write-only + 0 + 0 + + + MSTPENDINGCLR + Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. + 0 + 1 + write-only + + + MSTARBLOSSCLR + Master Arbitration Loss interrupt clear. + 4 + 1 + write-only + + + MSTSTSTPERRCLR + Master Start/Stop Error interrupt clear. + 6 + 1 + write-only + + + SLVPENDINGCLR + Slave Pending interrupt clear. + 8 + 1 + write-only + + + SLVNOTSTRCLR + Slave Not Stretching interrupt clear. + 11 + 1 + write-only + + + SLVDESELCLR + Slave Deselect interrupt clear. + 15 + 1 + write-only + + + MONRDYCLR + Monitor data Ready interrupt clear. + 16 + 1 + write-only + + + MONOVCLR + Monitor Overrun interrupt clear. + 17 + 1 + write-only + + + MONIDLECLR + Monitor Idle interrupt clear. + 19 + 1 + write-only + + + EVENTTIMEOUTCLR + Event time-out interrupt clear. + 24 + 1 + write-only + + + SCLTIMEOUTCLR + SCL time-out interrupt clear. + 25 + 1 + write-only + + + + + TIMEOUT + Time-out value register. + 0x810 + 32 + read-write + 0xFFFF + 0xFFFF + + + TOMIN + Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + 0 + 4 + read-write + + + TO + Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. + 4 + 12 + read-write + + + + + CLKDIV + Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. + 0x814 + 32 + read-write + 0 + 0xFFFF + + + DIVVAL + This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. + 0 + 16 + read-write + + + + + INTSTAT + Interrupt Status register for Master, Slave, and Monitor functions. + 0x818 + 32 + read-only + 0x801 + 0x30B8951 + + + MSTPENDING + Master Pending. + 0 + 1 + read-only + + + MSTARBLOSS + Master Arbitration Loss flag. + 4 + 1 + read-only + + + MSTSTSTPERR + Master Start/Stop Error flag. + 6 + 1 + read-only + + + SLVPENDING + Slave Pending. + 8 + 1 + read-only + + + SLVNOTSTR + Slave Not Stretching status. + 11 + 1 + read-only + + + SLVDESEL + Slave Deselected flag. + 15 + 1 + read-only + + + MONRDY + Monitor Ready. + 16 + 1 + read-only + + + MONOV + Monitor Overflow flag. + 17 + 1 + read-only + + + MONIDLE + Monitor Idle flag. + 19 + 1 + read-only + + + EVENTTIMEOUT + Event time-out Interrupt flag. + 24 + 1 + read-only + + + SCLTIMEOUT + SCL time-out Interrupt flag. + 25 + 1 + read-only + + + + + MSTCTL + Master control register. + 0x820 + 32 + read-write + 0 + 0xE + + + MSTCONTINUE + Master Continue. This bit is write-only. + 0 + 1 + write-only + + + NO_EFFECT + No effect. + 0 + + + CONTINUE + Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. + 0x1 + + + + + MSTSTART + Master Start control. This bit is write-only. + 1 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + START + Start. A Start will be generated on the I2C bus at the next allowed time. + 0x1 + + + + + MSTSTOP + Master Stop control. This bit is write-only. + 2 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + STOP + Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). + 0x1 + + + + + MSTDMA + Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. + 3 + 1 + read-write + + + DISABLED + Disable. No DMA requests are generated for master operation. + 0 + + + ENABLED + Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + 0x1 + + + + + + + MSTTIME + Master timing configuration. + 0x824 + 32 + read-write + 0x77 + 0x77 + + + MSTSCLLOW + Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + 0 + 3 + read-write + + + CLOCKS_2 + 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + 0 + + + CLOCKS_3 + 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + 0x1 + + + CLOCKS_4 + 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + 0x2 + + + CLOCKS_5 + 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + 0x3 + + + CLOCKS_6 + 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + 0x4 + + + CLOCKS_7 + 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + 0x5 + + + CLOCKS_8 + 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + 0x6 + + + CLOCKS_9 + 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + 0x7 + + + + + MSTSCLHIGH + Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + 4 + 3 + read-write + + + CLOCKS_2 + 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + 0 + + + CLOCKS_3 + 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + 0x1 + + + CLOCKS_4 + 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + 0x2 + + + CLOCKS_5 + 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + 0x3 + + + CLOCKS_6 + 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + 0x4 + + + CLOCKS_7 + 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + 0x5 + + + CLOCKS_8 + 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + 0x6 + + + CLOCKS_9 + 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + 0x7 + + + + + + + MSTDAT + Combined Master receiver and transmitter data register. + 0x828 + 32 + read-write + 0 + 0xFF + + + DATA + Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. + 0 + 8 + read-write + + + + + SLVCTL + Slave control register. + 0x840 + 32 + read-write + 0 + 0x30B + + + SLVCONTINUE + Slave Continue. + 0 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + CONTINUE + Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. + 0x1 + + + + + SLVNACK + Slave NACK. + 1 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + NACK + NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + 0x1 + + + + + SLVDMA + Slave DMA enable. + 3 + 1 + read-write + + + DISABLED + Disabled. No DMA requests are issued for Slave mode operation. + 0 + + + ENABLED + Enabled. DMA requests are issued for I2C slave data transmission and reception. + 0x1 + + + + + AUTOACK + Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. + 8 + 1 + read-write + + + NORMAL + Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + 0 + + + AUTOMATIC_ACK + A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + 0x1 + + + + + AUTOMATCHREAD + When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. + 9 + 1 + read-write + + + I2C_WRITE + The expected next operation in Automatic Mode is an I2C write. + 0 + + + I2C_READ + The expected next operation in Automatic Mode is an I2C read. + 0x1 + + + + + + + SLVDAT + Combined Slave receiver and transmitter data register. + 0x844 + 32 + read-write + 0 + 0xFF + + + DATA + Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. + 0 + 8 + read-write + + + + + SLVADR0 + Slave address register. + 0x848 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + AUTONACK + Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. + 15 + 1 + read-write + + + NORMAL + Normal operation, matching I2C addresses are not ignored. + 0 + + + AUTOMATIC + Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. + 0x1 + + + + + + + SLVADR1 + Slave address register. + 0x84C + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + + + SLVADR2 + Slave address register. + 0x850 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + + + SLVADR3 + Slave address register. + 0x854 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + + + SLVQUAL0 + Slave Qualification for address 0. + 0x858 + 32 + read-write + 0 + 0xFF + + + QUALMODE0 + Qualify mode for slave address 0. + 0 + 1 + read-write + + + MASK + Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + 0 + + + EXTEND + Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + 0x1 + + + + + SLVQUAL0 + Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + 1 + 7 + read-write + + + + + MONRXDAT + Monitor receiver data register. + 0x880 + 32 + read-only + 0 + 0x7FF + + + MONRXDAT + Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + 0 + 8 + read-only + + + MONSTART + Monitor Received Start. + 8 + 1 + read-only + + + NO_START_DETECTED + No start detected. The Monitor function has not detected a Start event on the I2C bus. + 0 + + + START_DETECTED + Start detected. The Monitor function has detected a Start event on the I2C bus. + 0x1 + + + + + MONRESTART + Monitor Received Repeated Start. + 9 + 1 + read-only + + + NOT_DETECTED + No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + 0 + + + DETECTED + Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + 0x1 + + + + + MONNACK + Monitor Received NACK. + 10 + 1 + read-only + + + ACKNOWLEDGED + Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + 0 + + + NOT_ACKNOWLEDGED + Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + 0x1 + + + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + I2C1 + I2C-bus interfaces + FLEXCOMM1 + I2C + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + I2C2 + I2C-bus interfaces + FLEXCOMM2 + I2C + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + I2C3 + I2C-bus interfaces + FLEXCOMM3 + I2C + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + I2C4 + I2C-bus interfaces + FLEXCOMM4 + I2C + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + I2C5 + I2C-bus interfaces + FLEXCOMM5 + I2C + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + I2C6 + I2C-bus interfaces + FLEXCOMM6 + I2C + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + I2C7 + I2C-bus interfaces + FLEXCOMM7 + I2C + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + I2S0 + I2S interface + FLEXCOMM0 + I2S + I2S + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + 3 + 0x20 + SECCHANNEL[%s] + no description available + 0 + + PCFG1 + Configuration register 1 for channel pair + 0xC20 + 32 + read-write + 0 + 0x401 + + + PAIRENABLE + Enable for this channel pair. + 0 + 1 + read-write + + + DISABLE + This I2S channel pair is disabled. + 0 + + + ENABLE + This I2S channel pair is enabled. + 0x1 + + + + + ONECHANNEL + Single channel mode. + 10 + 1 + read-write + + + STEREO + I2S data for this channel pair is treated as left and right channels. + 0 + + + SINGLE + I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. + 0x1 + + + + + + + PCFG2 + Configuration register 2 for channel pair + 0xC24 + 32 + read-write + 0 + 0x1FF0000 + + + POSITION + Data Position. + 16 + 9 + read-write + + + + + PSTAT + Status register for channel pair + 0xC28 + 32 + read-write + 0 + 0xF + + + BUSY + Busy status for this channel pair. + 0 + 1 + read-write + + + IDLE + The transmitter/receiver for this channel pair is currently idle. + 0 + + + PROCESSING + The transmitter/receiver for this channel pair is currently processing data. + 0x1 + + + + + SLVFRMERR + Save Frame Error flag. + 1 + 1 + read-write + + + LR + Left/Right indication. + 2 + 1 + read-write + + + DATAPAUSED + Data Paused status flag. + 3 + 1 + read-only + + + PAUSE + Data is not currently paused. + 0 + + + FORCE + A data pause has been requested and is now in force. + 0x1 + + + + + + + + CFG1 + Configuration register 1 for the primary channel pair. + 0xC00 + 32 + read-write + 0 + 0x1F3FFF + + + MAINENABLE + Main enable for I 2S function in this Flexcomm + 0 + 1 + read-write + + + DISABLED + All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. + 0 + + + ENABLED + This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + 0x1 + + + + + DATAPAUSE + Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. + 1 + 1 + read-write + + + NORMAL + Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + 0 + + + PAUSE + A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + 0x1 + + + + + PAIRCOUNT + Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + 2 + 2 + read-write + + + PAIRS_1 + 1 I2S channel pairs in this flexcomm + 0 + + + PAIRS_2 + 2 I2S channel pairs in this flexcomm + 0x1 + + + PAIRS_3 + 3 I2S channel pairs in this flexcomm + 0x2 + + + PAIRS_4 + 4 I2S channel pairs in this flexcomm + 0x3 + + + + + MSTSLVCFG + Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + 4 + 2 + read-write + + + NORMAL_SLAVE_MODE + Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + 0 + + + WS_SYNC_MASTER + WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. + 0x1 + + + MASTER_USING_SCK + Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + 0x2 + + + NORMAL_MASTER + Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + 0x3 + + + + + MODE + Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. + 6 + 2 + read-write + + + CLASSIC_MODE + I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + 0 + + + DSP_MODE_WS_50_DUTYCYCLE + DSP mode where WS has a 50% duty cycle. See remark for mode 0. + 0x1 + + + DSP_MODE_WS_1_CLOCK + DSP mode where WS has a one clock long pulse at the beginning of each data frame. + 0x2 + + + DSP_MODE_WS_1_DATA + DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + 0x3 + + + + + RIGHTLOW + Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + 8 + 1 + read-write + + + RIGHT_HIGH + The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. + 0 + + + RIGHT_LOW + The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. + 0x1 + + + + + LEFTJUST + Left Justify data. + 9 + 1 + read-write + + + RIGHT_JUSTIFIED + Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. + 0 + + + LEFT_JUSTIFIED + Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. + 0x1 + + + + + ONECHANNEL + Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. + 10 + 1 + read-write + + + DUAL_CHANNEL + I2S data for this channel pair is treated as left and right channels. + 0 + + + SINGLE_CHANNEL + I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. + 0x1 + + + + + SCK_POL + SCK polarity. + 12 + 1 + read-write + + + FALLING_EDGE + Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + 0 + + + RISING_EDGE + Data is launched on SCK rising edges and sampled on SCK falling edges. + 0x1 + + + + + WS_POL + WS polarity. + 13 + 1 + read-write + + + NOT_INVERTED + Data frames begin at a falling edge of WS (standard for classic I2S). + 0 + + + INVERTED + WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + 0x1 + + + + + DATALEN + Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length + 16 + 5 + read-write + + + + + CFG2 + Configuration register 2 for the primary channel pair. + 0xC04 + 32 + read-write + 0 + 0x1FF01FF + + + FRAMELEN + Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x7FF = frame is 2048 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. + 0 + 11 + read-write + + + POSITION + Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + 16 + 9 + read-write + + + + + STAT + Status register for the primary channel pair. + 0xC08 + 32 + read-write + 0 + 0xD + + + BUSY + Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + 0 + 1 + read-only + + + IDLE + The transmitter/receiver for channel pair is currently idle. + 0 + + + BUSY + The transmitter/receiver for channel pair is currently processing data. + 0x1 + + + + + SLVFRMERR + Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. + 1 + 1 + write-only + + + NO_ERROR + No error has been recorded. + 0 + + + ERROR + An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + 0x1 + + + + + LR + Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. + 2 + 1 + read-only + + + LEFT_CHANNEL + Left channel. + 0 + + + RIGHT_CHANNEL + Right channel. + 0x1 + + + + + DATAPAUSED + Data Paused status flag. Applies to all I2S channels + 3 + 1 + read-only + + + NOT_PAUSED + Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + 0 + + + PAUSED + A data pause has been requested and is now in force. + 0x1 + + + + + + + DIV + Clock divider, used by all channel pairs. + 0xC1C + 32 + read-write + 0 + 0xFFF + + + DIV + This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. + 0 + 12 + read-write + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + TXI2SE0 + Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. + 2 + 1 + read-write + + + LAST_VALUE + If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. + 0 + + + ZERO + If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + 0x1 + + + + + PACK48 + Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + 3 + 1 + read-write + + + BIT_24 + 48-bit I2S FIFO entries are handled as all 24-bit values. + 0 + + + BIT_32_16 + 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. The number of bits used depends on configuration details. + 0 + 32 + write-only + + + + + FIFOWR48H + FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE24 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0 + + + RXDATA + Received data from the FIFO. The number of bits used depends on configuration details. + 0 + 32 + read-only + + + + + FIFORD48H + FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE34 + 32 + read-only + 0 + 0xFFFFFF + + + RXDATA + Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0 + + + RXDATA + Received data from the FIFO. + 0 + 32 + read-only + + + + + FIFORD48HNOPOP + FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE44 + 32 + read-only + 0 + 0xFFFFFF + + + RXDATA + Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + read-only + + + + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + + + ID + I2S Module identification + 0xFFC + 32 + read-only + 0xE0900000 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation, starting at 0. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation, starting at 0. + 12 + 4 + read-only + + + ID + Unique module identifier for this IP block. + 16 + 16 + read-only + + + + + + + I2S1 + I2S interface + FLEXCOMM1 + I2S + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + I2S2 + I2S interface + FLEXCOMM2 + I2S + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + I2S3 + I2S interface + FLEXCOMM3 + I2S + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + I2S4 + I2S interface + FLEXCOMM4 + I2S + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + I2S5 + I2S interface + FLEXCOMM5 + I2S + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + I2S6 + I2S interface + FLEXCOMM6 + I2S + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + I2S7 + I2S interface + FLEXCOMM7 + I2S + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + SPI0 + Serial Peripheral Interfaces (SPI) + FLEXCOMM0 + SPI + SPI + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + SPI Configuration register + 0x400 + 32 + read-write + 0 + 0xFBD + + + ENABLE + SPI enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The SPI is disabled and the internal state machine and counters are reset. + 0 + + + ENABLED + Enabled. The SPI is enabled for operation. + 0x1 + + + + + MASTER + Master mode select. + 2 + 1 + read-write + + + SLAVE_MODE + Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + 0 + + + MASTER_MODE + Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + 0x1 + + + + + LSBF + LSB First mode enable. + 3 + 1 + read-write + + + STANDARD + Standard. Data is transmitted and received in standard MSB first order. + 0 + + + REVERSE + Reverse. Data is transmitted and received in reverse order (LSB first). + 0x1 + + + + + CPHA + Clock Phase select. + 4 + 1 + read-write + + + CHANGE + Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. + 0 + + + CAPTURE + Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. + 0x1 + + + + + CPOL + Clock Polarity select. + 5 + 1 + read-write + + + LOW + Low. The rest state of the clock (between transfers) is low. + 0 + + + HIGH + High. The rest state of the clock (between transfers) is high. + 0x1 + + + + + LOOP + Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. + 7 + 1 + read-write + + + DISABLED + Disabled. + 0 + + + ENABLED + Enabled. + 0x1 + + + + + SPOL0 + SSEL0 Polarity select. + 8 + 1 + read-write + + + LOW + Low. The SSEL0 pin is active low. + 0 + + + HIGH + High. The SSEL0 pin is active high. + 0x1 + + + + + SPOL1 + SSEL1 Polarity select. + 9 + 1 + read-write + + + LOW + Low. The SSEL1 pin is active low. + 0 + + + HIGH + High. The SSEL1 pin is active high. + 0x1 + + + + + SPOL2 + SSEL2 Polarity select. + 10 + 1 + read-write + + + LOW + Low. The SSEL2 pin is active low. + 0 + + + HIGH + High. The SSEL2 pin is active high. + 0x1 + + + + + SPOL3 + SSEL3 Polarity select. + 11 + 1 + read-write + + + LOW + Low. The SSEL3 pin is active low. + 0 + + + HIGH + High. The SSEL3 pin is active high. + 0x1 + + + + + + + DLY + SPI Delay register + 0x404 + 32 + read-write + 0 + 0xFFFF + + + PRE_DELAY + Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 0 + 4 + read-write + + + POST_DELAY + Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 4 + 4 + read-write + + + FRAME_DELAY + If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 8 + 4 + read-write + + + TRANSFER_DELAY + Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. + 12 + 4 + read-write + + + + + STAT + SPI Status. Some status flags can be cleared by writing a 1 to that bit position. + 0x408 + 32 + read-write + 0x100 + 0x1C0 + + + SSA + Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. + 4 + 1 + write-only + + + SSD + Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. + 5 + 1 + write-only + + + STALLED + Stalled status flag. This indicates whether the SPI is currently in a stall condition. + 6 + 1 + read-only + + + ENDTRANSFER + End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + 7 + 1 + read-write + + + MSTIDLE + Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. + 8 + 1 + read-only + + + + + INTENSET + SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. + 0x40C + 32 + read-write + 0 + 0x130 + + + SSAEN + Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + 4 + 1 + read-write + + + DISABLED + Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + 0 + + + ENABLED + Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + 0x1 + + + + + SSDEN + Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + 5 + 1 + read-write + + + DISABLED + Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + 0 + + + ENABLED + Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + 0x1 + + + + + MSTIDLEEN + Master idle interrupt enable. + 8 + 1 + read-write + + + DISABLED + No interrupt will be generated when the SPI master function is idle. + 0 + + + ENABLED + An interrupt will be generated when the SPI master function is fully idle. + 0x1 + + + + + + + INTENCLR + SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. + 0x410 + 32 + write-only + 0 + 0 + + + SSAEN + Writing 1 clears the corresponding bit in the INTENSET register. + 4 + 1 + write-only + + + SSDEN + Writing 1 clears the corresponding bit in the INTENSET register. + 5 + 1 + write-only + + + MSTIDLE + Writing 1 clears the corresponding bit in the INTENSET register. + 8 + 1 + write-only + + + + + DIV + SPI clock Divider + 0x424 + 32 + read-write + 0 + 0xFFFF + + + DIVVAL + Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. + 0 + 16 + read-write + + + + + INTSTAT + SPI Interrupt Status + 0x428 + 32 + read-only + 0 + 0x130 + + + SSA + Slave Select Assert. + 4 + 1 + read-only + + + SSD + Slave Select Deassert. + 5 + 1 + read-only + + + MSTIDLE + Master Idle status flag. + 8 + 1 + read-only + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. + 0 + 16 + write-only + + + TXSSEL0_N + Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + 16 + 1 + write-only + + + ASSERTED + SSEL0 asserted. + 0 + + + NOT_ASSERTED + SSEL0 not asserted. + 0x1 + + + + + TXSSEL1_N + Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + 17 + 1 + write-only + + + ASSERTED + SSEL1 asserted. + 0 + + + NOT_ASSERTED + SSEL1 not asserted. + 0x1 + + + + + TXSSEL2_N + Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + 18 + 1 + write-only + + + ASSERTED + SSEL2 asserted. + 0 + + + NOT_ASSERTED + SSEL2 not asserted. + 0x1 + + + + + TXSSEL3_N + Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + 19 + 1 + write-only + + + ASSERTED + SSEL3 asserted. + 0 + + + NOT_ASSERTED + SSEL3 not asserted. + 0x1 + + + + + EOT + End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. + 20 + 1 + write-only + + + NOT_DEASSERTED + SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + 0 + + + DEASSERTED + SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + 0x1 + + + + + EOF + End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. + 21 + 1 + write-only + + + NOT_EOF + Data not EOF. This piece of data transmitted is not treated as the end of a frame. + 0 + + + EOF + Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. + 0x1 + + + + + RXIGNORE + Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. + 22 + 1 + write-only + + + READ + Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. + 0 + + + IGNORE + Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. + 0x1 + + + + + TXIGNORE + Transmit Ignore. This allows data to be received using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA.This bit can only be set by writing to the upper 16 bits only of FIFOWR, i.e., a half-word write to offset 0xE22. + 23 + 1 + write-only + + + WRITE + Write transmit data. Transmit data must be written for each data exchange between master and slave. In slave mode, an underrun error occurs if transmit data is not provided before needed in a data frame. + 0 + + + IGNORE + Ignore transmit data. Data can be received without transmitting data (after FIFOWR has been initialized to set TXIGNORE). No transmitter flags are generated. When configured with TXIGNORE =1, the slave will set the data to always 0. + 0x1 + + + + + LEN + Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. + 24 + 4 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. + 0 + 16 + read-only + + + RXSSEL0_N + Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 16 + 1 + read-only + + + RXSSEL1_N + Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 17 + 1 + read-only + + + RXSSEL2_N + Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 18 + 1 + read-only + + + RXSSEL3_N + Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 19 + 1 + read-only + + + SOT + Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. + 20 + 1 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. + 0 + 16 + read-only + + + RXSSEL0_N + Slave Select for receive. + 16 + 1 + read-only + + + RXSSEL1_N + Slave Select for receive. + 17 + 1 + read-only + + + RXSSEL2_N + Slave Select for receive. + 18 + 1 + read-only + + + RXSSEL3_N + Slave Select for receive. + 19 + 1 + read-only + + + SOT + Start of transfer flag. + 20 + 1 + read-only + + + + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0xE0201200 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + SPI1 + Serial Peripheral Interfaces (SPI) + FLEXCOMM1 + SPI + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + SPI2 + Serial Peripheral Interfaces (SPI) + FLEXCOMM2 + SPI + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + SPI3 + Serial Peripheral Interfaces (SPI) + FLEXCOMM3 + SPI + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + SPI4 + Serial Peripheral Interfaces (SPI) + FLEXCOMM4 + SPI + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + SPI5 + Serial Peripheral Interfaces (SPI) + FLEXCOMM5 + SPI + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + SPI6 + Serial Peripheral Interfaces (SPI) + FLEXCOMM6 + SPI + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + SPI7 + Serial Peripheral Interfaces (SPI) + FLEXCOMM7 + SPI + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + SPI8 + Serial Peripheral Interfaces (SPI) + FLEXCOMM8 + SPI + 0x4009F000 + + 0 + 0x1000 + registers + + + FLEXCOMM8 + 59 + + + + USART0 + USARTs + FLEXCOMM0 + USART + USART + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + USART Configuration register. Basic USART configuration settings that typically are not changed during operation. + 0 + 32 + read-write + 0 + 0xFDDBFD + + + ENABLE + USART Enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. + 0 + + + ENABLED + Enabled. The USART is enabled for operation. + 0x1 + + + + + DATALEN + Selects the data size for the USART. + 2 + 2 + read-write + + + BIT_7 + 7 bit Data length. + 0 + + + BIT_8 + 8 bit Data length. + 0x1 + + + BIT_9 + 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + 0x2 + + + + + PARITYSEL + Selects what type of parity is used by the USART. + 4 + 2 + read-write + + + NO_PARITY + No parity. + 0 + + + EVEN_PARITY + Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. + 0x2 + + + ODD_PARITY + Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. + 0x3 + + + + + STOPLEN + Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + 6 + 1 + read-write + + + BIT_1 + 1 stop bit. + 0 + + + BITS_2 + 2 stop bits. This setting should only be used for asynchronous communication. + 0x1 + + + + + MODE32K + Selects standard or 32 kHz clocking mode. + 7 + 1 + read-write + + + DISABLED + Disabled. USART uses standard clocking. + 0 + + + ENABLED + Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + 0x1 + + + + + LINMODE + LIN break mode enable. + 8 + 1 + read-write + + + DISABLED + Disabled. Break detect and generate is configured for normal operation. + 0 + + + ENABLED + Enabled. Break detect and generate is configured for LIN bus operation. + 0x1 + + + + + CTSEN + CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. + 9 + 1 + read-write + + + DISABLED + No flow control. The transmitter does not receive any automatic flow control signal. + 0 + + + ENABLED + Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + 0x1 + + + + + SYNCEN + Selects synchronous or asynchronous operation. + 11 + 1 + read-write + + + ASYNCHRONOUS_MODE + Asynchronous mode. + 0 + + + SYNCHRONOUS_MODE + Synchronous mode. + 0x1 + + + + + CLKPOL + Selects the clock polarity and sampling edge of received data in synchronous mode. + 12 + 1 + read-write + + + FALLING_EDGE + Falling edge. Un_RXD is sampled on the falling edge of SCLK. + 0 + + + RISING_EDGE + Rising edge. Un_RXD is sampled on the rising edge of SCLK. + 0x1 + + + + + SYNCMST + Synchronous mode Master select. + 14 + 1 + read-write + + + SLAVE + Slave. When synchronous mode is enabled, the USART is a slave. + 0 + + + MASTER + Master. When synchronous mode is enabled, the USART is a master. + 0x1 + + + + + LOOP + Selects data loopback mode. + 15 + 1 + read-write + + + NORMAL + Normal operation. + 0 + + + LOOPBACK + Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + 0x1 + + + + + OETA + Output Enable Turnaround time enable for RS-485 operation. + 18 + 1 + read-write + + + DISABLED + Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + 0 + + + ENABLED + Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. + 0x1 + + + + + AUTOADDR + Automatic Address matching enable. + 19 + 1 + read-write + + + DISABLED + Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). + 0 + + + ENABLED + Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. + 0x1 + + + + + OESEL + Output Enable Select. + 20 + 1 + read-write + + + STANDARD + Standard. The RTS signal is used as the standard flow control function. + 0 + + + RS_485 + RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + 0x1 + + + + + OEPOL + Output Enable Polarity. + 21 + 1 + read-write + + + LOW + Low. If selected by OESEL, the output enable is active low. + 0 + + + HIGH + High. If selected by OESEL, the output enable is active high. + 0x1 + + + + + RXPOL + Receive data polarity. + 22 + 1 + read-write + + + STANDARD + Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + 0 + + + INVERTED + Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + 0x1 + + + + + TXPOL + Transmit data polarity. + 23 + 1 + read-write + + + STANDARD + Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + 0 + + + INVERTED + Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + 0x1 + + + + + + + CTL + USART Control register. USART control settings that are more likely to change during operation. + 0x4 + 32 + read-write + 0 + 0x10346 + + + TXBRKEN + Break Enable. + 1 + 1 + read-write + + + NORMAL + Normal operation. + 0 + + + CONTINOUS + Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + 0x1 + + + + + ADDRDET + Enable address detect mode. + 2 + 1 + read-write + + + DISABLED + Disabled. The USART presents all incoming data. + 0 + + + ENABLED + Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. + 0x1 + + + + + TXDIS + Transmit Disable. + 6 + 1 + read-write + + + ENABLED + Not disabled. USART transmitter is not disabled. + 0 + + + DISABLED + Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. + 0x1 + + + + + CC + Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + 8 + 1 + read-write + + + CLOCK_ON_CHARACTER + Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. + 0 + + + CONTINOUS_CLOCK + Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). + 0x1 + + + + + CLRCCONRX + Clear Continuous Clock. + 9 + 1 + read-write + + + NO_EFFECT + No effect. No effect on the CC bit. + 0 + + + AUTO_CLEAR + Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + 0x1 + + + + + AUTOBAUD + Autobaud enable. + 16 + 1 + read-write + + + DISABLED + Disabled. USART is in normal operating mode. + 0 + + + ENABLED + Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. + 0x1 + + + + + + + STAT + USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. + 0x8 + 32 + read-write + 0xA + 0x45A + + + RXIDLE + Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. + 1 + 1 + read-only + + + TXIDLE + Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. + 3 + 1 + read-only + + + CTS + This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. + 4 + 1 + read-only + + + DELTACTS + This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + 5 + 1 + write-only + + + TXDISSTAT + Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + 6 + 1 + read-only + + + RXBRK + Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. + 10 + 1 + read-only + + + DELTARXBRK + This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + 11 + 1 + write-only + + + START + This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. + 12 + 1 + write-only + + + FRAMERRINT + Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + write-only + + + PARITYERRINT + Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + 14 + 1 + write-only + + + RXNOISEINT + Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. + 15 + 1 + write-only + + + ABERR + Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. + 16 + 1 + write-only + + + + + INTENSET + Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. + 0xC + 32 + read-write + 0 + 0x1F868 + + + TXIDLEEN + When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + 3 + 1 + read-write + + + DELTACTSEN + When 1, enables an interrupt when there is a change in the state of the CTS input. + 5 + 1 + read-write + + + TXDISEN + When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + 6 + 1 + read-write + + + DELTARXBRKEN + When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). + 11 + 1 + read-write + + + STARTEN + When 1, enables an interrupt when a received start bit has been detected. + 12 + 1 + read-write + + + FRAMERREN + When 1, enables an interrupt when a framing error has been detected. + 13 + 1 + read-write + + + PARITYERREN + When 1, enables an interrupt when a parity error has been detected. + 14 + 1 + read-write + + + RXNOISEEN + When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + 15 + 1 + read-write + + + ABERREN + When 1, enables an interrupt when an auto baud error occurs. + 16 + 1 + read-write + + + + + INTENCLR + Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. + 0x10 + 32 + write-only + 0 + 0 + + + TXIDLECLR + Writing 1 clears the corresponding bit in the INTENSET register. + 3 + 1 + write-only + + + DELTACTSCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 5 + 1 + write-only + + + TXDISCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 6 + 1 + write-only + + + DELTARXBRKCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 11 + 1 + write-only + + + STARTCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 12 + 1 + write-only + + + FRAMERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 13 + 1 + write-only + + + PARITYERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 14 + 1 + write-only + + + RXNOISECLR + Writing 1 clears the corresponding bit in the INTENSET register. + 15 + 1 + write-only + + + ABERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 16 + 1 + write-only + + + + + BRG + Baud Rate Generator register. 16-bit integer baud rate divisor value. + 0x20 + 32 + read-write + 0 + 0xFFFF + + + BRGVAL + This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + 0 + 16 + read-write + + + + + INTSTAT + Interrupt status register. Reflects interrupts that are currently enabled. + 0x24 + 32 + read-only + 0 + 0x1F968 + + + TXIDLE + Transmitter Idle status. + 3 + 1 + read-only + + + DELTACTS + This bit is set when a change in the state of the CTS input is detected. + 5 + 1 + read-only + + + TXDISINT + Transmitter Disabled Interrupt flag. + 6 + 1 + read-only + + + DELTARXBRK + This bit is set when a change in the state of receiver break detection occurs. + 11 + 1 + read-only + + + START + This bit is set when a start is detected on the receiver input. + 12 + 1 + read-only + + + FRAMERRINT + Framing Error interrupt flag. + 13 + 1 + read-only + + + PARITYERRINT + Parity Error interrupt flag. + 14 + 1 + read-only + + + RXNOISEINT + Received Noise interrupt flag. + 15 + 1 + read-only + + + ABERRINT + Auto baud Error Interrupt flag. + 16 + 1 + read-only + + + + + OSR + Oversample selection register for asynchronous communication. + 0x28 + 32 + read-write + 0xF + 0xF + + + OSRVAL + Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + 0 + 4 + read-write + + + + + ADDR + Address register for automatic address matching. + 0x2C + 32 + read-write + 0 + 0xFF + + + ADDRESS + 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + 0 + 8 + read-write + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. + 0 + 9 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + 0 + 9 + read-only + + + FRAMERR + Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + read-only + + + PARITYERR + Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. + 14 + 1 + read-only + + + RXNOISE + Received Noise flag. See description of the RxNoiseInt bit in Table 354. + 15 + 1 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + 0 + 9 + read-only + + + FRAMERR + Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + read-only + + + PARITYERR + Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. + 14 + 1 + read-only + + + RXNOISE + Received Noise flag. See description of the RxNoiseInt bit in Table 354. + 15 + 1 + read-only + + + + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + USART1 + USARTs + FLEXCOMM1 + USART + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + USART2 + USARTs + FLEXCOMM2 + USART + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + USART3 + USARTs + FLEXCOMM3 + USART + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + USART4 + USARTs + FLEXCOMM4 + USART + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + USART5 + USARTs + FLEXCOMM5 + USART + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + USART6 + USARTs + FLEXCOMM6 + USART + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + USART7 + USARTs + FLEXCOMM7 + USART + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + GPIO + General Purpose I/O (GPIO) + GPIO + 0x4008C000 + + 0 + 0x2488 + registers + + + + 2 + 0x20 + B[%s] + no description available + 0 + + 32 + 0x1 + B_[%s] + Byte pin registers for all port GPIO pins + 0 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + + 2 + 0x80 + W[%s] + no description available + 0x1000 + + 32 + 0x4 + W_[%s] + Word pin registers for all port GPIO pins + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + + 2 + 0x4 + DIR[%s] + Direction registers for all port GPIO pins + 0x2000 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIRP + Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. + 0 + 32 + read-write + + + + + 2 + 0x4 + MASK[%s] + Mask register for all port GPIO pins + 0x2080 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASKP + Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. + 0 + 32 + read-write + + + + + 2 + 0x4 + PIN[%s] + Port pin register for all port GPIO pins + 0x2100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PORT + Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. + 0 + 32 + read-write + + + + + 2 + 0x4 + MPIN[%s] + Masked port register for all port GPIO pins + 0x2180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MPORTP + Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. + 0 + 32 + read-write + + + + + 2 + 0x4 + SET[%s] + Write: Set register for port. Read: output bits for port + 0x2200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETP + Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. + 0 + 32 + read-write + + + + + 2 + 0x4 + CLR[%s] + Clear port for all port GPIO pins + 0x2280 + 32 + write-only + 0 + 0 + + + CLRP + Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. + 0 + 32 + write-only + + + + + 2 + 0x4 + NOT[%s] + Toggle port for all port GPIO pins + 0x2300 + 32 + write-only + 0 + 0 + + + NOTP + Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. + 0 + 32 + write-only + + + + + 2 + 0x4 + DIRSET[%s] + Set pin direction bits for port + 0x2380 + 32 + write-only + 0 + 0 + + + DIRSETP + Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. + 0 + 32 + write-only + + + + + 2 + 0x4 + DIRCLR[%s] + Clear pin direction bits for port + 0x2400 + 32 + write-only + 0 + 0 + + + DIRCLRP + Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. + 0 + 32 + write-only + + + + + 2 + 0x4 + DIRNOT[%s] + Toggle pin direction bits for port + 0x2480 + 32 + write-only + 0 + 0 + + + DIRNOTP + Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + 0 + 32 + write-only + + + + + + + USBHSD + USB1 High-speed Device Controller + USBHSD + 0x40094000 + + 0 + 0x38 + registers + + + USB1 + 47 + + + USB1_NEEDCLK + 48 + + + + DEVCMDSTAT + USB Device Command/Status register + 0 + 32 + read-write + 0x800 + 0xF7DBFFFF + + + DEV_ADDR + USB device address. + 0 + 7 + read-write + + + DEV_EN + USB device enable. + 7 + 1 + read-write + + + SETUP + SETUP token received. + 8 + 1 + read-write + + + FORCE_NEEDCLK + Forces the NEEDCLK output to always be on:. + 9 + 1 + read-write + + + LPM_SUP + LPM Supported:. + 11 + 1 + read-write + + + INTONNAK_AO + Interrupt on NAK for interrupt and bulk OUT EP:. + 12 + 1 + read-write + + + INTONNAK_AI + Interrupt on NAK for interrupt and bulk IN EP:. + 13 + 1 + read-write + + + INTONNAK_CO + Interrupt on NAK for control OUT EP:. + 14 + 1 + read-write + + + INTONNAK_CI + Interrupt on NAK for control IN EP:. + 15 + 1 + read-write + + + DCON + Device status - connect. + 16 + 1 + read-write + + + DSUS + Device status - suspend. + 17 + 1 + read-write + + + LPM_SUS + Device status - LPM Suspend. + 19 + 1 + read-write + + + LPM_REWP + LPM Remote Wake-up Enabled by USB host. + 20 + 1 + read-only + + + Speed + This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). + 22 + 2 + read-only + + + DCON_C + Device status - connect change. + 24 + 1 + read-write + + + DSUS_C + Device status - suspend change. + 25 + 1 + read-write + + + DRES_C + Device status - reset change. + 26 + 1 + read-write + + + VBUS_DEBOUNCED + This bit indicates if VBUS is detected or not. + 28 + 1 + read-only + + + PHY_TEST_MODE + This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. + 29 + 3 + read-write + + + DISABLE + Test mode disabled. + 0 + + + TEST_J + Test_J. + 0x1 + + + TEST_K + Test_K. + 0x2 + + + TEST_SE0_NAK + Test_SE0_NAK. + 0x3 + + + TEST_PACKET + Test_Packet. + 0x4 + + + TEST_FORCE_ENABLE + Test_Force_Enable. + 0x5 + + + + + + + INFO + USB Info register + 0x4 + 32 + read-only + 0x2000000 + 0xFFFF7FFF + + + FRAME_NR + Frame number. + 0 + 11 + read-only + + + ERR_CODE + The error code which last occurred:. + 11 + 4 + read-only + + + MINREV + Minor revision. + 16 + 8 + read-only + + + MAJREV + Major revision. + 24 + 8 + read-only + + + + + EPLISTSTART + USB EP Command/Status List start address + 0x8 + 32 + read-write + 0 + 0xFFFFFF00 + + + EP_LIST_PRG + Programmable portion of the USB EP Command/Status List address. + 8 + 12 + read-write + + + EP_LIST_FIXED + Fixed portion of USB EP Command/Status List address. + 20 + 12 + read-only + + + + + DATABUFSTART + USB Data buffer start address + 0xC + 32 + read-write + 0x41000000 + 0xFFFFFFFF + + + DA_BUF + Start address of the memory page where all endpoint data buffers are located. + 0 + 32 + read-write + + + + + LPM + USB Link Power Management register + 0x10 + 32 + read-write + 0 + 0x1FF + + + HIRD_HW + Host Initiated Resume Duration - HW. + 0 + 4 + read-only + + + HIRD_SW + Host Initiated Resume Duration - SW. + 4 + 4 + read-write + + + DATA_PENDING + As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. + 8 + 1 + read-write + + + + + EPSKIP + USB Endpoint skip + 0x14 + 32 + read-write + 0 + 0xFFF + + + SKIP + Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. + 0 + 12 + read-write + + + + + EPINUSE + USB Endpoint Buffer in use + 0x18 + 32 + read-write + 0 + 0xFFC + + + BUF + Buffer in use: This register has one bit per physical endpoint. + 2 + 10 + read-write + + + + + EPBUFCFG + USB Endpoint Buffer Configuration register + 0x1C + 32 + read-write + 0 + 0xFFC + + + BUF_SB + Buffer usage: This register has one bit per physical endpoint. + 2 + 10 + read-write + + + + + INTSTAT + USB interrupt status register + 0x20 + 32 + read-write + 0 + 0xC0000FFF + + + EP0OUT + Interrupt status register bit for the Control EP0 OUT direction. + 0 + 1 + read-write + + + EP0IN + Interrupt status register bit for the Control EP0 IN direction. + 1 + 1 + read-write + + + EP1OUT + Interrupt status register bit for the EP1 OUT direction. + 2 + 1 + read-write + + + EP1IN + Interrupt status register bit for the EP1 IN direction. + 3 + 1 + read-write + + + EP2OUT + Interrupt status register bit for the EP2 OUT direction. + 4 + 1 + read-write + + + EP2IN + Interrupt status register bit for the EP2 IN direction. + 5 + 1 + read-write + + + EP3OUT + Interrupt status register bit for the EP3 OUT direction. + 6 + 1 + read-write + + + EP3IN + Interrupt status register bit for the EP3 IN direction. + 7 + 1 + read-write + + + EP4OUT + Interrupt status register bit for the EP4 OUT direction. + 8 + 1 + read-write + + + EP4IN + Interrupt status register bit for the EP4 IN direction. + 9 + 1 + read-write + + + EP5OUT + Interrupt status register bit for the EP5 OUT direction. + 10 + 1 + read-write + + + EP5IN + Interrupt status register bit for the EP5 IN direction. + 11 + 1 + read-write + + + FRAME_INT + Frame interrupt. + 30 + 1 + read-write + + + DEV_INT + Device status interrupt. + 31 + 1 + read-write + + + + + INTEN + USB interrupt enable register + 0x24 + 32 + read-write + 0 + 0xC0000FFF + + + EP_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 0 + 12 + read-write + + + FRAME_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 30 + 1 + read-write + + + DEV_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 31 + 1 + read-write + + + + + INTSETSTAT + USB set interrupt status register + 0x28 + 32 + read-write + 0 + 0xC0000FFF + + + EP_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 0 + 12 + read-write + + + FRAME_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 30 + 1 + read-write + + + DEV_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 31 + 1 + read-write + + + + + EPTOGGLE + USB Endpoint toggle register + 0x34 + 32 + read-only + 0 + 0x3FFFFFFF + + + TOGGLE + Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + 0 + 30 + read-only + + + + + + + CRC_ENGINE + CRC engine + CRC + 0x40095000 + + 0 + 0xC + registers + + + + MODE + CRC mode register + 0 + 32 + read-write + 0 + 0x3F + + + CRC_POLY + CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + 0 + 2 + read-write + + + BIT_RVS_WR + Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + 2 + 1 + read-write + + + CMPL_WR + Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + 3 + 1 + read-write + + + BIT_RVS_SUM + CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + 4 + 1 + read-write + + + CMPL_SUM + CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + 5 + 1 + read-write + + + + + SEED + CRC seed register + 0x4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + CRC_SEED + A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. + 0 + 32 + read-write + + + + + SUM + CRC checksum register + SUM_WR_DATA + 0x8 + 32 + read-only + 0xFFFF + 0xFFFFFFFF + + + CRC_SUM + The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + 0 + 32 + read-only + + + + + WR_DATA + CRC data register + SUM_WR_DATA + 0x8 + 32 + write-only + 0 + 0 + + + CRC_WR_DATA + Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. + 0 + 32 + write-only + + + + + + + DBGMAILBOX + MCU Debugger Mailbox + DBGMAILBOX + 0x4009C000 + + 0 + 0x100 + registers + + + + CSW + CRC mode register + 0 + 32 + read-write + 0 + 0x3F + + + RESYNCH_REQ + Debugger will set this bit to 1 to request a resynchronrisation + 0 + 1 + read-write + + + REQ_PENDING + Request is pending from debugger (i.e unread value in REQUEST) + 1 + 1 + read-write + + + DBG_OR_ERR + Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + 2 + 1 + read-write + + + AHB_OR_ERR + AHB overrun Error (Return value overwritten by ROM) + 3 + 1 + read-write + + + SOFT_RESET + Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM. + 4 + 1 + read-write + + + CHIP_RESET_REQ + Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + 5 + 1 + write-only + + + + + REQUEST + CRC seed register + 0x4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + REQ + Request Value + 0 + 32 + read-write + + + + + RETURN + Return value from ROM. + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RET + The Return value from ROM. + 0 + 32 + read-write + + + + + ID + Identification register + 0xFC + 32 + read-only + 0x2A0000 + 0xFFFFFFFF + + + ID + Identification value. + 0 + 32 + read-only + + + + + + + CAN0 + Controller Area Network Flexible Data (CAN FD) + CAN + 0x4009D000 + + 0 + 0x604 + registers + + + CAN0_IRQ0 + 43 + + + CAN0_IRQ1 + 44 + + + + DBTP + Data Bit Timing Prescaler Register + 0xC + 32 + read-write + 0xA33 + 0x9F1FFF + + + DSJW + Data (re)synchronization jump width. + 0 + 4 + read-write + + + DTSEG2 + Data time segment after sample point. + 4 + 4 + read-write + + + DTSEG1 + Data time segment before sample point. + 8 + 5 + read-write + + + DBRP + Data bit rate prescaler. + 16 + 5 + read-write + + + TDC + Transmitter delay compensation. + 23 + 1 + read-write + + + + + TEST + Test Register + 0x10 + 32 + read-write + 0 + 0xF0 + + + LBCK + Loop back mode. + 4 + 1 + read-write + + + TX + Control of transmit pin. + 5 + 2 + read-write + + + RX + Monitors the actual value of the CAN_RXD. + 7 + 1 + read-write + + + + + CCCR + CC Control Register + 0x18 + 32 + read-write + 0x1 + 0xF3FF + + + INIT + Initialization. + 0 + 1 + read-write + + + CCE + Configuration change enable. + 1 + 1 + read-write + + + ASM + Restricted operational mode. + 2 + 1 + read-write + + + CSA + Clock Stop Acknowledge. + 3 + 1 + read-write + + + CSR + Clock Stop Request. + 4 + 1 + read-write + + + MON + Bus monitoring mode. + 5 + 1 + read-write + + + DAR + Disable automatic retransmission. + 6 + 1 + read-write + + + TEST + Test mode enable. + 7 + 1 + read-write + + + FDOE + CAN FD operation enable. + 8 + 1 + read-write + + + BRSE + When CAN FD operation is disabled, this bit is not evaluated. + 9 + 1 + read-write + + + PXHD + Protocol exception handling disable. + 12 + 1 + read-write + + + EFBI + Edge filtering during bus integration. + 13 + 1 + read-write + + + TXP + Transmit pause. + 14 + 1 + read-write + + + NISO + Non ISO operation. + 15 + 1 + read-write + + + + + NBTP + Nominal Bit Timing and Prescaler Register + 0x1C + 32 + read-write + 0x6000A03 + 0xFFFFFF7F + + + NTSEG2 + Nominal time segment after sample point. + 0 + 7 + read-write + + + NTSEG1 + Nominal time segment before sample point. + 8 + 8 + read-write + + + NBRP + Nominal bit rate prescaler. + 16 + 9 + read-write + + + NSJW + Nominal (re)synchronization jump width. + 25 + 7 + read-write + + + + + TSCC + Timestamp Counter Configuration + 0x20 + 32 + read-write + 0 + 0xF0003 + + + TSS + Timestamp select. + 0 + 2 + read-write + + + TCP + Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. + 16 + 4 + read-write + + + + + TSCV + Timestamp Counter Value + 0x24 + 32 + read-write + 0 + 0xFFFF + + + TSC + Timestamp counter. + 0 + 16 + read-only + + + + + TOCC + Timeout Counter Configuration + 0x28 + 32 + read-write + 0xFFFF0000 + 0xFFFF0007 + + + ETOC + Enable timeout counter. + 0 + 1 + read-write + + + TOS + Timeout select. + 1 + 2 + read-write + + + TOP + Timeout period. + 16 + 16 + read-write + + + + + TOCV + Timeout Counter Value + 0x2C + 32 + read-only + 0xFFFF + 0xFFFF + + + TOC + Timeout counter. + 0 + 16 + read-only + + + + + ECR + Error Counter Register + 0x40 + 32 + read-only + 0 + 0xFFFFFF + + + TEC + Transmit error counter. + 0 + 8 + read-only + + + REC + Receive error counter. + 8 + 7 + read-only + + + RP + Receive error passive. + 15 + 1 + read-only + + + CEL + CAN error logging. + 16 + 8 + read-only + + + + + PSR + Protocol Status Register + 0x44 + 32 + read-only + 0x707 + 0x7F7FFF + + + LEC + Last error code. + 0 + 3 + read-only + + + ACT + Activity. + 3 + 2 + read-only + + + EP + Error Passive. + 5 + 1 + read-only + + + EW + Warning status. + 6 + 1 + read-only + + + BO + Bus Off Status. + 7 + 1 + read-only + + + DLEC + Data phase last error code. + 8 + 3 + read-only + + + RESI + ESI flag of the last received CAN FD message. + 11 + 1 + read-only + + + RBRS + BRS flag of last received CAN FD message. + 12 + 1 + read-only + + + RFDF + Received a CAN FD message. + 13 + 1 + read-only + + + PXE + Protocol exception event. + 14 + 1 + read-only + + + TDCV + Transmitter delay compensation value. + 16 + 7 + read-only + + + + + TDCR + Transmitter Delay Compensator Register + 0x48 + 32 + read-write + 0 + 0x7F7F + + + TDCF + Transmitter delay compensation filter window length. + 0 + 7 + read-write + + + TDCO + Transmitter delay compensation offset. + 8 + 7 + read-write + + + + + IR + Interrupt Register + 0x50 + 32 + read-write + 0 + 0x3FFFFFFF + + + RF0N + Rx FIFO 0 new message. + 0 + 1 + read-write + + + RF0W + Rx FIFO 0 watermark reached. + 1 + 1 + read-write + + + RF0F + Rx FIFO 0 full. + 2 + 1 + read-write + + + RF0L + Rx FIFO 0 message lost. + 3 + 1 + read-write + + + RF1N + Rx FIFO 1 new message. + 4 + 1 + read-write + + + RF1W + Rx FIFO 1 watermark reached. + 5 + 1 + read-write + + + RF1F + Rx FIFO 1 full. + 6 + 1 + read-write + + + RF1L + Rx FIFO 1 message lost. + 7 + 1 + read-write + + + HPM + High priority message. + 8 + 1 + read-write + + + TC + Transmission completed. + 9 + 1 + read-write + + + TCF + Transmission cancellation finished. + 10 + 1 + read-write + + + TFE + Tx FIFO empty. + 11 + 1 + read-write + + + TEFN + Tx event FIFO new entry. + 12 + 1 + read-write + + + TEFW + Tx event FIFO watermark reached. + 13 + 1 + read-write + + + TEFF + Tx event FIFO full. + 14 + 1 + read-write + + + TEFL + Tx event FIFO element lost. + 15 + 1 + read-write + + + TSW + Timestamp wraparound. + 16 + 1 + read-write + + + MRAF + Message RAM access failure. + 17 + 1 + read-write + + + TOO + Timeout occurred. + 18 + 1 + read-write + + + DRX + Message stored in dedicated Rx buffer. + 19 + 1 + read-write + + + BEC + Bit error corrected. + 20 + 1 + read-write + + + BEU + Bit error uncorrected. + 21 + 1 + read-write + + + ELO + Error logging overflow. + 22 + 1 + read-write + + + EP + Error passive. + 23 + 1 + read-write + + + EW + Warning status. + 24 + 1 + read-write + + + BO + Bus_Off Status. + 25 + 1 + read-write + + + WDI + Watchdog interrupt. + 26 + 1 + read-write + + + PEA + Protocol error in arbitration phase. + 27 + 1 + read-write + + + PED + Protocol error in data phase. + 28 + 1 + read-write + + + ARA + Access to reserved address. + 29 + 1 + read-write + + + + + IE + Interrupt Enable + 0x54 + 32 + read-write + 0 + 0x3FFFFFFF + + + RF0NE + Rx FIFO 0 new message interrupt enable. + 0 + 1 + read-write + + + RF0WE + Rx FIFO 0 watermark reached interrupt enable. + 1 + 1 + read-write + + + RF0FE + Rx FIFO 0 full interrupt enable. + 2 + 1 + read-write + + + RF0LE + Rx FIFO 0 message lost interrupt enable. + 3 + 1 + read-write + + + RF1NE + Rx FIFO 1 new message interrupt enable. + 4 + 1 + read-write + + + RF1WE + Rx FIFO 1 watermark reached interrupt enable. + 5 + 1 + read-write + + + RF1FE + Rx FIFO 1 full interrupt enable. + 6 + 1 + read-write + + + RF1LE + Rx FIFO 1 message lost interrupt enable. + 7 + 1 + read-write + + + HPME + High priority message interrupt enable. + 8 + 1 + read-write + + + TCE + Transmission completed interrupt enable. + 9 + 1 + read-write + + + TCFE + Transmission cancellation finished interrupt enable. + 10 + 1 + read-write + + + TFEE + Tx FIFO empty interrupt enable. + 11 + 1 + read-write + + + TEFNE + Tx event FIFO new entry interrupt enable. + 12 + 1 + read-write + + + TEFWE + Tx event FIFO watermark reached interrupt enable. + 13 + 1 + read-write + + + TEFFE + Tx event FIFO full interrupt enable. + 14 + 1 + read-write + + + TEFLE + Tx event FIFO element lost interrupt enable. + 15 + 1 + read-write + + + TSWE + Timestamp wraparound interrupt enable. + 16 + 1 + read-write + + + MRAFE + Message RAM access failure interrupt enable. + 17 + 1 + read-write + + + TOOE + Timeout occurred interrupt enable. + 18 + 1 + read-write + + + DRXE + Message stored in dedicated Rx buffer interrupt enable. + 19 + 1 + read-write + + + BECE + Bit error corrected interrupt enable. + 20 + 1 + read-write + + + BEUE + Bit error uncorrected interrupt enable. + 21 + 1 + read-write + + + ELOE + Error logging overflow interrupt enable. + 22 + 1 + read-write + + + EPE + Error passive interrupt enable. + 23 + 1 + read-write + + + EWE + Warning status interrupt enable. + 24 + 1 + read-write + + + BOE + Bus_Off Status interrupt enable. + 25 + 1 + read-write + + + WDIE + Watchdog interrupt enable. + 26 + 1 + read-write + + + PEAE + Protocol error in arbitration phase interrupt enable. + 27 + 1 + read-write + + + PEDE + Protocol error in data phase interrupt enable. + 28 + 1 + read-write + + + ARAE + Access to reserved address interrupt enable. + 29 + 1 + read-write + + + + + ILS + Interrupt Line Select + 0x58 + 32 + read-write + 0 + 0x3FFFFFFF + + + RF0NL + Rx FIFO 0 new message interrupt line. + 0 + 1 + read-write + + + RF0WL + Rx FIFO 0 watermark reached interrupt line. + 1 + 1 + read-write + + + RF0FL + Rx FIFO 0 full interrupt line. + 2 + 1 + read-write + + + RF0LL + Rx FIFO 0 message lost interrupt line. + 3 + 1 + read-write + + + RF1NL + Rx FIFO 1 new message interrupt line. + 4 + 1 + read-write + + + RF1WL + Rx FIFO 1 watermark reached interrupt line. + 5 + 1 + read-write + + + RF1FL + Rx FIFO 1 full interrupt line. + 6 + 1 + read-write + + + RF1LL + Rx FIFO 1 message lost interrupt line. + 7 + 1 + read-write + + + HPML + High priority message interrupt line. + 8 + 1 + read-write + + + TCL + Transmission completed interrupt line. + 9 + 1 + read-write + + + TCFL + Transmission cancellation finished interrupt line. + 10 + 1 + read-write + + + TFEL + Tx FIFO empty interrupt line. + 11 + 1 + read-write + + + TEFNL + Tx event FIFO new entry interrupt line. + 12 + 1 + read-write + + + TEFWL + Tx event FIFO watermark reached interrupt line. + 13 + 1 + read-write + + + TEFFL + Tx event FIFO full interrupt line. + 14 + 1 + read-write + + + TEFLL + Tx event FIFO element lost interrupt line. + 15 + 1 + read-write + + + TSWL + Timestamp wraparound interrupt line. + 16 + 1 + read-write + + + MRAFL + Message RAM access failure interrupt line. + 17 + 1 + read-write + + + TOOL + Timeout occurred interrupt line. + 18 + 1 + read-write + + + DRXL + Message stored in dedicated Rx buffer interrupt line. + 19 + 1 + read-write + + + BECL + Bit error corrected interrupt line. + 20 + 1 + read-write + + + BEUL + Bit error uncorrected interrupt line. + 21 + 1 + read-write + + + ELOL + Error logging overflow interrupt line. + 22 + 1 + read-write + + + EPL + Error passive interrupt line. + 23 + 1 + read-write + + + EWL + Warning status interrupt line. + 24 + 1 + read-write + + + BOL + Bus_Off Status interrupt line. + 25 + 1 + read-write + + + WDIL + Watchdog interrupt line. + 26 + 1 + read-write + + + PEAL + Protocol error in arbitration phase interrupt line. + 27 + 1 + read-write + + + PEDL + Protocol error in data phase interrupt line. + 28 + 1 + read-write + + + ARAL + Access to reserved address interrupt line. + 29 + 1 + read-write + + + + + ILE + Interrupt Line Enable + 0x5C + 32 + read-write + 0 + 0x3 + + + EINT0 + Enable interrupt line 0. + 0 + 1 + read-write + + + EINT1 + Enable interrupt line 1. + 1 + 1 + read-write + + + + + GFC + Global Filter Configuration + 0x80 + 32 + read-write + 0 + 0x3F + + + RRFE + Reject remote frames extended. + 0 + 1 + read-write + + + RRFS + Reject remote frames standard. + 1 + 1 + read-write + + + ANFE + Accept non-matching frames extended. + 2 + 2 + read-write + + + ANFS + Accept non-matching frames standard. + 4 + 2 + read-write + + + + + SIDFC + Standard ID Filter Configuration + 0x84 + 32 + read-write + 0 + 0xFFFFFC + + + FLSSA + Filter list standard start address. + 2 + 14 + read-write + + + LSS + List size standard 0 = No standard message ID filter. + 16 + 8 + read-write + + + + + XIDFC + Extended ID Filter Configuration + 0x88 + 32 + read-write + 0 + 0xFFFFFC + + + FLESA + Filter list extended start address. + 2 + 14 + read-write + + + LSE + List size extended 0 = No extended message ID filter. + 16 + 8 + read-write + + + + + XIDAM + Extended ID AND Mask + 0x90 + 32 + read-write + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID mask. + 0 + 29 + read-write + + + + + HPMS + High Priority Message Status + 0x94 + 32 + read-only + 0 + 0xFFFF + + + BIDX + Buffer index. + 0 + 6 + read-only + + + MSI + Message storage indicator. + 6 + 2 + read-only + + + FIDX + Filter index. + 8 + 7 + read-only + + + FLST + Filter list. + 15 + 1 + read-only + + + + + NDAT1 + New Data 1 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + ND + New Data. + 0 + 32 + read-write + + + + + NDAT2 + New Data 2 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + ND + New Data. + 0 + 32 + read-write + + + + + RXF0C + Rx FIFO 0 Configuration + 0xA0 + 32 + read-write + 0 + 0xFF7FFFFC + + + F0SA + Rx FIFO 0 start address. + 2 + 14 + read-write + + + F0S + Rx FIFO 0 size. + 16 + 7 + read-write + + + F0WM + Rx FIFO 0 watermark 0 = Watermark interrupt disabled. + 24 + 7 + read-write + + + F0OM + FIFO 0 operation mode. + 31 + 1 + read-write + + + + + RXF0S + Rx FIFO 0 Status + 0xA4 + 32 + read-write + 0 + 0x33F3F7F + + + F0FL + Rx FIFO 0 fill level. + 0 + 7 + read-only + + + F0GI + Rx FIFO 0 get index. + 8 + 6 + read-only + + + F0PI + Rx FIFO 0 put index. + 16 + 6 + read-only + + + F0F + Rx FIFO 0 full. + 24 + 1 + read-only + + + RF0L + Rx FIFO 0 message lost. + 25 + 1 + read-only + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0xA8 + 32 + read-write + 0 + 0x3F + + + F0AI + Rx FIFO 0 acknowledge index. + 0 + 6 + read-write + + + + + RXBC + Rx Buffer Configuration + 0xAC + 32 + read-write + 0 + 0xFFFC + + + RBSA + Rx buffer start address. + 2 + 14 + read-write + + + + + RXF1C + Rx FIFO 1 Configuration + 0xB0 + 32 + read-write + 0 + 0xFF7FFFFC + + + F1SA + Rx FIFO 1 start address. + 2 + 14 + read-write + + + F1S + Rx FIFO 1 size 0 = No Rx FIFO 1. + 16 + 7 + read-write + + + F1WM + Rx FIFO 1 watermark 0 = Watermark interrupt disabled. + 24 + 7 + read-write + + + F1OM + FIFO 1 operation mode. + 31 + 1 + read-write + + + + + RXF1S + Rx FIFO 1 Status + 0xB4 + 32 + read-only + 0 + 0x33F3F7F + + + F1FL + Rx FIFO 1 fill level. + 0 + 7 + read-only + + + F1GI + Rx FIFO 1 get index. + 8 + 6 + read-only + + + F1PI + Rx FIFO 1 put index. + 16 + 6 + read-only + + + F1F + Rx FIFO 1 full. + 24 + 1 + read-only + + + RF1L + Rx FIFO 1 message lost. + 25 + 1 + read-only + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0xB8 + 32 + read-write + 0 + 0x3F + + + F1AI + Rx FIFO 1 acknowledge index. + 0 + 6 + read-write + + + + + RXESC + Rx Buffer and FIFO Element Size Configuration + 0xBC + 32 + read-write + 0 + 0x777 + + + F0DS + Rx FIFO 0 data field size. + 0 + 3 + read-write + + + F1DS + Rx FIFO 1 data field size. + 4 + 3 + read-write + + + RBDS + . + 8 + 3 + read-write + + + + + TXBC + Tx Buffer Configuration + 0xC0 + 32 + read-write + 0 + 0x7F3FFFFC + + + TBSA + Tx buffers start address. + 2 + 14 + read-write + + + NDTB + Number of dedicated transmit buffers 0 = No dedicated Tx buffers. + 16 + 6 + read-write + + + TFQS + Transmit FIFO/queue size 0 = No tx FIFO/Queue. + 24 + 6 + read-write + + + TFQM + Tx FIFO/queue mode. + 30 + 1 + read-write + + + + + TXFQS + Tx FIFO/Queue Status + 0xC4 + 32 + read-write + 0 + 0x3F1F3F + + + TFGI + Tx FIFO get index. + 8 + 5 + read-write + + + TFQPI + Tx FIFO/queue put index. + 16 + 5 + read-write + + + TFQF + Tx FIFO/queue full. + 21 + 1 + read-write + + + + + TXESC + Tx Buffer Element Size Configuration + 0xC8 + 32 + read-write + 0 + 0x7 + + + TBDS + Tx buffer data field size. + 0 + 3 + read-write + + + + + TXBRP + Tx Buffer Request Pending + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + TRP + Transmission request pending. + 0 + 32 + read-only + + + + + TXBAR + Tx Buffer Add Request + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + AR + Add request. + 0 + 32 + read-write + + + + + TXBCR + Tx Buffer Cancellation Request + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CR + Cancellation request. + 0 + 32 + read-write + + + + + TXBTO + Tx Buffer Transmission Occurred + 0xD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + TO + Transmission occurred. + 0 + 32 + read-only + + + + + TXBCF + Tx Buffer Cancellation Finished + 0xDC + 32 + read-only + 0 + 0xFFFFFFFF + + + TO + Cancellation finished. + 0 + 32 + read-only + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIE + Transmission interrupt enable. + 0 + 32 + read-write + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CFIE + Cancellation finished interrupt enable. + 0 + 32 + read-write + + + + + TXEFC + Tx Event FIFO Configuration + 0xF0 + 32 + read-write + 0 + 0x3F3FFFFC + + + EFSA + Event FIFO start address. + 2 + 14 + read-write + + + EFS + Event FIFO size 0 = Tx event FIFO disabled. + 16 + 6 + read-write + + + EFWM + Event FIFO watermark 0 = Watermark interrupt disabled. + 24 + 6 + read-write + + + + + TXEFS + Tx Event FIFO Status + 0xF4 + 32 + read-only + 0 + 0x33F1F3F + + + EFFL + Event FIFO fill level. + 0 + 6 + read-only + + + EFGI + Event FIFO get index. + 8 + 5 + read-only + + + EFPI + Event FIFO put index. + 16 + 6 + read-only + + + EFF + Event FIFO full. + 24 + 1 + read-only + + + TEFL + Tx event FIFO element lost. + 25 + 1 + read-only + + + + + TXEFA + Tx Event FIFO Acknowledge + 0xF8 + 32 + read-write + 0 + 0x1F + + + EFAI + Event FIFO acknowledge index. + 0 + 5 + read-write + + + + + MRBA + CAN Message RAM Base Address + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + BA + Base address for the message RAM in the chip memory map. + 16 + 16 + read-write + + + + + ETSCC + External Timestamp Counter Configuration + 0x400 + 32 + read-write + 0 + 0x800007FF + + + ETCP + External timestamp prescaler value. + 0 + 11 + read-write + + + ETCE + External timestamp counter enable. + 31 + 1 + read-write + + + + + ETSCV + External Timestamp Counter Value + 0x600 + 32 + read-write + 0 + 0xFFFF + + + ETSC + External timestamp counter. + 0 + 16 + read-write + + + + + + + ADC0 + ADC + ADC + 0x400A0000 + + 0 + 0x584 + registers + + + ADC0 + 22 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1002C0B + 0xFFFFFFFF + + + RES + Resolution + 0 + 1 + read-only + + + RES_0 + Up to 13-bit differential/12-bit single ended resolution supported. + 0 + + + RES_1 + Up to 16-bit differential/16-bit single ended resolution supported. + 0x1 + + + + + DIFFEN + Differential Supported + 1 + 1 + read-only + + + DIFFEN_0 + Differential operation not supported. + 0 + + + DIFFEN_1 + Differential operation supported. CMDLa[CTYPE] controls fields implemented. + 0x1 + + + + + MVI + Multi Vref Implemented + 3 + 1 + read-only + + + MVI_0 + Single voltage reference high (VREFH) input supported. + 0 + + + MVI_1 + Multiple voltage reference high (VREFH) inputs supported. + 0x1 + + + + + CSW + Channel Scale Width + 4 + 3 + read-only + + + CSW_0 + Channel scaling not supported. + 0 + + + CSW_1 + Channel scaling supported. 1-bit CSCALE control field. + 0x1 + + + CSW_6 + Channel scaling supported. 6-bit CSCALE control field. + 0x6 + + + + + VR1RNGI + Voltage Reference 1 Range Control Bit Implemented + 8 + 1 + read-only + + + VR1RNGI_0 + Range control not required. CFG[VREF1RNG] is not implemented. + 0 + + + VR1RNGI_1 + Range control required. CFG[VREF1RNG] is implemented. + 0x1 + + + + + IADCKI + Internal ADC Clock implemented + 9 + 1 + read-only + + + IADCKI_0 + Internal clock source not implemented. + 0 + + + IADCKI_1 + Internal clock source (and CFG[ADCKEN]) implemented. + 0x1 + + + + + CALOFSI + Calibration Function Implemented + 10 + 1 + read-only + + + CALOFSI_0 + Calibration Not Implemented. + 0 + + + CALOFSI_1 + Calibration Implemented. + 0x1 + + + + + NUM_SEC + Number of Single Ended Outputs Supported + 11 + 1 + read-only + + + NUM_SEC_0 + This design supports one single ended conversion at a time. + 0 + + + NUM_SEC_1 + This design supports two simultanious single ended conversions. + 0x1 + + + + + NUM_FIFO + Number of FIFOs + 12 + 3 + read-only + + + NUM_FIFO_0 + N/A + 0 + + + NUM_FIFO_1 + This design supports one result FIFO. + 0x1 + + + NUM_FIFO_2 + This design supports two result FIFOs. + 0x2 + + + NUM_FIFO_3 + This design supports three result FIFOs. + 0x3 + + + NUM_FIFO_4 + This design supports four result FIFOs. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0xF041010 + 0xFFFFFFFF + + + TRIG_NUM + Trigger Number + 0 + 8 + read-only + + + FIFOSIZE + Result FIFO Depth + 8 + 8 + read-only + + + FIFOSIZE_1 + Result FIFO depth = 1 dataword. + 0x1 + + + FIFOSIZE_4 + Result FIFO depth = 4 datawords. + 0x4 + + + FIFOSIZE_8 + Result FIFO depth = 8 datawords. + 0x8 + + + FIFOSIZE_16 + Result FIFO depth = 16 datawords. + 0x10 + + + FIFOSIZE_32 + Result FIFO depth = 32 datawords. + 0x20 + + + FIFOSIZE_64 + Result FIFO depth = 64 datawords. + 0x40 + + + + + CV_NUM + Compare Value Number + 16 + 8 + read-only + + + CMD_NUM + Command Buffer Number + 24 + 8 + read-only + + + + + CTRL + ADC Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCEN + ADC Enable + 0 + 1 + read-write + + + ADCEN_0 + ADC is disabled. + 0 + + + ADCEN_1 + ADC is enabled. + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + ADC logic is not reset. + 0 + + + RST_1 + ADC logic is reset. + 0x1 + + + + + DOZEN + Doze Enable + 2 + 1 + read-write + + + DOZEN_0 + ADC is enabled in Doze mode. + 0 + + + DOZEN_1 + ADC is disabled in Doze mode. + 0x1 + + + + + CAL_REQ + Auto-Calibration Request + 3 + 1 + read-write + + + CAL_REQ_0 + No request for auto-calibration has been made. + 0 + + + CAL_REQ_1 + A request for auto-calibration has been made + 0x1 + + + + + CALOFS + Configure for offset calibration function + 4 + 1 + read-write + + + CALOFS_0 + Calibration function disabled + 0 + + + CALOFS_1 + Request for offset calibration function + 0x1 + + + + + RSTFIFO0 + Reset FIFO 0 + 8 + 1 + read-write + + + RSTFIFO0_0 + No effect. + 0 + + + RSTFIFO0_1 + FIFO 0 is reset. + 0x1 + + + + + RSTFIFO1 + Reset FIFO 1 + 9 + 1 + read-write + + + RSTFIFO1_0 + No effect. + 0 + + + RSTFIFO1_1 + FIFO 1 is reset. + 0x1 + + + + + CAL_AVGS + Auto-Calibration Averages + 16 + 3 + read-write + + + CAL_AVGS_0 + Single conversion. + 0 + + + CAL_AVGS_1 + 2 conversions averaged. + 0x1 + + + CAL_AVGS_2 + 4 conversions averaged. + 0x2 + + + CAL_AVGS_3 + 8 conversions averaged. + 0x3 + + + CAL_AVGS_4 + 16 conversions averaged. + 0x4 + + + CAL_AVGS_5 + 32 conversions averaged. + 0x5 + + + CAL_AVGS_6 + 64 conversions averaged. + 0x6 + + + CAL_AVGS_7 + 128 conversions averaged. + 0x7 + + + + + + + STAT + ADC Status Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDY0 + Result FIFO 0 Ready Flag + 0 + 1 + read-only + + + RDY0_0 + Result FIFO 0 data level not above watermark level. + 0 + + + RDY0_1 + Result FIFO 0 holding data above watermark level. + 0x1 + + + + + FOF0 + Result FIFO 0 Overflow Flag + 1 + 1 + read-write + oneToClear + + + FOF0_0 + No result FIFO 0 overflow has occurred since the last time the flag was cleared. + 0 + + + FOF0_1 + At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + RDY1 + Result FIFO1 Ready Flag + 2 + 1 + read-only + + + RDY1_0 + Result FIFO1 data level not above watermark level. + 0 + + + RDY1_1 + Result FIFO1 holding data above watermark level. + 0x1 + + + + + FOF1 + Result FIFO1 Overflow Flag + 3 + 1 + read-write + oneToClear + + + FOF1_0 + No result FIFO1 overflow has occurred since the last time the flag was cleared. + 0 + + + FOF1_1 + At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TEXC_INT + Interrupt Flag For High Priority Trigger Exception + 8 + 1 + read-write + oneToClear + + + TEXC_INT_0 + No trigger exceptions have occurred. + 0 + + + TEXC_INT_1 + A trigger exception has occurred and is pending acknowledgement. + 0x1 + + + + + TCOMP_INT + Interrupt Flag For Trigger Completion + 9 + 1 + read-write + oneToClear + + + TCOMP_INT_0 + Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + 0 + + + TCOMP_INT_1 + Trigger sequence has been completed and all data is stored in the associated FIFO. + 0x1 + + + + + CAL_RDY + Calibration Ready + 10 + 1 + read-only + + + CAL_RDY_0 + Calibration is incomplete or hasn't been ran. + 0 + + + CAL_RDY_1 + The ADC is calibrated. + 0x1 + + + + + ADC_ACTIVE + ADC Active + 11 + 1 + read-only + + + ADC_ACTIVE_0 + The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + 0 + + + ADC_ACTIVE_1 + The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + 0x1 + + + + + TRGACT + Trigger Active + 16 + 4 + read-only + + + TRGACT_0 + Command (sequence) associated with Trigger 0 currently being executed. + 0 + + + TRGACT_1 + Command (sequence) associated with Trigger 1 currently being executed. + 0x1 + + + TRGACT_2 + Command (sequence) associated with Trigger 2 currently being executed. + 0x2 + + + TRGACT_3 + Command (sequence) from the associated Trigger number is currently being executed. + 0x3 + + + TRGACT_4 + Command (sequence) from the associated Trigger number is currently being executed. + 0x4 + + + TRGACT_5 + Command (sequence) from the associated Trigger number is currently being executed. + 0x5 + + + TRGACT_6 + Command (sequence) from the associated Trigger number is currently being executed. + 0x6 + + + TRGACT_7 + Command (sequence) from the associated Trigger number is currently being executed. + 0x7 + + + TRGACT_8 + Command (sequence) from the associated Trigger number is currently being executed. + 0x8 + + + TRGACT_9 + Command (sequence) from the associated Trigger number is currently being executed. + 0x9 + + + + + CMDACT + Command Active + 24 + 4 + read-only + + + CMDACT_0 + No command is currently in progress. + 0 + + + CMDACT_1 + Command 1 currently being executed. + 0x1 + + + CMDACT_2 + Command 2 currently being executed. + 0x2 + + + CMDACT_3 + Associated command number is currently being executed. + 0x3 + + + CMDACT_4 + Associated command number is currently being executed. + 0x4 + + + CMDACT_5 + Associated command number is currently being executed. + 0x5 + + + CMDACT_6 + Associated command number is currently being executed. + 0x6 + + + CMDACT_7 + Associated command number is currently being executed. + 0x7 + + + CMDACT_8 + Associated command number is currently being executed. + 0x8 + + + CMDACT_9 + Associated command number is currently being executed. + 0x9 + + + + + + + IE + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMIE0 + FIFO 0 Watermark Interrupt Enable + 0 + 1 + read-write + + + FWMIE0_0 + FIFO 0 watermark interrupts are not enabled. + 0 + + + FWMIE0_1 + FIFO 0 watermark interrupts are enabled. + 0x1 + + + + + FOFIE0 + Result FIFO 0 Overflow Interrupt Enable + 1 + 1 + read-write + + + FOFIE0_0 + FIFO 0 overflow interrupts are not enabled. + 0 + + + FOFIE0_1 + FIFO 0 overflow interrupts are enabled. + 0x1 + + + + + FWMIE1 + FIFO1 Watermark Interrupt Enable + 2 + 1 + read-write + + + FWMIE1_0 + FIFO1 watermark interrupts are not enabled. + 0 + + + FWMIE1_1 + FIFO1 watermark interrupts are enabled. + 0x1 + + + + + FOFIE1 + Result FIFO1 Overflow Interrupt Enable + 3 + 1 + read-write + + + FOFIE1_0 + No result FIFO1 overflow has occurred since the last time the flag was cleared. + 0 + + + FOFIE1_1 + At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TEXC_IE + Trigger Exception Interrupt Enable + 8 + 1 + read-write + + + TEXC_IE_0 + Trigger exception interrupts are disabled. + 0 + + + TEXC_IE_1 + Trigger exception interrupts are enabled. + 0x1 + + + + + TCOMP_IE + Trigger Completion Interrupt Enable + 16 + 16 + read-write + + + TCOMP_IE_0 + Trigger completion interrupts are disabled. + 0 + + + TCOMP_IE_1 + Trigger completion interrupts are enabled for trigger source 0 only. + 0x1 + + + TCOMP_IE_2 + Trigger completion interrupts are enabled for trigger source 1 only. + 0x2 + + + TCOMP_IE_3 + Associated trigger completion interrupts are enabled. + 0x3 + + + TCOMP_IE_4 + Associated trigger completion interrupts are enabled. + 0x4 + + + TCOMP_IE_5 + Associated trigger completion interrupts are enabled. + 0x5 + + + TCOMP_IE_6 + Associated trigger completion interrupts are enabled. + 0x6 + + + TCOMP_IE_7 + Associated trigger completion interrupts are enabled. + 0x7 + + + TCOMP_IE_8 + Associated trigger completion interrupts are enabled. + 0x8 + + + TCOMP_IE_9 + Associated trigger completion interrupts are enabled. + 0x9 + + + TCOMP_IE_65535 + Trigger completion interrupts are enabled for every trigger source. + 0xFFFF + + + + + + + DE + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMDE0 + FIFO 0 Watermark DMA Enable + 0 + 1 + read-write + + + FWMDE0_0 + DMA request disabled. + 0 + + + FWMDE0_1 + DMA request enabled. + 0x1 + + + + + FWMDE1 + FIFO1 Watermark DMA Enable + 1 + 1 + read-write + + + FWMDE1_0 + DMA request disabled. + 0 + + + FWMDE1_1 + DMA request enabled. + 0x1 + + + + + + + CFG + ADC Configuration Register + 0x20 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + TPRICTRL + ADC trigger priority control + 0 + 2 + read-write + + + TPRICTRL_0 + If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. + 0 + + + TPRICTRL_1 + If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + 0x1 + + + TPRICTRL_2 + If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. + 0x2 + + + + + PWRSEL + Power Configuration Select + 4 + 2 + read-write + + + PWRSEL_0 + Lowest power setting. + 0 + + + PWRSEL_1 + Higher power setting than 0b0. + 0x1 + + + PWRSEL_2 + Higher power setting than 0b1. + 0x2 + + + PWRSEL_3 + Highest power setting. + 0x3 + + + + + REFSEL + Voltage Reference Selection + 6 + 2 + read-write + + + REFSEL_0 + (Default) Option 1 setting. + 0 + + + REFSEL_1 + Option 2 setting. + 0x1 + + + REFSEL_2 + Option 3 setting. + 0x2 + + + + + TRES + Trigger Resume Enable + 8 + 1 + read-write + + + TRES_0 + Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + 0 + + + TRES_1 + Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + 0x1 + + + + + TCMDRES + Trigger Command Resume + 9 + 1 + read-write + + + TCMDRES_0 + Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + 0 + + + TCMDRES_1 + Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + 0x1 + + + + + HPT_EXDI + High Priority Trigger Exception Disable + 10 + 1 + read-write + + + HPT_EXDI_0 + High priority trigger exceptions are enabled. + 0 + + + HPT_EXDI_1 + High priority trigger exceptions are disabled. + 0x1 + + + + + PUDLY + Power Up Delay + 16 + 8 + read-write + + + PWREN + ADC Analog Pre-Enable + 28 + 1 + read-write + + + PWREN_0 + ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + 0 + + + PWREN_1 + ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. + 0x1 + + + + + + + PAUSE + ADC Pause Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PAUSEDLY + Pause Delay + 0 + 9 + read-write + + + PAUSEEN + PAUSE Option Enable + 31 + 1 + read-write + + + PAUSEEN_0 + Pause operation disabled + 0 + + + PAUSEEN_1 + Pause operation enabled + 0x1 + + + + + + + SWTRIG + Software Trigger Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWT0 + Software trigger 0 event + 0 + 1 + read-write + + + SWT0_0 + No trigger 0 event generated. + 0 + + + SWT0_1 + Trigger 0 event generated. + 0x1 + + + + + SWT1 + Software trigger 1 event + 1 + 1 + read-write + + + SWT1_0 + No trigger 1 event generated. + 0 + + + SWT1_1 + Trigger 1 event generated. + 0x1 + + + + + SWT2 + Software trigger 2 event + 2 + 1 + read-write + + + SWT2_0 + No trigger 2 event generated. + 0 + + + SWT2_1 + Trigger 2 event generated. + 0x1 + + + + + SWT3 + Software trigger 3 event + 3 + 1 + read-write + + + SWT3_0 + No trigger 3 event generated. + 0 + + + SWT3_1 + Trigger 3 event generated. + 0x1 + + + + + SWT4 + Software trigger 4 event + 4 + 1 + read-write + + + SWT4_0 + No trigger 4 event generated. + 0 + + + SWT4_1 + Trigger 4 event generated. + 0x1 + + + + + SWT5 + Software trigger 5 event + 5 + 1 + read-write + + + SWT5_0 + No trigger 5 event generated. + 0 + + + SWT5_1 + Trigger 5 event generated. + 0x1 + + + + + SWT6 + Software trigger 6 event + 6 + 1 + read-write + + + SWT6_0 + No trigger 6 event generated. + 0 + + + SWT6_1 + Trigger 6 event generated. + 0x1 + + + + + SWT7 + Software trigger 7 event + 7 + 1 + read-write + + + SWT7_0 + No trigger 7 event generated. + 0 + + + SWT7_1 + Trigger 7 event generated. + 0x1 + + + + + SWT8 + Software trigger 8 event + 8 + 1 + read-write + + + SWT8_0 + No trigger 8 event generated. + 0 + + + SWT8_1 + Trigger 8 event generated. + 0x1 + + + + + SWT9 + Software trigger 9 event + 9 + 1 + read-write + + + SWT9_0 + No trigger 9 event generated. + 0 + + + SWT9_1 + Trigger 9 event generated. + 0x1 + + + + + SWT10 + Software trigger 10 event + 10 + 1 + read-write + + + SWT10_0 + No trigger 10 event generated. + 0 + + + SWT10_1 + Trigger 10 event generated. + 0x1 + + + + + SWT11 + Software trigger 11 event + 11 + 1 + read-write + + + SWT11_0 + No trigger 11 event generated. + 0 + + + SWT11_1 + Trigger 11 event generated. + 0x1 + + + + + SWT12 + Software trigger 12 event + 12 + 1 + read-write + + + SWT12_0 + No trigger 12 event generated. + 0 + + + SWT12_1 + Trigger 12 event generated. + 0x1 + + + + + SWT13 + Software trigger 13 event + 13 + 1 + read-write + + + SWT13_0 + No trigger 13 event generated. + 0 + + + SWT13_1 + Trigger 13 event generated. + 0x1 + + + + + SWT14 + Software trigger 14 event + 14 + 1 + read-write + + + SWT14_0 + No trigger 14 event generated. + 0 + + + SWT14_1 + Trigger 14 event generated. + 0x1 + + + + + SWT15 + Software trigger 15 event + 15 + 1 + read-write + + + SWT15_0 + No trigger 15 event generated. + 0 + + + SWT15_1 + Trigger 15 event generated. + 0x1 + + + + + + + TSTAT + Trigger Status Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEXC_NUM + Trigger Exception Number + 0 + 16 + read-write + oneToClear + + + TEXC_NUM_0 + No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + 0 + + + TEXC_NUM_1 + Trigger 0 has been interrupted by a high priority exception. + 0x1 + + + TEXC_NUM_2 + Trigger 1 has been interrupted by a high priority exception. + 0x2 + + + TEXC_NUM_3 + Associated trigger sequence has interrupted by a high priority exception. + 0x3 + + + TEXC_NUM_4 + Associated trigger sequence has interrupted by a high priority exception. + 0x4 + + + TEXC_NUM_5 + Associated trigger sequence has interrupted by a high priority exception. + 0x5 + + + TEXC_NUM_6 + Associated trigger sequence has interrupted by a high priority exception. + 0x6 + + + TEXC_NUM_7 + Associated trigger sequence has interrupted by a high priority exception. + 0x7 + + + TEXC_NUM_8 + Associated trigger sequence has interrupted by a high priority exception. + 0x8 + + + TEXC_NUM_9 + Associated trigger sequence has interrupted by a high priority exception. + 0x9 + + + TEXC_NUM_65535 + Every trigger sequence has been interrupted by a high priority exception. + 0xFFFF + + + + + TCOMP_FLAG + Trigger Completion Flag + 16 + 16 + read-write + oneToClear + + + TCOMP_FLAG_0 + No triggers have been completed. Trigger completion interrupts are disabled. + 0 + + + TCOMP_FLAG_1 + Trigger 0 has been completed and triger 0 has enabled completion interrupts. + 0x1 + + + TCOMP_FLAG_2 + Trigger 1 has been completed and triger 1 has enabled completion interrupts. + 0x2 + + + TCOMP_FLAG_3 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x3 + + + TCOMP_FLAG_4 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x4 + + + TCOMP_FLAG_5 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x5 + + + TCOMP_FLAG_6 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x6 + + + TCOMP_FLAG_7 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x7 + + + TCOMP_FLAG_8 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x8 + + + TCOMP_FLAG_9 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x9 + + + TCOMP_FLAG_65535 + Every trigger sequence has been completed and every trigger has enabled completion interrupts. + 0xFFFF + + + + + + + OFSTRIM + ADC Offset Trim Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFSTRIM_A + Trim for offset + 0 + 5 + read-write + + + OFSTRIM_B + Trim for offset + 16 + 5 + read-write + + + + + 16 + 0x4 + TCTRL[%s] + Trigger Control Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HTEN + Trigger enable + 0 + 1 + read-write + + + HTEN_0 + Hardware trigger source disabled + 0 + + + HTEN_1 + Hardware trigger source enabled + 0x1 + + + + + FIFO_SEL_A + SAR Result Destination For Channel A + 1 + 1 + read-write + + + FIFO_SEL_A_0 + Result written to FIFO 0 + 0 + + + FIFO_SEL_A_1 + Result written to FIFO 1 + 0x1 + + + + + FIFO_SEL_B + SAR Result Destination For Channel B + 2 + 1 + read-write + + + FIFO_SEL_B_0 + Result written to FIFO 0 + 0 + + + FIFO_SEL_B_1 + Result written to FIFO 1 + 0x1 + + + + + TPRI + Trigger priority setting + 8 + 4 + read-write + + + TPRI_0 + Set to highest priority, Level 1 + 0 + + + TPRI_1 + Set to corresponding priority level + 0x1 + + + TPRI_2 + Set to corresponding priority level + 0x2 + + + TPRI_3 + Set to corresponding priority level + 0x3 + + + TPRI_4 + Set to corresponding priority level + 0x4 + + + TPRI_5 + Set to corresponding priority level + 0x5 + + + TPRI_6 + Set to corresponding priority level + 0x6 + + + TPRI_7 + Set to corresponding priority level + 0x7 + + + TPRI_8 + Set to corresponding priority level + 0x8 + + + TPRI_9 + Set to corresponding priority level + 0x9 + + + TPRI_15 + Set to lowest priority, Level 16 + 0xF + + + + + RSYNC + Trigger Resync + 15 + 1 + read-write + + + TDLY + Trigger delay select + 16 + 4 + read-write + + + TCMD + Trigger command select + 24 + 4 + read-write + + + TCMD_0 + Not a valid selection from the command buffer. Trigger event is ignored. + 0 + + + TCMD_1 + CMD1 is executed + 0x1 + + + TCMD_2 + Corresponding CMD is executed + 0x2 + + + TCMD_3 + Corresponding CMD is executed + 0x3 + + + TCMD_4 + Corresponding CMD is executed + 0x4 + + + TCMD_5 + Corresponding CMD is executed + 0x5 + + + TCMD_6 + Corresponding CMD is executed + 0x6 + + + TCMD_7 + Corresponding CMD is executed + 0x7 + + + TCMD_8 + Corresponding CMD is executed + 0x8 + + + TCMD_9 + Corresponding CMD is executed + 0x9 + + + TCMD_15 + CMD15 is executed + 0xF + + + + + + + 2 + 0x4 + FCTRL[%s] + FIFO Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FCOUNT + Result FIFO counter + 0 + 5 + read-only + + + FWMARK + Watermark level selection + 16 + 4 + read-write + + + + + 2 + 0x4 + GCC[%s] + Gain Calibration Control + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GAIN_CAL + Gain Calibration Value + 0 + 16 + read-only + + + RDY + Gain Calibration Value Valid + 24 + 1 + read-only + + + RDY_0 + The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + 0 + + + RDY_1 + The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + 0x1 + + + + + + + 2 + 0x4 + GCR[%s] + Gain Calculation Result + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GCALR + Gain Calculation Result + 0 + 16 + read-write + + + RDY + Gain Calculation Ready + 24 + 1 + read-write + + + RDY_0 + The gain offset calculation value is invalid. + 0 + + + RDY_1 + The gain calibration value is valid. + 0x1 + + + + + + + CMDL1 + ADC Command Low Buffer Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH1 + ADC Command High Buffer Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL2 + ADC Command Low Buffer Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH2 + ADC Command High Buffer Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL3 + ADC Command Low Buffer Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH3 + ADC Command High Buffer Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL4 + ADC Command Low Buffer Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH4 + ADC Command High Buffer Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL5 + ADC Command Low Buffer Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH5 + ADC Command High Buffer Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL6 + ADC Command Low Buffer Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH6 + ADC Command High Buffer Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL7 + ADC Command Low Buffer Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH7 + ADC Command High Buffer Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL8 + ADC Command Low Buffer Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH8 + ADC Command High Buffer Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL9 + ADC Command Low Buffer Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH9 + ADC Command High Buffer Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL10 + ADC Command Low Buffer Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH10 + ADC Command High Buffer Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL11 + ADC Command Low Buffer Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH11 + ADC Command High Buffer Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL12 + ADC Command Low Buffer Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH12 + ADC Command High Buffer Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL13 + ADC Command Low Buffer Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH13 + ADC Command High Buffer Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL14 + ADC Command Low Buffer Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH14 + ADC Command High Buffer Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL15 + ADC Command Low Buffer Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH15 + ADC Command High Buffer Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + 4 + 0x4 + 1,2,3,4 + CV%s + Compare Value Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + CVL + Compare Value Low. + 0 + 16 + read-write + + + CVH + Compare Value High. + 16 + 16 + read-write + + + + + 2 + 0x4 + RESFIFO[%s] + ADC Data Result FIFO Register + 0x300 + 32 + read-only + 0 + 0xFFFFFFFF + + + D + Data result + 0 + 16 + read-only + + + TSRC + Trigger Source + 16 + 4 + read-only + + + TSRC_0 + Trigger source 0 initiated this conversion. + 0 + + + TSRC_1 + Trigger source 1 initiated this conversion. + 0x1 + + + TSRC_2 + Corresponding trigger source initiated this conversion. + 0x2 + + + TSRC_3 + Corresponding trigger source initiated this conversion. + 0x3 + + + TSRC_4 + Corresponding trigger source initiated this conversion. + 0x4 + + + TSRC_5 + Corresponding trigger source initiated this conversion. + 0x5 + + + TSRC_6 + Corresponding trigger source initiated this conversion. + 0x6 + + + TSRC_7 + Corresponding trigger source initiated this conversion. + 0x7 + + + TSRC_8 + Corresponding trigger source initiated this conversion. + 0x8 + + + TSRC_9 + Corresponding trigger source initiated this conversion. + 0x9 + + + TSRC_15 + Trigger source 15 initiated this conversion. + 0xF + + + + + LOOPCNT + Loop count value + 20 + 4 + read-only + + + LOOPCNT_0 + Result is from initial conversion in command. + 0 + + + LOOPCNT_1 + Result is from second conversion in command. + 0x1 + + + LOOPCNT_2 + Result is from LOOPCNT+1 conversion in command. + 0x2 + + + LOOPCNT_3 + Result is from LOOPCNT+1 conversion in command. + 0x3 + + + LOOPCNT_4 + Result is from LOOPCNT+1 conversion in command. + 0x4 + + + LOOPCNT_5 + Result is from LOOPCNT+1 conversion in command. + 0x5 + + + LOOPCNT_6 + Result is from LOOPCNT+1 conversion in command. + 0x6 + + + LOOPCNT_7 + Result is from LOOPCNT+1 conversion in command. + 0x7 + + + LOOPCNT_8 + Result is from LOOPCNT+1 conversion in command. + 0x8 + + + LOOPCNT_9 + Result is from LOOPCNT+1 conversion in command. + 0x9 + + + LOOPCNT_15 + Result is from 16th conversion in command. + 0xF + + + + + CMDSRC + Command Buffer Source + 24 + 4 + read-only + + + CMDSRC_0 + Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + 0 + + + CMDSRC_1 + CMD1 buffer used as control settings for this conversion. + 0x1 + + + CMDSRC_2 + Corresponding command buffer used as control settings for this conversion. + 0x2 + + + CMDSRC_3 + Corresponding command buffer used as control settings for this conversion. + 0x3 + + + CMDSRC_4 + Corresponding command buffer used as control settings for this conversion. + 0x4 + + + CMDSRC_5 + Corresponding command buffer used as control settings for this conversion. + 0x5 + + + CMDSRC_6 + Corresponding command buffer used as control settings for this conversion. + 0x6 + + + CMDSRC_7 + Corresponding command buffer used as control settings for this conversion. + 0x7 + + + CMDSRC_8 + Corresponding command buffer used as control settings for this conversion. + 0x8 + + + CMDSRC_9 + Corresponding command buffer used as control settings for this conversion. + 0x9 + + + CMDSRC_15 + CMD15 buffer used as control settings for this conversion. + 0xF + + + + + VALID + FIFO entry is valid + 31 + 1 + read-only + + + VALID_0 + FIFO is empty. Discard any read from RESFIFO. + 0 + + + VALID_1 + FIFO record read from RESFIFO is valid. + 0x1 + + + + + + + 33 + 0x4 + CAL_GAR[%s] + Calibration General A-Side Registers + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GAR_VAL + Calibration General A Side Register Element + 0 + 16 + read-write + + + + + 33 + 0x4 + CAL_GBR[%s] + Calibration General B-Side Registers + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GBR_VAL + Calibration General B Side Register Element + 0 + 16 + read-write + + + + + + + CDOG + CDOG + CDOG + 0x400A1000 + + 0 + 0x4C + registers + + + CDOG + 60 + + + + CONTROL + The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself. + 0 + 32 + read-write + 0x50092492 + 0xFFFFFFFF + + + LOCK_CTRL + Lock control field + 0 + 2 + read-write + + + TIMEOUT_CTRL + TIMEOUT control + 2 + 3 + read-write + + + MISCOMPARE_CTRL + MISCOMPARE control field + 5 + 3 + read-write + + + SEQUENCE_CTRL + SEQUENCE control field + 8 + 3 + read-write + + + CONTROL_CTRL + CONTROL control field + 11 + 3 + read-write + + + STATE_CTRL + STATE control field + 14 + 3 + read-write + + + ADDRESS_CTRL + ADDRESS control field + 17 + 3 + read-write + + + IRQ_PAUSE + IRQ pause control field + 28 + 2 + read-write + + + DEBUG_HALT_CTRL + DEBUG_HALT control field + 30 + 2 + read-write + + + + + RELOAD + Instruction timer reload + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RLOAD + Inst. Timer reload value + 0 + 32 + read-write + + + + + INSTRUCTION_TIMER + The INSTRUCTION TIMER itself + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + INSTIM + INSTRUCTION TIMER 32-bit value + 0 + 32 + read-write + + + + + SECURE_COUNTER + Also known as SEC_CNT + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SECCNT + Secure Counter + 0 + 32 + read-write + + + + + STATUS + Status register (1 of 2) + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + NUMTOF + Number of Timeout Faults + 0 + 8 + read-only + + + NUMMISCOMPF + Number of Miscompare Faults + 8 + 8 + read-only + + + NUMILSEQF + Number of illegal sequence faults + 16 + 8 + read-only + + + CURST + Current State + 24 + 4 + read-only + + + + + STATUS2 + STATUS register (2 of 2) + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + NUMCNTF + Number (of) control faults + 0 + 8 + read-only + + + NUMILLSTF + Number (of) state faults + 8 + 8 + read-only + + + NUMILLA + Number of (illegal) address faults + 16 + 8 + read-only + + + + + FLAGS + Hardware flags + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TO_FLAG + Timeout flag + 0 + 1 + read-write + + + MISCOM_FLAG + Miscompare flag + 1 + 1 + read-write + + + SEQ_FLAG + Sequence flag + 2 + 1 + read-write + + + CNT_FLAG + Control (fault) flag + 3 + 1 + read-write + + + STATE_FLAG + State flag + 4 + 1 + read-write + + + ADDR_FLAG + Address flag + 5 + 1 + read-write + + + POR_FLAG + Power-on reset flag + 16 + 1 + read-write + + + + + PERSISTENT + Persistent (Ad. Hoc., quasi-NV) data storage + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSIS + 32 regs free for user SW to enjoy + 0 + 32 + read-write + + + + + START + Write address for issuing the START command. + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + STRT + Address of start command access + 0 + 32 + write-only + + + + + STOP + Write address for issuing the STOP command. + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + STP + Address of stop command access + 0 + 32 + write-only + + + + + RESTART + Write address for issuing the RESTART command. + 0x28 + 32 + write-only + 0 + 0xFFFFFFFF + + + RSTRT + Write address for issuing the RESTART command. + 0 + 32 + write-only + + + + + ADD + Write address for issuing the ADD command. + 0x2C + 32 + write-only + 0 + 0xFFFFFFFF + + + AD + Address of ADD command + 0 + 32 + write-only + + + + + ADD1 + Write address for issuing the ADD1 command. + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + AD1 + Address of ADD1 command. + 0 + 32 + write-only + + + + + ADD16 + Write address for issuing the ADD16 command. + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + AD16 + Address of ADD16 + 0 + 32 + write-only + + + + + ADD256 + Write address for issuing the ADD16 command. + 0x38 + 32 + write-only + 0 + 0xFFFFFFFF + + + AD256 + Address of ADD256 command + 0 + 32 + write-only + + + + + SUB + Write address for issuing the SUB command. + 0x3C + 32 + write-only + 0 + 0xFFFFFFFF + + + S0B + Address of SUB command. + 0 + 32 + write-only + + + + + SUB1 + Write address for issuing the SUB1 command. + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + S1B + Address of SUB1 command. + 0 + 32 + write-only + + + + + SUB16 + Write address for issuing the SUB16 command. + 0x44 + 32 + write-only + 0 + 0xFFFFFFFF + + + SB16 + Address of SUB16 command. + 0 + 32 + write-only + + + + + SUB256 + Write address for issuing the SUB256 command. + 0x48 + 32 + write-only + 0 + 0xFFFFFFFF + + + SB256 + Address of (you guessed it) SUB256 command. + 0 + 32 + write-only + + + + + + + USBFSH + USB0 Full-speed Host controller + USBFSH + 0x400A2000 + + 0 + 0x60 + registers + + + USB0_NEEDCLK + 27 + + + USB0 + 28 + + + + HCREVISION + BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) + 0 + 32 + read-only + 0x10 + 0xFF + + + REV + Revision. + 0 + 8 + read-only + + + + + HCCONTROL + Defines the operating modes of the HC + 0x4 + 32 + read-write + 0 + 0x7FF + + + CBSR + ControlBulkServiceRatio. + 0 + 2 + read-write + + + PLE + PeriodicListEnable. + 2 + 1 + read-write + + + IE + IsochronousEnable. + 3 + 1 + read-write + + + CLE + ControlListEnable. + 4 + 1 + read-write + + + BLE + BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + 5 + 1 + read-write + + + HCFS + HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. + 6 + 2 + read-write + + + IR + InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + 8 + 1 + read-write + + + RWC + RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + 9 + 1 + read-write + + + RWE + RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. + 10 + 1 + read-write + + + + + HCCOMMANDSTATUS + This register is used to receive the commands from the Host Controller Driver (HCD) + 0x8 + 32 + read-write + 0 + 0xCF + + + HCR + HostControllerReset This bit is set by HCD to initiate a software reset of HC. + 0 + 1 + read-write + + + CLF + ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + 1 + 1 + read-write + + + BLF + BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + 2 + 1 + read-write + + + OCR + OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + 3 + 1 + read-write + + + SOC + SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + 6 + 2 + read-write + + + + + HCINTERRUPTSTATUS + Indicates the status on various events that cause hardware interrupts by setting the appropriate bits + 0xC + 32 + read-write + 0 + 0xFFFFFC7F + + + SO + SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. + 0 + 1 + read-write + + + WDH + WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + 1 + 1 + read-write + + + SF + StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + 2 + 1 + read-write + + + RD + ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + 3 + 1 + read-write + + + UE + UnrecoverableError This bit is set when HC detects a system error not related to USB. + 4 + 1 + read-write + + + FNO + FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + 5 + 1 + read-write + + + RHSC + RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. + 6 + 1 + read-write + + + OC + OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + 10 + 22 + read-write + + + + + HCINTERRUPTENABLE + Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt + 0x10 + 32 + read-write + 0 + 0xC000007F + + + SO + Scheduling Overrun interrupt. + 0 + 1 + read-write + + + WDH + HcDoneHead Writeback interrupt. + 1 + 1 + read-write + + + SF + Start of Frame interrupt. + 2 + 1 + read-write + + + RD + Resume Detect interrupt. + 3 + 1 + read-write + + + UE + Unrecoverable Error interrupt. + 4 + 1 + read-write + + + FNO + Frame Number Overflow interrupt. + 5 + 1 + read-write + + + RHSC + Root Hub Status Change interrupt. + 6 + 1 + read-write + + + OC + Ownership Change interrupt. + 30 + 1 + read-write + + + MIE + Master Interrupt Enable. + 31 + 1 + read-write + + + + + HCINTERRUPTDISABLE + The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt + 0x14 + 32 + read-write + 0 + 0xC000007F + + + SO + Scheduling Overrun interrupt. + 0 + 1 + read-write + + + WDH + HcDoneHead Writeback interrupt. + 1 + 1 + read-write + + + SF + Start of Frame interrupt. + 2 + 1 + read-write + + + RD + Resume Detect interrupt. + 3 + 1 + read-write + + + UE + Unrecoverable Error interrupt. + 4 + 1 + read-write + + + FNO + Frame Number Overflow interrupt. + 5 + 1 + read-write + + + RHSC + Root Hub Status Change interrupt. + 6 + 1 + read-write + + + OC + Ownership Change interrupt. + 30 + 1 + read-write + + + MIE + A 0 written to this field is ignored by HC. + 31 + 1 + read-write + + + + + HCHCCA + Contains the physical address of the host controller communication area + 0x18 + 32 + read-write + 0 + 0xFFFFFF00 + + + HCCA + Base address of the Host Controller Communication Area. + 8 + 24 + read-write + + + + + HCPERIODCURRENTED + Contains the physical address of the current isochronous or interrupt endpoint descriptor + 0x1C + 32 + read-write + 0 + 0xFFFFFFF0 + + + PCED + The content of this register is updated by HC after a periodic ED is processed. + 4 + 28 + read-only + + + + + HCCONTROLHEADED + Contains the physical address of the first endpoint descriptor of the control list + 0x20 + 32 + read-write + 0 + 0xFFFFFFF0 + + + CHED + HC traverses the Control list starting with the HcControlHeadED pointer. + 4 + 28 + read-write + + + + + HCCONTROLCURRENTED + Contains the physical address of the current endpoint descriptor of the control list + 0x24 + 32 + read-write + 0 + 0xFFFFFFF0 + + + CCED + ControlCurrentED. + 4 + 28 + read-write + + + + + HCBULKHEADED + Contains the physical address of the first endpoint descriptor of the bulk list + 0x28 + 32 + read-write + 0 + 0xFFFFFFF0 + + + BHED + BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + 4 + 28 + read-write + + + + + HCBULKCURRENTED + Contains the physical address of the current endpoint descriptor of the bulk list + 0x2C + 32 + read-write + 0 + 0xFFFFFFF0 + + + BCED + BulkCurrentED This is advanced to the next ED after the HC has served the current one. + 4 + 28 + read-write + + + + + HCDONEHEAD + Contains the physical address of the last transfer descriptor added to the 'Done' queue + 0x30 + 32 + read-write + 0 + 0xFFFFFFF0 + + + DH + DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + 4 + 28 + read-only + + + + + HCFMINTERVAL + Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun + 0x34 + 32 + read-write + 0x2EDF + 0xFFFF3FFF + + + FI + FrameInterval This specifies the interval between two consecutive SOFs in bit times. + 0 + 14 + read-write + + + FSMPS + FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. + 16 + 15 + read-write + + + FIT + FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + 31 + 1 + read-write + + + + + HCFMREMAINING + A 14-bit counter showing the bit time remaining in the current frame + 0x38 + 32 + read-write + 0 + 0x80003FFF + + + FR + FrameRemaining This counter is decremented at each bit time. + 0 + 14 + read-only + + + FRT + FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. + 31 + 1 + read-only + + + + + HCFMNUMBER + Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD + 0x3C + 32 + read-write + 0 + 0xFFFF + + + FN + FrameNumber This is incremented when HcFmRemaining is re-loaded. + 0 + 16 + read-only + + + + + HCPERIODICSTART + Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list + 0x40 + 32 + read-write + 0 + 0x3FFF + + + PS + PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + 0 + 14 + read-write + + + + + HCLSTHRESHOLD + Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF + 0x44 + 32 + read-write + 0x628 + 0xFFF + + + LST + LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. + 0 + 12 + read-write + + + + + HCRHDESCRIPTORA + First of the two registers which describes the characteristics of the root hub + 0x48 + 32 + read-write + 0xFF000902 + 0xFF001FFF + + + NDP + NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + 0 + 8 + read-write + + + PSM + PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + 8 + 1 + read-write + + + NPS + NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + 9 + 1 + read-write + + + DT + DeviceType This bit specifies that the root hub is not a compound device. + 10 + 1 + read-write + + + OCPM + OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + 11 + 1 + read-write + + + NOCP + NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + 12 + 1 + read-write + + + POTPGT + PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. + 24 + 8 + read-write + + + + + HCRHDESCRIPTORB + Second of the two registers which describes the characteristics of the Root Hub + 0x4C + 32 + read-write + 0 + 0x3FFFFFFF + + + DR + DeviceRemovable Each bit is dedicated to a port of the Root Hub. + 0 + 16 + read-write + + + PPCM + PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. + 16 + 16 + read-write + + + + + HCRHSTATUS + This register is divided into two parts + 0x50 + 32 + read-write + 0 + 0x80038003 + + + LPS + (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. + 0 + 1 + read-write + + + OCI + OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + 1 + 1 + read-write + + + DRWE + (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. + 15 + 1 + read-write + + + LPSC + (read) LocalPowerStatusChange The root hub does not support the local power status feature. + 16 + 1 + read-write + + + OCIC + OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + 17 + 1 + read-write + + + CRWE + (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + 31 + 1 + read-write + + + + + HCRHPORTSTATUS + Controls and reports the port events on a per-port basis + 0x54 + 32 + read-write + 0 + 0x1F031F + + + CCS + (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + 0 + 1 + read-write + + + PES + (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + 1 + 1 + read-write + + + PSS + (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + 2 + 1 + read-write + + + POCI + (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. + 3 + 1 + read-write + + + PRS + (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + 4 + 1 + read-write + + + PPS + (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. + 8 + 1 + read-write + + + LSDA + (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + 9 + 1 + read-write + + + CSC + ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + 16 + 1 + read-write + + + PESC + PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + 17 + 1 + read-write + + + PSSC + PortSuspendStatusChange This bit is set when the full resume sequence is completed. + 18 + 1 + read-write + + + OCIC + PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + 19 + 1 + read-write + + + PRSC + PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + 20 + 1 + read-write + + + + + PORTMODE + Controls the port if it is attached to the host block or the device block + 0x5C + 32 + read-write + 0 + 0x10101 + + + ID + Port ID pin value. + 0 + 1 + read-write + + + ID_EN + Port ID pin pull-up enable. + 8 + 1 + read-write + + + DEV_ENABLE + 1: device 0: host. + 16 + 1 + read-write + + + + + + + USBHSH + USB1 High-speed Host Controller + USBHSH + 0x400A3000 + + 0 + 0x54 + registers + + + USB1 + 47 + + + USB1_NEEDCLK + 48 + + + + CAPLENGTH_CHIPID + This register contains the offset value towards the start of the operational register space and the version number of the IP block + 0 + 32 + read-only + 0x1010010 + 0xFFFF00FF + + + CAPLENGTH + Capability Length: This is used as an offset. + 0 + 8 + read-only + + + CHIPID + Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + 16 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x4 + 32 + read-only + 0x10011 + 0x1001F + + + N_PORTS + This register specifies the number of physical downstream ports implemented on this host controller. + 0 + 4 + read-only + + + PPC + This field indicates whether the host controller implementation includes port power control. + 4 + 1 + read-only + + + P_INDICATOR + This bit indicates whether the ports support port indicator control. + 16 + 1 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x8 + 32 + read-only + 0x20006 + 0xFFFFFFFF + + + LPMC + Link Power Management Capability. + 17 + 1 + read-only + + + + + FLADJ_FRINDEX + Frame Length Adjustment + 0xC + 32 + read-write + 0x20 + 0x3FFF003F + + + FLADJ + Frame Length Timing Value. + 0 + 6 + read-write + + + FRINDEX + Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + 16 + 14 + read-write + + + + + ATLPTD + Memory base address where ATL PTD0 is stored + 0x10 + 32 + read-write + 0 + 0xFFFFFFF0 + + + ATL_CUR + This indicates the current PTD that is used by the hardware when it is processing the ATL list. + 4 + 5 + read-write + + + ATL_BASE + Base address to be used by the hardware to find the start of the ATL list. + 9 + 23 + read-write + + + + + ISOPTD + Memory base address where ISO PTD0 is stored + 0x14 + 32 + read-write + 0 + 0xFFFFFFE0 + + + ISO_FIRST + This indicates the first PTD that is used by the hardware when it is processing the ISO list. + 5 + 5 + read-write + + + ISO_BASE + Base address to be used by the hardware to find the start of the ISO list. + 10 + 22 + read-write + + + + + INTPTD + Memory base address where INT PTD0 is stored + 0x18 + 32 + read-write + 0 + 0xFFFFFFE0 + + + INT_FIRST + This indicates the first PTD that is used by the hardware when it is processing the INT list. + 5 + 5 + read-write + + + INT_BASE + Base address to be used by the hardware to find the start of the INT list. + 10 + 22 + read-write + + + + + DATAPAYLOAD + Memory base address that indicates the start of the data payload buffers + 0x1C + 32 + read-write + 0 + 0xFFFF0000 + + + DAT_BASE + Base address to be used by the hardware to find the start of the data payload section. + 16 + 16 + read-write + + + + + USBCMD + USB Command register + 0x20 + 32 + read-write + 0 + 0x1F00078F + + + RS + Run/Stop: 1b = Run. + 0 + 1 + read-write + + + HCRESET + Host Controller Reset: This control bit is used by the software to reset the host controller. + 1 + 1 + read-write + + + FLS + Frame List Size: This field specifies the size of the frame list. + 2 + 2 + read-write + + + LHCR + Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. + 7 + 1 + read-write + + + ATL_EN + ATL List enabled. + 8 + 1 + read-write + + + ISO_EN + ISO List enabled. + 9 + 1 + read-write + + + INT_EN + INT List enabled. + 10 + 1 + read-write + + + HIRD + Host-Initiated Resume Duration. + 24 + 4 + read-write + + + LPM_RWU + bRemoteWake field. + 28 + 1 + read-write + + + + + USBSTS + USB Interrupt Status register + 0x24 + 32 + read-write + 0 + 0xF000C + + + PCD + Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. + 2 + 1 + read-write + + + FLR + Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. + 3 + 1 + read-write + + + ATL_IRQ + ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + 16 + 1 + read-write + + + ISO_IRQ + ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + 17 + 1 + read-write + + + INT_IRQ + INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + 18 + 1 + read-write + + + SOF_IRQ + SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + 19 + 1 + read-write + + + + + USBINTR + USB Interrupt Enable register + 0x28 + 32 + read-write + 0 + 0xF000C + + + PCDE + Port Change Detect Interrupt Enable: 1: enable 0: disable. + 2 + 1 + read-write + + + FLRE + Frame List Rollover Interrupt Enable: 1: enable 0: disable. + 3 + 1 + read-write + + + ATL_IRQ_E + ATL IRQ Enable bit: 1: enable 0: disable. + 16 + 1 + read-write + + + ISO_IRQ_E + ISO IRQ Enable bit: 1: enable 0: disable. + 17 + 1 + read-write + + + INT_IRQ_E + INT IRQ Enable bit: 1: enable 0: disable. + 18 + 1 + read-write + + + SOF_E + SOF Interrupt Enable bit: 1: enable 0: disable. + 19 + 1 + read-write + + + + + PORTSC1 + Port Status and Control register + 0x2C + 32 + read-write + 0 + 0xFFFFDFFF + + + CCS + Current Connect Status: Logic 1 indicates a device is present on the port. + 0 + 1 + read-write + + + CSC + Connect Status Change: Logic 1 means that the value of CCS has changed. + 1 + 1 + read-write + + + PED + Port Enabled/Disabled. + 2 + 1 + read-write + + + PEDC + Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + 3 + 1 + read-write + + + OCA + Over-current active: Logic 1 means that this port has an over-current condition. + 4 + 1 + read-write + + + OCC + Over-current change: Logic 1 means that the value of OCA has changed. + 5 + 1 + read-write + + + FPR + Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + 6 + 1 + read-write + + + SUSP + Suspend: Logic 1 means port is in the suspend state. + 7 + 1 + read-write + + + PR + Port Reset: Logic 1 means the port is in the reset state. + 8 + 1 + read-write + + + SUS_L1 + Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume. + 9 + 1 + read-write + + + LS + Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + 10 + 2 + read-only + + + PP + Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + 12 + 1 + read-write + + + PIC + Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. + 14 + 2 + read-write + + + PTC + Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + 16 + 4 + read-write + + + PSPD + Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + 20 + 2 + read-write + + + WOO + Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. + 22 + 1 + read-write + + + SUS_STAT + These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. + 23 + 2 + read-write + + + DEV_ADD + Device Address for LPM tokens. + 25 + 7 + read-write + + + + + ATLPTDD + Done map for each ATL PTD + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATL_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + ATLPTDS + Skip map for each ATL PTD + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATL_SKIP + When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. + 0 + 32 + read-write + + + + + ISOPTDD + Done map for each ISO PTD + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISO_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + ISOPTDS + Skip map for each ISO PTD + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + ISO_SKIP + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + INTPTDD + Done map for each INT PTD + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + INTPTDS + Skip map for each INT PTD + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_SKIP + When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. + 0 + 32 + read-write + + + + + LASTPTD + Marks the last PTD in the list for ISO, INT and ATL + 0x48 + 32 + read-write + 0 + 0x1F1F1F + + + ATL_LAST + If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + 0 + 5 + read-write + + + ISO_LAST + This indicates the last PTD in the ISO list. + 8 + 5 + read-write + + + INT_LAST + This indicates the last PTD in the INT list. + 16 + 5 + read-write + + + + + PORTMODE + Controls the port if it is attached to the host block or the device block + 0x50 + 32 + read-write + 0x40000 + 0xD0101 + + + DEV_ENABLE + If this bit is set to one, one of the ports will behave as a USB device. + 16 + 1 + read-write + + + SW_CTRL_PDCOM + This bit indicates if the PHY power-down input is controlled by software or by hardware. + 18 + 1 + read-write + + + SW_PDCOM + This bit is only used when SW_CTRL_PDCOM is set to 1b. + 19 + 1 + read-write + + + + + + + HASHCRYPT + Hash-Crypt peripheral + HASHCRYPT + 0x400A4000 + + 0 + 0xDC + registers + + + HASHCRYPT + 54 + + + + CTRL + Control register to enable and operate Hash and Crypto + 0 + 32 + read-write + 0 + 0x3337 + + + Mode + The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. + 0 + 3 + read-write + + + DISABLED + Disabled + 0 + + + SHA1 + SHA1 is enabled + 0x1 + + + SHA2_256 + SHA2-256 is enabled + 0x2 + + + AES + AES if available (see also CRYPTCFG register for more controls) + 0x4 + + + + + New_Hash + Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. + 4 + 1 + write-only + + + START + Starts a new Hash/Crypto and initializes the Digest/Result. + 0x1 + + + + + Reload + If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash Digest (e.g. when need to run AES) and then reload it later for continuation. + 5 + 1 + read-write + + + RELOAD + Allow RELOAD registers to be used. + 0x1 + + + + + DMA_I + Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). + 8 + 1 + read-write + + + NOT_USED + DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + 0 + + + PUSH + DMA will push in the data. + 0x1 + + + + + DMA_O + Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. + 9 + 1 + read-write + + + NOTUSED + DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + 0 + + + + + HASHSWPB + If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register. + 12 + 1 + read-write + + + AESFLUSH + Flushes the AES engine registers. This bit self clears. + 13 + 1 + write-only + + + NOFLUSH + Do not flush the AES engine registers. + 0 + + + FLUSH + Flush the AES engine registers. + 0x1 + + + + + + + STATUS + Indicates status of Hash peripheral. + 0x4 + 32 + read-write + 0x1500 + 0x3F3737 + + + WAITING + If 1, the block is waiting for more data to process. + 0 + 1 + read-only + + + NOT_WAITING + Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. + 0 + + + WAITING + Waiting for data to be written in (16 words) + 0x1 + + + + + DIGEST + For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. + 1 + 1 + read-only + + + NOT_READY + No Digest is ready + 0 + + + READY + Digest is ready. Application may read it or may write more data + 0x1 + + + + + ERROR + If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. + 2 + 1 + read-write + oneToClear + + + NO_ERROR + No error. + 0 + + + ERROR + An error occurred since last cleared (written 1 to clear). + 0x1 + + + + + FAULT + Indicates if an AES or PRNG fault has occurred + 3 + 1 + read-only + + + NO_FAULT + No AES or PRNG fault has occurred. + 0 + + + FAULT + An AES or PRNG fault has occurred. + 0x1 + + + + + NEEDKEY + Indicates the block wants the key to be written in (set along with WAITING) + 4 + 1 + read-only + + + NOT_NEED + No Key is needed and writes will not be treated as Key + 0 + + + NEED + Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + 0x1 + + + + + NEEDIV + Indicates the block wants an IV/NONE to be written in (set along with WAITING) + 5 + 1 + read-only + + + NOT_NEED + No IV/Nonce is needed, either because written already or because not needed. + 0 + + + NEED + IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + 0x1 + + + + + AESFAULT + AES fault status + 8 + 1 + read-only + + + NO_FAULT + No AES fault has occurred. + 0 + + + FAULT + An AES fault has occurred. + 0x1 + + + + + PRNGFAULT + PRNG fault status + 9 + 1 + read-only + + + NO_FAULT + No PRNG fault has occurred. + 0 + + + FAULT + A PRNG fault has occurred. + 0x1 + + + + + + + INTENSET + Write 1 to enable interrupts; reads back with which are set. + 0x8 + 32 + read-write + 0 + 0xF + + + WAITING + Indicates if should interrupt when waiting for data input. + 0 + 1 + read-write + + + NO_INTERRUPT + Will not interrupt when waiting. + 0 + + + INTERRUPT + Will interrupt when waiting + 0x1 + + + + + DIGEST + Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + 1 + 1 + read-write + + + NO_INTERRUPT + Will not interrupt when Digest is ready + 0 + + + INTERRUPT + Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + 0x1 + + + + + ERROR + Indicates if should interrupt on an ERROR (as defined in Status) + 2 + 1 + read-write + + + NO_INTERRUPT + Will not interrupt on Error. + 0 + + + INTERRUPT + Will interrupt on Error (until cleared). + 0x1 + + + + + FAULT + Indicates if should interrupt on an AES or PRNG fault as indicated in the STATUS register + 3 + 1 + read-write + + + NO_INTERRUPT + No interrupt on an AES or PRNG fault + 0 + + + INTERRUPT + Interrupt on an AES or PRNG fault + 0x1 + + + + + + + INTENCLR + Write 1 to clear interrupts. + 0xC + 32 + read-write + 0 + 0 + + + WAITING + Write 1 to clear mask. + 0 + 1 + read-write + oneToClear + + + DIGEST + Write 1 to clear mask. + 1 + 1 + read-write + oneToClear + + + ERROR + Write 1 to clear mask. + 2 + 1 + read-write + oneToClear + + + FAULT + Write 1 to clear mask. + 3 + 1 + read-write + oneToClear + + + + + MEMCTRL + Setup Master to access memory (if available) + 0x10 + 32 + read-write + 0 + 0x7FF0001 + + + MASTER + Enables mastering. + 0 + 1 + read-write + + + NOT_USED + Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + 0 + + + ENABLED + Mastering is enabled and DMA and INDATA should not be used. + 0x1 + + + + + COUNT + Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash. + 16 + 11 + read-write + + + + + MEMADDR + Address to start memory access from (if available). + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE + Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI. + 0 + 32 + read-write + + + + + INDATA + Input of 16 words at a time to load up buffer. + 0x20 + 32 + write-only + 0 + 0 + + + DATA + Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. + 0 + 32 + write-only + + + + + 7 + 0x4 + ALIAS[%s] + Aliases to allow writing words in a burst. + 0x24 + 32 + write-only + 0 + 0 + + + DATA + Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. + 0 + 32 + write-only + + + + + 8 + 0x4 + DIGEST0[%s] + Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + DIGEST + One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + 0 + 32 + read-only + + + + + CRYPTCFG + Crypto settings for AES and Salsa and ChaCha + 0x80 + 32 + read-write + 0 + 0xF31FFF + + + MSW1ST_OUT + If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + 0 + 1 + read-write + + + SWAPKEY + If 1, will Swap the key input (bytes in each word). + 1 + 1 + read-write + + + SWAPDAT + If 1, will SWAP the data and IV inputs (bytes in each word). + 2 + 1 + read-write + + + MSW1ST + If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration. + 3 + 1 + read-write + + + AESMODE + AES Cipher mode to use if plain AES + 4 + 2 + read-write + + + ECB + ECB - used as is + 0 + + + CBC + CBC mode (see details on IV/nonce) + 0x1 + + + CTR + CTR mode (see details on IV/nonce). See also AESCTRPOS. + 0x2 + + + + + AESDECRYPT + AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + 6 + 1 + read-write + + + ENCRYPT + Encrypt + 0 + + + DECRYPT + Decrypt + 0x1 + + + + + AESSECRET + Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. + 7 + 1 + read-write + + + NORMAL_WAY + User key provided in normal way + 0 + + + HIDDEN_WAY + Secret key provided in hidden way by HW + 0x1 + + + + + AESKEYSZ + Sets the AES key size + 8 + 2 + read-write + + + BITS_128 + 128 bit key + 0 + + + BITS_192 + 192 bit key + 0x1 + + + BITS_256 + 256 bit key + 0x2 + + + + + AESCTRPOS + Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on. + 10 + 3 + read-write + + + STREAMLAST + Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + 16 + 1 + read-write + + + + + CONFIG + Returns the configuration of this block in this chip - indicates what services are available. + 0x84 + 32 + read-write + 0 + 0 + + + DUAL + 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + 0 + 1 + read-only + + + DMA + 1 if DMA is connected + 1 + 1 + read-only + + + AHB + 1 if AHB Master is enabled + 3 + 1 + read-only + + + AES + 1 if AES 128 included + 6 + 1 + read-only + + + AESKEY + 1 if AES 192 and 256 also included + 7 + 1 + read-only + + + SECRET + 1 if AES Secret key available + 8 + 1 + read-only + + + + + LOCK + Lock register allows locking to the current security level or unlocking by the lock holding level. + 0x8C + 32 + read-write + 0 + 0xFFF3 + + + SECLOCK + Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. + 0 + 2 + read-write + + + UNLOCK + Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + 0 + + + LOCK + Locks to the current security level. AHB Master will issue requests at this level. + 0x1 + + + + + PATTERN + Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + 4 + 12 + read-write + + + + + 4 + 0x4 + MASK[%s] + Allows Application to write a random mask for ICB use. Normally only a new one on each system reset (including power up). + 0x90 + 32 + write-only + 0 + 0 + + + MASK + A random word. + 0 + 32 + write-only + + + + + 8 + 0x4 + RELOAD[%s] + The WO digest-reload registers may be written with a saved Hash digest, to allow continuation from where left off. These registers may only be written if the Reload field in CTRL is 1. If SHA1, only the 1st 5 are used. + 0xA0 + 32 + write-only + 0 + 0 + + + DIGEST + SHA Digest word to reload. + 0 + 32 + write-only + + + + + PRNG_SEED + PRNG random input value used as an entropy source + 0xD0 + 32 + write-only + 0 + 0xFFFFFFFF + + + PRNG_SEED + Random input value used as an entropy source + 0 + 32 + write-only + + + + + PRNG_OUT + Provide random number. + 0xD8 + 32 + read-only + 0 + 0 + + + PRNG_OUT + Provide random number. + 0 + 32 + read-only + + + + + + + CASPER + CASPER + CASPER + 0x400A5000 + + 0 + 0x84 + registers + + + CASER + 55 + + + + CTRL0 + Contains the offsets of AB and CD in the RAM. + 0 + 32 + read-write + 0 + 0x1FFD0005 + + + ABBPAIR + Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + 0 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + ABOFF + Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + 2 + 11 + read-write + + + CDBPAIR + Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + CDOFF + Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values + 18 + 11 + read-write + + + + + CTRL1 + Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. + 0x4 + 32 + read-write + 0 + 0xDFFDFFFF + + + ITER + Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + 0 + 8 + read-write + + + MODE + Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + 8 + 8 + read-write + + + RESBPAIR + Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + RESOFF + Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values + 18 + 11 + read-write + + + CSKIP + Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + 30 + 2 + read-write + + + NO_SKIP + No Skip + 0 + + + SKIP_IF_1 + Skip if Carry is 1 + 0x1 + + + SKIP_IF_0 + Skip if Carry is 0 + 0x2 + + + SET_AND_SKIP + Set CTRLOFF to CDOFF and Skip + 0x3 + + + + + + + LOADER + Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. + 0x8 + 32 + read-write + 0 + 0x1FFD00FF + + + COUNT + Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load + 0 + 8 + read-write + + + CTRLBPAIR + Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + CTRLOFF + DWord Offset of CTRL pair to load next. + 18 + 11 + read-write + + + + + STATUS + Indicates operational status and would contain the carry bit if used. + 0xC + 32 + read-write + 0 + 0x31 + + + DONE + Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + 0 + 1 + read-write + + + BUSY + Busy or just cleared + 0 + + + COMPLETED + Completed last operation + 0x1 + + + + + CARRY + Last carry value if operation produced a carry bit + 4 + 1 + read-only + + + NO_CARRY + Carry was 0 or no carry + 0 + + + CARRY + Carry was 1 + 0x1 + + + + + BUSY + Indicates if the accelerator is busy performing an operation + 5 + 1 + read-only + + + IDLE + Not busy - is idle + 0 + + + BUSY + Is busy + 0x1 + + + + + + + INTENSET + Sets interrupts + 0x10 + 32 + read-write + 0 + 0x1 + + + DONE + Set if the accelerator should interrupt when done. + 0 + 1 + read-write + + + NO_INTERRUPT + Do not interrupt when done + 0 + + + INTERRUPT + Interrupt when done + 0x1 + + + + + + + INTENCLR + Clears interrupts + 0x14 + 32 + read-write + 0 + 0x1 + + + DONE + Written to clear an interrupt set with INTENSET. + 0 + 1 + read-write + oneToClear + + + IGNORED + If written 0, ignored + 0 + + + NO_INTERRUPT + If written 1, do not Interrupt when done + 0x1 + + + + + + + INTSTAT + Interrupt status bits (mask of INTENSET and STATUS) + 0x18 + 32 + read-write + 0 + 0x1 + + + DONE + If set, interrupt is caused by accelerator being done. + 0 + 1 + read-only + + + NOT_CAUSED + Not caused by accelerator being done + 0 + + + CAUSED + Caused by accelerator being done + 0x1 + + + + + + + AREG + A register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + BREG + B register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + CREG + C register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + DREG + D register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES0 + Result register 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES1 + Result register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES2 + Result register 2 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES3 + Result register 3 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + MASK + Optional mask register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + 0 + 32 + read-write + + + + + REMASK + Optional re-mask register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + 0 + 32 + read-write + + + + + LOCK + Security lock register + 0x80 + 32 + read-write + 0 + 0x1FFFF + + + LOCK + Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + 0 + 1 + read-write + + + UNLOCK + unlock + 0 + + + LOCK + Lock to current security level + 0x1 + + + + + KEY + Must be written as 0x73D to change the register. + 4 + 13 + read-write + + + KWY_VALUE + If set during write, will allow lock or unlock + 0x73D + + + + + + + + + SECGPIO + General Purpose I/O (GPIO) + GPIO + 0x400A8000 + + 0 + 0x2484 + registers + + + + B0_0 + Byte pin registers for all port GPIO pins + 0 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_1 + Byte pin registers for all port GPIO pins + 0x1 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_2 + Byte pin registers for all port GPIO pins + 0x2 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_3 + Byte pin registers for all port GPIO pins + 0x3 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_4 + Byte pin registers for all port GPIO pins + 0x4 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_5 + Byte pin registers for all port GPIO pins + 0x5 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_6 + Byte pin registers for all port GPIO pins + 0x6 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_7 + Byte pin registers for all port GPIO pins + 0x7 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_8 + Byte pin registers for all port GPIO pins + 0x8 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_9 + Byte pin registers for all port GPIO pins + 0x9 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_10 + Byte pin registers for all port GPIO pins + 0xA + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_11 + Byte pin registers for all port GPIO pins + 0xB + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_12 + Byte pin registers for all port GPIO pins + 0xC + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_13 + Byte pin registers for all port GPIO pins + 0xD + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_14 + Byte pin registers for all port GPIO pins + 0xE + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_15 + Byte pin registers for all port GPIO pins + 0xF + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_16 + Byte pin registers for all port GPIO pins + 0x10 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_17 + Byte pin registers for all port GPIO pins + 0x11 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_18 + Byte pin registers for all port GPIO pins + 0x12 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_19 + Byte pin registers for all port GPIO pins + 0x13 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_20 + Byte pin registers for all port GPIO pins + 0x14 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_21 + Byte pin registers for all port GPIO pins + 0x15 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_22 + Byte pin registers for all port GPIO pins + 0x16 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_23 + Byte pin registers for all port GPIO pins + 0x17 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_24 + Byte pin registers for all port GPIO pins + 0x18 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_25 + Byte pin registers for all port GPIO pins + 0x19 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_26 + Byte pin registers for all port GPIO pins + 0x1A + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_27 + Byte pin registers for all port GPIO pins + 0x1B + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_28 + Byte pin registers for all port GPIO pins + 0x1C + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_29 + Byte pin registers for all port GPIO pins + 0x1D + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_30 + Byte pin registers for all port GPIO pins + 0x1E + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_31 + Byte pin registers for all port GPIO pins + 0x1F + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + W0_0 + Word pin registers for all port GPIO pins + 0x1000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_1 + Word pin registers for all port GPIO pins + 0x1004 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_2 + Word pin registers for all port GPIO pins + 0x1008 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_3 + Word pin registers for all port GPIO pins + 0x100C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_4 + Word pin registers for all port GPIO pins + 0x1010 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_5 + Word pin registers for all port GPIO pins + 0x1014 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_6 + Word pin registers for all port GPIO pins + 0x1018 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_7 + Word pin registers for all port GPIO pins + 0x101C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_8 + Word pin registers for all port GPIO pins + 0x1020 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_9 + Word pin registers for all port GPIO pins + 0x1024 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_10 + Word pin registers for all port GPIO pins + 0x1028 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_11 + Word pin registers for all port GPIO pins + 0x102C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_12 + Word pin registers for all port GPIO pins + 0x1030 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_13 + Word pin registers for all port GPIO pins + 0x1034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_14 + Word pin registers for all port GPIO pins + 0x1038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_15 + Word pin registers for all port GPIO pins + 0x103C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_16 + Word pin registers for all port GPIO pins + 0x1040 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_17 + Word pin registers for all port GPIO pins + 0x1044 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_18 + Word pin registers for all port GPIO pins + 0x1048 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_19 + Word pin registers for all port GPIO pins + 0x104C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_20 + Word pin registers for all port GPIO pins + 0x1050 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_21 + Word pin registers for all port GPIO pins + 0x1054 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_22 + Word pin registers for all port GPIO pins + 0x1058 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_23 + Word pin registers for all port GPIO pins + 0x105C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_24 + Word pin registers for all port GPIO pins + 0x1060 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_25 + Word pin registers for all port GPIO pins + 0x1064 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_26 + Word pin registers for all port GPIO pins + 0x1068 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_27 + Word pin registers for all port GPIO pins + 0x106C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_28 + Word pin registers for all port GPIO pins + 0x1070 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_29 + Word pin registers for all port GPIO pins + 0x1074 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_30 + Word pin registers for all port GPIO pins + 0x1078 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_31 + Word pin registers for all port GPIO pins + 0x107C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + DIR0 + Direction registers for all port GPIO pins + 0x2000 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIRP + Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. + 0 + 32 + read-write + + + + + MASK0 + Mask register for all port GPIO pins + 0x2080 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASKP + Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. + 0 + 32 + read-write + + + + + PIN0 + Port pin register for all port GPIO pins + 0x2100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PORT + Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. + 0 + 32 + read-write + + + + + MPIN0 + Masked port register for all port GPIO pins + 0x2180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MPORTP + Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. + 0 + 32 + read-write + + + + + SET0 + Write: Set register for port. Read: output bits for port + 0x2200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETP + Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. + 0 + 32 + read-write + + + + + CLR0 + Clear port for all port GPIO pins + 0x2280 + 32 + write-only + 0 + 0 + + + CLRP + Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. + 0 + 32 + write-only + + + + + NOT0 + Toggle port for all port GPIO pins + 0x2300 + 32 + write-only + 0 + 0 + + + NOTP + Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. + 0 + 32 + write-only + + + + + DIRSET0 + Set pin direction bits for port + 0x2380 + 32 + write-only + 0 + 0 + + + DIRSETP + Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. + 0 + 32 + write-only + + + + + DIRCLR0 + Clear pin direction bits for port + 0x2400 + 32 + write-only + 0 + 0 + + + DIRCLRP + Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. + 0 + 32 + write-only + + + + + DIRNOT0 + Toggle pin direction bits for port + 0x2480 + 32 + write-only + 0 + 0 + + + DIRNOTP + Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + 0 + 32 + write-only + + + + + + + AHB_SECURE_CTRL + AHB secure controller + AHB_SECURE_CTRL + 0x400AC000 + + 0 + 0x1000 + registers + + + + SEC_CTRL_FLASH_ROM_SLAVE_RULE + Security access rules for Flash and ROM slaves. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASH_RULE + Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + ROM_RULE + Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_FLASH_MEM_RULE0 + Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE0 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE1 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE2 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE3 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAMX_SLAVE_RULE + Security access rules for RAMX slaves. + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAMX_RULE + Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAMX_MEM_RULE0 + Security access rules for RAMX slaves. + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_SLAVE_RULE + Security access rules for RAM0 slaves. + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM0_RULE + Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_MEM_RULE0 + Security access rules for RAM0 slaves. + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_SLAVE_RULE + Security access rules for RAM1 slaves. + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM1_RULE + Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_MEM_RULE0 + Security access rules for RAM1 slaves. + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_SLAVE_RULE + Security access rules for RAM2 slaves. + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM2_RULE + Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_MEM_RULE0 + Security access rules for RAM2 slaves. + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_USB_HS_SLAVE_RULE + Security access rules for USB High speed RAM slaves. + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_USB_HS_RULE + Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_USB_HS_MEM_RULE + Security access rules for RAM_USB_HS. + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRAM_SECT_0_RULE + Address space: 0x2001_0000 - 0x2001_0FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_1_RULE + Address space: 0x2001_1000 - 0x2001_1FFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_2_RULE + Address space: 0x2001_2000 - 0x2001_2FFF + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_3_RULE + Address space: 0x2001_3000 - 0x2001_3FFF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE_SLAVE_RULE + Security access rules for both APB Bridges slaves. + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + APBBRIDGE0_RULE + Security access rules for the whole APB Bridge 0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + APBBRIDGE1_RULE + Security access rules for the whole APB Bridge 1 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SYSCON_RULE + System Configuration + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + IOCON_RULE + I/O Configuration + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GINT0_RULE + GPIO input Interrupt 0 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GINT1_RULE + GPIO input Interrupt 1 + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PINT_RULE + Pin Interrupt and Pattern match + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SEC_PINT_RULE + Secure Pin Interrupt and Pattern match + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + INPUTMUX_RULE + Peripheral input multiplexing + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTIMER0_RULE + Standard counter/Timer 0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER1_RULE + Standard counter/Timer 1 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + WWDT_RULE + Windiwed wtachdog Timer + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MRT_RULE + Multi-rate Timer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + UTICK_RULE + Micro-Timer + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ANACTRL_RULE + Analog Modules controller + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PMC_RULE + Power Management Controller + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SYSCTRL_RULE + System Controller + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SPI_FILTER_RULE + SPI FILTER control + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTIMER2_RULE + Standard counter/Timer 2 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER3_RULE + Standard counter/Timer 3 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER4_RULE + Standard counter/Timer 4 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RTC_RULE + Real Time Counter + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + OSEVENT_RULE + OS Event Timer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASH_CTRL_RULE + Flash Controller + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PRINCE_RULE + Prince + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + USBHPHY_RULE + USB High Speed Phy controller + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RNG_RULE + True Random Number Generator + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PUF_RULE + PUF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PLU_RULE + Programmable Look-Up logic + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB_PORT7_SLAVE0_RULE + Security access rules for AHB peripherals. + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA0_RULE + DMA Controller + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FS_USB_DEV_RULE + USB Full-speed device + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SCT_RULE + SCTimer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM0_RULE + Flexcomm interface 0 + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM1_RULE + Flexcomm interface 1 + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB_PORT7_SLAVE1_RULE + Security access rules for AHB peripherals. + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXCOMM2_RULE + Flexcomm interface 2 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM3_RULE + Flexcomm interface 3 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM4_RULE + Flexcomm interface 4 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GPIO0_RULE + High Speed GPIO + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB_PORT8_SLAVE0_RULE + Security access rules for AHB peripherals. + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + USB_HS_DEV_RULE + USB high Speed device registers + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CRC_RULE + CRC engine + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM5_RULE + Flexcomm interface 5 + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM6_RULE + Flexcomm interface 6 + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB_PORT8_SLAVE1_RULE + Security access rules for AHB peripherals. + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXCOMM7_RULE + Flexcomm interface 7 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + DBG_MAILBOX_RULE + Debug mailbox (aka ISP-AP) + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CAN0_RULE + CAN-FD + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HS_LSPI_RULE + High Speed SPI + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB_PORT9_SLAVE0_RULE + Security access rules for AHB peripherals. + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_RULE + ADC + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USB_FS_HOST_RULE + USB Full Speed Host registers. + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USB_HS_HOST_RULE + USB High speed host registers + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HASH_RULE + SHA-2 crypto registers + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CASPER_RULE + RSA/ECC crypto accelerator + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + DMA1_RULE + DMA Controller (Secure) + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB_PORT9_SLAVE1_RULE + Security access rules for AHB peripherals. + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO1_RULE + Secure High Speed GPIO + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_RULE + AHB Secure Controller + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB_SEC_CTRL_MEM_RULE + Security access rules for AHB_SEC_CTRL_AHB. + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + AHB_SEC_CTRL_SECT_0_RULE + Address space: 0x400A_0000 - 0x400A_CFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_1_RULE + Address space: 0x400A_D000 - 0x400A_DFFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_2_RULE + Address space: 0x400A_E000 - 0x400A_EFFF + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_3_RULE + Address space: 0x400A_F000 - 0x400A_FFFF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + 10 + 0x4 + sec_vio_addr[%s] + most recent security violation address for AHB layer n + 0xE00 + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_VIO_ADDR + security violation address for AHB layer + 0 + 32 + read-only + + + + + 10 + 0x4 + sec_vio_misc_info[%s] + most recent security violation miscellaneous information for AHB layer n + 0xE80 + 32 + read-only + 0 + 0xFF3 + + + SEC_VIO_INFO_WRITE + security violation access read/write indicator. + 0 + 1 + read-only + + + READ + Read access. + 0 + + + WRITE + Write access. + 0x1 + + + + + SEC_VIO_INFO_DATA_ACCESS + security violation access data/code indicator. + 1 + 1 + read-only + + + CODE + Code access. + 0 + + + DATA + Data access. + 0x1 + + + + + SEC_VIO_INFO_MASTER_SEC_LEVEL + bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + 4 + 4 + read-only + + + SEC_VIO_INFO_MASTER + security violation master number + 8 + 4 + read-only + + + VALUE_0 + CPU0 Code. + 0 + + + VALUE_1 + CPU0 System. + 0x1 + + + VALUE_4 + USB-HS Device. + 0x4 + + + VALUE_5 + SDMA0. + 0x5 + + + VALUE_10 + HASH. + 0xA + + + VALUE_11 + USB-FS Host. + 0xB + + + VALUE_12 + SDMA1. + 0xC + + + VALUE_13 + CAN-FD. + 0xD + + + + + + + SEC_VIO_INFO_VALID + security violation address/information registers valid flags + 0xF00 + 32 + read-write + 0 + 0x3FFFF + + + VIO_INFO_VALID0 + violation information valid flag for AHB port 0. Write 1 to clear. + 0 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID1 + violation information valid flag for AHB port 1. Write 1 to clear. + 1 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID2 + violation information valid flag for AHB port 2. Write 1 to clear. + 2 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID3 + violation information valid flag for AHB port 3. Write 1 to clear. + 3 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID4 + violation information valid flag for AHB port 4. Write 1 to clear. + 4 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID5 + violation information valid flag for AHB port 5. Write 1 to clear. + 5 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID6 + violation information valid flag for AHB port 6. Write 1 to clear. + 6 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID7 + violation information valid flag for AHB port 7. Write 1 to clear. + 7 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID8 + violation information valid flag for AHB port 8. Write 1 to clear. + 8 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID9 + violation information valid flag for AHB port 9. Write 1 to clear. + 9 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + + + SEC_GPIO_MASK0 + Secure GPIO mask for port 0 pins. + 0xF80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PIO0_PIN0_SEC_MASK + Secure mask for pin P0_0 + 0 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN1_SEC_MASK + Secure mask for pin P0_1 + 1 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN2_SEC_MASK + Secure mask for pin P0_2 + 2 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN3_SEC_MASK + Secure mask for pin P0_3 + 3 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN4_SEC_MASK + Secure mask for pin P0_4 + 4 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN5_SEC_MASK + Secure mask for pin P0_5 + 5 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN6_SEC_MASK + Secure mask for pin P0_6 + 6 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN7_SEC_MASK + Secure mask for pin P0_7 + 7 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN8_SEC_MASK + Secure mask for pin P0_8 + 8 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN9_SEC_MASK + Secure mask for pin P0_9 + 9 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN10_SEC_MASK + Secure mask for pin P0_10 + 10 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN11_SEC_MASK + Secure mask for pin P0_11 + 11 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN12_SEC_MASK + Secure mask for pin P0_12 + 12 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN13_SEC_MASK + Secure mask for pin P0_13 + 13 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN14_SEC_MASK + Secure mask for pin P0_14 + 14 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN15_SEC_MASK + Secure mask for pin P0_15 + 15 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN16_SEC_MASK + Secure mask for pin P0_16 + 16 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN17_SEC_MASK + Secure mask for pin P0_17 + 17 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN18_SEC_MASK + Secure mask for pin P0_18 + 18 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN19_SEC_MASK + Secure mask for pin P0_19 + 19 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN20_SEC_MASK + Secure mask for pin P0_20 + 20 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN21_SEC_MASK + Secure mask for pin P0_21 + 21 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN22_SEC_MASK + Secure mask for pin P0_22 + 22 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN23_SEC_MASK + Secure mask for pin P0_23 + 23 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN24_SEC_MASK + Secure mask for pin P0_24 + 24 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN25_SEC_MASK + Secure mask for pin P0_25 + 25 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN26_SEC_MASK + Secure mask for pin P0_26 + 26 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN27_SEC_MASK + Secure mask for pin P0_27 + 27 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN28_SEC_MASK + Secure mask for pin P0_28 + 28 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN29_SEC_MASK + Secure mask for pin P0_29 + 29 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN30_SEC_MASK + Secure mask for pin P0_30 + 30 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN31_SEC_MASK + Secure mask for pin P0_31 + 31 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + + + SEC_GPIO_MASK1 + Secure GPIO mask for port 1 pins. + 0xF84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PIO1_PIN0_SEC_MASK + Secure mask for pin P1_0 + 0 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN1_SEC_MASK + Secure mask for pin P1_1 + 1 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN2_SEC_MASK + Secure mask for pin P1_2 + 2 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN3_SEC_MASK + Secure mask for pin P1_3 + 3 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN4_SEC_MASK + Secure mask for pin P1_4 + 4 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN5_SEC_MASK + Secure mask for pin P1_5 + 5 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN6_SEC_MASK + Secure mask for pin P1_6 + 6 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN7_SEC_MASK + Secure mask for pin P1_7 + 7 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN8_SEC_MASK + Secure mask for pin P1_8 + 8 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN9_SEC_MASK + Secure mask for pin P1_9 + 9 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN10_SEC_MASK + Secure mask for pin P1_10 + 10 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN11_SEC_MASK + Secure mask for pin P1_11 + 11 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN12_SEC_MASK + Secure mask for pin P1_12 + 12 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN13_SEC_MASK + Secure mask for pin P1_13 + 13 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN14_SEC_MASK + Secure mask for pin P1_14 + 14 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN15_SEC_MASK + Secure mask for pin P1_15 + 15 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN16_SEC_MASK + Secure mask for pin P1_16 + 16 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN17_SEC_MASK + Secure mask for pin P1_17 + 17 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN18_SEC_MASK + Secure mask for pin P1_18 + 18 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN19_SEC_MASK + Secure mask for pin P1_19 + 19 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN20_SEC_MASK + Secure mask for pin P1_20 + 20 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN21_SEC_MASK + Secure mask for pin P1_21 + 21 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN22_SEC_MASK + Secure mask for pin P1_22 + 22 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN23_SEC_MASK + Secure mask for pin P1_23 + 23 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN24_SEC_MASK + Secure mask for pin P1_24 + 24 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN25_SEC_MASK + Secure mask for pin P1_25 + 25 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN26_SEC_MASK + Secure mask for pin P1_26 + 26 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN27_SEC_MASK + Secure mask for pin P1_27 + 27 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN28_SEC_MASK + Secure mask for pin P1_28 + 28 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN29_SEC_MASK + Secure mask for pin P1_29 + 29 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN30_SEC_MASK + Secure mask for pin P1_30 + 30 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN31_SEC_MASK + Secure mask for pin P1_31 + 31 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + + + SEC_MASK_LOCK + Security General Purpose register access control. + 0xFBC + 32 + read-write + 0xAAA + 0xFFF + + + SEC_GPIO_MASK0_LOCK + SEC_GPIO_MASK0 register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + SEC_GPIO_MASK1_LOCK + SEC_GPIO_MASK1 register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MASTER_SEC_LEVEL + master secure level register + 0xFD0 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + USBFSD + USB Full Speed Device. + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDMA0 + System DMA 0. + 10 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HASH + Hash. + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USBFSH + USB Full speed Host. + 22 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDMA1 + System DMA 1 security level. + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CANFD + CAN FD. + 26 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MASTER_SEC_LEVEL_LOCK + MASTER_SEC_LEVEL write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MASTER_SEC_ANTI_POL_REG + master secure level anti-pole register + 0xFD4 + 32 + read-write + 0xBFFFFFFF + 0xFFFFFFFF + + + USBFSD + USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + 8 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDMA0 + System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + 10 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + HASH + Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + 20 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + USBFSH + USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + 22 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDMA1 + System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + 24 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + CANFD + CAN FD. Must be equal to NOT(MASTER_SEC_LEVEL.CANFD) + 26 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + MASTER_SEC_LEVEL_ANTIPOL_LOCK + MASTER_SEC_ANTI_POL_REG register write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + CPU0_LOCK_REG + Miscalleneous control signals for in Cortex M33 (CPU0) + 0xFEC + 32 + read-write + 0x800002AA + 0xC00003FF + + + LOCK_NS_VTOR + Cortex M33 (CPU0) VTOR_NS register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_NS_MPU + Cortex M33 (CPU0) non-secure MPU register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_S_VTAIRCR + Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + 4 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_S_MPU + Cortex M33 (CPU0) Secure MPU registers write-lock. + 6 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_SAU + Cortex M33 (CPU0) SAU registers write-lock. + 8 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + CPU0_LOCK_REG_LOCK + CPU0_LOCK_REG write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MISC_CTRL_DP_REG + secure control duplicate register + 0xFF8 + 32 + read-write + 0xAAAA + 0xFFFF + + + WRITE_LOCK + Write lock. + 0 + 2 + read-write + + + RESTRICTED + Restricted mode. + 0x1 + + + ACCESSIBLE + Secure control registers can be written. + 0x2 + + + + + ENABLE_SECURE_CHECKING + Enable secure check for AHB matrix. + 2 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_S_PRIV_CHECK + Enable secure privilege check for AHB matrix. + 4 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_NS_PRIV_CHECK + Enable non-secure privilege check for AHB matrix. + 6 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + DISABLE_VIOLATION_ABORT + Disable secure violation abort. + 8 + 2 + read-write + + + DISABLE + Disable abort fort secure checker. + 0x1 + + + ENABLE + Enable abort fort secure checker. + 0x2 + + + + + DISABLE_SIMPLE_MASTER_STRICT_MODE + Disable simple master strict mode. + 10 + 2 + read-write + + + TIER_MODE + Simple master in tier mode. + 0x1 + + + STRICT_MODE + Simple master in strict mode. + 0x2 + + + + + DISABLE_SMART_MASTER_STRICT_MODE + Disable smart master strict mode. + 12 + 2 + read-write + + + TIER_MODE + Smart master in tier mode. + 0x1 + + + STRICT_MODE + Smart master in strict mode. + 0x2 + + + + + IDAU_ALL_NS + Disable IDAU. + 14 + 2 + read-write + + + DISABLE + IDAU is disable. + 0x1 + + + ENABLE + IDAU is enabled. + 0x2 + + + + + + + MISC_CTRL_REG + secure control register + 0xFFC + 32 + read-write + 0xAAAA + 0xFFFF + + + WRITE_LOCK + Write lock. + 0 + 2 + read-write + + + RESTRICTED + Restricted mode. + 0x1 + + + ACCESSIBLE + Secure control registers can be written. + 0x2 + + + + + ENABLE_SECURE_CHECKING + Enable secure check for AHB matrix. + 2 + 2 + read-write + + + ENABLE + Enabled (restricted mode) + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_S_PRIV_CHECK + Enable secure privilege check for AHB matrix. + 4 + 2 + read-write + + + ENABLE + Enabled (restricted mode) + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_NS_PRIV_CHECK + Enable non-secure privilege check for AHB matrix. + 6 + 2 + read-write + + + ENABLE + Enabled (restricted mode) + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + DISABLE_VIOLATION_ABORT + Disable secure violation abort. + 8 + 2 + read-write + + + DISABLE + Disable abort fort secure checker. + 0x1 + + + ENABLE + Enable abort fort secure checker. + 0x2 + + + + + DISABLE_SIMPLE_MASTER_STRICT_MODE + Disable simple master strict mode. + 10 + 2 + read-write + + + TIER_MODE + Simple master in tier mode. + 0x1 + + + STRICT_MODE + Simple master in strict mode. + 0x2 + + + + + DISABLE_SMART_MASTER_STRICT_MODE + Disable smart master strict mode. + 12 + 2 + read-write + + + TIER_MODE + Smart master in tier mode. + 0x1 + + + STRICT_MODE + Smart master in strict mode. + 0x2 + + + + + IDAU_ALL_NS + Disable IDAU. + 14 + 2 + read-write + + + DISABLE + IDAU is disable. + 0x1 + + + ENABLE + IDAU is enabled. + 0x2 + + + + + + + + + SCnSCB + no description available + SCNSCB + 0xE000E000 + + 0 + 0x10 + registers + + + + CPPWR + Coprocessor Power Control Register + 0xC + 32 + read-write + 0 + 0 + + + SU0 + State UNKNOWN 0. + 0 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS0 + State UNKNOWN Secure only 0. + 1 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU0 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU0 field is only accessible from the Secure state. + 0x1 + + + + + SU1 + State UNKNOWN 1. + 2 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS1 + State UNKNOWN Secure only 1. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU2 + State UNKNOWN 2. + 4 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS2 + State UNKNOWN Secure only 2. + 5 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU2 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU2 field is only accessible from the Secure state. + 0x1 + + + + + SU3 + State UNKNOWN 3. + 6 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS3 + State UNKNOWN Secure only 3. + 7 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU3 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU3 field is only accessible from the Secure state. + 0x1 + + + + + SU4 + State UNKNOWN 4. + 8 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS4 + State UNKNOWN Secure only 4. + 9 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU4 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU4 field is only accessible from the Secure state. + 0x1 + + + + + SU5 + State UNKNOWN 5. + 10 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS5 + State UNKNOWN Secure only 5. + 11 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU5 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU5 field is only accessible from the Secure state. + 0x1 + + + + + SU6 + State UNKNOWN 6. + 12 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS6 + State UNKNOWN Secure only 6. + 13 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU6 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU6 field is only accessible from the Secure state. + 0x1 + + + + + SU7 + State UNKNOWN 7. + 14 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS7 + State UNKNOWN Secure only 7. + 15 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU10 + State UNKNOWN 10. + 20 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The floating-point state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The floating-point state is permitted to become UNKNOWN + 0x1 + + + + + SUS10 + State UNKNOWN Secure only 10. + 21 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU10 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU10 field is only accessible from the Secure state. + 0x1 + + + + + SU11 + State UNKNOWN 11. + 22 + 1 + read-write + + + SUS11 + State UNKNOWN Secure only 11. + 23 + 1 + read-write + + + + + + + NVIC + no description available + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + + 16 + 0x4 + ISER[%s] + Interrupt Set Enable Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA0 + Interrupt set-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA1 + Interrupt set-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA2 + Interrupt set-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA3 + Interrupt set-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA4 + Interrupt set-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA5 + Interrupt set-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA6 + Interrupt set-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA7 + Interrupt set-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA8 + Interrupt set-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA9 + Interrupt set-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA10 + Interrupt set-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA11 + Interrupt set-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA12 + Interrupt set-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA13 + Interrupt set-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA14 + Interrupt set-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA15 + Interrupt set-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA16 + Interrupt set-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA17 + Interrupt set-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA18 + Interrupt set-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA19 + Interrupt set-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA20 + Interrupt set-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA21 + Interrupt set-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA22 + Interrupt set-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA23 + Interrupt set-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA24 + Interrupt set-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA25 + Interrupt set-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA26 + Interrupt set-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA27 + Interrupt set-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA28 + Interrupt set-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA29 + Interrupt set-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA30 + Interrupt set-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA31 + Interrupt set-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ICER[%s] + Interrupt Clear Enable Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA0 + Interrupt clear-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA1 + Interrupt clear-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA2 + Interrupt clear-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA3 + Interrupt clear-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA4 + Interrupt clear-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA5 + Interrupt clear-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA6 + Interrupt clear-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA7 + Interrupt clear-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA8 + Interrupt clear-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA9 + Interrupt clear-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA10 + Interrupt clear-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA11 + Interrupt clear-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA12 + Interrupt clear-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA13 + Interrupt clear-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA14 + Interrupt clear-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA15 + Interrupt clear-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA16 + Interrupt clear-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA17 + Interrupt clear-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA18 + Interrupt clear-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA19 + Interrupt clear-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA20 + Interrupt clear-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA21 + Interrupt clear-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA22 + Interrupt clear-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA23 + Interrupt clear-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA24 + Interrupt clear-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA25 + Interrupt clear-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA26 + Interrupt clear-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA27 + Interrupt clear-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA28 + Interrupt clear-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA29 + Interrupt clear-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA30 + Interrupt clear-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA31 + Interrupt clear-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ISPR[%s] + Interrupt Set Pending Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND0 + Interrupt set-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND1 + Interrupt set-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND2 + Interrupt set-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND3 + Interrupt set-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND4 + Interrupt set-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND5 + Interrupt set-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND6 + Interrupt set-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND7 + Interrupt set-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND8 + Interrupt set-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND9 + Interrupt set-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND10 + Interrupt set-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND11 + Interrupt set-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND12 + Interrupt set-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND13 + Interrupt set-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND14 + Interrupt set-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND15 + Interrupt set-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND16 + Interrupt set-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND17 + Interrupt set-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND18 + Interrupt set-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND19 + Interrupt set-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND20 + Interrupt set-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND21 + Interrupt set-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND22 + Interrupt set-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND23 + Interrupt set-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND24 + Interrupt set-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND25 + Interrupt set-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND26 + Interrupt set-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND27 + Interrupt set-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND28 + Interrupt set-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND29 + Interrupt set-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND30 + Interrupt set-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND31 + Interrupt set-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + + + 16 + 0x4 + ICPR[%s] + Interrupt Clear Pending Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND0 + Interrupt clear-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND1 + Interrupt clear-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND2 + Interrupt clear-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND3 + Interrupt clear-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND4 + Interrupt clear-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND5 + Interrupt clear-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND6 + Interrupt clear-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND7 + Interrupt clear-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND8 + Interrupt clear-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND9 + Interrupt clear-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND10 + Interrupt clear-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND11 + Interrupt clear-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND12 + Interrupt clear-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND13 + Interrupt clear-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND14 + Interrupt clear-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND15 + Interrupt clear-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND16 + Interrupt clear-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND17 + Interrupt clear-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND18 + Interrupt clear-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND19 + Interrupt clear-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND20 + Interrupt clear-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND21 + Interrupt clear-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND22 + Interrupt clear-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND23 + Interrupt clear-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND24 + Interrupt clear-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND25 + Interrupt clear-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND26 + Interrupt clear-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND27 + Interrupt clear-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND28 + Interrupt clear-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND29 + Interrupt clear-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND30 + Interrupt clear-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND31 + Interrupt clear-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + + + 16 + 0x4 + IABR[%s] + Interrupt Active Bit Register + 0x200 + 32 + read-write + 0 + 0 + + + ACTIVE0 + Active state bits. + 0 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE1 + Active state bits. + 1 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE2 + Active state bits. + 2 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE3 + Active state bits. + 3 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE4 + Active state bits. + 4 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE5 + Active state bits. + 5 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE6 + Active state bits. + 6 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE7 + Active state bits. + 7 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE8 + Active state bits. + 8 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE9 + Active state bits. + 9 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE10 + Active state bits. + 10 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE11 + Active state bits. + 11 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE12 + Active state bits. + 12 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE13 + Active state bits. + 13 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE14 + Active state bits. + 14 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE15 + Active state bits. + 15 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE16 + Active state bits. + 16 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE17 + Active state bits. + 17 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE18 + Active state bits. + 18 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE19 + Active state bits. + 19 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE20 + Active state bits. + 20 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE21 + Active state bits. + 21 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE22 + Active state bits. + 22 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE23 + Active state bits. + 23 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE24 + Active state bits. + 24 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE25 + Active state bits. + 25 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE26 + Active state bits. + 26 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE27 + Active state bits. + 27 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE28 + Active state bits. + 28 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE29 + Active state bits. + 29 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE30 + Active state bits. + 30 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE31 + Active state bits. + 31 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + + + 16 + 0x4 + ITNS[%s] + Interrupt Target Non-secure Register + 0x280 + 32 + read-write + 0 + 0 + + + INTS0 + Interrupt Targets Non-secure bits. + 0 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS1 + Interrupt Targets Non-secure bits. + 1 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS2 + Interrupt Targets Non-secure bits. + 2 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS3 + Interrupt Targets Non-secure bits. + 3 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS4 + Interrupt Targets Non-secure bits. + 4 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS5 + Interrupt Targets Non-secure bits. + 5 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS6 + Interrupt Targets Non-secure bits. + 6 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS7 + Interrupt Targets Non-secure bits. + 7 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS8 + Interrupt Targets Non-secure bits. + 8 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS9 + Interrupt Targets Non-secure bits. + 9 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS10 + Interrupt Targets Non-secure bits. + 10 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS11 + Interrupt Targets Non-secure bits. + 11 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS12 + Interrupt Targets Non-secure bits. + 12 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS13 + Interrupt Targets Non-secure bits. + 13 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS14 + Interrupt Targets Non-secure bits. + 14 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS15 + Interrupt Targets Non-secure bits. + 15 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS16 + Interrupt Targets Non-secure bits. + 16 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS17 + Interrupt Targets Non-secure bits. + 17 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS18 + Interrupt Targets Non-secure bits. + 18 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS19 + Interrupt Targets Non-secure bits. + 19 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS20 + Interrupt Targets Non-secure bits. + 20 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS21 + Interrupt Targets Non-secure bits. + 21 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS22 + Interrupt Targets Non-secure bits. + 22 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS23 + Interrupt Targets Non-secure bits. + 23 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS24 + Interrupt Targets Non-secure bits. + 24 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS25 + Interrupt Targets Non-secure bits. + 25 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS26 + Interrupt Targets Non-secure bits. + 26 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS27 + Interrupt Targets Non-secure bits. + 27 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS28 + Interrupt Targets Non-secure bits. + 28 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS29 + Interrupt Targets Non-secure bits. + 29 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS30 + Interrupt Targets Non-secure bits. + 30 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS31 + Interrupt Targets Non-secure bits. + 31 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + + + 120 + 0x4 + IPR[%s] + Interrupt Priority Register + 0x300 + 32 + read-write + 0 + 0 + + + PRI_0 + no description available + 0 + 8 + read-write + + + PRI_1 + no description available + 8 + 8 + read-write + + + PRI_2 + no description available + 16 + 8 + read-write + + + PRI_3 + no description available + 24 + 8 + read-write + + + + + STIR + Software Trigger Interrupt Register + 0xE00 + 32 + write-only + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-479. + 0 + 9 + write-only + + + + + + + SCB + no description available + SCB + 0xE000ED00 + + 0 + 0x90 + registers + + + + AIRCR + Application Interrupt and Reset Control Register + 0xC + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTCLRACTIVE + Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states. + 1 + 1 + write-only + + + SYSRESETREQ + System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI. + 2 + 1 + read-write + + + NO_REQUEST + Do not request a system reset. + 0 + + + REQUEST_RESET + Request a system reset. + 0x1 + + + + + SYSRESETREQS + System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + SYSRESETREQ functionality is available to both Security states. + 0 + + + SECURE_ONLY + SYSRESETREQ functionality is only available to Secure state. + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states + 8 + 3 + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state. + 13 + 1 + read-write + + + SECURE + BusFault, HardFault, and NMI are Secure. + 0 + + + NON_SECURE + BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + 0x1 + + + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state. + 14 + 1 + read-write + + + SAME_PRIORITY + Priority ranges of Secure and Non-secure exceptions are identical + 0 + + + SECURE_PRIORITIZED + Non-secure exceptions are de-prioritized + 0x1 + + + + + ENDIANNESS + Data endianness bit. This bit is not banked between Security states. + 15 + 1 + read-only + + + LITTLE_ENDIAN + Little-endian. + 0 + + + BIG_ENDIAN + Big-endian + 0x1 + + + + + VECTKEY + Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states. + 16 + 16 + read-only + + + + + SCR + The SCR controls features of entry to and exit from low-power state. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. + 1 + 1 + read-write + + + NOT_SLEEP + Do not sleep when returning to Thread mode. + 0 + + + SLEEP + Enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states. + 2 + 1 + read-write + + + SLEEP + Sleep. + 0 + + + DEEP_SLEEP + Deep sleep. + 0x1 + + + + + SLEEPDEEPS + Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SLEEPDEEP bit is accessible from both Security states. + 0 + + + SECURE_ONLY + The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. + 0x1 + + + + + SEVONPEND + Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. + 4 + 1 + read-write + + + EXCLUDE_DISABLED_INTERRUPTS + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 0 + + + INCLUDE_DISABLED_INTERRUPTS + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + SHCSR + System Handler Control and State Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active. + 0 + 1 + read-write + + + NOT_ACTIVE + MemManage exception is not active. + 0 + + + ACTIVE + MemManage exception is active. + 0x1 + + + + + BUSFAULTACT + BusFault exception active. + 1 + 1 + read-write + + + NOT_ACTIVE + BusFault exception is not active. + 0 + + + ACTIVE + BusFault exception is active. + 0x1 + + + + + HARDFAULTACT + HardFault exception active. + 2 + 1 + read-write + + + NOT_ACTIVE + HardFault exception is not active. + 0 + + + ACTIVE + HardFault exception is active. + 0x1 + + + + + USGFAULTACT + UsageFault exception active. + 3 + 1 + read-write + + + NOT_ACTIVE + UsageFault exception is not active. + 0 + + + ACTIVE + UsageFault exception is active. + 0x1 + + + + + SECUREFAULTACT + SecureFault exception active + 4 + 1 + read-write + + + NOT_ACTIVE + SecureFault exception is not active. + 0 + + + ACTIVE + SecureFault exception is active. + 0x1 + + + + + NMIACT + NMI exception active. + 5 + 1 + read-write + + + NOT_ACTIVE + NMI exception is not active. + 0 + + + ACTIVE + NMI exception is active. + 0x1 + + + + + SVCALLACT + SVCall active. + 7 + 1 + read-write + + + NOT_ACTIVE + SVCall exception is not active. + 0 + + + ACTIVE + SVCall exception is active. + 0x1 + + + + + MONITORACT + Debug monitor active. + 8 + 1 + read-write + + + NOT_ACTIVE + Debug monitor exception is not active. + 0 + + + ACTIVE + Debug monitor exception is active. + 0x1 + + + + + PENDSVACT + PendSV exception active. + 10 + 1 + read-write + + + NOT_ACTIVE + PendSV exception is not active. + 0 + + + ACTIVE + PendSV exception is active. + 0x1 + + + + + SYSTICKACT + SysTick exception active. + 11 + 1 + read-write + + + NOT_ACTIVE + SysTick exception is not active. + 0 + + + ACTIVE + SysTick exception is active. + 0x1 + + + + + USGFAULTPENDED + UsageFault exception pending. + 12 + 1 + read-write + + + NOT_PENDING + UsageFault exception is not pending. + 0 + + + PENDING + UsageFault exception is pending. + 0x1 + + + + + MEMFAULTPENDED + MemManage exception pending. + 13 + 1 + read-write + + + NOT_PENDING + MemManage exception is not pending. + 0 + + + PENDING + MemManage exception is pending. + 0x1 + + + + + BUSFAULTPENDED + BusFault exception pending. + 14 + 1 + read-write + + + NOT_PENDING + BusFault exception is pending. + 0 + + + PENDING + BusFault exception is not pending. + 0x1 + + + + + SVCALLPENDED + SVCall pending. + 15 + 1 + read-write + + + NOT_PENDING + SVCall exception is not pending. + 0 + + + PENDING + SVCall exception is pending. + 0x1 + + + + + MEMFAULTENA + MemManage enable. + 16 + 1 + read-write + + + DISABLED + MemManage exception is disabled. + 0 + + + ENABLED + MemManage exception is enabled. + 0x1 + + + + + BUSFAULTENA + BusFault enable. + 17 + 1 + read-write + + + DISABLED + BusFault is disabled. + 0 + + + ENABLED + BusFault is enabled. + 0x1 + + + + + USGFAULTENA + UsageFault enable. + 18 + 1 + read-write + + + DISABLED + UsageFault is disabled. + 0 + + + ENABLED + UsageFault is enabled. + 0x1 + + + + + SECUREFAULTENA + SecureFault exception enable. + 19 + 1 + read-write + + + DISABLED + SecureFault exception is disabled. + 0 + + + ENABLED + SecureFault exception is enabled. + 0x1 + + + + + SECUREFAULTPENDED + SecureFault exception pended state bit. + 20 + 1 + read-write + + + DISABLED + SecureFault exception modification is disabled. + 0 + + + ENABLED + SecureFault exception modification is enabled. + 0x1 + + + + + HARDFAULTPENDED + HardFault exception pended state + 21 + 1 + read-write + + + DISABLED + HardFault exception modification is disabled. + 0 + + + ENABLED + HardFault exception modification is enabled. + 0x1 + + + + + + + NSACR + Non-secure Access Control Register + 0x8C + 32 + read-write + 0 + 0 + + + CP0 + CP0 access. + 0 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP1 + CP1 access. + 1 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP2 + CP2 access. + 2 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP3 + CP3 access. + 3 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP4 + CP4 access. + 4 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP5 + CP5 access. + 5 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP6 + CP6 access. + 6 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP7 + CP7 access. + 7 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP10 + CP10 access. + 10 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to the Floatingpoint Extension permitted. + 0x1 + + + + + CP11 + CP11 access. + 11 + 1 + read-write + + + + + + + SAU + no description available + SAU + 0xE000EDD0 + + 0 + 0xEC + registers + + + + CTRL + Security Attribution Unit Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. + 0 + 1 + read-write + + + DISABLED + The SAU is disabled. + 0 + + + ENABLED + The SAU is enabled. + 0x1 + + + + + ALLNS + All Non-secure. + 1 + 1 + read-write + + + SECURED_MEMORY + Memory is marked as Secure and is not Non-secure callable. + 0 + + + NON_SECURED_MEMORY + Memory is marked as Non-secure. + 0x1 + + + + + + + TYPE + Security Attribution Unit Type Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SREGION + SAU regions. The number of implemented SAU regions. + 0 + 8 + read-write + + + + + RNR + Security Attribution Unit Region Number Register + 0xD8 + 32 + read-write + 0 + 0 + + + REGION + Region number. + 0 + 8 + read-write + + + + + RBAR + Security Attribution Unit Region Base Address Register + 0xDC + 32 + read-write + 0 + 0 + + + BADDR + Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. + 5 + 27 + read-write + + + + + RLAR + Security Attribution Unit Region Limit Address Register + 0xE0 + 32 + read-write + 0 + 0 + + + ENABLE + Enable. SAU region enable. + 0 + 1 + read-write + + + ENABLED + SAU region is enabled. + 0 + + + DISABLED + SAU region is disabled. + 0x1 + + + + + NSC + Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. + 1 + 1 + read-write + + + NOT_NON_SECURE_CALLABLE + Region is not Non-secure callable. + 0 + + + NON_SECURE_CALLABLE + Region is Non-secure callable. + 0x1 + + + + + LADDR + Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. + 5 + 27 + read-write + + + + + SFSR + Secure Fault Status Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INVEP + Invalid entry point. + 0 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVIS + Invalid integrity signature flag. + 1 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVER + Invalid exception return flag. + 2 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + AUVIOL + Attribution unit violation flag. + 3 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVTRAN + Invalid transition flag. + 4 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + LSPERR + Lazy state preservation error flag. + 5 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + SFARVALID + Secure fault address valid. + 6 + 1 + read-write + + + NOT_VALID + SFAR content not valid. + 0 + + + VALID + SFAR content valid. + 0x1 + + + + + LSERR + Lazy state error flag. + 7 + 1 + read-write + + + NO_ERROR + Error has not occurred + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + + + SFAR + Secure Fault Address Register + 0xE8 + 32 + read-write + 0 + 0 + + + ADDRESS + When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. + 0 + 32 + read-write + + + + + + + \ No newline at end of file diff --git a/pyocd/debug/svd/loader.py b/pyocd/debug/svd/loader.py index 0214fce24..ee58f1e8b 100644 --- a/pyocd/debug/svd/loader.py +++ b/pyocd/debug/svd/loader.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,7 +17,7 @@ import threading import logging -import pkg_resources +import importlib_resources import zipfile from .parser import SVDParser @@ -31,7 +31,8 @@ class SVDFile(object): @classmethod def from_builtin(cls, svd_name): try: - zip_stream = pkg_resources.resource_stream("pyocd", BUILTIN_SVD_DATA_PATH) + zip_ref = importlib_resources.files("pyocd").joinpath(BUILTIN_SVD_DATA_PATH) + zip_stream = zip_ref.open('rb') zip = zipfile.ZipFile(zip_stream, 'r') return SVDFile(zip.open(svd_name)) except (KeyError, FileNotFoundError, zipfile.BadZipFile) as err: diff --git a/pyocd/flash/builder.py b/pyocd/flash/builder.py index 0f2b9d864..24ae46c25 100644 --- a/pyocd/flash/builder.py +++ b/pyocd/flash/builder.py @@ -394,7 +394,7 @@ def add_page_with_existing_data(): page = add_page_with_existing_data() sector_page_addr += page.size - def program(self, chip_erase=None, progress_cb=None, smart_flash=True, fast_verify=False, keep_unwritten=True): + def program(self, chip_erase=None, progress_cb=None, smart_flash=True, fast_verify=False, keep_unwritten=True, no_reset=False): """@brief Determine fastest method of flashing and then run flash programming. Data must have already been added with add_data(). @@ -419,6 +419,8 @@ def program(self, chip_erase=None, progress_cb=None, smart_flash=True, fast_veri written, there may be ranges of flash that would be erased but not written with new data. This parameter sets whether the existing contents of those unwritten ranges will be read from memory and restored while programming. + @param no_reset Boolean indicating whether if the device should not be reset after the + programming process has finished. """ # Send notification that we're about to program flash. @@ -512,7 +514,9 @@ def program(self, chip_erase=None, progress_cb=None, smart_flash=True, fast_veri # Cleanup flash algo and reset target after programming. self.flash.cleanup() - self.flash.target.reset_and_halt() + + if no_reset is not True: + self.flash.target.reset_and_halt() program_finish = time() self.perf.program_time = program_finish - program_start diff --git a/pyocd/flash/file_programmer.py b/pyocd/flash/file_programmer.py index 0d45e7260..195e02dd6 100755 --- a/pyocd/flash/file_programmer.py +++ b/pyocd/flash/file_programmer.py @@ -64,7 +64,8 @@ def __init__(self, chip_erase: Optional[bool] = None, smart_flash: Optional[bool] = None, trust_crc: Optional[bool] = None, - keep_unwritten: Optional[bool] = None + keep_unwritten: Optional[bool] = None, + no_reset: Optional[bool] = None ): """@brief Constructor. @@ -85,12 +86,15 @@ def __init__(self, written, there may be ranges of flash that would be erased but not written with new data. This parameter sets whether the existing contents of those unwritten ranges will be read from memory and restored while programming. + @param no_reset Boolean indicating whether if the device should not be reset after the + programming process has finished. """ self._session = session self._chip_erase = chip_erase self._smart_flash = smart_flash self._trust_crc = trust_crc self._keep_unwritten = keep_unwritten + self._no_reset = no_reset self._progress = progress self._loader = None @@ -149,7 +153,8 @@ def program(self, file_or_path: Union[str, IO[bytes]], file_format: Optional[str chip_erase=self._chip_erase, smart_flash=self._smart_flash, trust_crc=self._trust_crc, - keep_unwritten=self._keep_unwritten) + keep_unwritten=self._keep_unwritten, + no_reset=self._no_reset) # file_obj = None # Open the file if a path was provided. diff --git a/pyocd/flash/flash.py b/pyocd/flash/flash.py index a6fc54e53..831c65254 100644 --- a/pyocd/flash/flash.py +++ b/pyocd/flash/flash.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2013-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # Copyright (c) 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 # @@ -85,7 +85,7 @@ class Flash: passed to the ProgramPage() flash algo API. Pages must be the same size or smaller than sectors. - phrase: The minimum programming granularity, often from 1-16 bytes. For some flash - technologies, the is no distinction between a phrase and a page. + technologies, there is no distinction between a phrase and a page. The `flash_algo` parameter of the constructor is a dictionary that defines all the details of the flash algorithm. The keys of this dictionary are as follows. @@ -408,14 +408,16 @@ def program_page(self, address, bytes): def start_program_page_with_buffer(self, buffer_number, address): """@brief Start flashing one or more pages. """ - assert self.region is not None assert buffer_number < len(self.page_buffers), "Invalid buffer number" assert self._active_operation == self.Operation.PROGRAM + page_info = self.get_page_info(address) + assert page_info + # update core register to execute the program_page subroutine - TRACE.debug("start_program_page_with_buffer(addr=%x, len=%x, data=%x)", address, self.region.page_size, + TRACE.debug("start_program_page_with_buffer(addr=%x, len=%x, data=%x)", address, page_info.size, self.page_buffers[buffer_number]) - self._call_function(self.flash_algo['pc_program_page'], address, self.region.page_size, self.page_buffers[buffer_number]) + self._call_function(self.flash_algo['pc_program_page'], address, page_info.size, self.page_buffers[buffer_number]) def load_page_buffer(self, buffer_number, address, bytes): """@brief Load data to a numbered page buffer. @@ -466,31 +468,45 @@ def program_phrase(self, address, bytes): elif result != 0: raise FlashProgramFailure('flash program phrase failure', address=address, result_code=result) + def _get_region_or_subregion(self, addr: int): + assert self.region is not None + if not self.region.contains_address(addr): + return None + + region = None + if self.region.has_subregions: + region = self.region.submap.get_region_for_address(addr) + + if not region: + region = self.region + + return region + def get_sector_info(self, addr): """@brief Get info about the sector that contains this address. """ - assert self.region is not None - if not self.region.contains_address(addr): + region = self._get_region_or_subregion(addr) + if region is None: return None info = SectorInfo( - erase_weight=self.region.erase_sector_weight, - size=self.region.sector_size, - base_addr=align_down(addr, self.region.sector_size), + erase_weight=region.erase_sector_weight, + size=region.sector_size, + base_addr=align_down(addr, region.sector_size), ) return info def get_page_info(self, addr): """@brief Get info about the page that contains this address. """ - assert self.region is not None - if not self.region.contains_address(addr): + region = self._get_region_or_subregion(addr) + if region is None: return None info = PageInfo( - program_weight=self.region.program_page_weight, - size=self.region.page_size, - base_addr=align_down(addr, self.region.page_size) + program_weight=region.program_page_weight, + size=region.page_size, + base_addr=align_down(addr, region.page_size) ) return info diff --git a/pyocd/flash/loader.py b/pyocd/flash/loader.py index b61034408..f4c6df930 100755 --- a/pyocd/flash/loader.py +++ b/pyocd/flash/loader.py @@ -145,6 +145,7 @@ class MemoryLoader: _smart_flash: Optional[bool] _trust_crc: Optional[bool] _keep_unwritten: Optional[bool] + _no_reset: Optional[bool] def __init__(self, session: "Session", @@ -152,7 +153,8 @@ def __init__(self, chip_erase: Optional[bool] = None, smart_flash: Optional[bool] = None, trust_crc: Optional[bool] = None, - keep_unwritten: Optional[bool] = None + keep_unwritten: Optional[bool] = None, + no_reset: Optional[bool] = None ): """@brief Constructor. @@ -173,6 +175,8 @@ def __init__(self, written, there may be ranges of flash that would be erased but not written with new data. This parameter sets whether the existing contents of those unwritten ranges will be read from memory and restored while programming. + @param no_reset Boolean indicating whether if the device should not be reset after the + programming process has finished. """ self._session = session assert session.board @@ -195,6 +199,8 @@ def __init__(self, else self._session.options.get('fast_program') self._keep_unwritten = keep_unwritten if (keep_unwritten is not None) \ else self._session.options.get('keep_unwritten') + self._no_reset = no_reset if (no_reset is not None) \ + else self._session.options.get('no_reset') self._reset_state() @@ -290,7 +296,8 @@ def commit(self): progress_cb=self._progress_cb, smart_flash=self._smart_flash, fast_verify=self._trust_crc, - keep_unwritten=self._keep_unwritten) + keep_unwritten=self._keep_unwritten, + no_reset=self._no_reset) perfList.append(perf) didChipErase = True diff --git a/pyocd/gdbserver/gdbserver.py b/pyocd/gdbserver/gdbserver.py index 8f3fb1c2e..351377b80 100644 --- a/pyocd/gdbserver/gdbserver.py +++ b/pyocd/gdbserver/gdbserver.py @@ -22,7 +22,7 @@ import sys import io from xml.etree.ElementTree import (Element, SubElement, tostring) -from typing import (Dict, List, Optional) +from typing import (Dict, List, Optional, Tuple) from ..core import exceptions from ..core.target import Target @@ -33,6 +33,7 @@ from ..utility.server import StreamServer from ..utility.timeout import Timeout from ..trace.swv import SWVReader +from ..utility.rtt_server import RTTServer from ..utility.sockets import ListenerSocket from .syscall import GDBSyscallIOHandler from ..debug import semihost @@ -195,6 +196,9 @@ def __init__(self, session, core=None): semihost_console = semihost_io_handler self.semihost = semihost.SemihostAgent(self.target_context, io_handler=semihost_io_handler, console=semihost_console) + # Start with RTT disabled + self.rtt_server: Optional[RTTServer] = None + # # If SWV is enabled, create a SWVReader thread. Note that we only do # this if the core is 0: SWV is not a per-core construct, and can't @@ -295,6 +299,9 @@ def _cleanup(self): if self._swv_reader: self._swv_reader.stop() self._swv_reader = None + if self.rtt_server: + self.rtt_server.stop() + self.rtt_server = None self.abstract_socket.cleanup() def _cleanup_for_next_connection(self): @@ -617,6 +624,9 @@ def resume(self, data): try: state = self.target.get_state() + if self.rtt_server: + self.rtt_server.poll() + # If we were able to successfully read the target state after previously receiving a fault, # then clear the timeout. if fault_retry_timeout.is_running: @@ -1138,10 +1148,9 @@ def create_rsp_packet(self, data): resp = b'$' + data + b'#' + checksum(data) return resp - def syscall(self, op): - op = to_bytes_safe(op) + def syscall(self, op: str) -> Tuple[int, int]: LOG.debug("GDB server syscall: %s", op) - request = self.create_rsp_packet(b'F' + op) + request = self.create_rsp_packet(b'F' + op.encode()) self.packet_io.send(request) while not self.packet_io.interrupt_event.is_set(): diff --git a/pyocd/gdbserver/gdbserver_commands.py b/pyocd/gdbserver/gdbserver_commands.py index e5dde197b..5698b1705 100644 --- a/pyocd/gdbserver/gdbserver_commands.py +++ b/pyocd/gdbserver/gdbserver_commands.py @@ -19,6 +19,7 @@ from ..core import exceptions from ..commands.base import CommandBase +from ..utility.rtt_server import RTTServer LOG = logging.getLogger(__name__) @@ -125,3 +126,127 @@ class GdbserverMonitorExitCommand(CommandBase): def execute(self): for server in self.context.session.gdbservers.values(): server.stop(wait=False) + +class RTTCommand(CommandBase): + INFO = { + 'names': ['rtt'], + 'group': 'gdbserver', + 'category': 'rtt', + 'nargs': "*", + 'usage': "rtt {setup,start,stop,channels,server}", + 'help': "Control SEGGER RTT compatible interface.", + } + + def parse(self, args): + if len(args) < 1: + raise exceptions.CommandError("too few arguments") + + if args[0] == 'setup': + if len(args) < 4: + raise exceptions.CommandError("too few arguments") + + try: + self.addr = int(args[1], 0) + self.size = int(args[2], 0) + self.id = " ".join(args[3:]).encode("utf-8") + except ValueError as e: + raise exceptions.CommandError("invalid action") from e + elif args[0] == 'start' or args[0] == 'stop' or args[0] == 'channels': + if len(args) > 1: + raise exceptions.CommandError("too many arguments") + elif args[0] == 'server': + if len(args) < 2: + raise exceptions.CommandError("too few arguments") + + if args[1] == 'start': + if len(args) < 4: + raise exceptions.CommandError("too few arguments") + elif len(args) > 4: + raise exceptions.CommandError("too many arguments") + + try: + self.port = int(args[2], 0) + self.channel = int(args[3], 0) + except ValueError as e: + raise exceptions.CommandError("invalid action*") from e + elif args[1] == 'stop': + if len(args) < 3: + raise exceptions.CommandError("too few arguments") + elif len(args) > 3: + raise exceptions.CommandError("too many arguments") + + try: + self.port = int(args[2], 0) + except ValueError as e: + raise exceptions.CommandError("invalid action") from e + else: + raise exceptions.CommandError("invalid action") + + self.server_action = args[1] + else: + raise exceptions.CommandError("invalid action") + + self.action = args[0] + + def execute(self): + # Get the gdbserver for the selected core. + core_number = self.context.selected_core.core_number + try: + gdbserver = self.context.session.gdbservers[core_number] + except KeyError: + raise exceptions.CommandError("no gdbserver for core #%i" % core_number) + + if self.action == "setup": + if gdbserver.rtt_server is not None: + if gdbserver.rtt_server.running: + raise exceptions.CommandError("rtt is already running") + else: + gdbserver.rtt_server = None + + try: + gdbserver.rtt_server = RTTServer(gdbserver.target, address = self.addr, + size = self.size, + control_block_id = self.id) + except exceptions.RTTError as e: + raise exceptions.CommandError(str(e)) from e + elif self.action == "start": + if gdbserver.rtt_server is None: + raise exceptions.CommandError("rtt is not configured") + + try: + gdbserver.rtt_server.start() + except exceptions.RTTError as e: + raise exceptions.CommandError(str(e)) from e + + self.context.write(f"Found RTT control block.") + elif self.action == "stop": + if gdbserver.rtt_server is not None: + gdbserver.rtt_server.stop() + elif self.action == "channels": + control_block = gdbserver.rtt_server.control_block + self.context.write(f"Channels: up={len(control_block.up_channels)}, " + f"down={len(control_block.down_channels)}") + self.context.write("Up-channels:") + for i, chan in enumerate(control_block.up_channels): + name = chan.name if chan.name is not None else "" + self.context.write(f"{i}: {name} {chan.size}") + self.context.write("Down-channels:") + for i, chan in enumerate(control_block.up_channels): + name = chan.name if chan.name is not None else "" + self.context.write(f"{i}: {name} {chan.size}") + elif self.action == "server": + if gdbserver.rtt_server is None: + raise exceptions.CommandError("rtt is not configured") + elif not gdbserver.rtt_server.running: + raise exceptions.CommandError("rtt is not yet started") + + if self.server_action == "start": + try: + gdbserver.rtt_server.add_server(self.port, self.channel) + except exceptions.RTTError as e: + raise exceptions.CommandError(str(e)) from e + elif self.server_action == "stop": + try: + gdbserver.rtt_server.stop_server(self.port) + except exceptions.RTTError as e: + raise exceptions.CommandError(str(e)) from e diff --git a/pyocd/gdbserver/syscall.py b/pyocd/gdbserver/syscall.py index deb52e091..649602947 100644 --- a/pyocd/gdbserver/syscall.py +++ b/pyocd/gdbserver/syscall.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,10 +35,10 @@ class GDBSyscallIOHandler(SemihostIOHandler): """@brief Semihosting file I/O handler that performs GDB syscalls.""" def __init__(self, server): - super(GDBSyscallIOHandler, self).__init__() + super().__init__() self._server = server - def open(self, fnptr, fnlen, mode): + def open(self, fnptr: int, fnlen: int, mode: str) -> int: # Handle standard I/O. fd, _ = self._std_open(fnptr, fnlen, mode) if fd is not None: @@ -88,10 +88,12 @@ def read(self, fd, ptr, length): return length - result def readc(self): - ptr = self.agent.target.read_core_register('sp') - 4 + assert self.agent + ptr = self.agent.context.read_core_register('sp') - 4 + assert isinstance(ptr, int) result, self._errno = self._server.syscall('read,0,%x,1' % (ptr)) if result != -1: - result = self.agent.target.read8(ptr) + result = self.agent.context.read8(ptr) return result def istty(self, fd): @@ -105,12 +107,14 @@ def seek(self, fd, pos): return 0 if result != -1 else -1 def flen(self, fd): + assert self.agent fd -= FD_OFFSET - ptr = self.agent.target.read_core_register('sp') - 64 + ptr = self.agent.context.read_core_register('sp') - 64 + assert isinstance(ptr, int) result, self._errno = self._server.syscall('fstat,%x,%x' % (fd, ptr)) if result != -1: # Fields in stat struct are big endian as written by gdb. - size = self.agent.target.read_memory_block8(ptr, 8) + size = self.agent.context.read_memory_block8(ptr, 8) result = (size[0] << 56) \ | (size[1] << 48) \ | (size[2] << 40) \ diff --git a/pyocd/probe/cmsis_dap_probe.py b/pyocd/probe/cmsis_dap_probe.py index d777cc694..42cbe46f6 100644 --- a/pyocd/probe/cmsis_dap_probe.py +++ b/pyocd/probe/cmsis_dap_probe.py @@ -250,6 +250,17 @@ def create_associated_board(self) -> Optional["Board"]: return MbedBoard(self.session, board_info=board_info, board_id=self.board_id) return None + def get_accessible_pins(self, group: DebugProbe.PinGroup) -> Tuple[int, int]: + """@brief Return masks of pins accessible via the .read_pins()/.write_pins() methods. + + @return Tuple of pin masks for (0) readable, (1) writable pins. See DebugProbe.Pin for mask + values for those pins that have constants. + """ + if group is DebugProbe.PinGroup.PROTOCOL_PINS: + return (self.ProtocolPin.ALL_PINS, self.ProtocolPin.ALL_PINS) + else: + return (0, 0) + def open(self) -> None: if self._is_open: return @@ -289,6 +300,7 @@ def open(self) -> None: self.Capability.BANKED_DP_REGISTERS, self.Capability.APv2_ADDRESSES, self.Capability.JTAG_SEQUENCE, + self.Capability.PIN_ACCESS, } if self._link.has_swd_sequence: self._caps.add(self.Capability.SWD_SEQUENCE) @@ -411,6 +423,87 @@ def flush(self) -> None: TRACE.debug("trace: error from flush: %r", exc) raise self._convert_exception(exc) from exc + def read_pins(self, group: DebugProbe.PinGroup, mask: int) -> int: + """@brief Read values of selected debug probe pins. + + See DebugProbe.ProtocolPin for mask values. + + @param self + @param group Select the pin group to read. + @param mask Bit mask indicating which pins will be read. The return value will contain only + bits set in this mask. + @return Bit mask with the current value of selected pins at each pin's relevant bit position. + """ + try: + if group is DebugProbe.PinGroup.PROTOCOL_PINS: + # CMSIS-DAP DAP_SWJ_Pins command will always return all pin values, so mask + # the ones the caller wants. + result = self.from_cmsis_dap_pins(self._link.pin_access(0, 0)) & mask + TRACE.debug("trace: read_pins(%x) -> %s", mask, result) + return result + else: + return 0 + except DAPAccess.Error as exc: + raise self._convert_exception(exc) from exc + + def write_pins(self, group: DebugProbe.PinGroup, mask: int, value: int) -> None: + """@brief Set values of selected debug probe pins. + + See DebugProbe.ProtocolPin for mask values. + + @param self + @param group Select the pin group to read. + @param mask Bit mask indicating which pins will be written. + @param value Mask containing the bit value of to written for selected pins at each pin's + relevant bit position.. + """ + try: + if group is DebugProbe.PinGroup.PROTOCOL_PINS: + self._link.pin_access(self.to_cmsis_dap_pins(mask), self.to_cmsis_dap_pins(value)) + TRACE.debug("trace: write_pins(%s, %s)", mask, value) + except DAPAccess.Error as exc: + raise self._convert_exception(exc) from exc + + @staticmethod + def to_cmsis_dap_pins(mask: int) -> int: + # - [0] SWCLK/TCK + # - [1] SWDIO/TMS + # - [2] TDI + # - [3] TDO + # - [5] nTRST + # - [7] nRESET + result = 0 + if mask & DebugProbe.ProtocolPin.SWCLK_TCK: + result |= 1 << 0 + if mask & DebugProbe.ProtocolPin.SWDIO_TMS: + result |= 1 << 1 + if mask & DebugProbe.ProtocolPin.TDI: + result |= 1 << 2 + if mask & DebugProbe.ProtocolPin.TDO: + result |= 1 << 3 + if mask & DebugProbe.ProtocolPin.nRESET: + result |= 1 << 7 + if mask & DebugProbe.ProtocolPin.nTRST: + result |= 1 << 5 + return result + + @staticmethod + def from_cmsis_dap_pins(mask: int) -> int: + result = 0 + if mask & (1 << 0): + result |= DebugProbe.ProtocolPin.SWCLK_TCK + if mask & (1 << 1): + result |= DebugProbe.ProtocolPin.SWDIO_TMS + if mask & (1 << 2): + result |= DebugProbe.ProtocolPin.TDI + if mask & (1 << 3): + result |= DebugProbe.ProtocolPin.TDO + if mask & (1 << 5): + result |= DebugProbe.ProtocolPin.nTRST + if mask & (1 << 7): + result |= DebugProbe.ProtocolPin.nRESET + return result + # ------------------------------------------- # # DAP Access functions # ------------------------------------------- # diff --git a/pyocd/probe/debug_probe.py b/pyocd/probe/debug_probe.py index 725de904b..959924bfb 100644 --- a/pyocd/probe/debug_probe.py +++ b/pyocd/probe/debug_probe.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2018-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,7 +15,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -from enum import Enum +from enum import (Enum, IntFlag) import threading from typing import (Callable, Collection, Optional, overload, Sequence, Set, TYPE_CHECKING, Tuple, Union) from typing_extensions import Literal @@ -69,6 +69,21 @@ class Protocol(Enum): SWD = 1 JTAG = 2 + class PinGroup(Enum): + """@brief Available pin groups for read/write pins APIs.""" + PROTOCOL_PINS = 0 + GPIO_PINS = 1 + + class ProtocolPin(IntFlag): + """@brief Pin mask constants for SWD/JTAG protocol pins.""" + SWCLK_TCK = 1 << 0 + SWDIO_TMS = 1 << 1 + TDI = 1 << 2 + TDO = 1 << 3 + nRESET = 1 << 4 + nTRST = 1 << 5 + ALL_PINS = SWCLK_TCK | SWDIO_TMS | TDI | TDO | nRESET | nTRST + ## Map from wire protocol setting name to debug probe constant. PROTOCOL_NAME_MAP = { 'swd': Protocol.SWD, @@ -115,6 +130,9 @@ class Capability(Enum): ## @brief Whether the probe supports the jtag_sequence() API. JTAG_SEQUENCE = 7 + ## @brief Pin access via the read_pins()/write_pins() APIs. + PIN_ACCESS = 8 + @classmethod def get_all_connected_probes( cls, @@ -240,6 +258,16 @@ def create_associated_board(self) -> Optional["Board"]: """ return None + def get_accessible_pins(self, group: PinGroup) -> Tuple[int, int]: + """@brief Return masks of pins accessible via the .read_pins()/.write_pins() methods. + + This method is only expected to be implemented if Capability.PIN_ACCESS is present. + + @return Tuple of pin masks for (0) readable, (1) writable pins. See DebugProbe.Pin for mask + values for those pins that have constants. + """ + raise NotImplementedError() + def open(self) -> None: """@brief Open the USB interface to the probe for sending commands.""" raise NotImplementedError() @@ -351,6 +379,37 @@ def flush(self) -> None: """ pass + def read_pins(self, group: PinGroup, mask: int) -> int: + """@brief Read values of selected debug probe pins. + + See DebugProbe.ProtocolPin for mask values for the DebugProbe.PinGroup.PROTOCOL_PINS group. + + This method is only expected to be implemented if Capability.PIN_ACCESS is present. + + @param self + @param group Select the pin group to read. + @param mask Bit mask indicating which pins will be read. The return value will contain only + bits set in this mask. + @return Bit mask with the current value of selected pins at each pin's relevant bit position. + """ + raise NotImplementedError() + + def write_pins(self, group: PinGroup, mask: int, value: int) -> None: + """@brief Set values of selected debug probe pins. + + See DebugProbe.ProtocolPin for mask values for the DebugProbe.PinGroup.PROTOCOL_PINS group. + Note that input-only pins such as TDO are not writable with most debug probes. + + This method is only expected to be implemented if Capability.PIN_ACCESS is present. + + @param self + @param group Select the pin group to read. + @param mask Bit mask indicating which pins will be written. + @param value Mask containing the bit value of to written for selected pins at each pin's + relevant bit position.. + """ + raise NotImplementedError() + ##@} ## @name DAP access diff --git a/pyocd/probe/jlink_probe.py b/pyocd/probe/jlink_probe.py index c4664203b..341487940 100644 --- a/pyocd/probe/jlink_probe.py +++ b/pyocd/probe/jlink_probe.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,13 +19,18 @@ import logging from time import sleep import pylink +from pylink.enums import JLinkInterfaces from pylink.errors import (JLinkException, JLinkWriteException, JLinkReadException) +from typing import (TYPE_CHECKING, Optional, Tuple) from .debug_probe import DebugProbe from ..core import exceptions from ..core.plugin import Plugin from ..core.options import OptionInfo +if TYPE_CHECKING: + from pylink.structs import JLinkHardwareStatus + LOG = logging.getLogger(__name__) TRACE = LOG.getChild("trace") @@ -44,7 +49,7 @@ class JLinkProbe(DebugProbe): APSEL_APBANKSEL = APSEL | APBANKSEL @classmethod - def _get_jlink(cls): + def _get_jlink(cls) -> Optional[pylink.JLink]: # TypeError is raised by pylink if the JLink DLL cannot be found. try: return pylink.JLink( @@ -104,10 +109,11 @@ def __init__(self, serial_number): @param self The object. @param serial_number String. The J-Link's serial number. """ - super(JLinkProbe, self).__init__() - self._link = self._get_jlink() - if self._link is None: + super().__init__() + link = self._get_jlink() + if link is None: raise exceptions.ProbeError("unable to open JLink DLL") + self._link = link info = self._get_probe_info(serial_number, self._link) if info is None: @@ -156,9 +162,23 @@ def capabilities(self): self.Capability.SWO, self.Capability.BANKED_DP_REGISTERS, self.Capability.APv2_ADDRESSES, + self.Capability.PIN_ACCESS, } + def get_accessible_pins(self, group: DebugProbe.PinGroup) -> Tuple[int, int]: + """@brief Return masks of pins accessible via the .read_pins()/.write_pins() methods. + + @return Tuple of pin masks for (0) readable, (1) writable pins. See DebugProbe.Pin for mask + values for those pins that have constants. + """ + if group is DebugProbe.PinGroup.PROTOCOL_PINS: + return (self.ProtocolPin.ALL_PINS, self.ProtocolPin.ALL_PINS) + else: + return (0, 0) + def open(self): + assert self.session + try: # Configure UI usage. We must do this here rather than in the ctor because the ctor # doesn't have access to the session. @@ -171,9 +191,9 @@ def open(self): # Get available wire protocols. ifaces = self._link.supported_tifs() self._supported_protocols = [DebugProbe.Protocol.DEFAULT] - if ifaces & (1 << pylink.enums.JLinkInterfaces.JTAG): + if ifaces & (1 << JLinkInterfaces.JTAG): self._supported_protocols.append(DebugProbe.Protocol.JTAG) - if ifaces & (1 << pylink.enums.JLinkInterfaces.SWD): + if ifaces & (1 << JLinkInterfaces.SWD): self._supported_protocols.append(DebugProbe.Protocol.SWD) if not len(self._supported_protocols) >= 2: # default + 1 raise exceptions.ProbeError("J-Link probe {} does not support any known wire protocols".format( @@ -199,19 +219,24 @@ def close(self): # ------------------------------------------- # def connect(self, protocol=None): """@brief Connect to the target via JTAG or SWD.""" + assert self.session + # Handle default protocol. if (protocol is None) or (protocol == DebugProbe.Protocol.DEFAULT): protocol = self._default_protocol # Validate selected protocol. + assert self._supported_protocols is not None if protocol not in self._supported_protocols: raise ValueError("unsupported wire protocol %s" % protocol) # Convert protocol to port enum. if protocol == DebugProbe.Protocol.SWD: - iface = pylink.enums.JLinkInterfaces.SWD + iface = JLinkInterfaces.SWD elif protocol == DebugProbe.Protocol.JTAG: - iface = pylink.enums.JLinkInterfaces.JTAG + iface = JLinkInterfaces.JTAG + else: + raise exceptions.InternalError(f"unknown wire protocol ({protocol})") try: self._link.set_tif(iface) @@ -245,6 +270,7 @@ def swj_sequence(self, length, bits): def disconnect(self): """@brief Disconnect from the target.""" + assert self.session try: if self.session.options.get('jlink.power'): self._link.power_off() @@ -260,6 +286,7 @@ def set_clock(self, frequency): raise self._convert_exception(exc) from exc def reset(self): + assert self.session try: self._link.set_reset_pin_low() sleep(self.session.options.get('reset.hold_time')) @@ -284,6 +311,93 @@ def is_reset_asserted(self): except JLinkException as exc: raise self._convert_exception(exc) from exc + def read_pins(self, group: DebugProbe.PinGroup, mask: int) -> int: + """@brief Read values of selected debug probe pins. + + See DebugProbe.ProtocolPin for mask values. + + @param self + @param group Select the pin group to read. + @param mask Bit mask indicating which pins will be read. The return value will contain only + bits set in this mask. + @return Bit mask with the current value of selected pins at each pin's relevant bit position. + """ + try: + if group is DebugProbe.PinGroup.PROTOCOL_PINS: + status = self._link.hardware_status + return self.from_jlink_pins(status) & mask + else: + return 0 + except JLinkException as exc: + raise self._convert_exception(exc) from exc + + def write_pins(self, group: DebugProbe.PinGroup, mask: int, value: int) -> None: + """@brief Set values of selected debug probe pins. + + See DebugProbe.ProtocolPin for mask values. + + @param self + @param group Select the pin group to read. + @param mask Bit mask indicating which pins will be written. + @param value Mask containing the bit value of to written for selected pins at each pin's + relevant bit position.. + """ + assert self._link + try: + if group is not DebugProbe.PinGroup.PROTOCOL_PINS: + return + if mask & DebugProbe.ProtocolPin.SWCLK_TCK: + if value & DebugProbe.ProtocolPin.SWCLK_TCK: + self._link.set_tck_pin_high() + else: + self._link.set_tck_pin_low() + if mask & DebugProbe.ProtocolPin.SWDIO_TMS: + if value & DebugProbe.ProtocolPin.SWDIO_TMS: + self._link.set_tms_pin_high() + else: + self._link.set_tms_pin_low() + if mask & DebugProbe.ProtocolPin.TDI: + if value & DebugProbe.ProtocolPin.TDI: + self._link.set_tdi_pin_high() + else: + self._link.set_tdi_pin_low() + if mask & DebugProbe.ProtocolPin.nRESET: + if value & DebugProbe.ProtocolPin.nRESET: + self._link.set_reset_pin_high() + else: + self._link.set_reset_pin_low() + if mask & DebugProbe.ProtocolPin.nTRST: + if value & DebugProbe.ProtocolPin.nTRST: + self._link.set_trst_pin_high() + else: + self._link.set_trst_pin_low() + except JLinkException as exc: + raise self._convert_exception(exc) from exc + + @staticmethod + def from_jlink_pins(status: "JLinkHardwareStatus") -> int: + # JLinkHardwareStatus attributes: + # - tck: measured state of TCK pin. + # - tdi: measured state of TDI pin. + # - tdo: measured state of TDO pin. + # - tms: measured state of TMS pin. + # - tres: measured state of TRES pin. + # - trst: measured state of TRST pin. + result = 0 + if status.tck: + result |= DebugProbe.ProtocolPin.SWCLK_TCK + if status.tms: + result |= DebugProbe.ProtocolPin.SWDIO_TMS + if status.tdi: + result |= DebugProbe.ProtocolPin.TDI + if status.tdo: + result |= DebugProbe.ProtocolPin.TDO + if status.tres: + result |= DebugProbe.ProtocolPin.nRESET + if status.trst: + result |= DebugProbe.ProtocolPin.nTRST + return result + # ------------------------------------------- # # DAP Access functions # ------------------------------------------- # @@ -338,7 +452,7 @@ def write_ap_multiple(self, addr, values): def swo_start(self, baudrate): try: - self._link.swo_start(baudrate) + self._link.swo_start(int(baudrate)) except JLinkException as exc: raise self._convert_exception(exc) from exc diff --git a/pyocd/probe/pydapaccess/cmsis_dap_core.py b/pyocd/probe/pydapaccess/cmsis_dap_core.py index d5803d063..bb7ddd92d 100644 --- a/pyocd/probe/pydapaccess/cmsis_dap_core.py +++ b/pyocd/probe/pydapaccess/cmsis_dap_core.py @@ -340,7 +340,7 @@ def set_swj_pins(self, output, pins, wait=0): cmd = [] cmd.append(Command.DAP_SWJ_PINS) cmd.append(output & 0xff) - cmd.append(pins) + cmd.append(pins & 0xff) cmd.append(wait & 0xff) cmd.append((wait >> 8) & 0xff) cmd.append((wait >> 16) & 0xff) diff --git a/pyocd/probe/pydapaccess/dap_access_api.py b/pyocd/probe/pydapaccess/dap_access_api.py index c34176808..c81a60f5c 100644 --- a/pyocd/probe/pydapaccess/dap_access_api.py +++ b/pyocd/probe/pydapaccess/dap_access_api.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2006-2013,2018-2019 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -287,6 +287,10 @@ def is_reset_asserted(self): """@brief Returns True if the target reset line is asserted or False if de-asserted""" raise NotImplementedError() + def pin_access(self, mask: int, value: int) -> int: + """@brief Read/write probe pins""" + raise NotImplementedError() + def set_deferred_transfer(self, enable): """@brief Allow reads and writes to be buffered for increased speed""" raise NotImplementedError() diff --git a/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py b/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py index 0f39dfbd0..1934fe332 100644 --- a/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py +++ b/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py @@ -1,7 +1,7 @@ # pyOCD debugger # Copyright (c) 2006-2013,2018-2021 Arm Limited # Copyright (c) 2020 Koji Kitayama -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -820,6 +820,11 @@ def close(self): def get_unique_id(self): return self._unique_id + @locked + def pin_access(self, mask: int, value: int) -> int: + self.flush() + return self._protocol.set_swj_pins(value, mask) + @locked def assert_reset(self, asserted): self.flush() @@ -862,7 +867,13 @@ def set_deferred_transfer(self, enable): @locked def flush(self): - TRACE.debug("flush: sending cmd:%d; reading %d outstanding", self._crnt_cmd.uid, len(self._commands_to_read)) + if TRACE.isEnabledFor(logging.DEBUG): + if self._crnt_cmd.get_empty() and len(self._commands_to_read): + TRACE.debug("flush: reading %d outstanding (cmd:%d is empty)", + len(self._commands_to_read), self._crnt_cmd.uid) + elif not self._crnt_cmd.get_empty(): + TRACE.debug("flush: sending cmd:%d; reading %d outstanding", self._crnt_cmd.uid, len(self._commands_to_read)) + # Send current packet self._send_packet() # Read all backlogged diff --git a/pyocd/probe/pydapaccess/interface/common.py b/pyocd/probe/pydapaccess/interface/common.py index c9550e4c8..3437b88ea 100644 --- a/pyocd/probe/pydapaccess/interface/common.py +++ b/pyocd/probe/pydapaccess/interface/common.py @@ -77,8 +77,21 @@ (VEGA_VID, 0x9527), # Vega VT-LinkII NXP_LPCLINK2_ID, NXP_MCULINK_ID, + (0x1a86, 0x8011), # WCH-Link + (0x2a86, 0x8011), # WCH-Link clone ] +## List of substrings to look for in product and interface name strings. +# +# These strings identify a CMSIS-DAP compatible device. According to the specification, +# "CMSIS-DAP" is required. But some low cost probes have misspelled or outright wrong +# or missing strings. +KNOWN_DEVICE_STRINGS: List[str] = ( + "CMSIS-DAP", + "CMSIS_DAP", + "WCH-Link", + ) + ## List of VID/PID pairs for CMSIS-DAP probes that have multiple HID interfaces that must be # filtered by usage page. Currently these are only NXP probes. CMSIS_DAP_IDS_TO_FILTER_BY_USAGE_PAGE: List[VidPidPair] = [ @@ -90,6 +103,9 @@ def is_known_cmsis_dap_vid_pid(vid: int, pid: int) -> bool: """@brief Test whether a VID/PID pair belong to a known CMSIS-DAP device.""" return (vid, pid) in KNOWN_CMSIS_DAP_IDS +def is_known_device_string(device_string: str) -> bool: + return any(s in device_string for s in KNOWN_DEVICE_STRINGS) + def filter_device_by_class(vid: int, pid: int, device_class: int) -> bool: """@brief Test whether the device should be ignored by comparing bDeviceClass. diff --git a/pyocd/probe/pydapaccess/interface/pyusb_backend.py b/pyocd/probe/pydapaccess/interface/pyusb_backend.py index b1e6b2849..2aad880fa 100644 --- a/pyocd/probe/pydapaccess/interface/pyusb_backend.py +++ b/pyocd/probe/pydapaccess/interface/pyusb_backend.py @@ -27,6 +27,7 @@ from .common import ( USB_CLASS_HID, filter_device_by_class, + is_known_device_string, is_known_cmsis_dap_vid_pid, generate_device_unique_id, ) @@ -345,7 +346,7 @@ def __call__(self, dev): # Now read the product name string. device_string = dev.product - if ((device_string is None) or ("CMSIS-DAP" not in device_string)) and (not known_cmsis_dap): + if ((device_string is None) or (not is_known_device_string(device_string))) and (not known_cmsis_dap): return False # Get count of HID interfaces. diff --git a/pyocd/probe/stlink_probe.py b/pyocd/probe/stlink_probe.py index 877a75390..eb025e378 100644 --- a/pyocd/probe/stlink_probe.py +++ b/pyocd/probe/stlink_probe.py @@ -16,7 +16,7 @@ # limitations under the License. from time import sleep -from typing import (Any, Callable, List, Optional, Sequence, Union, TYPE_CHECKING) +from typing import (Any, Callable, Dict, List, Optional, Sequence, Union, TYPE_CHECKING) from .debug_probe import DebugProbe from ..core.memory_interface import MemoryInterface @@ -36,6 +36,12 @@ class StlinkProbe(DebugProbe): """@brief Wraps an STLink as a DebugProbe.""" + _board_id: Optional[str] + + # Shared cache for the STLink Mbed board IDs read from MSD volumes. + # The dict maps the serial number to 4-character board ID, or None if no ID is available. + _mbed_board_id_cache: Dict[str, Optional[str]] = {} + @classmethod def get_all_connected_probes(cls, unique_id: Optional[str] = None, is_explicit: bool = False) -> List["StlinkProbe"]: @@ -55,29 +61,46 @@ def __init__(self, device: STLinkUSBInterface) -> None: self._is_connected = False self._nreset_state = False self._memory_interfaces = {} - self._mbed_info = None - self._board_id = self._get_board_id() + self._board_id = None self._caps = set() + @property + def board_id(self) -> str: + """@brief Lazily loaded 4-character board ID.""" + if self._board_id is None: + self._board_id = self._get_board_id() + return self._board_id + def _get_board_id(self) -> Optional[str]: # Try to get the board ID first by sending a command, since it is much faster. This requires # opening the USB device, however, and requires a recent STLink firmware version. board_id = self._link.get_board_id() if board_id is None: - # Try to detect associated board info via the STLinkV2-1 MSD volume. - detector = create_mbed_detector() - if detector is not None: - for info in detector.list_mbeds(): - if info['target_id_usb_id'] == self._link.serial_number: - self._mbed_info = info + # Check the cache. + if self._link.serial_number in self._mbed_board_id_cache: + board_id = StlinkProbe._mbed_board_id_cache[self._link.serial_number] + else: + # Try to detect associated board info via the STLinkV2-1 MSD volume. + detector = create_mbed_detector() + if detector is not None: + for info in detector.list_mbeds(): + usb_id = info['target_id_usb_id'] # Some STLink probes provide an MSD volume, but not the mbed.htm file. # We can live without the board ID, so just ignore any error. try: - board_id = info['target_id_mbed_htm'][0:4] + this_board_id = info['target_id_mbed_htm'][0:4] except KeyError: - pass - break + # No board ID is available for this board. + StlinkProbe._mbed_board_id_cache[usb_id] = None + else: + # Populate the cache with the ID. + StlinkProbe._mbed_board_id_cache[usb_id] = this_board_id + + # Use this ID if it's for our board. + if usb_id == self._link.serial_number: + board_id = this_board_id + break return board_id @property @@ -114,16 +137,16 @@ def capabilities(self): @property def associated_board_info(self) -> Optional["BoardInfo"]: - if (self._board_id is not None) and (self._board_id in BOARD_ID_TO_INFO): - return BOARD_ID_TO_INFO[self._board_id] + if (self.board_id is not None) and (self.board_id in BOARD_ID_TO_INFO): + return BOARD_ID_TO_INFO[self.board_id] else: return None def create_associated_board(self): assert self.session is not None board_info = self.associated_board_info - if board_info or self._board_id: - return MbedBoard(self.session, board_info=board_info, board_id=self._board_id) + if board_info or self.board_id: + return MbedBoard(self.session, board_info=board_info, board_id=self.board_id) else: return None diff --git a/pyocd/rtos/argon.py b/pyocd/rtos/argon.py index 2ba15638e..bfb01ff3e 100644 --- a/pyocd/rtos/argon.py +++ b/pyocd/rtos/argon.py @@ -440,8 +440,12 @@ def get_actual_current_thread_id(self): def get_is_running(self): if self.g_ar is None: return False - flags = self._target_context.read32(self.g_ar + KERNEL_FLAGS_OFFSET) - return (flags & IS_RUNNING_MASK) != 0 + try: + flags = self._target_context.read32(self.g_ar + KERNEL_FLAGS_OFFSET) + return (flags & IS_RUNNING_MASK) != 0 + except exceptions.TransferFaultError: + LOG.warn("Argon: read kernel flags failed, target memory might not be initialized yet.") + return False class ArgonTraceEvent(events.TraceEvent): """@brief Argon kernel trace event.""" diff --git a/pyocd/rtos/freertos.py b/pyocd/rtos/freertos.py index 2fbdf24f5..c7f9b14cc 100644 --- a/pyocd/rtos/freertos.py +++ b/pyocd/rtos/freertos.py @@ -508,7 +508,12 @@ def get_actual_current_thread_id(self): def get_is_running(self): if self._symbols is None: return False - return self._target_context.read32(self._symbols['xSchedulerRunning']) != 0 + try: + return self._target_context.read32(self._symbols['xSchedulerRunning']) != 0 + except exceptions.TransferFaultError: + LOG.warn("FreeRTOS: read running state failed, target memory might not be initialized yet.") + return False + def _get_elf_symbol_size(self, name, addr, calculated_size): if self._target.elf is not None: diff --git a/pyocd/rtos/threadx.py b/pyocd/rtos/threadx.py index ccb84f0fd..c27280248 100644 --- a/pyocd/rtos/threadx.py +++ b/pyocd/rtos/threadx.py @@ -481,7 +481,11 @@ def is_enabled(self): # safer to compare it with TX_INITIALIZE_IN_PROGRESS. if self._system_state is None: return False - return self._target_context.read32(self._system_state) < self.TX_INITIALIZE_IN_PROGRESS + try: + return self._target_context.read32(self._system_state) < self.TX_INITIALIZE_IN_PROGRESS + except exceptions.TransferFaultError: + LOG.warn("ThreadX: read system state failed, target memory might not be initialized yet.") + return False @property def current_thread(self): diff --git a/pyocd/subcommands/base.py b/pyocd/subcommands/base.py index 16542331d..4a65cdcd6 100644 --- a/pyocd/subcommands/base.py +++ b/pyocd/subcommands/base.py @@ -1,5 +1,5 @@ # pyOCD debugger -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,7 +17,7 @@ import argparse import logging import prettytable -from typing import (List, Optional, Type) +from typing import (Any, Dict, List, Optional, Type) from ..utility.cmdline import convert_frequency @@ -169,4 +169,17 @@ def _get_pretty_table(self, fields: List[str], header: bool = None) -> prettytab pt.vrules = prettytable.NONE return pt + def _modified_option_defaults(self) -> Dict[str, Any]: + """@brief Returns a dict of session option defaults. + + @return A dict containing updated default values for session options, based on common + subcommand arguments. It is intended to be passed as the `option_defaults` argument when + creating a `Session` instance. + @precondition Logging must have been configured. + """ + return { + # Change 'debug.traceback' default to True if debug logging is enabled. + 'debug.traceback': logging.getLogger('pyocd').isEnabledFor(logging.DEBUG), + } + diff --git a/pyocd/subcommands/erase_cmd.py b/pyocd/subcommands/erase_cmd.py index 918820ea5..602d3fff0 100644 --- a/pyocd/subcommands/erase_cmd.py +++ b/pyocd/subcommands/erase_cmd.py @@ -85,7 +85,9 @@ def invoke(self) -> int: frequency=self._args.frequency, blocking=(not self._args.no_wait), connect_mode=self._args.connect_mode, - options=convert_session_options(self._args.options)) + options=convert_session_options(self._args.options), + option_defaults=self._modified_option_defaults(), + ) if session is None: LOG.error("No device available to erase") return 1 diff --git a/pyocd/subcommands/gdbserver_cmd.py b/pyocd/subcommands/gdbserver_cmd.py index a788c2c64..7b7df012c 100644 --- a/pyocd/subcommands/gdbserver_cmd.py +++ b/pyocd/subcommands/gdbserver_cmd.py @@ -183,7 +183,9 @@ def invoke(self) -> int: target_override=self._args.target_override, frequency=self._args.frequency, connect_mode=self._args.connect_mode, - options=sessionOptions) + options=sessionOptions, + option_defaults=self._modified_option_defaults(), + ) if session is None: LOG.error("No probe selected.") return 1 diff --git a/pyocd/subcommands/load_cmd.py b/pyocd/subcommands/load_cmd.py index 3fdec655c..29f7b2ef2 100644 --- a/pyocd/subcommands/load_cmd.py +++ b/pyocd/subcommands/load_cmd.py @@ -62,6 +62,8 @@ def get_args(cls) -> List[argparse.ArgumentParser]: "all must be of this type.") parser_options.add_argument("--skip", metavar="BYTES", default=0, type=int_base_0, help="Skip programming the first N bytes. Binary files only.") + parser_options.add_argument("--no-reset", action="store_true", + help="Specify to prevent resetting device after programming has finished.") parser.add_argument("file", metavar="", nargs="+", help="File to write to memory. Binary files can have an optional base address appended to the file " @@ -89,14 +91,17 @@ def invoke(self) -> int: frequency=self._args.frequency, blocking=(not self._args.no_wait), connect_mode=self._args.connect_mode, - options=convert_session_options(self._args.options)) + options=convert_session_options(self._args.options), + option_defaults=self._modified_option_defaults(), + ) if session is None: LOG.error("No target device available") return 1 with session: programmer = FileProgrammer(session, chip_erase=self._args.erase, - trust_crc=self._args.trust_crc) + trust_crc=self._args.trust_crc, + no_reset=self._args.no_reset) for filename in self._args.file: # Get an initial path with the argument as-is. file_path = Path(filename).expanduser() diff --git a/pyocd/subcommands/reset_cmd.py b/pyocd/subcommands/reset_cmd.py index 8d642546d..d14075c29 100644 --- a/pyocd/subcommands/reset_cmd.py +++ b/pyocd/subcommands/reset_cmd.py @@ -84,7 +84,9 @@ def invoke(self) -> None: connect_mode=self._args.connect_mode, resume_on_disconnect=not self._args.halt, reset_type=self._args.reset_type, - options=convert_session_options(self._args.options)) + options=convert_session_options(self._args.options), + option_defaults=self._modified_option_defaults(), + ) if session is None: LOG.error("No target device available to reset") sys.exit(1) diff --git a/pyocd/subcommands/rtt_cmd.py b/pyocd/subcommands/rtt_cmd.py index 32250d478..62e1648b4 100644 --- a/pyocd/subcommands/rtt_cmd.py +++ b/pyocd/subcommands/rtt_cmd.py @@ -3,6 +3,8 @@ # Copyright (C) 2021 Ciro Cattuto # Copyright (C) 2021 Simon D. Levy # Copyright (C) 2022 Johan Carlsson +# Copyright (C) 2022 Samuel Dewan +# Copyright (C) 2022 Zhengji Li # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,63 +20,28 @@ # limitations under the License. import argparse -from typing import List import logging +import sys +from time import sleep +import time +from typing import List + from pyocd.core.helpers import ConnectHelper -from pyocd.core.memory_map import MemoryMap, MemoryRegion, MemoryType from pyocd.core.soc_target import SoCTarget +from pyocd.debug.rtt import RTTControlBlock, RTTUpChannel, RTTDownChannel from pyocd.subcommands.base import SubcommandBase from pyocd.utility.cmdline import convert_session_options, int_base_0 from pyocd.utility.kbhit import KBHit -from ctypes import Structure, c_char, c_int32, c_uint32, sizeof LOG = logging.getLogger(__name__) -class SEGGER_RTT_BUFFER_UP(Structure): - """@brief `SEGGER RTT Ring Buffer` target to host.""" - - _fields_ = [ - ("sName", c_uint32), - ("pBuffer", c_uint32), - ("SizeOfBuffer", c_uint32), - ("WrOff", c_uint32), - ("RdOff", c_uint32), - ("Flags", c_uint32), - ] - - -class SEGGER_RTT_BUFFER_DOWN(Structure): - """@brief `SEGGER RTT Ring Buffer` host to target.""" - - _fields_ = [ - ("sName", c_uint32), - ("pBuffer", c_uint32), - ("SizeOfBuffer", c_uint32), - ("WrOff", c_uint32), - ("RdOff", c_uint32), - ("Flags", c_uint32), - ] - - -class SEGGER_RTT_CB(Structure): - """@brief `SEGGER RTT control block` structure. """ - - _fields_ = [ - ("acID", c_char * 16), - ("MaxNumUpBuffers", c_int32), - ("MaxNumDownBuffers", c_int32), - ("aUp", SEGGER_RTT_BUFFER_UP * 3), - ("aDown", SEGGER_RTT_BUFFER_DOWN * 3), - ] - - class RTTSubcommand(SubcommandBase): """@brief `pyocd rtt` subcommand.""" NAMES = ["rtt"] - HELP = "SEGGER RTT Viewer." + HELP = "SEGGER RTT Viewer/Logger." @classmethod def get_args(cls) -> List[argparse.ArgumentParser]: @@ -87,6 +54,12 @@ def get_args(cls) -> List[argparse.ArgumentParser]: help="Start address of RTT control block search range.") rtt_options.add_argument("-s", "--size", type=int_base_0, default=None, help="Size of RTT control block search range.") + rtt_options.add_argument("--up-channel-id", type=int, default=0, + help="Up channel ID.") + rtt_options.add_argument("--down-channel-id", type=int, default=0, + help="Down channel ID.") + rtt_options.add_argument("-d", "--log-file", type=str, default=None, + help="Log file name. When specified, logging mode is enabled.") return [cls.CommonOptions.COMMON, cls.CommonOptions.CONNECT, rtt_parser] @@ -107,7 +80,9 @@ def invoke(self) -> int: frequency=self._args.frequency, blocking=(not self._args.no_wait), connect_mode=self._args.connect_mode, - options=convert_session_options(self._args.options)) + options=convert_session_options(self._args.options), + option_defaults=self._modified_option_defaults(), + ) if session is None: LOG.error("No target device available") @@ -117,41 +92,21 @@ def invoke(self) -> int: target: SoCTarget = session.board.target - memory_map: MemoryMap = target.get_memory_map() - ram_region: MemoryRegion = memory_map.get_default_region_of_type(MemoryType.RAM) - - if self._args.address is None or self._args.size is None: - rtt_range_start = ram_region.start - rtt_range_size = ram_region.length - elif ram_region.start <= self._args.address and self._args.size <= ram_region.length: - rtt_range_start = self._args.address - rtt_range_size = self._args.size - - LOG.info(f"RTT control block search range [{rtt_range_start:#08x}, {rtt_range_size:#08x}]") - - rtt_cb_addr = -1 - data = bytearray(b'0000000000') - chunk_size = 1024 - while rtt_range_size > 0: - read_size = min(chunk_size, rtt_range_size) - data += bytearray(target.read_memory_block8(rtt_range_start, read_size)) - pos = data[-(read_size + 10):].find(b"SEGGER RTT") - if pos != -1: - rtt_cb_addr = rtt_range_start + pos - 10 - break - rtt_range_start += read_size - rtt_range_size -= read_size - - if rtt_cb_addr == -1: - LOG.error("No RTT control block available") + control_block = RTTControlBlock.from_target(target, + address = self._args.address, + size = self._args.size) + control_block.start() + + if len(control_block.up_channels) < 1: + LOG.error("No up channels.") return 1 - data = target.read_memory_block8(rtt_cb_addr, sizeof(SEGGER_RTT_CB)) - rtt_cb = SEGGER_RTT_CB.from_buffer(bytearray(data)) - up_addr = rtt_cb_addr + SEGGER_RTT_CB.aUp.offset - down_addr = up_addr + sizeof(SEGGER_RTT_BUFFER_UP) * rtt_cb.MaxNumUpBuffers + LOG.info(f"{len(control_block.up_channels)} up channels and " + f"{len(control_block.down_channels)} down channels found") - LOG.info(f"_SEGGER_RTT @ {rtt_cb_addr:#08x} with {rtt_cb.MaxNumUpBuffers} aUp and {rtt_cb.MaxNumDownBuffers} aDown") + up_chan: RTTUpChannel = control_block.up_channels[self._args.up_channel_id] + up_name = up_chan.name if up_chan.name is not None else "" + LOG.info(f"Reading from up channel {self._args.up_channel_id} (\"{up_name}\")") # some targets might need this here #target.reset_and_halt() @@ -161,79 +116,17 @@ def invoke(self) -> int: # set up terminal input kb = KBHit() - # byte array to send via RTT - cmd = bytes() - - while True: - # read data from up buffers (target -> host) - data = target.read_memory_block8(up_addr, sizeof(SEGGER_RTT_BUFFER_UP)) - up = SEGGER_RTT_BUFFER_UP.from_buffer(bytearray(data)) - - if up.WrOff > up.RdOff: - """ - |oooooo|xxxxxxxxxxxx|oooooo| - 0 rdOff WrOff SizeOfBuffer - """ - data = target.read_memory_block8(up.pBuffer + up.RdOff, up.WrOff - up.RdOff) - target.write_memory(up_addr + SEGGER_RTT_BUFFER_UP.RdOff.offset, up.WrOff) - print(bytes(data).decode(), end="", flush=True) - - elif up.WrOff < up.RdOff: - """ - |xxxxxx|oooooooooooo|xxxxxx| - 0 WrOff RdOff SizeOfBuffer - """ - data = target.read_memory_block8(up.pBuffer + up.RdOff, up.SizeOfBuffer - up.RdOff) - data += target.read_memory_block8(up.pBuffer, up.WrOff) - target.write_memory(up_addr + SEGGER_RTT_BUFFER_UP.RdOff.offset, up.WrOff) - print(bytes(data).decode(), end="", flush=True) - - else: # up buffer is empty - - # try and fetch character - if not kb.kbhit(): - continue - c = kb.getch() - - if ord(c) == 8 or ord(c) == 127: # process backspace - print("\b \b", end="", flush=True) - cmd = cmd[:-1] - continue - elif ord(c) == 27: # process ESC - break - else: - print(c, end="", flush=True) - cmd += c.encode() - - # keep accumulating until we see CR or LF - if not c in "\r\n": - continue - - # SEND TO TARGET - - data = target.read_memory_block8(down_addr, sizeof(SEGGER_RTT_BUFFER_DOWN)) - down = SEGGER_RTT_BUFFER_DOWN.from_buffer(bytearray(data)) - - # compute free space in down buffer - if down.WrOff >= down.RdOff: - num_avail = down.SizeOfBuffer - (down.WrOff - down.RdOff) - else: - num_avail = down.RdOff - down.WrOff - 1 - - # wait until there's space for the entire string in the RTT down buffer - if (num_avail < len(cmd)): - continue - - # write data to down buffer (host -> target), char by char - for i in range(len(cmd)): - target.write_memory_block8(down.pBuffer + down.WrOff, cmd[i:i+1]) - down.WrOff += 1 - if down.WrOff == down.SizeOfBuffer: - down.WrOff = 0; - target.write_memory(down_addr + SEGGER_RTT_BUFFER_DOWN.WrOff.offset, down.WrOff) - - # clear it and start anew - cmd = bytes() + if self._args.log_file is None: + if len(control_block.down_channels) < 1: + LOG.error("No down channels.") + return 1 + down_chan: RTTDownChannel = control_block.down_channels[self._args.down_channel_id] + down_name = down_chan.name if down_chan.name is not None else "" + LOG.info(f"Writing to down channel {self._args.down_channel_id} (\"{down_name}\")") + + self.viewer_loop(up_chan, down_chan, kb) + else: + self.logger_loop(up_chan, kb) except KeyboardInterrupt: pass @@ -245,3 +138,67 @@ def invoke(self) -> int: kb.set_normal_term() return 0 + + def logger_loop(self, up_chan, kb): + + LOG.info("start logging ... Press any key to stop") + total_size = 0 + block_size = 0 + last_time = time.time() + + with open(self._args.log_file, 'wb') as log_file: + + while True: + # poll at most 1000 times per second to limit CPU use + sleep(0.001) + + # read data from up buffer + data = up_chan.read() + log_file.write(data) + + s = len(data) + block_size += s + total_size += s + diff = time.time() - last_time + if diff > 1.0: + print(f"Transfer rate: {block_size / 1000:.1f} KByte/s; Bytes written: {total_size / 1000:.0f} KByte", end="\r") + block_size = 0 + last_time = time.time() + + # try to fetch character + if kb.kbhit(): + break + + def viewer_loop(self, up_chan, down_chan, kb): + # byte array to send via RTT + cmd = bytes() + + while True: + # poll at most 1000 times per second to limit CPU use + sleep(0.001) + + # read data from up buffer 0 (target -> host) and write to + # stdout + up_data: bytes = up_chan.read() + sys.stdout.buffer.write(up_data) + sys.stdout.buffer.flush() + + # try to fetch character + if kb.kbhit(): + c: str = kb.getch() + + if ord(c) == 27: # process ESC + break + elif c.isprintable() or c == '\n': + print(c, end="", flush=True) + + # add char to buffer + cmd += c.encode("utf-8") + + # write buffer to target + if not cmd: + continue + + # write cmd buffer to down buffer 0 (host -> target) + bytes_out = down_chan.write(cmd) + cmd = cmd[bytes_out:] diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 2d9bb2555..45382983f 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -101,6 +101,7 @@ from . import target_musca_s1 from . import target_LPC5526Jxxxxx from . import target_LPC55S69Jxxxxx +from . import target_LPC55S16 from . import target_LPC55S36 from . import target_LPC55S28Jxxxxx from . import target_M251 @@ -121,6 +122,10 @@ from . import target_MPS3_AN522 from . import target_MPS3_AN540 from . import target_RP2040 +from . import target_ytm32b1ld0 +from . import target_ytm32b1le0 +from . import target_ytm32b1me0 +from . import target_ytm32b1md1 ## @brief Dictionary of all builtin targets. # @@ -235,6 +240,7 @@ 'musca_s1' : target_musca_s1.MuscaS1, 'lpc5526' : target_LPC5526Jxxxxx.LPC5526, 'lpc55s69' : target_LPC55S69Jxxxxx.LPC55S69, + 'lpc55s16' : target_LPC55S16.LPC55S16, 'lpc55s36' : target_LPC55S36.LPC55S36, 'lpc55s28' : target_LPC55S28Jxxxxx.LPC55S28, 'cy8c64xx_cm0_full_flash' : target_CY8C64xx.cy8c64xx_cm0_full_flash, @@ -279,4 +285,8 @@ 'rp2040' : target_RP2040.RP2040Core0, 'rp2040_core0' : target_RP2040.RP2040Core0, 'rp2040_core1' : target_RP2040.RP2040Core1, + 'ytm32b1ld0': target_ytm32b1ld0.YTM32B1LD0, + 'ytm32b1le0': target_ytm32b1le0.YTM32B1LE0, + 'ytm32b1me0': target_ytm32b1me0.YTM32B1ME0, + 'ytm32b1md1': target_ytm32b1md1.YTM32B1MD1, } diff --git a/pyocd/target/builtin/target_LPC55S16.py b/pyocd/target/builtin/target_LPC55S16.py new file mode 100644 index 000000000..2bc307b9f --- /dev/null +++ b/pyocd/target/builtin/target_LPC55S16.py @@ -0,0 +1,183 @@ +# pyOCD debugger +# Copyright (c) 2022 PyOCD Authors +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ..family.target_lpc5500 import LPC5500Family +from ...core.memory_map import (FlashRegion, RamRegion, RomRegion, MemoryMap) +from ...debug.svd.loader import SVDFile + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b580, 0xf2c00004, 0xf6420000, 0xf84961e0, 0xf2401000, 0xf2c52000, 0x21000000, 0x1080f8c0, + 0x1084f8c0, 0x1180f8c0, 0x71fbf647, 0xf6406001, 0x21ff6004, 0x0000f2c5, 0x01def2cc, 0xf04f6001, + 0x210240a0, 0xf2407001, 0xf2c00008, 0x44480000, 0xf860f000, 0xbf182800, 0xbd802001, 0x47702000, + 0xf240b580, 0xf2c00008, 0xf2460000, 0x4448636c, 0xf6c62100, 0xf44f3365, 0xf0003276, 0x2800f851, + 0x2001bf18, 0xbf00bd80, 0xf020b580, 0xf2404170, 0xf2c00008, 0xf2460000, 0x4448636c, 0x3365f6c6, + 0x7200f44f, 0xf83cf000, 0xbf182800, 0xbd802001, 0x460bb580, 0x4170f020, 0x0008f240, 0x0000f2c0, + 0xf5b34448, 0xbf987f00, 0x7300f44f, 0xf82ef000, 0xbf182800, 0xbd802001, 0x460cb5b0, 0xf0204605, + 0x46114070, 0xf0004622, 0x2800f872, 0x4425bf08, 0xbdb04628, 0x460ab580, 0x4170f020, 0x0008f240, + 0x0000f2c0, 0xf0004448, 0x2800f817, 0x2001bf18, 0x0000bd80, 0x018cf245, 0x3100f2c1, 0x47086809, + 0x3c4ff64a, 0x3c00f2c1, 0xbf004760, 0x3cb5f64a, 0x3c00f2c1, 0xbf004760, 0x3381f64a, 0x3300f2c1, + 0xbf004718, 0x4ca5f64a, 0x3c00f2c1, 0xbf004760, 0x03a0f245, 0x3300f2c1, 0x4718681b, 0x01a4f245, + 0x3100f2c1, 0x47086809, 0x01a8f245, 0x3100f2c1, 0x47086809, 0x03acf245, 0x3300f2c1, 0x4718681b, + 0x0cb4f245, 0x3c00f2c1, 0xc000f8dc, 0xbf004760, 0x02b8f245, 0x3200f2c1, 0x47106812, 0x02bcf245, + 0x3200f2c1, 0x47106812, 0x03c0f245, 0x3300f2c1, 0x4718681b, 0x02b0f245, 0x3200f2c1, 0x47106812, + 0x0cc8f245, 0x3c00f2c1, 0xc000f8dc, 0xea404760, 0xb5100301, 0xd10f079b, 0xd30d2a04, 0xc908c810, + 0x429c1f12, 0xba20d0f8, 0x4288ba19, 0x2001d901, 0xf04fbd10, 0xbd1030ff, 0x07d3b11a, 0x1c52d003, + 0x2000e007, 0xf810bd10, 0xf8113b01, 0x1b1b4b01, 0xf810d107, 0xf8113b01, 0x1b1b4b01, 0x1e92d101, + 0x4618d1f1, 0x0000bd10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000061, + 'pc_program_page': 0x200000b5, + 'pc_erase_sector': 0x2000008d, + 'pc_eraseAll': 0x20000065, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000228, + 'begin_stack' : 0x20001670, + 'end_stack' : 0x20000670, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x200, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000270, + 0x20000470 + ], + 'min_program_length' : 0x200, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x228, + 'rw_start': 0x22c, + 'rw_size': 0x4, + 'zi_start': 0x230, + 'zi_size': 0x40, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x3d800, + 'sector_sizes': ( + (0x0, 0x200), + ) +} + +S_FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b580, 0xf2c00004, 0xf6420000, 0xf84961e0, 0xf2401000, 0xf2c52000, 0x21000000, 0x1080f8c0, + 0x1084f8c0, 0x1180f8c0, 0x71fbf647, 0xf6406001, 0x21ff6004, 0x0000f2c5, 0x01def2cc, 0xf04f6001, + 0x210240a0, 0xf2407001, 0xf2c00008, 0x44480000, 0xf860f000, 0xbf182800, 0xbd802001, 0x47702000, + 0xf240b580, 0xf2c00008, 0xf2460000, 0x4448636c, 0xf6c62100, 0xf44f3365, 0xf0003276, 0x2800f851, + 0x2001bf18, 0xbf00bd80, 0xf020b580, 0xf2404170, 0xf2c00008, 0xf2460000, 0x4448636c, 0x3365f6c6, + 0x7200f44f, 0xf83cf000, 0xbf182800, 0xbd802001, 0x460bb580, 0x4170f020, 0x0008f240, 0x0000f2c0, + 0xf5b34448, 0xbf987f00, 0x7300f44f, 0xf82ef000, 0xbf182800, 0xbd802001, 0x460cb5b0, 0xf0204605, + 0x46114070, 0xf0004622, 0x2800f872, 0x4425bf08, 0xbdb04628, 0x460ab580, 0x4170f020, 0x0008f240, + 0x0000f2c0, 0xf0004448, 0x2800f817, 0x2001bf18, 0x0000bd80, 0x018cf245, 0x3100f2c1, 0x47086809, + 0x3c4ff64a, 0x3c00f2c1, 0xbf004760, 0x3cb5f64a, 0x3c00f2c1, 0xbf004760, 0x3381f64a, 0x3300f2c1, + 0xbf004718, 0x4ca5f64a, 0x3c00f2c1, 0xbf004760, 0x03a0f245, 0x3300f2c1, 0x4718681b, 0x01a4f245, + 0x3100f2c1, 0x47086809, 0x01a8f245, 0x3100f2c1, 0x47086809, 0x03acf245, 0x3300f2c1, 0x4718681b, + 0x0cb4f245, 0x3c00f2c1, 0xc000f8dc, 0xbf004760, 0x02b8f245, 0x3200f2c1, 0x47106812, 0x02bcf245, + 0x3200f2c1, 0x47106812, 0x03c0f245, 0x3300f2c1, 0x4718681b, 0x02b0f245, 0x3200f2c1, 0x47106812, + 0x0cc8f245, 0x3c00f2c1, 0xc000f8dc, 0xea404760, 0xb5100301, 0xd10f079b, 0xd30d2a04, 0xc908c810, + 0x429c1f12, 0xba20d0f8, 0x4288ba19, 0x2001d901, 0xf04fbd10, 0xbd1030ff, 0x07d3b11a, 0x1c52d003, + 0x2000e007, 0xf810bd10, 0xf8113b01, 0x1b1b4b01, 0xf810d107, 0xf8113b01, 0x1b1b4b01, 0x1e92d101, + 0x4618d1f1, 0x0000bd10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000061, + 'pc_program_page': 0x200000b5, + 'pc_erase_sector': 0x2000008d, + 'pc_eraseAll': 0x20000065, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000228, + 'begin_stack' : 0x20001670, + 'end_stack' : 0x20000670, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x200, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000270, + 0x20000470 + ], + 'min_program_length' : 0x200, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x228, + 'rw_start': 0x22c, + 'rw_size': 0x4, + 'zi_start': 0x230, + 'zi_size': 0x40, + + # Flash information + 'flash_start': 0x10000000, + 'flash_size': 0x3d800, + 'sector_sizes': ( + (0x0, 0x200), + ) +} + + +class LPC55S16(LPC5500Family): + + MEMORY_MAP = MemoryMap( + FlashRegion(name='nsflash', start=0x00000000, length=0x0003d800, access='rx', + page_size=0x200, + sector_size=0x200, + is_boot_memory=True, + are_erased_sectors_readable=False, + algo=FLASH_ALGO), + RomRegion( name='nsrom', start=0x03000000, length=0x00020000, access='rx'), + RamRegion( name='nscoderam', start=0x04000000, length=0x00004000, access='rwx', + default=False), + FlashRegion(name='sflash', start=0x10000000, length=0x0003d800, access='rx', + page_size=0x200, + sector_size=0x200, + is_boot_memory=True, + are_erased_sectors_readable=False, + algo=S_FLASH_ALGO, + alias='nsflash'), + RomRegion( name='srom', start=0x13000000, length=0x00020000, access='srx', + alias='nsrom'), + RamRegion( name='scoderam', start=0x14000000, length=0x00004000, access='srwx', + alias='nscoderam', + default=False), + RamRegion( name='nsram', start=0x20000000, length=0x00010000, access='rwx'), + RamRegion( name='sram', start=0x30000000, length=0x00010000, access='srwx', + alias='nsram'), + ) + + def __init__(self, session): + super(LPC55S16, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("LPC55S16.xml") diff --git a/pyocd/target/builtin/target_ytm32b1ld0.py b/pyocd/target/builtin/target_ytm32b1ld0.py new file mode 100644 index 000000000..e18042619 --- /dev/null +++ b/pyocd/target/builtin/target_ytm32b1ld0.py @@ -0,0 +1,141 @@ +# pyOCD debugger +# Copyright (c) 2022 Yuntu Microelectronics +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) + +MAIN_FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x483c4601, 0x4a3b7e40, 0x29007650, 0x76d1d000, 0x4838bf00, 0x22207e40, 0x28004010, 0x4835d0f9, + 0x22167e40, 0x28004010, 0x2001d001, 0x20004770, 0xb570e7fc, 0x460d4604, 0x482f4616, 0x6008492f, + 0x6008482f, 0x68404608, 0x00400840, 0x482d6048, 0x6088492d, 0x6088482d, 0x6088482d, 0x6088482d, + 0x48286088, 0x482c6088, 0x482c6008, 0x482c6008, 0x482c6008, 0x60086008, 0x60084827, 0x6800481d, + 0x05892101, 0x491b4388, 0x20006008, 0xffb8f7ff, 0x4601bd70, 0x47702000, 0x4823b510, 0x60082100, + 0xf7ff2041, 0xbd10ffad, 0x4604b510, 0x6020481f, 0xf7ff2040, 0xbd10ffa5, 0xb082b5f7, 0x460d4604, + 0x46279e04, 0x90012004, 0xbf009500, 0xc701ce01, 0xf7ff2020, 0x2800ff95, 0x2001d002, 0xbdf0b005, + 0x98009901, 0x90001a40, 0x28009800, 0x2000dcee, 0x0000e7f4, 0x40020000, 0x0000b631, 0x40052000, + 0x0000c278, 0x0001001e, 0x40064000, 0x4001001e, 0x8001001e, 0xc001001e, 0x0001220c, 0x4001220c, + 0x8001220c, 0xc001220c, 0x00001234, 0x12345678, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000037, + 'pc_unInit': 0x20000097, + 'pc_program_page': 0x200000bd, + 'pc_erase_sector': 0x200000ad, + 'pc_eraseAll': 0x2000009d, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000130, + 'begin_stack' : 0x20001340, + 'end_stack' : 0x20000340, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x100, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000140, + 0x20000240 + ], + 'min_program_length' : 0x100, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x130, + 'rw_start': 0x134, + 'rw_size': 0x4, + 'zi_start': 0x138, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x10000, + 'sector_sizes': ( + (0x0, 0x200), + ) +} + +DATA_FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x483e4601, 0x4a3d7e40, 0x29007650, 0x76d1d000, 0x483abf00, 0x22207e40, 0x28004010, 0x4837d0f9, + 0x22167e40, 0x28004010, 0x2001d001, 0x20004770, 0xb570e7fc, 0x460d4604, 0x48314616, 0x60084931, + 0x60084831, 0x68404608, 0x00400840, 0x482f6048, 0x6088492f, 0x6088482f, 0x6088482f, 0x6088482f, + 0x482a6088, 0x482e6088, 0x482e6008, 0x482e6008, 0x482e6008, 0x60086008, 0x60084829, 0x6800481f, + 0x05892101, 0x491d4388, 0x48296008, 0x20006388, 0xffb6f7ff, 0x4601bd70, 0x4a182000, 0x47706390, + 0x4824b510, 0x60082100, 0xf7ff2041, 0xbd10ffa9, 0x4604b510, 0x60204820, 0xf7ff2040, 0xbd10ffa1, + 0xb082b5f7, 0x460d4604, 0x46279e04, 0x90012004, 0xbf009500, 0xc701ce01, 0xf7ff2020, 0x2800ff91, + 0x2001d002, 0xbdf0b005, 0x98009901, 0x90001a40, 0x28009800, 0x2000dcee, 0x0000e7f4, 0x40020000, + 0x0000b631, 0x40052000, 0x0000c278, 0x0001001e, 0x40064000, 0x4001001e, 0x8001001e, 0xc001001e, + 0x0001220c, 0x4001220c, 0x8001220c, 0xc001220c, 0x0065fe9a, 0x00001234, 0x12345678, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000037, + 'pc_unInit': 0x2000009b, + 'pc_program_page': 0x200000c5, + 'pc_erase_sector': 0x200000b5, + 'pc_eraseAll': 0x200000a5, + + 'static_base' : 0x20000000 + 0x00000004 + 0x0000013c, + 'begin_stack' : 0x20001350, + 'end_stack' : 0x20000350, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x100, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000150, + 0x20000250 + ], + 'min_program_length' : 0x100, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x13c, + 'rw_start': 0x140, + 'rw_size': 0x4, + 'zi_start': 0x144, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x400200, + 'flash_size': 0x800, + 'sector_sizes': ( + (0x400200, 0x200), + ) +} + +class YTM32B1LD0(CoreSightTarget): + + VENDOR = "Yuntu Microelectronics" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x00000000, length=0x10000, blocksize=0x200, is_boot_memory=True, algo=MAIN_FLASH_ALGO), + FlashRegion(start=0x00400200, length=0x800, blocksize=0x200, is_boot_memory=False, algo=DATA_FLASH_ALGO), + RamRegion( start=0x20000000, length=0x2000) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) diff --git a/pyocd/target/builtin/target_ytm32b1le0.py b/pyocd/target/builtin/target_ytm32b1le0.py new file mode 100644 index 000000000..cbb307754 --- /dev/null +++ b/pyocd/target/builtin/target_ytm32b1le0.py @@ -0,0 +1,140 @@ +# pyOCD debugger +# Copyright (c) 2022 Yuntu Microelectronics +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) + +MAIN_FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x48414601, 0x4a406840, 0x29006050, 0x483fd005, 0x60104a3f, 0x4a3cb2c8, 0xbf006090, 0x6840483a, + 0x40102280, 0xd0f92800, 0x68404837, 0x4010220e, 0xd0012800, 0x47702001, 0xe7fc2000, 0x4604b570, + 0x4616460d, 0x69004833, 0x43082101, 0x61084931, 0x49324831, 0x48326008, 0x46086008, 0x08406840, + 0x60480040, 0x492b2001, 0xbf006048, 0x68c04829, 0xd1fb2801, 0x49272000, 0xf7ff6008, 0xbd70ffc1, + 0x20004601, 0xb5104770, 0x48264604, 0x20106020, 0xffb6f7ff, 0xb510bd10, 0x20012400, 0xf7ff0700, + 0x4604fff2, 0xf7ff4820, 0x1904ffee, 0xf7ff481f, 0x1904ffea, 0xf7ff481e, 0x1904ffe6, 0x2100481d, + 0x20126008, 0xff9cf7ff, 0xbd101900, 0xb082b5f7, 0x460d4604, 0x46279e04, 0x90012004, 0xbf009500, + 0xc701ce01, 0xf7ff2002, 0x2800ff8b, 0x2001d002, 0xbdf0b005, 0x98009901, 0x90001a40, 0x28009800, + 0xbf00d1ee, 0x0000e7f4, 0x40020000, 0xfd9573f5, 0x40020200, 0x40064000, 0x0000b631, 0x40052000, + 0x0000c278, 0x12345678, 0x10000200, 0x10000400, 0x10000600, 0x00001234, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000041, + 'pc_unInit': 0x20000085, + 'pc_program_page': 0x200000d1, + 'pc_erase_sector': 0x2000008b, + 'pc_eraseAll': 0x2000009b, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000138, + 'begin_stack' : 0x20002150, + 'end_stack' : 0x20001150, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x8, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000140, + 0x20000148 + ], + 'min_program_length' : 0x8, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x138, + 'rw_start': 0x13c, + 'rw_size': 0x4, + 'zi_start': 0x140, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x20000, + 'sector_sizes': ( + (0x0, 0x200), + ) +} +DATA_FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x48414601, 0x4a406840, 0x29006050, 0x483fd005, 0x60104a3f, 0x4a3cb2c8, 0xbf006090, 0x6840483a, + 0x40102280, 0xd0f92800, 0x68404837, 0x4010220e, 0xd0012800, 0x47702001, 0xe7fc2000, 0x4604b570, + 0x4616460d, 0x69004833, 0x43082101, 0x61084931, 0x49324831, 0x48326008, 0x46086008, 0x08406840, + 0x60480040, 0x492b2001, 0xbf006048, 0x68c04829, 0xd1fb2801, 0x49272000, 0xf7ff6008, 0xbd70ffc1, + 0x20004601, 0xb5104770, 0x21004826, 0x20126008, 0xffb6f7ff, 0xb570bd10, 0x24004605, 0x07002001, + 0xfff9f7ff, 0x48204604, 0xfff5f7ff, 0x481f1904, 0xfff1f7ff, 0x481e1904, 0xffedf7ff, 0x48191904, + 0x60082100, 0xf7ff2012, 0x1900ff9b, 0xb5f7bd70, 0x4604b082, 0x9e04460d, 0x20044627, 0x95009001, + 0xce01bf00, 0x2002c701, 0xff8af7ff, 0xd0022800, 0xb0052001, 0x9901bdf0, 0x1a409800, 0x98009000, + 0xdcee2800, 0xe7f42000, 0x40020000, 0xfd9573f5, 0x40020200, 0x40064000, 0x0000b631, 0x40052000, + 0x0000c278, 0x00001234, 0x10000200, 0x10000400, 0x10000600, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000041, + 'pc_unInit': 0x20000085, + 'pc_program_page': 0x200000d3, + 'pc_erase_sector': 0x2000009b, + 'pc_eraseAll': 0x2000008b, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000134, + 'begin_stack' : 0x20002150, + 'end_stack' : 0x20001150, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x8, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000140, + 0x20000148 + ], + 'min_program_length' : 0x8, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x134, + 'rw_start': 0x138, + 'rw_size': 0x4, + 'zi_start': 0x13c, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x10000000, + 'flash_size': 0x800, + 'sector_sizes': ( + (0x10000000, 0x200), + ) +} + +class YTM32B1LE0(CoreSightTarget): + + VENDOR = "Yuntu Microelectronics" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x0000, length=0x10000, blocksize=0x200, is_boot_memory=True, algo=MAIN_FLASH_ALGO), + FlashRegion( start=0x10000000, length=0x800, blocksize=0x200, is_boot_memory=False, algo=DATA_FLASH_ALGO), + RamRegion( start=0x20000000, length=0x2000) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) diff --git a/pyocd/target/builtin/target_ytm32b1md1.py b/pyocd/target/builtin/target_ytm32b1md1.py new file mode 100644 index 000000000..05eb78edf --- /dev/null +++ b/pyocd/target/builtin/target_ytm32b1md1.py @@ -0,0 +1,84 @@ +# pyOCD debugger +# Copyright (c) 2022 Yuntu Microelectronics +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x48414601, 0x4a406840, 0x29006050, 0x483fd005, 0x60104a3f, 0x4a3cb2c8, 0xbf006090, 0x6840483a, + 0x40102280, 0xd0f92800, 0x68404837, 0x4010220c, 0xd0012800, 0x47702001, 0xe7fc2000, 0x4604b570, + 0x4616460d, 0x69004833, 0x43082101, 0x61084931, 0x49324831, 0x48326008, 0x46086008, 0x08406840, + 0x60480040, 0x492b2003, 0xbf006008, 0x68804829, 0x0f800780, 0xd1f92803, 0x49262001, 0xbf006048, + 0x68c04824, 0xd1fb2801, 0x4822bf00, 0x21046880, 0x28044008, 0x2000d1f9, 0x6008491e, 0x491a4821, + 0x20006008, 0xffacf7ff, 0x4601bd70, 0x47702000, 0x201eb510, 0xffa4f7ff, 0xb510bd10, 0x481a4604, + 0x20106020, 0xff9cf7ff, 0xb5f7bd10, 0x4606b082, 0x9c04460f, 0x20084635, 0x97009001, 0xcc01bf00, + 0xcc01c501, 0x2002c501, 0xff8af7ff, 0xd0022800, 0xb0052001, 0x9901bdf0, 0x1a409800, 0x98009000, + 0xdcec2800, 0xe7f42000, 0x40010000, 0xfd9573f5, 0x40010200, 0x4007c000, 0x0000b631, 0x4006a000, + 0x0000c278, 0x00308300, 0x12345678, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000041, + 'pc_unInit': 0x200000af, + 'pc_program_page': 0x200000cf, + 'pc_erase_sector': 0x200000bf, + 'pc_eraseAll': 0x200000b5, + + 'static_base' : 0x20000000 + 0x00000004 + 0x0000012c, + 'begin_stack' : 0x20002150, + 'end_stack' : 0x20001150, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x8, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000140, + 0x20000148 + ], + 'min_program_length' : 0x8, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x12c, + 'rw_start': 0x130, + 'rw_size': 0x4, + 'zi_start': 0x134, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x80000, + 'sector_sizes': ( + (0x0, 0x400), + ) +} +class YTM32B1MD1(CoreSightTarget): + + VENDOR = "Yuntu Microelectronics" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x00000000, length=0x80000, blocksize=0x400, is_boot_memory=True, algo=FLASH_ALGO), + RamRegion( start=0x20000000, length=0x2000) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) diff --git a/pyocd/target/builtin/target_ytm32b1me0.py b/pyocd/target/builtin/target_ytm32b1me0.py new file mode 100644 index 000000000..3e84fe773 --- /dev/null +++ b/pyocd/target/builtin/target_ytm32b1me0.py @@ -0,0 +1,154 @@ +# pyOCD debugger +# Copyright (c) 2022 Yuntu Microelectronics +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) + +MAIN_FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x48414601, 0x4a406840, 0x29006050, 0x483fd005, 0x60104a3f, 0x4a3cb2c8, 0xbf006090, 0x6840483a, + 0x40102280, 0xd0f92800, 0x68404837, 0x4010220c, 0xd0012800, 0x47702001, 0xe7fc2000, 0x4604b570, + 0x4616460d, 0x69004833, 0x43082101, 0x61084931, 0x49324831, 0x48326008, 0x46086008, 0x08406840, + 0x60480040, 0x492b2003, 0xbf006008, 0x68804829, 0x0f800780, 0xd1f92803, 0x49262001, 0xbf006048, + 0x68c04824, 0xd1fb2801, 0x4822bf00, 0x21046880, 0x28044008, 0x2000d1f9, 0x6008491e, 0x491a4821, + 0x20006008, 0xffacf7ff, 0x4601bd70, 0x47702000, 0x201eb510, 0xffa4f7ff, 0xb510bd10, 0x481a4604, + 0x20106020, 0xff9cf7ff, 0xb5f7bd10, 0x4606b082, 0x9c04460f, 0x20084635, 0x97009001, 0xcc01bf00, + 0xcc01c501, 0x2002c501, 0xff8af7ff, 0xd0022800, 0xb0052001, 0x9901bdf0, 0x1a409800, 0x98009000, + 0xdcec2800, 0xe7f42000, 0x40010000, 0xfd9573f5, 0x40010200, 0x4007c000, 0x0000b631, 0x4006a000, + 0x0000c278, 0x00308200, 0x12345678, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000041, + 'pc_unInit': 0x200000af, + 'pc_program_page': 0x200000cf, + 'pc_erase_sector': 0x200000bf, + 'pc_eraseAll': 0x200000b5, + + 'static_base' : 0x20000000 + 0x00000004 + 0x0000012c, + 'begin_stack' : 0x20002150, + 'end_stack' : 0x20001150, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x8, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000140, + 0x20000148 + ], + 'min_program_length' : 0x8, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x12c, + 'rw_start': 0x130, + 'rw_size': 0x4, + 'zi_start': 0x134, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x100000, + 'sector_sizes': ( + (0x0, 0x800), + ) +} +DATA_FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x48414601, 0x4a406840, 0x29006050, 0x483fd005, 0x60104a3f, 0x4a3cb2c8, 0xbf006090, 0x6840483a, + 0x40102280, 0xd0f92800, 0x68404837, 0x4010220c, 0xd0012800, 0x47702001, 0xe7fc2000, 0x4604b570, + 0x4616460d, 0x69004833, 0x43082101, 0x61084931, 0x49324831, 0x48326008, 0x46086008, 0x08406840, + 0x60480040, 0x492b2003, 0xbf006008, 0x68804829, 0x0f800780, 0xd1f92803, 0x49262001, 0xbf006048, + 0x68c04824, 0xd1fb2801, 0x4822bf00, 0x21046880, 0x28044008, 0x2000d1f9, 0x6008491e, 0x491a4821, + 0x20006008, 0xffacf7ff, 0x4601bd70, 0x47702000, 0x201eb510, 0xffa4f7ff, 0xb510bd10, 0x481a4604, + 0x20106020, 0xff9cf7ff, 0xb5f7bd10, 0x4606b082, 0x9c04460f, 0x20084635, 0x97009001, 0xcc01bf00, + 0xcc01c501, 0x2002c501, 0xff8af7ff, 0xd0022800, 0xb0052001, 0x9901bdf0, 0x1a409800, 0x98009000, + 0xdcec2800, 0xe7f42000, 0x40010000, 0xfd9573f5, 0x40010200, 0x4007c000, 0x0000b631, 0x4006a000, + 0x0000c278, 0x00308200, 0x12345678, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000041, + 'pc_unInit': 0x200000af, + 'pc_program_page': 0x200000cf, + 'pc_erase_sector': 0x200000bf, + 'pc_eraseAll': 0x200000b5, + + 'static_base' : 0x20000000 + 0x00000004 + 0x0000012c, + 'begin_stack' : 0x20002150, + 'end_stack' : 0x20001150, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x8, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000140, + 0x20000148 + ], + 'min_program_length' : 0x8, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x12c, + 'rw_start': 0x130, + 'rw_size': 0x4, + 'zi_start': 0x134, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x100000, + 'flash_size': 0x40000, + 'sector_sizes': ( + (0x100000, 0x400), + ) +} + +class YTM32B1ME0(CoreSightTarget): + + VENDOR = "YTMicro" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x00000000, length=0x100000, blocksize=0x800, is_boot_memory=True, algo=MAIN_FLASH_ALGO), + FlashRegion( start=0x00100000, length=0x040000, blocksize=0x400, is_boot_memory=False, algo=DATA_FLASH_ALGO), + RamRegion( start=0x20000000, length=0x10000) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + + def create_init_sequence(self): + # Insert init task to correct the ROM table base address value that incorrectly has the + # P (preset) bit 0 cleared in hardware. + + def fixup_rom_base(): + self.aps[0].rom_addr = 0xE00FF000 + self.aps[0].has_rom_table = True + + seq = super().create_init_sequence() + seq.wrap_task('discovery', + lambda seq: seq.insert_after('create_aps', ('fixup_rom_base', fixup_rom_base)) + ) + return seq diff --git a/pyocd/target/family/__init__.py b/pyocd/target/family/__init__.py index 58858e426..8b650cfaf 100644 --- a/pyocd/target/family/__init__.py +++ b/pyocd/target/family/__init__.py @@ -22,6 +22,7 @@ from . import target_kinetis from . import target_lpc5500 from . import target_nRF52 +from . import target_nRF91 class FamilyInfo(NamedTuple): """@brief Container for family matching information.""" @@ -38,8 +39,8 @@ class FamilyInfo(NamedTuple): # present), or the 'Dname' or 'Dvariant' part numbers. The comparisons are performed in order from # specific to general, starting with the part number. FAMILIES = [ - FamilyInfo("NXP", re.compile(r'LPC55.?[0-9]{2}.*'), target_lpc5500.LPC5500Family ), FamilyInfo("NXP", re.compile(r'MIMXRT[0-9]{4}.*'), target_imxrt.IMXRT ), FamilyInfo("NXP", re.compile(r'MK[LEVWS]?.*'), target_kinetis.Kinetis ), FamilyInfo("Nordic Semiconductor", re.compile(r'nRF52[0-9]+.*'), target_nRF52.NRF52 ), + FamilyInfo("Nordic Semiconductor", re.compile(r'nRF91[0-9]+.*'), target_nRF91.NRF91 ), ] diff --git a/pyocd/target/family/target_nRF52.py b/pyocd/target/family/target_nRF52.py index ed834c5d1..9131afe7d 100644 --- a/pyocd/target/family/target_nRF52.py +++ b/pyocd/target/family/target_nRF52.py @@ -1,6 +1,7 @@ # pyOCD debugger # Copyright (c) 2006-2013 Arm Limited # Copyright (c) 2019 Monadnock Systems Ltd. +# Copyright (c) 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,6 +52,28 @@ LOG = logging.getLogger(__name__) +def word_to_bytes(wrd): + result = [] + for i in range(4): + result.append((wrd >> (8*i)) & 0xFF) + return bytes(result) + +PACKAGE = { + 0x2004 : "QI", + 0x2000 : "QF", + 0x2005 : "CK" +} + +HARDENED_APPROTECT_REVISIONS = { + 0x52805 : "B0", + 0x52810 : "E0", + 0x52811 : "B0", + 0x52820 : "D0", + 0x52833 : "B0", + 0x52832 : "G0", + 0x52840 : "F0" +} + class NRF52(CoreSightTarget): @@ -59,6 +82,7 @@ class NRF52(CoreSightTarget): def __init__(self, session, memory_map=None): super(NRF52, self).__init__(session, memory_map) self.ctrl_ap = None + self.hardened_approtect = True def create_init_sequence(self): seq = super(NRF52, self).create_init_sequence() @@ -71,6 +95,12 @@ def create_init_sequence(self): ('check_flash_security', self.check_flash_security), ) ) + seq.wrap_task('discovery', + lambda seq: seq.insert_after('create_cores', + ('check_part_info', self.check_part_info), + ('persist_unlock', self.persist_unlock), + ) + ) return seq @@ -104,11 +134,17 @@ def check_flash_security(self): # Cached badness from create_ap run during AP lockout prevents create_cores from # succeeding. self._discoverer._create_1_ap(AHB_AP_NUM) + else: LOG.warning("%s APPROTECT enabled: not automatically unlocking", self.part_number) else: LOG.info("%s not in secure state", self.part_number) + def persist_unlock(self): + if self.session.options.get('auto_unlock') and self.hardened_approtect: + # Write HwDisabled to UICR.APPROTECT + self.write_uicr(0x10001208, 0x5A) + def is_locked(self): status = self.ctrl_ap.read_reg(CTRL_AP_APPROTECTSTATUS) return status == CTRL_AP_APPROTECTSTATUS_ENABLED @@ -130,3 +166,38 @@ def mass_erase(self): self.ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_NORESET) self.ctrl_ap.write_reg(CTRL_AP_ERASEALL, CTRL_AP_ERASEALL_NOOPERATION) return True + + def write_uicr(self, addr: int, value: int): + current_value = self.read32(addr) + if ((current_value & value) != value) and (current_value != 0xFFFFFFFF): + raise exceptions.TargetError("cannot write UICR value, mass_erase needed") + + self.write32(0x4001E504, 1) # NVMC.CONFIG = WriteEnable + self._wait_nvmc_ready() + self.write32(addr, value) + self._wait_nvmc_ready() + self.write32(0x4001E504, 0) # NVMC.CONFIG = ReadOnly + self._wait_nvmc_ready() + + def _wait_nvmc_ready(self): + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + if self.read32(0x4001E400) != 0x00000000: # NVMC.READY != BUSY + break + else: + raise exceptions.TargetError("wait for NVMC timed out") + + def check_part_info(self): + partno = self.read32(0x10000100) + variant = self.read32(0x10000104) + variant = word_to_bytes(variant)[::-1].decode('ASCII', errors='ignore') + build_code = variant[2:] + variant = variant[:2] + package = self.read32(0x10000108) + package = PACKAGE.get(package, "") + + hardened_approtect_min_revision = HARDENED_APPROTECT_REVISIONS.get(partno, None) + if hardened_approtect_min_revision and hardened_approtect_min_revision > build_code: + self.hardened_approtect = False + + LOG.info(f"This appears to be an nRF{partno:X} {package}{variant} {build_code}") diff --git a/pyocd/target/family/target_nRF91.py b/pyocd/target/family/target_nRF91.py new file mode 100644 index 000000000..aa77fd22a --- /dev/null +++ b/pyocd/target/family/target_nRF91.py @@ -0,0 +1,536 @@ +# pyOCD debugger +# Copyright (c) 2006-2013 Arm Limited +# Copyright (c) 2019 Monadnock Systems Ltd. +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +import logging +from time import sleep +import os +import re +from zipfile import ZipFile +from tempfile import TemporaryDirectory +from intelhex import IntelHex + +from ...core import exceptions +from ...core.target import Target +from ...coresight.coresight_target import CoreSightTarget +from ...flash.eraser import FlashEraser +from ...flash.file_programmer import FileProgrammer +from ...utility.timeout import Timeout +from ...utility.progress import print_progress + +from typing import (Callable, Optional, TYPE_CHECKING, Union) +ProgressCallback = Callable[[Union[int, float]], None] + +if TYPE_CHECKING: + from ...core.session import Session + +AHB_AP_NUM = 0x0 +APB_AP_NUM = 0x3 +CTRL_AP_NUM = 0x4 + +CTRL_AP_RESET = 0x000 +CTRL_AP_ERASEALL = 0x004 +CTRL_AP_ERASEALLSTATUS = 0x008 +CTRL_AP_APPROTECTSTATUS = 0x00C +CTRL_AP_ERASEPROTECTSTATUS = 0x018 +CTRL_AP_ERASEPROTECTDISABLE = 0x01C +CTRL_AP_MAILBOX_TXDATA = 0x020 +CTRL_AP_MAILBOX_TXSTATUS = 0x024 +CTRL_AP_MAILBOX_RXDATA = 0x028 +CTRL_AP_MAILBOX_RXSTATUS = 0x02C +CTRL_AP_IDR = 0x0FC + +CTRL_AP_ERASEALLSTATUS_READY = 0x0 +CTRL_AP_ERASEALLSTATUS_BUSY = 0x1 + +CTRL_AP_APPROTECTSTATUS_APPROTECT_MSK = 0x1 +CTRL_AP_APPROTECTSTATUS_SECUREAPPROTECT_MSK = 0x2 +CTRL_AP_ERASEPROTECTSTATUS_MSK = 0x1 + +CTRL_AP_MAILBOX_STATUS_NODATAPENDING = 0x0 +CTRL_AP_MAILBOX_STATUS_DATAPENDING = 0x1 + +CTRL_AP_RESET_NORESET = 0x0 +CTRL_AP_RESET_RESET = 0x1 + +CTRL_AP_ERASEALL_NOOPERATION = 0x0 +CTRL_AP_ERASEALL_ERASE = 0x1 + +CTRL_IDR_EXPECTED = 0x12880000 + +MASS_ERASE_TIMEOUT = 30.0 + +FAULT_EVENT = 0x4002A100 +COMMAND_EVENT = 0x4002A108 +DATA_EVENT = 0x4002A110 +IPC_PIPELINED_MAX_BUFFER_SIZE = 0xE000 +IPC_MAX_BUFFER_SIZE = 0x10000 + +LOG = logging.getLogger(__name__) + + +def change_endianness(x: int, n=4) -> int: + return sum(((x >> 8*i) & 0xFF) << 8*(n-i-1) for i in range(n)) + +def bytes_to_word(bts): + result = 0 + for i, b in enumerate(bts): + result |= b << (8*i) + return result + +def word_to_bytes(wrd): + result = [] + for i in range(4): + result.append((wrd >> (8*i)) & 0xFF) + return bytes(result) + +def split_addr_range_into_chunks(range, chunk_size): + chunks = [] + addr = range[0] + while True: + c = (addr, min(range[1], addr + chunk_size)) + chunks.append(c) + addr = c[1] + if addr == range[1]: + break + return chunks + + +class NRF91(CoreSightTarget): + + VENDOR = "Nordic Semiconductor" + + def __init__(self, session, memory_map=None): + super(NRF91, self).__init__(session, memory_map) + self.ctrl_ap = None + + def create_init_sequence(self): + seq = super(NRF91, self).create_init_sequence() + + # Must check whether security is enabled, and potentially auto-unlock, before + # any init tasks that require system bus access. + seq.wrap_task('discovery', + lambda seq: seq.insert_before('find_components', + ('check_ctrl_ap_idr', self.check_ctrl_ap_idr), + ('check_flash_security', self.check_flash_security), + ) + ) + + seq.insert_before('post_connect_hook', + ('check_part_info', self.check_part_info)) + + return seq + + def check_ctrl_ap_idr(self): + self.ctrl_ap = self.dp.aps[CTRL_AP_NUM] + + # Check CTRL-AP ID. + if self.ctrl_ap.idr != CTRL_IDR_EXPECTED: + LOG.error("%s: bad CTRL-AP IDR (is 0x%08x)", self.part_number, self.ctrl_ap.idr) + + def check_flash_security(self): + """@brief Check security and unlock device. + + This init task determines whether the device is locked (APPROTECT enabled). If it is, + and if auto unlock is enabled, then perform a mass erase to unlock the device. + + This init task runs *before* cores are created. + """ + + if self.is_locked(): + if self.session.options.get('auto_unlock'): + LOG.warning("%s APPROTECT enabled: will try to unlock via mass erase", self.part_number) + + # Do the mass erase. + if not self.mass_erase(): + LOG.error("%s: mass erase failed", self.part_number) + raise exceptions.TargetErrors.TargetError("unable to unlock device") + # Target needs to be reset to clear protection status + self.session.probe.reset() + self.pre_connect() + self.dp.connect() + self._discoverer._create_1_ap(AHB_AP_NUM) + self._discoverer._create_1_ap(APB_AP_NUM) + else: + LOG.warning("%s APPROTECT enabled: not automatically unlocking", self.part_number) + else: + LOG.info("%s not in secure state", self.part_number) + + def is_locked(self): + status = self.ctrl_ap.read_reg(CTRL_AP_APPROTECTSTATUS) + return (status & CTRL_AP_APPROTECTSTATUS_APPROTECT_MSK == 0) \ + or (status & CTRL_AP_APPROTECTSTATUS_SECUREAPPROTECT_MSK == 0) + + def is_eraseprotected(self): + status = self.ctrl_ap.read_reg(CTRL_AP_ERASEPROTECTSTATUS) + return status & CTRL_AP_ERASEPROTECTSTATUS_MSK == 0 + + def mass_erase(self): + if self.is_eraseprotected(): + LOG.warning("ERASEPROTECT is enabled.") + if self.is_locked(): + LOG.error("If the firmware supports unlocking with a known 32-bit key,") + LOG.error("then this is the only way to recover the device.") + return False + else: + LOG.warning("Performing a chip erase instead.") + eraser = FlashEraser(self.session, FlashEraser.Mode.CHIP) + eraser._log_chip_erase = False + eraser.erase() + return True + + # See Nordic Whitepaper nWP-027 for magic numbers and order of operations from the vendor + self.ctrl_ap.write_reg(CTRL_AP_ERASEALL, CTRL_AP_ERASEALL_ERASE) + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + status = self.ctrl_ap.read_reg(CTRL_AP_ERASEALLSTATUS) + if status == CTRL_AP_ERASEALLSTATUS_READY: + break + sleep(0.1) + else: + # Timed out + LOG.error("Mass erase timeout waiting for ERASEALLSTATUS") + return False + self.ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_RESET) + self.ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_NORESET) + self.ctrl_ap.write_reg(CTRL_AP_ERASEALL, CTRL_AP_ERASEALL_NOOPERATION) + return True + + def check_part_info(self): + partno = self.read32(0x00FF0140) + hwrevision = self.read32(0x00FF0144) + variant = self.read32(0x00FF0148) + + LOG.info(f"This appears to be an nRF{partno:X} " + + f"{word_to_bytes(variant).decode('ASCII', errors='ignore')} " + + f"{word_to_bytes(hwrevision).decode('ASCII', errors='ignore')}") + + def write_uicr(self, addr: int, value: int): + current_value = self.read32(addr) + if ((current_value & value) != value) and (current_value != 0xFFFFFFFF): + raise exceptions.TargetError("cannot write UICR value, mass_erase needed") + + self.write32(0x50039504, 1) # NVMC.CONFIG = WriteEnable + self._wait_nvmc_ready() + self.write32(addr, value) + self._wait_nvmc_ready() + self.write32(0x50039504, 0) # NVMC.CONFIG = ReadOnly + self._wait_nvmc_ready() + + def _wait_nvmc_ready(self): + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + if self.read32(0x50039400) != 0x00000000: # NVMC.READY != BUSY + break + else: + raise exceptions.TargetError("wait for NVMC timed out") + +class ModemUpdater(object): + """@brief Implements the nRF91 Modem Update procedure like described in nAN-41""" + _target: "Target" + _session: "Session" + _progress: Optional[ProgressCallback] + _total_data_size: int + _progress_offset: float + _current_progress_fraction: float + _chunk_size: int + _pipelined: bool + _segments: list + _firmware_update_digest: str + + def __init__(self, + session: "Session", + progress: Optional[ProgressCallback] = None, + ): + self._session = session + self._target = session.board.target + self._total_data_size = 0 + self._pipelined = False + self._segments = [] + self._firmware_update_digest = None + + if progress is not None: + self._progress = progress + elif session.options.get('hide_programming_progress'): + self._progress = None + else: + self._progress = print_progress() + + self._reset_state() + + def program_and_verify(self, mfw_zip: str): + """@brief Program and verify modem firmware from ZIP file.""" + self._setup_device() + self._process_zip_file(mfw_zip) + + LOG.info("programming modem firmware..") + self._total_data_size = sum(r[1]-r[0] for s in self._segments for r in s.segments()) + for s in self._segments: + self._program_segment(s) + self._progress(1.0) + LOG.info("modem firmware programmed.") + + LOG.info("verifying modem firmware..") + self._verify() + LOG.info("modem firmware verified.") + + def verify(self, mfw_zip: str): + """@brief Just verify modem firmware from ZIP file.""" + self._setup_device() + self._process_zip_file(mfw_zip) + + LOG.info("verifying modem firmware..") + self._verify() + LOG.info("modem firmware verified.") + + def _setup_device(self): + """@brief initialize device to use modem DFU""" + # init UICR.HFXOSR if necessary + if self._target.read32(0x00FF801C) == 0xFFFFFFFF: + LOG.warning("UICR.HFXOSR is not set, setting it to 0x0E") + self._target.write_uicr(addr=0x00FF801C, value=0x0000000E) + + # init UICR.HFXOCNT if necessary + if self._target.read32(0x00FF8020) == 0xFFFFFFFF: + LOG.warning("UICR.HFXOCNT is not set, setting it to 0x20") + self._target.write_uicr(addr=0x00FF8020, value=0x00000020) + + self._target.reset_and_halt(reset_type=Target.ResetType.SW) + + # 1. configure IPC to be in non-secure mode + self._target.write32(addr=0x500038A8, value=0x00000002) + + # 2. configure IPC HW for DFU + self._target.write32(addr=0x4002A514, value=0x00000002) + self._target.write32(addr=0x4002A51C, value=0x00000008) + self._target.write32(addr=0x4002A610, value=0x21000000) + self._target.write32(addr=0x4002A614, value=0x00000000) + self._target.write32(addr=0x4002A590, value=0x00000001) + self._target.write32(addr=0x4002A598, value=0x00000004) + self._target.write32(addr=0x4002A5A0, value=0x00000010) + + # 3. configure RAM as non-secure + for n in range(32): + self._target.write32(addr=0x50003700+(n*4), value=0x00000007) + + # 4. allocate memory in RAM + self._target.write32(addr=0x20000000, value=0x80010000) + self._target.write32(addr=0x20000004, value=0x2100000C) + self._target.write32(addr=0x20000008, value=0x0003FC00) + + # 5. reset the modem + self._target.write32(addr=0x50005610, value=0) + self._target.write32(addr=0x50005614, value=1) + self._target.write32(addr=0x50005610, value=1) + self._target.write32(addr=0x50005614, value=0) + self._target.write32(addr=0x50005610, value=0) + + def _process_zip_file(self, mfw_zip: str): + """@brief extract the mfw ZIP file and load DFU loader""" + digest_id = self._read_key_digest() + modem_firmware_loader = None + + with TemporaryDirectory() as tmpdir: + with ZipFile(mfw_zip, 'r') as zip_ref: + zip_ref.extractall(tmpdir) + files = os.listdir(tmpdir) + + # find modem firmware loader + for f in files: + if f.startswith(f"{digest_id}.ipc_dfu.signed_") and f.endswith(".ihex"): + modem_firmware_loader = os.path.join(tmpdir, f) + m = re.match(r"\.ipc_dfu\.signed_(\d+)\.(\d+)\.(\d+)\.ihex", f[7:]) + if m: + loader_version = tuple(int(x) for x in m.groups()) + LOG.info("modem_firmware_loader version: {}.{}.{}".format( + *loader_version)) + if loader_version > (1, 1, 2): + LOG.info("using pipelined method") + self._pipelined = True + break + if not modem_firmware_loader: + raise exceptions.TargetError( + f"No compatible loader {digest_id}.ipc_dfu.signed_x.x.x.ihex found.") + + # find modem firmware segments + for f in files: + m = re.match(r"firmware\.update\.image\.segments\.(\d+).hex", f) + if m: + self._segments.append( + (m.group(1), os.path.join(tmpdir, f))) + self._segments.sort() + self._segments = [IntelHex(s[1]) for s in self._segments] + + if len(self._segments) == 0: + raise exceptions.TargetError("No modem firmware segments found") + + # parse segment digests + with open(os.path.join(tmpdir, "firmware.update.image.digest.txt"), "r") as f: + for line in f: + m = re.match(r"SHA256 of all ranges in ascending address order:\s*(\w{64})", + line) + if m: + self._firmware_update_digest = m.group(1) + if not self._firmware_update_digest: + raise exceptions.TargetError("no firmware digest found") + + LOG.info("loading modem firmware loader..") + FileProgrammer(self._session).program( + modem_firmware_loader, file_format='hex') + self._target.write32(0x4002A004, 0x00000001) # start IPC task + self._wait_and_ack_events() + LOG.info("modem_firmware_loader started.") + + def _read_key_digest(self) -> str: + """@brief read first word of modem key digest for choosing a loader""" + self._wait_and_ack_events() + digest_data = change_endianness(self._target.read32(0x20000010)) + return (f"{digest_data:08X}")[:7] + + def _program_segment(self, segment: IntelHex): + """@brief program contents of segment HEX file using DFU loader""" + if self._pipelined: + bufsz = IPC_PIPELINED_MAX_BUFFER_SIZE + else: + bufsz = IPC_MAX_BUFFER_SIZE + + chunks = [] + for s in segment.segments(): + chunks += split_addr_range_into_chunks(s, bufsz) + + if self._pipelined: + self._write_chunk(segment, chunks[0], 0) + + for i, c in enumerate(chunks): + self._commit_chunk(c, i % 2) + + # write next chunk while current one is processed + if (i + 1) < len(chunks): + self._write_chunk(segment, chunks[i + 1], (i + 1) % 2) + + self._wait_and_ack_events() + else: + for i, c in enumerate(chunks): + self._write_chunk(segment, c, 0) + self._commit_chunk(c, 0) + self._wait_and_ack_events() + + def _write_chunk(self, segment: IntelHex, chunk, bank): + """@brief write a chunk of the current segment to RAM""" + start = chunk[0] + size = chunk[1]-chunk[0] + if self._pipelined: + ram_address = 0x2000001C + IPC_PIPELINED_MAX_BUFFER_SIZE * bank + else: + ram_address = 0x20000018 + + data = list(segment.tobinarray(start=start, size=size)) + data_words = [bytes_to_word(data[i:i+4]) + for i in range(0, len(data), 4)] + self._target.write_memory_block32(ram_address, data_words) + self._current_progress_fraction = size / float(self._total_data_size) + self._progress_cb(1.0) + self._progress_offset += self._current_progress_fraction + + def _commit_chunk(self, chunk, bank): + """@brief signal DFU loader that chunk is ready to be programmed""" + buffer_offset = bank * IPC_PIPELINED_MAX_BUFFER_SIZE + self._target.write32(0x20000010, chunk[0]) + self._target.write32(0x20000014, chunk[1]-chunk[0]) + if self._pipelined: + self._target.write32(0x20000018, buffer_offset) + if self._pipelined: + # command = PIPELINE_WRITE + self._target.write32(0x2000000C, 0x9) + else: + # command = WRITE + self._target.write32(0x2000000C, 0x3) + # start IPC task + self._target.write32(0x4002A004, 1) + + def _verify(self): + """@brief verify programmed modem firmware""" + ranges_to_verify = [] + for s in self._segments: + for r in s.segments(): + if r[0] < 0x1000000: + ranges_to_verify.append(r) + + # write given start, size pairs and number of entries + self._target.write32(0x20000010, len(ranges_to_verify)) + for i, (start, end) in enumerate(ranges_to_verify): + self._target.write32(0x20000014 + (8 * i), start) + self._target.write32(0x20000018 + (8 * i), end-start) + + # command = VERIFY + self._target.write32(0x2000000C, 0x7) + # start IPC task + self._target.write32(0x4002A004, 1) + + self._wait_and_ack_events() + + response = self._target.read32(0x2000000C) + if (response & 0xFF000000) == 0x5A000000: + raise exceptions.TargetError(f"Error while verifying: {response & 0xFFFFFF:X}") + + digest_data = [self._target.read32(x) for x in range(0x20000010, 0x2000002D, 0x4)] + digest_str = "".join(f"{x:08X}" for x in digest_data) + + if digest_str != self._firmware_update_digest: + raise exceptions.TargetError( + f"checksum mismatch: {digest_str} != {self._firmware_update_digest}" + ) + + def _wait_and_ack_events(self): + """@brief wait for and acknowledge DFU events""" + fault = False + + # poll for events + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + if self._target.read32(FAULT_EVENT) != 0: + fault = True + break + if self._target.read32(COMMAND_EVENT) != 0: + break + if self._target.read32(DATA_EVENT) != 0: + break + else: + raise exceptions.TargetError("wait for events timed out") + + # reset events + for reg in [FAULT_EVENT, COMMAND_EVENT, DATA_EVENT]: + self._target.write32(reg, 0) + + response = self._target.read32(0x2000000C) + if (response & 0xFF000000) == 0xA5000000: + LOG.debug(f"ACK response, code {response:08X}") + elif (response & 0xFF000000) == 0x5A000000: + raise exceptions.TargetError(f"NACK response, code {response:08X}") + + if fault: + raise exceptions.TargetError("modem triggered FAULT_EVENT") + + def _reset_state(self): + """@brief Clear all state variables. """ + self._total_data_size = 0 + self._progress_offset = 0.0 + self._current_progress_fraction = 0.0 + + def _progress_cb(self, amount): + """@brief callback for updating the progress bar""" + if self._progress is not None: + self._progress((amount * self._current_progress_fraction) + self._progress_offset) diff --git a/pyocd/target/pack/cmsis_pack.py b/pyocd/target/pack/cmsis_pack.py index 5c4ce6704..a04d3685e 100644 --- a/pyocd/target/pack/cmsis_pack.py +++ b/pyocd/target/pack/cmsis_pack.py @@ -3,7 +3,7 @@ # Copyright (c) 2019-2020 Arm Limited # Copyright (c) 2020 Men Shiyun # Copyright (c) 2020 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,16 +18,37 @@ # See the License for the specific language governing permissions and # limitations under the License. +from dataclasses import (dataclass, field) from xml.etree.ElementTree import (ElementTree, Element) import zipfile import logging import io -from typing import (Any, Callable, Dict, List, IO, Iterator, Optional, Tuple, TypeVar, Union) +import errno +from pathlib import Path +from typing import (Any, Callable, Dict, List, IO, Optional, Tuple, TypeVar, Set, Union) from .flash_algo import PackFlashAlgo from ...core import exceptions -from ...core.target import Target -from ...core.memory_map import (MemoryMap, MemoryRegion, MemoryType, MEMORY_TYPE_CLASS_MAP, FlashRegion, RamRegion) +from ...core.memory_map import ( + FlashRegion, + MemoryMap, + MemoryRange, + MemoryRegion, + MemoryType, + MEMORY_TYPE_CLASS_MAP, +) +from ...coresight.ap import ( + APAddressBase, + APv1Address, + APv2Address, +) +from ...debug.sequences.sequences import ( + Block, + DebugSequence, + DebugSequenceNode, + IfControl, + WhileControl, +) LOG = logging.getLogger(__name__) @@ -35,14 +56,37 @@ class MalformedCmsisPackError(exceptions.TargetSupportError): """@brief Exception raised for errors parsing a CMSIS-Pack.""" pass +@dataclass class _DeviceInfo: """@brief Simple container class to hold XML elements describing a device.""" - def __init__(self, element: Element, **kwargs): - self.element: Element = element - self.families: List[str] = kwargs.get('families', []) - self.memories: List[Element] = kwargs.get('memories', []) - self.algos: List[Element] = kwargs.get('algos', []) - self.debugs: List[Element] = kwargs.get('debugs', []) + element: Element + families: List[str] = field(default_factory=list) + processors: List[Element] = field(default_factory=list) + memories: List[Element] = field(default_factory=list) + algos: List[Element] = field(default_factory=list) + debugs: List[Element] = field(default_factory=list) + sequences: List[Element] = field(default_factory=list) + debugvars: List[Element] = field(default_factory=list) + debugports: List[Element] = field(default_factory=list) + accessports: List[Element] = field(default_factory=list) + +@dataclass +class ProcessorInfo: + """@brief Descriptor for a processor defined in a DFP.""" + ## The Pname attribute, or Dcore if not Pname was provided. + name: str = "unknown" + ## PE unit number within an MPCore. For single cores this will be 0. + unit: int = -1 + ## Total number of cores in an MPCore. + total_units: int = 1 + ## Address of AP through which the PE can be accessed. + ap_address: APAddressBase = APv1Address(-1) + ## Base address of the PE's memory mapped debug registers. Not used and 0 for M-profile. + address: int = 0 + ## SVD file path relative to the pack. + svd_path: Optional[str] = None + ## Default reset sequence name. + default_reset_sequence: str = "ResetSystem" def _get_part_number_from_element(element: Element) -> str: """@brief Extract the part number from a device or variant XML element.""" @@ -72,37 +116,63 @@ class CmsisPack: defined device and passes those to CmsisPackDevice. It is then CmsisPackDevice that performs the parsing of each element type into pyOCD-compatible data. """ - def __init__(self, file_or_path: Union[str, zipfile.ZipFile, IO[bytes]]) -> None: + def __init__(self, file_or_path: Union[str, zipfile.ZipFile, IO[bytes], Path]) -> None: """@brief Constructor. Opens the CMSIS-Pack and builds instances of CmsisPackDevice for all the devices and variants defined within the pack. @param self - @param file_or_path The .pack file to open. May be a string that is the path to the pack, - or may be a ZipFile, or a file-like object that is already opened. + @param file_or_path The .pack file to open. These values are supported: + - String that is the path to a .pack file (a Zip file). + - String that is the path to the root directory of an expanded pack. + - `ZipFile` object. + - File-like object that is already opened. @exception MalformedCmsisPackError The pack is not a zip file, or the .pdsc file is missing from within the pack. """ + self._is_dir = False if isinstance(file_or_path, zipfile.ZipFile): self._pack_file = file_or_path else: - try: - self._pack_file = zipfile.ZipFile(file_or_path, 'r') - except zipfile.BadZipFile as err: - raise MalformedCmsisPackError(f"Failed to open CMSIS-Pack '{file_or_path}': {err}") from err + # Check for an expanded pack as a directory. + if isinstance(file_or_path, (str, Path)): + path = Path(file_or_path).expanduser() + file_or_path = str(path) # Update with expanded path. + + self._is_dir = path.is_dir() + if self._is_dir: + self._dir_path = path + + if not self._is_dir: + try: + self._pack_file = zipfile.ZipFile(file_or_path, 'r') + except zipfile.BadZipFile as err: + raise MalformedCmsisPackError(f"Failed to open CMSIS-Pack '{file_or_path}': {err}") from err # Find the .pdsc file. - for name in self._pack_file.namelist(): - if name.endswith('.pdsc'): - self._pdscName = name - break + if self._is_dir: + for child_path in self._dir_path.iterdir(): + if child_path.suffix == '.pdsc': + self._pdsc_name = child_path.name + break + else: + raise MalformedCmsisPackError(f"CMSIS-Pack '{file_or_path}' is missing a .pdsc file") else: - raise MalformedCmsisPackError(f"CMSIS-Pack '{file_or_path}' is missing a .pdsc file") + for name in self._pack_file.namelist(): + if name.endswith('.pdsc'): + self._pdsc_name = name + break + else: + raise MalformedCmsisPackError(f"CMSIS-Pack '{file_or_path}' is missing a .pdsc file") - with self._pack_file.open(self._pdscName) as pdscFile: - self._pdsc = CmsisPackDescription(self, pdscFile) + if self._is_dir: + with (self._dir_path / self._pdsc_name).open('rb') as pdsc_file: + self._pdsc = CmsisPackDescription(self, pdsc_file) + else: + with self._pack_file.open(self._pdsc_name) as pdsc_file: + self._pdsc = CmsisPackDescription(self, pdsc_file) @property def filename(self) -> Optional[str]: @@ -119,7 +189,7 @@ def devices(self) -> List["CmsisPackDevice"]: """@brief A list of CmsisPackDevice objects for every part number defined in the pack.""" return self._pdsc.devices - def get_file(self, filename) -> IO[bytes]: + def get_file(self, filename: str) -> IO[bytes]: """@brief Return file-like object for a file within the pack. @param self @@ -132,17 +202,21 @@ def get_file(self, filename) -> IO[bytes]: # Some vendors place their pdsc in some subdirectories of the pack archive, # use relative directory to the pdsc file while reading other files. - pdsc_base = self._pdscName.rsplit('/', 1) + pdsc_base = self._pdsc_name.rsplit('/', 1) if len(pdsc_base) == 2: filename = f'{pdsc_base[0]}/{filename}' - return io.BytesIO(self._pack_file.read(filename)) + if self._is_dir: + path = self._dir_path / filename + return io.BytesIO(path.read_bytes()) + else: + return io.BytesIO(self._pack_file.read(filename)) class CmsisPackDescription: """@brief Parser for the PDSC XML file describing a CMSIS-Pack. """ - def __init__(self, pack: CmsisPack, pdsc_file: IO) -> None: + def __init__(self, pack: CmsisPack, pdsc_file: IO[bytes]) -> None: """@brief Constructor. @param self This object. @@ -165,6 +239,13 @@ def __init__(self, pack: CmsisPack, pdsc_file: IO) -> None: for family in self._pdsc.iter('family'): self._parse_devices(family) + @property + def pack_name(self) -> Optional[str]: + """@brief Name of the CMSIS-Pack. + @return Contents of the required element, or None if missing. + """ + return self._pdsc.findtext('name') + @property def pack(self) -> CmsisPack: """@brief Reference to the containing CmsisPack object.""" @@ -182,10 +263,20 @@ def _parse_devices(self, parent: Element) -> None: for elem in parent: if elem.tag == 'memory': newState.memories.append(elem) + elif elem.tag == 'processor': + newState.processors.append(elem) elif elem.tag == 'algorithm': newState.algos.append(elem) elif elem.tag == 'debug': newState.debugs.append(elem) + elif elem.tag == 'sequences': + newState.sequences += elem.findall('sequence') + elif elem.tag == 'debugvars': + newState.debugvars.append(elem) + elif elem.tag == 'debugport': + newState.debugports.append(elem) + elif elem.tag in ('accessportV1', 'accessportV2'): + newState.accessports.append(elem) # Save any elements that we will recurse into. elif elem.tag in ('subFamily', 'device', 'variant'): children.append(elem) @@ -198,12 +289,18 @@ def _parse_devices(self, parent: Element) -> None: # Build device info from elements applying to this device. deviceInfo = _DeviceInfo(element=parent, families=self._extract_families(), + processors=self._extract_processors(), memories=self._extract_memories(), algos=self._extract_algos(), - debugs=self._extract_debugs() + debugs=self._extract_debugs(), + sequences=self._extract_sequences(), + debugvars=self._extract_debugvars(), + debugports=self._extract_debugports(), + accessports=self._extract_accessports(), ) - dev = CmsisPackDevice(self.pack, deviceInfo) + # Support ._pack being None for testing. + dev = CmsisPackDevice(self, deviceInfo, self._pack.get_file if self._pack else None) self._devices.append(dev) # Recursively process subelements. @@ -224,9 +321,13 @@ def _extract_families(self) -> List[str]: return families ## Typevar used for _extract_items(). - V = TypeVar('V') + _V = TypeVar('_V') - def _extract_items(self, state_info_name: str, filter: Callable[[Dict[Any, V], Element], None]) -> List[V]: + def _extract_items( + self, + state_info_name: str, + filter: Callable[[Dict[Any, _V], Element], None] + ) -> List[_V]: """@brief Generic extractor utility. Iterates over saved elements for the specified device state info for each level of the @@ -247,9 +348,46 @@ def _extract_items(self, state_info_name: str, filter: Callable[[Dict[Any, V], E try: filter(map, elem) except (KeyError, ValueError) as err: - LOG.debug("error parsing CMSIS-Pack: " + str(err)) + LOG.debug("error parsing CMSIS-Pack %s: %s", self.pack_name, err) return list(map.values()) + def _inherit_attributes(self, to_elem: Element, from_elem: Optional[Element]) -> Element: + """@brief Add attributes missing from an elemnt but present in another. + + Copy to `to_elem` any attributes defined in `from_elem` but not defined, and therefore overridden, + in `to_elem`. + + @param self + @param to_elem The Element to which inherited attributes will be added. + @param from_elem The Element from which attributes should be inherited. May be None, in which case + `to_elem` is returned unmodified. + @return The `to_elem` parameter is returned. + """ + if from_elem is not None: + inherited = { + k: v + for k, v in from_elem.attrib.items() + if k not in to_elem.attrib + } + to_elem.attrib.update(inherited) + return to_elem + + def _extract_processors(self) -> List[Element]: + """@brief Extract processor elements. + + Attributes: + - `Pname`: optional str for single-core devices + - `Punits`: optional int, number of cores for MPCore cluster + - `Dcore`: str, CPU type + - plus a handful of others that specify processor options such as FPU or MVE + """ + def filter(map: Dict, elem: Element) -> None: + # Pname attribute is optional if there is only one CPU. + pname = elem.attrib.get('Pname') + map[pname] = self._inherit_attributes(elem, map.get(pname)) + + return self._extract_items('processors', filter) + def _extract_memories(self) -> List[Element]: """@brief Extract memory elements. @@ -258,6 +396,20 @@ def _extract_memories(self) -> List[Element]: a string. In addition to the name based filtering, memory regions are checked to prevent overlaps. + + Attributes: + - `Pname`: optional str + - `id`: optional str, deprecated in favour of `name` + - `name`: optional str, overrides `id` if both are present + - `access`: optional str + - `start`: int + - `size`: int + - `default`: optional, if true indicates the region needs no special provisions for accessing, + default false + - `startup`: optional, if true use the region for boot code, default false + - `init`: optional, deprecated, if true don't zeroise the memory, default false + - `uninit`, optional, if true the memory should not be initialised, default false + - `alias`: optional, another region's name """ def get_start_and_size(elem: Element) -> Tuple[int, int]: try: @@ -269,8 +421,8 @@ def get_start_and_size(elem: Element) -> Tuple[int, int]: return (start, size) def filter(map: Dict, elem: Element) -> None: - # Inner memory regions are allowed to override outer memory - # regions. If this is not done properly via name/id, we must make + # Inner memory regions are allowed to override outer memory regions. + # If this is not done properly via name/id, we must make # sure not to report overlapping memory regions to gdb since it # will ignore those completely, see: # https://github.com/pyocd/pyOCD/issues/980 @@ -300,8 +452,9 @@ def filter(map: Dict, elem: Element) -> None: end = start + size - 1 prev_end = prev_start + prev_size - 1 if (prev_start <= start < prev_end) or (prev_start <= end < prev_end): - # Only report warnings for overlapping regions from the same processor. Allow regions for different - # processors to override each other, since we don't yet support maps for each processor. + # Only report warnings for overlapping regions from the same processor. Allow regions for + # different processors to override each other, since we don't yet support maps for each + # processor. if (pname == prev_pname) and not self._warned_overlapping_memory_regions: filename = self.pack.filename if self.pack else "unknown" LOG.warning("Overlapping memory regions in file %s (%s); deleting outer region. " @@ -321,11 +474,21 @@ def _extract_algos(self) -> List[Element]: Any algorithm elements with a 'style' attribuet not set to 'Keil' (case-insensitive) are skipped. + + Attributes: + - `Pname`: optional str + - `name`: str + - `start`: int + - `size`: int + - `RAMstart`: optional int + - `RAMsize`: optional int + - `default`: optional bool + - `style`: optional str """ def filter(map: Dict, elem: Element) -> None: # We only support Keil FLM style flash algorithms (for now). if ('style' in elem.attrib) and (elem.attrib['style'].lower() != 'keil'): - LOG.debug("skipping non-Keil flash algorithm") + LOG.debug("%s DFP: skipping non-Keil flash algorithm", self.pack_name) return # Both start and size are required. @@ -347,6 +510,18 @@ def _extract_debugs(self) -> List[Element]: Otherwise, the identifier is the element's 'Pname' attribute combined with 'Punit' if present. When 'Pname' is detected and a "*" key is in the map, the map is cleared before adding the current element. + + Attributes: + - `__dp`: optional int + - `__ap`: optional int + - `__apid`: optional int + - `address`: optional int + - `svd`: optional str + - `Pname`: optional str + - `Punit`: optional int + - `defaultResetSequence`: optional str + + Can have `` elements as children. """ def filter(map: Dict, elem: Element) -> None: if 'Pname' in elem.attrib: @@ -356,14 +531,104 @@ def filter(map: Dict, elem: Element) -> None: if '*' in map: map.clear() - map[name] = elem + + map[name] = self._inherit_attributes(elem, map.get(name)) else: # No processor name was provided, so this debug element applies to + # all processors (well, there should only be one in this case). + new_elem = self._inherit_attributes(elem, map.get('*')) + map.clear() + map['*'] = new_elem + + return self._extract_items('debugs', filter) + + def _extract_sequences(self) -> List[Element]: + """@brief Extract debug sequence elements. + + The unique identifier is the sequence's 'name' attribute, combined with 'Pname' if present. + + Attributes: + - `name`: str + - `Pname`: optional str + - `disable`: optional bool + - `info`: optional str + """ + def filter(map: Dict, elem: Element) -> None: + if 'name' not in elem.attrib: + LOG.debug("skipping unnamed debug sequence") + return + + # Combine name and Pname. + name = elem.attrib['name'] + pname = elem.attrib.get('Pname', None) + + map[(name, pname)] = elem + + return self._extract_items('sequences', filter) + + def _extract_debugvars(self) -> List[Element]: + """@brief Extract debugvar elements. + + Works similar to _extract_debugs(), where only a single debugvar element is allowed unless + the 'Pname' attribute appears in one of the elements. + + Attributes: + - `configfile`: optional str + - `version`: optional str + - `Pname`: optional str + """ + def filter(map: Dict, elem: Element) -> None: + # No point in tracking an empty debugvars. + if elem.text is None: + return + if 'Pname' in elem.attrib: + name = elem.attrib['Pname'] + + if '*' in map: + map.clear() + map[name] = elem + else: + # No processor name was provided, so this debugvar element applies to # all processors. map.clear() map['*'] = elem - return self._extract_items('debugs', filter) + return self._extract_items('debugvars', filter) + + def _extract_debugports(self) -> List[Element]: + """@brief Extract debugport elements. + + Attributes: + - `__dp`: int + + Children: + - `` + - `` + - `` + """ + def filter(map: Dict, elem: Element) -> None: + map[elem.attrib['__dp']] = elem + + return self._extract_items('debugports', filter) + + def _extract_accessports(self) -> List[Element]: + """@brief Extract accessportV1 and accessportV2 elements. + + Attributes for ``: + - `__apid`: int + - `__dp`: optional int + - `index`: int + + Attributes for ``: + - `__apid`: int + - `__dp`: optional int + - `address`: int + - `parent`: optional int + """ + def filter(map: Dict, elem: Element) -> None: + map[elem.attrib['__apid']] = elem + + return self._extract_items('accessports', filter) def _get_bool_attribute(elem: Element, name: str, default: bool = False) -> bool: """@brief Extract an XML attribute with a boolean value. @@ -391,25 +656,40 @@ class CmsisPackDevice: """@brief Wraps a device defined in a CMSIS Device Family Pack. Responsible for converting the XML elements that describe the device into objects - usable by pyOCD. This includes the memory map and flash algorithms. + usable by pyOCD. This includes the memory map and flash algorithms. All extraction of data + into usuable data structures is done lazily, since a CmsisPackDevice instance will be + created for every device in installed DFPs but only one will actually be used per session. An instance of this class can represent either a `` or `` XML element from the PDSC. """ - def __init__(self, pack: CmsisPack, device_info: _DeviceInfo): + def __init__(self, pdsc: CmsisPackDescription, device_info: _DeviceInfo, + get_pack_file_cb: Optional[Callable[[str], IO[bytes]]]) -> None: """@brief Constructor. @param self - @param pack The CmsisPack object that contains this device. + @param pdsc The CmsisPackDescription object that contains this device. @param device_info A _DeviceInfo object with the XML elements that describe this device. + @param get_pack_file_cb Callable taking a relative filename and returning an open bytes file. May + raise IOError exceptions. If not supplied, then no flash algorithms or other files used by + the device description are accessible (primarily for testing). """ - self._pack: CmsisPack = pack + self._pdsc = pdsc self._info: _DeviceInfo = device_info + self._get_pack_file_cb = get_pack_file_cb self._part: str = _get_part_number_from_element(device_info.element) self._regions: List[MemoryRegion] = [] self._saw_startup: bool = False self._default_ram: Optional[MemoryRegion] = None self._memory_map: Optional[MemoryMap] = None + self._processed_algos: Set[Element] = set() # Algo elements we've converted to regions. + self._sequences: Set[DebugSequence] = set() + self._debugvars: Optional[Block] = None + self._valid_dps: List[int] = [] + self._apids: Dict[int, APAddressBase] = {} + self._processors_map: Dict[str, ProcessorInfo] = {} + self._processors_ap_map: Dict[APAddressBase, ProcessorInfo] = {} + self._built_apid_map: bool = False def _build_memory_regions(self) -> None: """@brief Creates memory region instances for the device. @@ -447,9 +727,9 @@ def _build_memory_regions(self) -> None: start = int(elem.attrib['start'], base=0) size = int(elem.attrib['size'], base=0) - isDefault = _get_bool_attribute(elem, 'default') - isStartup = _get_bool_attribute(elem, 'startup') - if isStartup: + is_default = _get_bool_attribute(elem, 'default') + is_startup = _get_bool_attribute(elem, 'startup') + if is_startup: self._saw_startup = True attrs = { @@ -457,209 +737,251 @@ def _build_memory_regions(self) -> None: 'start': start, 'length': size, 'access': access, - 'is_default': isDefault, - 'is_boot_memory': isStartup, - 'is_testable': isDefault, + 'is_default': is_default, + 'is_boot_memory': is_startup, + 'is_testable': is_default, 'alias': elem.attrib.get('alias', None), } + # Look for matching flash algo. + try: + # TODO multiple matching algos per region + algo_element = self._find_matching_algo(MemoryRange(attrs['start'], + length=attrs['length'])) + except KeyError: + # Must be a mask ROM or non-programmable flash. + algo_element = None + + # Convert the region to flash if we found a matching algorithm element. + if (algo_element is not None) and self._set_flash_attributes(algo_element, attrs): + # Mark this algo as processed. + self._processed_algos.add(algo_element) + + # Since this region has an algo, it's now flash. + type = MemoryType.FLASH + + # If we don't have a boot memory yet, pick the first flash. + if not self._saw_startup: + attrs['is_boot_memory'] = True + self._saw_startup = True + # Create the memory region and add to map. region = MEMORY_TYPE_CLASS_MAP[type](**attrs) self._regions.append(region) # Record the first default ram for use in flash algos. - if self._default_ram is None and type == MemoryType.RAM and isDefault: + if (self._default_ram is None) and (type is MemoryType.RAM) and is_default: self._default_ram = region except (KeyError, ValueError) as err: # Ignore errors. LOG.debug("ignoring error parsing memories for CMSIS-Pack devices %s: %s", self.part_number, str(err)) - def _get_containing_region(self, addr: int) -> Optional[MemoryRegion]: - """@brief Return the memory region containing the given address.""" - for region in self._regions: - if region.contains_address(addr): - return region - return None + # Now create flash regions for any algos we didn't process. + for algo in [a for a in self._info.algos if a not in self._processed_algos]: + # Should this algo be loaded by default? + is_default = _get_bool_attribute(algo, 'default') + if not is_default: + LOG.debug("%s DFP (%s): not loading non-default flash algorithm '%s'", + self.pack_description.pack_name, self.part_number, algo.attrib['name']) + continue - def _build_flash_regions(self) -> None: - """@brief Converts ROM memory regions to flash regions. + # Load flash algo from .FLM file so we can get its address range, etc. + pack_algo = self._load_flash_algo(algo.attrib['name']) + if pack_algo is None: + LOG.warning(f"{self.pack_description.pack_name} DFP ({self.part_number}): " + f"failed to find or load flash algorithm '{algo.attrib['name']}'") + continue - Each ROM region in the `_regions` attribute is converted to a flash region if a matching - flash algo can be found. If the flash has multiple sector sizes, then separate flash - regions will be created for each sector size range. The flash algo is converted to a - pyOCD-compatible flash algo dict by calling _get_pyocd_flash_algo(). - """ - # Must have a default ram. - if self._default_ram is None: - LOG.warning("CMSIS-Pack device %s has no default RAM defined, cannot program flash" % self.part_number) - return + ram_attrs = self._get_flash_ram_attributes(algo) - # Can't import at top level due to import loops. - from ...core.session import Session + # If we don't have a boot memory yet, pick the first flash. + # TODO this should be refactored to use the flash region with lowest address. + rgn_attrs: Dict[str, Any] = {} + if not self._saw_startup: + rgn_attrs['is_boot_memory'] = True + self._saw_startup = True - regions_to_delete = [] # List of regions to delete. - regions_to_add = [] # List of FlashRegion objects to add. + # Create the memory region. + region = FlashRegion( + name=pack_algo.flash_info.name.decode(encoding='ascii'), + start=pack_algo.flash_start, + length=pack_algo.flash_size, + access='rx', + flm=pack_algo, + sector_size=0, + # Mark the flash memory as inaccessible at boot, just to be safe. There's + # no real way to be sure about this. The vendor should have create a + # element! + is_default=False, + # Similarly, disallow testing of this region since we're not sure. This will + # make it impossible to run functional tests on some devices without a user + # script to help out. + is_testable=False, + **rgn_attrs, + **ram_attrs, + ) + self._regions.append(region) - # Create flash algo dicts once we have the full memory map. - for i, region in enumerate(self._regions): - # We're only interested in ROM regions here. - if region.type != MemoryType.ROM: - continue + def _get_flash_ram_attributes(self, algo_element: Element) -> Dict[str, int]: + attrs: Dict[str, int] = {} + if 'RAMstart' in algo_element.attrib: + attrs['_RAMstart'] = int(algo_element.attrib['RAMstart'], base=0) + if 'RAMsize' in algo_element.attrib: + attrs['_RAMsize'] = int(algo_element.attrib['RAMsize'], base=0) + else: + LOG.warning( + f"{self.pack_description.pack_name} DFP ({self.part_number}): " + f"flash algorithm '{algo_element.attrib['name']}' has RAMstart but is " + "missing RAMsize") + + return attrs + + def _set_flash_attributes(self, algo_element: Element, attrs: dict) -> bool: + # Load flash algo from .FLM file. + pack_algo = self._load_flash_algo(algo_element.attrib['name']) + if pack_algo is None: + LOG.warning(f"{self.pack_description.pack_name} DFP ({self.part_number}): " + f"failed to find or load flash algorithm '{algo_element.attrib['name']}'") + return False - # Look for matching flash algo. - try: - algo_element = self._find_matching_algo(region) - except KeyError: - # Must be a mask ROM or non-programmable flash. - continue + attrs['flm'] = pack_algo - # Load flash algo from .FLM file. - packAlgo = self._load_flash_algo(algo_element.attrib['name']) - if packAlgo is None: - LOG.warning("Failed to convert ROM region to flash region because flash algorithm '%s' could not be " - " found (%s)", algo_element.attrib['name'], self.part_number) - continue + # Save the algo element's RAM attributes in the region for later use in + # CoreSightTarget.create_flash(). + ram_attrs = self._get_flash_ram_attributes(algo_element) + attrs.update(ram_attrs) - # The ROM region will be replaced with one or more flash regions. - regions_to_delete.append(region) + # Set sector size to a fixed value to prevent any possibility of infinite recursion due to + # the default lambdas for sector_size and blocksize returning each other's value. + attrs['sector_size'] = 0 - # Log details of this flash algo if the debug option is enabled. - current_session = Session.get_current() - if current_session and current_session.options.get("debug.log_flm_info"): - LOG.debug("Flash algo info: %s", packAlgo.flash_info) + # We have at least a partially matching algo. Change type to flash. + return True - # Choose the page size. The check for <=32 is to handle some flash algos with incorrect - # page sizes that are too small and probably represent the phrase size. - page_size = packAlgo.page_size - if page_size <= 32: - page_size = min(s[1] for s in packAlgo.sector_sizes) + def _find_matching_algo(self, range: MemoryRange) -> Element: + """@brief Searches for a flash algo overlapping the regions's address range. - # Select the RAM to use for the algo. + The algo and region's ranges just have to overlap. There are some DFPs that specify algos that + don't fully cover the region range, and potentially vice versa. It is possible that one algo + covers more than one region, but that is handled by the method calling this one (per region). + """ + for algo in self._info.algos: try: - # See if an explicit RAM range was specified for the algo. - ram_start = int(algo_element.attrib['RAMstart'], base=0) + # Both start and size are required attributes. + algo_range = MemoryRange(start=self._get_int_attribute(algo, 'start'), + length=self._get_int_attribute(algo, 'size')) + except MalformedCmsisPackError: + # Ignore this algorithm. A warning has already been logged. + continue - # The region size comes either from the RAMsize attribute, the containing region's bounds, or - # a large, arbitrary value. - if 'RAMsize' in algo_element.attrib: - ram_size = int(algo_element.attrib['RAMsize'], base=0) + # Check if the region and the algo overlap. + if range.intersects_range(range=algo_range): + # Verify this is a valid algorithm specification. + if 'name' not in algo.attrib: + LOG.debug( + f"{self.pack_description.pack_name} DFP ({self.part_number}): flash algorithm " + f"covering {algo_range.start:x}-{algo_range.end:x} missing required 'name' element") else: - containing_region = self._get_containing_region(ram_start) - if containing_region is not None: - ram_size = containing_region.length - (ram_start - containing_region.start) - else: - # No size specified, and the RAMstart attribute is outside of a known region, - # so just use a relatively large arbitrary size. Because the algo is packed at the - # start of the provided region, this won't be a problem unless the DFP is - # actually erroneous. - ram_size = 128 * 1024 - - ram_for_algo = RamRegion(start=ram_start, length=ram_size) - except KeyError: - # No RAM addresses were given, so go with the RAM marked default. - ram_for_algo = self._default_ram + return algo + raise KeyError("no matching flash algorithm") - # Construct the pyOCD algo using the largest sector size. We can share the same - # algo for all sector sizes. - algo = packAlgo.get_pyocd_flash_algo(page_size, ram_for_algo) + def _load_flash_algo(self, filename: str) -> Optional[PackFlashAlgo]: + """@brief Return the PackFlashAlgo instance for the given flash algo filename.""" + try: + algo_data = self.get_file(filename) + return PackFlashAlgo(algo_data) + except FileNotFoundError: + # Return default value. + return None - # Create a separate flash region for each sector size range. - regions_to_add += list(self._split_flash_region_by_sector_size( - region, page_size, algo, packAlgo)) # type: ignore + def get_file(self, filename: str) -> IO[bytes]: + """@brief Return file-like object for a file within the containing pack. - # Now update the regions list. - for region in regions_to_delete: - self._regions.remove(region) - for region in regions_to_add: - self._regions.append(region) + @param self + @param filename Relative path within the pack. May use forward or back slashes. + @return A BytesIO object is returned that contains all of the data from the file + in the pack. This is done to isolate the returned file from how the pack was + opened (due to particularities of the ZipFile implementation). - def _split_flash_region_by_sector_size(self, - region: MemoryRegion, - page_size: int, - algo: Dict[str, Any], - pack_algo: PackFlashAlgo) -> Iterator[FlashRegion]: - """@brief Yield separate flash regions for each sector size range.""" - # The sector_sizes attribute is a list of bi-tuples of (start-address, sector-size), sorted by start address. - for j, (offset, sector_size) in enumerate(pack_algo.sector_sizes): - start = region.start + offset - - # Determine the end address of the this sector range. For the last range, the end - # is just the end of the entire region. Otherwise it's the start of the next - # range - 1. - if j + 1 >= len(pack_algo.sector_sizes): - end = region.end - else: - end = region.start + pack_algo.sector_sizes[j + 1][0] - 1 + @exception OSError A problem occurred opening the file. + @exception FileNotFoundError In addition to the usual case of the file actually not being found, + this exception is raised if no `get_pack_file_cb` was passed to the constructor. + """ + if self._get_pack_file_cb: + return self._get_pack_file_cb(filename) + else: + raise FileNotFoundError(errno.ENOENT, "No such file or directory", filename) - # Skip wrong start and end addresses - if end < start: + def _build_sequences(self): + """@brief Convert 'sequence' elements into DebugSequenceNode objects.""" + assert not len(self._sequences) + for elem in self._info.sequences: + # Extract sequence name. + try: + name = elem.attrib['name'] + except KeyError: + LOG.warning("invalid debug sequence; missing name") continue - # Limit page size. - if page_size > sector_size: - region_page_size = sector_size - LOG.warning("Page size (%d) is larger than sector size (%d) for flash region %s; " - "reducing page size to %d", page_size, sector_size, region.name, - region_page_size) - else: - region_page_size = page_size + try: + # Extract optional sequence attributes. + is_enabled = not _get_bool_attribute(elem, 'disable', False) + pname = elem.attrib.get('Pname', None) + info = elem.attrib.get('info', "") - # If we don't have a boot memory yet, pick the first flash. - if not self._saw_startup: - is_boot = True - self._saw_startup = True + # Create the top level sequence node. + sequence = DebugSequence(name, is_enabled, pname, info) + + # Start processing subelements in the sequence. + for child in elem: + self._build_one_sequence_node(sequence, child) + + # Save the complete sequence object. + self._sequences.add(sequence) + except KeyError: + LOG.debug("invalid debug sequence") + + def _build_one_sequence_node(self, parent: DebugSequenceNode, elem: Element) -> None: + """@brief Convert one 'sequence' element into a DebugSequenceNode object.""" + # Grab optional info text. + info = elem.attrib.get('info', "") + + # Generate a sequence node based on the element type. + if elem.tag == 'block': + # No reason to create a Block if there is no code within it. + if elem.text is not None: + # Create and attach a block node. No subelements are allowed. + is_atomic = _get_bool_attribute(elem, 'atomic', False) + node = Block(elem.text, is_atomic, info) + parent.add_child(node) + elif elem.tag == 'control': + # The attribute name determines the control node's function. + if 'if' in elem.attrib: + node = IfControl(elem.attrib['if'], info) + elif 'while' in elem.attrib: + node = WhileControl(elem.attrib['while'], info, int(elem.attrib.get('timeout', "0"))) else: - is_boot = region.is_boot_memory - - # Construct region name. If there is more than one sector size, we need to make the region's name unique. - region_name = region.name - if len(pack_algo.sector_sizes) > 1: - region_name += f"_{sector_size:#x}" - - # Construct the flash region. - yield FlashRegion(name=region_name, - access=region.access, - start=start, - end=end, - sector_size=sector_size, - page_size=region_page_size, - flm=pack_algo, - algo=algo, - erased_byte_value=pack_algo.flash_info.value_empty, - is_default=region.is_default, - is_boot_memory=is_boot, - is_testable=region.is_testable, - alias=region.alias) - - def _find_matching_algo(self, region: MemoryRegion) -> Element: - """@brief Searches for a flash algo covering the regions's address range.'""" - for algo in self._info.algos: - # Both start and size are required attributes. - algoStart = int(algo.attrib['start'], base=0) - algoSize = int(algo.attrib['size'], base=0) - algoEnd = algoStart + algoSize - 1 - - # Check if the region indicated by start..size fits within the algo. - if (algoStart <= region.start <= algoEnd) and (algoStart <= region.end <= algoEnd): - return algo - raise KeyError("no matching flash algorithm") + root_node = parent.find_root() + assert isinstance(root_node, DebugSequence) + LOG.warning("invalid 'control' node in debug sequence '%s'", root_node.name) + return - def _load_flash_algo(self, filename: str) -> Optional[PackFlashAlgo]: - """@brief Return the PackFlashAlgo instance for the given flash algo filename.""" - if self.pack is not None: - try: - algo_data = self.pack.get_file(filename) - return PackFlashAlgo(algo_data) - except FileNotFoundError: - pass - # Return default value. - return None + # Attach the new node. + parent.add_child(node) + + # Process control node subelements recursively. + for child in elem: + self._build_one_sequence_node(node, child) + else: + root_node = parent.find_root() + assert isinstance(root_node, DebugSequence) + LOG.warning("unexpected XML element '%s' in debug sequence '%s'", elem.tag, root_node.name) @property - def pack(self) -> CmsisPack: - """@brief The CmsisPack object that defines this device.""" - return self._pack + def pack_description(self) -> CmsisPackDescription: + """@brief The CmsisPackDescription object that defines this device.""" + return self._pdsc @property def part_number(self) -> str: @@ -686,7 +1008,6 @@ def memory_map(self) -> MemoryMap: # Lazily construct the memory map. if self._memory_map is None: self._build_memory_regions() - self._build_flash_regions() # Warn if there was no boot memory. if not self._saw_startup: @@ -703,31 +1024,265 @@ def svd(self) -> Optional[IO[bytes]]: """ try: svdPath = self._info.debugs[0].attrib['svd'] - return self._pack.get_file(svdPath) + return self.get_file(svdPath) except (KeyError, IndexError): return None @property - def default_reset_type(self) -> Target.ResetType: - """@brief One of the Target.ResetType enums. - @todo Support multiple cores. + def sequences(self) -> Set[DebugSequence]: + """@brief Dictionary of defined sequence elements. + + The dictionary key is the sequence name, value is a DebugSequence instance. """ - try: - resetSequence = self._info.debugs[0].attrib['defaultResetSequence'] - if resetSequence == 'ResetHardware': - return Target.ResetType.HW - elif resetSequence == 'ResetSystem': - return Target.ResetType.SW_SYSRESETREQ - elif resetSequence == 'ResetProcessor': - return Target.ResetType.SW_VECTRESET + # Lazily construct. + if (not len(self._sequences)) and len(self._info.sequences): + self._build_sequences() + return self._sequences + + @property + def debug_vars_sequence(self) -> Optional[Block]: + """@brief A debug sequence Block for the 'debugvars' element.""" + # Lazily construct. + if (self._debugvars is None) and len(self._info.debugvars): + elem = self._info.debugvars[0] + assert elem.text is not None # Ensured by CmsisPackDescription._extract_debugvars. + self._debugvars = Block(elem.text, info="debugvars") + return self._debugvars + + @property + def valid_dps(self) -> List[int]: + """@brief List of valid DP indices. + + If the device has only one DP, its number will be 0. + """ + if not self._valid_dps: + self._build_valid_dps() + return self._valid_dps + + @property + def uses_apid(self) -> bool: + """@brief Whether use of __apid values is required. + + This is based on whether the DFP defined accessportV1/2 elements. + """ + return len(self.apid_map) > 0 + + @property + def apid_map(self) -> Dict[int, APAddressBase]: + """@brief Map of AP unique IDs to AP address objects. + + These AP unique IDs (__apid) are defined by the DFP author and are valid only within the scope + of the DFP. They are referenced by the __apid special variable used in debug sequences. + """ + # A bool attr is used here instead of the usual empty test for the other lazy properties + # because the apid map can be empty, in which case apids are not used by this device. + if not self._built_apid_map: + self._build_aps_map() + return self._apids + + @property + def processors_map(self) -> Dict[str, ProcessorInfo]: + """@brief Map of processor names to processor info objects. + + If the device has only one PE, it may not have a defined Pname. In that case, the Dcore + attribute will be used in place of the Pname. + """ + if not self._processors_map: + self._build_aps_map() + return self._processors_map + + @property + def processors_ap_map(self) -> Dict[APAddressBase, ProcessorInfo]: + """@brief Map from AP address to processor info objects""" + if not self._processors_ap_map: + self._processors_ap_map = { + proc.ap_address: proc + for proc in self.processors_map.values() + } + return self._processors_ap_map + + def _get_int_attribute( + self, + elem: Element, + name: str, + default: Optional[int] = None + ) -> int: + """@brief Retrieve a DFP XML element's attribute value as an integer. + @exception MalformedCmsisPackError Raised if the attribute is missing but is required (no default + was provided), or cannot be converted to an integer. + """ + if name not in elem.attrib: + if default is None: + raise MalformedCmsisPackError( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{elem.tag}> missing " + f"required '{name}' attribute") else: - return Target.ResetType.SW - except (KeyError, IndexError): - return Target.ResetType.SW + return default - def __repr__(self): - return "<%s@%x %s>" % (self.__class__.__name__, id(self), self.part_number) + try: + value = int(elem.attrib[name], base=0) + return value + except ValueError: + raise MalformedCmsisPackError( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{elem.tag}> '{name}' " + f"attribute is invalid ('{elem.attrib[name]}')") + + def _build_valid_dps(self) -> None: + """@brief Extract list of DP indices defined for the device.""" + # Build list of defined DPs. + for debugport in self._info.debugports: + try: + self._valid_dps.append(self._get_int_attribute(debugport, '__dp')) + except MalformedCmsisPackError as err: + LOG.warning("%s", err) + # If no (valid) elements are defined, just use a default of 0. + if len(self._valid_dps) == 0: + self._valid_dps.append(0) + def _handle_accessports(self) -> None: + """@brief Process accessportV1 and accessportV2 elements. + The ._apids attribute is filled in with information from accessportVx elements. + """ + # Process accessportV1 and accessportV2 elements. + for accessport in self._info.accessports: + try: + # Get the __dp attribute, with a default of 0. + ap_dp = self._get_int_attribute(accessport, '__dp', 0) + + # Validate __dp, but be forgiving and only log a warning. + if ap_dp not in self.valid_dps: + LOG.warning( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{accessport.tag}> " + f"'__dp' attribute is invalid ({ap_dp})") + + # APv1 + if accessport.tag == 'accessportV1': + index = self._get_int_attribute(accessport, 'index') + ap_address = APv1Address(index, ap_dp) + # APv2 + elif accessport.tag == 'accessportV2': + address = self._get_int_attribute(accessport, 'address') + ap_address = APv2Address(address, ap_dp) + else: + raise exceptions.InternalError( + f"unexpected element <{accessport.tag}> in access ports list") + + # Save this AP address and the specified __apid. + apid = self._get_int_attribute(accessport, '__apid') + self._apids[apid] = ap_address + except MalformedCmsisPackError as err: + LOG.warning("%s", err) + + def _handle_processors(self) -> None: + """@brief Extract processor definitions.""" + for proc in self._info.processors: + try: + # Get the processor name. + if 'Pname' in proc.attrib: + pname = proc.attrib['Pname'] + elif 'Dcore' in proc.attrib: + pname = proc.attrib['Dcore'] + else: + raise MalformedCmsisPackError( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{proc.tag}> is " + "missing 'Dcore' attribute") + + # Get optional number of processor units. + punits = self._get_int_attribute(proc, 'Punits', 1) + + # Check for an existing processor with the same name. + if pname in self._processors_map: + LOG.warning( + f"{self.pack_description.pack_name} DFP ({self.part_number}): " + f"element has duplicate name '{pname}'") + continue + + # Add the processor, with temp AP and base address. + self._processors_map[pname] = ProcessorInfo(name=pname, total_units=punits) + + except MalformedCmsisPackError as err: + LOG.warning("%s", err) + + # At least one processor must have been defined. + if len(self._processors_map) == 0: + LOG.warning( + f"{self.pack_description.pack_name} DFP ({self.part_number}): no " + "elements were found") + + # Add dummy processor. + self._processors_map["unknown"] = ProcessorInfo(name="unknown") + + def _build_aps_map(self) -> None: + """@brief Extract map of __apids and Pname to AP. + + Process the , , and elements to extract maps of __apid values + to AP addresses. Also extracts a map of processor Pname values to AP addresses. + """ + # Go ahead and set this flag so we don't try to rebuild the map in case there's an error. + self._built_apid_map = True + + self._handle_accessports() + self._handle_processors() + assert len(self._processors_map) + + for debug in self._info.debugs: + try: + # Get the Pname attribute. If there isn't one, just use the first (there should only be + # one) processor's name. + if 'Pname' in debug.attrib: + pname = debug.attrib['Pname'] + else: + pname = list(self._processors_map.keys())[0] + + if pname not in self._processors_map: + raise MalformedCmsisPackError( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{debug.tag}> " + f"references undefined processor name ('{pname}')") + + # Check for __apid attribute. + if '__apid' in debug.attrib: + apid = self._get_int_attribute(debug, '__apid') + if apid not in self._apids: + raise MalformedCmsisPackError( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{debug.tag}> " + f"references undefined '__apid' ({apid})") + + ap_address = self._apids[apid] + # Fall back to __ap address with optional __dp. + elif '__ap' in debug.attrib: + # Get and validate optional __dp. + dp_index = self._get_int_attribute(debug, '__dp', 0) + if dp_index not in self.valid_dps: + raise MalformedCmsisPackError( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{debug.tag}> " + f"'__dp' attribute is invalid ({dp_index})") + + ap_index = self._get_int_attribute(debug, '__ap') + ap_address = APv1Address(ap_index, dp_index) + # Otherwise define a default AP #0. + else: + ap_address = APv1Address(0) + + # Update address info for this processor. + try: + proc = self._processors_map[pname] + except KeyError: + raise MalformedCmsisPackError( + f"{self.pack_description.pack_name} DFP ({self.part_number}): <{debug.tag}> " + f"'Pname' attribute is invalid ({pname})") + proc.unit = self._get_int_attribute(debug, 'Punit', 0) + proc.ap_address = ap_address + proc.address = self._get_int_attribute(debug, 'address', 0) + proc.svd_path = debug.attrib.get('svd') + if 'defaultResetSequence' in debug.attrib: + # Still need to validate the specified default reset sequence after this. If not + # set, the default value is 'ResetSystem'. + proc.default_reset_sequence = debug.attrib['defaultResetSequence'] + except MalformedCmsisPackError as err: + LOG.warning("%s", err) + + def __repr__(self): + return "<%s@%x %s>" % (self.__class__.__name__, id(self), self.part_number) diff --git a/pyocd/target/pack/flash_algo.py b/pyocd/target/pack/flash_algo.py index 75bb91f44..d7d77e52e 100644 --- a/pyocd/target/pack/flash_algo.py +++ b/pyocd/target/pack/flash_algo.py @@ -19,13 +19,18 @@ import struct import logging import itertools +from typing import (TYPE_CHECKING, Any, Dict, Iterator, List, Optional, Sequence, Set, Tuple) from ...debug.elf.elf import ELFBinaryFile from ...utility.compatibility import to_str_safe from ...core.memory_map import MemoryRange from ...core import exceptions from ...utility.conversion import byte_list_to_u32le_list -from ...utility.mask import align_up +from ...utility.mask import align_down + +if TYPE_CHECKING: + from ...debug.elf.elf import ELFSection + from ...core.memory_map import RamRegion LOG = logging.getLogger(__name__) @@ -33,7 +38,9 @@ class FlashAlgoException(exceptions.TargetSupportError): """@brief Exception class for errors parsing an FLM file.""" pass -class PackFlashAlgo(object): +RoRwZiType = Tuple[Optional["ELFSection"], Optional["ELFSection"], Optional[MemoryRange]] + +class PackFlashAlgo: """@brief Class to wrap a flash algo This class is intended to provide easy access to the information @@ -77,9 +84,8 @@ class PackFlashAlgo(object): ## @brief Size of the flash blob header in bytes. _FLASH_BLOB_HEADER_SIZE = len(_FLASH_BLOB_HEADER) * 4 - # Minimum and maximum sizes allocated for the flash algo stack. + # Minimum size that must be allocated for the flash algo stack. _MIN_STACK_SIZE = 512 - _MAX_STACK_SIZE = 8192 # Alignment for page buffers. _PAGE_BUFFER_ALIGN = 16 @@ -94,8 +100,9 @@ def __init__(self, data): self.page_size = self.flash_info.page_size self.sector_sizes = self.flash_info.sector_info_list - symbols = {} - symbols.update(self._extract_symbols(self.REQUIRED_SYMBOLS)) + symbols: Dict[str, int] = {} + x = self._extract_symbols(self.REQUIRED_SYMBOLS) + symbols.update(x) symbols.update(self._extract_symbols(self.EXTRA_SYMBOLS, default=0xFFFFFFFF)) self.symbols = symbols @@ -107,6 +114,7 @@ def __init__(self, data): raise FlashAlgoException(error_msg) sect_ro, sect_rw, sect_zi = ro_rw_zi + assert sect_ro and sect_rw and sect_zi self.ro_start = sect_ro.start self.ro_size = sect_ro.length self.rw_start = sect_rw.start @@ -116,7 +124,29 @@ def __init__(self, data): self.algo_data = self._create_algo_bin(ro_rw_zi) - def get_pyocd_flash_algo(self, blocksize, ram_region): + def iter_sector_size_ranges(self) -> Iterator[Tuple[MemoryRange, int]]: + """@brief Iterator yielding tuples with a memory ranges and sector size for each of the algo's + sector sizes. + """ + # The sector_sizes attribute is a list of bi-tuples of (start-address, sector-size), sorted by start address. + for j, (offset, sector_size) in enumerate(self.sector_sizes): + start = self.flash_start + offset + + # Determine the end address of the this sector range. For the last range, the end + # is just the end of the entire region. Otherwise it's the start of the next + # range - 1. + if j + 1 >= len(self.sector_sizes): + end = self.flash_start + self.flash_size - 1 + else: + end = self.flash_start + self.sector_sizes[j + 1][0] - 1 + + # Skip wrong start and end addresses + if end < start: + continue + + yield MemoryRange(start, end), sector_size + + def get_pyocd_flash_algo(self, blocksize: int, ram_region: "RamRegion") -> Dict[str, Any]: """@brief Return a dictionary representing a pyOCD flash algorithm, or None. The most interesting operation this method performs is dynamically allocating memory @@ -127,7 +157,8 @@ def get_pyocd_flash_algo(self, blocksize, ram_region): Memory layout: ``` - [code] [buf1] [buf2] [<--stack] + [<--stack] [buf2] [buf1] [code] + ^ ram start ^ ram end ``` @param self @@ -135,83 +166,63 @@ def get_pyocd_flash_algo(self, blocksize, ram_region): @param ram_region A RamRegion object where the flash algo will be allocated. @return A pyOCD-style flash algo dictionary. If None is returned, the flash algo did not fit into the provided ram_region. + + @exception FlashAlgoException Raised if the algo cannot be placed in memory. """ instructions = self._FLASH_BLOB_HEADER + byte_list_to_u32le_list(self.algo_data) - offset = 0 + # Start at end of RAM and work backwards. + addr = ram_region.start + ram_region.length # Load address - addr_load = ram_region.start + offset - offset += len(instructions) * 4 + addr -= len(instructions) * 4 + addr_load = addr # Data buffer 1 - unaligned_buffer_addr = ram_region.start + offset - addr_data = align_up(unaligned_buffer_addr, self._PAGE_BUFFER_ALIGN) - offset += blocksize + (addr_data - unaligned_buffer_addr) + unaligned_buffer_addr = addr - blocksize + addr = align_down(unaligned_buffer_addr, self._PAGE_BUFFER_ALIGN) + addr_data = addr - if offset > ram_region.length: + if addr_data < ram_region.start: # Not enough space for flash algorithm - LOG.warning("Not enough space for flash algorithm") - return None + raise FlashAlgoException("not enough memory space to fit flash algorithm") # Data buffer 2 - unaligned_buffer_addr = ram_region.start + offset - addr_data2 = align_up(unaligned_buffer_addr, self._PAGE_BUFFER_ALIGN) - data2_offset = offset + blocksize + (addr_data2 - unaligned_buffer_addr) + unaligned_buffer_addr = addr - blocksize + addr = align_down(unaligned_buffer_addr, self._PAGE_BUFFER_ALIGN) + addr_data2 = addr # Stack # Select best fit for one or two data buffers and a variable size stack. # TODO Switching down from two to one buffer should probably be done with the stack size around # mid-level instead of going all the way down to minimum first. - min_stack_offset_one_buf = offset + self._MIN_STACK_SIZE - max_stack_offset_one_buf = offset + self._MAX_STACK_SIZE - min_stack_offset_two_bufs = data2_offset + self._MIN_STACK_SIZE - max_stack_offset_two_bufs = data2_offset + self._MAX_STACK_SIZE - - stack_size = self._MAX_STACK_SIZE - - # Max stack with double buffering - if max_stack_offset_two_bufs <= ram_region.length: - stack_offset = max_stack_offset_two_bufs - # Between min and max stack with double buffering - elif min_stack_offset_two_bufs <= ram_region.length: - stack_size = ram_region.length - min_stack_offset_two_bufs - stack_offset = data2_offset + stack_size - # Max stack with single buffer - elif max_stack_offset_one_buf <= ram_region.length: - stack_offset = max_stack_offset_one_buf - # Between min and max stack with single buffer - elif min_stack_offset_one_buf <= ram_region.length: - stack_size = ram_region.length - min_stack_offset_one_buf - stack_offset = offset + stack_size - else: - # Cannot fit single buffer and minimum stack. - LOG.warning("Not enough space for flash algorithm") - return None - - addr_stack = ram_region.start + stack_offset + stack_size_one_buf = addr_data - ram_region.start + stack_size_two_bufs = addr_data2 - ram_region.start - # Data buffer list - if stack_offset > data2_offset: - page_buffers = [addr_data, addr_data2] + if stack_size_two_bufs < self._MIN_STACK_SIZE: + # One buffer + stack_size = stack_size_one_buf + addr_stack = addr_data + page_buffers = [addr_data] - LOG.debug("flash algo: [code=%#x] [b1=%#x,%#x] [b2=%#x,%#x] [stack=%#x; %#x b] (ram=%#010x, %#x b)", - len(instructions) * 4, - addr_data - ram_region.start, offset, - addr_data2 - ram_region.start, data2_offset, - stack_offset, stack_size, + LOG.debug("flash algo: [stack=%#x; %#x b] [b1=%#x,+%#x] [code=%#x,+%#x,%#x b] (ram=%#010x, %#x b)", + addr_stack, stack_size, + addr_data, addr_data - ram_region.start, + addr_load, addr_load - ram_region.start, len(instructions) * 4, ram_region.start, ram_region.length ) else: - page_buffers = [addr_data] + stack_size = stack_size_two_bufs + addr_stack = addr_data2 + page_buffers = [addr_data, addr_data2] - LOG.debug("flash algo: [code=%#x] [b1=%#x,%#x] [stack=%#x; %#x b] (ram=%#010x, %#x b)", - len(instructions) * 4, - addr_data - ram_region.start, offset, - stack_offset, stack_size, + LOG.debug("flash algo: [stack=%#x; %#x b] [b2=%#x,+%#x] [b1=%#x,+%#x] [code=%#x,+%#x,%#x b] (ram=%#010x, %#x b)", + addr_stack, stack_size, + addr_data, addr_data - ram_region.start, + addr_data2, addr_data2 - ram_region.start, + addr_load, addr_load - ram_region.start, len(instructions) * 4, ram_region.start, ram_region.length ) - # TODO - analyzer support code_start = addr_load + self._FLASH_BLOB_HEADER_SIZE @@ -233,9 +244,9 @@ def get_pyocd_flash_algo(self, blocksize, ram_region): } return flash_algo - def _extract_symbols(self, symbols, default=None): + def _extract_symbols(self, symbols: Set[str], default: Optional[int] = None) -> Dict[str, int]: """@brief Fill 'symbols' field with required flash algo symbols""" - to_ret = {} + to_ret: Dict[str, int] = {} for symbol in symbols: symbolInfo = self.elf.symbol_decoder.get_symbol_for_name(symbol) if symbolInfo is None: @@ -246,9 +257,9 @@ def _extract_symbols(self, symbols, default=None): to_ret[symbol] = symbolInfo.address return to_ret - def _find_sections(self, name_type_pairs): + def _find_sections(self, name_type_pairs: Sequence[Tuple[str, str]]) -> Tuple[Optional["ELFSection"], ...]: """@brief Return a list of sections the same length and order of the input list""" - sections = [None] * len(name_type_pairs) + sections: List[Optional["ELFSection"]] = [None] * len(name_type_pairs) for section in self.elf.sections: section_name = to_str_safe(section.name) section_type = section.type @@ -259,9 +270,9 @@ def _find_sections(self, name_type_pairs): raise FlashAlgoException("Elf contains duplicate section %s attr %s" % (section_name, section_type)) sections[i] = section - return sections + return tuple(sections) - def _algo_fill_zi_if_missing(self, ro_rw_zi): + def _algo_fill_zi_if_missing(self, ro_rw_zi: RoRwZiType) -> RoRwZiType: """@brief Create an empty zi section if it is missing""" s_ro, s_rw, s_zi = ro_rw_zi if s_rw is None: @@ -271,7 +282,7 @@ def _algo_fill_zi_if_missing(self, ro_rw_zi): s_zi = MemoryRange(start=(s_rw.start + s_rw.length), length=0) return s_ro, s_rw, s_zi - def _algo_check_for_section_problems(self, ro_rw_zi): + def _algo_check_for_section_problems(self, ro_rw_zi: RoRwZiType) -> Optional[str]: """@brief Return a string describing any errors with the layout or None if good""" s_ro, s_rw, s_zi = ro_rw_zi if s_ro is None: @@ -288,9 +299,10 @@ def _algo_check_for_section_problems(self, ro_rw_zi): return "ZI section does not follow RW section" return None - def _create_algo_bin(self, ro_rw_zi): + def _create_algo_bin(self, ro_rw_zi: RoRwZiType): """Create a binary blob of the flash algo which can execute from ram""" sect_ro, sect_rw, sect_zi = ro_rw_zi + assert sect_ro and sect_rw and sect_zi algo_size = sect_ro.length + sect_rw.length + sect_zi.length algo_data = bytearray(algo_size) for section in (sect_ro, sect_rw): @@ -314,9 +326,11 @@ class PackFlashInfo(object): def __init__(self, elf): dev_info = elf.symbol_decoder.get_symbol_for_name("FlashDevice") if dev_info is None: - values = [0] * 10 + values: Sequence[Any] = [0] * 10 values[1] = b"" self.sector_info_list = [] + info_start = 0 + info_size = 0 else: info_start = dev_info.address info_size = struct.calcsize(self.FLASH_DEVICE_STRUCT) diff --git a/pyocd/target/pack/flm_region_builder.py b/pyocd/target/pack/flm_region_builder.py new file mode 100644 index 000000000..e52b9af2c --- /dev/null +++ b/pyocd/target/pack/flm_region_builder.py @@ -0,0 +1,226 @@ +# pyOCD debugger +# Copyright (c) 2022-2023 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import logging +from pathlib import PurePath +from typing import (Any, Dict, cast, TYPE_CHECKING) + +from ...core.memory_map import ( + FlashRegion, + MemoryMap, + MemoryRange, + MemoryType, + RamRegion, +) +from .flash_algo import (PackFlashAlgo, FlashAlgoException) + +if TYPE_CHECKING: + from ...coresight.coresight_target import CoreSightTarget + from ...core.memory_map import (MemoryMap) + +LOG = logging.getLogger(__name__) + +class FlmFlashRegionBuilder: + """ + @brief Finishes the process of constructing flash regions with algos based on FLM files. + + If a flash region passed to finalise_region() is missing an algo dict but has an associated FLM + algo file, the FLM will be loaded. + """ + + def __init__(self, target: "CoreSightTarget", memory_map: "MemoryMap") -> None: + self._target = target + self._session = target.session + self._memory_map = memory_map + + def finalise_region(self, region: FlashRegion) -> bool: + """@brief Load FLM file for the given flash region. + + The region is ignored if it has an algo dict already, or if it doesn't have an FLM file. Otherwise + the algo dict is constructed from the FLM and subregions are added for each of the algo's sector + size ranges. + + @return Boolean indicating whether the region was finalised successfully. + """ + try: + # If the region doesn't have an algo dict but does have an FLM file, try to load + # the FLM and create the algo dict. + if (region.algo is None) and (region.flm is not None): + if isinstance(region.flm, (str, PurePath)): + flm_path = self._session.find_user_file(None, [str(region.flm)]) + if flm_path is not None: + LOG.info("Creating flash algo for region %s from: %s", region.name, flm_path) + pack_algo = PackFlashAlgo(flm_path) + else: + LOG.warning("Failed to find FLM file: %s", region.flm) + return False + elif isinstance(region.flm, PackFlashAlgo): + pack_algo = region.flm + else: + LOG.warning("Flash region %s flm attribute is unexpected type", region) + return False + + # Log details of this flash algo if the debug option is enabled. + if self._session.options.get("debug.log_flm_info"): + LOG.debug("Flash algo info: %s", pack_algo.flash_info) + + # Get the page size. If it's unreasonably small, then use the smallest sector size. + page_size = pack_algo.page_size + if page_size <= 32: + page_size = min(s[1] for s in pack_algo.sector_sizes) + + # Select the RAM to use for the algo. + try: + ram_for_algo = self._select_flash_ram(region) + except RuntimeError: + return False + + # Create the algo dict from the FLM. + algo = pack_algo.get_pyocd_flash_algo(page_size, ram_for_algo) + + # If we got a valid algo from the FLM, set it on the region. + if algo is not None: + region.algo = algo + + # Set region page/sector sizes and algorithm range; add sector subregions. + self._update_flash_attributes(region, pack_algo, page_size, algo) + + return True + except FlashAlgoException as algo_err: + LOG.warning("Failed to load flash algorithm for region '%s' (%x-%x): %s", + region.name, region.start, region.end, algo_err) + return False + + def _select_flash_ram(self, region: FlashRegion) -> RamRegion: + """@brief Choose the RAM region to use for the given flash region's algo. + + @exception RuntimeError No RAM region is available. + """ + # See if an explicit RAM range was specified for the algo. + if hasattr(region, '_RAMstart'): + ram_start = region._RAMstart + + # The region size comes either from the RAMsize attribute, the containing region's + # bounds, or a large, arbitrary value. + if hasattr(region, '_RAMsize'): + ram_size = region._RAMsize + else: + containing_region = self._memory_map.get_region_for_address(ram_start) + if containing_region is not None: + ram_size = containing_region.length - (ram_start - containing_region.start) + else: + # No size specified, and the RAMstart attribute is outside of a known region, + # so just use a mid-range arbitrary size. + ram_size = 16 * 1024 + + ram_for_algo = RamRegion(start=ram_start, length=ram_size) + else: + # No RAM addresses were given, so go with the RAM marked default. + ram_for_algo = cast(RamRegion, self._memory_map.get_default_region_of_type(MemoryType.RAM)) + # Must have a default ram. + if ram_for_algo is None: + LOG.warning(f"CMSIS-Pack device {self._target.part_number} has no default RAM defined; cannot program flash") + raise RuntimeError("no default RAM") + + return ram_for_algo + + def _update_flash_attributes( + self, + region: FlashRegion, + pack_algo: PackFlashAlgo, + page_size: int, + algo: Dict[str, Any], + ) -> None: + """Depending on the sector size(s) defined by the flash algorithm, either simply set + the parent flash region's attributes or create sector size subregions.""" + # First set the region's start and end if they weren't set. + if region.start == region.end: + # Directly access the attributes. Normally region start/end are not settable to + # prevent modification of regions in a memory map such that they overlap. + region._start = pack_algo.flash_start + region._end = pack_algo.flash_start + pack_algo.flash_size - 1 + + # Don't need to create subregions if there is a single sector size and its range + # starts at the same address and is equal or larger than the parent flash region. + sector_sizes = list(pack_algo.iter_sector_size_ranges()) + create_subregions = not (len(sector_sizes) == 1 + and sector_sizes[0][0].start == region.start + and sector_sizes[0][0].end >= region.end) + + if create_subregions: + self._add_flash_subregions(region, pack_algo, page_size, algo) + else: + # Set attributes on parent flash region. The parent region still has to have these attributes + # even though there are subregions. + region.attributes['page_size'] = page_size + region.attributes['sector_size'] = sector_sizes[0][1] + + def _add_flash_subregions( + self, + region: FlashRegion, + pack_algo: PackFlashAlgo, + page_size: int, + algo: Dict[str, Any], + ) -> None: + """@brief Create subregions of the parent flash region for each sector size. + + The overall range of combined sector sizes doesn't necessarily fill the parent region's + entire size. Conversely, the algorithm may define more sectors than fit in the parent + region. + """ + max_sector_size = 0 + + # Create subregions. + for range, sector_size in pack_algo.iter_sector_size_ranges(): + # Limit subregion range to parent region size. There are cases (eg nRF5340, nRF9160) where + # the flash algo defines a larger flash memory, then the DFP's attribute sets a + # smaller value. + if not region.contains_range(range): + range = MemoryRange(max(region.start, range.start), end=min(region.end, range.end)) + if range.is_empty: + continue + + # Track maximum sector size. + max_sector_size = max(max_sector_size, sector_size) + + # Limit page size. + if page_size > sector_size: + region_page_size = sector_size + LOG.warning(f"Page size ({page_size}) is larger than sector size ({sector_size}) for flash " + f"region {region.name}; using sector size") + else: + region_page_size = page_size + + # Construct unique region name. + region_name = region.name + f"_{sector_size:#x}" + + subregion = FlashRegion( + name=region_name, + access=region.access, + start=range.start, + end=range.end, + sector_size=sector_size, + page_size=region_page_size, + erased_byte_value=pack_algo.flash_info.value_empty, + algo=algo, + ) + + region.submap.add_region(subregion) + + # Set attributes on parent flash region. The parent region still has to have these attributes + # even though there are subregions. + region.attributes['page_size'] = page_size + region.attributes['sector_size'] = max_sector_size diff --git a/pyocd/target/pack/pack_target.py b/pyocd/target/pack/pack_target.py index dc415905b..0ed42303e 100644 --- a/pyocd/target/pack/pack_target.py +++ b/pyocd/target/pack/pack_target.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2017-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,22 +15,37 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging import os -from typing import (IO, TYPE_CHECKING, Callable, Iterable, List, Optional, Type, Union) +from typing import (cast, Callable, Dict, IO, Iterable, List, Optional, Set, Tuple, Type, Union, TYPE_CHECKING) + from .cmsis_pack import (CmsisPack, CmsisPackDevice, MalformedCmsisPackError) +from .reset_sequence_maps import (RESET_SEQUENCE_TO_TYPE_MAP, RESET_TYPE_TO_SEQUENCE_MAP) from ..family import FAMILIES -from .. import TARGET +from .. import (normalise_target_type_name, TARGET) +from ...core import exceptions +from ...core.target import Target +from ...coresight.ap import APv1Address from ...coresight.coresight_target import CoreSightTarget +from ...coresight.cortex_m import CortexM +from ...debug.sequences.delegates import DebugSequenceDelegate +from ...debug.sequences.functions import DebugSequenceCommonFunctions +from ...debug.sequences.sequences import (Block, DebugSequence, DebugSequenceExecutionContext) +from ...debug.sequences.scope import Scope from ...debug.svd.loader import SVDFile -from .. import normalise_target_type_name +from ...core.session import Session +from ...probe.debug_probe import DebugProbe if TYPE_CHECKING: from zipfile import ZipFile from cmsis_pack_manager import CmsisPackRef - from ...core.session import Session from ...utility.sequencer import CallSequence + from ...core.core_target import CoreTarget + from ...commands.execution_context import CommandSet + from ...utility.notification import Notification try: import cmsis_pack_manager @@ -62,7 +77,7 @@ class ManagedPacksImpl: """ @staticmethod - def get_installed_packs(cache: Optional[cmsis_pack_manager.Cache] = None) -> List["CmsisPackRef"]: # type:ignore + def get_installed_packs(cache: Optional[cmsis_pack_manager.Cache] = None) -> List[CmsisPackRef]: # type:ignore """@brief Return a list containing CmsisPackRef objects for all installed packs.""" if cache is None: cache = cmsis_pack_manager.Cache(True, True) @@ -84,9 +99,13 @@ def get_installed_targets(cache: Optional[cmsis_pack_manager.Cache] = None) -> L cache = cmsis_pack_manager.Cache(True, True) results = [] for pack in ManagedPacks.get_installed_packs(cache=cache): - pack_path = os.path.join(cache.data_path, pack.get_pack_name()) - pack = CmsisPack(pack_path) - results += list(pack.devices) + try: + pack_path = os.path.join(cache.data_path, pack.get_pack_name()) + pack = CmsisPack(pack_path) + results += list(pack.devices) + except Exception as err: + LOG.error("failure to access managed CMSIS-Pack: %s", + err, exc_info=Session.get_current().log_tracebacks) return sorted(results, key=lambda dev:dev.part_number) @staticmethod @@ -108,11 +127,253 @@ def populate_target(device_name: str) -> None: else: ManagedPacks = ManagedPacksStub +class PackDebugSequenceDelegate(DebugSequenceDelegate): + """! @brief Main delegate for debug sequences.""" + + ## Map from pyocd reset types to the __connection variable reset type field. + # + # 0=error, 1=hw, 2=SYSRESETREQ, 3=VECTRESET + RESET_TYPE_MAP = { + Target.ResetType.HW: 1, + Target.ResetType.SW: 2, # TODO pick default sw reset type + Target.ResetType.SW_SYSRESETREQ: 2, + Target.ResetType.SW_VECTRESET: 3, + Target.ResetType.SW_EMULATED: 2, # no direct match + } + + def __init__(self, target: CoreSightTarget, device: CmsisPackDevice) -> None: + self._target = target + self._session = target.session + self._pack_device = device + self._sequences: Set[DebugSequence] = device.sequences + self._debugvars: Optional[Scope] = None + self._functions = DebugSequenceCommonFunctions() + + self._session.options.subscribe(self._debugvars_did_change, 'pack.debug_sequences.debugvars') + + @property + def all_sequences(self) -> Set[DebugSequence]: + return self._sequences + + @property + def cmsis_pack_device(self) -> CmsisPackDevice: + """@brief Accessor for the pack device that contains the sequences.""" + return self._pack_device + + def get_root_scope(self, context: DebugSequenceExecutionContext) -> Scope: + """@brief Return a scope that will be used as the parent of sequences.""" + # TODO should a fresh exec context be used? debugvars aren't supposed to depend on any + # runtime debug settings nor do they even have access to those variables. + if self._debugvars is not None: + return self._debugvars + + # Populate a scope with definitions from the element, if defined. If not defined, + # the the scope will be empty. + self._debugvars = Scope(name="debugvars") + debugvars_block = self._pack_device.debug_vars_sequence + if debugvars_block is not None: + # This is the only case where a Block will be pushed to the context stack. + with context.push(debugvars_block, self._debugvars): + debugvars_block.execute(context) + + # Now run the debugvars session option, if defined, as a block to override default + # debugvars values from the element. + debugvars_option = self._session.options.get('pack.debug_sequences.debugvars') + if (debugvars_option is not None) and (debugvars_option.strip() != ""): + debugvars_option_block = Block(debugvars_option) + # This is the only case where a Block will be pushed to the context stack. + with context.push(debugvars_option_block, self._debugvars): + debugvars_option_block.execute(context) + + # Make all vars read-only. + self._debugvars.freeze() + + # Debug log all debugvar values. + if LOG.isEnabledFor(logging.INFO): + for name in sorted(self._debugvars.variables): + value = self._debugvars.get(name) + LOG.info(f"debugvar '{name}' = {value:#x} ({value:d})") + + return self._debugvars + + def _debugvars_did_change(self, notification: Notification) -> None: + """@brief Notification handler for change to pack.debug_sequences.debugvars option.""" + # Clear the cached debugvars scope to force it to be rebuilt. + self._debugvars = None + + def _is_sequence_manually_disabled(self, name: str, pname: Optional[str] = None) -> bool: + """@brief Check session options to see if the sequence has been disabled by the user.""" + disabled_seqs = self._session.options.get('pack.debug_sequences.disabled_sequences') + if not disabled_seqs: + return False + + name = name.casefold() + if pname is not None: + pname = pname.casefold() + + for dseq in disabled_seqs: + if ':' in dseq: + dseq, core_name = dseq.split(':') + core_name = core_name.casefold() + else: + core_name = None + dseq = dseq.casefold() + + if (name == dseq) and ((core_name is None) or (pname == core_name)): + return True + + return False + + def run_sequence(self, name: str, pname: Optional[str] = None) -> Optional[Scope]: + """@brief Run a top level debug sequence. + + @return The scope created while running the sequence is returned. If the sequence wasn't executed + for some reason, e.g. it was disabled, then None is returned instead. + """ + pname_desc = f" ({pname})" if (pname and LOG.isEnabledFor(logging.DEBUG)) else "" + + # Handle global debug sequence enable. + if not self._session.options.get('pack.debug_sequences.enable'): + LOG.debug("Not running debug sequence '%s'%s because all sequences are disabled", + name, pname_desc) + return None + + # Error out for invalid sequence. + if not self.has_sequence_with_name(name, pname): + raise NameError(name) + + # Get the sequence object. + seq = self.get_sequence_with_name(name, pname) + + # If the sequence is disabled, we won't run it. + if not seq.is_enabled: + LOG.debug("Not running disabled debug sequence '%s'%s", name, pname_desc) + return None + # Check for manual disabling of this sequence. + if self._is_sequence_manually_disabled(name, pname): + LOG.debug("Not running debug sequence '%s'%s because it was manually disabled", name, pname_desc) + return None + + LOG.debug("Running debug sequence '%s'%s", name, pname_desc) + + # Create runtime context and contextified functions instance. + context = DebugSequenceExecutionContext(self._session, self, pname) + + # Map optional pname to AP address. If the pname is not specified, then use the device's + # first available AP. If no APs are known (eg haven't been discovered yet) then use 0. + if pname: + proc_map = self._pack_device.processors_map + ap_address = proc_map[pname].ap_address + else: + ap = self._target.first_ap + if ap is not None: + ap_address = ap.address + else: + ap_address = APv1Address(0) + + # Set the default AP in the exec context. + context.default_ap = ap_address + + # Activate the context while running this sequence, making the context available + # to sequence functions. + with context: + try: + executed_scope = seq.execute(context) + except exceptions.Error as err: + if pname: + LOG.error("Error while running debug sequence '%s' (core %s): %s", name, pname, err) + else: + LOG.error("Error while running debug sequence '%s': %s", name, err) + raise + + return executed_scope + + def sequences_for_pname(self, pname: Optional[str]) -> Dict[str, DebugSequence]: + # Return *only* sequences with no Pname when passed pname=None. Otherwise we'd have + # to mangle the dict keys to include pname since there can be multiple sequences with + # the same name but different + return { + seq.name: seq + for seq in self._sequences + if (seq.pname is None) or (seq.pname == pname) + } + + def has_sequence_with_name(self, name: str, pname: Optional[str] = None) -> bool: + return name in self.sequences_for_pname(pname) + + def get_sequence_with_name(self, name: str, pname: Optional[str] = None) -> DebugSequence: + return self.sequences_for_pname(pname)[name] + + def get_protocol(self) -> int: + """@brief Return the value for the __protocol variable. + __protocol fields: + - [15:0] 0=error, 1=JTAG, 2=SWD, 3=cJTAG + - [16] SWJ-DP present? + - [17] switch through dormant state? + """ + session = self._target.session + assert session.probe, "must have a valid probe" + # Not having a wire protocol set is allowed if performing pre-reset since it will only + # execute ResetHardware (or equivalent), which can only access pins and such (theoretically). + assert self._session.context_state.is_performing_pre_reset or session.probe.wire_protocol, \ + "must have valid, connected probe" + if session.probe.wire_protocol == DebugProbe.Protocol.JTAG: + protocol = 1 + elif session.probe.wire_protocol == DebugProbe.Protocol.SWD: + protocol = 2 + else: + protocol = 0 # Error + if session.options.get('dap_swj_enable'): + protocol |= 1 << 16 + if session.options.get('dap_swj_use_dormant'): + protocol |= 1 << 17 + return protocol + + def get_connection_type(self) -> int: + """@brief Return the value for the __connection variable. + __connection fields: + - [7:0] connection type: 0=error/disconnected, 1=for debug, 2=for flashing + - [15:8] reset type: 0=error, 1=hw, 2=SYSRESETREQ, 3=VECTRESET + - [16] connect under reset? + - [17] pre-connect reset? + """ + ctype = 1 + ctype |= self.RESET_TYPE_MAP.get(self._session.options.get('reset_type'), 0) << 8 + + connect_mode = self._target.session.options.get('connect_mode') + if connect_mode == 'under-reset': + ctype |= 1 << 16 + + # The pre-reset bit should only be set when running ResetHardware for a connect pre-reset. + # This is stored in the is_performing_pre_reset session state variable, set by CoreSightTarget's + # pre_connect() method. + if self._session.context_state.is_performing_pre_reset: + ctype |= 1 << 17 + return ctype + + def get_traceout(self) -> int: + """@brief Return the value for the __traceout variable. + __traceout fields: + - [0] SWO enabled? + - [1] parallel trace enabled? + - [2] trace buffer enabled? + - [21:16] selected parallel trace port size + """ + # Set SWO bit depending on the option value. + return 1 if self._target.session.options.get('enable_swv') else 0 + + def get_sequence_functions(self) -> DebugSequenceCommonFunctions: + return self._functions + class _PackTargetMethods: - """@brief Container for methods added to the dynamically generated pack target subclass.""" + """@brief Container for methods added to the dynamically generated pack target subclass. + + We can't just make a subclass of CoreSightTarget out of these methods, because the superclass + is variable based on the possible family class. + """ @staticmethod - def _pack_target__init__(self, session: "Session") -> None: # type:ignore + def _pack_target__init__(self, session: Session) -> None: # type:ignore """@brief Constructor for dynamically created target class.""" super(self.__class__, self).__init__(session, self._pack_device.memory_map) @@ -122,22 +383,142 @@ def _pack_target__init__(self, session: "Session") -> None: # type:ignore self._svd_location = SVDFile(filename=self._pack_device.svd) + self.debug_sequence_delegate = PackDebugSequenceDelegate(self, self._pack_device) + @staticmethod - def _pack_target_create_init_sequence(self) -> "CallSequence": # type:ignore + def _pack_target_create_init_sequence(self) -> CallSequence: # type:ignore """@brief Creates an init task to set the default reset type.""" seq = super(self.__class__, self).create_init_sequence() + seq.wrap_task('discovery', lambda seq: seq.insert_after('create_cores', - ('set_default_reset_type', self.set_default_reset_type) + ('configure_core_reset', self.configure_core_reset) ) ) return seq @staticmethod - def _pack_target_set_default_reset_type(self) -> None: # type:ignore - """@brief Set's the first core's default reset type to the one specified in the pack.""" - if 0 in self.cores: - self.cores[0].default_reset_type = self._pack_device.default_reset_type + def _pack_target_configure_core_reset(self) -> None: # type:ignore + """@brief Init sequence method to configure resets for all cores. + + This init sequence method is designed to run after the cores have been created by standard + discovery. + + Sets each core's default reset type to the one specified in the pack, and configures the + list of enabled reset types. + """ + for core_num, core in self.cores.items(): + # Look up the processor info for this core. + core_ap_addr = core.ap.address + try: + proc_info = self._pack_device.processors_ap_map[core_ap_addr] + except KeyError: + LOG.debug("core #%d not specified in DFP", core_num) + continue + + # Get this processor's list of sequences. + sequences = self.debug_sequence_delegate.sequences_for_pname(proc_info.name) + + def is_reset_sequence_enabled(name: str) -> bool: + return (name not in sequences) or sequences[name].is_enabled + + # Set the supported reset types by filtering existing supported reset types. + updated_reset_types: Set[Target.ResetType] = set() + for resettype in core._supported_reset_types: + # These two types are not in the map, and should always be present. + if resettype in (Target.ResetType.SW, Target.ResetType.SW_EMULATED): + updated_reset_types.add(resettype) + continue + + resettype_sequence_name = RESET_TYPE_TO_SEQUENCE_MAP[resettype] + if is_reset_sequence_enabled(resettype_sequence_name): + updated_reset_types.add(resettype) + + # Special case to enable processor reset even when the core doesn't support VECTRESET, if + # there is a non-default ResetProcessor sequence definition. + if ((Target.ResetType.SW_CORE not in updated_reset_types) # type:ignore + and ('ResetProcessor' in sequences) + and sequences['ResetProcessor'].is_enabled): + updated_reset_types.add(Target.ResetType.SW_CORE) # type:ignore + + core._supported_reset_types = updated_reset_types + LOG.debug(f"updated DFP core #{core_num} reset types: {core._supported_reset_types}") + + default_reset_seq = proc_info.default_reset_sequence + + # Check that the default reset sequence is a standard sequence. The specification allows for + # custom reset sequences to be used, but that is not supported by pyocd yet. + # TODO support custom default reset sequences (requires a new reset type) + if default_reset_seq not in RESET_SEQUENCE_TO_TYPE_MAP: + if default_reset_seq in sequences: + # Custom reset sequence, not yet supported by pyocd. + LOG.warning("DFP device definition error: custom reset sequences are not yet supported " + "by pyocd; core #%d (%s) requested default reset sequence %s", + core_num, proc_info.name, default_reset_seq) + else: + # Invalid/unknown default reset sequence. + LOG.warning("DFP device definition error: specified default reset sequence %s " + "for core #%d (%s) does not exist", + default_reset_seq, core_num, proc_info.name) + + # Handle multicore debug mode causing secondary cores to default to processor reset. + did_force_core_reset = False + if (self.session.options.get('enable_multicore_debug') + and (core_num != self.session.options.get('primary_core'))): + if not is_reset_sequence_enabled('ResetProcessor'): + LOG.warning("Multicore debug mode cannot select processor reset for secondary core " + "#%d (%s) because it is disabled by the DFP; using emulated processor " + "reset instead", core_num, proc_info.name) + core.default_reset_type = Target.ResetType.SW_EMULATED + continue + else: + default_reset_seq = 'ResetProcessor' + did_force_core_reset = True + + # Verify that the specified default reset sequence hasn't been disabled. + if not is_reset_sequence_enabled(default_reset_seq): + # Only log a warning if we didn't decide to use core reset due to multicore mode. + if not did_force_core_reset: + LOG.warning("DFP device definition conflict: specified default reset sequence %s " + "for core #%d (%s) is disabled by the DFP", + default_reset_seq, core_num, proc_info.name) + + # Map from disabled default to primary and secondary fallbacks. + RESET_FALLBACKS: Dict[str, Tuple[str, str]] = { + 'ResetSystem': ('ResetProcessor', 'ResetHardware'), + 'ResetHardware': ('ResetSystem', 'ResetProcessor'), + 'ResetProcessor': ('ResetSystem', 'ResetHardware'), + } + + # Select another default. + fallbacks = RESET_FALLBACKS[default_reset_seq] + if is_reset_sequence_enabled(fallbacks[0]): + default_reset_seq = fallbacks[0] + elif is_reset_sequence_enabled(fallbacks[1]): + default_reset_seq = fallbacks[1] + else: + LOG.warning("DFP device definition conflict: all reset types are disabled for " + "core #%d (%s) by the DFP; using emulated core reset", + default_reset_seq, core_num) + core.default_reset_type = Target.ResetType.SW_EMULATED + continue + + LOG.info("Setting core #%d (%s) default reset sequence to %s", + core_num, proc_info.name, default_reset_seq) + core.default_reset_type = RESET_SEQUENCE_TO_TYPE_MAP[default_reset_seq] + + @staticmethod + def _pack_target_add_core(_self, core: CoreTarget) -> None: + """@brief Override to set node name of added core to its pname.""" + pname = _self._pack_device.processors_ap_map[cast(CortexM, core).ap.address].name + core.node_name = pname + CoreSightTarget.add_core(_self, core) + + @staticmethod + def _pack_target_add_target_command_groups(_self, command_set: CommandSet): + """@brief Add pack related commands to the command set.""" + command_set.add_command_group('pack-target') + class PackTargets: """@brief Namespace for CMSIS-Pack target generation utilities. """ @@ -155,6 +536,8 @@ def _find_family_class(dev: CmsisPackDevice) -> Type[CoreSightTarget]: # Require the regex to match the entire family name. match = familyInfo.matches.match(compare_name) if match and match.span() == (0, len(compare_name)): + LOG.debug("using family class %s for %s (matched against %s)", + familyInfo.klass.__name__, dev.part_number, compare_name) return familyInfo.klass # Didn't match, so return default target superclass. @@ -179,7 +562,9 @@ def _generate_pack_target_class(dev: CmsisPackDevice) -> Optional[type]: "_pack_device": dev, "__init__": _PackTargetMethods._pack_target__init__, "create_init_sequence": _PackTargetMethods._pack_target_create_init_sequence, - "set_default_reset_type": _PackTargetMethods._pack_target_set_default_reset_type, + "configure_core_reset": _PackTargetMethods._pack_target_configure_core_reset, + "add_core": _PackTargetMethods._pack_target_add_core, + "add_target_command_groups": _PackTargetMethods._pack_target_add_target_command_groups, }) return targetClass except (MalformedCmsisPackError, FileNotFoundError) as err: @@ -195,16 +580,17 @@ def populate_device(dev: CmsisPackDevice) -> None: @param dev A CmsisPackDevice object. """ try: - tgt = PackTargets._generate_pack_target_class(dev) - if tgt is None: - return + # Check if we're even going to populate this target before bothing to build the class. part = normalise_target_type_name(dev.part_number) + if part in TARGET: + LOG.debug("did not populate target for DFP part number %s because there is already " + "a %s target installed", dev.part_number, part) + return - # Make sure there isn't a duplicate target name. - if part not in TARGET: + # Generate target subclass and install it. + tgt = PackTargets._generate_pack_target_class(dev) + if tgt: TARGET[part] = tgt - else: - LOG.debug("did not populate %s because there is already a %s target installed", dev.part_number, part) except (MalformedCmsisPackError, FileNotFoundError) as err: LOG.warning(err) @@ -223,8 +609,8 @@ def process_targets_from_pack( @param cb Callable to run. Must take a CmsisPackDevice object as the sole parameter and return None. """ if not isinstance(pack_list, (list, tuple)): - pack_list = [pack_list] - for pack_or_path in pack_list: + pack_list = [pack_list] # type:ignore + for pack_or_path in pack_list: # type:ignore if isinstance(pack_or_path, CmsisPack): pack = pack_or_path else: @@ -244,7 +630,7 @@ def populate_targets_from_pack(pack_list: Union[PackReferenceType, Iterable[Pack """ PackTargets.process_targets_from_pack(pack_list, PackTargets.populate_device) -def is_pack_target_available(target_name: str, session: "Session") -> bool: +def is_pack_target_available(target_name: str, session: Session) -> bool: """@brief Test whether a given target type is available.""" # Create targets from provided CMSIS pack. if session.options['pack'] is not None: diff --git a/pyocd/target/pack/reset_sequence_maps.py b/pyocd/target/pack/reset_sequence_maps.py new file mode 100644 index 000000000..82cb69c63 --- /dev/null +++ b/pyocd/target/pack/reset_sequence_maps.py @@ -0,0 +1,35 @@ +# pyOCD debugger +# Copyright (c) 2022 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...core.target import Target + +## Map from DFP reset sequence names to our reset types. +RESET_SEQUENCE_TO_TYPE_MAP = { + 'ResetHardware': Target.ResetType.HW, + 'ResetSystem': Target.ResetType.SW_SYSTEM, + 'ResetProcessor': Target.ResetType.SW_CORE, +} + +## Map from DFP reset sequence names to our reset types. +# +# ResetType.SW is expected to have been mapped to its actual value before using this map. +# ResetType.SW_EMULATED doesn't have a corresponding reset sequence, so it must be handled +# in another way. +RESET_TYPE_TO_SEQUENCE_MAP = { + Target.ResetType.HW: 'ResetHardware', + Target.ResetType.SW_SYSTEM: 'ResetSystem', + Target.ResetType.SW_CORE: 'ResetProcessor', +} diff --git a/pyocd/tools/lists.py b/pyocd/tools/lists.py index 159136e21..743f4dbc0 100644 --- a/pyocd/tools/lists.py +++ b/pyocd/tools/lists.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2018-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,7 +16,7 @@ # limitations under the License. import os -import pkg_resources +from importlib_metadata import entry_points from .. import __version__ from ..core.session import Session @@ -235,7 +235,7 @@ def list_plugins(): 'plugins': plugin_list, } - for entry_point in pkg_resources.iter_entry_points(group_name): + for entry_point in entry_points(group=group_name): klass = entry_point.load() plugin = klass() info = { diff --git a/pyocd/trace/events.py b/pyocd/trace/events.py index 51b303ee5..dc79616b2 100644 --- a/pyocd/trace/events.py +++ b/pyocd/trace/events.py @@ -1,5 +1,6 @@ # pyOCD debugger # Copyright (c) 2017-2019 Arm Limited +# Copyright (c) 2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,65 +15,67 @@ # See the License for the specific language governing permissions and # limitations under the License. -class TraceEvent(object): +from typing import Optional + +class TraceEvent: """@brief Base trace event class.""" - def __init__(self, desc="", ts=0): + def __init__(self, desc: str = "", ts: int = 0) -> None: self._desc = desc self._timestamp = ts @property - def timestamp(self): + def timestamp(self) -> int: return self._timestamp @timestamp.setter - def timestamp(self, ts): + def timestamp(self, ts: int) -> None: self._timestamp = ts - def __str__(self): + def __str__(self) -> str: return "[{}] {}".format(self._timestamp, self._desc) - def __repr__(self): + def __repr__(self) -> str: return "<{}: {}>".format(self.__class__.__name__, str(self)) class TraceOverflow(TraceEvent): """@brief Trace overflow event.""" - def __init__(self, ts=0): - super(TraceOverflow, self).__init__("overflow", ts) + def __init__(self, ts: int = 0) -> None: + super().__init__("overflow", ts) class TraceTimestamp(TraceEvent): """@brief Trace local timestamp.""" - def __init__(self, tc, ts=0): - super(TraceTimestamp, self).__init__("timestamp", ts) - self._tc = 0 + def __init__(self, tc: int, ts: int = 0): + super().__init__("timestamp", ts) + self._tc = tc @property - def tc(self): + def tc(self) -> int: return self._tc - def __str__(self): + def __str__(self) -> str: return "[{}] local timestamp TC={:#x} {}".format(self._timestamp, self.tc, self.timestamp) class TraceITMEvent(TraceEvent): """@brief Trace ITM stimulus port event.""" - def __init__(self, port, data, width, ts=0): - super(TraceITMEvent, self).__init__("itm", ts) + def __init__(self, port: int, data: int, width: int, ts: int = 0) -> None: + super().__init__("itm", ts) self._port = port self._data = data self._width = width @property - def port(self): + def port(self) -> int: return self._port @property - def data(self): + def data(self) -> int: return self._data @property - def width(self): + def width(self) -> int: return self._width - def __str__(self): + def __str__(self) -> str: width = self.width if width == 1: d = "{:#04x}".format(self.data) @@ -91,15 +94,15 @@ class TraceEventCounter(TraceEvent): FOLD_MASK = 0x10 CYC_MASK = 0x20 - def __init__(self, counterMask, ts=0): - super(TraceEventCounter, self).__init__("exception", ts) - self._mask = counterMask + def __init__(self, counter_mask: int, ts: int = 0) -> None: + super().__init__("exception", ts) + self._mask = counter_mask @property - def counter_mask(self): + def counter_mask(self) -> int: return self._mask - def _get_event_desc(self, evt): + def _get_event_desc(self, evt: int) -> str: msg = "" if evt & TraceEventCounter.CYC_MASK: msg += " Cyc" @@ -115,7 +118,7 @@ def _get_event_desc(self, evt): msg += " CPI" return msg - def __str__(self): + def __str__(self) -> str: return "[{}] DWT: Event:{}".format(self.timestamp, self._get_event_desc(self.counter_mask)) class TraceExceptionEvent(TraceEvent): @@ -130,39 +133,40 @@ class TraceExceptionEvent(TraceEvent): RETURNED : "Returned" } - def __init__(self, exceptionNumber, exceptionName, action, ts=0): - super(TraceExceptionEvent, self).__init__("exception", ts) - self._number = exceptionNumber - self._name = exceptionName + def __init__(self, exception_number: int, exception_name: Optional[str], action: int, ts: int = 0) -> None: + super().__init__("exception", ts) + self._number = exception_number + self._name = exception_name or "" self._action = action @property - def exception_number(self): + def exception_number(self) -> int: return self._number @property - def exception_name(self): + def exception_name(self) -> str: + """@note This property is deprecated.""" return self._name @property - def action(self): + def action(self) -> int: return self._action - def __str__(self): + def __str__(self) -> str: action = TraceExceptionEvent.ACTION_DESC.get(self.action, "") return "[{}] DWT: Exception #{:d} {} {}".format(self.timestamp, self.exception_number, action, self.exception_name) class TracePeriodicPC(TraceEvent): """@brief Periodic PC trace event.""" - def __init__(self, pc, ts=0): - super(TracePeriodicPC, self).__init__("pc", ts) + def __init__(self, pc: int, ts: int = 0) -> None: + super().__init__("pc", ts) self._pc = pc @property - def pc(self): + def pc(self) -> int: return self._pc - def __str__(self): + def __str__(self) -> str: return "[{}] DWT: PC={:#010x}".format(self.timestamp, self.pc) class TraceDataTraceEvent(TraceEvent): @@ -175,50 +179,61 @@ class TraceDataTraceEvent(TraceEvent): - PC value, data value, whether it was read or written, and the transfer size. - Bits[15:0] of a data address, data value, whether it was read or written, and the transfer size. """ - def __init__(self, cmpn=None, pc=None, addr=None, value=None, rnw=None, sz=None, ts=0): - super(TraceDataTraceEvent, self).__init__("data-trace", ts) + def __init__( + self, + cmpn: Optional[int] = None, + pc: Optional[int] = None, + addr: Optional[int] = None, + value: Optional[int] = None, + rnw: Optional[int] = None, + sz: Optional[int] = None, + ts: int = 0 + ) -> None: + super().__init__("data-trace", ts) self._cmpn = cmpn self._pc = pc self._addr = addr self._value = value self._rnw = rnw self._sz = sz + # Setting a value must also include a read/write flag and value size. + assert (self._value is None) or ((self._rnw is not None) and (self._sz is not None)) @property - def comparator(self): + def comparator(self) -> Optional[int]: return self._cmpn @property - def pc(self): + def pc(self) -> Optional[int]: return self._pc @property - def address(self): + def address(self) -> Optional[int]: return self._addr @property - def value(self): + def value(self) -> Optional[int]: return self._value @property - def is_read(self): + def is_read(self) -> Optional[int]: return self._rnw @property - def transfer_size(self): + def transfer_size(self) -> Optional[int]: return self._sz - def __str__(self): - hasPC = self.pc is not None - hasAddress = self.address is not None - hasValue = self.value is not None - if hasPC: + def __str__(self) -> str: + has_pc = self.pc is not None + has_address = self.address is not None + has_value = self.value is not None + if has_pc: msg = "PC={:#010x}".format(self.pc) - elif hasAddress: + elif has_address: msg = "Addr[15:0]={:#06x}".format(self.address) else: msg = "" - if hasValue: + if has_value: width = self.transfer_size rnw = "R" if self.is_read else "W" if width == 1: diff --git a/pyocd/trace/sink.py b/pyocd/trace/sink.py index e8bd49730..31991d60b 100644 --- a/pyocd/trace/sink.py +++ b/pyocd/trace/sink.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2017-2019 Arm Limited -# COpyright (c) 2021 Chris Reed +# COpyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,10 +16,14 @@ # limitations under the License. import collections.abc +from typing import (TYPE_CHECKING, Iterable, List, Optional, Sequence, Union) -class TraceEventSink(object): +if TYPE_CHECKING: + from .events import TraceEvent + +class TraceEventSink: """@brief Abstract interface for a trace event sink.""" - def receive(self, event): + def receive(self, event: "TraceEvent") -> None: """@brief Handle a single trace event. @param self @param event An instance of TraceEvent or one of its subclasses. @@ -29,14 +33,14 @@ def receive(self, event): class TraceEventFilter(TraceEventSink): """@brief Abstract interface for a trace event filter.""" - def __init__(self, sink=None): + def __init__(self, sink: Optional[TraceEventSink] = None) -> None: self._sink = sink - def connect(self, sink): + def connect(self, sink: TraceEventSink) -> None: """@brief Connect the downstream trace sink or filter.""" self._sink = sink - def receive(self, event): + def receive(self, event: "TraceEvent") -> None: """@brief Handle a single trace event. Passes the event through the filter() method. If one or more objects are returned, they @@ -45,15 +49,15 @@ def receive(self, event): @param self @param event An instance of TraceEvent or one of its subclasses. """ - event = self.filter(event) - if (event is not None) and (self._sink is not None): + filtered_event = self.filter(event) + if (filtered_event is not None) and (self._sink is not None): if isinstance(event, collections.abc.Iterable): for event_item in event: self._sink.receive(event_item) else: self._sink.receive(event) - def filter(self, event): + def filter(self, event: "TraceEvent") -> Union[None, "TraceEvent", Sequence["TraceEvent"]]: """@brief Filter a single trace event. @param self @@ -65,10 +69,10 @@ def filter(self, event): class TraceEventTee(TraceEventSink): """@brief Trace event sink that replicates events to multiple sinks.""" - def __init__(self): - self._sinks = [] + def __init__(self) -> None: + self._sinks: List[TraceEventSink] = [] - def connect(self, sinks): + def connect(self, sinks: Iterable[TraceEventSink]) -> None: """@brief Connect one or more downstream trace sinks. @param self @@ -77,11 +81,11 @@ def connect(self, sinks): completely replace the current list of trace event sinks. """ if isinstance(sinks, collections.abc.Iterable): - self._sinks = sinks + self._sinks = list(sinks) elif sinks not in self._sinks: self._sinks.append(sinks) - def receive(self, event): + def receive(self, event: "TraceEvent") -> None: """@brief Replicate a single trace event to all connected downstream trace event sinks. @param self diff --git a/pyocd/trace/swo.py b/pyocd/trace/swo.py index 769fb706a..85dd5d05c 100644 --- a/pyocd/trace/swo.py +++ b/pyocd/trace/swo.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2017-2019 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,9 +15,15 @@ # See the License for the specific language governing permissions and # limitations under the License. +from typing import (TYPE_CHECKING, Generator, Iterable, List, Optional) + from . import events -class SWOParser(object): +if TYPE_CHECKING: + from ..core.core_target import CoreTarget + from .sink import TraceEventSink + +class SWOParser: """@brief SWO data stream parser. Processes a stream of SWO data and generates TraceEvent objects. SWO data is passed to the @@ -28,32 +34,32 @@ class SWOParser(object): A SWOParser instance can be reused for multiple SWO sessions. If a break in SWO data streaming occurs, the reset() method should be called before passing further data to parse(). """ - def __init__(self, core, sink=None): + def __init__(self, core: "CoreTarget", sink: Optional["TraceEventSink"] = None) -> None: self.reset() self._core = core self._sink = sink - def reset(self): + def reset(self) -> None: self._bytes_parsed = 0 self._itm_page = 0 self._timestamp = 0 - self._pending_events = [] + self._pending_events: List[events.TraceEvent] = [] self._pending_data_trace = None # Get generator instance and prime it. self._parser = self._parse() next(self._parser) - def connect(self, sink): + def connect(self, sink: "TraceEventSink") -> None: """@brief Connect the downstream trace sink or filter.""" self._sink = sink @property - def bytes_parsed(self): + def bytes_parsed(self) -> int: """@brief The number of bytes of SWO data parsed thus far.""" return self._bytes_parsed - def parse(self, data): + def parse(self, data: Iterable[int]) -> None: """@brief Process SWO data. This method will return once the provided data is consumed, and can be called again when @@ -68,14 +74,14 @@ def parse(self, data): self._parser.send(value) self._bytes_parsed += 1 - def _flush_events(self): + def _flush_events(self) -> None: """@brief Send all pending events to event sink.""" if self._sink is not None: for event in self._pending_events: self._sink.receive(event) self._pending_events = [] - def _merge_data_trace_events(self, event): + def _merge_data_trace_events(self, event: events.TraceEvent) -> bool: """@brief Look for pairs of data trace events and merge.""" if isinstance(event, events.TraceDataTraceEvent): # Record the first data trace event. @@ -106,7 +112,7 @@ def _merge_data_trace_events(self, event): self._pending_data_trace = None return False - def _send_event(self, event): + def _send_event(self, event: events.TraceEvent) -> None: """@brief Process event objects and decide when to send to event sink. This method handles the logic to associate a timestamp event with the prior other @@ -132,7 +138,7 @@ def _send_event(self, event): if flush: self._flush_events() - def _parse(self): + def _parse(self) -> Generator[None, int, None]: """@brief SWO parser as generator function coroutine. The generator yields every time it needs a byte of SWO data. The caller must use the @@ -240,11 +246,13 @@ def _parse(self): self._send_event(events.TraceEventCounter(payload, timestamp)) # Exception trace elif a == 1: - exceptionNumber = payload & 0x1ff - exceptionName = self._core.exception_number_to_name(exceptionNumber, True) + exception_number = payload & 0x1ff + # TODO remove exception name and dependency on core + exception_name = self._core.exception_number_to_name(exception_number) fn = (payload >> 12) & 0x3 if 1 <= fn <= 3: - self._send_event(events.TraceExceptionEvent(exceptionNumber, exceptionName, fn, timestamp)) + self._send_event(events.TraceExceptionEvent( + exception_number, exception_name, fn, timestamp)) else: invalid = True # Periodic PC @@ -264,7 +272,8 @@ def _parse(self): self._send_event(events.TraceDataTraceEvent(cmpn=cmpn, addr=payload, ts=timestamp)) # Data value elif type == 0b10: - self._send_event(events.TraceDataTraceEvent(cmpn=cmpn, value=payload, rnw=(bit3 == 0), sz=l, ts=timestamp)) + self._send_event(events.TraceDataTraceEvent( + cmpn=cmpn, value=payload, rnw=(bit3 == 0), sz=l, ts=timestamp)) else: invalid = True # Invalid DWT 'a' value. diff --git a/pyocd/trace/swv.py b/pyocd/trace/swv.py index 850ef667c..118cd3479 100644 --- a/pyocd/trace/swv.py +++ b/pyocd/trace/swv.py @@ -19,9 +19,10 @@ import logging import threading from time import sleep +from typing import (Optional, TextIO, TYPE_CHECKING) from .sink import TraceEventSink -from .events import TraceITMEvent +from .events import (TraceEvent, TraceITMEvent) from .swo import SWOParser from ..coresight.itm import ITM from ..coresight.tpiu import TPIU @@ -30,19 +31,23 @@ from ..probe.debug_probe import DebugProbe from ..utility.server import StreamServer +if TYPE_CHECKING: + from ..core.session import Session + from ..utility.notification import Notification + LOG = logging.getLogger(__name__) class SWVEventSink(TraceEventSink): """@brief Trace event sink that converts ITM packets to a text stream.""" - def __init__(self, console): + def __init__(self, console: TextIO) -> None: """@brief Constructor. @param self @param console File-like object to which SWV data will be written. """ self._console = console - def receive(self, event): + def receive(self, event: TraceEvent) -> None: """@brief Handle an SWV trace event. @param self @param event An instance of TraceITMEvent. If the event is not this class, or isn't @@ -70,24 +75,27 @@ def receive(self, event): class SWVReader(threading.Thread): """@brief Sets up SWV and processes data in a background thread.""" - def __init__(self, session, core_number=0, lock=None): + def __init__(self, session: "Session", core_number: int = 0, lock: Optional[threading.Lock] = None) -> None: """@brief Constructor. @param self @param session The Session instance. @param core_number The number of the core being traced. Default is core 0. """ - super(SWVReader, self).__init__() - self.name = "SWVReader" - self.daemon = True + super().__init__(name="SWVReader", daemon=True) self._session = session self._core_number = core_number self._shutdown_event = threading.Event() self._swo_clock = 0 self._lock = lock - self._session.subscribe(self._reset_handler, Target.Event.POST_RESET, self._session.target.cores[core_number]) + target = self._session.target + assert target + self._target = target + self._core = target.cores[core_number] + + self._session.subscribe(self._reset_handler, Target.Event.POST_RESET, self._core) - def init(self, sys_clock, swo_clock, console) -> bool: + def init(self, sys_clock: int, swo_clock: int, console: TextIO) -> bool: """@brief Configures trace graph and starts thread. This method performs all steps required to start up SWV. It first calls the target's @@ -107,20 +115,21 @@ def init(self, sys_clock, swo_clock, console) -> bool: """ self._swo_clock = swo_clock + assert self._session.probe if DebugProbe.Capability.SWO not in self._session.probe.capabilities: LOG.warning(f"SWV not initalized: Probe {self._session.probe.unique_id} does not support SWO") return False - itm = self._session.target.get_first_child_of_type(ITM) + itm = self._target.get_first_child_of_type(ITM) if not itm: LOG.warning("SWV not initalized: Target does not have ITM component") return False - tpiu = self._session.target.get_first_child_of_type(TPIU) + tpiu = self._target.get_first_child_of_type(TPIU) if not tpiu: LOG.warning("SWV not initalized: Target does not have TPIU component") return False - self._session.target.trace_start() + self._target.trace_start() itm.init() itm.enable() @@ -132,7 +141,7 @@ def init(self, sys_clock, swo_clock, console) -> bool: LOG.warning("SWV not initalized: Failed to set SWO clock rate") return False - self._parser = SWOParser(self._session.target.cores[self._core_number]) + self._parser = SWOParser(self._core) self._sink = SWVEventSink(console) self._parser.connect(self._sink) @@ -140,7 +149,7 @@ def init(self, sys_clock, swo_clock, console) -> bool: return True - def stop(self): + def stop(self) -> None: """@brief Stops processing SWV data. The reader thread is terminated first, then the ITM is disabled. The last step is to call @@ -155,19 +164,20 @@ def stop(self): self.join() # init() should never have started the SWV thread unless the target has ITM and TPIU. - itm = self._session.target.get_first_child_of_type(ITM) + itm = self._target.get_first_child_of_type(ITM) assert itm itm.disable() - self._session.target.trace_stop() + self._target.trace_stop() - def run(self): + def run(self) -> None: """@brief SWV reader thread routine. Starts the probe receiving SWO data by calling DebugProbe.swo_start(). For as long as the thread runs, it reads SWO data from the probe and passes it to the SWO parser created in init(). When the thread is signaled to stop, it calls DebugProbe.swo_stop() before exiting. """ + assert self._session.probe if self._lock: self._lock.acquire() @@ -209,12 +219,12 @@ def run(self): if self._lock: self._lock.release() - def _reset_handler(self, notification): + def _reset_handler(self, notification: "Notification") -> None: """@brief Reset notification handler. If the target is reset while the SWV reader is running, then the Target::trace_start() method is called to reinit trace output. """ if self.is_alive(): - self._session.target.trace_start() + self._target.trace_start() diff --git a/pyocd/utility/cmdline.py b/pyocd/utility/cmdline.py index 47952be03..a40aac9dc 100644 --- a/pyocd/utility/cmdline.py +++ b/pyocd/utility/cmdline.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,7 +16,7 @@ # limitations under the License. import logging -from typing import (Any, Dict, Iterable, List, Optional, Tuple, Union, cast) +from typing import (Any, Callable, Dict, Iterable, List, Optional, Tuple, Union, cast) from ..core.target import Target from ..core.options import OPTIONS_INFO @@ -128,6 +128,26 @@ def convert_vector_catch(vcvalue: Union[str, bytes]) -> int: # Reraise an error with a more helpful message. raise ValueError("invalid vector catch option '{}'".format(e.args[0])) +def _convert_string_list_option(value: Optional[str]) -> List[str]: + """@brief Convert a comma-separated list of strings. + + A None value results in an empty list. + + No special support for quoted values is provided, so a comma in between quotes is treated + the same as a comma elsewhere. + """ + if value is None: + return [] + return [ + i.strip() + for i in value.split(',') + ] + +## Map with special converter routines for session options that need them. +_OPTION_CONVERTERS: Dict[str, Callable[[Optional[str]], Any]] = { + 'pack.debug_sequences.disabled_sequences': _convert_string_list_option, +} + def convert_one_session_option(name: str, value: Optional[str]) -> Tuple[str, Any]: """@brief Convert one session option's value from a string. @@ -157,6 +177,10 @@ def convert_one_session_option(name: str, value: Optional[str]) -> Tuple[str, An LOG.warning("'no-' prefix used on non-boolean session option '%s'", name) return name, None + # Check for a special converter function. + if name in _OPTION_CONVERTERS: + return name, _OPTION_CONVERTERS[name](value) + # Default result; unset option value. result = None @@ -222,9 +246,13 @@ def convert_session_options(option_list: Iterable[str]) -> Dict[str, Any]: 'sw': Target.ResetType.SW, 'hardware': Target.ResetType.HW, 'software': Target.ResetType.SW, + 'sw_system': Target.ResetType.SW_SYSTEM, + 'sw_core': Target.ResetType.SW_CORE, 'sw_sysresetreq': Target.ResetType.SW_SYSRESETREQ, 'sw_vectreset': Target.ResetType.SW_VECTRESET, 'sw_emulated': Target.ResetType.SW_EMULATED, + 'system': Target.ResetType.SW_SYSTEM, + 'core': Target.ResetType.SW_CORE, 'sysresetreq': Target.ResetType.SW_SYSRESETREQ, 'vectreset': Target.ResetType.SW_VECTRESET, 'emulated': Target.ResetType.SW_EMULATED, diff --git a/pyocd/utility/conversion.py b/pyocd/utility/conversion.py index 636bd7022..2ecce509e 100644 --- a/pyocd/utility/conversion.py +++ b/pyocd/utility/conversion.py @@ -17,13 +17,11 @@ import struct import binascii -from typing import (Any, Iterator, Sequence, Tuple, cast) +from typing import (Any, Iterator, List, Sequence, Tuple, cast) from .mask import align_up -ByteList = Sequence[int] - -def byte_list_to_nbit_le_list(data: ByteList, bitwidth: int, pad: int = 0x00) -> Sequence[int]: +def byte_list_to_nbit_le_list(data: Sequence[int], bitwidth: int, pad: int = 0x00) -> List[int]: """@brief Convert a list of bytes to a list of n-bit integers (little endian) If the length of the data list is not a multiple of `bitwidth` // 8, then the pad value is used @@ -46,7 +44,7 @@ def byte_list_to_nbit_le_list(data: ByteList, bitwidth: int, pad: int = 0x00) -> res.append(sum((padded_data[i] << (i * 8)) for i in range(bytewidth))) return res -def nbit_le_list_to_byte_list(data: Sequence[int], bitwidth: int) -> ByteList: +def nbit_le_list_to_byte_list(data: Sequence[int], bitwidth: int) -> List[int]: """@brief Convert a list of n-bit values into a byte list. @param data List of n-bit values. @@ -55,7 +53,7 @@ def nbit_le_list_to_byte_list(data: Sequence[int], bitwidth: int) -> ByteList: """ return [(x >> shift) & 0xff for x in data for shift in range(0, bitwidth, 8)] -def byte_list_to_u32le_list(data: ByteList, pad: int = 0x00) -> Sequence[int]: +def byte_list_to_u32le_list(data: Sequence[int], pad: int = 0x00) -> List[int]: """@brief Convert a list of bytes to a list of 32-bit integers (little endian) If the length of the data list is not a multiple of 4, then the pad value is used @@ -69,11 +67,11 @@ def byte_list_to_u32le_list(data: ByteList, pad: int = 0x00) -> Sequence[int]: data[i * 4 + 3] << 24) remainder = (len(data) % 4) if remainder != 0: - padCount = 4 - remainder - res += byte_list_to_u32le_list(list(data[-remainder:]) + [pad] * padCount) + pad_count = 4 - remainder + res += byte_list_to_u32le_list(list(data[-remainder:]) + [pad] * pad_count) return res -def u32le_list_to_byte_list(data: Sequence[int]) -> ByteList: +def u32le_list_to_byte_list(data: Sequence[int]) -> List[int]: """@brief Convert a word array into a byte array""" res = [] for x in data: @@ -83,18 +81,18 @@ def u32le_list_to_byte_list(data: Sequence[int]) -> ByteList: res.append((x >> 24) & 0xff) return res -def u16le_list_to_byte_list(data: Sequence[int]) -> ByteList: +def u16le_list_to_byte_list(data: Sequence[int]) -> List[int]: """@brief Convert a halfword array into a byte array""" - byteData = [] + byte_data = [] for h in data: - byteData.extend([h & 0xff, (h >> 8) & 0xff]) - return byteData + byte_data.extend([h & 0xff, (h >> 8) & 0xff]) + return byte_data -def byte_list_to_u16le_list(byteData: ByteList) -> Sequence[int]: +def byte_list_to_u16le_list(byte_data: Sequence[int]) -> List[int]: """@brief Convert a byte array into a halfword array""" data = [] - for i in range(0, len(byteData), 2): - data.append(byteData[i] | (byteData[i + 1] << 8)) + for i in range(0, len(byte_data), 2): + data.append(byte_data[i] | (byte_data[i + 1] << 8)) return data def u32_to_float32(data: int) -> float: @@ -173,7 +171,7 @@ def byte_to_hex2(val: int) -> str: """@brief Create 2-digit hexadecimal string from 8-bit value""" return "%02x" % int(val) -def hex_to_byte_list(data: str) -> ByteList: +def hex_to_byte_list(data: str) -> List[int]: """@brief Convert string of hex bytes to list of integers""" return list(binascii.unhexlify(data)) @@ -193,5 +191,3 @@ def pairwise(iterable: Iterator[Any]) -> Iterator[Tuple[Any, Any]]: if len(r) == 2: yield cast(Tuple[Any, Any], tuple(r)) r = [] - if len(r) > 0: - yield (r[0], r[1]) diff --git a/pyocd/utility/graph.py b/pyocd/utility/graph.py index 9cf01dbaa..31c5c93bd 100644 --- a/pyocd/utility/graph.py +++ b/pyocd/utility/graph.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2019 Arm Limited -# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021-2022 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,12 +15,15 @@ # See the License for the specific language governing permissions and # limitations under the License. -from typing import (Callable, List, Optional, Sequence, Type, Union) +from typing import (Callable, List, Optional, Sequence, Type, TypeVar, Union, cast) + +_T = TypeVar("_T", bound="GraphNode") class GraphNode: """@brief Simple graph node. All nodes have a parent, which is None for a root node, and zero or more children. + Nodes optionally have a name. Supports indexing and iteration over children. """ @@ -30,6 +33,16 @@ def __init__(self) -> None: super().__init__() self._parent: Optional[GraphNode] = None self._children: List[GraphNode] = [] + self._node_name: Optional[str] = None + + @property + def node_name(self) -> Optional[str]: + """@brief Name of this graph node.""" + return self._node_name + + @node_name.setter + def node_name(self, new_name: str) -> None: + self._node_name = new_name @property def parent(self) -> Optional["GraphNode"]: @@ -89,7 +102,7 @@ def _search(node: GraphNode): return _search(self) - def get_first_child_of_type(self, klass: Type) -> Optional["GraphNode"]: + def get_first_child_of_type(self, klass: Type[_T]) -> Optional[_T]: """@brief Breadth-first search for a child of the given class. @param self @param klass The class type to search for. The first child at any depth that is an instance @@ -99,16 +112,24 @@ def get_first_child_of_type(self, klass: Type) -> Optional["GraphNode"]: """ matches = self.find_children(lambda c: isinstance(c, klass)) if len(matches): - return matches[0] + return cast(Optional[_T], matches[0]) else: return None - def __getitem__(self, key: Union[int, slice]) -> Union["GraphNode", List["GraphNode"]]: - """@brief Returns the indexed child. + def __getitem__(self, key: Union[int, str, slice]) -> Union["GraphNode", List["GraphNode"]]: + """@brief Returns the child with the given index or node name. - Slicing is supported. + Slicing is supported with integer indexes. """ - return self._children[key] + if isinstance(key, str): + # Replace with dict at some point. + for c in self._children: + if c.node_name == key: + return c + else: + raise KeyError(f"no child node with name '{key}'") + else: + return self._children[key] def __iter__(self): """@brief Iterate over the node's children.""" diff --git a/pyocd/utility/rtt_server.py b/pyocd/utility/rtt_server.py new file mode 100644 index 000000000..43bfa65fd --- /dev/null +++ b/pyocd/utility/rtt_server.py @@ -0,0 +1,251 @@ +# pyOCD debugger +# Copyright (c) 2022 Samuel Dewan +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from abc import ABC, abstractmethod +import selectors +import socket +from typing import Optional, Sequence + +from ..core.soc_target import SoCTarget +from ..core import exceptions +from ..debug.rtt import RTTControlBlock, RTTUpChannel, RTTDownChannel + + +class RTTChanWorker(ABC): + """@brief Source and sink for data to be transferred over RTT. """ + + @abstractmethod + def write_up_data(self, data: bytes) -> int: + """@brief Write data that has been received from an up channel to the + correct destination. + + @param data The data to be written. + @return The number of bytes that were successfully written. + """ + pass + + @abstractmethod + def get_down_data(self) -> bytes: + """@brief Get data that should be written to a down channel if there is + any. + + @return Data to be written to down channel. + """ + pass + + @abstractmethod + def close(self): + """@brief Cleanup channel worker and close any file descriptors.""" + pass + + +class RTTChanTCPWorker(RTTChanWorker): + """@brief Implementation of channel worker that forwards RTT data via a TCP + socket. """ + + port: int + + def __init__(self, port: int, listen: bool = True): + """ + @param port The port to connect to or to listen for connects on. + @param listen If true a server will be started to accept one connection + at a time on the given port. If false a connection will be + made as a TCP client to a server running on the given + port on localhost. + """ + if listen: + self.server = socket.socket() + self.server.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1) + self.server.bind(('localhost', port)) + self.server.listen(1) + self.server.setblocking(False) + self.client = None + else: + self.server = None + self.client = socket.create_connection(('localhost', port), timeout = 1.0) + self.client.setblocking(False) + + self.port = port + + def _check_for_new_client(self): + if self.server is None: + return + + sel = selectors.DefaultSelector() + sel.register(self.server, selectors.EVENT_READ, None) + events = sel.select(timeout = 0) + for key, _ in events: + if key.fileobj == self.server: + self.client, _ = self.server.accept() + self.client.setblocking(False) + + def write_up_data(self, data: bytes): + if self.client is None: + self._check_for_new_client() + if self.client is None: + return 0 + + return self.client.send(data) + + def get_down_data(self): + if self.client is None: + self._check_for_new_client() + if self.client is None: + return b'' + + sel = selectors.DefaultSelector() + sel.register(self.client, selectors.EVENT_READ, None) + events = sel.select(timeout = 0) + for key, _ in events: + if key.fileobj == self.client: + data = self.client.recv(4096) + if not data: + # client socket closed at other end + self.client.close() + self.client = None + return data + + return bytes() + + def close(self): + if self.server is not None: + self.server.close() + if self.client is not None: + self.client.close() + +class RTTChanFileWorker(RTTChanWorker): + """@brief Implementation of channel worker that write data from RTT channel + to a file and optionally reads data from a file into an RTT + channel. """ + + +class RTTServer: + """@brief Keeps track of polling for multiple active RTT channels and the + sources and sinks of data for each channel. """ + control_block: RTTControlBlock + workers: Optional[Sequence[Optional[RTTChanWorker]]] + up_buffers: Optional[Sequence[bytes]] + down_buffers: Optional[Sequence[bytes]] + + def __init__(self, target: SoCTarget, address: int, size: int, + control_block_id: bytes): + """ + @param target The target with which RTT communication is desired. + @param address Base address for control block search range. + @param size Control block search range. If 0 the control block will be + expected to be located at the provided address. + @param control_block_id The control block ID string to search for. Must + be at most 16 bytes long. Will be padded with + zeroes if less than 16 bytes. + """ + self.control_block = RTTControlBlock.from_target(target, address = address, + size = size, control_block_id = control_block_id) + + self.workers = None + self.up_buffers = None + self.down_buffers = None + + def poll(self): + """@brief Reads from and writes to active RTT channels. """ + if not self.running: + # not yet started + return + + for i, worker in enumerate(self.workers): + if worker is None: + continue + + # Read from up channel + try: + up_chan: RTTUpChannel = self.control_block.up_channels[i] + except IndexError: + pass + else: + self.up_buffers[i] += up_chan.read() + + # Write to worker + bytes_written = worker.write_up_data(self.up_buffers[i]) + self.up_buffers[i] = self.up_buffers[i][bytes_written:] + + # Read from worker + self.down_buffers[i] += worker.get_down_data() + + # Write data to down channel + try: + down_chan: RTTDownChannel = self.control_block.down_channels[i] + except IndexError: + pass + else: + bytes_out: int = down_chan.write(self.down_buffers[i]) + self.down_buffers[i] = self.down_buffers[i][bytes_out:] + + def start(self): + """@brief Find and parse RTT control block. """ + self.control_block.start() + + num_up_chans: int = len(self.control_block.up_channels) + num_down_chans: int = len(self.control_block.down_channels) + num_chans: int = max(num_up_chans, num_down_chans) + + self.workers = [None] * num_chans + self.up_buffers = [bytes()] * num_up_chans + self.down_buffers = [bytes()] * num_down_chans + + def stop(self): + """@brief Close all RTT workers. """ + if not self.running: + return + + for i, worker in enumerate(self.workers): + if worker is not None: + worker.close() + + self.workers = None + self.up_buffers = None + self.down_buffers = None + + @property + def running(self): + """@brief True if RTT is started. """ + return self.workers is not None + + def add_server(self, port: int, channel: int): + """@brief Start a new TCP server to communicate with a given RTT channel. + + @param port The port on which the server should listen for new connections. + @param channel The RTT channel which should be exposed over TCP. + """ + if not self.running: + raise exceptions.RTTError("RTT is not yet started") + elif self.workers[channel] is not None: + raise exceptions.RTTError(f"RTT is already started for channel {channel}") + + self.workers[channel] = RTTChanTCPWorker(port, listen = True) + + def stop_server(self, port: int): + """@brief Stop a TCP server. + + @param port The port of the server to be stopped. + """ + + if not self.running: + return + + for i, worker in enumerate(self.workers): + if isinstance(worker, RTTChanTCPWorker): + if worker.port == port: + worker.close() + self.workers[i] = None diff --git a/scripts/set_version.sh b/scripts/set_version.sh new file mode 100755 index 000000000..1076a621e --- /dev/null +++ b/scripts/set_version.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +# Fill the version with the current commit number to simplify local debug + +FULL_SCRIPT_PATH="$(pwd)/${0}" +PROJECT_DIR="${FULL_SCRIPT_PATH%/scripts/*}" +cd "${PROJECT_DIR}" + +echo "version = '$(git describe --long --always)'" > pyocd/_version.py + +# Now you can run the following command inside of $PROJECT_DIR +# python3.8 -m pyocd --version diff --git a/setup.cfg b/setup.cfg index 928e39adf..d27543a50 100644 --- a/setup.cfg +++ b/setup.cfg @@ -22,11 +22,11 @@ classifiers = Operating System :: POSIX :: Linux Programming Language :: Python Programming Language :: Python :: 3 - Programming Language :: Python :: 3.6 Programming Language :: Python :: 3.7 Programming Language :: Python :: 3.8 Programming Language :: Python :: 3.9 Programming Language :: Python :: 3.10 + Programming Language :: Python :: 3.11 Topic :: Software Development Topic :: Software Development :: Debuggers Topic :: Software Development :: Embedded Systems @@ -44,16 +44,21 @@ project_urls = zip_safe = True include_package_data = True packages = find: -python_requires = >=3.6.0 +python_requires = >=3.7.0 # Use hidapi on macOS and Windows, not needed on Linux. +# +# importlib_resources is used instead of stdlib importlib.resources because we +# want the selectable entry_points API, which is not present until Python 3.10. install_requires = capstone>=4.0,<5.0 - cmsis-pack-manager>=0.4.0,<1.0 + cmsis-pack-manager>=0.5.2,<1.0 colorama<1.0 - dataclasses; python_version < "3.7" hidapi>=0.10.1,<1.0; platform_system != "Linux" + importlib_metadata>=3.6 + importlib_resources intelhex>=2.0,<3.0 intervaltree>=3.0.2,<4.0 + lark>=1.1.5,<2.0 libusb-package>=1.0,<2.0 natsort>=8.0.0,<9.0 prettytable>=2.0,<4.0 diff --git a/test/cortex_test.py b/test/cortex_test.py index 67fb6a00c..d90f7d661 100644 --- a/test/cortex_test.py +++ b/test/cortex_test.py @@ -204,51 +204,76 @@ def simulate_step(): print("\n\n------ Testing Reset Types ------") def reset_methods(fnc): - print("Hardware reset") - fnc(reset_type=Target.ResetType.HW) - print("Hardware reset (default=HW)") - target.selected_core.default_reset_type = Target.ResetType.HW - fnc(reset_type=None) - print("Software reset (default=SYSRESETREQ)") - target.selected_core.default_reset_type = Target.ResetType.SW_SYSRESETREQ - fnc(reset_type=None) - print("Software reset (default=VECTRESET)") - target.selected_core.default_reset_type = Target.ResetType.SW_VECTRESET - fnc(reset_type=None) - print("Software reset (default=emulated)") - target.selected_core.default_reset_type = Target.ResetType.SW_EMULATED - fnc(reset_type=None) - - print("(Default) Software reset (SYSRESETREQ)") - target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ - fnc(reset_type=Target.ResetType.SW) - print("(Default) Software reset (VECTRESET)") - target.selected_core.default_software_reset_type = Target.ResetType.SW_VECTRESET - fnc(reset_type=Target.ResetType.SW) - print("(Default) Software reset (emulated)") - target.selected_core.default_software_reset_type = Target.ResetType.SW_EMULATED - fnc(reset_type=Target.ResetType.SW) - - print("Software reset (option=default)") - target.selected_core.default_reset_type = Target.ResetType.SW - target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ - session.options['reset_type'] = 'default' - fnc(reset_type=None) - print("Software reset (option=hw)") - session.options['reset_type'] = 'hw' - fnc(reset_type=None) + test_hw_reset = Target.ResetType.HW in target.selected_core.supported_reset_types + test_system_reset = Target.ResetType.SW_SYSTEM in target.selected_core.supported_reset_types + test_core_reset = Target.ResetType.SW_CORE in target.selected_core.supported_reset_types + test_emulated_reset = Target.ResetType.SW_EMULATED in target.selected_core.supported_reset_types + + if test_hw_reset: + print("Hardware reset") + fnc(reset_type=Target.ResetType.HW) + print("Hardware reset (default=HW)") + target.selected_core.default_reset_type = Target.ResetType.HW + fnc(reset_type=None) + else: + print("Hardware reset is disabled") + if test_system_reset: + print("Software reset (default=SYSTEM)") + target.selected_core.default_reset_type = Target.ResetType.SW_SYSTEM + fnc(reset_type=None) + else: + print("System reset is disabled") + if test_core_reset: + print("Software reset (default=CORE)") + target.selected_core.default_reset_type = Target.ResetType.SW_CORE + fnc(reset_type=None) + else: + print("Core reset is disabled") + if test_emulated_reset: + print("Software reset (default=emulated)") + target.selected_core.default_reset_type = Target.ResetType.SW_EMULATED + fnc(reset_type=None) + else: + print("Emulated reset is disabled") + + if test_system_reset: + print("(Default) Software reset (SYSTEM)") + target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSTEM + fnc(reset_type=Target.ResetType.SW) + if test_core_reset: + print("(Default) Software reset (CORE)") + target.selected_core.default_software_reset_type = Target.ResetType.SW_CORE + fnc(reset_type=Target.ResetType.SW) + if test_emulated_reset: + print("(Default) Software reset (emulated)") + target.selected_core.default_software_reset_type = Target.ResetType.SW_EMULATED + fnc(reset_type=Target.ResetType.SW) + + if test_system_reset: + print("Software reset (option=default)") + target.selected_core.default_reset_type = Target.ResetType.SW + target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSTEM + session.options['reset_type'] = 'default' + fnc(reset_type=None) + if test_hw_reset: + print("Reset (option=hw)") + session.options['reset_type'] = 'hw' + fnc(reset_type=None) print("Software reset (option=sw)") session.options['reset_type'] = 'sw' fnc(reset_type=None) - print("Software reset (option=sw_sysresetreq)") - session.options['reset_type'] = 'sw_sysresetreq' - fnc(reset_type=None) - print("Software reset (option=sw_vectreset)") - session.options['reset_type'] = 'sw_vectreset' - fnc(reset_type=None) - print("Software reset (option=sw_emulated)") - session.options['reset_type'] = 'sw_emulated' - fnc(reset_type=None) + if test_system_reset: + print("Software reset (option=system)") + session.options['reset_type'] = 'system' + fnc(reset_type=None) + if test_core_reset: + print("Software reset (option=core)") + session.options['reset_type'] = 'core' + fnc(reset_type=None) + if test_emulated_reset: + print("Software reset (option=emulated)") + session.options['reset_type'] = 'emulated' + fnc(reset_type=None) reset_methods(target.reset) diff --git a/test/data/packs/LPC553XX_256.FLM b/test/data/packs/LPC553XX_256.FLM new file mode 100644 index 000000000..a2d502349 Binary files /dev/null and b/test/data/packs/LPC553XX_256.FLM differ diff --git a/test/data/packs/LPC553XX_FLEXSPI.FLM b/test/data/packs/LPC553XX_FLEXSPI.FLM new file mode 100644 index 000000000..5e1761e54 Binary files /dev/null and b/test/data/packs/LPC553XX_FLEXSPI.FLM differ diff --git a/test/data/packs/LPC553XX_FLEXSPI_S.FLM b/test/data/packs/LPC553XX_FLEXSPI_S.FLM new file mode 100644 index 000000000..a98a90d28 Binary files /dev/null and b/test/data/packs/LPC553XX_FLEXSPI_S.FLM differ diff --git a/test/data/packs/LPC553XX_S_256.FLM b/test/data/packs/LPC553XX_S_256.FLM new file mode 100644 index 000000000..a1c8df323 Binary files /dev/null and b/test/data/packs/LPC553XX_S_256.FLM differ diff --git a/test/data/packs/NXP.LPC55S36_DFP.13.0.0.pdsc b/test/data/packs/NXP.LPC55S36_DFP.13.0.0.pdsc new file mode 100644 index 000000000..a41da721b --- /dev/null +++ b/test/data/packs/NXP.LPC55S36_DFP.13.0.0.pdsc @@ -0,0 +1,333 @@ + + + LPC55S36_DFP + NXP + Device Family Pack for LPC55S36 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + Licenses.txt + + NXP CMSIS Packs based on MCUXpresso SDK 2.10.2 + + + Device Family Pack + + + NXP MCUXpresso SDK Project Template + NXP MCUXpresso SDK RTE Device Project Template + NXP MCUXpresso SDK Peripheral Drivers + NXP MCUXpresso SDK Utilities + NXP MCUXpresso SDK Start up + NXP MCUXpresso SDK Peripheral CMSIS Drivers + + + + + + + + + + + + + + + + __var SYSCON_NS_Base_Addr = 0x40000000; + __var IOCON_NS_Base_Addr = 0x40001000; + __var TRACECLKSEL_Addr = SYSCON_NS_Base_Addr + 0x268; + __var TRACECLKDIV_Addr = SYSCON_NS_Base_Addr + 0x308; + __var AHBCLKCTRLSET0_Addr = IOCON_NS_Base_Addr + 0x220; + __var clksel = 0; + __var clkdiv = 0; + + + + clksel = Read32(TRACECLKSEL_Addr); // Read current TRACECLKSEL value + + + + Write32(TRACECLKSEL_Addr, 0x0); // Select Trace divided clock + + + + clkdiv = (Read32(TRACECLKDIV_Addr) & 0xFF); // Read current TRACECLKDIV value, preserve divider but clear rest to enable + Write32(TRACECLKDIV_Addr, clkdiv); + + Write32(AHBCLKCTRLSET0_Addr, (1 << 13)); // Enable IOCON clock + + + + + + __var status=0x55aa; + Message(0, "LPC55xx connect srcipt start"); + + // Read APIDR + __dp = 0; + __ap = 2; + status = ReadAP(0xFC); + Message(0, "APIDR: 0x%08X", status); + + // Read DPIDR + __dp = 0; + __ap = 2; + status = ReadDP(0x0); + Message(0, "DPIDR: 0x%08X", status); + + // Active DebugMailbox + __dp = 0; + __ap = 2; + WriteAP(0x0, 0x00000021); + DAP_Delay(30000); + ReadAP(0x0); + + // Enter Debug Session + __dp = 0; + __ap = 2; + WriteAP(0x4, 0x00000007); + DAP_Delay(30000); + ReadAP(0x8); + + __dp = 0; + __ap = 0; + + Message(0, "LPC55xx connect srcipt end"); + + + + + __var SW_DP_ABORT = 0x0; + __var DP_CTRL_STAT = 0x4; + __var DP_SELECT = 0x8; + __var powered_down = 0; + // Switch to DP Register Bank 0 + WriteDP(DP_SELECT, 0x00000000); + + // Read DP CTRL/STAT Register and check if CSYSPWRUPACK and CDBGPWRUPACK bits are set + powered_down = ((ReadDP(DP_CTRL_STAT) & 0xA0000000) != 0xA0000000); + + + + // Request Debug/System Power-Up + WriteDP(DP_CTRL_STAT, 0x50000000); + + + + + + + // Init AP Transfer Mode, Transaction Counter, and Lane Mask (Normal Transfer Mode, Include all Byte Lanes) + WriteDP(DP_CTRL_STAT, 0x50000F00); + + // Clear WDATAERR, STICKYORUN, STICKYCMP, and STICKYERR bits of CTRL/STAT Register by write to ABORT register + WriteDP(SW_DP_ABORT, 0x0000001E); + + Sequence("EnableDebugMailbox"); + + + + + + + + Sequence("EnableTraceClk"); // Enable trace clock to enable TPIU register accesses + + + + + + __var SCS_Addr = 0xE000E000; + __var DHCSR_Addr = SCS_Addr + 0xDF0; + __var DEMCR_Addr = SCS_Addr + 0xDFC; + __var resetVector = 0xFFFFFFFF; // Reset Vector + + Write32(0xE000EDFC, Read32(DEMCR_Addr) & (~0x00000001)); // Clear Reset Vector Catch + + Write32(0x40034010, 0x00000000); // Program Flash Word Start Address to 0x0 to read reset vector (STARTA) + Write32(0x40034014, 0x00000000); // Program Flash Word Stop Address to 0x0 to read reset vector (STOPA) + Write32(0x40034080, 0x00000000); // DATAW0: Prepare for read + Write32(0x40034084, 0x00000000); // DATAW1: Prepare for read + Write32(0x40034088, 0x00000000); // DATAW2: Prepare for read + Write32(0x4003408C, 0x00000000); // DATAW3: Prepare for read + Write32(0x40034090, 0x00000000); // DATAW4: Prepare for read + Write32(0x40034094, 0x00000000); // DATAW5: Prepare for read + Write32(0x40034098, 0x00000000); // DATAW6: Prepare for read + Write32(0x4003409C, 0x00000000); // DATAW7: Prepare for read + + Write32(0x40034FE8, 0x0000000F); // Clear FLASH Controller Status (INT_CLR_STATUS) + Write32(0x40034000, 0x00000003); // Read single Flash Word (CMD_READ_SINGLE_WORD) + + + + + // Lowest flash page readable, read via AHB (flash controller for some reason returns garbage) + resetVector = Read32(0x00000004); // Read Reset Vector (Address 0x00000004) + + + + + + Write32(0xE0002008, resetVector|1); // Program FPB Comparator 0 with reset handler address + Write32(0xE0002000, 0x00000003); // Enable FPB + + + + + + Write32(DEMCR_Addr, (Read32(DEMCR_Addr) | 0x00000001)); // Enable Reset Vector Catch in DEMCR + + + + // Read DHCSR to clear potentially set DHCSR.S_RESET_ST bit + Read32(DHCSR_Addr); + + + + + __var DEMCR_Addr = 0xE000EDFC; + + // Clear FPB Comparators 0 and 1 + Write32(0xE0002008, 0x00000000); + + // Disable FPB + Write32(0xE0002000, 0x00000002); + + // Clear Reset Vector Catch + Write32(DEMCR_Addr, Read32(DEMCR_Addr) & (~0x00000001)); + + + + + __var SCS_Addr = 0xE000E000; + __var DHCSR_Addr = SCS_Addr + 0xDF0; + + // Give bootloader time to do what it needs to do + DAP_Delay(BootTime); // try 10ms + + Sequence("EnableDebugMailbox"); + + + + + + Write32(DHCSR_Addr, 0xA05F0003); // Force halt until finding a proper catch. Probably works better from flash. + + + + + + __var nReset = 0x80; + __var canReadPins = 0; + __var SCS_Addr = 0xE000E000; + __var DHCSR_Addr = SCS_Addr + 0xDF0; + + // De-assert nRESET line + canReadPins = (DAP_SWJ_Pins(0x00, nReset, 0) != 0xFFFFFFFF); + + + + + + + + + + // Assert nRESET line + DAP_SWJ_Pins(nReset, nReset, 0); + + + + + + + Sequence("WaitForStopAfterReset"); + + + + + + // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M. + __var SCS_Addr = 0xE000E000; + __var AIRCR_Addr = SCS_Addr + 0xD0C; + __var DHCSR_Addr = SCS_Addr + 0xDF0; + + __var ap0_disable=0x55aa; + + __errorcontrol = 1; + + // Execute SYSRESETREQ via AIRCR + Write32(AIRCR_Addr, 0x05FA0004); + + __errorcontrol = 0; + + // Give bootloader time to do what it needs to do + DAP_Delay(BootTime); // try 10ms + + // Read AP0 CSW + __dp = 0; + __ap = 0; + ap0_disable = ReadAP(0x0); + ap0_disable = ((ap0_disable & 0x40) == 0); + Message(0, "AP0 DIS: %x", ap0_disable); + + + + Sequence("WaitForStopAfterReset"); + + + + + + + + Sequence("EnableTraceClk"); // Enable and configure trace clock + + + + Write32(0x40001028, 0x00000046); // Configure PIO0_10: FUNC - 6, MODE - 0, SLEW - 1, INVERT - 0, DIGMODE - 0, OD - 0 + + + + + Write32(0x40001020, 0x00000044); // Configure PIO0_10: FUNC - 4, MODE - 0, SLEW - 1, INVERT - 0, DIGMODE - 0, OD - 0 + + + + + + + // Debug Access Variables, can be modified by user via copies of DBGCONF files as created by uVision. Also see sub-family level. + __var SWO_Pin = 0; // Serial Wire Output pin: 0 = PIO0_10, 1 = PIO0_8 + __var Dbg_CR = 0x00000000; // DBG_CR + __var BootTime = 10000; // 10 milliseconds + + Arm Cortex-M33-based Microcontroller Family + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test/data/packs/STM32F4xx_2048.FLM b/test/data/packs/STM32F4xx_2048.FLM new file mode 100755 index 000000000..8f0f56751 Binary files /dev/null and b/test/data/packs/STM32F4xx_2048.FLM differ diff --git a/test/data/packs/Test1.pdsc b/test/data/packs/Test1.pdsc new file mode 100644 index 000000000..1b02a1049 --- /dev/null +++ b/test/data/packs/Test1.pdsc @@ -0,0 +1,30 @@ + + + Generic + Pack + Test + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test/data/packs/Test2_algo_overlaps_alias.pdsc b/test/data/packs/Test2_algo_overlaps_alias.pdsc new file mode 100644 index 000000000..3a1ab4f1d --- /dev/null +++ b/test/data/packs/Test2_algo_overlaps_alias.pdsc @@ -0,0 +1,22 @@ + + + LPC55S36_DFP + NXP + Device Family Pack for LPC55S36 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + Licenses.txt + + + + Arm Cortex-M33-based Microcontroller Family + + + + + + + + + + + diff --git a/test/unit/test_debug_sequences.py b/test/unit/test_debug_sequences.py new file mode 100644 index 000000000..9446abd94 --- /dev/null +++ b/test/unit/test_debug_sequences.py @@ -0,0 +1,704 @@ +# pyOCD debugger +# Copyright (c) 2020 Arm Limited +# Copyright (c) 2021-2022 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from __future__ import annotations + +import logging +import pytest +from unittest import mock +from lark.lexer import Token as LarkToken +from lark.tree import Tree as LarkTree + +from pyocd.core import exceptions +from pyocd.debug.sequences.scope import Scope +from pyocd.debug.sequences.sequences import ( + DebugSequenceSemanticError, + DebugSequenceExecutionContext, + DebugSequence, + Block, + WhileControl, + IfControl, + Parser, + SemanticChecker, + _ConstantFolder, +) +from pyocd.core.session import Session +from pyocd.probe.debug_probe import DebugProbe + +# Substitute for SequenceFunctionDelegate for testing. +class SequenceFunctionsDelegateForTesting: + def valid_fn_no_args(self): + pass + + def valid_fn_1_arg(self, a: int): + pass + + def valid_fn_3_arg(self, a: int, b: int, c: int): + pass + + def valid_fn_varg(self, a: int, *vargs): + pass + + def fn_with_str_parm(self, foo: str): + pass + + def sequence(self, name: str): + pass + +class SequenceDelegateForTesting: + # This same root scope instance must be return from all .get_root_scope() calls since it is + # checked for by id in some tests. + _root = Scope(name="unit-test-root") + + @property + def sequences(self): + return set() + + @property + def cmsis_pack_device(self): + return mock.MagicMock() + + def get_root_scope(self, context) -> Scope: + self._root.set('rootvar', 42) + return self._root + + def has_sequence_with_name(self, name, pname=None): + return name == "valid" + + def get_sequence_with_name(self, name, pname=None): + print(f"SequenceDelegateForTesting.get_sequence_by_name: name={name} pname={pname}") + if name == "valid": + x = mock.Mock() + print(f"returning {x}") + return x + else: + return None + + def get_protocol(self): + return 2 + + def get_connection_type(self): + return 1 + + def get_traceout(self): + return 0 + + def get_sequence_functions(self) -> SequenceFunctionsDelegateForTesting: + return SequenceFunctionsDelegateForTesting() + + +class MockProbe: + def __init__(self): + self.wire_protocol = DebugProbe.Protocol.SWD + +@pytest.fixture(scope='function') +def session(): + s = Session(None) + setattr(s, '_probe', MockProbe()) + return s + +@pytest.fixture(scope='function') +def delegate(): + return SequenceDelegateForTesting() + +@pytest.fixture(scope='function') +def scope(): + s = Scope(name="fixture") + s.set("a", 0) + s.set("b", 128) + return s + +@pytest.fixture(scope='function') +def context(session, delegate): + c = DebugSequenceExecutionContext(session, delegate, pname=None) + return c + +@pytest.fixture(scope='function') +def block_context(context): + # Return a context set up to be able to run a Block. + # + # First create a sequence node with no children. Use the private _create_scope() method to get + # the new sequence scope with the delegate's root scope at parent. Then push the sequence node + # and scope onto the context stack. We can't just execute the sequence to do all that because + # it will pop the context before returning, leaving us without the proper context for running + # a block. + seq = DebugSequence('test_sequence') + scope = seq._create_scope(context) + # Must manually enter the push context manager. + ctxmgr = context._push(seq, scope) + return context + +class TestDebugSequenceScope: + def test_name(self): + s = Scope(name='test') + assert s.name == 'test' + + def test_get_1(self, scope): + assert scope.get('a') == 0 + assert scope.get('b') == 128 + assert len(scope) == 2 + + def test_get_invalid(self, scope): + with pytest.raises(KeyError): + scope.get('missing') + with pytest.raises(KeyError): + scope.get('') + + def test_set_1(self, scope): + scope.set('a', 10) + assert scope.get('a') == 10 + assert scope.get('b') == 128 + + def test_set_ro(self, scope): + scope.set('x', 32, readonly=True) + assert scope.is_read_only('x') + assert scope.get('x') == 32 + with pytest.raises(RuntimeError): + scope.set('x', 50) + + def test_freeze(self, scope): + scope.set('y', 16) + scope.freeze() + with pytest.raises(RuntimeError): + scope.set('a', 1) + assert len(scope) == 3 + assert scope.is_read_only('b') + + def test_parent_1(self, scope): + sub = Scope(parent=scope, name='subscope') + assert sub.parent is scope + assert sub.get('a') == 0 + assert sub.get('b') == 128 + assert sub.is_defined('b') + + def test_parent_2(self, scope): + sub = Scope(parent=scope, name='subscope') + sub.set('x', 1) + assert sub.parent is scope + assert sub.get('a') == 0 + assert sub.get('x') == 1 + assert sub.is_defined('b') + assert not scope.is_defined('x') + + def test_parent_3(self, scope): + sub = Scope(parent=scope, name='subscope') + sub.set('a', 1) + assert sub.parent is scope + assert sub.get('a') == 1 + assert scope.get('a') == 1 # Make sure it was set in parent scope. + assert sub.is_defined('a') + assert 'a' not in sub._variables + assert scope.is_defined('a') + + def test_parent_4(self, scope): + sub = Scope(parent=scope, name='subscope') + scope.set('y', 12, readonly=True) + with pytest.raises(RuntimeError): + sub.set('y', 1) + assert sub.get('y') == 12 + assert scope.get('y') == 12 + + def test_copy(self, scope): + other = Scope(name='other') + other.copy_variables(from_scope=scope, variables=['a', 'b']) + assert other.is_defined('a') \ + and other.is_defined('b') + assert other.get('a') == scope.get('a') + assert other.get('b') == scope.get('b') + + def test_copy_undefined(self, scope): + other = Scope(name='other') + other.copy_variables(from_scope=scope, variables=['a', 'missing']) + assert other.is_defined('a') \ + and not other.is_defined('b') \ + and not other.is_defined('missing') + assert other.get('a') == scope.get('a') + + +class TestDebugSequenceParser: + def test_semicolons(self): + # first with semicolon + ast = Parser().parse("12;") + print("ast=", ast) + assert ast.children[0].children[0] == 12 + + # now without semicolon + ast = Parser().parse("12") + print("ast=", ast) + assert ast.children[0].children[0] == 12 + + def test_fncall_no_args(self): + ast = Parser().parse("myfunc();") + print("ast=", ast) + fncall = ast.children[0].children[0] # start.expr_stmt... + assert fncall.data == 'fncall' + assert len(fncall.children) == 1 # IDENT only + assert fncall.children[0] == LarkToken('IDENT', 'myfunc') + + def test_fncall_3_arg(self): + ast = Parser().parse("myfunc(1, 2, 3);") + print("ast=", ast) + fncall = ast.children[0].children[0] # start.expr_stmt... + assert fncall.data == 'fncall' + assert len(fncall.children) == 4 # IDENT, arg1, arg2, arg3 + assert fncall.children[0] == LarkToken('IDENT', 'myfunc') + assert fncall.children[1] == 1 + assert fncall.children[2] == 2 + assert fncall.children[3] == 3 + + def test_bad_input(self): + with pytest.raises(exceptions.Error): + Parser().parse("bad input ••• wooo") + + def test_unary_op_assign(self): + # Statement from Infineon.PSoC6_DFP + ast = Parser().parse("__Result = -1; // DAP is unavailable") + print("ast=", ast) + + def test_assign_minus_negative(self): + ast = Parser().parse("a = 1 - -1;") + print("ast=", ast) + e = ast.children[0].children[2] # start.assign_stmt.binary_expr + assert e.children[0] == 1 + assert e.children[1] == LarkToken('MINUS', '-') + assert e.children[2].data == 'unary_expr' + assert e.children[2].children[0] == LarkToken('MINUS', '-') + assert e.children[2].children[1] == 1 + + def test_assign_minus_positive(self): + ast = Parser().parse("a = 1 - +1;") + print("ast=", ast) + e = ast.children[0].children[2] # start.assign_stmt.binary_expr + assert e.children[0] == 1 + assert e.children[1] == LarkToken('MINUS', '-') + assert e.children[2].data == 'unary_expr' + assert e.children[2].children[0] == LarkToken('PLUS', '+') + assert e.children[2].children[1] == 1 + +class TestDebugSequenceBlockExecute: + def test_semicolons(self, block_context): + block_context.current_scope.set("a", 0) + + # First with semicolon. + s = Block("a == 0;") + s.execute(block_context) + assert block_context.current_scope.get("a") == 0 + + # Now without semicolon. + s = Block("a == 0") + s.execute(block_context) + assert block_context.current_scope.get("a") == 0 + + def test_set_var(self, block_context): + s = Block("__var x = 100;") + s.execute(block_context) + assert block_context.current_scope.get("x") == 100 + + def test_var_no_expr(self, block_context): + s = Block("__var x;") + s.execute(block_context) + assert block_context.current_scope.get("x") == 0 + + def test_var_no_expr_separate_set(self, block_context): + s = Block("__var x; x = 123;") + s.execute(block_context) + assert block_context.current_scope.get("x") == 123 + + @pytest.mark.parametrize(("expr", "result"), [ + ("-1", 0xffffffffffffffff), + ("-2", 0xfffffffffffffffe), + ("!1", 0), + ("!0", 1), + ("+1", 1), + ("~0xffff", 0xffffffffffff0000), + ]) + def test_int_unary_ops(self, block_context, expr, result): + s = Block("__var x = %s;" % expr) + s.execute(block_context) + assert block_context.current_scope.get("x") == result + + @pytest.mark.parametrize(("expr", "result"), [ + ("1 + 1", 2), + ("2 - 1", 1), + ("2 * 4", 8), + ("4 / 2", 2), + ("5 % 4", 1), + ("1 << 12", 4096), + ("0x80 >> 4", 0x8), + ("0b1000 | 0x2", 0b1010), + ("0b1100 & 0b0100", 0b0100), + ]) + def test_int_expr(self, block_context, expr, result): + s = Block("__var x = %s;" % expr) + s.execute(block_context) + assert block_context.current_scope.get("x") == result + + @pytest.mark.parametrize(("expr", "result"), [ + ("1 == 1", 1), + ("1 == 0", 0), + ("0 == 1", 0), + ("1 != 1", 0), + ("1 != 0", 1), + ("0 != 1", 1), + ("20 > 10", 1), + ("20 > 20", 0), + ("20 > 100", 0), + ("5 >= 2", 1), + ("5 >= 5", 1), + ("5 >= 100", 0), + ("10 < 20", 1), + ("10 < 10", 0), + ("10 < 4", 0), + ("10 <= 20", 1), + ("10 <= 10", 1), + ("10 <= 5", 0), + ]) + def test_bool_cmp_expr(self, block_context, expr, result): + s = Block("__var x = %s;" % expr) + s.execute(block_context) + assert block_context.current_scope.get("x") == result + + # Aside from the obvious, verify that && and || are evaluated as in C rather than Python. + # That is, they must produce a 1 or 0 and not the value of either operand. + @pytest.mark.parametrize(("expr", "result"), [ + ("1 && 1", 1), + ("1 && 0", 0), + ("0 && 1", 0), + ("0 && 0", 0), + ("1 || 1", 1), + ("1 || 0", 1), + ("0 || 1", 1), + ("0 || 0", 0), + ("5 && 1000", 1), + ("432 && 0", 0), + ("0 && 2", 0), + ("0 && 0", 0), + ("348 || 4536", 1), + ("5 || 0", 1), + ("0 || 199", 1), + ("0 || 0", 0), + ]) + def test_bool_and_or_expr(self, block_context, expr, result): + s = Block("__var x = %s;" % expr) + s.execute(block_context) + assert block_context.current_scope.get("x") == result + + @pytest.mark.parametrize(("expr", "result"), [ + ("1 + 2 * 5", 11), + ("7 * 12 + 5", 89), + ("1 + 5 - 3", 3), + ("(1 + 2) * 5", 15), + ("1 + (2 * 5)", 11), + ("2 + 16 / 2", 10), + ("1 + 17 % 3", 3), + ("2 * 3 * 4", 24), + ("0 || 1 && 1", 1), + ("0 && 1 || 0", 0), + ("1 == 6 > 5", 1), + ("1 != 6 < 12", 0), + ("1 << 4 > 1 << 2", 1), + ("1 << (4 > 1) << 2", 8), + ("!1 == 0", 1), + ]) + def test_precedence(self, block_context, expr, result): + s = Block("__var x = %s;" % expr) + logging.info("Block: %s", s._ast.pretty()) + s.execute(block_context) + actual = block_context.current_scope.get("x") + assert actual == result + + @pytest.mark.parametrize(("expr", "result"), [ + ("(7 * (1 << 3) + 1) >> 1", 28), + ]) + def test_longer_expr(self, block_context, expr, result): + s = Block("__var x = %s;" % expr) + logging.info("Block: %s", s._ast.pretty()) + s.execute(block_context) + actual = block_context.current_scope.get("x") + assert actual == result + + def test_unary_op_assign(self, block_context): + # Statement from Infineon.PSoC6_DFP + s = Block("__Result = -1; // DAP is unavailable") + logging.info(f"Block: {s._ast.pretty()}") + s.execute(block_context) + actual = block_context.current_scope.get("__Result") + assert actual == 0xffffffffffffffff + + @pytest.mark.parametrize(("expr", "result"), [ + ("1 ? (1 + 1) : (1 - 1)", 2), + ("0 ? 10: 20", 20), + ("1 << 5 ? 17 * (2 + 1) : 0", 51), + ]) + def test_ternary_expr(self, block_context, expr, result): + s = Block(f"__var x = {expr};") + logging.info("Block: %s", s._ast.pretty()) + s.execute(block_context) + actual = block_context.current_scope.get("x") + assert actual == result + + @pytest.mark.parametrize(("expr", "result"), [ + ("x += 1", 2), + ("x -= 1", 0), + ("x *= 10", 10), + ("x /= 1", 1), + ("x %= 1", 0), + ("x &= 3", 1), + ("x |= 0x40", 0x41), + ("x ^= 3", 2), + ("x <<= 5", 1 << 5), + ("x >>= 0", 1), + ]) + def test_compound_assign(self, block_context, expr, result): + s = Block("__var x = 1; %s;" % expr) + s.execute(block_context) + assert block_context.current_scope.get("x") == result + +class TestConstantFolder: + def _get_folded_ast(self, expr): + ast = Parser.parse(expr) + logging.info("Unoptimized AST:\n%s", ast.pretty()) + ast_opt = _ConstantFolder().transform(ast) + logging.info("Optimized AST:\n%s", ast_opt.pretty()) + return ast_opt + + def _do_fold_test(self, expr, expected): + ast_opt = self._get_folded_ast(expr) + assert isinstance(ast_opt, LarkTree) + assert ast_opt.data == 'start' + assert ast_opt.children[0].data == 'expr_stmt' + assert ast_opt.children[0].children[0] == expected + + @pytest.mark.parametrize(("op", "expected"), [ + # return left + ("+", "x"), + ("-", "x"), + ("|", "x"), + ("^", "x"), + ("<<", "x"), + (">>", "x"), + ("||", "x"), + # return 0 + ("*", 0), + ("/", 0), + ("%", 0), + ("&", 0), + ("&&", 0), + ]) + def test_fold_left_0(self, op, expected): + self._do_fold_test(f"x {op} 0", expected) + + @pytest.mark.parametrize(("op", "expected"), [ + # return right + ("+", "x"), + ("-", "x"), + ("|", "x"), + ("^", "x"), + ("||", "x"), + # return 0 + ("*", 0), + ("/", 0), + ("%", 0), + ("&", 0), + ("<<", 0), + (">>", 0), + ("&&", 0), + ]) + def test_fold_right_0(self, op, expected): + self._do_fold_test(f"0 {op} x", expected) + + @pytest.mark.parametrize(("op", "expected"), [ + # return left + ("*", "x"), + ("/", "x"), + # return 1 + ("||", 1), + # return 0 + ("%", 0), + ]) + def test_fold_left_1(self, op, expected): + self._do_fold_test(f"x {op} 1", expected) + + # Really more of a parser test. + def test_unary_parens(self): + self._do_fold_test(f"! (1)", 0) + + # Really more of a parser test. + def test_unary_unfolded(self): + ast_opt = self._get_folded_ast("! x") + + assert isinstance(ast_opt, LarkTree) + assert ast_opt.data == 'start' + assert ast_opt.children[0].data == 'expr_stmt' + assert ast_opt.children[0].children[0].data == 'unary_expr' + + @pytest.mark.parametrize(("expr", "expected"), [ + ("-1", 0xffffffffffffffff), + ("-0", 0), + ]) + def test_unary_fold(self, expr, expected): + self._do_fold_test(expr, expected) + + @pytest.mark.parametrize(("expr", "expected"), [ + ("1 ? 10 : 20", 10), + ("0 ? 1 : 2", 2), + ("0 ? 1 : 2 + 2", 4), + ("1 + 1 ? 99 : 77", 99), + ]) + def test_ternary_fold(self, expr, expected): + self._do_fold_test(expr, expected) + +class TestSemanticChecker: + + @pytest.mark.parametrize("expr", [ + "funkymonkey();", # fncall: invalid function name + "valid_fn_1_arg(2134, x << 4);", # fncall: too many args + "valid_fn_1_arg(\"a-string\");", # fncall: string arg for int param + "valid_fn_3_arg(1, 2);", # fncall: too few args + "fn_with_str_parm(123);", # fncall: int arg for string param + "valid_fn_varg();", # vararg fn: too few args + '"just a string in this expr";', # expr consisting of only a string + "__var a = \"string value\";", # decl: attempt to assign string to variable + "b = \"string value\";", # assign: attempt to assign string to variable + "Sequence();", # fn-specific check: no args + "Sequence(1000);", # fn-specific check: int arg for str arg + ]) + def test_sem_checker_raises(self, expr, context, scope): + ast = Parser.parse(expr) + logging.info("ast:\n%s", ast.pretty()) + c = SemanticChecker(ast, scope, context) + with pytest.raises(DebugSequenceSemanticError): + c.check() + + @pytest.mark.parametrize("expr", [ + "valid_fn_no_args();", + "valid_fn_1_arg(2134);", + "valid_fn_3_arg(1, 2, 3);", + "fn_with_str_parm(\"bubblegum\");", # fncall: string arg for string param + "valid_fn_varg(a);", # vararg fn: exact number of positional args + "valid_fn_varg(123, x, q + 1, \"hi there\", 99);", # vararg fn: several var args + "__var a = 3 + x * 2;", # decl: valid assignment + "b = 3 + x * 2;", # assign: valid assignment + "Sequence(\"valid\");", # fn-specific check: valid call + ]) + def test_sem_checker_passes(self, expr, context, scope): + ast = Parser.parse(expr) + logging.info("ast:\n%s", ast.pretty()) + c = SemanticChecker(ast, scope, context) + c.check() + +class TestDebugSequences: + def test_pname(self): + seq = DebugSequence('test', pname="cm4") + assert seq.name == 'test' + assert seq.pname == 'cm4' + + assert DebugSequence('test').pname is None + + def test_info(self): + assert DebugSequence('test').info == '' + assert DebugSequence('test', info='hi there').info == 'hi there' + + def test_enable(self): + assert DebugSequence('test').is_enabled + assert not DebugSequence('test', is_enabled=False).is_enabled + + def test_scope_create(self, context): + seq = DebugSequence('test') + scope = seq._create_scope(context) + assert scope.parent is context.delegate.get_root_scope(context) + assert scope.get('__Result') == 0 + assert not scope.is_read_only('_Result') + assert scope.get('__dp') == 0 + assert not scope.is_read_only('__dp') + assert scope.get('__ap') == 0 + assert not scope.is_read_only('__ap') + assert scope.get('__apid') == 0 + assert not scope.is_read_only('__apid') + assert scope.get('__errorcontrol') == 0 + assert not scope.is_read_only('__errorcontrol') + assert scope.get('__protocol') == 2 + assert scope.is_read_only('__protocol') + assert scope.get('__connection') == 1 + assert scope.is_read_only('__connection') + assert scope.get('__traceout') == 0 + assert scope.is_read_only('__traceout') + assert scope.get('__FlashOp') == 0 + assert scope.is_read_only('__FlashOp') + assert scope.get('__FlashAddr') == 0 + assert scope.is_read_only('__FlashAddr') + assert scope.get('__FlashLen') == 0 + assert scope.is_read_only('__FlashLen') + assert scope.get('__FlashArg') == 0 + assert scope.is_read_only('__FlashArg') + + def test_scope_create_with_calling_seq(self, block_context): + # Modify some of the stacked scope's special vars. + super_scope = block_context.current_scope + super_scope.set('__dp', 1) + super_scope.set('__ap', 2) + super_scope.set('__apid', 3) + super_scope.set('__errorcontrol', 1) + super_scope.set('__Result', 333) + + # Create a sub-sequence. + seq = DebugSequence('test') + # _create_scope() will see the stacked sequence in the context. + scope = seq._create_scope(block_context) + + # Certain vars are propagated to subsequences. + assert scope.get('__dp') == 1 + assert scope.get('__ap') == 2 + assert scope.get('__apid') == 3 + assert scope.get('__errorcontrol') == 1 + # __Result should not have been propagated. + assert scope.get('__Result') == 0 + + # Modify the propagated variables. + scope.set('__dp', 2) + scope.set('__ap', 1) + scope.set('__apid', 5) + scope.set('__errorcontrol', 0) + scope.set('__Result', 555) + + # Verify the variables weren't set in the supersequences. + assert super_scope.get('__dp') == 1 + assert super_scope.get('__ap') == 2 + assert super_scope.get('__apid') == 3 + assert super_scope.get('__errorcontrol') == 1 + assert super_scope.get('__Result') == 333 + + def test_exec_block(self, context): + seq = DebugSequence('test') + seq.add_child(Block("__var x = 1 + 1;")) + seq.execute(context) + + def test_exec_if(self, context): + seq = DebugSequence('test') + seq.add_child(Block("__var x = 1;")) + seq.add_child(IfControl("x")) + seq.execute(context) + + def test_exec_while(self, context): + seq = DebugSequence('test') + seq.add_child(Block("__var x = 0;")) + w = WhileControl("x < 2") + w.add_child(Block("x += 1;")) + seq.add_child(w) + seq.execute(context) + + diff --git a/test/unit/test_memory_map.py b/test/unit/test_memory_map.py index 503c4b00b..eee044f31 100644 --- a/test/unit/test_memory_map.py +++ b/test/unit/test_memory_map.py @@ -120,6 +120,50 @@ def test_inplace_sort(self, ram1, ram2, flash, rom): regionList.sort() assert regionList == [flash, rom, ram1, ram2] + def test_split_addr_empty(self, flash): + assert list(flash.iter_split_by_address([])) == [MemoryRange(0, 1023)] + + def test_split_addr_1(self, flash): + assert list(flash.iter_split_by_address([500])) == [MemoryRange(0, 499), MemoryRange(500, 1023)] + + def test_split_addr_2(self, flash): + assert list(flash.iter_split_by_address([500, 900])) == \ + [MemoryRange(0, 499), MemoryRange(500, 899), MemoryRange(900, 1023)] + + def test_split_addr_2_start(self, flash): + assert list(flash.iter_split_by_address([0, 900])) == [MemoryRange(0, 899), MemoryRange(900, 1023)] + + def test_split_addr_2_end(self, flash): + assert list(flash.iter_split_by_address([700, 1023])) == \ + [MemoryRange(0, 699), MemoryRange(700, 1022), MemoryRange(1023, 1023)] + + def test_split_addr_1_out_of_bounds(self, flash): + assert list(flash.iter_split_by_address([722, 72742])) == \ + [MemoryRange(0, 721), MemoryRange(722, 1023)] + + def test_split_range(self, flash): + assert list(flash.iter_split_by_range(MemoryRange(500, 699))) == \ + [MemoryRange(0, 499), MemoryRange(500, 699), MemoryRange(700, 1023)] + + def test_split_range_out_of_bounds(self, flash): + assert list(flash.iter_split_by_range(MemoryRange(9000, length=10))) == [MemoryRange(0, 1023)] + + def test_split_range_start(self, flash): + assert list(flash.iter_split_by_range(MemoryRange(0, length=128))) == \ + [MemoryRange(0, 127), MemoryRange(128, 1023)] + + def test_split_range_start_overlap(self): + assert list(MemoryRange(1024, 2047).iter_split_by_range(MemoryRange(768, 1199))) == \ + [MemoryRange(1024, 1199), MemoryRange(1200, 2047)] + + def test_split_range_end(self, flash): + assert list(flash.iter_split_by_range(MemoryRange(768, 1023))) == \ + [MemoryRange(0, 767), MemoryRange(768, 1023)] + + def test_split_range_end_overlap(self): + assert list(MemoryRange(1024, 2047).iter_split_by_range(MemoryRange(2000, length=8000))) == \ + [MemoryRange(1024, 1999), MemoryRange(2000, 2047)] + class TestHash: def test_range_neq(self): a = MemoryRange(0, 0x1000) @@ -341,6 +385,8 @@ def test_eq(self, flash, ram1): b = RamRegion(name='a', start=0x1000, length=0x2000) assert a == b + def test_set_attr(self, flash): + flash.is_boot_memory = True # MemoryMap test cases. class TestMemoryMap: diff --git a/test/unit/test_pack.py b/test/unit/test_pack.py index 42fc9c0a2..d80525af6 100644 --- a/test/unit/test_pack.py +++ b/test/unit/test_pack.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2019-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,21 +20,30 @@ import zipfile from xml.etree import ElementTree from pathlib import Path +from unittest.mock import MagicMock from pyocd.target.pack import (cmsis_pack, flash_algo, pack_target) +from pyocd.target.pack.flm_region_builder import FlmFlashRegionBuilder from pyocd.target import TARGET -from pyocd.core import (memory_map, target) -from pyocd.utility.mask import align_up +from pyocd.core import memory_map +from pyocd.utility.mask import align_down +from pyocd.coresight.ap import APv1Address K64F = "MK64FN1M0VDC12" NRF5340 = "nRF5340_xxAA" STM32L4R5 = "STM32L4R5AGIx" +LPC55S36 = "LPC55S36JBD100" TEST_DATA_DIR = Path(__file__).resolve().parents[1] / "data" / "packs" K64F_PACK_PATH = TEST_DATA_DIR / "NXP.MK64F12_DFP.11.0.0.pack" K64F_1M0_FLM = "arm/MK_P1M0.FLM" +STM32F4_2M0_FLM = TEST_DATA_DIR / "STM32F4xx_2048.FLM" +NRF5340_APP_FLM = TEST_DATA_DIR / "nrf53xx_application.flm" NRF_PDSC_PATH = TEST_DATA_DIR / "NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0.pdsc" STM32L4_PDSC_PATH = TEST_DATA_DIR / "Keil.STM32L4xx_DFP.2.5.0.pdsc" +TEST1_PDSC_PATH = TEST_DATA_DIR / "Test1.pdsc" +TEST2_PDSC_PATH = TEST_DATA_DIR / "Test2_algo_overlaps_alias.pdsc" +LPC55S36_PDSC_PATH = TEST_DATA_DIR / "NXP.LPC55S36_DFP.13.0.0.pdsc" @pytest.fixture(scope='module') def pack_ref(): @@ -75,36 +84,73 @@ def k64algo(k64pack): flm = k64pack.get_file(K64F_1M0_FLM) return flash_algo.PackFlashAlgo(flm) +@pytest.fixture(scope='function') +def nrf5340appflm(): + return flash_algo.PackFlashAlgo(open(NRF5340_APP_FLM, 'rb')) + +@pytest.fixture(scope='function') +def stm32f42mflm(): + return flash_algo.PackFlashAlgo(open(STM32F4_2M0_FLM, 'rb')) + # Replacement for CmsisPackDevice._load_flash_algo() that loads the FLM from the test data dir # instead of the (unset) CmsisPack object. def load_test_flm(filename): p = TEST_DATA_DIR / Path(filename).name - return flash_algo.PackFlashAlgo(p.open('rb')) + return p.open('rb') @pytest.fixture(scope='function') def nrfpdsc(): - return cmsis_pack.CmsisPackDescription(None, NRF_PDSC_PATH) + return cmsis_pack.CmsisPackDescription(None, open(NRF_PDSC_PATH, 'rb')) # type:ignore + +@pytest.fixture(scope='function') +def test2pdsc(): + return cmsis_pack.CmsisPackDescription(None, open(TEST2_PDSC_PATH, 'rb')) # type:ignore + +@pytest.fixture(scope='function') +def test2dev(test2pdsc): + dev = test2pdsc.devices[0] + dev._get_pack_file_cb = load_test_flm + return dev + +@pytest.fixture(scope='function') +def test1pdsc(): + return cmsis_pack.CmsisPackDescription(None, TEST1_PDSC_PATH) + +@pytest.fixture(scope='function') +def test1dev(test1pdsc): + return test1pdsc.devices[0] # Fixture to provide nRF5340 CmsisPackDevice modified to load FLM from test data dir. @pytest.fixture(scope='function') -def nrf5340(monkeypatch, nrfpdsc): +def nrf5340(nrfpdsc): dev = [d for d in nrfpdsc.devices if d.part_number == NRF5340].pop() - monkeypatch.setattr(dev, '_load_flash_algo', load_test_flm) + dev._get_pack_file_cb = load_test_flm return dev @pytest.fixture(scope='function') def stm32l4pdsc(): - return cmsis_pack.CmsisPackDescription(None, STM32L4_PDSC_PATH) + return cmsis_pack.CmsisPackDescription(None, open(STM32L4_PDSC_PATH, 'rb')) # type:ignore # Fixture to provide STM32L4R5 CmsisPackDevice modified to load FLM from test data dir. @pytest.fixture(scope='function') -def stm32l4r5(monkeypatch, stm32l4pdsc): +def stm32l4r5(stm32l4pdsc): dev = [d for d in stm32l4pdsc.devices if d.part_number == STM32L4R5].pop() - monkeypatch.setattr(dev, '_load_flash_algo', load_test_flm) + dev._get_pack_file_cb = load_test_flm + return dev + +@pytest.fixture(scope='function') +def lpc55s36pdsc(): + return cmsis_pack.CmsisPackDescription(None, open(LPC55S36_PDSC_PATH, 'rb')) # type:ignore + +# Fixture to provide STM32L4R5 CmsisPackDevice modified to load FLM from test data dir. +@pytest.fixture(scope='function') +def lpc55s36(lpc55s36pdsc): + dev = [d for d in lpc55s36pdsc.devices if d.part_number == LPC55S36].pop() + dev._get_pack_file_cb = load_test_flm return dev # Tests for managed packs. Currently disabled as they fail on most systems. -class Disabled_TestPack(object): +class Disabled_TestPack: def test_get_installed(self, pack_ref): p = pack_target.ManagedPacks.get_installed_packs() assert p == [pack_ref] @@ -126,7 +172,7 @@ def test_k64_mem_map(self, k64dev): assert flash.start == 0 and flash.length == 0x100000 assert flash.sector_size == 0x1000 -class TestPack(object): +class TestPack: def test_devices(self, k64pack): devs = k64pack.devices pns = [x.part_number for x in devs] @@ -143,7 +189,6 @@ def test_zipfile(self): def test_parse_device_info(self, k64f1m0): assert k64f1m0.vendor == "NXP" assert k64f1m0.families == ["MK64F12"] - assert k64f1m0.default_reset_type == target.Target.ResetType.SW def test_get_svd(self, k64f1m0): svd = k64f1m0.svd @@ -158,14 +203,16 @@ def test_mem_map(self, k64f1m0): assert ram.start == 0x20000000 and ram.length == 0x30000 # Verify the flash region was converted correctly. + # Note that the sector size will be 0 because CmsisPackDevice just prepares the flash region + # for processing by FlmFlashRegionBuilder. def test_flash(self, k64f1m0): map = k64f1m0.memory_map flash = map.get_boot_memory() assert isinstance(flash, memory_map.FlashRegion) assert flash.start == 0 and flash.length == 1 * 1024 * 1024 - assert flash.sector_size == 4096 + # assert flash.sector_size == 4096 -class TestFLM(object): +class TestFLM: def test_algo(self, k64algo): i = k64algo.flash_info # print(i) @@ -179,32 +226,178 @@ def test_algo_dict_entry_points(self, k64algo): # Create the RAM region where we want the algo to be placed. ram = memory_map.RamRegion(0x20000000, length=0x10000) d = k64algo.get_pyocd_flash_algo(4096, ram) - assert d['load_address'] == ram.start - assert d['pc_init'] == ram.start + 0x5 - assert d['pc_unInit'] == ram.start + 0x55 - assert d['pc_eraseAll'] == ram.start + 0x79 - assert d['pc_erase_sector'] == ram.start + 0xaf - assert d['pc_program_page'] == ram.start + 0xc3 - - def test_algo_dict_full_mem(self, k64algo): + instr_len = len(d['instructions']) * 4 + load_addr = ram.end + 1 - instr_len + assert d['load_address'] == load_addr + assert d['pc_init'] == load_addr + 0x5 + assert d['pc_unInit'] == load_addr + 0x55 + assert d['pc_eraseAll'] == load_addr + 0x79 + assert d['pc_erase_sector'] == load_addr + 0xaf + assert d['pc_program_page'] == load_addr + 0xc3 + + def test_algo_dict_two_page_bufs(self, k64algo): # Create the RAM region where we want the algo to be placed. ram = memory_map.RamRegion(0x20000000, length=0x10000) d = k64algo.get_pyocd_flash_algo(k64algo.page_size, ram) - instr_len = len(d['instructions']) * 4 - buf_base = align_up(instr_len, 0x10) - buf1 = ram.start + buf_base - buf2 = buf1 + k64algo.page_size + instr_base = d['load_address'] + buf_top = align_down(instr_base, flash_algo.PackFlashAlgo._PAGE_BUFFER_ALIGN) + buf1 = buf_top - k64algo.page_size + buf2 = buf1 - k64algo.page_size assert d['page_buffers'] == [buf1, buf2] + def test_algo_dict_one_page_buf(self, k64algo): + # First get a full-sized algo allocation. + ram = memory_map.RamRegion(0x20000000, length=0x10000) + d = k64algo.get_pyocd_flash_algo(k64algo.page_size, ram) + + # Create a memory region with only enough memory for one page buf + stack. + min_ram_size = len(d['instructions']) * 4 + k64algo.page_size + k64algo.page_size // 2 + min_ram = memory_map.RamRegion(0x20000000, length=min_ram_size) + d = k64algo.get_pyocd_flash_algo(k64algo.page_size, min_ram) + + instr_base = d['load_address'] + assert instr_base == min_ram.end + 1 - len(d['instructions']) * 4 + buf_top = align_down(instr_base, flash_algo.PackFlashAlgo._PAGE_BUFFER_ALIGN) + buf1 = buf_top - k64algo.page_size + assert d['page_buffers'] == [buf1] + + # Flash Device: + # name=b'nRF53xxx_app' + # version=0x101 + # type=1 + # start=0x0 + # size=0x200000 + # page_size=0x1000 + # value_empty=0xff + # prog_timeout_ms=1000 + # erase_timeout_ms=3000 + # sectors: + # start=0x0, size=0x1000 + def test_iter_sector_sizes_single(self, nrf5340appflm): + sector_sizes = list(nrf5340appflm.iter_sector_size_ranges()) + assert sector_sizes == [ + (memory_map.MemoryRange(0x0000000, length=0x200000), 0x1000), + ] + + # Flash Device: + # name=b'STM32F4xx 2MB Flash' + # version=0x101 + # type=1 + # start=0x8000000 + # size=0x200000 + # page_size=0x400 + # value_empty=0xff + # prog_timeout_ms=100 + # erase_timeout_ms=6000 + # sectors: + # start=0x0, size=0x4000 + # start=0x10000, size=0x10000 + # start=0x20000, size=0x20000 + # start=0x100000, size=0x4000 + # start=0x110000, size=0x10000 + # start=0x120000, size=0x20000 + def test_iter_sector_sizes_multiple(self, stm32f42mflm): + sector_sizes = list(stm32f42mflm.iter_sector_size_ranges()) + assert sector_sizes == [ + (memory_map.MemoryRange(0x8000000, length=0x10000), 0x4000), + (memory_map.MemoryRange(0x8010000, length=0x10000), 0x10000), + (memory_map.MemoryRange(0x8020000, length=(0x100000 - 0x20000)), 0x20000), + (memory_map.MemoryRange(0x8100000, length=0x10000), 0x4000), + (memory_map.MemoryRange(0x8110000, length=0x10000), 0x10000), + (memory_map.MemoryRange(0x8120000, length=(0x100000 - 0x20000)), 0x20000), + ] + +class TestFlmRegionBuilder: + @pytest.fixture(scope='module') + def builder(self): + mock_target = MagicMock() + mock_target.part_number = "TestPartNumber" + ram = memory_map.RamRegion(0x20000000, length=0x10000, is_default=True) + ram2 = memory_map.RamRegion(0x30010000, length=0x10000, is_default=False) + memmap = memory_map.MemoryMap(ram, ram2) + builder = FlmFlashRegionBuilder(mock_target, memmap) + return builder + + def test_single_sector_size(self, builder: FlmFlashRegionBuilder, nrf5340appflm): + flash = memory_map.FlashRegion(0, length=0x200000, flm=nrf5340appflm) + assert builder.finalise_region(flash) + assert not flash.has_subregions + assert flash.sector_size == 0x1000 + + def test_multiple_sector_size(self, builder: FlmFlashRegionBuilder, stm32f42mflm): + flash = memory_map.FlashRegion(0x08000000, length=0x200000, flm=stm32f42mflm) + assert builder.finalise_region(flash) + assert flash.has_subregions + submap = flash.submap + assert submap.region_count == 6 + assert submap[0].sector_size == 0x4000 + assert submap[1].sector_size == 0x10000 + assert submap[2].sector_size == 0x20000 + assert submap[3].sector_size == 0x4000 + assert submap[4].sector_size == 0x10000 + assert submap[5].sector_size == 0x20000 + + def test_ram_select_default(self, builder: FlmFlashRegionBuilder, nrf5340appflm): + flash = memory_map.FlashRegion(0, length=0x200000, flm=nrf5340appflm) + builder.finalise_region(flash) + assert flash.algo + instr_len = len(flash.algo['instructions']) * 4 + assert flash.algo['load_address'] == (0x20010000 - instr_len) + assert not flash.has_subregions + assert flash.algo + + def test_ram_select_explicit(self, builder: FlmFlashRegionBuilder, nrf5340appflm): + flash = memory_map.FlashRegion(0, length=0x200000, flm=nrf5340appflm, + _RAMstart=0x30010000, _RAMsize=0x4000) + assert builder.finalise_region(flash) + assert flash.algo + instr_len = len(flash.algo['instructions']) * 4 + assert flash.algo['load_address'] == (0x30014000 - instr_len) + assert not flash.has_subregions + assert flash.algo + def has_overlapping_regions(memmap): return any((len(memmap.get_intersecting_regions(r.start, r.end)) > 1) for r in memmap.regions) -class TestNRF(): +class TestNRF: def test_regions(self, nrf5340): memmap = nrf5340.memory_map assert not has_overlapping_regions(memmap) -class TestSTM32L4(): +class TestSTM32L4: def test_regions(self, stm32l4r5): memmap = stm32l4r5.memory_map assert not has_overlapping_regions(memmap) + +class TestLPC55S36: + def test_regions(self, lpc55s36): + import pprint + memmap = lpc55s36.memory_map + print("memory map:") + pprint.pprint(memmap.regions) + assert not has_overlapping_regions(memmap) + +class TestAlgoOverlappingAliasRegion: + def test_regions(self, test2dev): + import pprint + memmap = test2dev.memory_map + print("memory map:") + pprint.pprint(memmap.regions) + assert not has_overlapping_regions(memmap) + # assert False + +class TestAPID: + def test1_dp(self, test1dev): + assert test1dev.valid_dps == [0] + + def test1_procs(self, test1dev): + procs = test1dev.processors_map + m4 = procs['CM4'] + assert m4.name == 'CM4' + assert m4.ap_address == APv1Address(0) + assert m4.svd_path == "cm4.svd" + m0p = procs['CM0p'] + assert m0p.name == 'CM0p' + assert m0p.ap_address == APv1Address(2) + assert m0p.svd_path == "cm0p.svd" + diff --git a/test/unit/test_semihosting.py b/test/unit/test_semihosting.py index eb2a0b798..981b133ba 100644 --- a/test/unit/test_semihosting.py +++ b/test/unit/test_semihosting.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2006-2020 Arm Limited -# Copyright (c) 2022 Chris Reed +# Copyright (c) 2022-2023 Chris Reed # Copyright (c) 2023 Hardy Griech # SPDX-License-Identifier: Apache-2.0 # @@ -16,10 +16,11 @@ # See the License for the specific language governing permissions and # limitations under the License. +from pathlib import Path import pytest import os import logging -import telnetlib +# import telnetlib import six from pyocd.core.helpers import ConnectHelper @@ -112,17 +113,21 @@ def get_output_data(self, fd): return None def write(self, fd, ptr, length): + assert self.agent if fd not in self._out_data: self._out_data[fd] = b'' + assert self.agent s = self.agent.get_data(ptr, length) self._out_data[fd] += s return 0 def read(self, fd, ptr, length): + assert self.agent if fd not in self._in_data: return length d = self._in_data[fd][:length] self._in_data[fd] = self._in_data[fd][length:] + assert self.agent self.agent.context.write_memory_block8(ptr, bytearray(six.ensure_binary(d))) return length - len(d) @@ -162,7 +167,7 @@ def setup_semihost_request(self, rqnum): return self.ramrgn.start + 0x200 def do_open(self, filename, mode): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_OPEN) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_OPEN) # Write filename filename = bytearray(six.ensure_binary(filename) + b'\x00') @@ -179,7 +184,7 @@ def do_open(self, filename, mode): return result def do_close(self, fd): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_CLOSE) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_CLOSE) self.ctx.write32(argsptr, fd) was_semihost = run_til_halt(self.tgt, self.semihostagent) @@ -189,7 +194,7 @@ def do_close(self, fd): return result def do_write(self, fd, data): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_WRITE) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_WRITE) # Write data data = six.ensure_binary(data) @@ -207,7 +212,7 @@ def do_write(self, fd, data): return result def do_writec(self, c): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_WRITEC) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_WRITEC) self.ctx.write8(argsptr, ord(c)) was_semihost = run_til_halt(self.tgt, self.semihostagent) @@ -217,7 +222,7 @@ def do_writec(self, c): return result def do_write0(self, data): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_WRITE0) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_WRITE0) data = data + b'\x00' self.ctx.write_memory_block8(argsptr, data) @@ -229,7 +234,7 @@ def do_write0(self, data): return result def do_read(self, fd, length): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_READ) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_READ) # Clear read buffer. self.ctx.write_memory_block8(argsptr + 12, bytearray(b'\x00') * length) @@ -250,7 +255,7 @@ def do_read(self, fd, length): return result, data def do_seek(self, fd, pos): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_SEEK) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_SEEK) self.ctx.write32(argsptr, fd) # fd self.ctx.write32(argsptr + 4, pos) # pos @@ -264,7 +269,7 @@ def do_seek(self, fd, pos): return result def do_flen(self, fd): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_FLEN) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_FLEN) self.ctx.write32(argsptr, fd) # fd self.ctx.flush() @@ -277,7 +282,7 @@ def do_flen(self, fd): return result def do_istty(self, fd): - argsptr = self.setup_semihost_request(semihost.TARGET_SYS_ISTTY) + argsptr = self.setup_semihost_request(semihost.SemihostingRequests.SYS_ISTTY) self.ctx.write32(argsptr, fd) # fd self.ctx.flush() @@ -331,6 +336,28 @@ def test_open_stdio(self, semihost_builder): fd = semihost_builder.do_open(":tt", 'a') # stderr assert fd == 2 + def test_open_home_file(self, semihost_builder, request): + testfilepath = Path("~/testfile").expanduser() + + def delete_it(): + try: + testfilepath.unlink() + except OSError: + pass + request.addfinalizer(delete_it) + + fd = semihost_builder.do_open("~/testfile", 'wb') + assert fd > 2 + + result = semihost_builder.do_write(fd, b"foo") + assert result == 0 + + result = semihost_builder.do_close(fd) + assert result == 0 + + data = testfilepath.read_bytes() + assert data == b"foo" + def test_open_close_file(self, semihost_builder, delete_testfile): fd = semihost_builder.do_open("testfile", 'w+b') assert fd > 2 @@ -444,28 +471,28 @@ def test_console_readc(self, semihost_builder): console.set_input_data(semihost.STDIN_FD, 'x') - result = semihost_builder.do_no_args_call(semihost.TARGET_SYS_READC) + result = semihost_builder.do_no_args_call(semihost.SemihostingRequests.SYS_READC) assert chr(result) == 'x' def test_clock(self, semihost_builder): - result = semihost_builder.do_no_args_call(semihost.TARGET_SYS_CLOCK) + result = semihost_builder.do_no_args_call(semihost.SemihostingRequests.SYS_CLOCK) assert result != -1 assert result != 0 logging.info("clock = %d cs", result) - result2 = semihost_builder.do_no_args_call(semihost.TARGET_SYS_CLOCK) + result2 = semihost_builder.do_no_args_call(semihost.SemihostingRequests.SYS_CLOCK) assert result2 != -1 assert result2 != 0 assert result2 > result logging.info("clock = %d cs", result2) def test_time(self, semihost_builder): - result = semihost_builder.do_no_args_call(semihost.TARGET_SYS_TIME) + result = semihost_builder.do_no_args_call(semihost.SemihostingRequests.SYS_TIME) assert result != 0 logging.info("time = %d sec", result) def test_errno_no_err(self, semihost_builder): - result = semihost_builder.do_no_args_call(semihost.TARGET_SYS_ERRNO) + result = semihost_builder.do_no_args_call(semihost.SemihostingRequests.SYS_ERRNO) assert result == 0 @pytest.mark.parametrize(("fd"), [ @@ -487,6 +514,47 @@ def test_istty_non_stdio(self, semihost_builder, delete_testfile): result = semihost_builder.do_close(fd) assert result == 0 + def test_feature_bits(self, semihost_builder): + fd = semihost_builder.do_open(":semihosting-features", 'rb') + assert fd > 2 + + # Required requests: SYS_FLEN, SYS_ISTTY, SYS_SEEK, SYS_READ, SYS_CLOSE + + n = semihost_builder.do_flen(fd) + assert n >= 5 # 4 magic bytes + at least 1 feature flags byte + + result = semihost_builder.do_istty(fd) + assert result == 0 + + result = semihost_builder.do_seek(fd, 0) + assert result == 0 + + # Verify header + result, data = semihost_builder.do_read(fd, 4) + assert result == 0 + assert data == b'SHFB' + + result = semihost_builder.do_seek(fd, 4) + assert result == 0 + + # Verify first feature byte. + result, data = semihost_builder.do_read(fd, 1) + assert result == 0 + assert (data[0] & 0x3) == 0x02 # Only check feature bits defined at the time this test was written. + + # Seek back to earlier. + result = semihost_builder.do_seek(fd, 2) + assert result == 0 + + result, data = semihost_builder.do_read(fd, 2) + assert result == 0 + assert data == b'FB' + + # Close. + result = semihost_builder.do_close(fd) + assert result == 0 + + @pytest.fixture(scope='function') def telnet_server(request): telnet_server = StreamServer( @@ -514,61 +582,64 @@ def cleanup(): def semihost_telnet_builder(tgt, semihost_telnet_agent, ramrgn): return SemihostRequestBuilder(tgt, semihost_telnet_agent, ramrgn) -@pytest.fixture(scope='function') -def telnet_conn(request, telnet_server): - from time import sleep - # Sleep for a bit to ensure the semihost telnet server has started up in its own thread. - while not telnet_server.is_running: - sleep(0.005) - telnet = telnetlib.Telnet('localhost', telnet_server.port, 10.0) - def cleanup(): - telnet.close() - request.addfinalizer(cleanup) - return telnet - -class TestSemihostingTelnet: - def test_connect(self, semihost_telnet_builder, telnet_conn): - result = semihost_telnet_builder.do_no_args_call(semihost.TARGET_SYS_ERRNO) - assert result == 0 - - def test_write(self, semihost_telnet_builder, telnet_conn): - result = semihost_telnet_builder.do_write(semihost.STDOUT_FD, b'hello world') - assert result == 0 - - index, _, text = telnet_conn.expect([b'hello world']) - assert index != -1 - assert text == b'hello world' - - def test_writec(self, semihost_telnet_builder, telnet_conn): - for c in (bytes([i]) for i in b'xyzzy'): - result = semihost_telnet_builder.do_writec(c) - assert result == 0 - - index, _, text = telnet_conn.expect([c]) - assert index != -1 - assert text == c - - def test_write0(self, semihost_telnet_builder, telnet_conn): - result = semihost_telnet_builder.do_write0(b'hello world') - assert result == 0 - - index, _, text = telnet_conn.expect([b'hello world']) - assert index != -1 - assert text == b'hello world' - - def test_read(self, semihost_telnet_builder, telnet_conn): - telnet_conn.write(b'hello world') - - result, data = semihost_telnet_builder.do_read(semihost.STDIN_FD, 11) - assert result == 0 - assert data == b'hello world' - - def test_readc(self, semihost_telnet_builder, telnet_conn): - telnet_conn.write(b'xyz') - - for c in 'xyz': - rc = semihost_telnet_builder.do_no_args_call(semihost.TARGET_SYS_READC) - assert chr(rc) == c +# Telnet based tests are commented out for the time being, until they can be rewritten +# to not use the telnetlib package that is now deprecated and will be removed in Python 3.13. + +# @pytest.fixture(scope='function') +# def telnet_conn(request, telnet_server): +# from time import sleep +# # Sleep for a bit to ensure the semihost telnet server has started up in its own thread. +# while not telnet_server.is_running: +# sleep(0.005) +# telnet = telnetlib.Telnet('localhost', telnet_server.port, 10.0) +# def cleanup(): +# telnet.close() +# request.addfinalizer(cleanup) +# return telnet + +# class TestSemihostingTelnet: +# def test_connect(self, semihost_telnet_builder, telnet_conn): +# result = semihost_telnet_builder.do_no_args_call(semihost.SemihostingRequests.TARGET_SYS_ERRNO) +# assert result == 0 + +# def test_write(self, semihost_telnet_builder, telnet_conn): +# result = semihost_telnet_builder.do_write(semihost.STDOUT_FD, b'hello world') +# assert result == 0 + +# index, _, text = telnet_conn.expect([b'hello world']) +# assert index != -1 +# assert text == b'hello world' + +# def test_writec(self, semihost_telnet_builder, telnet_conn): +# for c in (bytes([i]) for i in b'xyzzy'): +# result = semihost_telnet_builder.do_writec(c) +# assert result == 0 + +# index, _, text = telnet_conn.expect([c]) +# assert index != -1 +# assert text == c + +# def test_write0(self, semihost_telnet_builder, telnet_conn): +# result = semihost_telnet_builder.do_write0(b'hello world') +# assert result == 0 + +# index, _, text = telnet_conn.expect([b'hello world']) +# assert index != -1 +# assert text == b'hello world' + +# def test_read(self, semihost_telnet_builder, telnet_conn): +# telnet_conn.write(b'hello world') + +# result, data = semihost_telnet_builder.do_read(semihost.STDIN_FD, 11) +# assert result == 0 +# assert data == b'hello world' + +# def test_readc(self, semihost_telnet_builder, telnet_conn): +# telnet_conn.write(b'xyz') + +# for c in 'xyz': +# rc = semihost_telnet_builder.do_no_args_call(semihost.SemihostingRequests.TARGET_SYS_READC) +# assert chr(rc) == c class TestSemihostAgent: def test_no_io_handler(self, ctx): diff --git a/test/unit/test_svd.py b/test/unit/test_svd.py new file mode 100644 index 000000000..e40723d5d --- /dev/null +++ b/test/unit/test_svd.py @@ -0,0 +1,34 @@ +# pyOCD debugger +# Copyright (c) 2023 Chris Reed +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from pyocd.debug.svd.loader import ( + SVDFile, + SVDLoader, +) + +class TestIntervalSvdAccess: + def builtin_svd(self, name: str) -> SVDLoader: + def completion(dev): + pass + loader = SVDLoader(SVDFile.from_builtin(name), completion) + loader.run() + return loader + + def test_load(self): + loader = self.builtin_svd('Musca_B1.svd') + assert loader.device + assert [p for p in loader.device.peripherals if p.name == 'UART0'] + diff --git a/udev/49-wch-link.rules b/udev/49-wch-link.rules new file mode 100644 index 000000000..af5143bf3 --- /dev/null +++ b/udev/49-wch-link.rules @@ -0,0 +1,19 @@ +# # WCH-Link +# SUBSYSTEMS=="usb", ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="8011", \ +# MODE:="0666", \ +# SYMLINK+="wch-link_%n" +# +# # WCH-Link clone +# SUBSYSTEMS=="usb", ATTRS{idVendor}=="2a86", ATTRS{idProduct}=="8011", \ +# MODE:="0666", \ +# SYMLINK+="wch-link_%n" + +# Try to cover all the cases +SUBSYSTEMS=="usb", ATTRS{product}=="WCH-Link", \ + MODE:="0666", \ + SYMLINK+="wch-link_%n" + +# If you share your linux system with other users, or just don't like the +# idea of write permission for everybody, you can replace MODE:="0666" with +# OWNER:="yourusername" to create the device owned by you, or with +# GROUP:="somegroupname" and mange access using standard unix groups.