From 2ddc501456544871f54d8037949993c52d7d854d Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Mon, 1 Jan 2024 16:27:30 +0100 Subject: [PATCH 1/2] coresight: target: allow algos to run on secondary cores Signed-off-by: Maximilian Deubel --- pyocd/core/memory_map.py | 1 + pyocd/coresight/coresight_target.py | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/pyocd/core/memory_map.py b/pyocd/core/memory_map.py index d42d54c85..e79e6228c 100644 --- a/pyocd/core/memory_map.py +++ b/pyocd/core/memory_map.py @@ -474,6 +474,7 @@ class FlashRegion(MemoryRegion): 'erased_byte_value': 0xff, 'access': 'rx', # By default flash is not writable. 'are_erased_sectors_readable': True, + 'core_index': 0, # Core to be used to access this region }) _algo: Optional[Dict[str, Any]] diff --git a/pyocd/coresight/coresight_target.py b/pyocd/coresight/coresight_target.py index 49887d6f9..1c0e8d8b0 100644 --- a/pyocd/coresight/coresight_target.py +++ b/pyocd/coresight/coresight_target.py @@ -286,12 +286,12 @@ def create_flash(self) -> None: argspec = getfullargspec(klass.__init__) if 'flash_algo' in argspec.args: if region.algo is not None: - obj = klass(self, region.algo) + obj = klass(self._cores[region.core_index], region.algo) else: LOG.warning("flash region '%s' has no flash algo" % region.name) continue else: - obj = klass(self) # type:ignore + obj = klass(self._cores[region.core_index]) # type:ignore # Set the region in the flash instance. obj.region = region From ae384abb7efcddf30484da92374d92c319f66735 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Mon, 1 Jan 2024 16:27:39 +0100 Subject: [PATCH 2/2] target: add nrf5340 support Signed-off-by: Maximilian Deubel --- docs/builtin-targets.md | 5 + pyocd/debug/svd/data/nrf5340_application.svd | 59296 +++++++++++++++++ pyocd/target/builtin/__init__.py | 2 + pyocd/target/builtin/target_nRF5340_xxAA.py | 444 + pyocd/target/family/__init__.py | 2 + pyocd/target/family/target_nRF53.py | 850 + 6 files changed, 60599 insertions(+) create mode 100644 pyocd/debug/svd/data/nrf5340_application.svd create mode 100644 pyocd/target/builtin/target_nRF5340_xxAA.py create mode 100644 pyocd/target/family/target_nRF53.py diff --git a/docs/builtin-targets.md b/docs/builtin-targets.md index c18ce7dad..cf08e5ff6 100644 --- a/docs/builtin-targets.md +++ b/docs/builtin-targets.md @@ -666,6 +666,11 @@ title: Built-in targets NRF52840 + nrf53 + Nordic Semiconductor + NRF5340 + + nrf91 Nordic Semiconductor NRF9160 diff --git a/pyocd/debug/svd/data/nrf5340_application.svd b/pyocd/debug/svd/data/nrf5340_application.svd new file mode 100644 index 000000000..ca9272e6b --- /dev/null +++ b/pyocd/debug/svd/data/nrf5340_application.svd @@ -0,0 +1,59296 @@ + + + + Nordic Semiconductor + Nordic + nrf5340_application + nrf53 + 1 + nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers + +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 69 + 0 + + system_nrf53 + NRF_ + + 240 + + + + CACHEDATA_S + CACHEDATA + 0x00F00000 + CACHEDATA + + + + 0 + 0x1000 + registers + + CACHEDATA + 0x20 + + + 256 + 0x020 + SET[%s] + Unspecified + CACHEDATA_SET + read-write + 0x0 + + 2 + 0x010 + WAY[%s] + Unspecified + CACHEDATA_SET_WAY + read-write + 0x0 + + DATA0 + Description cluster: Cache data bits [31:0] of SET[n], WAY[o]. + 0x0 + read-write + + + Data + Data + 0 + 31 + + + + + DATA1 + Description cluster: Cache data bits [63:32] of SET[n], WAY[o]. + 0x4 + read-write + + + Data + Data + 0 + 31 + + + + + DATA2 + Description cluster: Cache data bits [95:64] of SET[n], WAY[o]. + 0x8 + read-write + + + Data + Data + 0 + 31 + + + + + DATA3 + Description cluster: Cache data bits [127:96] of SET[n], WAY[o]. + 0xC + read-write + + + Data + Data + 0 + 31 + + + + + + + + + CACHEINFO_S + CACHEINFO + 0x00F08000 + CACHEINFO + + + + 0 + 0x1000 + registers + + CACHEINFO + 0x20 + + + 256 + 0x008 + SET[%s] + Unspecified + CACHEINFO_SET + read-write + 0x0 + + 0x2 + 0x4 + WAY[%s] + Description collection: Cache information for SET[n], WAY[o]. + 0x0 + read-write + + + TAG + Cache tag. + 0 + 16 + + + V + Valid bit + 30 + 30 + read-only + + + Invalid + Invalid cache line + 0 + + + Valid + Valid cache line + 1 + + + + + MRU + Most recently used way. + 31 + 31 + read-only + + + Way0 + Way0 was most recently used + 0 + + + Way1 + Way1 was most recently used + 1 + + + + + + + + + + FICR_S + Factory Information Configuration Registers + 0x00FF0000 + FICR + + + + 0 + 0x1000 + registers + + FICR + 0x20 + + + INFO + Device info + FICR_INFO + read-write + 0x200 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + + + HWID + Identification number for the HW + 0 + 15 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + PART + Part code + 0x00C + read-only + 0x00005340 + + + PART + Part code + 0 + 31 + + + N5340 + nRF5340 + 0x5340 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x010 + read-only + 0xFFFFFFFF + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + QKAA + QKAA + 0x514B4141 + + + CLAA + CLAA + 0x434C4141 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x014 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QK + QKxx - 94-pin aQFN + 0x2000 + + + CL + CLxx - WLCSP + 0x2005 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x018 + read-only + 0xFFFFFFFF + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + K128 + 128 kByte RAM + 0x80 + + + K256 + 256 kByte RAM + 0x100 + + + K512 + 512 kByte RAM + 0x200 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x01C + read-only + 0xFFFFFFFF + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + K1024 + 1 MByte FLASH + 0x400 + + + K2048 + 2 MByte FLASH + 0x800 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODEPAGESIZE + Code memory page size in bytes + 0x020 + read-only + 0x00001000 + + + CODEPAGESIZE + Code memory page size in bytes + 0 + 31 + + + K4096 + 4 kByte + 0x1000 + + + + + + + CODESIZE + Code memory size + 0x024 + read-only + 0x00000100 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + P256 + 256 pages + 256 + + + + + + + DEVICETYPE + Device type + 0x028 + read-only + 0x00000000 + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x0000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + 32 + 0x008 + TRIMCNF[%s] + Unspecified + FICR_TRIMCNF + read-write + 0x300 + + ADDR + Description cluster: Address of the PAR register which will be written + 0x000 + read-only + 0xFFFFFFFF + uint32_t * + + + Address + Address + 0 + 31 + + + + + DATA + Description cluster: Data + 0x004 + read-only + 0xFFFFFFFF + + + Data + Data to be written into the PAR register + 0 + 31 + + + + + + NFC + Unspecified + FICR_NFC + read-write + 0x450 + + TAGHEADER0 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + TRNG90B + NIST800-90B RNG calibration data + FICR_TRNG90B + read-write + 0xC00 + + BYTES + Amount of bytes for the required entropy bits + 0x000 + read-only + 0x00000210 + + + BYTES + Amount of bytes for the required entropy bits + 0 + 31 + + + + + RCCUTOFF + Repetition counter cutoff + 0x004 + read-only + 0xFFFFFFFF + + + RCCUTOFF + Repetition counter cutoff + 0 + 31 + + + + + APCUTOFF + Adaptive proportion cutoff + 0x008 + read-only + 0xFFFFFFFF + + + APCUTOFF + Adaptive proportion cutoff + 0 + 31 + + + + + STARTUP + Amount of bytes for the startup tests + 0x00C + read-only + 0xFFFFFFFF + + + STARTUP + Amount of bytes for the startup tests + 0 + 31 + + + + + ROSC1 + Sample count for ring oscillator 1 + 0x010 + read-only + 0xFFFFFFFF + + + ROSC1 + Sample count for ring oscillator 1 + 0 + 31 + + + + + ROSC2 + Sample count for ring oscillator 2 + 0x014 + read-only + 0xFFFFFFFF + + + ROSC2 + Sample count for ring oscillator 2 + 0 + 31 + + + + + ROSC3 + Sample count for ring oscillator 3 + 0x018 + read-only + 0xFFFFFFFF + + + ROSC3 + Sample count for ring oscillator 3 + 0 + 31 + + + + + ROSC4 + Sample count for ring oscillator 4 + 0x01C + read-only + 0xFFFFFFFF + + + ROSC4 + Sample count for ring oscillator 4 + 0 + 31 + + + + + + XOSC32MTRIM + XOSC32M capacitor selection trim values + 0xC20 + read-only + 0xFFFFFFFF + + + SLOPE + Slope trim factor on twos complement form + 0 + 4 + + + OFFSET + Offset trim factor on integer form + 5 + 9 + + + + + + + UICR_S + User Information Configuration Registers User information configuration registers + 0x00FF8000 + UICR + + + + 0 + 0x1000 + registers + + UICR + 0x20 + + + APPROTECT + Access port protection + 0x000 + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all CPU registers and + memory mapped addresses. + 0 + 31 + + + Unprotected + Unprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + VREGHVOUT + Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. + 0x010 + read-write + 0xFFFFFFFF + + + VREGHVOUT + VREGH regulator output voltage. + 0 + 2 + + + 1V8 + 1.8 V + 0 + + + 2V1 + 2.1 V + 1 + + + 2V4 + 2.4 V + 2 + + + 2V7 + 2.7 V + 3 + + + 3V0 + 3.0 V + 4 + + + 3V3 + 3.3 V + 5 + + + DEFAULT + Default voltage: 1.8 V + 7 + + + + + + + HFXOCNT + HFXO startup counter + 0x014 + read-write + 0xFFFFFFFF + + + HFXOCNT + HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us + 0 + 7 + + + MinDebounceTime + Min debounce time = (0*64 us + 0.5 us) + 0 + + + MaxDebounceTime + Max debounce time = (254*64 us + 0.5 us) + 254 + + + DefaultDebounceTime + Default debounce time for erased UICR = 4*64 us + 0.5 us + 255 + + + + + + + SECUREAPPROTECT + Secure access port protection + 0x01C + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all secure CPU registers and secure memory + mapped addresses. + 0 + 31 + + + Unprotected + Unprotected + 0x50FA50FA + + + Protected + Protected + 0x00000000 + + + + + + + ERASEPROTECT + Erase protection + 0x020 + read-write + 0x00000000 + + + PALL + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + TINSTANCE + SW-DP Target instance + 0x024 + read-write + 0xFFFFFFFF + + + TINSTANCE + TINSTANCE bits are negated and used in the SW-DP DLPIDR.TINSTANCE field. E.g. 0xF in this field is translated to 0x0 in DLPIDR.TINSTANCE field. + 28 + 31 + + + + + NFCPINS + Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + 0x028 + read-write + 0xFFFFFFFF + + + PROTECT + Setting of pins dedicated to NFC functionality + 0 + 0 + + + Disabled + Operation as GPIO pins. Same protection as normal GPIO pins + 0 + + + NFC + Operation as NFC antenna pins. Configures the protection for NFC operation + 1 + + + + + + + 0xC0 + 0x4 + OTP[%s] + Description collection: One time programmable memory + 0x100 + read-write + 0xFFFFFFFF + + + LOWER + Lower half word + 0 + 15 + read-writeonce + + + UPPER + Upper half word + 16 + 31 + read-writeonce + + + + + KEYSLOT + Unspecified + UICR_KEYSLOT + read-write + 0x400 + + 128 + 0x008 + CONFIG[%s] + Unspecified + UICR_KEYSLOT_CONFIG + read-write + 0x000 + + DEST + Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) + will be pushed by KMU. Note that this address must match that of a peripherals + APB mapped write-only key registers, else the KMU can push this key value into + an address range which the CPU can potentially read. + 0x000 + read-write + 0xFFFFFFFF + + + DEST + Secure APB destination address + 0 + 31 + + + + + PERM + Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. + 0x004 + read-write + 0xFFFFFFFF + + + WRITE + Write permission for key slot + 0 + 0 + + + Disabled + Disable write to the key value registers + 0 + + + Enabled + Enable write to the key value registers + 1 + + + + + READ + Read permission for key slot + 1 + 1 + + + Disabled + Disable read from key value registers + 0 + + + Enabled + Enable read from key value registers + 1 + + + + + PUSH + Push permission for key slot + 2 + 2 + + + Disabled + Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled + 0 + + + Enabled + Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! + 1 + + + + + STATE + Revocation state for the key slot + 16 + 16 + + + Revoked + Key value registers can no longer be read or pushed + 0 + + + Active + Key value registers are readable (if enabled) and can be pushed (if enabled) + 1 + + + + + + + + 128 + 0x010 + KEY[%s] + Unspecified + UICR_KEYSLOT_KEY + read-write + 0x400 + + 0x4 + 0x4 + VALUE[%s] + Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. + 0x000 + read-write + 0xFFFFFFFF + + + VALUE + Define bits [31+o*32:0+o*32] of value assigned to KMU key slot + 0 + 31 + + + + + + + + + CTI_S + Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. + 0xE0042000 + CTI + + + + 0 + 0x1000 + registers + + CTI + 0x20 + + + CTICONTROL + CTI Control register + 0x000 + read-write + 0x00000000 + + + GLBEN + Enables or disables the CTI. + 0 + 0 + + + Disabled + All cross-triggering mapping logic functionality is disabled. + 0 + + + Enabled + Cross-triggering mapping logic functionality is enabled. + 1 + + + + + + + CTIINTACK + CTI Interrupt Acknowledge register + 0x010 + write-only + 0x00000000 + + + DEBUGREQ + Processor debug request + 0 + 0 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + CPURESTART + Processor Restart + 1 + 1 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED0 + N/A + 2 + 2 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + UNUSED1 + N/A + 3 + 3 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN0 + ETM Event Input 0 + 4 + 4 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN1 + ETM Event Input 1 + 5 + 5 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN2 + ETM Event Input 2 + 6 + 6 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + ETMEVTIN3 + ETM Event Input 3 + 7 + 7 + + write + + Acknowledge + Clears the ctitrigout. + 1 + + + + + + + CTIAPPSET + CTI Application Trigger Set register + 0x014 + read-write + 0x00000000 + + + APPSET_0 + Application trigger event for channel 0. + 0 + 0 + + read + + Inactive + Application trigger 0 is inactive. + 0 + + + Active + Application trigger 0 is active. + 1 + + + + write + + Activate + Generate channel event for channel 0. + 1 + + + + + APPSET_1 + Application trigger event for channel 1. + 1 + 1 + + read + + Inactive + Application trigger 1 is inactive. + 0 + + + Active + Application trigger 1 is active. + 1 + + + + write + + Activate + Generate channel event for channel 1. + 1 + + + + + APPSET_2 + Application trigger event for channel 2. + 2 + 2 + + read + + Inactive + Application trigger 2 is inactive. + 0 + + + Active + Application trigger 2 is active. + 1 + + + + write + + Activate + Generate channel event for channel 2. + 1 + + + + + APPSET_3 + Application trigger event for channel 3. + 3 + 3 + + read + + Inactive + Application trigger 3 is inactive. + 0 + + + Active + Application trigger 3 is active. + 1 + + + + write + + Activate + Generate channel event for channel 3. + 1 + + + + + + + CTIAPPCLEAR + CTI Application Trigger Clear register + 0x018 + write-only + 0x00000000 + + + APPCLEAR_0 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 0 + 0 + + write + + Clear + Clears the event for channel 0. + 1 + + + + + APPCLEAR_1 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 1 + 1 + + write + + Clear + Clears the event for channel 1. + 1 + + + + + APPCLEAR_2 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 2 + 2 + + write + + Clear + Clears the event for channel 2. + 1 + + + + + APPCLEAR_3 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 3 + 3 + + write + + Clear + Clears the event for channel 3. + 1 + + + + + + + CTIAPPPULSE + CTI Application Pulse register + 0x01C + write-only + 0x00000000 + + + APPULSE_0 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 0 + 0 + + write + + Generate + Generates an event pulse on channel 0. + 1 + + + + + APPULSE_1 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 1 + 1 + + write + + Generate + Generates an event pulse on channel 1. + 1 + + + + + APPULSE_2 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 2 + 2 + + write + + Generate + Generates an event pulse on channel 2. + 1 + + + + + APPULSE_3 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 3 + 3 + + write + + Generate + Generates an event pulse on channel 3. + 1 + + + + + + + 0x8 + 0x4 + CTIINEN[%s] + Description collection: CTI Trigger input + 0x020 + read-write + 0x00000000 + + + TRIGINEN_0 + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. + 0 + 0 + + + Disabled + Input trigger n events are ignored by channel 0. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. + 1 + + + + + TRIGINEN_1 + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. + 1 + 1 + + + Disabled + Input trigger n events are ignored by channel 1. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. + 1 + + + + + TRIGINEN_2 + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. + 2 + 2 + + + Disabled + Input trigger n events are ignored by channel 2. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. + 1 + + + + + TRIGINEN_3 + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. + 3 + 3 + + + Disabled + Input trigger n events are ignored by channel 3. + 0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. + 1 + + + + + + + 0x8 + 0x4 + CTIOUTEN[%s] + Description collection: CTI Trigger output + 0x0A0 + read-write + 0x00000000 + + + TRIGOUTEN_0 + Enables a cross trigger event to ctitrigout when channel 0 is activated. + 0 + 0 + + + Disabled + Channel 0 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_1 + Enables a cross trigger event to ctitrigout when channel 1 is activated. + 1 + 1 + + + Disabled + Channel 1 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_2 + Enables a cross trigger event to ctitrigout when channel 2 is activated. + 2 + 2 + + + Disabled + Channel 2 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). + 1 + + + + + TRIGOUTEN_3 + Enables a cross trigger event to ctitrigout when channel 3 is activated. + 3 + 3 + + + Disabled + Channel 3 is ignored by output trigger n. + 0 + + + Enabled + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). + 1 + + + + + + + CTITRIGINSTATUS + CTI Trigger In Status register + 0x130 + read-only + 0x00000000 + + + CPUHALTED + Processor Halted + 0 + 0 + + + Active + Ctitrigin 0 is active. + 1 + + + Inactive + Ctitrigin 0 is inactive. + 0 + + + + + DWTCOMPOUT0 + DWT Comparator Output 0 + 1 + 1 + + + Active + Ctitrigin 1 is active. + 1 + + + Inactive + Ctitrigin 1 is inactive. + 0 + + + + + DWTCOMPOUT1 + DWT Comparator Output 1 + 2 + 2 + + + Active + Ctitrigin 2 is active. + 1 + + + Inactive + Ctitrigin 2 is inactive. + 0 + + + + + DWTCOMPOUT2 + DWT Comparator Output 2 + 3 + 3 + + + Active + Ctitrigin 3 is active. + 1 + + + Inactive + Ctitrigin 3 is inactive. + 0 + + + + + ETMEVTOUT0 + ETM Event Output 0 + 4 + 4 + + + Active + Ctitrigin 4 is active. + 1 + + + Inactive + Ctitrigin 4 is inactive. + 0 + + + + + ETMEVTOUT1 + ETM Event Output 1 + 5 + 5 + + + Active + Ctitrigin 5 is active. + 1 + + + Inactive + Ctitrigin 5 is inactive. + 0 + + + + + UNUSED0 + N/A + 6 + 6 + + + Active + Ctitrigin 6 is active. + 1 + + + Inactive + Ctitrigin 6 is inactive. + 0 + + + + + UNUSED1 + N/A + 7 + 7 + + + Active + Ctitrigin 7 is active. + 1 + + + Inactive + Ctitrigin 7 is inactive. + 0 + + + + + + + CTITRIGOUTSTATUS + CTI Trigger Out Status register + 0x134 + read-only + 0x00000000 + + + DEBUGREQ + Processor debug request + 0 + 0 + + + Active + Ctitrigout 0 is active. + 1 + + + Inactive + Ctitrigout 0 is inactive. + 0 + + + + + CPURESTART + Processor Restart + 1 + 1 + + + Active + Ctitrigout 1 is active. + 1 + + + Inactive + Ctitrigout 1 is inactive. + 0 + + + + + UNUSED0 + N/A + 2 + 2 + + + Active + Ctitrigout 2 is active. + 1 + + + Inactive + Ctitrigout 2 is inactive. + 0 + + + + + UNUSED1 + N/A + 3 + 3 + + + Active + Ctitrigout 3 is active. + 1 + + + Inactive + Ctitrigout 3 is inactive. + 0 + + + + + ETMEVTIN0 + ETM Event Input 0 + 4 + 4 + + + Active + Ctitrigout 4 is active. + 1 + + + Inactive + Ctitrigout 4 is inactive. + 0 + + + + + ETMEVTIN1 + ETM Event Input 1 + 5 + 5 + + + Active + Ctitrigout 5 is active. + 1 + + + Inactive + Ctitrigout 5 is inactive. + 0 + + + + + ETMEVTIN2 + ETM Event Input 2 + 6 + 6 + + + Active + Ctitrigout 6 is active. + 1 + + + Inactive + Ctitrigout 6 is inactive. + 0 + + + + + ETMEVTIN3 + ETM Event Input 3 + 7 + 7 + + + Active + Ctitrigout 7 is active. + 1 + + + Inactive + Ctitrigout 7 is inactive. + 0 + + + + + + + CTICHINSTATUS + CTI Channel In Status register + 0x138 + read-only + 0x00000000 + + + CTICHINSTATUS_0 + Shows the status of the ctitrigin 0 input. + 0 + 0 + + + Active + Ctichin 0 is active. + 1 + + + Inactive + Ctichin 0 is inactive. + 0 + + + + + CTICHINSTATUS_1 + Shows the status of the ctitrigin 1 input. + 1 + 1 + + + Active + Ctichin 1 is active. + 1 + + + Inactive + Ctichin 1 is inactive. + 0 + + + + + CTICHINSTATUS_2 + Shows the status of the ctitrigin 2 input. + 2 + 2 + + + Active + Ctichin 2 is active. + 1 + + + Inactive + Ctichin 2 is inactive. + 0 + + + + + CTICHINSTATUS_3 + Shows the status of the ctitrigin 3 input. + 3 + 3 + + + Active + Ctichin 3 is active. + 1 + + + Inactive + Ctichin 3 is inactive. + 0 + + + + + + + CTIGATE + Enable CTI Channel Gate register + 0x140 + read-write + 0x0000000F + + + CTIGATEEN_0 + Enable ctichout0. + 0 + 0 + + + Enabled + Enable ctichout channel 0 propagation. + 1 + + + Disabled + Disable ctichout channel 0 propagation. + 0 + + + + + CTIGATEEN_1 + Enable ctichout1. + 1 + 1 + + + Enabled + Enable ctichout channel 1 propagation. + 1 + + + Disabled + Disable ctichout channel 1 propagation. + 0 + + + + + CTIGATEEN_2 + Enable ctichout2. + 2 + 2 + + + Enabled + Enable ctichout channel 2 propagation. + 1 + + + Disabled + Disable ctichout channel 2 propagation. + 0 + + + + + CTIGATEEN_3 + Enable ctichout3. + 3 + 3 + + + Enabled + Enable ctichout channel 3 propagation. + 1 + + + Disabled + Disable ctichout channel 3 propagation. + 0 + + + + + + + DEVARCH + Device Architecture register + 0xFBC + read-only + 0x47701A14 + + + Architecture + Contains the CTI device architecture. + 0 + 0 + + + + + DEVID + Device Configuration register + 0xFC8 + read-only + 0x00040800 + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. + The default value of 0b00000 indicates that no multiplexing is present. + 0 + 4 + + + NUMTRIG + Number of ECT triggers available. + 8 + 15 + + + NUMCH + Number of ECT channels available. + 16 + 19 + + + + + DEVTYPE + Device Type Identifier register + 0xFCC + read-only + 0x00000014 + + + MAJOR + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this + debug and trace component. + 0 + 3 + + + Controller + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 4 + + + + + SUB + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within + the major classification as specified in the MAJOR field. + 4 + 7 + + + Crosstrigger + Indicates that this component is a sub-triggering component. + 1 + + + + + + + PIDR4 + Peripheral ID4 Register + 0xFD0 + read-only + 0x00000004 + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + + + Code + JEDEC continuation code. + 4 + + + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory. + 4 + 7 + + + + + PIDR5 + Peripheral ID5 register + 0xFD4 + read-only + + + PIDR6 + Peripheral ID6 register + 0xFD8 + read-only + + + PIDR7 + Peripheral ID7 register + 0xFDC + read-only + + + PIDR0 + Peripheral ID0 Register + 0xFE0 + read-only + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 7 + + + PartnumberL + Indicates bits[7:0] of the part number of the component. + 0x21 + + + + + + + PIDR1 + Peripheral ID1 Register + 0xFE4 + read-only + 0x000000BD + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 3 + + + PartnumberH + Indicates bits[11:8] of the part number of the component. + 13 + + + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 7 + + + Arm + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 11 + + + + + + + PIDR2 + Peripheral ID2 Register + 0xFE8 + read-only + 0x0000000B + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 2 + + + Arm + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 3 + + + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + 3 + 3 + + + REVISION + Peripheral revision + 4 + 7 + + + Rev0p0 + This device is at r0p0 + 0 + + + + + + + PIDR3 + Peripheral ID3 Register + 0xFEC + read-only + 0x00000000 + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, + this field is 0b0000. Customers change this value when they make authorized modifications to this component. + 0 + 3 + + + Unmodified + Indicates that the customer has not modified this component. + 0 + + + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a + metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + 4 + 7 + + + NoErrata + Indicates that there are no errata fixes to this component. + 0 + + + + + + + CIDR0 + Component ID0 Register + 0xFF0 + read-only + 0x0000000D + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code. + 0 + 7 + + + Value + Bits[7:0] of the identification code. + 0x0D + + + + + + + CIDR1 + Component ID1 Register + 0xFF4 + read-only + 0x00000090 + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + 0 + 3 + + + Value + Bits[11:8] of the identification code. + 0 + + + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code + 4 + 7 + + + Coresight + Indicates that the component is a CoreSight component. + 9 + + + + + + + CIDR2 + Component ID2 Register + 0xFF8 + read-only + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + 0 + 7 + + + Value + Bits[23:16] of the identification code. + 0x05 + + + + + + + CIDR3 + Component ID3 Register + 0xFFC + read-only + 0x000000B1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + 0 + 7 + + + Value + Bits[31:24] of the identification code. + 0xB1 + + + + + + + + + TAD_S + Trace and debug control + 0xE0080000 + TAD + + + + 0 + 0x1000 + registers + + TAD + 0x20 + + + CLOCKSTART + Start all trace and debug clocks. + 0x004 + write-only + + + START + 0 + 0 + + + Start + Start all trace and debug clocks. + 1 + + + + + + + CLOCKSTOP + Stop all trace and debug clocks. + 0x008 + write-only + + + STOP + 0 + 0 + + + Stop + Stop all trace and debug clocks. + 1 + + + + + + + ENABLE + Enable debug domain and aquire selected GPIOs + 0x500 + read-write + + + ENABLE + 0 + 0 + + + DISABLED + Disable debug domain and release selected GPIOs + 0 + + + ENABLED + Enable debug domain and aquire selected GPIOs + 1 + + + + + + + PSEL + Unspecified + TAD_PSEL + read-write + 0x504 + + TRACECLK + Pin configuration for TRACECLK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Traceclk + TRACECLK pin + 12 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA0 + Pin configuration for TRACEDATA[0] + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata0 + TRACEDATA0 pin + 11 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA1 + Pin configuration for TRACEDATA[1] + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata1 + TRACEDATA1 pin + 10 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA2 + Pin configuration for TRACEDATA[2] + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata2 + TRACEDATA2 pin + 9 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA3 + Pin configuration for TRACEDATA[3] + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata3 + TRACEDATA3 pin + 8 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + TRACEPORTSPEED + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components + 0x518 + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. + 0 + 1 + + + 64MHz + Trace Port clock is: 64MHz + 0 + + + 32MHz + Trace Port clock is: 32MHz + 1 + + + 16MHz + Trace Port clock is: 16MHz + 2 + + + 8MHz + Trace Port clock is: 8MHz + 3 + + + + + + + + + DCNF_NS + Domain configuration management 0 + 0x40000000 + DCNF + + + + 0 + 0x1000 + registers + + DCNF + 0x20 + + + CPUID + CPU ID of this subsystem + 0x420 + read-only + 0x00000000 + + + CPUID + CPU ID + 0 + 7 + + + + + 1 + 0x004 + EXTPERI[%s] + Unspecified + DCNF_EXTPERI + read-write + 0x440 + + PROTECT + Description cluster: Control access for master connected to AMLI master port EXTPERI[n] + 0x000 + read-write + + + SLAVE0 + Control access to slave 0 of master EXTPERI[n] + 0 + 0 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + + + + 1 + 0x004 + EXTRAM[%s] + Unspecified + DCNF_EXTRAM + read-write + 0x460 + + PROTECT + Description cluster: Control access from master connected to AMLI master port EXTRAM[n] + 0x000 + read-write + + + SLAVE0 + Control access to slave 0 of master EXTRAM[n] + 0 + 0 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE1 + Control access to slave 1 of master EXTRAM[n] + 1 + 1 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE2 + Control access to slave 2 of master EXTRAM[n] + 2 + 2 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE3 + Control access to slave 3 of master EXTRAM[n] + 3 + 3 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE4 + Control access to slave 4 of master EXTRAM[n] + 4 + 4 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE5 + Control access to slave 5 of master EXTRAM[n] + 5 + 5 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE6 + Control access to slave 6 of master EXTRAM[n] + 6 + 6 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + SLAVE7 + Control access to slave 7 of master EXTRAM[n] + 7 + 7 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + + + + 1 + 0x004 + EXTCODE[%s] + Unspecified + DCNF_EXTCODE + read-write + 0x480 + + PROTECT + Description cluster: Control access from master connected to AMLI master port EXTCODE[n] + 0x000 + read-write + + + SLAVE0 + Control access to slave 0 of master EXTCODE[n] + 0 + 0 + + + Allowed + Access to slave is allowed + 0 + + + Blocked + Access to slave is blocked + 1 + + + + + + + + + + FPU_NS + FPU control peripheral 0 + 0x40000000 + DCNF_NS + FPU + + + + 0 + 0x1000 + registers + + + FPU + 0 + + FPU + 0x20 + + + EVENTS_INVALIDOPERATION + An FPUIOC exception triggered by an invalid operation has occurred in the FPU + 0x100 + read-write + + + EVENTS_INVALIDOPERATION + An FPUIOC exception triggered by an invalid operation has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DIVIDEBYZERO + An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU + 0x104 + read-write + + + EVENTS_DIVIDEBYZERO + An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVERFLOW + An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU + 0x108 + read-write + + + EVENTS_OVERFLOW + An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UNDERFLOW + An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU + 0x10C + read-write + + + EVENTS_UNDERFLOW + An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_INEXACT + An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU + 0x110 + read-write + + + EVENTS_INEXACT + An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DENORMALINPUT + An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU + 0x114 + read-write + + + EVENTS_DENORMALINPUT + An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + INVALIDOPERATION + Enable or disable interrupt for event INVALIDOPERATION + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DIVIDEBYZERO + Enable or disable interrupt for event DIVIDEBYZERO + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVERFLOW + Enable or disable interrupt for event OVERFLOW + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UNDERFLOW + Enable or disable interrupt for event UNDERFLOW + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + INEXACT + Enable or disable interrupt for event INEXACT + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DENORMALINPUT + Enable or disable interrupt for event DENORMALINPUT + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + INVALIDOPERATION + Write '1' to enable interrupt for event INVALIDOPERATION + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DIVIDEBYZERO + Write '1' to enable interrupt for event DIVIDEBYZERO + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVERFLOW + Write '1' to enable interrupt for event OVERFLOW + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UNDERFLOW + Write '1' to enable interrupt for event UNDERFLOW + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + INEXACT + Write '1' to enable interrupt for event INEXACT + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DENORMALINPUT + Write '1' to enable interrupt for event DENORMALINPUT + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + INVALIDOPERATION + Write '1' to disable interrupt for event INVALIDOPERATION + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DIVIDEBYZERO + Write '1' to disable interrupt for event DIVIDEBYZERO + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVERFLOW + Write '1' to disable interrupt for event OVERFLOW + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UNDERFLOW + Write '1' to disable interrupt for event UNDERFLOW + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + INEXACT + Write '1' to disable interrupt for event INEXACT + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DENORMALINPUT + Write '1' to disable interrupt for event DENORMALINPUT + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + DCNF_S + Domain configuration management 1 + 0x50000000 + + + + + FPU_S + FPU control peripheral 1 + 0x50000000 + DCNF_S + + + + FPU + 0 + + + + CACHE_S + Cache + 0x50001000 + CACHE + + + + 0 + 0x1000 + registers + + + CACHE + 1 + + CACHE + 0x20 + + + 2 + 0x020 + PROFILING[%s] + Unspecified + CACHE_PROFILING + read-write + 0x400 + + IHIT + Description cluster: Instruction fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x000 + read-only + + + HITS + Number of instruction cache hits + 0 + 31 + + + + + IMISS + Description cluster: Instruction fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x004 + read-only + + + MISSES + Number of instruction cache misses + 0 + 31 + + + + + DHIT + Description cluster: Data fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x008 + read-only + + + HITS + Number of data cache hits + 0 + 31 + + + + + DMISS + Description cluster: Data fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. + 0x00C + read-only + + + MISSES + Number of data cache misses + 0 + 31 + + + + + + ENABLE + Enable cache. + 0x500 + read-write + + + ENABLE + Enable cache + 0 + 0 + + + Disabled + Disable cache + 0 + + + Enabled + Enable cache + 1 + + + + + + + INVALIDATE + Invalidate the cache. + 0x504 + write-only + + + INVALIDATE + Invalidate the cache + 0 + 0 + + + Invalidate + Invalidate the cache + 1 + + + + + + + ERASE + Erase the cache. + 0x508 + write-only + + + ERASE + Erase the cache + 0 + 0 + + + Erase + Erase cache + 1 + + + + + + + PROFILINGENABLE + Enable the profiling counters. + 0x50C + read-write + + + ENABLE + Enable the profiling counters + 0 + 0 + + + Disable + Disable profiling + 0 + + + Enable + Enable profiling + 1 + + + + + + + PROFILINGCLEAR + Clear the profiling counters. + 0x510 + write-only + + + CLEAR + Clearing the profiling counters + 0 + 0 + + + Clear + Clear the profiling counters + 1 + + + + + + + MODE + Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. + 0x514 + read-write + + + MODE + Cache mode + 0 + 0 + + + Cache + Cache mode + 0 + + + Ram + RAM mode + 1 + + + + + + + DEBUGLOCK + Lock debug mode. + 0x518 + read-writeonce + + + DEBUGLOCK + Lock debug mode + 0 + 0 + + + Unlocked + Debug mode unlocked + 0 + + + Locked + Debug mode locked + 1 + + + + + + + ERASESTATUS + Cache erase status. + 0x51C + read-write + + + ERASESTATUS + Cache erase status + 0 + 0 + + + Idle + Erase is not complete or hasn't started + 0 + + + Finished + Cache erase is finished + 1 + + + + + + + WRITELOCK + Lock cache updates. Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content already present in the cache. Ignored in RAM mode. + 0x520 + read-write + + + WRITELOCK + Lock cache updates + 0 + 0 + + + Unlocked + Cache updates unlocked + 0 + + + Locked + Cache updates locked + 1 + + + + + + + + + SPU_S + System protection unit + 0x50003000 + SPU + + + + 0 + 0x1000 + registers + + + SPU + 3 + + SPU + 0x20 + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0x100 + read-write + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0x104 + read-write + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x108 + read-write + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RAMACCERR + Publish configuration for event RAMACCERR + 0x180 + read-write + + + CHIDX + DPPI channel that event RAMACCERR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FLASHACCERR + Publish configuration for event FLASHACCERR + 0x184 + read-write + + + CHIDX + DPPI channel that event FLASHACCERR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PERIPHACCERR + Publish configuration for event PERIPHACCERR + 0x188 + read-write + + + CHIDX + DPPI channel that event PERIPHACCERR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RAMACCERR + Enable or disable interrupt for event RAMACCERR + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FLASHACCERR + Enable or disable interrupt for event FLASHACCERR + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RAMACCERR + Write '1' to enable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FLASHACCERR + Write '1' to enable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RAMACCERR + Write '1' to disable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FLASHACCERR + Write '1' to disable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CAP + Show implemented features for the current device + 0x400 + read-only + 0x00000001 + + + TZM + Show Arm TrustZone status + 0 + 0 + + + NotAvailable + Arm TrustZone support not available + 0 + + + Enabled + Arm TrustZone support is available + 1 + + + + + + + CPULOCK + Configure bits to lock down CPU features at runtime + 0x404 + read-write + 0x00000000 + oneToSet + + + LOCKSVTAIRCR + Write '1' to prevent updating the secure interrupt configuration until the next reset + 0 + 0 + + + Locked + Disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers + 1 + + + Unlocked + These registers can be updated + 0 + + + + + LOCKNSVTOR + Write '1' to prevent updating the non-secure vector table base address until the next reset + 1 + 1 + + + Locked + The address of the non-secure vector table is locked + 1 + + + Unlocked + The address of the non-secure vector table can be updated + 0 + + + + + LOCKSMPU + Write '1' to prevent updating the secure MPU regions until the next reset + 2 + 2 + + + Locked + Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state + 1 + + + Unlocked + These registers can be updated + 0 + + + + + LOCKNSMPU + Write '1' to prevent updating the Non-secure MPU regions until the next reset + 3 + 3 + + + Locked + Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + 1 + + + Unlocked + These registers can be updated + 0 + + + + + LOCKSAU + Write '1' to prevent updating the secure SAU regions until the next reset + 4 + 4 + + + Locked + Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + 1 + + + Unlocked + These registers can be updated + 0 + + + + + + + 1 + 0x004 + EXTDOMAIN[%s] + Unspecified + SPU_EXTDOMAIN + read-write + 0x440 + + PERM + Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n + 0x000 + read-write + 0x00000002 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + The bus access from this external domain always have the non-secure attribute set + 0 + + + Secure + The bus access from this external domain always have the secure attribute set + 1 + + + UserSelectable + Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + NonSecure + Bus accesses from this domain have the non-secure attribute set + 0 + + + Secure + Bus accesses from this domain have secure attribute set + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 1 + 0x008 + DPPI[%s] + Unspecified + SPU_DPPI + read-write + 0x480 + + PERM + Description cluster: Select between secure and non-secure attribute for the DPPI channels + 0x000 + read-write + 0xFFFFFFFF + + + CHANNEL0 + Select secure attribute + 0 + 0 + + + Secure + Channel 0 has its secure attribute set + 1 + + + NonSecure + Channel 0 has its non-secure attribute set + 0 + + + + + CHANNEL1 + Select secure attribute + 1 + 1 + + + Secure + Channel 1 has its secure attribute set + 1 + + + NonSecure + Channel 1 has its non-secure attribute set + 0 + + + + + CHANNEL2 + Select secure attribute + 2 + 2 + + + Secure + Channel 2 has its secure attribute set + 1 + + + NonSecure + Channel 2 has its non-secure attribute set + 0 + + + + + CHANNEL3 + Select secure attribute + 3 + 3 + + + Secure + Channel 3 has its secure attribute set + 1 + + + NonSecure + Channel 3 has its non-secure attribute set + 0 + + + + + CHANNEL4 + Select secure attribute + 4 + 4 + + + Secure + Channel 4 has its secure attribute set + 1 + + + NonSecure + Channel 4 has its non-secure attribute set + 0 + + + + + CHANNEL5 + Select secure attribute + 5 + 5 + + + Secure + Channel 5 has its secure attribute set + 1 + + + NonSecure + Channel 5 has its non-secure attribute set + 0 + + + + + CHANNEL6 + Select secure attribute + 6 + 6 + + + Secure + Channel 6 has its secure attribute set + 1 + + + NonSecure + Channel 6 has its non-secure attribute set + 0 + + + + + CHANNEL7 + Select secure attribute + 7 + 7 + + + Secure + Channel 7 has its secure attribute set + 1 + + + NonSecure + Channel 7 has its non-secure attribute set + 0 + + + + + CHANNEL8 + Select secure attribute + 8 + 8 + + + Secure + Channel 8 has its secure attribute set + 1 + + + NonSecure + Channel 8 has its non-secure attribute set + 0 + + + + + CHANNEL9 + Select secure attribute + 9 + 9 + + + Secure + Channel 9 has its secure attribute set + 1 + + + NonSecure + Channel 9 has its non-secure attribute set + 0 + + + + + CHANNEL10 + Select secure attribute + 10 + 10 + + + Secure + Channel 10 has its secure attribute set + 1 + + + NonSecure + Channel 10 has its non-secure attribute set + 0 + + + + + CHANNEL11 + Select secure attribute + 11 + 11 + + + Secure + Channel 11 has its secure attribute set + 1 + + + NonSecure + Channel 11 has its non-secure attribute set + 0 + + + + + CHANNEL12 + Select secure attribute + 12 + 12 + + + Secure + Channel 12 has its secure attribute set + 1 + + + NonSecure + Channel 12 has its non-secure attribute set + 0 + + + + + CHANNEL13 + Select secure attribute + 13 + 13 + + + Secure + Channel 13 has its secure attribute set + 1 + + + NonSecure + Channel 13 has its non-secure attribute set + 0 + + + + + CHANNEL14 + Select secure attribute + 14 + 14 + + + Secure + Channel 14 has its secure attribute set + 1 + + + NonSecure + Channel 14 has its non-secure attribute set + 0 + + + + + CHANNEL15 + Select secure attribute + 15 + 15 + + + Secure + Channel 15 has its secure attribute set + 1 + + + NonSecure + Channel 15 has its non-secure attribute set + 0 + + + + + CHANNEL16 + Select secure attribute + 16 + 16 + + + Secure + Channel 16 has its secure attribute set + 1 + + + NonSecure + Channel 16 has its non-secure attribute set + 0 + + + + + CHANNEL17 + Select secure attribute + 17 + 17 + + + Secure + Channel 17 has its secure attribute set + 1 + + + NonSecure + Channel 17 has its non-secure attribute set + 0 + + + + + CHANNEL18 + Select secure attribute + 18 + 18 + + + Secure + Channel 18 has its secure attribute set + 1 + + + NonSecure + Channel 18 has its non-secure attribute set + 0 + + + + + CHANNEL19 + Select secure attribute + 19 + 19 + + + Secure + Channel 19 has its secure attribute set + 1 + + + NonSecure + Channel 19 has its non-secure attribute set + 0 + + + + + CHANNEL20 + Select secure attribute + 20 + 20 + + + Secure + Channel 20 has its secure attribute set + 1 + + + NonSecure + Channel 20 has its non-secure attribute set + 0 + + + + + CHANNEL21 + Select secure attribute + 21 + 21 + + + Secure + Channel 21 has its secure attribute set + 1 + + + NonSecure + Channel 21 has its non-secure attribute set + 0 + + + + + CHANNEL22 + Select secure attribute + 22 + 22 + + + Secure + Channel 22 has its secure attribute set + 1 + + + NonSecure + Channel 22 has its non-secure attribute set + 0 + + + + + CHANNEL23 + Select secure attribute + 23 + 23 + + + Secure + Channel 23 has its secure attribute set + 1 + + + NonSecure + Channel 23 has its non-secure attribute set + 0 + + + + + CHANNEL24 + Select secure attribute + 24 + 24 + + + Secure + Channel 24 has its secure attribute set + 1 + + + NonSecure + Channel 24 has its non-secure attribute set + 0 + + + + + CHANNEL25 + Select secure attribute + 25 + 25 + + + Secure + Channel 25 has its secure attribute set + 1 + + + NonSecure + Channel 25 has its non-secure attribute set + 0 + + + + + CHANNEL26 + Select secure attribute + 26 + 26 + + + Secure + Channel 26 has its secure attribute set + 1 + + + NonSecure + Channel 26 has its non-secure attribute set + 0 + + + + + CHANNEL27 + Select secure attribute + 27 + 27 + + + Secure + Channel 27 has its secure attribute set + 1 + + + NonSecure + Channel 27 has its non-secure attribute set + 0 + + + + + CHANNEL28 + Select secure attribute + 28 + 28 + + + Secure + Channel 28 has its secure attribute set + 1 + + + NonSecure + Channel 28 has its non-secure attribute set + 0 + + + + + CHANNEL29 + Select secure attribute + 29 + 29 + + + Secure + Channel 29 has its secure attribute set + 1 + + + NonSecure + Channel 29 has its non-secure attribute set + 0 + + + + + CHANNEL30 + Select secure attribute + 30 + 30 + + + Secure + Channel 30 has its secure attribute set + 1 + + + NonSecure + Channel 30 has its non-secure attribute set + 0 + + + + + CHANNEL31 + Select secure attribute + 31 + 31 + + + Secure + Channel 31 has its secure attribute set + 1 + + + NonSecure + Channel 31 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + DPPI[n].PERM register can't be changed until next reset + 1 + + + Unlocked + DPPI[n].PERM register content can be changed + 0 + + + + + + + + 2 + 0x008 + GPIOPORT[%s] + Unspecified + SPU_GPIOPORT + read-write + 0x4C0 + + PERM + Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n + 0x000 + read-write + 0xFFFFFFFF + + + PIN0 + Select secure attribute attribute for PIN 0. + 0 + 0 + + + Secure + Pin 0 has its secure attribute set + 1 + + + NonSecure + Pin 0 has its non-secure attribute set + 0 + + + + + PIN1 + Select secure attribute attribute for PIN 1. + 1 + 1 + + + Secure + Pin 1 has its secure attribute set + 1 + + + NonSecure + Pin 1 has its non-secure attribute set + 0 + + + + + PIN2 + Select secure attribute attribute for PIN 2. + 2 + 2 + + + Secure + Pin 2 has its secure attribute set + 1 + + + NonSecure + Pin 2 has its non-secure attribute set + 0 + + + + + PIN3 + Select secure attribute attribute for PIN 3. + 3 + 3 + + + Secure + Pin 3 has its secure attribute set + 1 + + + NonSecure + Pin 3 has its non-secure attribute set + 0 + + + + + PIN4 + Select secure attribute attribute for PIN 4. + 4 + 4 + + + Secure + Pin 4 has its secure attribute set + 1 + + + NonSecure + Pin 4 has its non-secure attribute set + 0 + + + + + PIN5 + Select secure attribute attribute for PIN 5. + 5 + 5 + + + Secure + Pin 5 has its secure attribute set + 1 + + + NonSecure + Pin 5 has its non-secure attribute set + 0 + + + + + PIN6 + Select secure attribute attribute for PIN 6. + 6 + 6 + + + Secure + Pin 6 has its secure attribute set + 1 + + + NonSecure + Pin 6 has its non-secure attribute set + 0 + + + + + PIN7 + Select secure attribute attribute for PIN 7. + 7 + 7 + + + Secure + Pin 7 has its secure attribute set + 1 + + + NonSecure + Pin 7 has its non-secure attribute set + 0 + + + + + PIN8 + Select secure attribute attribute for PIN 8. + 8 + 8 + + + Secure + Pin 8 has its secure attribute set + 1 + + + NonSecure + Pin 8 has its non-secure attribute set + 0 + + + + + PIN9 + Select secure attribute attribute for PIN 9. + 9 + 9 + + + Secure + Pin 9 has its secure attribute set + 1 + + + NonSecure + Pin 9 has its non-secure attribute set + 0 + + + + + PIN10 + Select secure attribute attribute for PIN 10. + 10 + 10 + + + Secure + Pin 10 has its secure attribute set + 1 + + + NonSecure + Pin 10 has its non-secure attribute set + 0 + + + + + PIN11 + Select secure attribute attribute for PIN 11. + 11 + 11 + + + Secure + Pin 11 has its secure attribute set + 1 + + + NonSecure + Pin 11 has its non-secure attribute set + 0 + + + + + PIN12 + Select secure attribute attribute for PIN 12. + 12 + 12 + + + Secure + Pin 12 has its secure attribute set + 1 + + + NonSecure + Pin 12 has its non-secure attribute set + 0 + + + + + PIN13 + Select secure attribute attribute for PIN 13. + 13 + 13 + + + Secure + Pin 13 has its secure attribute set + 1 + + + NonSecure + Pin 13 has its non-secure attribute set + 0 + + + + + PIN14 + Select secure attribute attribute for PIN 14. + 14 + 14 + + + Secure + Pin 14 has its secure attribute set + 1 + + + NonSecure + Pin 14 has its non-secure attribute set + 0 + + + + + PIN15 + Select secure attribute attribute for PIN 15. + 15 + 15 + + + Secure + Pin 15 has its secure attribute set + 1 + + + NonSecure + Pin 15 has its non-secure attribute set + 0 + + + + + PIN16 + Select secure attribute attribute for PIN 16. + 16 + 16 + + + Secure + Pin 16 has its secure attribute set + 1 + + + NonSecure + Pin 16 has its non-secure attribute set + 0 + + + + + PIN17 + Select secure attribute attribute for PIN 17. + 17 + 17 + + + Secure + Pin 17 has its secure attribute set + 1 + + + NonSecure + Pin 17 has its non-secure attribute set + 0 + + + + + PIN18 + Select secure attribute attribute for PIN 18. + 18 + 18 + + + Secure + Pin 18 has its secure attribute set + 1 + + + NonSecure + Pin 18 has its non-secure attribute set + 0 + + + + + PIN19 + Select secure attribute attribute for PIN 19. + 19 + 19 + + + Secure + Pin 19 has its secure attribute set + 1 + + + NonSecure + Pin 19 has its non-secure attribute set + 0 + + + + + PIN20 + Select secure attribute attribute for PIN 20. + 20 + 20 + + + Secure + Pin 20 has its secure attribute set + 1 + + + NonSecure + Pin 20 has its non-secure attribute set + 0 + + + + + PIN21 + Select secure attribute attribute for PIN 21. + 21 + 21 + + + Secure + Pin 21 has its secure attribute set + 1 + + + NonSecure + Pin 21 has its non-secure attribute set + 0 + + + + + PIN22 + Select secure attribute attribute for PIN 22. + 22 + 22 + + + Secure + Pin 22 has its secure attribute set + 1 + + + NonSecure + Pin 22 has its non-secure attribute set + 0 + + + + + PIN23 + Select secure attribute attribute for PIN 23. + 23 + 23 + + + Secure + Pin 23 has its secure attribute set + 1 + + + NonSecure + Pin 23 has its non-secure attribute set + 0 + + + + + PIN24 + Select secure attribute attribute for PIN 24. + 24 + 24 + + + Secure + Pin 24 has its secure attribute set + 1 + + + NonSecure + Pin 24 has its non-secure attribute set + 0 + + + + + PIN25 + Select secure attribute attribute for PIN 25. + 25 + 25 + + + Secure + Pin 25 has its secure attribute set + 1 + + + NonSecure + Pin 25 has its non-secure attribute set + 0 + + + + + PIN26 + Select secure attribute attribute for PIN 26. + 26 + 26 + + + Secure + Pin 26 has its secure attribute set + 1 + + + NonSecure + Pin 26 has its non-secure attribute set + 0 + + + + + PIN27 + Select secure attribute attribute for PIN 27. + 27 + 27 + + + Secure + Pin 27 has its secure attribute set + 1 + + + NonSecure + Pin 27 has its non-secure attribute set + 0 + + + + + PIN28 + Select secure attribute attribute for PIN 28. + 28 + 28 + + + Secure + Pin 28 has its secure attribute set + 1 + + + NonSecure + Pin 28 has its non-secure attribute set + 0 + + + + + PIN29 + Select secure attribute attribute for PIN 29. + 29 + 29 + + + Secure + Pin 29 has its secure attribute set + 1 + + + NonSecure + Pin 29 has its non-secure attribute set + 0 + + + + + PIN30 + Select secure attribute attribute for PIN 30. + 30 + 30 + + + Secure + Pin 30 has its secure attribute set + 1 + + + NonSecure + Pin 30 has its non-secure attribute set + 0 + + + + + PIN31 + Select secure attribute attribute for PIN 31. + 31 + 31 + + + Secure + Pin 31 has its secure attribute set + 1 + + + NonSecure + Pin 31 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + GPIOPORT[n].PERM register can't be changed until next reset + 1 + + + Unlocked + GPIOPORT[n].PERM register content can be changed + 0 + + + + + + + + 2 + 0x008 + FLASHNSC[%s] + Unspecified + SPU_FLASHNSC + read-write + 0x500 + + REGION + Description cluster: Define which flash region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 5 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with size 32 bytes + 1 + + + 64 + The region n is defined as non-secure callable with size 64 bytes + 2 + + + 128 + The region n is defined as non-secure callable with size 128 bytes + 3 + + + 256 + The region n is defined as non-secure callable with size 256 bytes + 4 + + + 512 + The region n is defined as non-secure callable with size 512 bytes + 5 + + + 1024 + The region n is defined as non-secure callable with size 1024 bytes + 6 + + + 2048 + The region n is defined as non-secure callable with size 2048 bytes + 7 + + + 4096 + The region n is defined as non-secure callable with size 4096 bytes + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 2 + 0x008 + RAMNSC[%s] + Unspecified + SPU_RAMNSC + read-write + 0x540 + + REGION + Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 5 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with size 32 bytes + 1 + + + 64 + The region n is defined as non-secure callable with size 64 bytes + 2 + + + 128 + The region n is defined as non-secure callable with size 128 bytes + 3 + + + 256 + The region n is defined as non-secure callable with size 256 bytes + 4 + + + 512 + The region n is defined as non-secure callable with size 512 bytes + 5 + + + 1024 + The region n is defined as non-secure callable with size 1024 bytes + 6 + + + 2048 + The region n is defined as non-secure callable with size 2048 bytes + 7 + + + 4096 + The region n is defined as non-secure callable with size 4096 bytes + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 64 + 0x004 + FLASHREGION[%s] + Unspecified + SPU_FLASHREGION + read-write + 0x600 + + PERM + Description cluster: Access permissions for flash region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from flash region n + 0 + 0 + + + Enable + Allow instruction fetches from flash region n + 1 + + + Disable + Block instruction fetches from flash region n + 0 + + + + + WRITE + Configure write permission for flash region n + 1 + 1 + + + Enable + Allow write operation to region n + 1 + + + Disable + Block write operation to region n + 0 + + + + + READ + Configure read permissions for flash region n + 2 + 2 + + + Enable + Allow read operation from flash region n + 1 + + + Disable + Block read operation from flash region n + 0 + + + + + SECATTR + Security attribute for flash region n + 4 + 4 + + + Non_Secure + Flash region n security attribute is non-secure + 0 + + + Secure + Flash region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 64 + 0x004 + RAMREGION[%s] + Unspecified + SPU_RAMREGION + read-write + 0x700 + + PERM + Description cluster: Access permissions for RAM region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from RAM region n + 0 + 0 + + + Enable + Allow instruction fetches from RAM region n + 1 + + + Disable + Block instruction fetches from RAM region n + 0 + + + + + WRITE + Configure write permission for RAM region n + 1 + 1 + + + Enable + Allow write operation to RAM region n + 1 + + + Disable + Block write operation to RAM region n + 0 + + + + + READ + Configure read permissions for RAM region n + 2 + 2 + + + Enable + Allow read operation from RAM region n + 1 + + + Disable + Block read operation from RAM region n + 0 + + + + + SECATTR + Security attribute for RAM region n + 4 + 4 + + + Non_Secure + RAM region n security attribute is non-secure + 0 + + + Secure + RAM region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 256 + 0x004 + PERIPHID[%s] + Unspecified + SPU_PERIPHID + read-write + 0x800 + + PERM + Description cluster: List capabilities and access permissions for the peripheral with ID n + 0x000 + read-write + 0x00000012 + + + SECUREMAPPING + Define configuration capabilities for Arm TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0 + + + Secure + This peripheral is always accessible as a secure peripheral + 1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register + 2 + + + Split + This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. + 3 + + + + + DMA + Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + PRESENT + Indicate if a peripheral is present with ID n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0 + + + IsPresent + Peripheral is present + 1 + + + + + + + + + + OSCILLATORS_NS + Oscillator control 0 + 0x40004000 + OSCILLATORS + + + + 0 + 0x1000 + registers + + OSCILLATORS + 0x20 + + + XOSC32MCAPS + Programmable capacitance of XC1 and XC2 + 0x5C4 + read-write + + + CAPVALUE + Value representing capacitance, calculated using provided equation + 0 + 4 + + + ENABLE + Enable on-chip capacitors on XC1 and XC2 + 8 + 8 + + + Disabled + Capacitor disabled (use external caps) + 0 + + + Enabled + Capacitor enabled + 1 + + + + + + + XOSC32KI + Unspecified + OSCILLATORS_XOSC32KI + read-write + 0x6C0 + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0x000 + read-write + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 0 + 0 + + + Disabled + Disable (use with crystal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + + + INTCAP + Control usage of internal load capacitors + 0x010 + read-write + + + INTCAP + Control usage of internal load capacitors + 0 + 1 + + + External + Use external load capacitors + 0 + + + C6PF + 6 pF internal load capacitance + 1 + + + C7PF + 7 pF internal load capacitance + 2 + + + C9PF + 9 pF internal load capacitance + 3 + + + + + + + + + + REGULATORS_NS + Voltage regulators 0 + 0x40004000 + OSCILLATORS_NS + REGULATORS + + + + 0 + 0x1000 + registers + + REGULATORS + 0x20 + + + MAINREGSTATUS + Main supply status + 0x428 + read-only + 0x00000000 + + + VREGH + VREGH status + 0 + 0 + + + Inactive + Normal voltage mode. Voltage supplied on VDD and VDDH. + 0 + + + Active + High voltage mode. Voltage supplied on VDDH. + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power-fail comparator configuration + 0x510 + read-write + + + POF + Enable or disable power-fail comparator + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power-fail comparator threshold setting + 1 + 4 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + THRESHOLDVDDH + Power-fail comparator threshold setting for voltage supply on VDDH + 8 + 11 + + + V27 + Set threshold to 2.7 V + 0 + + + V28 + Set threshold to 2.8 V + 1 + + + V29 + Set threshold to 2.9 V + 2 + + + V30 + Set threshold to 3.0 V + 3 + + + V31 + Set threshold to 3.1 V + 4 + + + V32 + Set threshold to 3.2 V + 5 + + + V33 + Set threshold to 3.3 V + 6 + + + V34 + Set threshold to 3.4 V + 7 + + + V35 + Set threshold to 3.5 V + 8 + + + V36 + Set threshold to 3.6 V + 9 + + + V37 + Set threshold to 3.7 V + 10 + + + V38 + Set threshold to 3.8 V + 11 + + + V39 + Set threshold to 3.9 V + 12 + + + V40 + Set threshold to 4.0 V + 13 + + + V41 + Set threshold to 4.1 V + 14 + + + V42 + Set threshold to 4.2 V + 15 + + + + + + + VREGMAIN + Unspecified + REGULATORS_VREGMAIN + read-write + 0x704 + + DCDCEN + DC/DC enable register for VREGMAIN + 0x000 + read-write + 0x00000000 + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + + VREGRADIO + Unspecified + REGULATORS_VREGRADIO + read-write + 0x900 + + DCDCEN + DC/DC enable register for VREGRADIO + 0x004 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + + VREGH + Unspecified + REGULATORS_VREGH + read-write + 0xB00 + + DCDCEN + DC/DC enable register for VREGH + 0x000 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + + + + OSCILLATORS_S + Oscillator control 1 + 0x50004000 + + + + + REGULATORS_S + Voltage regulators 1 + 0x50004000 + OSCILLATORS_S + + + + + CLOCK_NS + Clock management 0 + 0x40005000 + CLOCK + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK128M/HFCLK64M source + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK128M/HFCLK64M source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLKSRC + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLKSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKAUDIOSTART + Start HFCLKAUDIO source + 0x018 + write-only + + + TASKS_HFCLKAUDIOSTART + Start HFCLKAUDIO source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKAUDIOSTOP + Stop HFCLKAUDIO source + 0x01C + write-only + + + TASKS_HFCLKAUDIOSTOP + Stop HFCLKAUDIO source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLK192MSTART + Start HFCLK192M source as selected in HFCLK192MSRC + 0x020 + write-only + + + TASKS_HFCLK192MSTART + Start HFCLK192M source as selected in HFCLK192MSRC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLK192MSTOP + Stop HFCLK192M source + 0x024 + write-only + + + TASKS_HFCLK192MSTOP + Stop HFCLK192M source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_HFCLKSTART + Subscribe configuration for task HFCLKSTART + 0x080 + read-write + + + CHIDX + DPPI channel that task HFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKSTOP + Subscribe configuration for task HFCLKSTOP + 0x084 + read-write + + + CHIDX + DPPI channel that task HFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTART + Subscribe configuration for task LFCLKSTART + 0x088 + read-write + + + CHIDX + DPPI channel that task LFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTOP + Subscribe configuration for task LFCLKSTOP + 0x08C + read-write + + + CHIDX + DPPI channel that task LFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CAL + Subscribe configuration for task CAL + 0x090 + read-write + + + CHIDX + DPPI channel that task CAL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKAUDIOSTART + Subscribe configuration for task HFCLKAUDIOSTART + 0x098 + read-write + + + CHIDX + DPPI channel that task HFCLKAUDIOSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKAUDIOSTOP + Subscribe configuration for task HFCLKAUDIOSTOP + 0x09C + read-write + + + CHIDX + DPPI channel that task HFCLKAUDIOSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLK192MSTART + Subscribe configuration for task HFCLK192MSTART + 0x0A0 + read-write + + + CHIDX + DPPI channel that task HFCLK192MSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLK192MSTOP + Subscribe configuration for task HFCLK192MSTOP + 0x0A4 + read-write + + + CHIDX + DPPI channel that task HFCLK192MSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK128M/HFCLK64M source started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK128M/HFCLK64M source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0x11C + read-write + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_HFCLKAUDIOSTARTED + HFCLKAUDIO source started + 0x120 + read-write + + + EVENTS_HFCLKAUDIOSTARTED + HFCLKAUDIO source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_HFCLK192MSTARTED + HFCLK192M source started + 0x124 + read-write + + + EVENTS_HFCLK192MSTARTED + HFCLK192M source started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_HFCLKSTARTED + Publish configuration for event HFCLKSTARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event HFCLKSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LFCLKSTARTED + Publish configuration for event LFCLKSTARTED + 0x184 + read-write + + + CHIDX + DPPI channel that event LFCLKSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x19C + read-write + + + CHIDX + DPPI channel that event DONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_HFCLKAUDIOSTARTED + Publish configuration for event HFCLKAUDIOSTARTED + 0x1A0 + read-write + + + CHIDX + DPPI channel that event HFCLKAUDIOSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_HFCLK192MSTARTED + Publish configuration for event HFCLK192MSTARTED + 0x1A4 + read-write + + + CHIDX + DPPI channel that event HFCLK192MSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + HFCLKSTARTED + Enable or disable interrupt for event HFCLKSTARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LFCLKSTARTED + Enable or disable interrupt for event LFCLKSTARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + HFCLKAUDIOSTARTED + Enable or disable interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + HFCLK192MSTARTED + Enable or disable interrupt for event HFCLK192MSTARTED + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + HFCLKAUDIOSTARTED + Write '1' to enable interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + HFCLK192MSTARTED + Write '1' to enable interrupt for event HFCLK192MSTARTED + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + HFCLKAUDIOSTARTED + Write '1' to disable interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + HFCLK192MSTARTED + Write '1' to disable interrupt for event HFCLK192MSTARTED + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + HFCLKSTARTED + Read pending status of interrupt for event HFCLKSTARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + LFCLKSTARTED + Read pending status of interrupt for event LFCLKSTARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + DONE + Read pending status of interrupt for event DONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + HFCLKAUDIOSTARTED + Read pending status of interrupt for event HFCLKAUDIOSTARTED + 8 + 8 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + HFCLK192MSTARTED + Read pending status of interrupt for event HFCLK192MSTARTED + 9 + 9 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + 0x40C + read-only + + + SRC + Active clock source + 0 + 0 + + + HFINT + Clock source: HFINT - 128 MHz on-chip oscillator + 0 + + + HFXO + Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator + 1 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + 0x418 + read-only + + + SRC + Active clock source + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + + + HFCLKAUDIORUN + Status indicating that HFCLKAUDIOSTART task has been triggered + 0x450 + read-only + + + STATUS + HFCLKAUDIOSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKAUDIOSTAT + Status indicating which HFCLKAUDIO source is running + 0x454 + read-only + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + HFCLKAUDIO state + 16 + 16 + + + NotRunning + HFCLKAUDIO not running + 0 + + + Running + HFCLKAUDIO running + 1 + + + + + + + HFCLK192MRUN + Status indicating that HFCLK192MSTART task has been triggered + 0x458 + read-only + + + STATUS + HFCLK192MSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLK192MSTAT + Status indicating which HFCLK192M source is running + 0x45C + read-only + + + SRC + Active clock source + 0 + 0 + + + HFINT + Clock source: HFINT - on-chip oscillator + 0 + + + HFXO + Clock source: HFXO - derived from external 32 MHz crystal oscillator + 1 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0 + + + Running + Oscillator is always running + 1 + + + + + STATE + HFCLK192M state + 16 + 16 + + + NotRunning + HFCLK192M not running + 0 + + + Running + HFCLK192M running + 1 + + + + + + + HFCLKSRC + Clock source for HFCLK128M/HFCLK64M + 0x514 + read-write + 0x00000001 + + + SRC + Select which HFCLK source is started by the HFCLKSTART task + 0 + 0 + + + HFINT + HFCLKSTART task starts HFINT oscillator + 0 + + + HFXO + HFCLKSTART task starts HFXO oscillator + 1 + + + + + + + LFCLKSRC + Clock source for LFCLK + 0x518 + read-write + 0x00000001 + + + SRC + Select which LFCLK source is started by the LFCLKSTART task + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 3 + + + + + + + HFCLKCTRL + HFCLK128M frequency configuration + 0x558 + read-write + 0x00000001 + + + HCLK + High frequency clock HCLK + 0 + 1 + + + Div1 + Divide HFCLK by 1 + 0 + + + Div2 + Divide HFCLK by 2 + 1 + + + + + + + HFCLKAUDIO + Unspecified + CLOCK_HFCLKAUDIO + read-write + 0x55C + + FREQUENCY + Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands + 0x000 + read-write + 0x00009BAE + + + FREQUENCY + Frequency 0: 10.666 MHz 65535: 13.333 MHz + 0 + 15 + + + + + + HFCLKALWAYSRUN + Automatic or manual control of HFCLK128M/HFCLK64M + 0x570 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + LFCLKALWAYSRUN + Automatic or manual control of LFCLK + 0x574 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + HFCLKAUDIOALWAYSRUN + Automatic or manual control of HFCLKAUDIO + 0x57C + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + HFCLK192MSRC + Clock source for HFCLK192M + 0x580 + read-write + 0x00000001 + + + SRC + Select which HFCLK192M source is started by the HFCLK192MSTART task + 0 + 0 + + + HFINT + HFCLK192MSTART task starts HFINT oscillator + 0 + + + HFXO + HFCLK192MSTART task starts HFXO oscillator + 1 + + + + + + + HFCLK192MALWAYSRUN + Automatic or manual control of HFCLK192M + 0x584 + read-write + + + ALWAYSRUN + Ensure clock is always running + 0 + 0 + + + Automatic + Use automatic clock control + 0 + + + AlwaysRun + Ensure clock is always running + 1 + + + + + + + HFCLK192MCTRL + HFCLK192M frequency configuration + 0x5B8 + read-write + 0x00000002 + + + HCLK192M + High frequency clock HCLK192M + 0 + 1 + + + Div1 + Divide HFCLK192M by 1 + 0 + + + Div2 + Divide HFCLK192M by 2 + 1 + + + Div4 + Divide HFCLK192M by 4 + 2 + + + + + + + + + POWER_NS + Power control 0 + 0x40005000 + CLOCK_NS + POWER + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x78 + write-only + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable Low-Power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable Low-Power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_CONSTLAT + Subscribe configuration for task CONSTLAT + 0xF8 + read-write + + + CHIDX + DPPI channel that task CONSTLAT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LOWPWR + Subscribe configuration for task LOWPWR + 0xFC + read-write + + + CHIDX + DPPI channel that task LOWPWR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_POFWARN + Publish configuration for event POFWARN + 0x188 + read-write + + + CHIDX + DPPI channel that event POFWARN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPENTER + Publish configuration for event SLEEPENTER + 0x194 + read-write + + + CHIDX + DPPI channel that event SLEEPENTER will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPEXIT + Publish configuration for event SLEEPEXIT + 0x198 + read-write + + + CHIDX + DPPI channel that event SLEEPEXIT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + POFWARN + Enable or disable interrupt for event POFWARN + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPENTER + Enable or disable interrupt for event SLEEPENTER + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPEXIT + Enable or disable interrupt for event SLEEPEXIT + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x2 + 0x4 + GPREGRET[%s] + Description collection: General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + + + RESET_NS + Reset control 0 + 0x40005000 + CLOCK_NS + RESET + + + + 0 + 0x1000 + registers + + RESET + 0x20 + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG0 + Reset from application watchdog timer 0 detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + CTRLAP + Reset from application CTRL-AP detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from application soft reset detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from application CPU lockup detected + 4 + 4 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO + 5 + 5 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP + 6 + 6 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode + 7 + 7 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset after wakeup from System OFF mode due to NFC field being detected + 24 + 24 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG1 + Reset from application watchdog timer 1 detected + 25 + 25 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + VBUS + Reset after wakeup from System OFF mode due to VBUS rising into valid range + 26 + 26 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + NETWORK + ULP network core control + RESET_NETWORK + read-write + 0x610 + + FORCEOFF + Force network core off + 0x004 + read-write + 0x00000001 + + + FORCEOFF + Force network core off + 0 + 0 + + + Release + Release Force-OFF + 0 + + + Hold + Hold Force-OFF + 1 + + + + + + + + + + CLOCK_S + Clock management 1 + 0x50005000 + + + + CLOCK_POWER + 5 + + + + POWER_S + Power control 1 + 0x50005000 + CLOCK_S + + + + CLOCK_POWER + 5 + + + + RESET_S + Reset control 1 + 0x50005000 + CLOCK_S + + + + + CTRLAP_NS + Control access port 0 + 0x40006000 + CTRLAPPERI + + + + 0 + 0x1000 + registers + + CTRLAPPERI + 0x20 + + + MAILBOX + Unspecified + CTRLAPPERI_MAILBOX + read-write + 0x400 + + RXDATA + Data sent from the debugger to the CPU. + 0x000 + read-only + 0x00000000 + + + RXDATA + Data received from debugger + 0 + 31 + + + + + RXSTATUS + This register shows a status that indicates if data sent from the debugger to the CPU has been read. + 0x004 + read-only + 0x00000000 + + + RXSTATUS + Status of data in register RXDATA + 0 + 0 + + + NoDataPending + No data pending in register RXDATA + 0 + + + DataPending + Data pending in register RXDATA + 1 + + + + + + + TXDATA + Data sent from the CPU to the debugger. + 0x80 + read-write + 0x00000000 + + + TXDATA + Data sent to debugger + 0 + 31 + + + + + TXSTATUS + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. + 0x84 + read-only + 0x00000000 + + + TXSTATUS + Status of data in register TXDATA + 0 + 0 + + + NoDataPending + No data pending in register TXDATA + 0 + + + DataPending + Data pending in register TXDATA + 1 + + + + + + + + ERASEPROTECT + Unspecified + CTRLAPPERI_ERASEPROTECT + read-write + 0x500 + + LOCK + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeonce + 0x00000000 + + + LOCK + Lock ERASEPROTECT.DISABLE register from being written until next reset + 0 + 0 + + + Unlocked + Register ERASEPROTECT.DISABLE is writeable + 0 + + + Locked + Register ERASEPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the ERASEPROTECT register and performs an ERASEALL operation. + 0x004 + read-writeonce + 0x00000000 + + + KEY + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + 0 + 31 + + + + + + APPROTECT + Unspecified + CTRLAPPERI_APPROTECT + read-write + 0x540 + + LOCK + This register locks the APPROTECT.DISABLE register from being written to until next reset. + 0x000 + read-writeonce + 0x00000000 + + + LOCK + Lock the APPROTECT.DISABLE register from being written to until next reset + 0 + 0 + + + Unlocked + Register APPROTECT.DISABLE is writeable + 0 + + + Locked + Register APPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the APPROTECT register and enables debug access to non-secure mode. + 0x004 + read-write + 0x00000000 + + + KEY + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. + 0 + 31 + + + + + + SECUREAPPROTECT + Unspecified + CTRLAPPERI_SECUREAPPROTECT + read-write + 0x548 + + LOCK + This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeonce + 0x00000000 + + + LOCK + Lock register SECUREAPPROTECT.DISABLE from being written until next reset + 0 + 0 + + + Unlocked + Register SECUREAPPROTECT.DISABLE is writeable + 0 + + + Locked + Register SECUREAPPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the SECUREAPPROTECT register and enables debug access to secure mode. + 0x004 + read-write + 0x00000000 + + + KEY + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled. + 0 + 31 + + + + + + STATUS + Status bits for CTRL-AP peripheral. + 0x600 + read-only + 0x00000000 + + + UICRAPPROTECT + Status bit for UICR part of access port protection at last reset. + 0 + 0 + + + Enabled + APPROTECT was enabled in UICR + 0 + + + Disabled + APPROTECT wasdisabled in UICR + 1 + + + + + UICRSECUREAPPROTECT + Status bit for UICR part of secure access port protection at last reset. + 1 + 1 + + + Enabled + SECUREAPPROTECT was enabled in UICR + 0 + + + Disabled + SECUREAPPROTECT was disabled in UICR + 1 + + + + + DBGIFACEMODE + Status bit for device debug interface mode + 2 + 2 + + + Disabled + No debugger attached + 0 + + + Enabled + Debugger is attached and device is in debug interface mode + 1 + + + + + + + + + CTRLAP_S + Control access port 1 + 0x50006000 + + + + + SPIM0_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x40008000 + SPIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x090 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x198 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + 0x400 + read-write + 0x00000000 + + + TX + Stall status for EasyDMA RAM reads + 0 + 0 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + RX + Stall status for EasyDMA RAM writes + 1 + 1 + + + NOSTALL + No stall + 0 + + + STALL + A stall has occurred + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + M16 + 16 Mbps + 0x0A000000 + + + M32 + 32 Mbps + 0x14000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + + + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 + + + CSNPOL + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0 + + + HIGH + Active high (idle state low) + 1 + + + + + + + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DCXCNT + DCX configuration + 0x570 + read-write + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0_NS + SPI Slave 0 + 0x40008000 + SPIM0_NS + SPIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x0A4 + read-write + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x0A8 + read-write + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x1A8 + read-write + + + CHIDX + DPPI channel that event ACQUIRED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWIM0_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1C8 + read-write + + + CHIDX + DPPI channel that event SUSPENDED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1DC + read-write + + + CHIDX + DPPI channel that event LASTRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1E0 + read-write + + + CHIDX + DPPI channel that event LASTTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + K1000 + 1000 kbps + 0x0FF00000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0B0 + read-write + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0B4 + read-write + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1E4 + read-write + + + CHIDX + DPPI channel that event WRITE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1E8 + read-write + + + CHIDX + DPPI channel that event READ will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + UARTE0_NS + UART with EasyDMA 0 + 0x40008000 + SPIM0_NS + UARTE + + + + 0 + 0x1000 + registers + + + SERIAL0 + 8 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPRX + Subscribe configuration for task STOPRX + 0x084 + read-write + + + CHIDX + DPPI channel that task STOPRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPTX + Subscribe configuration for task STOPTX + 0x08C + read-write + + + CHIDX + DPPI channel that task STOPTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x0AC + read-write + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + + + CHIDX + DPPI channel that event CTS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + + + CHIDX + DPPI channel that event NCTS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x188 + read-write + + + CHIDX + DPPI channel that event RXDRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x19C + read-write + + + CHIDX + DPPI channel that event TXDRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1C4 + read-write + + + CHIDX + DPPI channel that event RXTO will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1D8 + read-write + + + CHIDX + DPPI channel that event TXSTOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0 + + + Odd + Odd parity + 1 + + + + + + + + + SPIM0_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x50008000 + + + + SERIAL0 + 8 + + + + SPIS0_S + SPI Slave 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + TWIM0_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + TWIS0_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + UARTE0_S + UART with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SERIAL0 + 8 + + + + SPIM1_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x40009000 + + + + SERIAL1 + 9 + + + + SPIS1_NS + SPI Slave 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + TWIM1_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + TWIS1_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + UARTE1_NS + UART with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SERIAL1 + 9 + + + + SPIM1_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x50009000 + + + + SERIAL1 + 9 + + + + SPIS1_S + SPI Slave 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + TWIM1_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + TWIS1_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + UARTE1_S + UART with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SERIAL1 + 9 + + + + SPIM4_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x4000A000 + + + + SPIM4 + 10 + + + + SPIM4_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x5000A000 + + + + SPIM4 + 10 + + + + SPIM2_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x4000B000 + + + + SERIAL2 + 11 + + + + SPIS2_NS + SPI Slave 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + TWIM2_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + TWIS2_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + UARTE2_NS + UART with EasyDMA 4 + 0x4000B000 + SPIM2_NS + + + + SERIAL2 + 11 + + + + SPIM2_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x5000B000 + + + + SERIAL2 + 11 + + + + SPIS2_S + SPI Slave 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + TWIM2_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + TWIS2_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + UARTE2_S + UART with EasyDMA 5 + 0x5000B000 + SPIM2_S + + + + SERIAL2 + 11 + + + + SPIM3_NS + Serial Peripheral Interface Master with EasyDMA 8 + 0x4000C000 + + + + SERIAL3 + 12 + + + + SPIS3_NS + SPI Slave 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + TWIM3_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + TWIS3_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + UARTE3_NS + UART with EasyDMA 6 + 0x4000C000 + SPIM3_NS + + + + SERIAL3 + 12 + + + + SPIM3_S + Serial Peripheral Interface Master with EasyDMA 9 + 0x5000C000 + + + + SERIAL3 + 12 + + + + SPIS3_S + SPI Slave 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + TWIM3_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + TWIS3_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + UARTE3_S + UART with EasyDMA 7 + 0x5000C000 + SPIM3_S + + + + SERIAL3 + 12 + + + + GPIOTE0_S + GPIO Tasks and Events 0 + 0x5000D000 + GPIOTE + + + + 0 + 0x1000 + registers + + + GPIOTE0 + 13 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event IN[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PORT + Publish configuration for event PORT + 0x1FC + read-write + + + CHIDX + DPPI channel that event PORT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section + 0 + + + LowLatency + Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC_NS + Analog to Digital Converter 0 + 0x4000E000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 14 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any ongoing conversion + 0x008 + write-only + + + TASKS_STOP + Stop the ADC and terminate any ongoing conversion + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM + 0x10C + read-write + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + + + CHIDX + DPPI channel that event DONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + + + CHIDX + DPPI channel that event RESULTDONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No ongoing conversion. + 0 + + + Busy + ADC is busy. Single conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0xD + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0xD + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single-ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value; sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + SAADC_S + Analog to Digital Converter 1 + 0x5000E000 + + + + SAADC + 14 + + + + TIMER0_NS + Timer/Counter 0 + 0x4000F000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER0 + 15 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x6 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x6 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0 + + + Enable + Enable one-shot operation + 1 + + + + + + + + + TIMER0_S + Timer/Counter 1 + 0x5000F000 + + + + TIMER0 + 15 + + + + TIMER1_NS + Timer/Counter 2 + 0x40010000 + + + + TIMER1 + 16 + + + + TIMER1_S + Timer/Counter 3 + 0x50010000 + + + + TIMER1 + 16 + + + + TIMER2_NS + Timer/Counter 4 + 0x40011000 + + + + TIMER2 + 17 + + + + TIMER2_S + Timer/Counter 5 + 0x50011000 + + + + TIMER2 + 17 + + + + RTC0_NS + Real-time counter 0 + 0x40014000 + RTC + + + + 0 + 0x1000 + registers + + + RTC0 + 20 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x4 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x4 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + + + CHIDX + DPPI channel that event TICK will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + + + CHIDX + DPPI channel that event OVRFLW will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x4 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + RTC0_S + Real-time counter 1 + 0x50014000 + + + + RTC0 + 20 + + + + RTC1_NS + Real-time counter 2 + 0x40015000 + + + + RTC1 + 21 + + + + RTC1_S + Real-time counter 3 + 0x50015000 + + + + RTC1 + 21 + + + + DPPIC_NS + Distributed programmable peripheral interconnect controller 0 + 0x40017000 + DPPIC + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + 6 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing 0 has no effect. + 24 + 24 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing 0 has no effect. + 24 + 24 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing 0 has no effect. + 25 + 25 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing 0 has no effect. + 26 + 26 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing 0 has no effect. + 27 + 27 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing 0 has no effect. + 28 + 28 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing 0 has no effect. + 29 + 29 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing 0 has no effect. + 30 + 30 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing 0 has no effect. + 31 + 31 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + + + DPPIC_S + Distributed programmable peripheral interconnect controller 1 + 0x50017000 + + + + + WDT0_NS + Watchdog Timer 0 + 0x40018000 + WDT + + + + 0 + 0x1000 + registers + + + WDT0 + 24 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + + + CHIDX + DPPI channel that event TIMEOUT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0 + + + Run + Keep WDT running while the CPU is sleeping + 1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0 + + + Enable + Allow stopping WDT + 1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + WDT0_S + Watchdog Timer 1 + 0x50018000 + + + + WDT0 + 24 + + + + WDT1_NS + Watchdog Timer 2 + 0x40019000 + + + + WDT1 + 25 + + + + WDT1_S + Watchdog Timer 3 + 0x50019000 + + + + WDT1 + 25 + + + + COMP_NS + Comparator 0 + 0x4001A000 + COMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 26 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + + + CHIDX + DPPI channel that event DOWN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + + + CHIDX + DPPI channel that event UP will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + + + CHIDX + DPPI channel that event CROSS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF + 5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + + + ISOURCE + Comparator hysteresis + 0 + 1 + + + Off + Current source disabled + 0 + + + Ien2mA5 + Current source enabled (+/- 2.5 uA) + 1 + + + Ien5mA + Current source enabled (+/- 5 uA) + 2 + + + Ien10mA + Current source enabled (+/- 10 uA) + 3 + + + + + + + + + LPCOMP_NS + Low-power comparator 0 + 0x4001A000 + COMP_NS + LPCOMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 26 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + + + CHIDX + DPPI channel that event DOWN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + + + CHIDX + DPPI channel that event UP will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + + + CHIDX + DPPI channel that event CROSS will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 0 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0 + + + Up + Generate ANADETECT on upward crossing only + 1 + + + Down + Generate ANADETECT on downward crossing only + 2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0 + + + Enabled + Comparator hysteresis enabled + 1 + + + + + + + + + COMP_S + Comparator 1 + 0x5001A000 + + + + COMP_LPCOMP + 26 + + + + LPCOMP_S + Low-power comparator 1 + 0x5001A000 + COMP_S + + + + COMP_LPCOMP + 26 + + + + EGU0_NS + Event generator unit 0 + 0x4001B000 + EGU + + + + 0 + 0x1000 + registers + + + EGU0 + 27 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + EGU0_S + Event generator unit 1 + 0x5001B000 + + + + EGU0 + 27 + + + + EGU1_NS + Event generator unit 2 + 0x4001C000 + + + + EGU1 + 28 + + + + EGU1_S + Event generator unit 3 + 0x5001C000 + + + + EGU1 + 28 + + + + EGU2_NS + Event generator unit 4 + 0x4001D000 + + + + EGU2 + 29 + + + + EGU2_S + Event generator unit 5 + 0x5001D000 + + + + EGU2 + 29 + + + + EGU3_NS + Event generator unit 6 + 0x4001E000 + + + + EGU3 + 30 + + + + EGU3_S + Event generator unit 7 + 0x5001E000 + + + + EGU3 + 30 + + + + EGU4_NS + Event generator unit 8 + 0x4001F000 + + + + EGU4 + 31 + + + + EGU4_S + Event generator unit 9 + 0x5001F000 + + + + EGU4 + 31 + + + + EGU5_NS + Event generator unit 10 + 0x40020000 + + + + EGU5 + 32 + + + + EGU5_S + Event generator unit 11 + 0x50020000 + + + + EGU5 + 32 + + + + PWM0_NS + Pulse width modulation unit 0 + 0x40021000 + PWM + + + + 0 + 0x1000 + registers + + + PWM0 + 33 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x2 + 0x4 + SUBSCRIBE_SEQSTART[%s] + Description collection: Subscribe configuration for task SEQSTART[n] + 0x088 + read-write + + + CHIDX + DPPI channel that task SEQSTART[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x090 + read-write + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + + + CHIDX + DPPI channel that event SEQEND[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + + + CHIDX + DPPI channel that event LOOPSDONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PWM0_S + Pulse width modulation unit 1 + 0x50021000 + + + + PWM0 + 33 + + + + PWM1_NS + Pulse width modulation unit 2 + 0x40022000 + + + + PWM1 + 34 + + + + PWM1_S + Pulse width modulation unit 3 + 0x50022000 + + + + PWM1 + 34 + + + + PWM2_NS + Pulse width modulation unit 4 + 0x40023000 + + + + PWM2 + 35 + + + + PWM2_S + Pulse width modulation unit 5 + 0x50023000 + + + + PWM2 + 35 + + + + PWM3_NS + Pulse width modulation unit 6 + 0x40024000 + + + + PWM3 + 36 + + + + PWM3_S + Pulse width modulation unit 7 + 0x50024000 + + + + PWM3 + 36 + + + + PDM0_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x40026000 + PDM + + + + 0 + 0x1000 + registers + + + PDM0 + 38 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + + + CHIDX + DPPI channel that event END will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration. Enumerations are deprecated, use + PDMCLKCTRL equation to find the register value. The 12 least significant bits of the + register are ignored and shall be set to zero. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + MCLKCONFIG + Master clock generator configuration + 0x54C + read-write + 0x00000000 + + + SRC + Master clock source selection + 0 + 0 + + + PCLK32M + 32 MHz peripheral clock + 0 + + + ACLK + Audio PLL clock + 1 + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + PDM0_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x50026000 + + + + PDM0 + 38 + + + + I2S0_NS + Inter-IC Sound 0 + 0x40028000 + I2S + + + + 0 + 0x1000 + registers + + + I2S0 + 40 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0x11C + read-write + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + + + CHIDX + DPPI channel that event RXPTRUPD will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + + + CHIDX + DPPI channel that event TXPTRUPD will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x19C + read-write + + + CHIDX + DPPI channel that event FRAMESTART will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FRAMESTART + Enable or disable interrupt for event FRAMESTART + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + I2S clock generator control + 0x010 + read-write + 0x20000000 + + + MCKFREQ + I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample and half-frame width + 0 + 2 + + + 8Bit + 8 bit sample. + 0 + + + 16Bit + 16 bit sample. + 1 + + + 24Bit + 24 bit sample. + 2 + + + 32Bit + 32 bit sample. + 3 + + + 8BitIn16 + 8 bit sample in a 16-bit half-frame. + 4 + + + 8BitIn32 + 8 bit sample in a 32-bit half-frame. + 5 + + + 16BitIn32 + 16 bit sample in a 32-bit half-frame. + 6 + + + 24BitIn32 + 24 bit sample in a 32-bit half-frame. + 7 + + + + + + + ALIGN + Alignment of sample within a frame + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + CLKCONFIG + Clock source selection for the I2S module + 0x028 + read-write + 0x00000000 + + + CLKSRC + Clock source selection + 0 + 0 + + + PCLK32M + 32MHz peripheral clock + 0 + + + ACLK + Audio PLL clock + 1 + + + + + BYPASS + Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. + 8 + 8 + + + Disable + Disable bypass + 0 + + + Enable + Enable bypass + 1 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + I2S0_S + Inter-IC Sound 1 + 0x50028000 + + + + I2S0 + 40 + + + + IPC_NS + Interprocessor communication 0 + 0x4002A000 + IPC + + + + 0 + 0x1000 + registers + + + IPC + 42 + + IPC + 0x20 + + + 0x10 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] + 0x000 + write-only + + + TASKS_SEND + Trigger events on IPC channel enabled in SEND_CNF[n] + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0x100 + read-write + + + EVENTS_RECEIVE + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE8 + Enable or disable interrupt for event RECEIVE[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE9 + Enable or disable interrupt for event RECEIVE[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE10 + Enable or disable interrupt for event RECEIVE[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE11 + Enable or disable interrupt for event RECEIVE[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE12 + Enable or disable interrupt for event RECEIVE[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE13 + Enable or disable interrupt for event RECEIVE[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE14 + Enable or disable interrupt for event RECEIVE[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE15 + Enable or disable interrupt for event RECEIVE[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE8 + Write '1' to enable interrupt for event RECEIVE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE9 + Write '1' to enable interrupt for event RECEIVE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE10 + Write '1' to enable interrupt for event RECEIVE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE11 + Write '1' to enable interrupt for event RECEIVE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE12 + Write '1' to enable interrupt for event RECEIVE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE13 + Write '1' to enable interrupt for event RECEIVE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE14 + Write '1' to enable interrupt for event RECEIVE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE15 + Write '1' to enable interrupt for event RECEIVE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE8 + Write '1' to disable interrupt for event RECEIVE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE9 + Write '1' to disable interrupt for event RECEIVE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE10 + Write '1' to disable interrupt for event RECEIVE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE11 + Write '1' to disable interrupt for event RECEIVE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE12 + Write '1' to disable interrupt for event RECEIVE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE13 + Write '1' to disable interrupt for event RECEIVE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE14 + Write '1' to disable interrupt for event RECEIVE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE15 + Write '1' to disable interrupt for event RECEIVE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE8 + Read pending status of interrupt for event RECEIVE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE9 + Read pending status of interrupt for event RECEIVE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE10 + Read pending status of interrupt for event RECEIVE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE11 + Read pending status of interrupt for event RECEIVE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE12 + Read pending status of interrupt for event RECEIVE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE13 + Read pending status of interrupt for event RECEIVE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE14 + Read pending status of interrupt for event RECEIVE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE15 + Read pending status of interrupt for event RECEIVE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + 0x10 + 0x4 + SEND_CNF[%s] + Description collection: Send event configuration for TASKS_SEND[n] + 0x510 + read-write + 0x00000000 + + + CHEN0 + Enable broadcasting on IPC channel 0 + 0 + 0 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN1 + Enable broadcasting on IPC channel 1 + 1 + 1 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN2 + Enable broadcasting on IPC channel 2 + 2 + 2 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN3 + Enable broadcasting on IPC channel 3 + 3 + 3 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN4 + Enable broadcasting on IPC channel 4 + 4 + 4 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN5 + Enable broadcasting on IPC channel 5 + 5 + 5 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN6 + Enable broadcasting on IPC channel 6 + 6 + 6 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN7 + Enable broadcasting on IPC channel 7 + 7 + 7 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN8 + Enable broadcasting on IPC channel 8 + 8 + 8 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN9 + Enable broadcasting on IPC channel 9 + 9 + 9 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN10 + Enable broadcasting on IPC channel 10 + 10 + 10 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN11 + Enable broadcasting on IPC channel 11 + 11 + 11 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN12 + Enable broadcasting on IPC channel 12 + 12 + 12 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN13 + Enable broadcasting on IPC channel 13 + 13 + 13 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN14 + Enable broadcasting on IPC channel 14 + 14 + 14 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN15 + Enable broadcasting on IPC channel 15 + 15 + 15 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + + + 0x10 + 0x4 + RECEIVE_CNF[%s] + Description collection: Receive event configuration for EVENTS_RECEIVE[n] + 0x590 + read-write + 0x00000000 + + + CHEN0 + Enable subscription to IPC channel 0 + 0 + 0 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN1 + Enable subscription to IPC channel 1 + 1 + 1 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN2 + Enable subscription to IPC channel 2 + 2 + 2 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN3 + Enable subscription to IPC channel 3 + 3 + 3 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN4 + Enable subscription to IPC channel 4 + 4 + 4 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN5 + Enable subscription to IPC channel 5 + 5 + 5 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN6 + Enable subscription to IPC channel 6 + 6 + 6 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN7 + Enable subscription to IPC channel 7 + 7 + 7 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN8 + Enable subscription to IPC channel 8 + 8 + 8 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN9 + Enable subscription to IPC channel 9 + 9 + 9 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN10 + Enable subscription to IPC channel 10 + 10 + 10 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN11 + Enable subscription to IPC channel 11 + 11 + 11 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN12 + Enable subscription to IPC channel 12 + 12 + 12 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN13 + Enable subscription to IPC channel 13 + 13 + 13 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN14 + Enable subscription to IPC channel 14 + 14 + 14 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN15 + Enable subscription to IPC channel 15 + 15 + 15 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + + + 0x2 + 0x4 + GPMEM[%s] + Description collection: General purpose memory + 0x610 + read-write + 0x00000000 + + + GPMEM + General purpose memory + 0 + 31 + + + + + + + IPC_S + Interprocessor communication 1 + 0x5002A000 + + + + IPC + 42 + + + + QSPI_NS + External flash interface 0 + 0x4002B000 + QSPI + + + + 0 + 0x1000 + registers + + + QSPI + 43 + + QSPI + 0x20 + + + TASKS_ACTIVATE + Activate QSPI interface + 0x000 + write-only + + + TASKS_ACTIVATE + Activate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0x004 + write-only + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0x008 + write-only + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ERASESTART + Start external flash memory erase operation + 0x00C + write-only + + + TASKS_ERASESTART + Start external flash memory erase operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0x010 + write-only + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACTIVATE + Subscribe configuration for task ACTIVATE + 0x080 + read-write + + + CHIDX + DPPI channel that task ACTIVATE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_READSTART + Subscribe configuration for task READSTART + 0x084 + read-write + + + CHIDX + DPPI channel that task READSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_WRITESTART + Subscribe configuration for task WRITESTART + 0x088 + read-write + + + CHIDX + DPPI channel that task WRITESTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_ERASESTART + Subscribe configuration for task ERASESTART + 0x08C + read-write + + + CHIDX + DPPI channel that task ERASESTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DEACTIVATE + Subscribe configuration for task DEACTIVATE + 0x090 + read-write + + + CHIDX + DPPI channel that task DEACTIVATE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. + 0x100 + read-write + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable QSPI peripheral and acquire the pins selected in PSELn registers + 0x500 + read-write + + + ENABLE + Enable or disable QSPI + 0 + 0 + + + Disabled + Disable QSPI + 0 + + + Enabled + Enable QSPI + 1 + + + + + + + READ + Unspecified + QSPI_READ + read-write + 0x504 + + SRC + Flash memory source address + 0x000 + read-write + + + SRC + Word-aligned flash memory source address. + 0 + 31 + + + + + DST + RAM destination address + 0x004 + read-write + + + DST + Word-aligned RAM destination address. + 0 + 31 + + + + + CNT + Read transfer length + 0x008 + read-write + + + CNT + Read transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 20 + + + + + + WRITE + Unspecified + QSPI_WRITE + read-write + 0x510 + + DST + Flash destination address + 0x000 + read-write + + + DST + Word-aligned flash destination address. + 0 + 31 + + + + + SRC + RAM source address + 0x004 + read-write + + + SRC + Word-aligned RAM source address. + 0 + 31 + + + + + CNT + Write transfer length + 0x008 + read-write + + + CNT + Write transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 20 + + + + + + ERASE + Unspecified + QSPI_ERASE + read-write + 0x51C + + PTR + Start address of flash block to be erased + 0x000 + read-write + + + PTR + Word-aligned start address of block to be erased. + 0 + 31 + + + + + LEN + Size of block to be erased. + 0x004 + read-write + + + LEN + LEN + 0 + 1 + + + 4KB + Erase 4 kB block (flash command 0x20) + 0 + + + 64KB + Erase 64 kB block (flash command 0xD8) + 1 + + + All + Erase all (flash command 0xC7) + 2 + + + + + + + + PSEL + Unspecified + QSPI_PSEL + read-write + 0x524 + + SCK + Pin select for serial clock SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for chip select signal CSN. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO0 + Pin select for serial data MOSI/IO0. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO1 + Pin select for serial data MISO/IO1. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO2 + Pin select for serial data WP/IO2. + 0x014 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO3 + Pin select for serial data HOLD/IO3. + 0x018 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. + 0x540 + read-write + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + 0 + 31 + + + + + IFCONFIG0 + Interface configuration. + 0x544 + read-write + + + READOC + Configure number of data lines and opcode used for reading. + 0 + 2 + + + FASTREAD + Single data line SPI. FAST_READ (opcode 0x0B). + 0 + + + READ2O + Dual data line SPI. READ2O (opcode 0x3B). + 1 + + + READ2IO + Dual data line SPI. READ2IO (opcode 0xBB). + 2 + + + READ4O + Quad data line SPI. READ4O (opcode 0x6B). + 3 + + + READ4IO + Quad data line SPI. READ4IO (opcode 0xEB). + 4 + + + + + WRITEOC + Configure number of data lines and opcode used for writing. + 3 + 5 + + + PP + Single data line SPI. PP (opcode 0x02). + 0 + + + PP2O + Dual data line SPI. PP2O (opcode 0xA2). + 1 + + + PP4O + Quad data line SPI. PP4O (opcode 0x32). + 2 + + + PP4IO + Quad data line SPI. PP4IO (opcode 0x38). + 3 + + + + + ADDRMODE + Addressing mode. + 6 + 6 + + + 24BIT + 24-bit addressing. + 0 + + + 32BIT + 32-bit addressing. + 1 + + + + + DPMENABLE + Enable deep power-down mode (DPM) feature. + 7 + 7 + + + Disable + Disable DPM feature. + 0 + + + Enable + Enable DPM feature. + 1 + + + + + PPSIZE + Page size for commands PP, PP2O, PP4O and PP4IO. + 12 + 12 + + + 256Bytes + 256 bytes. + 0 + + + 512Bytes + 512 bytes. + 1 + + + + + + + XIPEN + Enable Execute in Place operation. + 0x54C + read-write + 0x00000001 + + + XIPEN + Enable XIP AHB Slave interface and access to XIP memory range + 0 + 0 + + + Disable + Disable XIP interface + 0 + + + Enable + Enable XIP interface + 1 + + + + + + + XIP_ENC + Unspecified + QSPI_XIP_ENC + read-write + 0x560 + + KEY0 + Bits 31:0 of XIP AES KEY + 0x000 + write-only + 0x00000000 + + + KEY0 + Bits 31:0 of XIP AES KEY + 0 + 31 + + + + + KEY1 + Bits 63:32 of XIP AES KEY + 0x004 + write-only + 0x00000000 + + + KEY1 + Bits 63:32 of XIP AES KEY + 0 + 31 + + + + + KEY2 + Bits 95:64 of XIP AES KEY + 0x008 + write-only + 0x00000000 + + + KEY2 + Bits 95:64 of XIP AES KEY + 0 + 31 + + + + + KEY3 + Bits 127:96 of XIP AES KEY + 0x00C + write-only + 0x00000000 + + + KEY3 + Bits 127:96 of XIP AES KEY + 0 + 31 + + + + + NONCE0 + Bits 31:0 of XIP NONCE + 0x010 + write-only + 0x00000000 + + + NONCE0 + Bits 31:0 of XIP NONCE + 0 + 31 + + + + + NONCE1 + Bits 63:32 of XIP NONCE + 0x014 + write-only + 0x00000000 + + + NONCE1 + Bits 63:32 of XIP NONCE + 0 + 31 + + + + + NONCE2 + Bits 95:64 of XIP NONCE + 0x018 + write-only + 0x00000000 + + + NONCE2 + Bits 95:64 of XIP NONCE + 0 + 31 + + + + + ENABLE + Enable stream cipher for XIP + 0x01C + read-write + + + ENABLE + Enable or disable stream cipher for XIP + 0 + 0 + + + Disabled + Disable stream cipher for QSPI XIP + 0 + + + Enabled + Enable stream cipher for QSPI XIP + 1 + + + + + + + + DMA_ENC + Unspecified + QSPI_DMA_ENC + read-write + 0x580 + + KEY0 + Bits 31:0 of DMA AES KEY + 0x000 + write-only + 0x00000000 + + + KEY0 + Bits 31:0 of DMA AES KEY + 0 + 31 + + + + + KEY1 + Bits 63:32 of DMA AES KEY + 0x004 + write-only + 0x00000000 + + + KEY1 + Bits 63:32 of DMA AES KEY + 0 + 31 + + + + + KEY2 + Bits 95:64 of DMA AES KEY + 0x008 + write-only + 0x00000000 + + + KEY2 + Bits 95:64 of DMA AES KEY + 0 + 31 + + + + + KEY3 + Bits 127:96 of DMA AES KEY + 0x00C + write-only + 0x00000000 + + + KEY3 + Bits 127:96 of DMA AES KEY + 0 + 31 + + + + + NONCE0 + Bits 31:0 of DMA NONCE + 0x010 + write-only + 0x00000000 + + + NONCE0 + Bits 31:0 of DMA NONCE + 0 + 31 + + + + + NONCE1 + Bits 63:32 of DMA NONCE + 0x014 + write-only + 0x00000000 + + + NONCE1 + Bits 63:32 of DMA NONCE + 0 + 31 + + + + + NONCE2 + Bits 95:64 of DMA NONCE + 0x018 + write-only + 0x00000000 + + + NONCE2 + Bits 95:64 of DMA NONCE + 0 + 31 + + + + + ENABLE + Enable stream cipher for EasyDMA + 0x01C + read-write + + + ENABLE + Enable or disable stream cipher for EasyDMA + 0 + 0 + + + Disabled + Disable stream cipher for QSPI EasyDMA + 0 + + + Enabled + Enable stream cipher for QSPI EasyDMA + 1 + + + + + + + + IFCONFIG1 + Interface configuration. + 0x600 + read-write + 0x00040480 + + + SCKDELAY + Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). + 0 + 7 + + + DPMEN + Enter/exit deep power-down mode (DPM) for external flash memory. + 24 + 24 + + + Exit + Exit DPM. + 0 + + + Enter + Enter DPM. + 1 + + + + + SPIMODE + Select SPI mode. + 25 + 25 + + + MODE0 + Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). + 0 + + + MODE3 + Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). + 1 + + + + + SCKFREQ + SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). + 28 + 31 + + + + + STATUS + Status register. + 0x604 + read-only + + + DPM + Deep power-down mode (DPM) status of external flash. + 2 + 2 + + + Disabled + External flash is not in DPM. + 0 + + + Enabled + External flash is in DPM. + 1 + + + + + READY + Ready status. + 3 + 3 + + + READY + QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + 1 + + + BUSY + QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. + 0 + + + + + SREG + Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. + 24 + 31 + + + + + DPMDUR + Set the duration required to enter/exit deep power-down mode (DPM). + 0x614 + read-write + 0xFFFFFFFF + + + ENTER + Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns + 0 + 15 + + + EXIT + Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns. + 16 + 31 + + + + + ADDRCONF + Extended address configuration. + 0x624 + read-write + 0x000000B7 + + + OPCODE + Opcode that enters the 32-bit addressing mode. + 0 + 7 + + + BYTE0 + Byte 0 following opcode. + 8 + 15 + + + BYTE1 + Byte 1 following byte 0. + 16 + 23 + + + MODE + Extended addressing mode. + 24 + 25 + + + NoInstr + Do not send any instruction. + 0 + + + Opcode + Send opcode. + 1 + + + OpByte0 + Send opcode, BYTE0. + 2 + + + All + Send opcode, BYTE0, BYTE1. + 3 + + + + + WIPWAIT + Wait for write complete before sending command. + 26 + 26 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 27 + 27 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + + + CINSTRCONF + Custom instruction configuration register. + 0x634 + read-write + 0x00002000 + + + OPCODE + Opcode of Custom instruction. + 0 + 7 + + + LENGTH + Length of custom instruction in number of bytes. + 8 + 11 + + + 1B + Send opcode only. + 1 + + + 2B + Send opcode, CINSTRDAT0.BYTE0. + 2 + + + 3B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. + 3 + + + 4B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. + 4 + + + 5B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. + 5 + + + 6B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. + 6 + + + 7B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. + 7 + + + 8B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. + 8 + + + 9B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. + 9 + + + + + LIO2 + Level of the IO2 pin (if connected) during transmission of custom instruction. + 12 + 12 + + + LIO3 + Level of the IO3 pin (if connected) during transmission of custom instruction. + 13 + 13 + + + WIPWAIT + Wait for write complete before sending command. + 14 + 14 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 15 + 15 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + LFEN + Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + 16 + 16 + + + Disable + Long frame mode disabled + 0 + + + Enable + Long frame mode enabled + 1 + + + + + LFSTOP + Stop (finalize) long frame transaction + 17 + 17 + + + Stop + Stop + 1 + + + + + + + CINSTRDAT0 + Custom instruction data register 0. + 0x638 + read-write + + + BYTE0 + Data byte 0 + 0 + 7 + + + BYTE1 + Data byte 1 + 8 + 15 + + + BYTE2 + Data byte 2 + 16 + 23 + + + BYTE3 + Data byte 3 + 24 + 31 + + + + + CINSTRDAT1 + Custom instruction data register 1. + 0x63C + read-write + + + BYTE4 + Data byte 4 + 0 + 7 + + + BYTE5 + Data byte 5 + 8 + 15 + + + BYTE6 + Data byte 6 + 16 + 23 + + + BYTE7 + Data byte 7 + 24 + 31 + + + + + IFTIMING + SPI interface timing. + 0x640 + read-write + 0x00000200 + + + RXDELAY + Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK. + 8 + 10 + + + + + + + QSPI_S + External flash interface 1 + 0x5002B000 + + + + QSPI + 43 + + + + NFCT_NS + NFC-A compatible radio 0 + 0x4002D000 + NFCT + + + + 0 + 0x1000 + registers + + + NFCT + 45 + + NFCT + 0x20 + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable NFCT peripheral + 0x004 + write-only + + + TASKS_DISABLE + Disable NFCT peripheral + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0x00C + write-only + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACTIVATE + Subscribe configuration for task ACTIVATE + 0x080 + read-write + + + CHIDX + DPPI channel that task ACTIVATE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DISABLE + Subscribe configuration for task DISABLE + 0x084 + read-write + + + CHIDX + DPPI channel that task DISABLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SENSE + Subscribe configuration for task SENSE + 0x088 + read-write + + + CHIDX + DPPI channel that task SENSE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x08C + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_ENABLERXDATA + Subscribe configuration for task ENABLERXDATA + 0x09C + read-write + + + CHIDX + DPPI channel that task ENABLERXDATA will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_GOIDLE + Subscribe configuration for task GOIDLE + 0x0A4 + read-write + + + CHIDX + DPPI channel that task GOIDLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_GOSLEEP + Subscribe configuration for task GOSLEEP + 0x0A8 + read-write + + + CHIDX + DPPI channel that task GOSLEEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0x100 + read-write + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + + + CHIDX + DPPI channel that event READY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FIELDDETECTED + Publish configuration for event FIELDDETECTED + 0x184 + read-write + + + CHIDX + DPPI channel that event FIELDDETECTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FIELDLOST + Publish configuration for event FIELDLOST + 0x188 + read-write + + + CHIDX + DPPI channel that event FIELDLOST will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXFRAMESTART + Publish configuration for event TXFRAMESTART + 0x18C + read-write + + + CHIDX + DPPI channel that event TXFRAMESTART will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXFRAMEEND + Publish configuration for event TXFRAMEEND + 0x190 + read-write + + + CHIDX + DPPI channel that event TXFRAMEEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXFRAMESTART + Publish configuration for event RXFRAMESTART + 0x194 + read-write + + + CHIDX + DPPI channel that event RXFRAMESTART will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXFRAMEEND + Publish configuration for event RXFRAMEEND + 0x198 + read-write + + + CHIDX + DPPI channel that event RXFRAMEEND will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x19C + read-write + + + CHIDX + DPPI channel that event ERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXERROR + Publish configuration for event RXERROR + 0x1A8 + read-write + + + CHIDX + DPPI channel that event RXERROR will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x1AC + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1B0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_AUTOCOLRESSTARTED + Publish configuration for event AUTOCOLRESSTARTED + 0x1B8 + read-write + + + CHIDX + DPPI channel that event AUTOCOLRESSTARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_COLLISION + Publish configuration for event COLLISION + 0x1C8 + read-write + + + CHIDX + DPPI channel that event COLLISION will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SELECTED + Publish configuration for event SELECTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event SELECTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS + read-write + 0x40C + + RX + Result of last incoming frame + 0x000 + read-write + oneToClear + + + CRCERROR + No valid end of frame (EoF) detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + + + NFCTAGSTATE + Current operating state of NFC tag + 0x410 + read-only + + + NFCTAGSTATE + NfcTag state + 0 + 2 + + + Disabled + Disabled or sense + 0 + + + RampUp + RampUp + 2 + + + Idle + Idle + 3 + + + Receive + Receive + 4 + + + FrameDelay + FrameDelay + 5 + + + Transmit + Transmit + 6 + + + + + + + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 + + + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. + 0 + 0 + + + Idle + State is IDLE. + 0 + + + SleepA + State is SLEEP_A. + 1 + + + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + + + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0 + + + FieldPresent + Valid field detected + 1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0 + + + Locked + Locked to field + 1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clock cycles + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clock cycles + 0 + 19 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 + read-write + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0 + 8 + + + + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0 + + + Parity + Parity is added to TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0 + + + SoF + SoF symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0 + + + SoF + SoF symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + MODULATIONCTRL + Enables the modulation output to a GPIO pin which can be connected to a second external antenna. + 0x52C + read-write + 0x00000001 + + + MODULATIONCTRL + Configuration of modulation control. + 0 + 1 + + + Invalid + Invalid, defaults to same behaviour as for Internal + 0x0 + + + Internal + Use internal modulator only + 0x1 + + + ModToGpio + Output digital modulation signal to a GPIO pin. + 0x2 + + + InternalAndModToGpio + Use internal modulator and output digital modulation signal to a GPIO pin. + 0x3 + + + + + + + MODULATIONPSEL + Pin select for Modulation control + 0x538 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 + + + NFCID1_Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 + + + + + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write + + + NFCID1_V + NFCID1 byte V + 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 + + + + + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 + read-write + + + NFCID1_S + NFCID1 byte S + 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 + + + + + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. + 0x59C + read-write + 0x00000002 + + + MODE + Enables/disables auto collision resolution + 0 + 0 + + + Enabled + Auto collision resolution enabled + 0 + + + Disabled + Auto collision resolution disabled + 1 + + + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + 2 + 2 + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + NFCT_S + NFC-A compatible radio 1 + 0x5002D000 + + + + NFCT + 45 + + + + GPIOTE1_NS + GPIO Tasks and Events 1 + 0x4002F000 + + + + GPIOTE1 + 47 + + + + MUTEX_NS + MUTEX 0 + 0x40030000 + MUTEX + + + + 0 + 0x1000 + registers + + MUTEX + 0x20 + + + 0x10 + 0x4 + MUTEX[%s] + Description collection: Mutex register + 0x400 + read-write + + + MUTEX + Mutex register n + 0 + 0 + + + Unlocked + Mutex n is in unlocked state + 0 + + + Locked + Mutex n is in locked state + 1 + + + + + + + + + MUTEX_S + MUTEX 1 + 0x50030000 + + + + + QDEC0_NS + Quadrature Decoder 0 + 0x40033000 + QDEC + + + + 0 + 0x1000 + registers + + + QDEC0 + 51 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_READCLRACC + Subscribe configuration for task READCLRACC + 0x088 + read-write + + + CHIDX + DPPI channel that task READCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RDCLRACC + Subscribe configuration for task RDCLRACC + 0x08C + read-write + + + CHIDX + DPPI channel that task RDCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RDCLRDBL + Subscribe configuration for task RDCLRDBL + 0x090 + read-write + + + CHIDX + DPPI channel that task RDCLRDBL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_SAMPLERDY + Publish configuration for event SAMPLERDY + 0x180 + read-write + + + CHIDX + DPPI channel that event SAMPLERDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_REPORTRDY + Publish configuration for event REPORTRDY + 0x184 + read-write + + + CHIDX + DPPI channel that event REPORTRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ACCOF + Publish configuration for event ACCOF + 0x188 + read-write + + + CHIDX + DPPI channel that event ACCOF will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DBLRDY + Publish configuration for event DBLRDY + 0x18C + read-write + + + CHIDX + DPPI channel that event DBLRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x190 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0 + + + 40Smpl + 40 samples/report + 1 + + + 80Smpl + 80 samples/report + 2 + + + 120Smpl + 120 samples/report + 3 + + + 160Smpl + 160 samples/report + 4 + + + 200Smpl + 200 samples/report + 5 + + + 240Smpl + 240 samples/report + 6 + + + 280Smpl + 280 samples/report + 7 + + + 1Smpl + 1 sample/report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + QDEC0_S + Quadrature Decoder 1 + 0x50033000 + + + + QDEC0 + 51 + + + + QDEC1_NS + Quadrature Decoder 2 + 0x40034000 + + + + QDEC1 + 52 + + + + QDEC1_S + Quadrature Decoder 3 + 0x50034000 + + + + QDEC1 + 52 + + + + USBD_NS + Universal serial bus device 0 + 0x40036000 + USBD + + + + 0 + 0x1000 + registers + + + USBD + 54 + + USBD + 0x20 + + + 0x8 + 0x4 + TASKS_STARTEPIN[%s] + Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0x004 + write-only + + + TASKS_STARTEPIN + Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0x024 + write-only + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_STARTEPOUT[%s] + Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0x028 + write-only + + + TASKS_STARTEPOUT + Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0x048 + write-only + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0x04C + write-only + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0x050 + write-only + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0x054 + write-only + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0x058 + write-only + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0x05C + write-only + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_STARTEPIN[%s] + Description collection: Subscribe configuration for task STARTEPIN[n] + 0x084 + read-write + + + CHIDX + DPPI channel that task STARTEPIN[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTISOIN + Subscribe configuration for task STARTISOIN + 0x0A4 + read-write + + + CHIDX + DPPI channel that task STARTISOIN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_STARTEPOUT[%s] + Description collection: Subscribe configuration for task STARTEPOUT[n] + 0x0A8 + read-write + + + CHIDX + DPPI channel that task STARTEPOUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTISOOUT + Subscribe configuration for task STARTISOOUT + 0x0C8 + read-write + + + CHIDX + DPPI channel that task STARTISOOUT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EP0RCVOUT + Subscribe configuration for task EP0RCVOUT + 0x0CC + read-write + + + CHIDX + DPPI channel that task EP0RCVOUT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EP0STATUS + Subscribe configuration for task EP0STATUS + 0x0D0 + read-write + + + CHIDX + DPPI channel that task EP0STATUS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_EP0STALL + Subscribe configuration for task EP0STALL + 0x0D4 + read-write + + + CHIDX + DPPI channel that task EP0STALL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DPDMDRIVE + Subscribe configuration for task DPDMDRIVE + 0x0D8 + read-write + + + CHIDX + DPPI channel that task DPDMDRIVE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_DPDMNODRIVE + Subscribe configuration for task DPDMNODRIVE + 0x0DC + read-write + + + CHIDX + DPPI channel that task DPDMNODRIVE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0x100 + read-write + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0x104 + read-write + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPIN[%s] + Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x108 + read-write + + + EVENTS_ENDEPIN + The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0x128 + read-write + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0x12C + read-write + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + EVENTS_ENDEPOUT[%s] + Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0x130 + read-write + + + EVENTS_ENDEPOUT + The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0x150 + read-write + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0x154 + read-write + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0x158 + read-write + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0x15C + read-write + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0x160 + read-write + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_USBRESET + Publish configuration for event USBRESET + 0x180 + read-write + + + CHIDX + DPPI channel that event USBRESET will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x184 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_ENDEPIN[%s] + Description collection: Publish configuration for event ENDEPIN[n] + 0x188 + read-write + + + CHIDX + DPPI channel that event ENDEPIN[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EP0DATADONE + Publish configuration for event EP0DATADONE + 0x1A8 + read-write + + + CHIDX + DPPI channel that event EP0DATADONE will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDISOIN + Publish configuration for event ENDISOIN + 0x1AC + read-write + + + CHIDX + DPPI channel that event ENDISOIN will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_ENDEPOUT[%s] + Description collection: Publish configuration for event ENDEPOUT[n] + 0x1B0 + read-write + + + CHIDX + DPPI channel that event ENDEPOUT[n] will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDISOOUT + Publish configuration for event ENDISOOUT + 0x1D0 + read-write + + + CHIDX + DPPI channel that event ENDISOOUT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SOF + Publish configuration for event SOF + 0x1D4 + read-write + + + CHIDX + DPPI channel that event SOF will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_USBEVENT + Publish configuration for event USBEVENT + 0x1D8 + read-write + + + CHIDX + DPPI channel that event USBEVENT will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EP0SETUP + Publish configuration for event EP0SETUP + 0x1DC + read-write + + + CHIDX + DPPI channel that event EP0SETUP will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_EPDATA + Publish configuration for event EPDATA + 0x1E0 + read-write + + + CHIDX + DPPI channel that event EPDATA will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + EP0DATADONE_STARTEPIN0 + Shortcut between event EP0DATADONE and task STARTEPIN[0] + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_STARTEPOUT0 + Shortcut between event EP0DATADONE and task STARTEPOUT[0] + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EP0DATADONE_EP0STATUS + Shortcut between event EP0DATADONE and task EP0STATUS + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0STATUS + Shortcut between event ENDEPOUT[0] and task EP0STATUS + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDEPOUT0_EP0RCVOUT + Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + USBRESET + Enable or disable interrupt for event USBRESET + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN0 + Enable or disable interrupt for event ENDEPIN[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN1 + Enable or disable interrupt for event ENDEPIN[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN2 + Enable or disable interrupt for event ENDEPIN[2] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN3 + Enable or disable interrupt for event ENDEPIN[3] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN4 + Enable or disable interrupt for event ENDEPIN[4] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN5 + Enable or disable interrupt for event ENDEPIN[5] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN6 + Enable or disable interrupt for event ENDEPIN[6] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPIN7 + Enable or disable interrupt for event ENDEPIN[7] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0DATADONE + Enable or disable interrupt for event EP0DATADONE + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOIN + Enable or disable interrupt for event ENDISOIN + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT0 + Enable or disable interrupt for event ENDEPOUT[0] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT1 + Enable or disable interrupt for event ENDEPOUT[1] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT2 + Enable or disable interrupt for event ENDEPOUT[2] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT3 + Enable or disable interrupt for event ENDEPOUT[3] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT4 + Enable or disable interrupt for event ENDEPOUT[4] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT5 + Enable or disable interrupt for event ENDEPOUT[5] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT6 + Enable or disable interrupt for event ENDEPOUT[6] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDEPOUT7 + Enable or disable interrupt for event ENDEPOUT[7] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDISOOUT + Enable or disable interrupt for event ENDISOOUT + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SOF + Enable or disable interrupt for event SOF + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBEVENT + Enable or disable interrupt for event USBEVENT + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EP0SETUP + Enable or disable interrupt for event EP0SETUP + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + EPDATA + Enable or disable interrupt for event EPDATA + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + USBRESET + Write '1' to enable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN0 + Write '1' to enable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN1 + Write '1' to enable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN2 + Write '1' to enable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN3 + Write '1' to enable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN4 + Write '1' to enable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN5 + Write '1' to enable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN6 + Write '1' to enable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPIN7 + Write '1' to enable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0DATADONE + Write '1' to enable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOIN + Write '1' to enable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT0 + Write '1' to enable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT1 + Write '1' to enable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT2 + Write '1' to enable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT3 + Write '1' to enable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT4 + Write '1' to enable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT5 + Write '1' to enable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT6 + Write '1' to enable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDEPOUT7 + Write '1' to enable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDISOOUT + Write '1' to enable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SOF + Write '1' to enable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBEVENT + Write '1' to enable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EP0SETUP + Write '1' to enable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EPDATA + Write '1' to enable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + USBRESET + Write '1' to disable interrupt for event USBRESET + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN0 + Write '1' to disable interrupt for event ENDEPIN[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN1 + Write '1' to disable interrupt for event ENDEPIN[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN2 + Write '1' to disable interrupt for event ENDEPIN[2] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN3 + Write '1' to disable interrupt for event ENDEPIN[3] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN4 + Write '1' to disable interrupt for event ENDEPIN[4] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN5 + Write '1' to disable interrupt for event ENDEPIN[5] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN6 + Write '1' to disable interrupt for event ENDEPIN[6] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPIN7 + Write '1' to disable interrupt for event ENDEPIN[7] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0DATADONE + Write '1' to disable interrupt for event EP0DATADONE + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOIN + Write '1' to disable interrupt for event ENDISOIN + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT0 + Write '1' to disable interrupt for event ENDEPOUT[0] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT1 + Write '1' to disable interrupt for event ENDEPOUT[1] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT2 + Write '1' to disable interrupt for event ENDEPOUT[2] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT3 + Write '1' to disable interrupt for event ENDEPOUT[3] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT4 + Write '1' to disable interrupt for event ENDEPOUT[4] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT5 + Write '1' to disable interrupt for event ENDEPOUT[5] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT6 + Write '1' to disable interrupt for event ENDEPOUT[6] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDEPOUT7 + Write '1' to disable interrupt for event ENDEPOUT[7] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDISOOUT + Write '1' to disable interrupt for event ENDISOOUT + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SOF + Write '1' to disable interrupt for event SOF + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBEVENT + Write '1' to disable interrupt for event USBEVENT + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EP0SETUP + Write '1' to disable interrupt for event EP0SETUP + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EPDATA + Write '1' to disable interrupt for event EPDATA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVENTCAUSE + Details on what caused the USBEVENT event + 0x400 + read-write + oneToClear + + + ISOOUTCRC + CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + 0 + 0 + + + NotDetected + No error detected + 0 + + + Detected + Error detected + 1 + + + + + SUSPEND + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + 8 + 8 + + + NotDetected + Suspend not detected + 0 + + + Detected + Suspend detected + 1 + + + + + RESUME + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. + 9 + 9 + + + NotDetected + Resume not detected + 0 + + + Detected + Resume detected + 1 + + + + + USBWUALLOWED + USB MAC has been woken up and operational. Write '1' to clear. + 10 + 10 + + + NotAllowed + Wake up not allowed + 0 + + + Allowed + Wake up allowed + 1 + + + + + READY + USB device is ready for normal operation. Write '1' to clear. + 11 + 11 + + + NotDetected + USBEVENT was not issued due to USBD peripheral ready + 0 + + + Ready + USBD peripheral is ready + 1 + + + + + + + HALTED + Unspecified + USBD_HALTED + read-write + 0x420 + + 0x8 + 0x4 + EPIN[%s] + Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x000 + read-only + + + GETSTATUS + IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + 0x8 + 0x4 + EPOUT[%s] + Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x024 + read-only + + + GETSTATUS + OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + + EPSTATUS + Provides information on which endpoint's EasyDMA registers have been captured + 0x468 + read-write + oneToClear + + + EPIN0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 0 + 0 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 1 + 1 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 2 + 2 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 3 + 3 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 4 + 4 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 5 + 5 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 6 + 6 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 7 + 7 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPIN8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 8 + 8 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 16 + 16 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 17 + 17 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 18 + 18 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 19 + 19 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 20 + 20 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 21 + 21 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 22 + 22 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 23 + 23 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + EPOUT8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 24 + 24 + + + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint + 1 + + + + + + + EPDATASTATUS + Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + 0x46C + read-write + oneToClear + + + EPIN1 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 1 + 1 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN2 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 2 + 2 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN3 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 3 + 3 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN4 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 4 + 4 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN5 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 5 + 5 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN6 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 6 + 6 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPIN7 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 7 + 7 + + + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT1 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 17 + 17 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT2 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 18 + 18 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT3 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 19 + 19 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT4 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 20 + 20 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT5 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 21 + 21 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT6 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 22 + 22 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + EPOUT7 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 23 + 23 + + + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred + 1 + + + + + + + USBADDR + Device USB address + 0x470 + read-only + + + ADDR + Device USB address + 0 + 6 + + + + + BMREQUESTTYPE + SETUP data, byte 0, bmRequestType + 0x480 + read-only + 0x00000000 + + + RECIPIENT + Data transfer type + 0 + 4 + + + Device + Device + 0 + + + Interface + Interface + 1 + + + Endpoint + Endpoint + 2 + + + Other + Other + 3 + + + + + TYPE + Data transfer type + 5 + 6 + + + Standard + Standard + 0 + + + Class + Class + 1 + + + Vendor + Vendor + 2 + + + + + DIRECTION + Data transfer direction + 7 + 7 + + + HostToDevice + Host-to-device + 0 + + + DeviceToHost + Device-to-host + 1 + + + + + + + BREQUEST + SETUP data, byte 1, bRequest + 0x484 + read-only + 0x00000000 + + + BREQUEST + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. + 0 + 7 + + + STD_GET_STATUS + Standard request GET_STATUS + 0 + + + STD_CLEAR_FEATURE + Standard request CLEAR_FEATURE + 1 + + + STD_SET_FEATURE + Standard request SET_FEATURE + 3 + + + STD_SET_ADDRESS + Standard request SET_ADDRESS + 5 + + + STD_GET_DESCRIPTOR + Standard request GET_DESCRIPTOR + 6 + + + STD_SET_DESCRIPTOR + Standard request SET_DESCRIPTOR + 7 + + + STD_GET_CONFIGURATION + Standard request GET_CONFIGURATION + 8 + + + STD_SET_CONFIGURATION + Standard request SET_CONFIGURATION + 9 + + + STD_GET_INTERFACE + Standard request GET_INTERFACE + 10 + + + STD_SET_INTERFACE + Standard request SET_INTERFACE + 11 + + + STD_SYNCH_FRAME + Standard request SYNCH_FRAME + 12 + + + + + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0x488 + read-only + 0x00000000 + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0 + 7 + + + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0x48C + read-only + 0x00000000 + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0 + 7 + + + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0x490 + read-only + 0x00000000 + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0 + 7 + + + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0x494 + read-only + 0x00000000 + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0 + 7 + + + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0x498 + read-only + 0x00000000 + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0 + 7 + + + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0x49C + read-only + 0x00000000 + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0 + 7 + + + + + SIZE + Unspecified + USBD_SIZE + read-write + 0x4A0 + + 0x8 + 0x4 + EPOUT[%s] + Description collection: Number of bytes received last in the data stage of this OUT endpoint + 0x000 + read-write + zeroToClear + + + SIZE + Number of bytes received last in the data stage of this OUT endpoint + 0 + 6 + + + + + ISOOUT + Number of bytes received last on this ISO OUT data endpoint + 0x020 + read-only + 0x00010000 + + + SIZE + Number of bytes received last on this ISO OUT data endpoint + 0 + 9 + + + ZERO + Zero-length data packet received + 16 + 16 + + + Normal + No zero-length data received, use value in SIZE + 0 + + + ZeroData + Zero-length data received, ignore value in SIZE + 1 + + + + + + + + ENABLE + Enable USB + 0x500 + read-write + + + ENABLE + Enable USB + 0 + 0 + + + Disabled + USB peripheral is disabled + 0 + + + Enabled + USB peripheral is enabled + 1 + + + + + + + USBPULLUP + Control of the USB pull-up + 0x504 + read-write + + + CONNECT + Control of the USB pull-up on the D+ line + 0 + 0 + + + Disabled + Pull-up is disconnected + 0 + + + Enabled + Pull-up is connected to D+ + 1 + + + + + + + DPDMVALUE + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + 0x508 + read-write + + + STATE + State D+ and D- lines will be forced into by the DPDMDRIVE task + 0 + 4 + + + Resume + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + 1 + + + J + D+ forced high, D- forced low (J state) + 2 + + + K + D+ forced low, D- forced high (K state) + 4 + + + + + + + DTOGGLE + Data toggle control and status + 0x50C + read-write + 0x00000100 + + + EP + Select bulk endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + VALUE + Data toggle value + 8 + 9 + + + Nop + No action on data toggle when writing the register with this value + 0 + + + Data0 + Data toggle is DATA0 on endpoint set by EP and IO + 1 + + + Data1 + Data toggle is DATA1 on endpoint set by EP and IO + 2 + + + + + + + EPINEN + Endpoint IN enable + 0x510 + read-write + 0x00000001 + + + IN0 + Enable IN endpoint 0 + 0 + 0 + + + Disable + Disable endpoint IN 0 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 0 (response to IN tokens) + 1 + + + + + IN1 + Enable IN endpoint 1 + 1 + 1 + + + Disable + Disable endpoint IN 1 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 1 (response to IN tokens) + 1 + + + + + IN2 + Enable IN endpoint 2 + 2 + 2 + + + Disable + Disable endpoint IN 2 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 2 (response to IN tokens) + 1 + + + + + IN3 + Enable IN endpoint 3 + 3 + 3 + + + Disable + Disable endpoint IN 3 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 3 (response to IN tokens) + 1 + + + + + IN4 + Enable IN endpoint 4 + 4 + 4 + + + Disable + Disable endpoint IN 4 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 4 (response to IN tokens) + 1 + + + + + IN5 + Enable IN endpoint 5 + 5 + 5 + + + Disable + Disable endpoint IN 5 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 5 (response to IN tokens) + 1 + + + + + IN6 + Enable IN endpoint 6 + 6 + 6 + + + Disable + Disable endpoint IN 6 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 6 (response to IN tokens) + 1 + + + + + IN7 + Enable IN endpoint 7 + 7 + 7 + + + Disable + Disable endpoint IN 7 (no response to IN tokens) + 0 + + + Enable + Enable endpoint IN 7 (response to IN tokens) + 1 + + + + + ISOIN + Enable ISO IN endpoint + 8 + 8 + + + Disable + Disable ISO IN endpoint 8 + 0 + + + Enable + Enable ISO IN endpoint 8 + 1 + + + + + + + EPOUTEN + Endpoint OUT enable + 0x514 + read-write + 0x00000001 + + + OUT0 + Enable OUT endpoint 0 + 0 + 0 + + + Disable + Disable endpoint OUT 0 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 0 (response to OUT tokens) + 1 + + + + + OUT1 + Enable OUT endpoint 1 + 1 + 1 + + + Disable + Disable endpoint OUT 1 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 1 (response to OUT tokens) + 1 + + + + + OUT2 + Enable OUT endpoint 2 + 2 + 2 + + + Disable + Disable endpoint OUT 2 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 2 (response to OUT tokens) + 1 + + + + + OUT3 + Enable OUT endpoint 3 + 3 + 3 + + + Disable + Disable endpoint OUT 3 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 3 (response to OUT tokens) + 1 + + + + + OUT4 + Enable OUT endpoint 4 + 4 + 4 + + + Disable + Disable endpoint OUT 4 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 4 (response to OUT tokens) + 1 + + + + + OUT5 + Enable OUT endpoint 5 + 5 + 5 + + + Disable + Disable endpoint OUT 5 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 5 (response to OUT tokens) + 1 + + + + + OUT6 + Enable OUT endpoint 6 + 6 + 6 + + + Disable + Disable endpoint OUT 6 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 6 (response to OUT tokens) + 1 + + + + + OUT7 + Enable OUT endpoint 7 + 7 + 7 + + + Disable + Disable endpoint OUT 7 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 7 (response to OUT tokens) + 1 + + + + + ISOOUT + Enable ISO OUT endpoint 8 + 8 + 8 + + + Disable + Disable ISO OUT endpoint 8 + 0 + + + Enable + Enable ISO OUT endpoint 8 + 1 + + + + + + + EPSTALL + STALL endpoints + 0x518 + write-only + 0x00000000 + modifyExternal + + + EP + Select endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 + + + Out + Selects OUT endpoint + 0 + + + In + Selects IN endpoint + 1 + + + + + STALL + Stall selected endpoint + 8 + 8 + + + UnStall + Don't stall selected endpoint + 0 + + + Stall + Stall selected endpoint + 1 + + + + + + + ISOSPLIT + Controls the split of ISO buffers + 0x51C + read-write + + + SPLIT + Controls the split of ISO buffers + 0 + 15 + + + OneDir + Full buffer dedicated to either ISO IN or OUT + 0x0000 + + + HalfIN + Lower half for IN, upper half for OUT + 0x0080 + + + + + + + FRAMECNTR + Returns the current value of the start of frame counter + 0x520 + read-only + + + FRAMECNTR + Returns the current value of the start of frame counter + 0 + 10 + + + + + LOWPOWER + Controls USBD peripheral low power mode during USB suspend + 0x52C + read-write + 0x00000000 + + + LOWPOWER + Controls USBD peripheral low-power mode during USB suspend + 0 + 0 + + + ForceNormal + Software must write this value to exit low power mode and before performing a remote wake-up + 0 + + + LowPower + Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + 1 + + + + + + + ISOINCONFIG + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0x530 + read-write + + + RESPONSE + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0 + 0 + + + NoResp + Endpoint does not respond in that case + 0 + + + ZeroData + Endpoint responds with a zero-length data packet in that case + 1 + + + + + + + 8 + 0x014 + EPIN[%s] + Unspecified + USBD_EPIN + read-write + 0x600 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOIN + Unspecified + USBD_ISOIN + read-write + 0x6A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + 8 + 0x014 + EPOUT[%s] + Unspecified + USBD_EPOUT + read-write + 0x700 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOOUT + Unspecified + USBD_ISOOUT + read-write + 0x7A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + + + USBD_S + Universal serial bus device 1 + 0x50036000 + + + + USBD + 54 + + + + USBREGULATOR_NS + USB Regulator 0 + 0x40037000 + USBREG + + + + 0 + 0x1000 + registers + + + USBREGULATOR + 55 + + USBREG + 0x20 + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0x100 + read-write + + + EVENTS_USBDETECTED + Voltage supply detected on VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0x104 + read-write + + + EVENTS_USBREMOVED + Voltage supply removed from VBUS + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0x108 + read-write + + + EVENTS_USBPWRRDY + USB 3.3 V supply ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_USBDETECTED + Publish configuration for event USBDETECTED + 0x180 + read-write + + + CHIDX + DPPI channel that event USBDETECTED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_USBREMOVED + Publish configuration for event USBREMOVED + 0x184 + read-write + + + CHIDX + DPPI channel that event USBREMOVED will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_USBPWRRDY + Publish configuration for event USBPWRRDY + 0x188 + read-write + + + CHIDX + DPPI channel that event USBPWRRDY will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + USBDETECTED + Enable or disable interrupt for event USBDETECTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBREMOVED + Enable or disable interrupt for event USBREMOVED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + USBPWRRDY + Enable or disable interrupt for event USBPWRRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + USBDETECTED + Write '1' to enable interrupt for event USBDETECTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBREMOVED + Write '1' to enable interrupt for event USBREMOVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBPWRRDY + Write '1' to enable interrupt for event USBPWRRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + USBDETECTED + Write '1' to disable interrupt for event USBDETECTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBREMOVED + Write '1' to disable interrupt for event USBREMOVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + USBPWRRDY + Write '1' to disable interrupt for event USBPWRRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + USBREGSTATUS + USB supply status + 0x400 + read-only + 0x00000000 + + + VBUSDETECT + VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) + 0 + 0 + + + NoVbus + VBUS voltage below valid threshold + 0 + + + VbusPresent + VBUS voltage above valid threshold + 1 + + + + + OUTPUTRDY + USB supply output settling time elapsed + 1 + 1 + + + NotReady + USBREG output settling time not elapsed + 0 + + + Ready + USBREG output settling time elapsed (same information as USBPWRRDY event) + 1 + + + + + + + + + USBREGULATOR_S + USB Regulator 1 + 0x50037000 + + + + USBREGULATOR + 55 + + + + KMU_NS + Key management unit 0 + 0x40039000 + KMU + + + + 0 + 0x1000 + registers + + + KMU + 57 + + KMU + 0x20 + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0x0000 + write-only + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0x100 + read-write + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0x104 + read-write + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0x108 + read-write + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + KEYSLOT_PUSHED + Enable or disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_REVOKED + Enable or disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_ERROR + Enable or disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + KEYSLOT_PUSHED + Write '1' to enable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to enable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_ERROR + Write '1' to enable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + KEYSLOT_PUSHED + Write '1' to disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_ERROR + Write '1' to disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + KEYSLOT_PUSHED + Read pending status of interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_REVOKED + Read pending status of interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_ERROR + Read pending status of interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + STATUS + Status bits for KMU operation + 0x40C + read-only + 0x00000000 + + + SELECTED + Key slot ID successfully selected by the KMU + 0 + 0 + + + Disabled + No key slot ID selected by KMU + 0 + + + Enabled + Key slot ID successfully selected by KMU + 1 + + + + + BLOCKED + Violation status + 1 + 1 + + + Disabled + No access violation detected + 0 + + + Enabled + Access violation detected and blocked + 1 + + + + + + + SELECTKEYSLOT + Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started + 0x500 + read-write + 0x00000000 + + + ID + Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. + 0 + 7 + + + + + + + NVMC_NS + Non-volatile memory controller 0 + 0x40039000 + KMU_NS + NVMC + + + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (ongoing write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. + 0 + 2 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + PEen + Partial erase enabled + 4 + + + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + + ERASEALL + Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + CONFIGNS + Non-secure configuration register + 0x584 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + WRITEUICRNS + Non-secure APPROTECT enable register + 0x588 + write-only + + + SET + Allow non-secure code to set APPROTECT + 0 + 0 + + + Set + Set value + 1 + + + + + KEY + Key to write in order to validate the write operation + 4 + 31 + + + Keyvalid + Key value + 0xAFBE5A7 + + + + + + + + + KMU_S + Key management unit 1 + 0x50039000 + + + + KMU + 57 + + + + NVMC_S + Non-volatile memory controller 1 + 0x50039000 + KMU_S + + + + + P0_NS + GPIO Port 0 + 0x40842500 + GPIO + + + + 0 + 0x300 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x004 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x008 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x00C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x010 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x014 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x018 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x01C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + + + PIN0 + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) + 0x024 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + DETECTMODE_SEC + Select between default DETECT signal behavior and LDETECT mode (For secure pin only) + 0x028 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x200 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 11 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0', standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0', disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + E0E1 + Extra high drive '0', extra high drive '1' + 11 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + MCUSEL + Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. + 28 + 30 + + + AppMCU + Application MCU + 0x0 + + + NetworkMCU + Network MCU + 0x1 + + + Peripheral + Peripheral with dedicated pins + 0x3 + + + TND + Trace and Debug Subsystem + 0x7 + + + + + + + + + P1_NS + GPIO Port 1 + 0x40842800 + + + + + P0_S + GPIO Port 2 + 0x50842500 + + + + + P1_S + GPIO Port 3 + 0x50842800 + + + + + CRYPTOCELL_S + ARM TrustZone CryptoCell register interface + 0x50844000 + CRYPTOCELL + + + + 0 + 0x1000 + registers + + + CRYPTOCELL + 68 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable the CRYPTOCELL subsystem. + 0 + 0 + + + Disabled + CRYPTOCELL subsystem disabled. + 0 + + + Enabled + CRYPTOCELL subsystem enabled. + 1 + + + + + + + + + VMC_NS + Volatile Memory controller 0 + 0x40081000 + VMC + + + + 0 + 0x1000 + registers + + VMC + 0x20 + + + 8 + 0x010 + RAM[%s] + Unspecified + VMC_RAM + read-write + 0x600 + + POWER + Description cluster: RAM[n] power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 of RAM[n] on or off in System ON mode + 4 + 4 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 of RAM[n] on or off in System ON mode + 5 + 5 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 of RAM[n] on or off in System ON mode + 6 + 6 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 of RAM[n] on or off in System ON mode + 7 + 7 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 of RAM[n] on or off in System ON mode + 8 + 8 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 of RAM[n] on or off in System ON mode + 9 + 9 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 of RAM[n] on or off in System ON mode + 10 + 10 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 of RAM[n] on or off in System ON mode + 11 + 11 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 of RAM[n] on or off in System ON mode + 12 + 12 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 of RAM[n] on or off in System ON mode + 13 + 13 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 of RAM[n] on or off in System ON mode + 14 + 14 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 of RAM[n] on or off in System ON mode + 15 + 15 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 of RAM[n] when RAM section is switched off + 20 + 20 + + + Off + Off + 0 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 of RAM[n] when RAM section is switched off + 21 + 21 + + + Off + Off + 0 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 of RAM[n] when RAM section is switched off + 22 + 22 + + + Off + Off + 0 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 of RAM[n] when RAM section is switched off + 23 + 23 + + + Off + Off + 0 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 of RAM[n] when RAM section is switched off + 24 + 24 + + + Off + Off + 0 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 of RAM[n] when RAM section is switched off + 25 + 25 + + + Off + Off + 0 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 of RAM[n] when RAM section is switched off + 26 + 26 + + + Off + Off + 0 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 of RAM[n] when RAM section is switched off + 27 + 27 + + + Off + Off + 0 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 of RAM[n] when RAM section is switched off + 28 + 28 + + + Off + Off + 0 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 of RAM[n] when RAM section is switched off + 29 + 29 + + + Off + Off + 0 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 of RAM[n] when RAM section is switched off + 30 + 30 + + + Off + Off + 0 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 of RAM[n] when RAM section is switched off + 31 + 31 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAM[n] power control set register + 0x004 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S4POWER + Keep RAM section S4 of RAM[n] on or off in System ON mode + 4 + 4 + + + On + On + 1 + + + + + S5POWER + Keep RAM section S5 of RAM[n] on or off in System ON mode + 5 + 5 + + + On + On + 1 + + + + + S6POWER + Keep RAM section S6 of RAM[n] on or off in System ON mode + 6 + 6 + + + On + On + 1 + + + + + S7POWER + Keep RAM section S7 of RAM[n] on or off in System ON mode + 7 + 7 + + + On + On + 1 + + + + + S8POWER + Keep RAM section S8 of RAM[n] on or off in System ON mode + 8 + 8 + + + On + On + 1 + + + + + S9POWER + Keep RAM section S9 of RAM[n] on or off in System ON mode + 9 + 9 + + + On + On + 1 + + + + + S10POWER + Keep RAM section S10 of RAM[n] on or off in System ON mode + 10 + 10 + + + On + On + 1 + + + + + S11POWER + Keep RAM section S11 of RAM[n] on or off in System ON mode + 11 + 11 + + + On + On + 1 + + + + + S12POWER + Keep RAM section S12 of RAM[n] on or off in System ON mode + 12 + 12 + + + On + On + 1 + + + + + S13POWER + Keep RAM section S13 of RAM[n] on or off in System ON mode + 13 + 13 + + + On + On + 1 + + + + + S14POWER + Keep RAM section S14 of RAM[n] on or off in System ON mode + 14 + 14 + + + On + On + 1 + + + + + S15POWER + Keep RAM section S15 of RAM[n] on or off in System ON mode + 15 + 15 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 of RAM[n] when RAM section is switched off + 20 + 20 + + + On + On + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 of RAM[n] when RAM section is switched off + 21 + 21 + + + On + On + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 of RAM[n] when RAM section is switched off + 22 + 22 + + + On + On + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 of RAM[n] when RAM section is switched off + 23 + 23 + + + On + On + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 of RAM[n] when RAM section is switched off + 24 + 24 + + + On + On + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 of RAM[n] when RAM section is switched off + 25 + 25 + + + On + On + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 of RAM[n] when RAM section is switched off + 26 + 26 + + + On + On + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 of RAM[n] when RAM section is switched off + 27 + 27 + + + On + On + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 of RAM[n] when RAM section is switched off + 28 + 28 + + + On + On + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 of RAM[n] when RAM section is switched off + 29 + 29 + + + On + On + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 of RAM[n] when RAM section is switched off + 30 + 30 + + + On + On + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 of RAM[n] when RAM section is switched off + 31 + 31 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAM[n] power control clear register + 0x008 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM[n] on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAM[n] on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAM[n] on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAM[n] on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S4POWER + Keep RAM section S4 of RAM[n] on or off in System ON mode + 4 + 4 + + + Off + Off + 1 + + + + + S5POWER + Keep RAM section S5 of RAM[n] on or off in System ON mode + 5 + 5 + + + Off + Off + 1 + + + + + S6POWER + Keep RAM section S6 of RAM[n] on or off in System ON mode + 6 + 6 + + + Off + Off + 1 + + + + + S7POWER + Keep RAM section S7 of RAM[n] on or off in System ON mode + 7 + 7 + + + Off + Off + 1 + + + + + S8POWER + Keep RAM section S8 of RAM[n] on or off in System ON mode + 8 + 8 + + + Off + Off + 1 + + + + + S9POWER + Keep RAM section S9 of RAM[n] on or off in System ON mode + 9 + 9 + + + Off + Off + 1 + + + + + S10POWER + Keep RAM section S10 of RAM[n] on or off in System ON mode + 10 + 10 + + + Off + Off + 1 + + + + + S11POWER + Keep RAM section S11 of RAM[n] on or off in System ON mode + 11 + 11 + + + Off + Off + 1 + + + + + S12POWER + Keep RAM section S12 of RAM[n] on or off in System ON mode + 12 + 12 + + + Off + Off + 1 + + + + + S13POWER + Keep RAM section S13 of RAM[n] on or off in System ON mode + 13 + 13 + + + Off + Off + 1 + + + + + S14POWER + Keep RAM section S14 of RAM[n] on or off in System ON mode + 14 + 14 + + + Off + Off + 1 + + + + + S15POWER + Keep RAM section S15 of RAM[n] on or off in System ON mode + 15 + 15 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM[n] when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM[n] when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM[n] when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM[n] when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + S4RETENTION + Keep retention on RAM section S4 of RAM[n] when RAM section is switched off + 20 + 20 + + + Off + Off + 1 + + + + + S5RETENTION + Keep retention on RAM section S5 of RAM[n] when RAM section is switched off + 21 + 21 + + + Off + Off + 1 + + + + + S6RETENTION + Keep retention on RAM section S6 of RAM[n] when RAM section is switched off + 22 + 22 + + + Off + Off + 1 + + + + + S7RETENTION + Keep retention on RAM section S7 of RAM[n] when RAM section is switched off + 23 + 23 + + + Off + Off + 1 + + + + + S8RETENTION + Keep retention on RAM section S8 of RAM[n] when RAM section is switched off + 24 + 24 + + + Off + Off + 1 + + + + + S9RETENTION + Keep retention on RAM section S9 of RAM[n] when RAM section is switched off + 25 + 25 + + + Off + Off + 1 + + + + + S10RETENTION + Keep retention on RAM section S10 of RAM[n] when RAM section is switched off + 26 + 26 + + + Off + Off + 1 + + + + + S11RETENTION + Keep retention on RAM section S11 of RAM[n] when RAM section is switched off + 27 + 27 + + + Off + Off + 1 + + + + + S12RETENTION + Keep retention on RAM section S12 of RAM[n] when RAM section is switched off + 28 + 28 + + + Off + Off + 1 + + + + + S13RETENTION + Keep retention on RAM section S13 of RAM[n] when RAM section is switched off + 29 + 29 + + + Off + Off + 1 + + + + + S14RETENTION + Keep retention on RAM section S14 of RAM[n] when RAM section is switched off + 30 + 30 + + + Off + Off + 1 + + + + + S15RETENTION + Keep retention on RAM section S15 of RAM[n] when RAM section is switched off + 31 + 31 + + + Off + Off + 1 + + + + + + + + + + VMC_S + Volatile Memory controller 1 + 0x50081000 + + + + + \ No newline at end of file diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index c6e0a00a2..97106bcbd 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -61,6 +61,7 @@ from . import target_nRF52832_xxAA from . import target_nRF52833_xxAA from . import target_nRF52840_xxAA +from . import target_nRF5340_xxAA from . import target_nRF91xx from . import target_STM32F103RC from . import target_STM32F051T8 @@ -202,6 +203,7 @@ 'nrf52832': target_nRF52832_xxAA.NRF52832, 'nrf52833': target_nRF52833_xxAA.NRF52833, 'nrf52840' : target_nRF52840_xxAA.NRF52840, + 'nrf53' : target_nRF5340_xxAA.NRF53XX, 'nrf91' : target_nRF91xx.NRF91XX, 'stm32f103rc': target_STM32F103RC.STM32F103RC, 'stm32f051': target_STM32F051T8.STM32F051, diff --git a/pyocd/target/builtin/target_nRF5340_xxAA.py b/pyocd/target/builtin/target_nRF5340_xxAA.py new file mode 100644 index 000000000..1f66054c2 --- /dev/null +++ b/pyocd/target/builtin/target_nRF5340_xxAA.py @@ -0,0 +1,444 @@ +# Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of Nordic Semiconductor ASA nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +import logging +from ...core.memory_map import FlashRegion, RamRegion, MemoryMap +from ...debug.svd.loader import SVDFile +from ..family.target_nRF53 import NRF53 +from ...flash.flash import Flash + +LOG = logging.getLogger(__name__) + +class Flash_NRF5340(Flash): + def __init__(self, target, flash_algo): + super(Flash_NRF5340, self).__init__(target, flash_algo) + + def prepare_target(self): + self.target.other_core.reset_and_halt() + + +FLASH_ALGO_APP = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b5b0, 0xf2c00504, 0x20000500, 0x0105eb09, 0x0005f849, 0x0001e9c1, 0xb2d060c8, 0xf0004614, + 0xb120fa3d, 0x0105eb09, 0x0402e9c1, 0xeb09bdb0, 0x21010005, 0xf0006041, 0x2000fa2b, 0xbf00bdb0, + 0x4604b510, 0xf0002000, 0xb138fa29, 0x0104f240, 0x0100f2c0, 0xe9c14449, 0xbd100402, 0x0004f240, + 0x0000f2c0, 0x0100eb09, 0x29006889, 0x2000bf04, 0xf244bd10, 0xf2c20100, 0x22010100, 0xf859600a, + 0x44482000, 0x6842604a, 0x6882608a, 0x68c060ca, 0x20006108, 0xbf00bd10, 0x0004f240, 0x0000f2c0, + 0xf8492101, 0x44481000, 0xe9c02100, 0x60c11101, 0xba28f000, 0xf240b5b0, 0x46040504, 0x0500f2c0, + 0xf8492002, 0xeb090005, 0x21000005, 0x1101e9c0, 0xf00060c1, 0xfbb4f9a5, 0xfb01f1f0, 0xb1304010, + 0x0005eb09, 0xe9c02103, 0x20651402, 0xeb09bdb0, 0x21010005, 0xf0006041, 0x42a0f9ad, 0xf000d813, + 0x42a0f9ab, 0xeb09d90f, 0x21020005, 0x46206041, 0xf9c2f000, 0xbf1c2803, 0xbdb02067, 0xf0004620, + 0x2000f9e7, 0xeb09bdb0, 0x21040005, 0x1402e9c0, 0xbdb02066, 0x41f0e92d, 0x0704f240, 0xf2c04604, + 0x46150700, 0x2003460e, 0x0107eb09, 0x07a32200, 0x0007f849, 0x2201e9c1, 0xd00660ca, 0x0107eb09, + 0x0402e9c1, 0xe8bd2065, 0xeb0981f0, 0x21010007, 0xf0006041, 0x42a0f96f, 0xf000d815, 0x42a0f96d, + 0xeb09d911, 0x21030007, 0xeb066041, 0xf0000804, 0x4580f963, 0xeb09d90f, 0x21040007, 0x1802e9c0, + 0xe8bd2066, 0xeb0981f0, 0x21040007, 0x1402e9c0, 0xe8bd2066, 0xeb0981f0, 0x21040007, 0xf0006041, + 0xb130f969, 0x0007eb09, 0x60812102, 0xe8bd2067, 0xeb0981f0, 0x21050007, 0x46206041, 0xf95cf000, + 0xd2072802, 0x0007eb09, 0xe9c02102, 0x20671402, 0x81f0e8bd, 0x22ffd10f, 0x46314620, 0xf836f000, + 0x2003b148, 0x0007f849, 0x0007eb09, 0x60412105, 0xe8bd2067, 0x200381f0, 0x0007f849, 0xebb02000, + 0xeb090f96, 0xf04f0107, 0x604a0206, 0xe8bdbf08, 0xea4f81f0, 0x26000896, 0x0026f854, 0xd10c3001, + 0x0026f855, 0x0026f844, 0xf942f000, 0x45463601, 0x0000f04f, 0xe8bdd3f0, 0xeb0981f0, 0x21050007, + 0xe9c019a2, 0x20681202, 0x81f0e8bd, 0x41f0e92d, 0x0704f240, 0x4604460d, 0x0700f2c0, 0x46162005, + 0x0007f849, 0x0007eb09, 0x07aa2100, 0x1101e9c0, 0xd00760c1, 0x0007eb09, 0xe9c02103, 0x20651502, + 0x81f0e8bd, 0x0007eb09, 0x60412102, 0xf8d2f000, 0xd81542a0, 0xf8d0f000, 0xd91142a0, 0x0007eb09, + 0x60412103, 0x0804eb05, 0xf8c6f000, 0xd90f4580, 0x0007eb09, 0xe9c02104, 0x20661802, 0x81f0e8bd, + 0x0007eb09, 0xe9c02104, 0x20661402, 0x81f0e8bd, 0x0007eb09, 0x2d002104, 0xbf046041, 0xe8bd2000, + 0x210081f0, 0xbf00e007, 0x42a93101, 0x0000f04f, 0xe8bdbf28, 0x5c6081f0, 0xd0f542b0, 0xeb091860, + 0x22050107, 0x2002e9c1, 0xe8bd2001, 0xbf0081f0, 0x41f0e92d, 0x0504f240, 0xf2c04604, 0x20040500, + 0x460f4690, 0x0005f849, 0x0005eb09, 0x07a22100, 0x1101e9c0, 0xd00860c1, 0x0005eb09, 0x26652103, + 0x1402e9c0, 0xe8bd4630, 0xeb0981f0, 0x21010005, 0xf0006041, 0x42a0f86f, 0xf000d812, 0x42a0f86d, + 0xeb09d90e, 0x21030005, 0x193e6041, 0xf864f000, 0xd90e4286, 0x0005eb09, 0xe9c02104, 0xe0041602, + 0x0005eb09, 0xe9c02104, 0x26661402, 0xe8bd4630, 0x210081f0, 0x0f97ebb1, 0x0005eb09, 0x0104f04f, + 0xd00b6041, 0x210008b8, 0xf8586822, 0x429a3021, 0x3101d10b, 0xf1044281, 0xd3f50404, 0x0005eb09, + 0x60412105, 0xe8bd4630, 0xeb0981f0, 0x21060005, 0x1402e9c0, 0xe8bd4620, 0x000081f0, 0x1030f240, + 0x00fff2c0, 0x31016801, 0x6800bf1c, 0xf6404770, 0xf2cf71e0, 0x78080100, 0xf3616849, 0x4770200b, + 0x2020f240, 0x00fff2c0, 0x31016801, 0x6800bf14, 0x5080f44f, 0xbf004770, 0x2024f240, 0x00fff2c0, + 0x31016801, 0x6800bf14, 0x7000f44f, 0xbf004770, 0x47702000, 0x47702000, 0xf7ffb510, 0x4604ffe1, + 0xffeaf7ff, 0xf004fb00, 0xbf00bd10, 0x42814401, 0x2001bf9c, 0xe0034770, 0xbf244288, 0x47702001, + 0x2b04f850, 0xbf1c3201, 0x47702000, 0xbf00e7f4, 0xbf004770, 0x47702000, 0x47702003, 0xbf842803, + 0x47702069, 0xb240b580, 0xf851a105, 0xf2490020, 0xf2c55104, 0x60080103, 0xf80af000, 0xbd802000, + 0x00000000, 0x00000002, 0x00000001, 0x00000000, 0x4000f249, 0x0003f2c5, 0x29006801, 0x4770d0fc, + 0x500cf249, 0x0003f2c5, 0x60012101, 0xbf00e7f0, 0x9000b081, 0xf04f9800, 0x600131ff, 0xe7e7b001, + 0x47702069, 0xf7ffb5b0, 0x4604ffa7, 0x2500b140, 0xf7ff4628, 0xf7ffffed, 0x4405ff83, 0xd3f742a5, + 0xbdb02000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000045, + 'pc_program_page': 0x20000139, + 'pc_erase_sector': 0x200000b9, + 'pc_eraseAll': 0x2000009d, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000524, + 'begin_stack' : 0x20003540, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x1000, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000540, + 0x20001540 + ], + 'min_program_length' : 0x1000, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x524, + 'rw_start': 0x528, + 'rw_size': 0x4, + 'zi_start': 0x52c, + 'zi_size': 0x10, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x200000, + 'sector_sizes': ( + (0x0, 0x1000), + ) +} + + +FLASH_ALGO_NET = { + 'load_address' : 0x21000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b5b0, 0xf2c00504, 0x20000500, 0x0105eb09, 0x0005f849, 0x0001e9c1, 0xb2d060c8, 0xf0004614, + 0xb120fa3f, 0x0105eb09, 0x0402e9c1, 0xeb09bdb0, 0x21010005, 0xf0006041, 0x2000fa2d, 0xbf00bdb0, + 0x4604b510, 0xf0002000, 0xb138fa2b, 0x0104f240, 0x0100f2c0, 0xe9c14449, 0xbd100402, 0x0004f240, + 0x0000f2c0, 0x0100eb09, 0x29006889, 0x2000bf04, 0xf244bd10, 0xf2c20100, 0x22011100, 0xf859600a, + 0x44482000, 0x6842604a, 0x6882608a, 0x68c060ca, 0x20006108, 0xbf00bd10, 0x0004f240, 0x0000f2c0, + 0xf8492101, 0x44481000, 0xe9c02100, 0x60c11101, 0xba2af000, 0xf240b5b0, 0x46040504, 0x0500f2c0, + 0xf8492002, 0xeb090005, 0x21000005, 0x1101e9c0, 0xf00060c1, 0xfbb4f9a5, 0xfb01f1f0, 0xb1304010, + 0x0005eb09, 0xe9c02103, 0x20651402, 0xeb09bdb0, 0x21010005, 0xf0006041, 0x42a0f9ab, 0xf000d813, + 0x42a0f9ab, 0xeb09d90f, 0x21020005, 0x46206041, 0xf9c4f000, 0xbf1c2803, 0xbdb02067, 0xf0004620, + 0x2000f9e9, 0xeb09bdb0, 0x21040005, 0x1402e9c0, 0xbdb02066, 0x41f0e92d, 0x0704f240, 0xf2c04604, + 0x46150700, 0x2003460e, 0x0107eb09, 0x07a32200, 0x0007f849, 0x2201e9c1, 0xd00660ca, 0x0107eb09, + 0x0402e9c1, 0xe8bd2065, 0xeb0981f0, 0x21010007, 0xf0006041, 0x42a0f96d, 0xf000d815, 0x42a0f96d, + 0xeb09d911, 0x21030007, 0xeb066041, 0xf0000804, 0x4580f963, 0xeb09d90f, 0x21040007, 0x1802e9c0, + 0xe8bd2066, 0xeb0981f0, 0x21040007, 0x1402e9c0, 0xe8bd2066, 0xeb0981f0, 0x21040007, 0xf0006041, + 0xb130f96b, 0x0007eb09, 0x60812102, 0xe8bd2067, 0xeb0981f0, 0x21050007, 0x46206041, 0xf95ef000, + 0xd2072802, 0x0007eb09, 0xe9c02102, 0x20671402, 0x81f0e8bd, 0x22ffd10f, 0x46314620, 0xf836f000, + 0x2003b148, 0x0007f849, 0x0007eb09, 0x60412105, 0xe8bd2067, 0x200381f0, 0x0007f849, 0xebb02000, + 0xeb090f96, 0xf04f0107, 0x604a0206, 0xe8bdbf08, 0xea4f81f0, 0x26000896, 0x0026f854, 0xd10c3001, + 0x0026f855, 0x0026f844, 0xf944f000, 0x45463601, 0x0000f04f, 0xe8bdd3f0, 0xeb0981f0, 0x21050007, + 0xe9c019a2, 0x20681202, 0x81f0e8bd, 0x41f0e92d, 0x0704f240, 0x4604460d, 0x0700f2c0, 0x46162005, + 0x0007f849, 0x0007eb09, 0x07aa2100, 0x1101e9c0, 0xd00760c1, 0x0007eb09, 0xe9c02103, 0x20651502, + 0x81f0e8bd, 0x0007eb09, 0x60412102, 0xf8d0f000, 0xd81542a0, 0xf8d0f000, 0xd91142a0, 0x0007eb09, + 0x60412103, 0x0804eb05, 0xf8c6f000, 0xd90f4580, 0x0007eb09, 0xe9c02104, 0x20661802, 0x81f0e8bd, + 0x0007eb09, 0xe9c02104, 0x20661402, 0x81f0e8bd, 0x0007eb09, 0x2d002104, 0xbf046041, 0xe8bd2000, + 0x210081f0, 0xbf00e007, 0x42a93101, 0x0000f04f, 0xe8bdbf28, 0x5c6081f0, 0xd0f542b0, 0xeb091860, + 0x22050107, 0x2002e9c1, 0xe8bd2001, 0xbf0081f0, 0x41f0e92d, 0x0504f240, 0xf2c04604, 0x20040500, + 0x460f4690, 0x0005f849, 0x0005eb09, 0x07a22100, 0x1101e9c0, 0xd00860c1, 0x0005eb09, 0x26652103, + 0x1402e9c0, 0xe8bd4630, 0xeb0981f0, 0x21010005, 0xf0006041, 0x42a0f86d, 0xf000d812, 0x42a0f86d, + 0xeb09d90e, 0x21030005, 0x193e6041, 0xf864f000, 0xd90e4286, 0x0005eb09, 0xe9c02104, 0xe0041602, + 0x0005eb09, 0xe9c02104, 0x26661402, 0xe8bd4630, 0x210081f0, 0x0f97ebb1, 0x0005eb09, 0x0104f04f, + 0xd00b6041, 0x210008b8, 0xf8586822, 0x429a3021, 0x3101d10b, 0xf1044281, 0xd3f50404, 0x0005eb09, + 0x60412105, 0xe8bd4630, 0xeb0981f0, 0x21060005, 0x1402e9c0, 0xe8bd4620, 0x000081f0, 0x1030f240, + 0x10fff2c0, 0x31016801, 0x6800bf1c, 0xf6404770, 0xf2cf71e0, 0x78080100, 0xf3616849, 0x4770200b, + 0x2020f240, 0x10fff2c0, 0x31016801, 0x6800bf14, 0x6000f44f, 0xbf004770, 0x2024f240, 0x10fff2c0, + 0x31016801, 0x6800bf14, 0x47702080, 0x47702000, 0x7080f04f, 0xbf004770, 0xf7ffb510, 0x4604ffe1, + 0xffeaf7ff, 0xf004fb00, 0x7080f100, 0xbf00bd10, 0x42814401, 0x2001bf9c, 0xe0034770, 0xbf244288, + 0x47702001, 0x2b04f850, 0xbf1c3201, 0x47702000, 0xbf00e7f4, 0xbf004770, 0x47702000, 0x47702003, + 0xbf842803, 0x47702069, 0xb240b580, 0xf851a105, 0xf2400020, 0xf2c45104, 0x60081108, 0xf80af000, + 0xbd802000, 0x00000000, 0x00000002, 0x00000001, 0x00000000, 0x4000f240, 0x1008f2c4, 0x29006801, + 0x4770d0fc, 0x500cf240, 0x1008f2c4, 0x60012101, 0xbf00e7f0, 0x9000b081, 0xf04f9800, 0x600131ff, + 0xe7e7b001, 0x47702069, 0xf7ffb5b0, 0x4604ffa5, 0x7f80f1b0, 0xf04fd90a, 0xbf007580, 0xf7ff4628, + 0xf7ffffe9, 0x4405ff7d, 0xd3f742a5, 0xbdb02000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x21000005, + 'pc_unInit': 0x21000045, + 'pc_program_page': 0x21000139, + 'pc_erase_sector': 0x210000b9, + 'pc_eraseAll': 0x2100009d, + + 'static_base' : 0x21000000 + 0x00000004 + 0x00000530, + 'begin_stack' : 0x21002550, + 'begin_data' : 0x21000000 + 0x1000, + 'page_size' : 0x800, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x21000550, + 0x21000d50 + ], + 'min_program_length' : 0x800, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x530, + 'rw_start': 0x534, + 'rw_size': 0x4, + 'zi_start': 0x538, + 'zi_size': 0x10, + + # Flash information + 'flash_start': 0x1000000, + 'flash_size': 0x40000, + 'sector_sizes': ( + (0x1000000, 0x800), + ) +} + + +FLASH_ALGO_APP_UICR = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b570, 0xf2c00604, 0x25000600, 0x0006eb09, 0x5006f849, 0x5501e9c0, 0xb2d060c5, 0xf0004614, + 0x2800fa99, 0xeb09bf1e, 0xe9c10106, 0x46050402, 0xbd704628, 0x4604b510, 0xf0002000, 0xf240fa8b, + 0xf2c00104, 0x44490100, 0xe9c1b110, 0xe0030402, 0x29006889, 0xbd10bf08, 0x0100f244, 0x0100f2c2, + 0x600a2201, 0x0204f240, 0x0200f2c0, 0x3002f859, 0x604b444a, 0x608b6853, 0x60cb6893, 0x610a68d2, + 0xbf00bd10, 0xf240b580, 0xf2c00004, 0x21010000, 0x1000f849, 0x21004448, 0x1101e9c0, 0xf00060c1, + 0x2000fa8f, 0xbf00bd80, 0xf240b570, 0xf2c00404, 0x20020400, 0x0504eb09, 0xf8492600, 0xe9c50004, + 0x60ee6601, 0xf9e0f000, 0xf8492105, 0x21011004, 0x0f03f010, 0x1601e9c5, 0xd00460ee, 0x0104eb09, + 0x608a2203, 0xf248e013, 0xf2c00c00, 0xeb000cff, 0xf50c010c, 0xeb095380, 0x42990204, 0x0303f04f, + 0xd9106053, 0x0004eb09, 0x60822204, 0xeb094608, 0x60c80104, 0xfa7ef000, 0x28694601, 0x2900bf14, + 0x46082100, 0xb1f0bd70, 0xf81c2300, 0x29ff1003, 0x1c59d123, 0xd2164281, 0x0103eb0c, 0x2aff784a, + 0x1c9ad114, 0xd20e4282, 0x2aff788a, 0x1cdad111, 0xd2084282, 0x29ff78c9, 0x3304d10e, 0xf04f4283, + 0xd3e20100, 0x2100e7dd, 0xbd704608, 0x0301f043, 0xf043e003, 0xe0000302, 0xeb0c4613, 0xeb090003, + 0x22050104, 0xbf00e7ad, 0xf240b570, 0xf2c00c04, 0x23050c00, 0x300cf849, 0x030ceb09, 0x0e00f04f, + 0xe9c30784, 0xf8c3ee01, 0xd005e00c, 0x010ceb09, 0xe9c12203, 0xe00c2002, 0x030ceb09, 0x0e01f04f, + 0xf8c3078c, 0xd007e004, 0x000ceb09, 0xe9c02203, 0x23652102, 0xbd704618, 0x7efff648, 0x0efff2c0, + 0x030ceb09, 0x45702402, 0xd905605c, 0x010ceb09, 0xe9c12204, 0xe00d2002, 0xf10e180b, 0xeb090501, + 0x2603040c, 0x606642ab, 0xeb09d907, 0x2104000c, 0x1302e9c0, 0x46182366, 0xb319bd70, 0x0e00f04f, + 0x300ef810, 0xd1274293, 0x0301f10e, 0xd219428b, 0x030eeb00, 0x4294785c, 0xf10ed117, 0x428c0402, + 0x789cd210, 0xd1134294, 0x0403f10e, 0xd209428c, 0x429378db, 0xf10ed10f, 0x458e0e04, 0x0300f04f, + 0xe010d3de, 0x46182300, 0xf04ebd70, 0xe0030e01, 0x0e02f04e, 0x46a6e000, 0xeb094470, 0x2205010c, + 0xe9c12301, 0x46182002, 0xbf00bd70, 0x41f0e92d, 0x0604f240, 0x0600f2c0, 0x46044615, 0xeb092003, + 0x23000206, 0xf849078f, 0xe9c20006, 0x60d33301, 0xeb09d006, 0xe9c20206, 0x20650102, 0x81f0e8bd, + 0x70fff648, 0x00fff2c0, 0x0206eb09, 0x42842302, 0xd9076053, 0x0006eb09, 0xe9c02104, 0x20661402, + 0x81f0e8bd, 0x3001190a, 0x0306eb09, 0x42822703, 0xd907605f, 0x0006eb09, 0xe9c02104, 0x20661202, + 0x81f0e8bd, 0xebb02000, 0xd01b0f91, 0x0891ea4f, 0xe00c2700, 0x0027f855, 0x0027f844, 0xf940f000, + 0x45473701, 0x0000f04f, 0xe8bdbf28, 0xf85481f0, 0x30010027, 0xeb09d0ee, 0x21050006, 0xe9c019e2, + 0x20681202, 0x81f0e8bd, 0x41f0e92d, 0x0c04f240, 0x0c00f2c0, 0xf8492304, 0xeb09300c, 0x2600030c, + 0xe9c30785, 0x60de6601, 0xeb09d005, 0x2203010c, 0x2002e9c1, 0xeb09e00a, 0x2601030c, 0x605e078d, + 0xeb09d008, 0x2203000c, 0x2102e9c0, 0x46182365, 0x81f0e8bd, 0x74fff648, 0x04fff2c0, 0x030ceb09, + 0x42a02602, 0xd905605e, 0x010ceb09, 0xe9c12204, 0xe00c2002, 0x3401180b, 0x060ceb09, 0x42a32503, + 0xd9086075, 0x000ceb09, 0xe9c02104, 0x23661302, 0xe8bd4618, 0x250081f0, 0x0f91ebb5, 0x060ceb09, + 0x0504f04f, 0xd0396075, 0x0e91ea4f, 0x240c2100, 0x19161905, 0x5c0cf855, 0x6c0cf856, 0xd12642b5, + 0x45751c4d, 0xeb00d22a, 0xeb020581, 0xf8d50681, 0x68778004, 0xd11345b8, 0x45771c8f, 0x68add21e, + 0x42b568b6, 0x1ccdd10f, 0xd2174575, 0x59175906, 0xd10b42be, 0x45713104, 0x0410f104, 0xe00dd3d8, + 0x0101f041, 0xf041e003, 0xe0000102, 0xeb004629, 0xeb090381, 0x2106000c, 0x1302e9c0, 0xe8bd4618, + 0x000081f0, 0x1030f240, 0x00fff2c0, 0x31016801, 0x6800bf1c, 0xf6404770, 0xf2cf71e0, 0x78080100, + 0xf3616849, 0x4770200b, 0x2020f240, 0x00fff2c0, 0x31016801, 0x6800bf14, 0x5080f44f, 0xbf004770, + 0x2024f240, 0x00fff2c0, 0x31016801, 0x6800bf14, 0x7000f44f, 0xbf004770, 0x47702000, 0x47702000, + 0x2120f240, 0x01fff2c0, 0x30016808, 0x6808bf14, 0x5080f44f, 0x3201684a, 0x6849bf14, 0x7100f44f, + 0xf000fb01, 0xbf004770, 0x42814401, 0x2001bf9c, 0xbf004770, 0x32016802, 0x2000bf1c, 0x30044770, + 0xbf244288, 0x47702001, 0x32016802, 0x2000bf1c, 0x30044770, 0xbf244288, 0x47702001, 0x32016802, + 0x2000bf1c, 0x30044770, 0xbf244288, 0x47702001, 0x32016802, 0x2000bf1c, 0x30044770, 0xbf244288, + 0x47702001, 0xbf00e7d6, 0xbf004770, 0x47702000, 0x47702003, 0xbf842803, 0x47702069, 0xa10cb240, + 0x1020f851, 0x4000f249, 0x0003f2c5, 0x1104f8c0, 0xbf00e005, 0x29006801, 0x2000bf1c, 0x68014770, + 0x6801b921, 0x6801b911, 0xd0f32900, 0x47702000, 0x00000000, 0x00000002, 0x00000001, 0x00000000, + 0x4000f249, 0x0003f2c5, 0xb9416801, 0xb9316801, 0x29006801, 0x4770bf18, 0x29006801, 0x4770d0f4, + 0x4000f249, 0x0003f2c5, 0xf8c02101, 0xbf00110c, 0xb9416801, 0xb9316801, 0x29006801, 0x4770bf18, + 0x29006801, 0x4770d0f4, 0x9000b081, 0x4100f249, 0xf2c59800, 0xf04f0103, 0x600232ff, 0xb9306808, + 0xb9206808, 0xb9106808, 0x28006808, 0xb001d0f6, 0xbf004770, 0x47702069, 0xb081b580, 0x2e20f240, + 0x0efff2c0, 0x0000f8de, 0xbf143001, 0x1000f8de, 0x5180f44f, 0x0004f8de, 0xbf143001, 0x2004f8de, + 0x7200f44f, 0xf101fb02, 0xf249b1f1, 0x22004300, 0x0303f2c5, 0x3cfff04f, 0x98009200, 0xc000f8c0, + 0xb9306818, 0xb9206818, 0xb9106818, 0x28006818, 0xf8ded0f6, 0x30010000, 0xf8debf14, 0xf44f0000, + 0x44025080, 0xd3e7428a, 0xb0012000, 0x0000bd80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000039, + 'pc_program_page': 0x20000291, + 'pc_erase_sector': 0x200000ad, + 'pc_eraseAll': 0x20000089, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000690, + 'begin_stack' : 0x200036b0, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x1000, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x200006b0, + 0x200016b0 + ], + 'min_program_length' : 0x1000, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x690, + 'rw_start': 0x694, + 'rw_size': 0x4, + 'zi_start': 0x698, + 'zi_size': 0x10, + + # Flash information + 'flash_start': 0xff8000, + 'flash_size': 0x1000, + 'sector_sizes': ( + (0x0, 0x1000), + ) +} + + +FLASH_ALGO_NET_UICR = { + 'load_address' : 0x21000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b570, 0xf2c00604, 0x25000600, 0x0006eb09, 0x5006f849, 0x5501e9c0, 0xb2d060c5, 0xf0004614, + 0x2800f9e5, 0xeb09bf1e, 0xe9c10106, 0x46050402, 0xbd704628, 0x4604b510, 0xf0002000, 0xf240f9d7, + 0xf2c00104, 0x44490100, 0xe9c1b110, 0xe0030402, 0x29006889, 0xbd10bf08, 0x0100f244, 0x1100f2c2, + 0x600a2201, 0x0204f240, 0x0200f2c0, 0x3002f859, 0x604b444a, 0x608b6853, 0x60cb6893, 0x610a68d2, + 0xbf00bd10, 0xf240b580, 0xf2c00004, 0x21010000, 0x1000f849, 0x21004448, 0x1101e9c0, 0xf00060c1, + 0x2000f9c7, 0xbf00bd80, 0xf240b510, 0xf2c00004, 0x21020000, 0x1000f849, 0x24004448, 0x4401e9c0, + 0xf00060c4, 0x4601f953, 0x0000f248, 0x10fff2c0, 0xf00022ff, 0xb130f80b, 0xf9baf000, 0x28694604, + 0x2c00bf14, 0x46202400, 0xbf00bd10, 0xf240b570, 0xf2c00c04, 0x23050c00, 0x300cf849, 0x030ceb09, + 0x0e00f04f, 0xe9c30784, 0xf8c3ee01, 0xd005e00c, 0x010ceb09, 0xe9c12203, 0xe00c2002, 0x030ceb09, + 0x0e01f04f, 0xf8c3078c, 0xd008e004, 0x000ceb09, 0xe9c02203, 0xf04f2102, 0x46700e65, 0xf648bd70, + 0xf2c07eff, 0xeb091eff, 0x2402030c, 0x605c4570, 0xeb09d905, 0x2204010c, 0x2002e9c1, 0x180be00d, + 0x0501f10e, 0x040ceb09, 0x42ab2603, 0xd9086066, 0x000ceb09, 0xe9c02104, 0xf04f1302, 0x46700e66, + 0xb151bd70, 0xf04f2300, 0xbf000e00, 0x42965cc6, 0x3301d107, 0xd3f9428b, 0xf04fe00b, 0x46700e00, + 0x4418bd70, 0x010ceb09, 0xf04f2205, 0xe9c10e01, 0x46702002, 0xbf00bd70, 0x41f0e92d, 0x0604f240, + 0x0600f2c0, 0x46044615, 0xeb092003, 0x23000206, 0xf849078f, 0xe9c20006, 0x60d33301, 0xeb09d006, + 0xe9c20206, 0x20650102, 0x81f0e8bd, 0x70fff648, 0x10fff2c0, 0x0206eb09, 0x42842302, 0xd9076053, + 0x0006eb09, 0xe9c02104, 0x20661402, 0x81f0e8bd, 0x3001190a, 0x0306eb09, 0x42822703, 0xd907605f, + 0x0006eb09, 0xe9c02104, 0x20661202, 0x81f0e8bd, 0xebb02000, 0xd01b0f91, 0x0891ea4f, 0xe00c2700, + 0x0027f855, 0x0027f844, 0xf8eaf000, 0x45473701, 0x0000f04f, 0xe8bdbf28, 0xf85481f0, 0x30010027, + 0xeb09d0ee, 0x21050006, 0xe9c019e2, 0x20681202, 0x81f0e8bd, 0xf240b570, 0xf2c00c04, 0x23040c00, + 0x300cf849, 0x030ceb09, 0x0e00f04f, 0xe9c30784, 0xf8c3ee01, 0xd005e00c, 0x010ceb09, 0xe9c12203, + 0xe00c2002, 0x030ceb09, 0x0e01f04f, 0xf8c3078c, 0xd007e004, 0x000ceb09, 0xe9c02203, 0x23652102, + 0xbd704618, 0x7efff648, 0x1efff2c0, 0x030ceb09, 0x45702402, 0xd905605c, 0x010ceb09, 0xe9c12204, + 0xe00d2002, 0xf10e180b, 0xeb090501, 0x2603040c, 0x606642ab, 0xeb09d907, 0x2104000c, 0x1302e9c0, + 0x46182366, 0x2500bd70, 0x0f91ebb5, 0x060ceb09, 0x0504f04f, 0xd0146075, 0x0e91ea4f, 0xbf002100, + 0xf8526804, 0x42ac5021, 0x3101d105, 0xf1004571, 0xd3f50004, 0xeb09e005, 0x2206010c, 0xe9c14603, + 0x46182002, 0x0000bd70, 0x1030f240, 0x10fff2c0, 0x31016801, 0x6800bf1c, 0xf6404770, 0xf2cf71e0, + 0x78080100, 0xf3616849, 0x4770200b, 0x2020f240, 0x10fff2c0, 0x31016801, 0x6800bf14, 0x6000f44f, + 0xbf004770, 0x2024f240, 0x10fff2c0, 0x31016801, 0x6800bf14, 0x47702080, 0x47702000, 0x7080f04f, + 0xbf004770, 0xf7ffb510, 0x4604ffe1, 0xffeaf7ff, 0xf004fb00, 0x7080f100, 0xbf00bd10, 0x42814401, + 0x2001bf9c, 0xe0034770, 0xbf244288, 0x47702001, 0x2b04f850, 0xbf1c3201, 0x47702000, 0xbf00e7f4, + 0xbf004770, 0x47702000, 0x47702003, 0xbf842803, 0x47702069, 0xb240b580, 0xf851a105, 0xf2400020, + 0xf2c45104, 0x60081108, 0xf80af000, 0xbd802000, 0x00000000, 0x00000002, 0x00000001, 0x00000000, + 0x4000f240, 0x1008f2c4, 0x29006801, 0x4770d0fc, 0x500cf240, 0x1008f2c4, 0x60012101, 0xbf00e7f0, + 0x9000b081, 0xf04f9800, 0x600131ff, 0xe7e7b001, 0x47702069, 0xf7ffb5b0, 0x4604ffa5, 0x7f80f1b0, + 0xf04fd90a, 0xbf007580, 0xf7ff4628, 0xf7ffffe9, 0x4405ff7d, 0xd3f742a5, 0xbdb02000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x21000005, + 'pc_unInit': 0x21000039, + 'pc_program_page': 0x210001bd, + 'pc_erase_sector': 0x210000ad, + 'pc_eraseAll': 0x21000089, + + 'static_base' : 0x21000000 + 0x00000004 + 0x0000047c, + 'begin_stack' : 0x210024a0, + 'begin_data' : 0x21000000 + 0x1000, + 'page_size' : 0x800, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x210004a0, + 0x21000ca0 + ], + 'min_program_length' : 0x800, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x47c, + 'rw_start': 0x480, + 'rw_size': 0x4, + 'zi_start': 0x484, + 'zi_size': 0x10, + + # Flash information + 'flash_start': 0x1ff8000, + 'flash_size': 0x1000, + 'sector_sizes': ( + (0x1000000, 0x800), + ) +} + + +class NRF53XX(NRF53): + MEMORY_MAP = MemoryMap( + FlashRegion( + start=0x0, + length=0x200000, + blocksize=0x1000, + algo=FLASH_ALGO_APP, + flash_class=Flash_NRF5340, + core_index=0, + ), + FlashRegion( + start=0x01000000, + length=0x00040000, + blocksize=0x800, + algo=FLASH_ALGO_NET, + flash_class=Flash_NRF5340, + core_index=1, + ), + FlashRegion( + start=0x00ff8000, + length=0x1000, + blocksize=0x1000, + is_erasable=False, + algo=FLASH_ALGO_APP_UICR, + flash_class=Flash_NRF5340, + core_index=0, + ), + FlashRegion( + start=0x01ff8000, + length=0x800, + blocksize=0x800, + is_erasable=False, + algo=FLASH_ALGO_NET, + flash_class=Flash_NRF5340, + core_index=1, + ), + RamRegion(start=0x20000000, length=0x80000), + ) + + def __init__(self, session): + super(NRF53XX, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("nrf5340_application.svd") # TODO diff --git a/pyocd/target/family/__init__.py b/pyocd/target/family/__init__.py index 7ef8bb893..11c644502 100644 --- a/pyocd/target/family/__init__.py +++ b/pyocd/target/family/__init__.py @@ -22,6 +22,7 @@ from . import target_kinetis from . import target_lpc5500 from . import target_nRF52 +from . import target_nRF53 from . import target_nRF91 class FamilyInfo(NamedTuple): @@ -41,5 +42,6 @@ class FamilyInfo(NamedTuple): FAMILIES = [ FamilyInfo("NXP", re.compile(r'MK[LEVWS]?.*'), target_kinetis.Kinetis ), FamilyInfo("Nordic Semiconductor", re.compile(r'nRF52[0-9]+.*'), target_nRF52.NRF52 ), + FamilyInfo("Nordic Semiconductor", re.compile(r'nRF53[0-9]+.*'), target_nRF53.NRF53 ), FamilyInfo("Nordic Semiconductor", re.compile(r'nRF91[0-9]+.*'), target_nRF91.NRF91 ), ] diff --git a/pyocd/target/family/target_nRF53.py b/pyocd/target/family/target_nRF53.py new file mode 100644 index 000000000..93892e481 --- /dev/null +++ b/pyocd/target/family/target_nRF53.py @@ -0,0 +1,850 @@ +# pyOCD debugger +# Copyright (c) 2006-2013 Arm Limited +# Copyright (c) 2019 Monadnock Systems Ltd. +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +import logging +from time import sleep + +from ...core import exceptions +from ...coresight.coresight_target import CoreSightTarget +from ...core.target import Target +from ...flash.eraser import FlashEraser +from ...utility.timeout import Timeout +from ...coresight.cortex_m_v8m import CortexM_v8M + +from typing import (Callable, TYPE_CHECKING, Union) +ProgressCallback = Callable[[Union[int, float]], None] + +AHB_AP_APP_NUM = 0x0 +AHB_AP_NET_NUM = 0x1 +CTRL_AP_APP_NUM = 0x2 +CTRL_AP_NET_NUM = 0x3 + +CTRL_AP_RESET = 0x000 +CTRL_AP_ERASEALL = 0x004 +CTRL_AP_ERASEALLSTATUS = 0x008 +CTRL_AP_APPROTECT_DISABLE = 0x010 +CTRL_AP_SECURE_APPROTECT_DISABLE = 0x014 +CTRL_AP_ERASEPROTECTSTATUS = 0x018 +CTRL_AP_ERASEPROTECTDISABLE = 0x01C +CTRL_AP_MAILBOX_TXDATA = 0x020 +CTRL_AP_MAILBOX_TXSTATUS = 0x024 +CTRL_AP_MAILBOX_RXDATA = 0x028 +CTRL_AP_MAILBOX_RXSTATUS = 0x02C +CTRL_AP_IDR = 0x0FC + +CTRL_AP_ERASEALLSTATUS_READY = 0x0 +CTRL_AP_ERASEALLSTATUS_BUSY = 0x1 + +CTRL_AP_ERASEPROTECTSTATUS_MSK = 0x1 + +CTRL_AP_MAILBOX_STATUS_NODATAPENDING = 0x0 +CTRL_AP_MAILBOX_STATUS_DATAPENDING = 0x1 + +CTRL_AP_RESET_NORESET = 0x0 +CTRL_AP_RESET_RESET = 0x1 + +CTRL_AP_ERASEALL_NOOPERATION = 0x0 +CTRL_AP_ERASEALL_ERASE = 0x1 + +CTRL_IDR_EXPECTED = 0x12880000 + +MASS_ERASE_TIMEOUT = 30.0 + +CSW_DEVICEEN = 0x00000040 + +nrf53_app_empty_image = [ + 0x00, 0x00, 0x04, 0x20, 0x8d, 0x07, 0x00, 0x00, 0xb5, 0x07, 0x00, 0x00, + 0xb7, 0x07, 0x00, 0x00, 0xb9, 0x07, 0x00, 0x00, 0xbb, 0x07, 0x00, 0x00, + 0xbd, 0x07, 0x00, 0x00, 0xbf, 0x07, 0x00, 0x00, 0x00, 0x00, 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reset_type=None): + if reset_type == Target.ResetType.SW_CORE: + self.ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_RESET) + self.ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_NORESET) + sleep(0.2) + else: + super().reset(reset_type) + +class NRF53(CoreSightTarget): + + VENDOR = "Nordic Semiconductor" + + def __init__(self, session, memory_map=None): + super(NRF53, self).__init__(session, memory_map) + self.ctrl_ap_app = None + self.ctrl_ap_net = None + self.was_locked_app = False + self.was_locked_net = False + self.default_reset_type = Target.ResetType.SW_SYSTEM + + def create_init_sequence(self): + seq = super(NRF53, self).create_init_sequence() + + # Must check whether security is enabled, and potentially auto-unlock, before + # any init tasks that require system bus access. + seq.wrap_task('discovery', + lambda seq: seq.insert_before('find_components', + ('check_ctrl_ap_idr', self.check_ctrl_ap_idr), + ('check_device_family', self.check_device_family), + ) + ) + seq.wrap_task('discovery', + lambda seq: seq.replace_task('create_cores', self.create_cores) + ) + seq.wrap_task('discovery', + lambda seq: seq.insert_after('create_cores', + ('persist_unlock_app', self.persist_unlock_app), + ('persist_unlock_net', self.persist_unlock_net), + ) + ) + seq.insert_before('post_connect_hook', + ('check_part_info', self.check_part_info)) + + return seq + + def check_ctrl_ap_idr(self): + self.ctrl_ap_app = self.dp.aps[CTRL_AP_APP_NUM] + self.ctrl_ap_net = self.dp.aps[CTRL_AP_NET_NUM] + self.was_locked_app = not self.ap_is_enabled(AHB_AP_APP_NUM) + + # Check CTRL-AP IDs. + if self.ctrl_ap_app.idr != CTRL_IDR_EXPECTED: + LOG.error("%s: bad CTRL-AP IDR (is 0x%08x)", self.part_number, self.ctrl_ap_app.idr) + if self.ctrl_ap_net.idr != CTRL_IDR_EXPECTED: + LOG.error("%s: bad CTRL-AP IDR (is 0x%08x)", self.part_number, self.ctrl_ap_net.idr) + + def ap_is_enabled(self, ap_num): + csw = self.dp.aps[ap_num].read_reg(0) + return csw & CSW_DEVICEEN + + def create_cores(self): + """@brief Prepare and create cores + """ + self.check_flash_security_app() + core_app = NRF53Core(self.session, self.aps[0], self.memory_map, 0, self.ctrl_ap_app) + core_app.default_reset_type = self.ResetType.SW_CORE + self.aps[AHB_AP_APP_NUM].core = core_app + core_app.init() + self.add_core(core_app) + + self.check_flash_security_net() + core_net = NRF53Core(self.session, self.aps[1], self.memory_map, 1, self.ctrl_ap_net) + core_net.default_reset_type = self.ResetType.SW_CORE + self.aps[AHB_AP_NET_NUM].core = core_net + core_net.init() + self.add_core(core_net) + + core_app.other_core = core_net + core_net.other_core = core_app + + def check_device_family(self): + """@brief Check whether the device is what we expect. + """ + + target_id = self.dp.read_dp(0x24) + if target_id & 0xFFF != 0x289: + LOG.error(f"This doesn't look like a Nordic Semiconductor device!") + if target_id & 0xF0000 != 0x70000: + LOG.error(f"This doesn't look like an nRF53 devcice!") + + + + def check_flash_security_app(self): + """@brief Check security and unlock app core. + + This init task determines whether the core is locked (APPROTECT enabled). If it is, + and if auto unlock is enabled, then perform a mass erase to unlock the core. + + This init task runs *before* cores are created. + """ + if self.was_locked_app: + if self.session.options.get('auto_unlock'): + LOG.warning("%s APP CORE APPROTECT enabled: will try to unlock via mass erase", self.part_number) + + self.mass_erase_app() + + # Check if AP was enabled + if not self.ap_is_enabled(AHB_AP_APP_NUM): + raise exceptions.TargetError("unable to unlock device") + + self._discoverer._create_1_ap(AHB_AP_APP_NUM) + else: + LOG.warning("%s APP CORE APPROTECT enabled: not automatically unlocking", self.part_number) + else: + LOG.info("%s APP not in secure state", self.part_number) + + + def check_flash_security_net(self): + """@brief Enable and unlock net core if needed. + + This init task determines whether the core is locked (APPROTECT enabled). If it is, + and if auto unlock is enabled, then perform a mass erase to unlock the core. + + This init task runs *before* cores are created. + """ + # Release NETWORK.FORCEOFF + self.write32(0x50005614, 0) + + self.was_locked_net = not self.ap_is_enabled(AHB_AP_NET_NUM) + + if not self.ap_is_enabled(AHB_AP_NET_NUM): + if self.session.options.get('auto_unlock'): + LOG.warning("%s NET CORE APPROTECT enabled: will try to unlock via mass erase", self.part_number) + self.mass_erase_net() + self._discoverer._create_1_ap(AHB_AP_NET_NUM) + else: + LOG.info("%s NET not in secure state", self.part_number) + + + def is_eraseprotected(self, ctrl_ap): + status = ctrl_ap.read_reg(CTRL_AP_ERASEPROTECTSTATUS) + return status & CTRL_AP_ERASEPROTECTSTATUS_MSK == 0 + + def mass_erase(self): + self.mass_erase_app() + self.mass_erase_net() + + def mass_erase_app(self): + if self.is_eraseprotected(self.ctrl_ap_app): + LOG.warning("ERASEPROTECT is enabled.") + if self.was_locked_app: + LOG.error("If the firmware supports unlocking with a known 32-bit key,") + LOG.error("then this is the only way to recover the device.") + return False + else: + LOG.warning("Performing a chip erase instead.") + eraser = FlashEraser(self.session, FlashEraser.Mode.CHIP) + eraser._log_chip_erase = False + eraser.erase() + return True + self.mass_erase_ctrl_ap(self.ctrl_ap_app) + + + def mass_erase_net(self): + self.mass_erase_ctrl_ap(self.ctrl_ap_net) + + def mass_erase_ctrl_ap(self, ctrl_ap): + # See Nordic Whitepaper nWP-027 for magic numbers and order of operations from the vendor + ctrl_ap.write_reg(CTRL_AP_ERASEALL, CTRL_AP_ERASEALL_ERASE) + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + status = ctrl_ap.read_reg(CTRL_AP_ERASEALLSTATUS) + if status == CTRL_AP_ERASEALLSTATUS_READY: + break + sleep(0.5) + else: + # Timed out + LOG.error("Mass erase timeout waiting for ERASEALLSTATUS") + return False + sleep(0.01) + ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_RESET) + ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_NORESET) + sleep(0.2) + return True + + def check_part_info(self): + partno = self.read32(0x00FF020C) + variant = self.read32(0x00FF0210) + + LOG.info(f"This appears to be an nRF{partno:X} " + + f"{word_to_bytes(variant)[::-1].decode('ASCII', errors='ignore')} ") + + def persist_unlock_app(self): + if self.session.options.get('auto_unlock'): + # Write Unprotected to UICR.APPROTECT + self.write_uicr_app(0x00FF8000, 0x50FA50FA) + + # Write Unprotected to UICR.SECUREAPPROTECT + self.write_uicr_app(0x00FF801C, 0x50FA50FA) + + if self.was_locked_app: + # write unlock image + LOG.info("writing empty APP image to persist unlock") + self.write_flash_app(0, nrf53_app_empty_image) + + def persist_unlock_net(self): + if self.session.options.get('auto_unlock'): + # Write Unprotected to UICR.APPROTECT + self.write_uicr_net(0x01FF8000, 0x50FA50FA) + + if self.was_locked_net: + # write unlock image + LOG.info("writing empty NET image to persist unlock") + self.write_flash_net(0x01000000, nrf53_net_empty_image) + + def write_uicr_app(self, addr: int, value: int): + return self._write_uicr(addr, value, self.cores[0], 0x50039000) + + def write_uicr_net(self, addr: int, value: int): + return self._write_uicr(addr, value, self.cores[1], 0x41080000) + + def write_flash_app(self, addr: int, bytes): + return self._write_flash(addr, bytes, self.cores[0], 0x50039000) + + def write_flash_net(self, addr: int, bytes): + return self._write_flash(addr, bytes, self.cores[1], 0x41080000) + + def _write_uicr(self, addr: int, value: int, core, nvmc_base): + current_value = core.read32(addr) + if ((current_value & value) != value) and (current_value != 0xFFFFFFFF): + raise exceptions.TargetError("cannot write UICR value, mass_erase needed") + + core.write32(nvmc_base + 0x504, 1) # NVMC.CONFIG = WriteEnable + self._wait_nvmc_ready(core, nvmc_base) + core.write32(addr, value) + self._wait_nvmc_ready(core, nvmc_base) + core.write32(nvmc_base + 0x504, 0) # NVMC.CONFIG = ReadOnly + self._wait_nvmc_ready(core, nvmc_base) + + def _write_flash(self, addr: int, bytes, core, nvmc_base): + assert len(bytes) % 4 == 0, "only full words can be written" + core.write32(nvmc_base + 0x504, 1) # NVMC.CONFIG = WriteEnable + self._wait_nvmc_ready(core, nvmc_base) + for off in range(0, len(bytes), 4): + core.write32(addr+off, bytes_to_word(bytes[off:off+4])) + self._wait_nvmc_readynext(core, nvmc_base) + core.write32(nvmc_base + 0x504, 0) # NVMC.CONFIG = ReadOnly + self._wait_nvmc_ready(core, nvmc_base) + + def _wait_nvmc_ready(self, core, nvmc_base): + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + if core.read32(nvmc_base + 0x400) != 0x00000000: # NVMC.READY != BUSY + break + else: + raise exceptions.TargetError("wait for NVMC timed out") + + def _wait_nvmc_readynext(self, core, nvmc_base): + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + if core.read32(nvmc_base + 0x408) != 0x00000000: # NVMC.READYNEXT != BUSY + break + else: + raise exceptions.TargetError("wait for NVMC timed out")