diff --git a/pyocd/debug/svd/data/EG32M0x.svd b/pyocd/debug/svd/data/EG32M0x.svd new file mode 100644 index 000000000..42ac8edf6 --- /dev/null +++ b/pyocd/debug/svd/data/EG32M0x.svd @@ -0,0 +1,15400 @@ + + + EGmicro Ltd. + + EGmicro + + EG32M0x + + EG32M0x + + 1.0 + + EGmicro 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 72MHz, etc. + + + EGmicro Limited (EGmicro) is supplying this software for use with Cortex-M0! + + + + CM0 + r0p0 + little + false + false + 3 + false + + 8 + + 32 + + + 32 + + read-write + + 0x00000000 + + 0xFFFFFFFF + + + + + + FLASH + FLASH unit + FLASH + 0x40020240 + + 0x0 + 0x50 + registers + + + + CTRL0 + CTRL0 + CTRL0 + 0x00 + 0x20 + read-write + 0x00001000 + + + 20 + 1 + EMIE + multiple bit error interrpution enable + + + 19 + 1 + EDIE + one bit error interrpution enable + + + 18 + 1 + FWUP + EFLASH fast wake-up enable + + + 16 + 1 + PCS + FLASH burning clock source selection + + + 12 + 1 + PRCE + Add CRC value at the end when moving RAM data to FLASH + + + 11 + 1 + LPS + Is it allowed to interrupt FLASH programming and erase except + + + 10 + 1 + PRM + Directly write RAM data to FLASH + + + + + KST + KST + KST + 0x04 + 0x20 + read-write + 0x00000000 + + + 26 + 1 + CKE + CRC trigger enable of FLASH + + + 10 + 1 + CK + CRC check trigger of FLASH + + + + + DONE + DONE + DONE + 0x08 + 0x20 + read-write + 0x00001c53 + + + 12 + 1 + CEOF + Chip erases results + + + 11 + 1 + POF + As a result of programming + + + 10 + 1 + CD + CRC completion flag of FLASH + + + 6 + 1 + PD + End of program flag + + + 1 + 1 + CED + The Main field is fully erased + + + 0 + 1 + SED + Sector erase flag + + + + + PROG_ADDR + PROG_ADDR + PROG_ADDR + 0x0C + 0x20 + read-write + 0x80000000 + + + 29 + 1 + PNS + Choose MAIN/NVR as the programming address + + + 0 + 16 + ADDR + FLASH programming logical address + + + + + PROG_DATA + PROG_DATA + PROG_DATA + 0x10 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DATA + Configure PROG_DATA to start programming or display data when going to FLASH programming + + + + + ERASE_CTRL + ERASE_CTRL + ERASE_CTRL + 0x14 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + CEK + Trigger for Chip erase + + + 30 + 1 + SEK + Trigger for sector erase + + + 29 + 1 + NSE + Sector enable bit of the NVR + + + 0 + 7 + SEA + Erase the sector selection + + + + + TIME_REG0 + TIME_REG0 + TIME_REG0 + 0x18 + 0x20 + read-write + 0x7efdfbf2 + + + 25 + 7 + PGH + WE high to PROG2 high hold min time is 500ns + + + 18 + 7 + ADS + BYTE/Address/data setup min time is 500ns + + + 11 + 7 + ADH + BYTE/Address/data hold min time is 500ns + + + 4 + 7 + RW + Latency to next operation after PROG/sector ERASE low min time is 500ns + + + 0 + 4 + RC + Read flash cycle + + + + + TIME_REG1 + TIME_REG1 + TIME_REG1 + 0x1C + 0x20 + read-write + 0x0003e810 + + + 8 + 11 + MCS + 1ms Time configuration value, in the unit of 1us + + + 0 + 8 + UCS + The clock frequency is 32MHz by default 2 frequency division + + + + + NVR_PWD + NVR_PWD + NVR_PWD + 0x20 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + NPW + NVR area password + + + + + MAIN_PWD + MAIN_PWD + MAIN_PWD + 0x24 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + MPW + MAIN area password + + + + + CRC_ADDR + CRC_ADDR + CRC_ADDR + 0x28 + 0x20 + read-write + 0x00000000 + + + 29 + 1 + NS + Whether the address is an NVR zone + + + 2 + 27 + CA + Set this parameter to the start address of the CRC check + + + + + CRC_LEN + CRC_LEN + CRC_LEN + 0x2C + 0x20 + read-write + 0x00000000 + + + 2 + 15 + CL + FLASH verifies the data length of the CRC + + + + + CRC_OUT + CRC_OUT + CRC_OUT + 0x30 + 0x20 + read-write + 0x5a5a55aa + + + 0 + 32 + CO + CRC results + + + + + CFG_SECTOR + CFG_SECTOR + CFG_SECTOR + 0x40 + 0x20 + read-write + 0x00000380 + + + 16 + 2 + RS + Size of RAM + + + 0 + 16 + MSN + sector number of the EFLASH MAIN + + + + + + + + + + CRC + CRC unit + CRC + 0x40020210 + + 0x0 + 0x20 + registers + + + + CFG + CFG + CFG + 0x00 + 0x20 + read-write + 0x00000100 + + + 8 + 1 + PW + Polynomial width + + + 1 + 1 + BO + Check order of input data + + + 0 + 1 + EN + CRC enablement + + + + + INIT + INIT + INIT + 0x04 + 0x20 + read-write + 0xffffffff + + + 0 + 32 + INITV + CRC initial value + + + + + INV + INV + INV + 0x08 + 0x20 + read-write + 0xffffffff + + + 0 + 32 + INVV + CRC output takes reverse control + + + + + POLY + POLY + POLY + 0x0C + 0x20 + read-write + 0xedb88320 + + + 0 + 32 + PV + CRC polynomial value + + + + + STA + STA + STA + 0x10 + 0x20 + read-write + 0x00000000 + + + 0 + 1 + BUSY + CRC busy state + + + + + DATA + DATA + DATA + 0x14 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DATA + CRC data register + + + + + LEN + LEN + LEN + 0x18 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + LENGTH + CRC Indicates the byte length of the verification data + + + + + + + + + + HWDIV + HWDIV unit + HWDIV + 0x400203A0 + + 0x0 + 0x20 + registers + + + + DR + DR + DR + 0x00 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DIVDR + Dividend data + + + + + SR + SR + SR + 0x04 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DIVSR + Divisor data + + + + + QUO + QUO + QUO + 0x08 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DIVQUO + Quotient result + + + + + REM + REM + REM + 0x0C + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DIVREM + Remainder result + + + + + CR + CR + CR + 0x10 + 0x20 + read-write + 0x00000000 + + + 2 + 1 + UNSIGN + Operation symbol bit control + + + 1 + 1 + DIE + End of operation interrupt control bit + + + 0 + 1 + DIV0IE + Divisor is 0 interrupt control bit + + + + + STA + STA + STA + 0x14 + 0x20 + read-write + 0x00000000 + + + 1 + 1 + DP + End of operation flag bit + + + 0 + 1 + DIV0P + The divisor is 0 + + + + + + + + + + POWER_MAN + POWER MANAGEMENT unit + POWER MANAGEMENT + 0x40020120 + + 0x0 + 0x10 + registers + + + + LVDCON + LVDCON + LVDCON + 0x00 + 0x20 + read-write + 0x00000e15 + + + 31 + 1 + VDDP + When the VDD voltage is lower than the threshold, the PEND is triggered + + + 30 + 1 + VCCP + When the VCC voltage is lower than the threshold, the PEND is triggered + + + 29 + 1 + VDDLAOD + VDD_LVD Analog signal output is enabled + + + 22 + 7 + DLLS + Low level burr filter width for PMU_LVD_VDD signal The degree of + + + 15 + 7 + DHLS + High level burr filter width for PMU_LVD_VDD signal The degree of + + + 14 + 1 + VSD + VCC_LVD Indicates whether to wake up the CPU in interrupt mode The system clock must be synchronized first + + + 13 + 1 + VDDSDE + Mask the filtering processing of PMU_VDD_LVD signal + + + 12 + 1 + VCCSDE + Mask the filtering processing of PMU_VCC_LVD signal + + + 11 + 1 + LDE + LVD digital switch + + + 10 + 1 + VDDRE + The system reset function is enabled after the VDD threshold is triggered + + + 9 + 1 + VCCRE + The system reset function is enabled after the VCC threshold is triggered + + + 8 + 1 + VCCLAOD + VCC_LVD Analog signal output is enabled + + + 5 + 3 + VDDLS + VDD_LVD Voltage detection Setting + + + 4 + 1 + VDDLE + VDD_LVD analog switch + + + 1 + 3 + VCCLS + VCC_LVD Voltage detection Setting + + + 0 + 1 + VCCLE + VCC_LVD analog switch + + + + + LVDCON1 + LVDCON1 + LVDCON1 + 0x04 + 0x20 + read-write + 0x00000000 + + + 8 + 7 + VDLL + Low level burr filter width for PMU_LVD_VCC signal The degree of + + + 0 + 7 + VDHL + High level burr filter width for PMU_LVD_VCC signal The degree of + + + + + + + + + + GPIOA + GPIOA unit + GPIOA + 0x400200A0 + + 0x0 + 0x40 + registers + + + + MODE + MODE + MODE + 0x00 + 0x20 + read-write + 0x00000000 + + + 30 + 2 + MODER15 + The mode bit of GPIOA PIN15 + + + 28 + 2 + MODER14 + The mode bit of GPIOA PIN14 + + + 26 + 2 + MODER13 + The mode bit of GPIOA PIN13 + + + 24 + 2 + MODER12 + The mode bit of GPIOA PIN12 + + + 22 + 2 + MODER11 + The mode bit of GPIOA PIN11 + + + 20 + 2 + MODER10 + The mode bit of GPIOA PIN10 + + + 18 + 2 + MODER9 + The mode bit of GPIOA PIN9 + + + 16 + 2 + MODER8 + The mode bit of GPIOA PIN8 + + + 14 + 2 + MODER7 + The mode bit of GPIOA PIN7 + + + 12 + 2 + MODER6 + The mode bit of GPIOA PIN6 + + + 10 + 2 + MODER5 + The mode bit of GPIOA PIN5 + + + 8 + 2 + MODER4 + The mode bit of GPIOA PIN4 + + + 6 + 2 + MODER3 + The mode bit of GPIOA PIN3 + + + 4 + 2 + MODER2 + The mode bit of GPIOA PIN2 + + + 2 + 2 + MODER1 + The mode bit of GPIOA PIN1 + + + 0 + 2 + MODER0 + The mode bit of GPIOA PIN0 + + + + + OTYPE + OTYPE + OTYPE + 0x04 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OTYPE15 + The output type selection bit of GPIOA PIN15 + + + 14 + 1 + OTYPE14 + The output type selection bit of GPIOA PIN14 + + + 13 + 1 + OTYPE13 + The output type selection bit of GPIOA PIN13 + + + 12 + 1 + OTYPE12 + The output type selection bit of GPIOA PIN12 + + + 11 + 1 + OTYPE11 + The output type selection bit of GPIOA PIN11 + + + 10 + 1 + OTYPE10 + The output type selection bit of GPIOA PIN10 + + + 9 + 1 + OTYPE9 + The output type selection bit of GPIOA PIN9 + + + 8 + 1 + OTYPE8 + The output type selection bit of GPIOA PIN8 + + + 7 + 1 + OTYPE7 + The output type selection bit of GPIOA PIN7 + + + 6 + 1 + OTYPE6 + The output type selection bit of GPIOA PIN6 + + + 5 + 1 + OTYPE5 + The output type selection bit of GPIOA PIN5 + + + 4 + 1 + OTYPE4 + The output type selection bit of GPIOA PIN4 + + + 3 + 1 + OTYPE3 + The output type selection bit of GPIOA PIN3 + + + 2 + 1 + OTYPE2 + The output type selection bit of GPIOA PIN2 + + + 1 + 1 + OTYPE1 + The output type selection bit of GPIOA PIN1 + + + 0 + 1 + OTYPE0 + The output type selection bit of GPIOA PIN0 + + + + + OSPEED + OSPEED + OSPEED + 0x08 + 0x20 + read-write + 0x00000000 + + + 30 + 2 + OSPEED15 + The Speed gear selection bit of GPIOA PIN15 + + + 28 + 2 + OSPEED14 + The Speed gear selection bit of GPIOA PIN14 + + + 26 + 2 + OSPEED13 + The Speed gear selection bit of GPIOA PIN13 + + + 24 + 2 + OSPEED12 + The Speed gear selection bit of GPIOA PIN12 + + + 22 + 2 + OSPEED11 + The Speed gear selection bit of GPIOA PIN11 + + + 20 + 2 + OSPEED10 + The Speed gear selection bit of GPIOA PIN10 + + + 18 + 2 + OSPEED9 + The Speed gear selection bit of GPIOA PIN9 + + + 16 + 2 + OSPEED8 + The Speed gear selection bit of GPIOA PIN8 + + + 14 + 2 + OSPEED7 + The Speed gear selection bit of GPIOA PIN7 + + + 12 + 2 + OSPEED6 + The Speed gear selection bit of GPIOA PIN6 + + + 10 + 2 + OSPEED5 + The Speed gear selection bit of GPIOA PIN5 + + + 8 + 2 + OSPEED4 + The Speed gear selection bit of GPIOA PIN4 + + + 6 + 2 + OSPEED3 + The Speed gear selection bit of GPIOA PIN3 + + + 4 + 2 + OSPEED2 + The Speed gear selection bit of GPIOA PIN2 + + + 2 + 2 + OSPEED1 + The Speed gear selection bit of GPIOA PIN1 + + + 0 + 2 + OSPEED0 + The Speed gear selection bit of GPIOA PIN0 + + + + + PUPD + PUPD + PUPD + 0x10 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + PD15 + The drop-down enable bit of GPIOA PIN15 + + + 30 + 1 + PD14 + The drop-down enable bit of GPIOA PIN14 + + + 29 + 1 + PD13 + The drop-down enable bit of GPIOA PIN13 + + + 28 + 1 + PD12 + The drop-down enable bit of GPIOA PIN12 + + + 27 + 1 + PD11 + The drop-down enable bit of GPIOA PIN11 + + + 26 + 1 + PD10 + The drop-down enable bit of GPIOA PIN10 + + + 25 + 1 + PD9 + The drop-down enable bit of GPIOA PIN9 + + + 24 + 1 + PD8 + The drop-down enable bit of GPIOA PIN8 + + + 23 + 1 + PD7 + The drop-down enable bit of GPIOA PIN7 + + + 22 + 1 + PD6 + The drop-down enable bit of GPIOA PIN6 + + + 21 + 1 + PD5 + The drop-down enable bit of GPIOA PIN5 + + + 20 + 1 + PD4 + The drop-down enable bit of GPIOA PIN4 + + + 19 + 1 + PD3 + The drop-down enable bit of GPIOA PIN3 + + + 18 + 1 + PD2 + The drop-down enable bit of GPIOA PIN2 + + + 17 + 1 + PD1 + The drop-down enable bit of GPIOA PIN1 + + + 16 + 1 + PD0 + The drop-down enable bit of GPIOA PIN0 + + + 15 + 1 + PU15 + The pull-up enable bit of GPIOA PIN15 + + + 14 + 1 + PU14 + The pull-up enable bit of GPIOA PIN14 + + + 13 + 1 + PU13 + The pull-up enable bit of GPIOA PIN13 + + + 12 + 1 + PU12 + The pull-up enable bit of GPIOA PIN12 + + + 11 + 1 + PU11 + The pull-up enable bit of GPIOA PIN11 + + + 10 + 1 + PU10 + The pull-up enable bit of GPIOA PIN10 + + + 9 + 1 + PU9 + The pull-up enable bit of GPIOA PIN9 + + + 8 + 1 + PU8 + The pull-up enable bit of GPIOA PIN8 + + + 7 + 1 + PU7 + The pull-up enable bit of GPIOA PIN7 + + + 6 + 1 + PU6 + The pull-up enable bit of GPIOA PIN6 + + + 5 + 1 + PU5 + The pull-up enable bit of GPIOA PIN5 + + + 4 + 1 + PU4 + The pull-up enable bit of GPIOA PIN4 + + + 3 + 1 + PU3 + The pull-up enable bit of GPIOA PIN3 + + + 2 + 1 + PU2 + The pull-up enable bit of GPIOA PIN2 + + + 1 + 1 + PU1 + The pull-up enable bit of GPIOA PIN1 + + + 0 + 1 + PU0 + The pull-up enable bit of GPIOA PIN0 + + + + + IDAT + IDAT + IDAT + 0x14 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + IDAT15 + The Input data bit of GPIOA PIN15 + + + 14 + 1 + IDAT14 + The Input data bit of GPIOA PIN14 + + + 13 + 1 + IDAT13 + The Input data bit of GPIOA PIN13 + + + 12 + 1 + IDAT12 + The Input data bit of GPIOA PIN12 + + + 11 + 1 + IDAT11 + The Input data bit of GPIOA PIN11 + + + 10 + 1 + IDAT10 + The Input data bit of GPIOA PIN10 + + + 9 + 1 + IDAT9 + The Input data bit of GPIOA PIN9 + + + 8 + 1 + IDAT8 + The Input data bit of GPIOA PIN8 + + + 7 + 1 + IDAT7 + The Input data bit of GPIOA PIN7 + + + 6 + 1 + IDAT6 + The Input data bit of GPIOA PIN6 + + + 5 + 1 + IDAT5 + The Input data bit of GPIOA PIN5 + + + 4 + 1 + IDAT4 + The Input data bit of GPIOA PIN4 + + + 3 + 1 + IDAT3 + The Input data bit of GPIOA PIN3 + + + 2 + 1 + IDAT2 + The Input data bit of GPIOA PIN2 + + + 1 + 1 + IDAT1 + The Input data bit of GPIOA PIN1 + + + 0 + 1 + IDAT0 + The Input data bit of GPIOA PIN0 + + + + + ODAT + ODAT + ODAT + 0x18 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ODAT15 + The output data bit of GPIOA PIN15 + + + 14 + 1 + ODAT14 + The output data bit of GPIOA PIN14 + + + 13 + 1 + ODAT13 + The output data bit of GPIOA PIN13 + + + 12 + 1 + ODAT12 + The output data bit of GPIOA PIN12 + + + 11 + 1 + ODAT11 + The output data bit of GPIOA PIN11 + + + 10 + 1 + ODAT10 + The output data bit of GPIOA PIN10 + + + 9 + 1 + ODAT9 + The output data bit of GPIOA PIN9 + + + 8 + 1 + ODAT8 + The output data bit of GPIOA PIN8 + + + 7 + 1 + ODAT7 + The output data bit of GPIOA PIN7 + + + 6 + 1 + ODAT6 + The output data bit of GPIOA PIN6 + + + 5 + 1 + ODAT5 + The output data bit of GPIOA PIN5 + + + 4 + 1 + ODAT4 + The output data bit of GPIOA PIN4 + + + 3 + 1 + ODAT3 + The output data bit of GPIOA PIN3 + + + 2 + 1 + ODAT2 + The output data bit of GPIOA PIN2 + + + 1 + 1 + ODAT1 + The output data bit of GPIOA PIN1 + + + 0 + 1 + ODAT0 + The output data bit of GPIOA PIN0 + + + + + BSR + BSR + BSR + 0x1C + 0x20 + read-write + 0x00000000 + + + 31 + 1 + BR15 + The Clear bit of GPIOA PIN15 + + + 30 + 1 + BR14 + The Clear bit of GPIOA PIN14 + + + 29 + 1 + BR13 + The Clear bit of GPIOA PIN13 + + + 28 + 1 + BR12 + The Clear bit of GPIOA PIN12 + + + 27 + 1 + BR11 + The Clear bit of GPIOA PIN11 + + + 26 + 1 + BR10 + The Clear bit of GPIOA PIN10 + + + 25 + 1 + BR9 + The Clear bit of GPIOA PIN9 + + + 24 + 1 + BR8 + The Clear bit of GPIOA PIN8 + + + 23 + 1 + BR7 + The Clear bit of GPIOA PIN7 + + + 22 + 1 + BR6 + The Clear bit of GPIOA PIN6 + + + 21 + 1 + BR5 + The Clear bit of GPIOA PIN5 + + + 20 + 1 + BR4 + The Clear bit of GPIOA PIN4 + + + 19 + 1 + BR3 + The Clear bit of GPIOA PIN3 + + + 18 + 1 + BR2 + The Clear bit of GPIOA PIN2 + + + 17 + 1 + BR1 + The Clear bit of GPIOA PIN1 + + + 16 + 1 + BR0 + The Clear bit of GPIOA PIN0 + + + 15 + 1 + BS15 + The setting bit of GPIOA PIN15 + + + 14 + 1 + BS14 + The setting bit of GPIOA PIN14 + + + 13 + 1 + BS13 + The setting bit of GPIOA PIN13 + + + 12 + 1 + BS12 + The setting bit of GPIOA PIN12 + + + 11 + 1 + BS11 + The setting bit of GPIOA PIN11 + + + 10 + 1 + BS10 + The setting bit of GPIOA PIN10 + + + 9 + 1 + BS9 + The setting bit of GPIOA PIN9 + + + 8 + 1 + BS8 + The setting bit of GPIOA PIN8 + + + 7 + 1 + BS7 + The setting bit of GPIOA PIN7 + + + 6 + 1 + BS6 + The setting bit of GPIOA PIN6 + + + 5 + 1 + BS5 + The setting bit of GPIOA PIN5 + + + 4 + 1 + BS4 + The setting bit of GPIOA PIN4 + + + 3 + 1 + BS3 + The setting bit of GPIOA PIN3 + + + 2 + 1 + BS2 + The setting bit of GPIOA PIN2 + + + 1 + 1 + BS1 + The setting bit of GPIOA PIN1 + + + 0 + 1 + BS0 + The setting bit of GPIOA PIN0 + + + + + LCK + LCK + LCK + 0x20 + 0x20 + read-write + 0x00000000 + + + 16 + 1 + LCKK + The locking mechanism valid bit of GPIOA + + + 15 + 1 + LCK15 + The lock enable bit of GPIOA PIN15 + + + 14 + 1 + LCK14 + The lock enable bit of GPIOA PIN14 + + + 13 + 1 + LCK13 + The lock enable bit of GPIOA PIN13 + + + 12 + 1 + LCK12 + The lock enable bit of GPIOA PIN12 + + + 11 + 1 + LCK11 + The lock enable bit of GPIOA PIN11 + + + 10 + 1 + LCK10 + The lock enable bit of GPIOA PIN10 + + + 9 + 1 + LCK9 + The lock enable bit of GPIOA PIN9 + + + 8 + 1 + LCK8 + The lock enable bit of GPIOA PIN8 + + + 7 + 1 + LCK7 + The lock enable bit of GPIOA PIN7 + + + 6 + 1 + LCK6 + The lock enable bit of GPIOA PIN6 + + + 5 + 1 + LCK5 + The lock enable bit of GPIOA PIN5 + + + 4 + 1 + LCK4 + The lock enable bit of GPIOA PIN4 + + + 3 + 1 + LCK3 + The lock enable bit of GPIOA PIN3 + + + 2 + 1 + LCK2 + The lock enable bit of GPIOA PIN2 + + + 1 + 1 + LCK1 + The lock enable bit of GPIOA PIN1 + + + 0 + 1 + LCK0 + The lock enable bit of GPIOA PIN0 + + + + + AFRL + AFRL + AFRL + 0x24 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + AFR7 + GPIOA[7] multiplexed channel selection bit + + + 24 + 4 + AFR6 + GPIOA[6] multiplexed channel selection bit + + + 20 + 4 + AFR5 + GPIOA[5] multiplexed channel selection bit + + + 16 + 4 + AFR4 + GPIOA[4] multiplexed channel selection bit + + + 12 + 4 + AFR3 + GPIOA[3] multiplexed channel selection bit + + + 8 + 4 + AFR2 + GPIOA[2] multiplexed channel selection bit + + + 4 + 4 + AFR1 + GPIOA[1] multiplexed channel selection bit + + + 0 + 4 + AFR0 + GPIOA[0] multiplexed channel selection bit + + + + + AFRH + AFRH + AFRH + 0x28 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + AFR15 + GPIOA[15] multiplexed channel selection bit + + + 24 + 4 + AFR14 + GPIOA[14] multiplexed channel selection bit + + + 20 + 4 + AFR13 + GPIOA[13] multiplexed channel selection bit + + + 16 + 4 + AFR12 + GPIOA[12] multiplexed channel selection bit + + + 12 + 4 + AFR11 + GPIOA[11] multiplexed channel selection bit + + + 8 + 4 + AFR10 + GPIOA[10] multiplexed channel selection bit + + + 4 + 4 + AFR9 + GPIOA[9] multiplexed channel selection bit + + + 0 + 4 + AFR8 + GPIOA[8] multiplexed channel selection bit + + + + + TGL + TGL + TGL + 0x2C + 0x20 + read-write + 0x00000000 + + + 15 + 1 + TG15 + The flip bit of GPIOA PIN15 + + + 14 + 1 + TG14 + The flip bit of GPIOA PIN14 + + + 13 + 1 + TG13 + The flip bit of GPIOA PIN13 + + + 12 + 1 + TG12 + The flip bit of GPIOA PIN12 + + + 11 + 1 + TG11 + The flip bit of GPIOA PIN11 + + + 10 + 1 + TG10 + The flip bit of GPIOA PIN10 + + + 9 + 1 + TG9 + The flip bit of GPIOA PIN9 + + + 8 + 1 + TG8 + The flip bit of GPIOA PIN8 + + + 7 + 1 + TG7 + The flip bit of GPIOA PIN7 + + + 6 + 1 + TG6 + The flip bit of GPIOA PIN6 + + + 5 + 1 + TG5 + The flip bit of GPIOA PIN5 + + + 4 + 1 + TG4 + The flip bit of GPIOA PIN4 + + + 3 + 1 + TG3 + The flip bit of GPIOA PIN3 + + + 2 + 1 + TG2 + The flip bit of GPIOA PIN2 + + + 1 + 1 + TG1 + The flip bit of GPIOA PIN1 + + + 0 + 1 + TG0 + The flip bit of GPIOA PIN0 + + + + + IMK + IMK + IMK + 0x30 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + IMK15 + The Interrupt enable bit of GPIOA PIN15 + + + 14 + 1 + IMK14 + The Interrupt enable bit of GPIOA PIN14 + + + 13 + 1 + IMK13 + The Interrupt enable bit of GPIOA PIN13 + + + 12 + 1 + IMK12 + The Interrupt enable bit of GPIOA PIN12 + + + 11 + 1 + IMK11 + The Interrupt enable bit of GPIOA PIN11 + + + 10 + 1 + IMK10 + The Interrupt enable bit of GPIOA PIN10 + + + 9 + 1 + IMK9 + The Interrupt enable bit of GPIOA PIN9 + + + 8 + 1 + IMK8 + The Interrupt enable bit of GPIOA PIN8 + + + 7 + 1 + IMK7 + The Interrupt enable bit of GPIOA PIN7 + + + 6 + 1 + IMK6 + The Interrupt enable bit of GPIOA PIN6 + + + 5 + 1 + IMK5 + The Interrupt enable bit of GPIOA PIN5 + + + 4 + 1 + IMK4 + The Interrupt enable bit of GPIOA PIN4 + + + 3 + 1 + IMK3 + The Interrupt enable bit of GPIOA PIN3 + + + 2 + 1 + IMK2 + The Interrupt enable bit of GPIOA PIN2 + + + 1 + 1 + IMK1 + The Interrupt enable bit of GPIOA PIN1 + + + 0 + 1 + IMK0 + The Interrupt enable bit of GPIOA PIN0 + + + + + TGPEND + TGPEND + TGPEND + 0x34 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + TP15 + The input edge detection flag bit of GPIOA PIN15 + + + 14 + 1 + TP14 + The input edge detection flag bit of GPIOA PIN14 + + + 13 + 1 + TP13 + The input edge detection flag bit of GPIOA PIN13 + + + 12 + 1 + TP12 + The input edge detection flag bit of GPIOA PIN12 + + + 11 + 1 + TP11 + The input edge detection flag bit of GPIOA PIN11 + + + 10 + 1 + TP10 + The input edge detection flag bit of GPIOA PIN10 + + + 9 + 1 + TP9 + The input edge detection flag bit of GPIOA PIN9 + + + 8 + 1 + TP8 + The input edge detection flag bit of GPIOA PIN8 + + + 7 + 1 + TP7 + The input edge detection flag bit of GPIOA PIN7 + + + 6 + 1 + TP6 + The input edge detection flag bit of GPIOA PIN6 + + + 5 + 1 + TP5 + The input edge detection flag bit of GPIOA PIN5 + + + 4 + 1 + TP4 + The input edge detection flag bit of GPIOA PIN4 + + + 3 + 1 + TP3 + The input edge detection flag bit of GPIOA PIN3 + + + 2 + 1 + TP2 + The input edge detection flag bit of GPIOA PIN2 + + + 1 + 1 + TP1 + The input edge detection flag bit of GPIOA PIN1 + + + 0 + 1 + TP0 + The input edge detection flag bit of GPIOA PIN0 + + + + + IE_EN + IE_EN + IE_EN + 0x38 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + GA15IEE + The input force enable bit of GPIOA PIN15 + + + 14 + 1 + GA14IEE + The input force enable bit of GPIOA PIN14 + + + 13 + 1 + GA13IEE + The input force enable bit of GPIOA PIN13 + + + 12 + 1 + GA12IEE + The input force enable bit of GPIOA PIN12 + + + 11 + 1 + GA11IEE + The input force enable bit of GPIOA PIN11 + + + 10 + 1 + GA10IEE + The input force enable bit of GPIOA PIN10 + + + 9 + 1 + GA9IEE + The input force enable bit of GPIOA PIN9 + + + 8 + 1 + GA8IEE + The input force enable bit of GPIOA PIN8 + + + 7 + 1 + GA7IEE + The input force enable bit of GPIOA PIN7 + + + 6 + 1 + GA6IEE + The input force enable bit of GPIOA PIN6 + + + 5 + 1 + GA5IEE + The input force enable bit of GPIOA PIN5 + + + 4 + 1 + GA4IEE + The input force enable bit of GPIOA PIN4 + + + 3 + 1 + GA3IEE + The input force enable bit of GPIOA PIN3 + + + 2 + 1 + GA2IEE + The input force enable bit of GPIOA PIN2 + + + 1 + 1 + GA1IEE + The input force enable bit of GPIOA PIN1 + + + 0 + 1 + GA0IEE + The input force enable bit of GPIOA PIN0 + + + + + TG_EDGE + TG_EDGE + TG_EDGE + 0x3C + 0x20 + read-write + 0x00000000 + + + 30 + 2 + TGD15 + Detection control bit of the input edge of GPIOA PIN15 + + + 28 + 2 + TGD14 + Detection control bit of the input edge of GPIOA PIN14 + + + 26 + 2 + TGD13 + Detection control bit of the input edge of GPIOA PIN13 + + + 24 + 2 + TGD12 + Detection control bit of the input edge of GPIOA PIN12 + + + 22 + 2 + TGD11 + Detection control bit of the input edge of GPIOA PIN11 + + + 20 + 2 + TGD10 + Detection control bit of the input edge of GPIOA PIN10 + + + 18 + 2 + TGD9 + Detection control bit of the input edge of GPIOA PIN9 + + + 16 + 2 + TGD8 + Detection control bit of the input edge of GPIOA PIN8 + + + 14 + 2 + TGD7 + Detection control bit of the input edge of GPIOA PIN7 + + + 12 + 2 + TGD6 + Detection control bit of the input edge of GPIOA PIN6 + + + 10 + 2 + TGD5 + Detection control bit of the input edge of GPIOA PIN5 + + + 8 + 2 + TGD4 + Detection control bit of the input edge of GPIOA PIN4 + + + 6 + 2 + TGD3 + Detection control bit of the input edge of GPIOA PIN3 + + + 4 + 2 + TGD2 + Detection control bit of the input edge of GPIOA PIN2 + + + 2 + 2 + TGD1 + Detection control bit of the input edge of GPIOA PIN1 + + + 0 + 2 + TGD0 + Detection control bit of the input edge of GPIOA PIN0 + + + + + + + + + + GPIOB + GPIOB unit + GPIOB + 0x400200E0 + + 0x0 + 0x40 + registers + + + + MODE + MODE + MODE + 0x00 + 0x20 + read-write + 0x00000000 + + + 30 + 2 + MODER15 + The mode bit of GPIOB PIN15 + + + 28 + 2 + MODER14 + The mode bit of GPIOB PIN14 + + + 26 + 2 + MODER13 + The mode bit of GPIOB PIN13 + + + 24 + 2 + MODER12 + The mode bit of GPIOB PIN12 + + + 22 + 2 + MODER11 + The mode bit of GPIOB PIN11 + + + 20 + 2 + MODER10 + The mode bit of GPIOB PIN10 + + + 18 + 2 + MODER9 + The mode bit of GPIOB PIN9 + + + 16 + 2 + MODER8 + The mode bit of GPIOB PIN8 + + + 14 + 2 + MODER7 + The mode bit of GPIOB PIN7 + + + 12 + 2 + MODER6 + The mode bit of GPIOB PIN6 + + + 10 + 2 + MODER5 + The mode bit of GPIOB PIN5 + + + 8 + 2 + MODER4 + The mode bit of GPIOB PIN4 + + + 6 + 2 + MODER3 + The mode bit of GPIOB PIN3 + + + 4 + 2 + MODER2 + The mode bit of GPIOB PIN2 + + + 2 + 2 + MODER1 + The mode bit of GPIOB PIN1 + + + 0 + 2 + MODER0 + The mode bit of GPIOB PIN0 + + + + + OTYPE + OTYPE + OTYPE + 0x04 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OTYPE15 + The output type selection bit of GPIOB PIN15 + + + 14 + 1 + OTYPE14 + The output type selection bit of GPIOB PIN14 + + + 13 + 1 + OTYPE13 + The output type selection bit of GPIOB PIN13 + + + 12 + 1 + OTYPE12 + The output type selection bit of GPIOB PIN12 + + + 11 + 1 + OTYPE11 + The output type selection bit of GPIOB PIN11 + + + 10 + 1 + OTYPE10 + The output type selection bit of GPIOB PIN10 + + + 9 + 1 + OTYPE9 + The output type selection bit of GPIOB PIN9 + + + 8 + 1 + OTYPE8 + The output type selection bit of GPIOB PIN8 + + + 7 + 1 + OTYPE7 + The output type selection bit of GPIOB PIN7 + + + 6 + 1 + OTYPE6 + The output type selection bit of GPIOB PIN6 + + + 5 + 1 + OTYPE5 + The output type selection bit of GPIOB PIN5 + + + 4 + 1 + OTYPE4 + The output type selection bit of GPIOB PIN4 + + + 3 + 1 + OTYPE3 + The output type selection bit of GPIOB PIN3 + + + 2 + 1 + OTYPE2 + The output type selection bit of GPIOB PIN2 + + + 1 + 1 + OTYPE1 + The output type selection bit of GPIOB PIN1 + + + 0 + 1 + OTYPE0 + The output type selection bit of GPIOB PIN0 + + + + + OSPEED + OSPEED + OSPEED + 0x08 + 0x20 + read-write + 0x00000000 + + + 30 + 2 + OSPEED15 + The Speed gear selection bit of GPIOB PIN15 + + + 28 + 2 + OSPEED14 + The Speed gear selection bit of GPIOB PIN14 + + + 26 + 2 + OSPEED13 + The Speed gear selection bit of GPIOB PIN13 + + + 24 + 2 + OSPEED12 + The Speed gear selection bit of GPIOB PIN12 + + + 22 + 2 + OSPEED11 + The Speed gear selection bit of GPIOB PIN11 + + + 20 + 2 + OSPEED10 + The Speed gear selection bit of GPIOB PIN10 + + + 18 + 2 + OSPEED9 + The Speed gear selection bit of GPIOB PIN9 + + + 16 + 2 + OSPEED8 + The Speed gear selection bit of GPIOB PIN8 + + + 14 + 2 + OSPEED7 + The Speed gear selection bit of GPIOB PIN7 + + + 12 + 2 + OSPEED6 + The Speed gear selection bit of GPIOB PIN6 + + + 10 + 2 + OSPEED5 + The Speed gear selection bit of GPIOB PIN5 + + + 8 + 2 + OSPEED4 + The Speed gear selection bit of GPIOB PIN4 + + + 6 + 2 + OSPEED3 + The Speed gear selection bit of GPIOB PIN3 + + + 4 + 2 + OSPEED2 + The Speed gear selection bit of GPIOB PIN2 + + + 2 + 2 + OSPEED1 + The Speed gear selection bit of GPIOB PIN1 + + + 0 + 2 + OSPEED0 + The Speed gear selection bit of GPIOB PIN0 + + + + + PUPD + PUPD + PUPD + 0x10 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + PD15 + The drop-down enable bit of GPIOB PIN15 + + + 30 + 1 + PD14 + The drop-down enable bit of GPIOB PIN14 + + + 29 + 1 + PD13 + The drop-down enable bit of GPIOB PIN13 + + + 28 + 1 + PD12 + The drop-down enable bit of GPIOB PIN12 + + + 27 + 1 + PD11 + The drop-down enable bit of GPIOB PIN11 + + + 26 + 1 + PD10 + The drop-down enable bit of GPIOB PIN10 + + + 25 + 1 + PD9 + The drop-down enable bit of GPIOB PIN9 + + + 24 + 1 + PD8 + The drop-down enable bit of GPIOB PIN8 + + + 23 + 1 + PD7 + The drop-down enable bit of GPIOB PIN7 + + + 22 + 1 + PD6 + The drop-down enable bit of GPIOB PIN6 + + + 21 + 1 + PD5 + The drop-down enable bit of GPIOB PIN5 + + + 20 + 1 + PD4 + The drop-down enable bit of GPIOB PIN4 + + + 19 + 1 + PD3 + The drop-down enable bit of GPIOB PIN3 + + + 18 + 1 + PD2 + The drop-down enable bit of GPIOB PIN2 + + + 17 + 1 + PD1 + The drop-down enable bit of GPIOB PIN1 + + + 16 + 1 + PD0 + The drop-down enable bit of GPIOB PIN0 + + + 15 + 1 + PU15 + The pull-up enable bit of GPIOB PIN15 + + + 14 + 1 + PU14 + The pull-up enable bit of GPIOB PIN14 + + + 13 + 1 + PU13 + The pull-up enable bit of GPIOB PIN13 + + + 12 + 1 + PU12 + The pull-up enable bit of GPIOB PIN12 + + + 11 + 1 + PU11 + The pull-up enable bit of GPIOB PIN11 + + + 10 + 1 + PU10 + The pull-up enable bit of GPIOB PIN10 + + + 9 + 1 + PU9 + The pull-up enable bit of GPIOB PIN9 + + + 8 + 1 + PU8 + The pull-up enable bit of GPIOB PIN8 + + + 7 + 1 + PU7 + The pull-up enable bit of GPIOB PIN7 + + + 6 + 1 + PU6 + The pull-up enable bit of GPIOB PIN6 + + + 5 + 1 + PU5 + The pull-up enable bit of GPIOB PIN5 + + + 4 + 1 + PU4 + The pull-up enable bit of GPIOB PIN4 + + + 3 + 1 + PU3 + The pull-up enable bit of GPIOB PIN3 + + + 2 + 1 + PU2 + The pull-up enable bit of GPIOB PIN2 + + + 1 + 1 + PU1 + The pull-up enable bit of GPIOB PIN1 + + + 0 + 1 + PU0 + The pull-up enable bit of GPIOB PIN0 + + + + + IDAT + IDAT + IDAT + 0x14 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + IDAT15 + The Input data bit of GPIOB PIN15 + + + 14 + 1 + IDAT14 + The Input data bit of GPIOB PIN14 + + + 13 + 1 + IDAT13 + The Input data bit of GPIOB PIN13 + + + 12 + 1 + IDAT12 + The Input data bit of GPIOB PIN12 + + + 11 + 1 + IDAT11 + The Input data bit of GPIOB PIN11 + + + 10 + 1 + IDAT10 + The Input data bit of GPIOB PIN10 + + + 9 + 1 + IDAT9 + The Input data bit of GPIOB PIN9 + + + 8 + 1 + IDAT8 + The Input data bit of GPIOB PIN8 + + + 7 + 1 + IDAT7 + The Input data bit of GPIOB PIN7 + + + 6 + 1 + IDAT6 + The Input data bit of GPIOB PIN6 + + + 5 + 1 + IDAT5 + The Input data bit of GPIOB PIN5 + + + 4 + 1 + IDAT4 + The Input data bit of GPIOB PIN4 + + + 3 + 1 + IDAT3 + The Input data bit of GPIOB PIN3 + + + 2 + 1 + IDAT2 + The Input data bit of GPIOB PIN2 + + + 1 + 1 + IDAT1 + The Input data bit of GPIOB PIN1 + + + 0 + 1 + IDAT0 + The Input data bit of GPIOB PIN0 + + + + + ODAT + ODAT + ODAT + 0x18 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ODAT15 + The output data bit of GPIOB PIN15 + + + 14 + 1 + ODAT14 + The output data bit of GPIOB PIN14 + + + 13 + 1 + ODAT13 + The output data bit of GPIOB PIN13 + + + 12 + 1 + ODAT12 + The output data bit of GPIOB PIN12 + + + 11 + 1 + ODAT11 + The output data bit of GPIOB PIN11 + + + 10 + 1 + ODAT10 + The output data bit of GPIOB PIN10 + + + 9 + 1 + ODAT9 + The output data bit of GPIOB PIN9 + + + 8 + 1 + ODAT8 + The output data bit of GPIOB PIN8 + + + 7 + 1 + ODAT7 + The output data bit of GPIOB PIN7 + + + 6 + 1 + ODAT6 + The output data bit of GPIOB PIN6 + + + 5 + 1 + ODAT5 + The output data bit of GPIOB PIN5 + + + 4 + 1 + ODAT4 + The output data bit of GPIOB PIN4 + + + 3 + 1 + ODAT3 + The output data bit of GPIOB PIN3 + + + 2 + 1 + ODAT2 + The output data bit of GPIOB PIN2 + + + 1 + 1 + ODAT1 + The output data bit of GPIOB PIN1 + + + 0 + 1 + ODAT0 + The output data bit of GPIOB PIN0 + + + + + BSR + BSR + BSR + 0x1C + 0x20 + read-write + 0x00000000 + + + 31 + 1 + BR15 + The Clear bit of GPIOB PIN15 + + + 30 + 1 + BR14 + The Clear bit of GPIOB PIN14 + + + 29 + 1 + BR13 + The Clear bit of GPIOB PIN13 + + + 28 + 1 + BR12 + The Clear bit of GPIOB PIN12 + + + 27 + 1 + BR11 + The Clear bit of GPIOB PIN11 + + + 26 + 1 + BR10 + The Clear bit of GPIOB PIN10 + + + 25 + 1 + BR9 + The Clear bit of GPIOB PIN9 + + + 24 + 1 + BR8 + The Clear bit of GPIOB PIN8 + + + 23 + 1 + BR7 + The Clear bit of GPIOB PIN7 + + + 22 + 1 + BR6 + The Clear bit of GPIOB PIN6 + + + 21 + 1 + BR5 + The Clear bit of GPIOB PIN5 + + + 20 + 1 + BR4 + The Clear bit of GPIOB PIN4 + + + 19 + 1 + BR3 + The Clear bit of GPIOB PIN3 + + + 18 + 1 + BR2 + The Clear bit of GPIOB PIN2 + + + 17 + 1 + BR1 + The Clear bit of GPIOB PIN1 + + + 16 + 1 + BR0 + The Clear bit of GPIOB PIN0 + + + 15 + 1 + BS15 + The setting bit of GPIOB PIN15 + + + 14 + 1 + BS14 + The setting bit of GPIOB PIN14 + + + 13 + 1 + BS13 + The setting bit of GPIOB PIN13 + + + 12 + 1 + BS12 + The setting bit of GPIOB PIN12 + + + 11 + 1 + BS11 + The setting bit of GPIOB PIN11 + + + 10 + 1 + BS10 + The setting bit of GPIOB PIN10 + + + 9 + 1 + BS9 + The setting bit of GPIOB PIN9 + + + 8 + 1 + BS8 + The setting bit of GPIOB PIN8 + + + 7 + 1 + BS7 + The setting bit of GPIOB PIN7 + + + 6 + 1 + BS6 + The setting bit of GPIOB PIN6 + + + 5 + 1 + BS5 + The setting bit of GPIOB PIN5 + + + 4 + 1 + BS4 + The setting bit of GPIOB PIN4 + + + 3 + 1 + BS3 + The setting bit of GPIOB PIN3 + + + 2 + 1 + BS2 + The setting bit of GPIOB PIN2 + + + 1 + 1 + BS1 + The setting bit of GPIOB PIN1 + + + 0 + 1 + BS0 + The setting bit of GPIOB PIN0 + + + + + LCK + LCK + LCK + 0x20 + 0x20 + read-write + 0x00000000 + + + 16 + 1 + LCKK + The locking mechanism valid bit of GPIOB + + + 15 + 1 + LCK15 + The lock enable bit of GPIOB PIN15 + + + 14 + 1 + LCK14 + The lock enable bit of GPIOB PIN14 + + + 13 + 1 + LCK13 + The lock enable bit of GPIOB PIN13 + + + 12 + 1 + LCK12 + The lock enable bit of GPIOB PIN12 + + + 11 + 1 + LCK11 + The lock enable bit of GPIOB PIN11 + + + 10 + 1 + LCK10 + The lock enable bit of GPIOB PIN10 + + + 9 + 1 + LCK9 + The lock enable bit of GPIOB PIN9 + + + 8 + 1 + LCK8 + The lock enable bit of GPIOB PIN8 + + + 7 + 1 + LCK7 + The lock enable bit of GPIOB PIN7 + + + 6 + 1 + LCK6 + The lock enable bit of GPIOB PIN6 + + + 5 + 1 + LCK5 + The lock enable bit of GPIOB PIN5 + + + 4 + 1 + LCK4 + The lock enable bit of GPIOB PIN4 + + + 3 + 1 + LCK3 + The lock enable bit of GPIOB PIN3 + + + 2 + 1 + LCK2 + The lock enable bit of GPIOB PIN2 + + + 1 + 1 + LCK1 + The lock enable bit of GPIOB PIN1 + + + 0 + 1 + LCK0 + The lock enable bit of GPIOB PIN0 + + + + + AFRL + AFRL + AFRL + 0x24 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + AFR7 + GPIOB[7] multiplexed channel selection bit + + + 24 + 4 + AFR6 + GPIOB[6] multiplexed channel selection bit + + + 20 + 4 + AFR5 + GPIOB[5] multiplexed channel selection bit + + + 16 + 4 + AFR4 + GPIOB[4] multiplexed channel selection bit + + + 12 + 4 + AFR3 + GPIOB[3] multiplexed channel selection bit + + + 8 + 4 + AFR2 + GPIOB[2] multiplexed channel selection bit + + + 4 + 4 + AFR1 + GPIOB[1] multiplexed channel selection bit + + + 0 + 4 + AFR0 + GPIOB[0] multiplexed channel selection bit + + + + + AFRH + AFRH + AFRH + 0x28 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + AFR15 + GPIOB[15] multiplexed channel selection bit + + + 24 + 4 + AFR14 + GPIOB[14] multiplexed channel selection bit + + + 20 + 4 + AFR13 + GPIOB[13] multiplexed channel selection bit + + + 16 + 4 + AFR12 + GPIOB[12] multiplexed channel selection bit + + + 12 + 4 + AFR11 + GPIOB[11] multiplexed channel selection bit + + + 8 + 4 + AFR10 + GPIOB[10] multiplexed channel selection bit + + + 4 + 4 + AFR9 + GPIOB[9] multiplexed channel selection bit + + + 0 + 4 + AFR8 + GPIOB[8] multiplexed channel selection bit + + + + + TGL + TGL + TGL + 0x2C + 0x20 + read-write + 0x00000000 + + + 15 + 1 + TG15 + The flip bit of GPIOB PIN15 + + + 14 + 1 + TG14 + The flip bit of GPIOB PIN14 + + + 13 + 1 + TG13 + The flip bit of GPIOB PIN13 + + + 12 + 1 + TG12 + The flip bit of GPIOB PIN12 + + + 11 + 1 + TG11 + The flip bit of GPIOB PIN11 + + + 10 + 1 + TG10 + The flip bit of GPIOB PIN10 + + + 9 + 1 + TG9 + The flip bit of GPIOB PIN9 + + + 8 + 1 + TG8 + The flip bit of GPIOB PIN8 + + + 7 + 1 + TG7 + The flip bit of GPIOB PIN7 + + + 6 + 1 + TG6 + The flip bit of GPIOB PIN6 + + + 5 + 1 + TG5 + The flip bit of GPIOB PIN5 + + + 4 + 1 + TG4 + The flip bit of GPIOB PIN4 + + + 3 + 1 + TG3 + The flip bit of GPIOB PIN3 + + + 2 + 1 + TG2 + The flip bit of GPIOB PIN2 + + + 1 + 1 + TG1 + The flip bit of GPIOB PIN1 + + + 0 + 1 + TG0 + The flip bit of GPIOB PIN0 + + + + + IMK + IMK + IMK + 0x30 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + IMK15 + The Interrupt enable bit of GPIOB PIN15 + + + 14 + 1 + IMK14 + The Interrupt enable bit of GPIOB PIN14 + + + 13 + 1 + IMK13 + The Interrupt enable bit of GPIOB PIN13 + + + 12 + 1 + IMK12 + The Interrupt enable bit of GPIOB PIN12 + + + 11 + 1 + IMK11 + The Interrupt enable bit of GPIOB PIN11 + + + 10 + 1 + IMK10 + The Interrupt enable bit of GPIOB PIN10 + + + 9 + 1 + IMK9 + The Interrupt enable bit of GPIOB PIN9 + + + 8 + 1 + IMK8 + The Interrupt enable bit of GPIOB PIN8 + + + 7 + 1 + IMK7 + The Interrupt enable bit of GPIOB PIN7 + + + 6 + 1 + IMK6 + The Interrupt enable bit of GPIOB PIN6 + + + 5 + 1 + IMK5 + The Interrupt enable bit of GPIOB PIN5 + + + 4 + 1 + IMK4 + The Interrupt enable bit of GPIOB PIN4 + + + 3 + 1 + IMK3 + The Interrupt enable bit of GPIOB PIN3 + + + 2 + 1 + IMK2 + The Interrupt enable bit of GPIOB PIN2 + + + 1 + 1 + IMK1 + The Interrupt enable bit of GPIOB PIN1 + + + 0 + 1 + IMK0 + The Interrupt enable bit of GPIOB PIN0 + + + + + TGPEND + TGPEND + TGPEND + 0x34 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + TP15 + The input edge detection flag bit of GPIOB PIN15 + + + 14 + 1 + TP14 + The input edge detection flag bit of GPIOB PIN14 + + + 13 + 1 + TP13 + The input edge detection flag bit of GPIOB PIN13 + + + 12 + 1 + TP12 + The input edge detection flag bit of GPIOB PIN12 + + + 11 + 1 + TP11 + The input edge detection flag bit of GPIOB PIN11 + + + 10 + 1 + TP10 + The input edge detection flag bit of GPIOB PIN10 + + + 9 + 1 + TP9 + The input edge detection flag bit of GPIOB PIN9 + + + 8 + 1 + TP8 + The input edge detection flag bit of GPIOB PIN8 + + + 7 + 1 + TP7 + The input edge detection flag bit of GPIOB PIN7 + + + 6 + 1 + TP6 + The input edge detection flag bit of GPIOB PIN6 + + + 5 + 1 + TP5 + The input edge detection flag bit of GPIOB PIN5 + + + 4 + 1 + TP4 + The input edge detection flag bit of GPIOB PIN4 + + + 3 + 1 + TP3 + The input edge detection flag bit of GPIOB PIN3 + + + 2 + 1 + TP2 + The input edge detection flag bit of GPIOB PIN2 + + + 1 + 1 + TP1 + The input edge detection flag bit of GPIOB PIN1 + + + 0 + 1 + TP0 + The input edge detection flag bit of GPIOB PIN0 + + + + + IE_EN + IE_EN + IE_EN + 0x38 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + GB15IEE + The input force enable bit of GPIOB PIN15 + + + 14 + 1 + GB14IEE + The input force enable bit of GPIOB PIN14 + + + 13 + 1 + GB13IEE + The input force enable bit of GPIOB PIN13 + + + 12 + 1 + GB12IEE + The input force enable bit of GPIOB PIN12 + + + 11 + 1 + GB11IEE + The input force enable bit of GPIOB PIN11 + + + 10 + 1 + GB10IEE + The input force enable bit of GPIOB PIN10 + + + 9 + 1 + GB9IEE + The input force enable bit of GPIOB PIN9 + + + 8 + 1 + GB8IEE + The input force enable bit of GPIOB PIN8 + + + 7 + 1 + GB7IEE + The input force enable bit of GPIOB PIN7 + + + 6 + 1 + GB6IEE + The input force enable bit of GPIOB PIN6 + + + 5 + 1 + GB5IEE + The input force enable bit of GPIOB PIN5 + + + 4 + 1 + GB4IEE + The input force enable bit of GPIOB PIN4 + + + 3 + 1 + GB3IEE + The input force enable bit of GPIOB PIN3 + + + 2 + 1 + GB2IEE + The input force enable bit of GPIOB PIN2 + + + 1 + 1 + GB1IEE + The input force enable bit of GPIOB PIN1 + + + 0 + 1 + GB0IEE + The input force enable bit of GPIOB PIN0 + + + + + TG_EDGE + TG_EDGE + TG_EDGE + 0x3C + 0x20 + read-write + 0x00000000 + + + 30 + 2 + TGD15 + Detection control bit of the input edge of GPIOB PIN15 + + + 28 + 2 + TGD14 + Detection control bit of the input edge of GPIOB PIN14 + + + 26 + 2 + TGD13 + Detection control bit of the input edge of GPIOB PIN13 + + + 24 + 2 + TGD12 + Detection control bit of the input edge of GPIOB PIN12 + + + 22 + 2 + TGD11 + Detection control bit of the input edge of GPIOB PIN11 + + + 20 + 2 + TGD10 + Detection control bit of the input edge of GPIOB PIN10 + + + 18 + 2 + TGD9 + Detection control bit of the input edge of GPIOB PIN9 + + + 16 + 2 + TGD8 + Detection control bit of the input edge of GPIOB PIN8 + + + 14 + 2 + TGD7 + Detection control bit of the input edge of GPIOB PIN7 + + + 12 + 2 + TGD6 + Detection control bit of the input edge of GPIOB PIN6 + + + 10 + 2 + TGD5 + Detection control bit of the input edge of GPIOB PIN5 + + + 8 + 2 + TGD4 + Detection control bit of the input edge of GPIOB PIN4 + + + 6 + 2 + TGD3 + Detection control bit of the input edge of GPIOB PIN3 + + + 4 + 2 + TGD2 + Detection control bit of the input edge of GPIOB PIN2 + + + 2 + 2 + TGD1 + Detection control bit of the input edge of GPIOB PIN1 + + + 0 + 2 + TGD0 + Detection control bit of the input edge of GPIOB PIN0 + + + + + + + + + + GPIOC + GPIOC unit + GPIOC + 0x400201B0 + + 0x0 + 0x40 + registers + + + + MODE + MODE + MODE + 0x00 + 0x20 + read-write + 0x00000000 + + + 30 + 2 + MODER15 + The mode bit of GPIOC PIN15 + + + 28 + 2 + MODER14 + The mode bit of GPIOC PIN14 + + + 26 + 2 + MODER13 + The mode bit of GPIOC PIN13 + + + 24 + 2 + MODER12 + The mode bit of GPIOC PIN12 + + + 22 + 2 + MODER11 + The mode bit of GPIOC PIN11 + + + 20 + 2 + MODER10 + The mode bit of GPIOC PIN10 + + + 18 + 2 + MODER9 + The mode bit of GPIOC PIN9 + + + 16 + 2 + MODER8 + The mode bit of GPIOC PIN8 + + + 14 + 2 + MODER7 + The mode bit of GPIOC PIN7 + + + 12 + 2 + MODER6 + The mode bit of GPIOC PIN6 + + + 10 + 2 + MODER5 + The mode bit of GPIOC PIN5 + + + 8 + 2 + MODER4 + The mode bit of GPIOC PIN4 + + + 6 + 2 + MODER3 + The mode bit of GPIOC PIN3 + + + 4 + 2 + MODER2 + The mode bit of GPIOC PIN2 + + + 2 + 2 + MODER1 + The mode bit of GPIOC PIN1 + + + 0 + 2 + MODER0 + The mode bit of GPIOC PIN0 + + + + + OTYPE + OTYPE + OTYPE + 0x04 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OTYPE15 + The output type selection bit of GPIOC PIN15 + + + 14 + 1 + OTYPE14 + The output type selection bit of GPIOC PIN14 + + + 13 + 1 + OTYPE13 + The output type selection bit of GPIOC PIN13 + + + 12 + 1 + OTYPE12 + The output type selection bit of GPIOC PIN12 + + + 11 + 1 + OTYPE11 + The output type selection bit of GPIOC PIN11 + + + 10 + 1 + OTYPE10 + The output type selection bit of GPIOC PIN10 + + + 9 + 1 + OTYPE9 + The output type selection bit of GPIOC PIN9 + + + 8 + 1 + OTYPE8 + The output type selection bit of GPIOC PIN8 + + + 7 + 1 + OTYPE7 + The output type selection bit of GPIOC PIN7 + + + 6 + 1 + OTYPE6 + The output type selection bit of GPIOC PIN6 + + + 5 + 1 + OTYPE5 + The output type selection bit of GPIOC PIN5 + + + 4 + 1 + OTYPE4 + The output type selection bit of GPIOC PIN4 + + + 3 + 1 + OTYPE3 + The output type selection bit of GPIOC PIN3 + + + 2 + 1 + OTYPE2 + The output type selection bit of GPIOC PIN2 + + + 1 + 1 + OTYPE1 + The output type selection bit of GPIOC PIN1 + + + 0 + 1 + OTYPE0 + The output type selection bit of GPIOC PIN0 + + + + + OSPEED + OSPEED + OSPEED + 0x08 + 0x20 + read-write + 0x00000000 + + + 30 + 2 + OSPEED15 + The Speed gear selection bit of GPIOC PIN15 + + + 28 + 2 + OSPEED14 + The Speed gear selection bit of GPIOC PIN14 + + + 26 + 2 + OSPEED13 + The Speed gear selection bit of GPIOC PIN13 + + + 24 + 2 + OSPEED12 + The Speed gear selection bit of GPIOC PIN12 + + + 22 + 2 + OSPEED11 + The Speed gear selection bit of GPIOC PIN11 + + + 20 + 2 + OSPEED10 + The Speed gear selection bit of GPIOC PIN10 + + + 18 + 2 + OSPEED9 + The Speed gear selection bit of GPIOC PIN9 + + + 16 + 2 + OSPEED8 + The Speed gear selection bit of GPIOC PIN8 + + + 14 + 2 + OSPEED7 + The Speed gear selection bit of GPIOC PIN7 + + + 12 + 2 + OSPEED6 + The Speed gear selection bit of GPIOC PIN6 + + + 10 + 2 + OSPEED5 + The Speed gear selection bit of GPIOC PIN5 + + + 8 + 2 + OSPEED4 + The Speed gear selection bit of GPIOC PIN4 + + + 6 + 2 + OSPEED3 + The Speed gear selection bit of GPIOC PIN3 + + + 4 + 2 + OSPEED2 + The Speed gear selection bit of GPIOC PIN2 + + + 2 + 2 + OSPEED1 + The Speed gear selection bit of GPIOC PIN1 + + + 0 + 2 + OSPEED0 + The Speed gear selection bit of GPIOC PIN0 + + + + + PUPD + PUPD + PUPD + 0x10 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + PD15 + The drop-down enable bit of GPIOC PIN15 + + + 30 + 1 + PD14 + The drop-down enable bit of GPIOC PIN14 + + + 29 + 1 + PD13 + The drop-down enable bit of GPIOC PIN13 + + + 28 + 1 + PD12 + The drop-down enable bit of GPIOC PIN12 + + + 27 + 1 + PD11 + The drop-down enable bit of GPIOC PIN11 + + + 26 + 1 + PD10 + The drop-down enable bit of GPIOC PIN10 + + + 25 + 1 + PD9 + The drop-down enable bit of GPIOC PIN9 + + + 24 + 1 + PD8 + The drop-down enable bit of GPIOC PIN8 + + + 23 + 1 + PD7 + The drop-down enable bit of GPIOC PIN7 + + + 22 + 1 + PD6 + The drop-down enable bit of GPIOC PIN6 + + + 21 + 1 + PD5 + The drop-down enable bit of GPIOC PIN5 + + + 20 + 1 + PD4 + The drop-down enable bit of GPIOC PIN4 + + + 19 + 1 + PD3 + The drop-down enable bit of GPIOC PIN3 + + + 18 + 1 + PD2 + The drop-down enable bit of GPIOC PIN2 + + + 17 + 1 + PD1 + The drop-down enable bit of GPIOC PIN1 + + + 16 + 1 + PD0 + The drop-down enable bit of GPIOC PIN0 + + + 15 + 1 + PU15 + The pull-up enable bit of GPIOC PIN15 + + + 14 + 1 + PU14 + The pull-up enable bit of GPIOC PIN14 + + + 13 + 1 + PU13 + The pull-up enable bit of GPIOC PIN13 + + + 12 + 1 + PU12 + The pull-up enable bit of GPIOC PIN12 + + + 11 + 1 + PU11 + The pull-up enable bit of GPIOC PIN11 + + + 10 + 1 + PU10 + The pull-up enable bit of GPIOC PIN10 + + + 9 + 1 + PU9 + The pull-up enable bit of GPIOC PIN9 + + + 8 + 1 + PU8 + The pull-up enable bit of GPIOC PIN8 + + + 7 + 1 + PU7 + The pull-up enable bit of GPIOC PIN7 + + + 6 + 1 + PU6 + The pull-up enable bit of GPIOC PIN6 + + + 5 + 1 + PU5 + The pull-up enable bit of GPIOC PIN5 + + + 4 + 1 + PU4 + The pull-up enable bit of GPIOC PIN4 + + + 3 + 1 + PU3 + The pull-up enable bit of GPIOC PIN3 + + + 2 + 1 + PU2 + The pull-up enable bit of GPIOC PIN2 + + + 1 + 1 + PU1 + The pull-up enable bit of GPIOC PIN1 + + + 0 + 1 + PU0 + The pull-up enable bit of GPIOC PIN0 + + + + + IDAT + IDAT + IDAT + 0x14 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + IDAT15 + The Input data bit of GPIOC PIN15 + + + 14 + 1 + IDAT14 + The Input data bit of GPIOC PIN14 + + + 13 + 1 + IDAT13 + The Input data bit of GPIOC PIN13 + + + 12 + 1 + IDAT12 + The Input data bit of GPIOC PIN12 + + + 11 + 1 + IDAT11 + The Input data bit of GPIOC PIN11 + + + 10 + 1 + IDAT10 + The Input data bit of GPIOC PIN10 + + + 9 + 1 + IDAT9 + The Input data bit of GPIOC PIN9 + + + 8 + 1 + IDAT8 + The Input data bit of GPIOC PIN8 + + + 7 + 1 + IDAT7 + The Input data bit of GPIOC PIN7 + + + 6 + 1 + IDAT6 + The Input data bit of GPIOC PIN6 + + + 5 + 1 + IDAT5 + The Input data bit of GPIOC PIN5 + + + 4 + 1 + IDAT4 + The Input data bit of GPIOC PIN4 + + + 3 + 1 + IDAT3 + The Input data bit of GPIOC PIN3 + + + 2 + 1 + IDAT2 + The Input data bit of GPIOC PIN2 + + + 1 + 1 + IDAT1 + The Input data bit of GPIOC PIN1 + + + 0 + 1 + IDAT0 + The Input data bit of GPIOC PIN0 + + + + + ODAT + ODAT + ODAT + 0x18 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ODAT15 + The output data bit of GPIOC PIN15 + + + 14 + 1 + ODAT14 + The output data bit of GPIOC PIN14 + + + 13 + 1 + ODAT13 + The output data bit of GPIOC PIN13 + + + 12 + 1 + ODAT12 + The output data bit of GPIOC PIN12 + + + 11 + 1 + ODAT11 + The output data bit of GPIOC PIN11 + + + 10 + 1 + ODAT10 + The output data bit of GPIOC PIN10 + + + 9 + 1 + ODAT9 + The output data bit of GPIOC PIN9 + + + 8 + 1 + ODAT8 + The output data bit of GPIOC PIN8 + + + 7 + 1 + ODAT7 + The output data bit of GPIOC PIN7 + + + 6 + 1 + ODAT6 + The output data bit of GPIOC PIN6 + + + 5 + 1 + ODAT5 + The output data bit of GPIOC PIN5 + + + 4 + 1 + ODAT4 + The output data bit of GPIOC PIN4 + + + 3 + 1 + ODAT3 + The output data bit of GPIOC PIN3 + + + 2 + 1 + ODAT2 + The output data bit of GPIOC PIN2 + + + 1 + 1 + ODAT1 + The output data bit of GPIOC PIN1 + + + 0 + 1 + ODAT0 + The output data bit of GPIOC PIN0 + + + + + BSR + BSR + BSR + 0x1C + 0x20 + read-write + 0x00000000 + + + 31 + 1 + BR15 + The Clear bit of GPIOC PIN15 + + + 30 + 1 + BR14 + The Clear bit of GPIOC PIN14 + + + 29 + 1 + BR13 + The Clear bit of GPIOC PIN13 + + + 28 + 1 + BR12 + The Clear bit of GPIOC PIN12 + + + 27 + 1 + BR11 + The Clear bit of GPIOC PIN11 + + + 26 + 1 + BR10 + The Clear bit of GPIOC PIN10 + + + 25 + 1 + BR9 + The Clear bit of GPIOC PIN9 + + + 24 + 1 + BR8 + The Clear bit of GPIOC PIN8 + + + 23 + 1 + BR7 + The Clear bit of GPIOC PIN7 + + + 22 + 1 + BR6 + The Clear bit of GPIOC PIN6 + + + 21 + 1 + BR5 + The Clear bit of GPIOC PIN5 + + + 20 + 1 + BR4 + The Clear bit of GPIOC PIN4 + + + 19 + 1 + BR3 + The Clear bit of GPIOC PIN3 + + + 18 + 1 + BR2 + The Clear bit of GPIOC PIN2 + + + 17 + 1 + BR1 + The Clear bit of GPIOC PIN1 + + + 16 + 1 + BR0 + The Clear bit of GPIOC PIN0 + + + 15 + 1 + BS15 + The setting bit of GPIOC PIN15 + + + 14 + 1 + BS14 + The setting bit of GPIOC PIN14 + + + 13 + 1 + BS13 + The setting bit of GPIOC PIN13 + + + 12 + 1 + BS12 + The setting bit of GPIOC PIN12 + + + 11 + 1 + BS11 + The setting bit of GPIOC PIN11 + + + 10 + 1 + BS10 + The setting bit of GPIOC PIN10 + + + 9 + 1 + BS9 + The setting bit of GPIOC PIN9 + + + 8 + 1 + BS8 + The setting bit of GPIOC PIN8 + + + 7 + 1 + BS7 + The setting bit of GPIOC PIN7 + + + 6 + 1 + BS6 + The setting bit of GPIOC PIN6 + + + 5 + 1 + BS5 + The setting bit of GPIOC PIN5 + + + 4 + 1 + BS4 + The setting bit of GPIOC PIN4 + + + 3 + 1 + BS3 + The setting bit of GPIOC PIN3 + + + 2 + 1 + BS2 + The setting bit of GPIOC PIN2 + + + 1 + 1 + BS1 + The setting bit of GPIOC PIN1 + + + 0 + 1 + BS0 + The setting bit of GPIOC PIN0 + + + + + LCK + LCK + LCK + 0x20 + 0x20 + read-write + 0x00000000 + + + 16 + 1 + LCKK + The locking mechanism valid bit of GPIOC + + + 15 + 1 + LCK15 + The lock enable bit of GPIOC PIN15 + + + 14 + 1 + LCK14 + The lock enable bit of GPIOC PIN14 + + + 13 + 1 + LCK13 + The lock enable bit of GPIOC PIN13 + + + 12 + 1 + LCK12 + The lock enable bit of GPIOC PIN12 + + + 11 + 1 + LCK11 + The lock enable bit of GPIOC PIN11 + + + 10 + 1 + LCK10 + The lock enable bit of GPIOC PIN10 + + + 9 + 1 + LCK9 + The lock enable bit of GPIOC PIN9 + + + 8 + 1 + LCK8 + The lock enable bit of GPIOC PIN8 + + + 7 + 1 + LCK7 + The lock enable bit of GPIOC PIN7 + + + 6 + 1 + LCK6 + The lock enable bit of GPIOC PIN6 + + + 5 + 1 + LCK5 + The lock enable bit of GPIOC PIN5 + + + 4 + 1 + LCK4 + The lock enable bit of GPIOC PIN4 + + + 3 + 1 + LCK3 + The lock enable bit of GPIOC PIN3 + + + 2 + 1 + LCK2 + The lock enable bit of GPIOC PIN2 + + + 1 + 1 + LCK1 + The lock enable bit of GPIOC PIN1 + + + 0 + 1 + LCK0 + The lock enable bit of GPIOC PIN0 + + + + + AFRL + AFRL + AFRL + 0x24 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + AFR7 + GPIOC[7] multiplexed channel selection bit + + + 24 + 4 + AFR6 + GPIOC[6] multiplexed channel selection bit + + + 20 + 4 + AFR5 + GPIOC[5] multiplexed channel selection bit + + + 16 + 4 + AFR4 + GPIOC[4] multiplexed channel selection bit + + + 12 + 4 + AFR3 + GPIOC[3] multiplexed channel selection bit + + + 8 + 4 + AFR2 + GPIOC[2] multiplexed channel selection bit + + + 4 + 4 + AFR1 + GPIOC[1] multiplexed channel selection bit + + + 0 + 4 + AFR0 + GPIOC[0] multiplexed channel selection bit + + + + + AFRH + AFRH + AFRH + 0x28 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + AFR15 + GPIOC[15] multiplexed channel selection bit + + + 24 + 4 + AFR14 + GPIOC[14] multiplexed channel selection bit + + + 20 + 4 + AFR13 + GPIOC[13] multiplexed channel selection bit + + + 16 + 4 + AFR12 + GPIOC[12] multiplexed channel selection bit + + + 12 + 4 + AFR11 + GPIOC[11] multiplexed channel selection bit + + + 8 + 4 + AFR10 + GPIOC[10] multiplexed channel selection bit + + + 4 + 4 + AFR9 + GPIOC[9] multiplexed channel selection bit + + + 0 + 4 + AFR8 + GPIOC[8] multiplexed channel selection bit + + + + + TGL + TGL + TGL + 0x2C + 0x20 + read-write + 0x00000000 + + + 15 + 1 + TG15 + The flip bit of GPIOC PIN15 + + + 14 + 1 + TG14 + The flip bit of GPIOC PIN14 + + + 13 + 1 + TG13 + The flip bit of GPIOC PIN13 + + + 12 + 1 + TG12 + The flip bit of GPIOC PIN12 + + + 11 + 1 + TG11 + The flip bit of GPIOC PIN11 + + + 10 + 1 + TG10 + The flip bit of GPIOC PIN10 + + + 9 + 1 + TG9 + The flip bit of GPIOC PIN9 + + + 8 + 1 + TG8 + The flip bit of GPIOC PIN8 + + + 7 + 1 + TG7 + The flip bit of GPIOC PIN7 + + + 6 + 1 + TG6 + The flip bit of GPIOC PIN6 + + + 5 + 1 + TG5 + The flip bit of GPIOC PIN5 + + + 4 + 1 + TG4 + The flip bit of GPIOC PIN4 + + + 3 + 1 + TG3 + The flip bit of GPIOC PIN3 + + + 2 + 1 + TG2 + The flip bit of GPIOC PIN2 + + + 1 + 1 + TG1 + The flip bit of GPIOC PIN1 + + + 0 + 1 + TG0 + The flip bit of GPIOC PIN0 + + + + + IMK + IMK + IMK + 0x30 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + IMK15 + The Interrupt enable bit of GPIOC PIN15 + + + 14 + 1 + IMK14 + The Interrupt enable bit of GPIOC PIN14 + + + 13 + 1 + IMK13 + The Interrupt enable bit of GPIOC PIN13 + + + 12 + 1 + IMK12 + The Interrupt enable bit of GPIOC PIN12 + + + 11 + 1 + IMK11 + The Interrupt enable bit of GPIOC PIN11 + + + 10 + 1 + IMK10 + The Interrupt enable bit of GPIOC PIN10 + + + 9 + 1 + IMK9 + The Interrupt enable bit of GPIOC PIN9 + + + 8 + 1 + IMK8 + The Interrupt enable bit of GPIOC PIN8 + + + 7 + 1 + IMK7 + The Interrupt enable bit of GPIOC PIN7 + + + 6 + 1 + IMK6 + The Interrupt enable bit of GPIOC PIN6 + + + 5 + 1 + IMK5 + The Interrupt enable bit of GPIOC PIN5 + + + 4 + 1 + IMK4 + The Interrupt enable bit of GPIOC PIN4 + + + 3 + 1 + IMK3 + The Interrupt enable bit of GPIOC PIN3 + + + 2 + 1 + IMK2 + The Interrupt enable bit of GPIOC PIN2 + + + 1 + 1 + IMK1 + The Interrupt enable bit of GPIOC PIN1 + + + 0 + 1 + IMK0 + The Interrupt enable bit of GPIOC PIN0 + + + + + TGPEND + TGPEND + TGPEND + 0x34 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + TP15 + The input edge detection flag bit of GPIOC PIN15 + + + 14 + 1 + TP14 + The input edge detection flag bit of GPIOC PIN14 + + + 13 + 1 + TP13 + The input edge detection flag bit of GPIOC PIN13 + + + 12 + 1 + TP12 + The input edge detection flag bit of GPIOC PIN12 + + + 11 + 1 + TP11 + The input edge detection flag bit of GPIOC PIN11 + + + 10 + 1 + TP10 + The input edge detection flag bit of GPIOC PIN10 + + + 9 + 1 + TP9 + The input edge detection flag bit of GPIOC PIN9 + + + 8 + 1 + TP8 + The input edge detection flag bit of GPIOC PIN8 + + + 7 + 1 + TP7 + The input edge detection flag bit of GPIOC PIN7 + + + 6 + 1 + TP6 + The input edge detection flag bit of GPIOC PIN6 + + + 5 + 1 + TP5 + The input edge detection flag bit of GPIOC PIN5 + + + 4 + 1 + TP4 + The input edge detection flag bit of GPIOC PIN4 + + + 3 + 1 + TP3 + The input edge detection flag bit of GPIOC PIN3 + + + 2 + 1 + TP2 + The input edge detection flag bit of GPIOC PIN2 + + + 1 + 1 + TP1 + The input edge detection flag bit of GPIOC PIN1 + + + 0 + 1 + TP0 + The input edge detection flag bit of GPIOC PIN0 + + + + + IE_EN + IE_EN + IE_EN + 0x38 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + GC15IEE + The input force enable bit of GPIOC PIN15 + + + 14 + 1 + GC14IEE + The input force enable bit of GPIOC PIN14 + + + 13 + 1 + GC13IEE + The input force enable bit of GPIOC PIN13 + + + 12 + 1 + GC12IEE + The input force enable bit of GPIOC PIN12 + + + 11 + 1 + GC11IEE + The input force enable bit of GPIOC PIN11 + + + 10 + 1 + GC10IEE + The input force enable bit of GPIOC PIN10 + + + 9 + 1 + GC9IEE + The input force enable bit of GPIOC PIN9 + + + 8 + 1 + GC8IEE + The input force enable bit of GPIOC PIN8 + + + 7 + 1 + GC7IEE + The input force enable bit of GPIOC PIN7 + + + 6 + 1 + GC6IEE + The input force enable bit of GPIOC PIN6 + + + 5 + 1 + GC5IEE + The input force enable bit of GPIOC PIN5 + + + 4 + 1 + GC4IEE + The input force enable bit of GPIOC PIN4 + + + 3 + 1 + GC3IEE + The input force enable bit of GPIOC PIN3 + + + 2 + 1 + GC2IEE + The input force enable bit of GPIOC PIN2 + + + 1 + 1 + GC1IEE + The input force enable bit of GPIOC PIN1 + + + 0 + 1 + GC0IEE + The input force enable bit of GPIOC PIN0 + + + + + TG_EDGE + TG_EDGE + TG_EDGE + 0x3C + 0x20 + read-write + 0x00000000 + + + 30 + 2 + TGD15 + Detection control bit of the input edge of GPIOC PIN15 + + + 28 + 2 + TGD14 + Detection control bit of the input edge of GPIOC PIN14 + + + 26 + 2 + TGD13 + Detection control bit of the input edge of GPIOC PIN13 + + + 24 + 2 + TGD12 + Detection control bit of the input edge of GPIOC PIN12 + + + 22 + 2 + TGD11 + Detection control bit of the input edge of GPIOC PIN11 + + + 20 + 2 + TGD10 + Detection control bit of the input edge of GPIOC PIN10 + + + 18 + 2 + TGD9 + Detection control bit of the input edge of GPIOC PIN9 + + + 16 + 2 + TGD8 + Detection control bit of the input edge of GPIOC PIN8 + + + 14 + 2 + TGD7 + Detection control bit of the input edge of GPIOC PIN7 + + + 12 + 2 + TGD6 + Detection control bit of the input edge of GPIOC PIN6 + + + 10 + 2 + TGD5 + Detection control bit of the input edge of GPIOC PIN5 + + + 8 + 2 + TGD4 + Detection control bit of the input edge of GPIOC PIN4 + + + 6 + 2 + TGD3 + Detection control bit of the input edge of GPIOC PIN3 + + + 4 + 2 + TGD2 + Detection control bit of the input edge of GPIOC PIN2 + + + 2 + 2 + TGD1 + Detection control bit of the input edge of GPIOC PIN1 + + + 0 + 2 + TGD0 + Detection control bit of the input edge of GPIOC PIN0 + + + + + + + + + + SPI + SPI unit + SPI + 0x400202C0 + + 0x0 + 0x20 + registers + + + + CON0 + CON0 + CON0 + 0x00 + 0x20 + read-write + 0x00000000 + + + 14 + 2 + FS + SPI data frame length + + + 13 + 1 + CPIE + Enable SPI rising edge interrupt from machine mode CS + + + 12 + 1 + SCE + SPI_CS pin enabled + + + 11 + 1 + SC + SPI CS pins control the output + + + 8 + 3 + MCD + SPI host mode delay sampling data + + + 7 + 1 + SSE + Enable SPI to synchronize input data in slave mode + + + 6 + 1 + MSE + Enable SPI to synchronize input data in master mode + + + 4 + 1 + LSBDE + The SPI transmits the lower-level function first + + + 2 + 1 + WM + SPI communication mode + + + 0 + 2 + SM + SPI interface clock polarity and sampling phase + + + + + CON1 + CON1 + CON1 + 0x04 + 0x20 + read-write + 0x00000000 + + + 12 + 1 + RE + Receive DMA enablement control + + + 11 + 1 + TE + Send DMA enable control + + + 8 + 1 + BOIE + Enable receive buffer overflow interrupt + + + 7 + 1 + RNIE + The receive buffer is not broken in the air + + + 6 + 1 + TNIE + The send buffer unsatisfactory interrupt function was enabled + + + 5 + 1 + DIE + Enable data interruption after sending/receiving a frame + + + 4 + 1 + SFD + Select the full duplex mode + + + 3 + 1 + TR + Interface send/receive enable + + + 2 + 1 + MSS + The interface master/slave mode is set + + + 1 + 1 + SIS + SPI/IIC mode selection + + + 0 + 1 + SE + The SPI and IIC modules were enabled + + + + + CMD_DATA + CMD_DATA + CMD_DATA + 0x08 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + CD + Read and write data registers + + + + + BAUD + BAUD + BAUD + 0x0C + 0x20 + read-write + 0x00000000 + + + 0 + 16 + BAUD + SSP baud rate + + + + + STA + STA + STA + 0x10 + 0x20 + read-write + 0x00000804 + + + 28 + 3 + STATE + IIC states + + + 27 + 1 + SA + IIC slave mode is addressed flag + + + 23 + 1 + CBC + The software writes 1 to the bit to clear TBUF_CNT and RBUF_CNT to zero + + + 22 + 1 + RO + Receive buffer overflow + + + 19 + 3 + TC + Indicates how many bytes of valid data are in the send buffer + + + 16 + 3 + RC + Indicates how many bytes of valid data are in the receive buffer + + + 15 + 1 + MRB + Indicates whether to read what needs to be read data length + + + 14 + 1 + IRN + The reply signal received at 9bit + + + 13 + 1 + ISR + The read and write flag received + + + 12 + 1 + IBB + The IIC detects that the line is busy + + + 11 + 1 + SSC + CS level state received by SPI from machine mode + + + 10 + 1 + SB + The status of the SPI/IIC when it is in host or slave mode + + + 9 + 1 + AP + Quorum loss is detected in the IIC host mode + + + 8 + 1 + SP + The IIC detects that the STOP bit is generated on the line + + + 7 + 1 + AMP + Received the correct slave address from the host + + + 6 + 1 + IBP + Broadcast address flag bit detected + + + 5 + 1 + SCPP + SPI detects CS pin rising edge from machine mode + + + 4 + 1 + TE + Send buffer empty flag + + + 3 + 1 + TF + Send buffer full flag + + + 2 + 1 + RE + Receive buffer empty flag + + + 1 + 1 + RF + Receive buffer full flag + + + 0 + 1 + SD + Data transmission completion mark + + + + + RONLY_CNT + RONLY_CNT + RONLY_CNT + 0x14 + 0x20 + read-write + 0x00000000 + + + 0 + 12 + RC + Length of data received by the SPI in half-duplex read-only mode + + + + + + + + + + IIC + IIC unit + IIC + 0x400202E0 + + 0x0 + 0x20 + registers + + + + CON0 + CON0 + CON0 + 0x00 + 0x20 + read-write + 0x00000000 + + + 22 + 1 + RNIE + The NACK interrupt was received + + + 21 + 1 + AIE + The host quorum loss interrupt function was enabled + + + 20 + 1 + SIE + The STOP signal was detected online. The STOP signal was enabled + + + 19 + 1 + AMIE + The slave address matching interrupt was enabled + + + 14 + 5 + FM + IIC Each IIC_FILTER_CNT Indicates the clock of an IIC module + + + 13 + 1 + BIE + The IIC is disabled from receiving a broadcast address + + + 12 + 1 + BE + Enable the IIC to receive the broadcast address from the host + + + 2 + 10 + SA + IIC slave address + + + 1 + 1 + TN + Whether the IIC responds to the NACK when receiving data or the ACK select bit + + + 0 + 1 + AW + IIC slave IP address width + + + + + CON1 + CON1 + CON1 + 0x04 + 0x20 + read-write + 0x00000000 + + + 12 + 1 + RE + Receive DMA enablement control + + + 11 + 1 + TE + Send DMA enable control + + + 8 + 1 + BOIE + Enable receive buffer overflow interrupt + + + 7 + 1 + RNIE + The receive buffer is not broken in the air + + + 6 + 1 + TNIE + The send buffer unsatisfactory interrupt function was enabled + + + 5 + 1 + DIE + Enable data interruption after sending/receiving a frame + + + 4 + 1 + SFD + Select the full duplex mode + + + 3 + 1 + TR + Interface send/receive enable + + + 2 + 1 + MSS + The interface master/slave mode is set + + + 1 + 1 + SIS + SPI/IIC mode selection + + + 0 + 1 + SE + The SPI and IIC modules were enabled + + + + + CMD_DATA + CMD_DATA + CMD_DATA + 0x08 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + CD + Read and write data registers + + + + + BAUD + BAUD + BAUD + 0x0C + 0x20 + read-write + 0x00000000 + + + 0 + 16 + BAUD + SSP baud rate + + + + + STA + STA + STA + 0x10 + 0x20 + read-write + 0x00000804 + + + 28 + 3 + STATE + IIC states + + + 27 + 1 + SA + IIC slave mode is addressed flag + + + 23 + 1 + CBC + The software writes 1 to the bit to clear TBUF_CNT and RBUF_CNT to zero + + + 22 + 1 + RO + Receive buffer overflow + + + 19 + 3 + TC + Indicates how many bytes of valid data are in the send buffer + + + 16 + 3 + RC + Indicates how many bytes of valid data are in the receive buffer + + + 15 + 1 + MRB + Indicates whether to read what needs to be read data length + + + 14 + 1 + IRN + The reply signal received at 9bit + + + 13 + 1 + ISR + The read and write flag received + + + 12 + 1 + IBB + The IIC detects that the line is busy + + + 11 + 1 + SSC + CS level state received by SPI from machine mode + + + 10 + 1 + SB + The status of the SPI/IIC when it is in host or slave mode + + + 9 + 1 + AP + Quorum loss is detected in the IIC host mode + + + 8 + 1 + SP + The IIC detects that the STOP bit is generated on the line + + + 7 + 1 + AMP + Received the correct slave address from the host + + + 6 + 1 + IBP + Broadcast address flag bit detected + + + 5 + 1 + SCPP + SPI detects CS pin rising edge from machine mode + + + 4 + 1 + TE + Send buffer empty flag + + + 3 + 1 + TF + Send buffer full flag + + + 2 + 1 + RE + Receive buffer empty flag + + + 1 + 1 + RF + Receive buffer full flag + + + 0 + 1 + SD + Data transmission completion mark + + + + + RONLY_CNT + RONLY_CNT + RONLY_CNT + 0x14 + 0x20 + read-write + 0x00000000 + + + 0 + 12 + RC + Length of data received by the SPI in half-duplex read-only mode + + + + + + + + + + UART0 + UART0 unit + UART0 + 0x40020290 + + 0x0 + 0x10 + registers + + + + CON + CON + CON + 0x00 + 0x20 + read-write + 0x00360000 + + + 31 + 1 + RE + DMA receive request enable configuration + + + 30 + 1 + TDE + DMA send request enable configuration + + + 16 + 14 + TBL + Timeout configuration + + + 15 + 1 + TCIE + The UART send completion interrupt was enabled + + + 14 + 1 + TPE + The TX of UART has TMR PWM carrier + + + 13 + 1 + TOIE + TIME OUT Indicates the interrupt enable bit + + + 12 + 1 + TOE + TIME OUT detects the enable bit + + + 11 + 1 + FIE + Frame error interrupt enable bit + + + 10 + 1 + TBEIE + Send buffer air break enable bit + + + 9 + 1 + RBNIE + Receive buffer non - air break enable bit + + + 8 + 1 + TI + Send the output signal to take the inverse selection bit + + + 7 + 1 + RI + Receive the input signal to take the inverse selection bit + + + 6 + 1 + OE + Parity check selection + + + 5 + 1 + PE + Parity check is enabled + + + 4 + 1 + BE + UART transmits 9bit data mode selection bits + + + 3 + 1 + SB + UART stop bit selection + + + 2 + 1 + RCE + Disable the UART receiving function + + + 1 + 1 + WM + UART working mode selection + + + 0 + 1 + UE + The UART module enabled bit + + + + + BAUD + BAUD + BAUD + 0x04 + 0x20 + read-write + 0x000009c3 + + + 0 + 18 + BAUD + UART Baud rate control register + + + + + DATA + DATA + DATA + 0x08 + 0x20 + read-write + 0x00000000 + + + 0 + 9 + DATA + UART data register + + + + + STA + STA + STA + 0x0C + 0x20 + read-write + 0x00000001 + + + 15 + 1 + TCP + UART Send completion flag + + + 11 + 1 + TOP + TIME OUT flag bit + + + 7 + 4 + PERR + UART Parity check flag bit + + + 4 + 3 + RC + The number of cached data received by UART + + + 3 + 1 + FERR + Frame error + + + 2 + 1 + RBO + UART receive cache full flag + + + 1 + 1 + RBNE + Receive buffer non-empty flag + + + 0 + 1 + TBE + UART sends cache empty flag + + + + + + + + + + UART1 + UART1 unit + UART1 + 0x400202A0 + + 0x0 + 0x10 + registers + + + + CON + CON + CON + 0x00 + 0x20 + read-write + 0x00360000 + + + 31 + 1 + RE + DMA receive request enable configuration + + + 30 + 1 + TDE + DMA send request enable configuration + + + 16 + 14 + TBL + Timeout configuration + + + 15 + 1 + TCIE + The UART send completion interrupt was enabled + + + 14 + 1 + TPE + The TX of UART has TMR PWM carrier + + + 13 + 1 + TOIE + TIME OUT Indicates the interrupt enable bit + + + 12 + 1 + TOE + TIME OUT detects the enable bit + + + 11 + 1 + FIE + Frame error interrupt enable bit + + + 10 + 1 + TBEIE + Send buffer air break enable bit + + + 9 + 1 + RBNIE + Receive buffer non - air break enable bit + + + 8 + 1 + TI + Send the output signal to take the inverse selection bit + + + 7 + 1 + RI + Receive the input signal to take the inverse selection bit + + + 6 + 1 + OE + Parity check selection + + + 5 + 1 + PE + Parity check is enabled + + + 4 + 1 + BE + UART transmits 9bit data mode selection bits + + + 3 + 1 + SB + UART stop bit selection + + + 2 + 1 + RCE + Disable the UART receiving function + + + 1 + 1 + WM + UART working mode selection + + + 0 + 1 + UE + The UART module enabled bit + + + + + BAUD + BAUD + BAUD + 0x04 + 0x20 + read-write + 0x000009c3 + + + 0 + 18 + BAUD + UART Baud rate control register + + + + + DATA + DATA + DATA + 0x08 + 0x20 + read-write + 0x00000000 + + + 0 + 9 + DATA + UART data register + + + + + STA + STA + STA + 0x0C + 0x20 + read-write + 0x00000001 + + + 15 + 1 + TCP + UART Send completion flag + + + 11 + 1 + TOP + TIME OUT flag bit + + + 7 + 4 + PERR + UART Parity check flag bit + + + 4 + 3 + RC + The number of cached data received by UART + + + 3 + 1 + FERR + Frame error + + + 2 + 1 + RBO + UART receive cache full flag + + + 1 + 1 + RBNE + Receive buffer non-empty flag + + + 0 + 1 + TBE + UART sends cache empty flag + + + + + + + + + + TIMER1 + TIMER1 unit + TIMER1 + 0x40020400 + + 0x0 + 0x60 + registers + + + + CR1 + CR1 + CR1 + 0x00 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + EKE + External IO brake input switch + + + 14 + 1 + SYSE + System error brake switch + + + 13 + 1 + C1BP + Comparator 1 brake polarity + + + 12 + 1 + C1BE + Comparator 1 brake switch + + + 11 + 1 + C0BP + Comparator 0 brake polarity + + + 10 + 1 + C0BE + Comparator 0 brake switch + + + 8 + 2 + CKD + Clock frequency division factor + + + 7 + 1 + ARPE + Automatic reloading preloading allows bits + + + 5 + 2 + CMS + Select the center alignment mode + + + 4 + 1 + DIR + Counting direction + + + 3 + 1 + OPM + Single pulse mode + + + 2 + 1 + URS + Update request source + + + 1 + 1 + UDIS + Forbid updating + + + 0 + 1 + CEN + Enable counter + + + + + CR2 + CR2 + CR2 + 0x04 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ADCBKEN + ADC brake switch + + + 14 + 1 + OIS4 + Output idle status 4 + + + 13 + 1 + OIS3N + Output idle status 3 + + + 12 + 1 + OIS3 + Output idle status 3 + + + 11 + 1 + OIS2N + Output idle status 2 + + + 10 + 1 + OIS2 + Output idle status 2 + + + 9 + 1 + OIS1N + Output idle status 1 + + + 8 + 1 + OIS1 + Output idle status 1 + + + 7 + 1 + TI1S + TI1 selection + + + 4 + 3 + MMS + Master mode selection + + + 3 + 1 + CCDS + DMA selection for capture/comparison + + + 2 + 1 + CCUS + Capture/compare control update selection + + + 0 + 1 + CCPC + Capture/compare preloaded control bits + + + + + SMCR + SMCR + SMCR + 0x08 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ETP + External trigger polarity + + + 14 + 1 + ECE + External clock enable bit + + + 12 + 2 + ETPS + External trigger predivision + + + 8 + 4 + ETF + External trigger filtering + + + 7 + 1 + MSM + Master/slave mode + + + 4 + 3 + TS + Trigger selection + + + 0 + 3 + SMS + Mode selection + + + + + DIER + DIER + DIER + 0x0C + 0x20 + read-write + 0x00000000 + + + 14 + 1 + TDE + Allows DMA requests to be triggered + + + 13 + 1 + COMDE + DMA requests for COM are allowed + + + 12 + 1 + CC4DE + DMA requests for capture/compare 4 are allowed + + + 11 + 1 + CC3DE + DMA requests for capture/compare 3 are allowed + + + 10 + 1 + CC2DE + DMA requests for capture/compare 2 are allowed + + + 9 + 1 + CC1DE + DMA requests for capture/compare 1 are allowed + + + 8 + 1 + UDE + DMA requests that allow updates + + + 7 + 1 + BIE + Allow brake break + + + 6 + 1 + TIE + The interrupt function was triggered + + + 5 + 1 + COMIE + Allow COM interrupt + + + 4 + 1 + CC4IE + Allows capture/compare 4 interrupts + + + 3 + 1 + CC3IE + Allows capture/compare 3 interrupts + + + 2 + 1 + CC2IE + Allows capture/compare 2 interrupts + + + 1 + 1 + CC1IE + Allows capture/compare 1 interrupts + + + 0 + 1 + UIE + Allow update interrupt + + + + + SR + SR + SR + 0x10 + 0x20 + read-write + 0x00000000 + + + 12 + 1 + CC4OF + Capture 4 Repeat the capture tag + + + 11 + 1 + CC3OF + Capture 3 Repeat the capture tag + + + 10 + 1 + CC2OF + Capture 2 Repeat the capture tag + + + 9 + 1 + CC1OF + Capture 1 Repeat the capture tag + + + 7 + 1 + BIF + Brake interrupt flag + + + 6 + 1 + TIF + Trigger interrupt flag + + + 5 + 1 + COMIF + COM interrupt flag + + + 4 + 1 + CC4IF + Capture/compare 4 interrupt flags + + + 3 + 1 + CC3IF + Capture/compare 3 interrupt flags + + + 2 + 1 + CC2IF + Capture/compare 2 interrupt flags + + + 1 + 1 + CC1IF + Capture/compare 1 interrupt flags + + + 0 + 1 + UIF + Update interrupt flag + + + + + EGR + EGR + EGR + 0x14 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + BG + Generating brake event + + + 6 + 1 + TG + Generate trigger event + + + 5 + 1 + COMG + Capture/compare event generation control updates + + + 4 + 1 + CC4G + Generate the capture/Compare 4 event + + + 3 + 1 + CC3G + Generate the capture/Compare 3 event + + + 2 + 1 + CC2G + Generate the capture/Compare 2 event + + + 1 + 1 + CC1G + Generate the capture/Compare 1 event + + + 0 + 1 + UG + Generate update event + + + + + CCMR1 + CCMR1 + CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OC2CE + Output comparison 2 Clear 0 enable + + + 12 + 3 + OC2M + Output comparison 2 mode + + + 11 + 1 + OC2PE + Output comparison 2 Preload enable + + + 10 + 1 + OC2FE + Output comparison 2 Fast enable + + + 8 + 2 + CC2S + Capture/Compare 2 Select + + + 7 + 1 + OC1CE + Output comparison 1 Clear 0 enable + + + 4 + 3 + OC1M + Output comparison 1 mode + + + 3 + 1 + OC1PE + Output comparison 1 Preload enable + + + 2 + 1 + OC1FE + Output comparison 1 Fast enable + + + 0 + 2 + CC1S + Capture/Compare 1 Select + + + + + CCMR2 + CCMR2 + CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OC4CE + Output comparison 4 clear 0 enabled + + + 12 + 3 + OC4M + Output comparison 4 mode + + + 11 + 1 + OC4PE + Output comparison 4 Preload enable + + + 10 + 1 + OC4FE + Compare the output 4 Fast enable + + + 8 + 2 + CC4S + Capture/Compare 4 Select + + + 7 + 1 + OC3CE + Output comparison 3 clear 0 enabled + + + 4 + 3 + OC3M + Output comparison 3 mode + + + 3 + 1 + OC3PE + Output comparison 3 Preload enable + + + 2 + 1 + OC3FE + Compare the output 3 Fast enable + + + 0 + 2 + CC3S + Capture/Compare 3 Select + + + + + CCER + CCER + CCER + 0x20 + 0x20 + read-write + 0x00000000 + + + 13 + 1 + CC4P + Input/Capture 4 Output polarity + + + 12 + 1 + CC4E + Input/Capture 4 Enable the output + + + 11 + 1 + CC3NP + Input/Capture 3 Complementary output polarity + + + 10 + 1 + CC3NE + Input/Capture 3 Enable complementary output + + + 9 + 1 + CC3P + Input/Capture 3 Output polarity + + + 8 + 1 + CC3E + Input/Capture 3 Output Enable + + + 7 + 1 + CC2NP + Input/Capture 2 Complementary output polarity + + + 6 + 1 + CC2NE + Input/Capture 2 Enable complementary output + + + 5 + 1 + CC2P + Input/Capture 2 Output polarity + + + 4 + 1 + CC2E + Input/Capture 2 Output Enable + + + 3 + 1 + CC1NP + Input/Capture 1 Complementary output polarity + + + 2 + 1 + CC1NE + Input/Capture 1 Enable complementary output + + + 1 + 1 + CC1P + Input/Capture 1 Output polarity + + + 0 + 1 + CC1E + Input/Capture 1 Output Enable + + + + + CNT + CNT + CNT + 0x24 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + CNT + Counter value + + + + + PSC + PSC + PSC + 0x28 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + PSC + The value of the pre-divider + + + + + ARR + ARR + ARR + 0x2C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + ARR + The value of automatic reloading + + + + + RCR + RCR + RCR + 0x30 + 0x20 + read-write + 0x00000000 + + + 0 + 8 + REP + Repeat the value of the counter + + + + + CCR1 + CCR1 + CCR1 + 0x34 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR1 + Capture/compare values for channel 1 + + + + + CCR2 + CCR2 + CCR2 + 0x38 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR2 + Capture/compare values for channel 2 + + + + + CCR3 + CCR3 + CCR3 + 0x3C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR3 + Capture/compare values for channel 3 + + + + + CCR4 + CCR4 + CCR4 + 0x40 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR4 + Capture/compare values for channel 4 + + + + + BDTR + BDTR + BDTR + 0x44 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + MOE + Master output is enabled + + + 14 + 1 + AOE + Automatic output is enabled + + + 13 + 1 + BKP + External IO brake input polarity + + + 12 + 1 + BKE + The brake function is enabled + + + 11 + 1 + OSSR + Off state in run mode + + + 10 + 1 + OSSI + Off state in idle mode + + + 8 + 2 + LOCK + Lock setting + + + 0 + 8 + DTG + Dead zone generator setting + + + + + ALLCON + ALLCON + ALLCON + 0x5C + 0x20 + read-write + 0x00000000 + + + 24 + 1 + TES + TIM4/5/6 External IO brake signal selection + + + 16 + 6 + TS + TIM1 to TIM6 stops counting + + + 8 + 6 + TC + The TIM1 to TIM6 counters were cleared to zero + + + 0 + 6 + TK + TIM1 to TIM6 counters are enabled + + + + + + + + + + TIMER2 + TIMER2 unit + TIMER2 + 0x40020460 + + 0x0 + 0x60 + registers + + + + CR1 + CR1 + CR1 + 0x00 + 0x20 + read-write + 0x00000000 + + + 8 + 2 + CKD + Clock frequency division factor + + + 7 + 1 + ARPE + Automatic reloading preloading allows bits + + + 5 + 2 + CMS + Select the center alignment mode + + + 4 + 1 + DIR + Counting direction + + + 3 + 1 + OPM + Single pulse mode + + + 2 + 1 + URS + Update request source + + + 1 + 1 + UDIS + Forbid updating + + + 0 + 1 + CEN + Enable counter + + + + + CR2 + CR2 + CR2 + 0x04 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + TI1S + TI1 selection + + + 4 + 3 + MMS + Master mode selection + + + 3 + 1 + CCDS + DMA selection for capture/comparison + + + + + SMCR + SMCR + SMCR + 0x08 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ETP + External trigger polarity + + + 14 + 1 + ECE + External clock enable bit + + + 12 + 2 + ETPS + External trigger predivision + + + 8 + 4 + ETF + External trigger filtering + + + 7 + 1 + MSM + Master/slave mode + + + 4 + 3 + TS + Trigger selection + + + 0 + 3 + SMS + Mode selection + + + + + DIER + DIER + DIER + 0x0C + 0x20 + read-write + 0x00000000 + + + 14 + 1 + TDE + Allows DMA requests to be triggered + + + 12 + 1 + CC4DE + DMA requests for capture/compare 4 are allowed + + + 11 + 1 + CC3DE + DMA requests for capture/compare 3 are allowed + + + 10 + 1 + CC2DE + DMA requests for capture/compare 2 are allowed + + + 9 + 1 + CC1DE + DMA requests for capture/compare 1 are allowed + + + 8 + 1 + UDE + DMA requests that allow updates + + + 6 + 1 + TIE + The interrupt function was triggered + + + 4 + 1 + CC4IE + Allows capture/compare 4 interrupts + + + 3 + 1 + CC3IE + Allows capture/compare 3 interrupts + + + 2 + 1 + CC2IE + Allows capture/compare 2 interrupts + + + 1 + 1 + CC1IE + Allows capture/compare 1 interrupts + + + 0 + 1 + UIE + Allow update interrupt + + + + + SR + SR + SR + 0x10 + 0x20 + read-write + 0x00000000 + + + 12 + 1 + CC4OF + Capture 4 Repeat the capture tag + + + 11 + 1 + CC3OF + Capture 3 Repeat the capture tag + + + 10 + 1 + CC2OF + Capture 2 Repeat the capture tag + + + 9 + 1 + CC1OF + Capture 1 Repeat the capture tag + + + 6 + 1 + TIF + Trigger interrupt flag + + + 4 + 1 + CC4IF + Capture/compare 4 interrupt flags + + + 3 + 1 + CC3IF + Capture/compare 3 interrupt flags + + + 2 + 1 + CC2IF + Capture/compare 2 interrupt flags + + + 1 + 1 + CC1IF + Capture/compare 1 interrupt flags + + + 0 + 1 + UIF + Update interrupt flag + + + + + EGR + EGR + EGR + 0x14 + 0x20 + read-write + 0x00000000 + + + 6 + 1 + TG + Generate trigger event + + + 4 + 1 + CC4G + Generate the capture/Compare 4 event + + + 3 + 1 + CC3G + Generate the capture/Compare 3 event + + + 2 + 1 + CC2G + Generate the capture/Compare 2 event + + + 1 + 1 + CC1G + Generate the capture/Compare 1 event + + + 0 + 1 + UG + Generate update event + + + + + CCMR1 + CCMR1 + CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OC2CE + Output comparison 2 Clear 0 enable + + + 12 + 3 + OC2M + Output comparison 2 mode + + + 11 + 1 + OC2PE + Output comparison 2 Preload enable + + + 10 + 1 + OC2FE + Output comparison 2 Fast enable + + + 8 + 2 + CC2S + Capture/Compare 2 Select + + + 7 + 1 + OC1CE + Output comparison 1 Clear 0 enable + + + 4 + 3 + OC1M + Output comparison 1 mode + + + 3 + 1 + OC1PE + Output comparison 1 Preload enable + + + 2 + 1 + OC1FE + Output comparison 1 Fast enable + + + 0 + 2 + CC1S + Capture/Compare 1 Select + + + + + CCMR2 + CCMR2 + CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OC4CE + Output comparison 4 clear 0 enabled + + + 12 + 3 + OC4M + Output comparison 4 mode + + + 11 + 1 + OC4PE + Output comparison 4 Preload enable + + + 10 + 1 + OC4FE + Compare the output 4 Fast enable + + + 8 + 2 + CC4S + Capture/Compare 4 Select + + + 7 + 1 + OC3CE + Output comparison 3 clear 0 enabled + + + 4 + 3 + OC3M + Output comparison 3 mode + + + 3 + 1 + OC3PE + Output comparison 3 Preload enable + + + 2 + 1 + OC3FE + Compare the output 3 Fast enable + + + 0 + 2 + CC3S + Capture/Compare 3 Select + + + + + CCER + CCER + CCER + 0x20 + 0x20 + read-write + 0x00000000 + + + 13 + 1 + CC4P + Input/Capture 4 Output polarity + + + 12 + 1 + CC4E + Input/Capture 4 Enable the output + + + 11 + 1 + CC3NP + Input/Capture 3 Complementary output polarity + + + 9 + 1 + CC3P + Input/Capture 3 Output polarity + + + 8 + 1 + CC3E + Input/Capture 3 Output Enable + + + 7 + 1 + CC2NP + Input/Capture 2 Complementary output polarity + + + 5 + 1 + CC2P + Input/Capture 2 Output polarity + + + 4 + 1 + CC2E + Input/Capture 2 Output Enable + + + 3 + 1 + CC1NP + Input/Capture 1 Complementary output polarity + + + 1 + 1 + CC1P + Input/Capture 1 Output polarity + + + 0 + 1 + CC1E + Input/Capture 1 Output Enable + + + + + CNT + CNT + CNT + 0x24 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + CNT + Counter value + + + + + PSC + PSC + PSC + 0x28 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + PSC + The value of the pre-divider + + + + + ARR + ARR + ARR + 0x2C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + ARR + The value of automatic reloading + + + + + CCR1 + CCR1 + CCR1 + 0x34 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR1 + Capture/compare values for channel 1 + + + + + CCR2 + CCR2 + CCR2 + 0x38 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR2 + Capture/compare values for channel 2 + + + + + CCR3 + CCR3 + CCR3 + 0x3C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR3 + Capture/compare values for channel 3 + + + + + CCR4 + CCR4 + CCR4 + 0x40 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR4 + Capture/compare values for channel 4 + + + + + + + + + + TIMER3 + TIMER3 unit + TIMER3 + 0x400204C0 + + 0x0 + 0x60 + registers + + + + CR1 + CR1 + CR1 + 0x00 + 0x20 + read-write + 0x00000000 + + + 8 + 2 + CKD + Clock frequency division factor + + + 7 + 1 + ARPE + Automatic reloading preloading allows bits + + + 5 + 2 + CMS + Select the center alignment mode + + + 4 + 1 + DIR + Counting direction + + + 3 + 1 + OPM + Single pulse mode + + + 2 + 1 + URS + Update request source + + + 1 + 1 + UDIS + Forbid updating + + + 0 + 1 + CEN + Enable counter + + + + + CR2 + CR2 + CR2 + 0x04 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + TI1S + TI1 selection + + + 4 + 3 + MMS + Master mode selection + + + 3 + 1 + CCDS + DMA selection for capture/comparison + + + + + SMCR + SMCR + SMCR + 0x08 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ETP + External trigger polarity + + + 14 + 1 + ECE + External clock enable bit + + + 12 + 2 + ETPS + External trigger predivision + + + 8 + 4 + ETF + External trigger filtering + + + 7 + 1 + MSM + Master/slave mode + + + 4 + 3 + TS + Trigger selection + + + 0 + 3 + SMS + Mode selection + + + + + DIER + DIER + DIER + 0x0C + 0x20 + read-write + 0x00000000 + + + 14 + 1 + TDE + Allows DMA requests to be triggered + + + 12 + 1 + CC4DE + DMA requests for capture/compare 4 are allowed + + + 11 + 1 + CC3DE + DMA requests for capture/compare 3 are allowed + + + 10 + 1 + CC2DE + DMA requests for capture/compare 2 are allowed + + + 9 + 1 + CC1DE + DMA requests for capture/compare 1 are allowed + + + 8 + 1 + UDE + DMA requests that allow updates + + + 6 + 1 + TIE + The interrupt function was triggered + + + 4 + 1 + CC4IE + Allows capture/compare 4 interrupts + + + 3 + 1 + CC3IE + Allows capture/compare 3 interrupts + + + 2 + 1 + CC2IE + Allows capture/compare 2 interrupts + + + 1 + 1 + CC1IE + Allows capture/compare 1 interrupts + + + 0 + 1 + UIE + Allow update interrupt + + + + + SR + SR + SR + 0x10 + 0x20 + read-write + 0x00000000 + + + 12 + 1 + CC4OF + Capture 4 Repeat the capture tag + + + 11 + 1 + CC3OF + Capture 3 Repeat the capture tag + + + 10 + 1 + CC2OF + Capture 2 Repeat the capture tag + + + 9 + 1 + CC1OF + Capture 1 Repeat the capture tag + + + 6 + 1 + TIF + Trigger interrupt flag + + + 4 + 1 + CC4IF + Capture/compare 4 interrupt flags + + + 3 + 1 + CC3IF + Capture/compare 3 interrupt flags + + + 2 + 1 + CC2IF + Capture/compare 2 interrupt flags + + + 1 + 1 + CC1IF + Capture/compare 1 interrupt flags + + + 0 + 1 + UIF + Update interrupt flag + + + + + EGR + EGR + EGR + 0x14 + 0x20 + read-write + 0x00000000 + + + 6 + 1 + TG + Generate trigger event + + + 4 + 1 + CC4G + Generate the capture/Compare 4 event + + + 3 + 1 + CC3G + Generate the capture/Compare 3 event + + + 2 + 1 + CC2G + Generate the capture/Compare 2 event + + + 1 + 1 + CC1G + Generate the capture/Compare 1 event + + + 0 + 1 + UG + Generate update event + + + + + CCMR1 + CCMR1 + CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OC2CE + Output comparison 2 Clear 0 enable + + + 12 + 3 + OC2M + Output comparison 2 mode + + + 11 + 1 + OC2PE + Output comparison 2 Preload enable + + + 10 + 1 + OC2FE + Output comparison 2 Fast enable + + + 8 + 2 + CC2S + Capture/Compare 2 Select + + + 7 + 1 + OC1CE + Output comparison 1 Clear 0 enable + + + 4 + 3 + OC1M + Output comparison 1 mode + + + 3 + 1 + OC1PE + Output comparison 1 Preload enable + + + 2 + 1 + OC1FE + Output comparison 1 Fast enable + + + 0 + 2 + CC1S + Capture/Compare 1 Select + + + + + CCMR2 + CCMR2 + CCMR2 + 0x1C + 0x20 + read-write + 0x00000000 + + + 15 + 1 + OC4CE + Output comparison 4 clear 0 enabled + + + 12 + 3 + OC4M + Output comparison 4 mode + + + 11 + 1 + OC4PE + Output comparison 4 Preload enable + + + 10 + 1 + OC4FE + Compare the output 4 Fast enable + + + 8 + 2 + CC4S + Capture/Compare 4 Select + + + 7 + 1 + OC3CE + Output comparison 3 clear 0 enabled + + + 4 + 3 + OC3M + Output comparison 3 mode + + + 3 + 1 + OC3PE + Output comparison 3 Preload enable + + + 2 + 1 + OC3FE + Compare the output 3 Fast enable + + + 0 + 2 + CC3S + Capture/Compare 3 Select + + + + + CCER + CCER + CCER + 0x20 + 0x20 + read-write + 0x00000000 + + + 13 + 1 + CC4P + Input/Capture 4 Output polarity + + + 12 + 1 + CC4E + Input/Capture 4 Enable the output + + + 11 + 1 + CC3NP + Input/Capture 3 Complementary output polarity + + + 9 + 1 + CC3P + Input/Capture 3 Output polarity + + + 8 + 1 + CC3E + Input/Capture 3 Output Enable + + + 7 + 1 + CC2NP + Input/Capture 2 Complementary output polarity + + + 5 + 1 + CC2P + Input/Capture 2 Output polarity + + + 4 + 1 + CC2E + Input/Capture 2 Output Enable + + + 3 + 1 + CC1NP + Input/Capture 1 Complementary output polarity + + + 1 + 1 + CC1P + Input/Capture 1 Output polarity + + + 0 + 1 + CC1E + Input/Capture 1 Output Enable + + + + + CNT + CNT + CNT + 0x24 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + CNT + Counter value + + + + + PSC + PSC + PSC + 0x28 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + PSC + The value of the pre-divider + + + + + ARR + ARR + ARR + 0x2C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + ARR + The value of automatic reloading + + + + + CCR1 + CCR1 + CCR1 + 0x34 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR1 + Capture/compare values for channel 1 + + + + + CCR2 + CCR2 + CCR2 + 0x38 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR2 + Capture/compare values for channel 2 + + + + + CCR3 + CCR3 + CCR3 + 0x3C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR3 + Capture/compare values for channel 3 + + + + + CCR4 + CCR4 + CCR4 + 0x40 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR4 + Capture/compare values for channel 4 + + + + + + + + + + TIMER4 + TIMER4 unit + TIMER4 + 0x40020520 + + 0x0 + 0x60 + registers + + + + CR1 + CR1 + CR1 + 0x00 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + EKE + External IO brake input switch + + + 14 + 1 + SYSE + System error brake switch + + + 13 + 1 + C1BP + Comparator 1 brake polarity + + + 12 + 1 + C1BE + Comparator 1 brake switch + + + 11 + 1 + C0BP + Comparator 0 brake polarity + + + 10 + 1 + C0BE + Comparator 0 brake switch + + + 8 + 2 + CKD + Clock frequency division factor + + + 7 + 1 + ARPE + Automatic reloading preloading allows bits + + + 5 + 2 + CMS + Select the center alignment mode + + + 4 + 1 + DIR + Counting direction + + + 3 + 1 + OPM + Single pulse mode + + + 2 + 1 + URS + Update request source + + + 1 + 1 + UDIS + Forbid updating + + + 0 + 1 + CEN + Enable counter + + + + + CR2 + CR2 + CR2 + 0x04 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ADCBKEN + ADC brake switch + + + 10 + 1 + OIS2 + Output idle status 2 + + + 9 + 1 + OIS1N + Output idle status 1 + + + 8 + 1 + OIS1 + Output idle status 1 + + + 4 + 3 + MMS + Master mode selection + + + 3 + 1 + CCDS + DMA selection for capture/comparison + + + 2 + 1 + CCUS + Capture/compare control update selection + + + 0 + 1 + CCPC + Capture/compare preloaded control bits + + + + + SMCR + SMCR + SMCR + 0x08 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + MSM + Master/slave mode + + + 4 + 3 + TS + Trigger selection + + + 0 + 3 + SMS + Mode selection + + + + + DIER + DIER + DIER + 0x0C + 0x20 + read-write + 0x00000000 + + + 14 + 1 + TDE + Allows DMA requests to be triggered + + + 13 + 1 + COMDE + DMA requests for COM are allowed + + + 10 + 1 + CC2DE + DMA requests for capture/compare 2 are allowed + + + 9 + 1 + CC1DE + DMA requests for capture/compare 1 are allowed + + + 8 + 1 + UDE + DMA requests that allow updates + + + 7 + 1 + BIE + Allow brake break + + + 6 + 1 + TIE + The interrupt function was triggered + + + 5 + 1 + COMIE + Allow COM interrupt + + + 2 + 1 + CC2IE + Allows capture/compare 2 interrupts + + + 1 + 1 + CC1IE + Allows capture/compare 1 interrupts + + + 0 + 1 + UIE + Allow update interrupt + + + + + SR + SR + SR + 0x10 + 0x20 + read-write + 0x00000000 + + + 10 + 1 + CC2OF + Capture 2 Repeat the capture tag + + + 9 + 1 + CC1OF + Capture 1 Repeat the capture tag + + + 7 + 1 + BIF + Brake interrupt flag + + + 6 + 1 + TIF + Trigger interrupt flag + + + 5 + 1 + COMIF + COM interrupt flag + + + 2 + 1 + CC2IF + Capture/compare 2 interrupt flags + + + 1 + 1 + CC1IF + Capture/compare 1 interrupt flags + + + 0 + 1 + UIF + Update interrupt flag + + + + + EGR + EGR + EGR + 0x14 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + BG + Generating brake event + + + 6 + 1 + TG + Generate trigger event + + + 5 + 1 + COMG + Capture/compare event generation control updates + + + 2 + 1 + CC2G + Generate the capture/Compare 2 event + + + 1 + 1 + CC1G + Generate the capture/Compare 1 event + + + 0 + 1 + UG + Generate update event + + + + + CCMR1 + CCMR1 + CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + + + 12 + 3 + OC2M + Output comparison 2 mode + + + 11 + 1 + OC2PE + Output comparison 2 Preload enable + + + 10 + 1 + OC2FE + Output comparison 2 Fast enable + + + 8 + 2 + CC2S + Capture/Compare 2 Select + + + 4 + 3 + OC1M + Output comparison 1 mode + + + 3 + 1 + OC1PE + Output comparison 1 Preload enable + + + 2 + 1 + OC1FE + Output comparison 1 Fast enable + + + 0 + 2 + CC1S + Capture/Compare 1 Select + + + + + CCER + CCER + CCER + 0x20 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + CC2NP + Input/Capture 2 Complementary output polarity + + + 5 + 1 + CC2P + Input/Capture 2 Output polarity + + + 4 + 1 + CC2E + Input/Capture 2 Output Enable + + + 3 + 1 + CC1NP + Input/Capture 1 Complementary output polarity + + + 2 + 1 + CC1NE + Input/Capture 1 Enable complementary output + + + 1 + 1 + CC1P + Input/Capture 1 Output polarity + + + 0 + 1 + CC1E + Input/Capture 1 Output Enable + + + + + CNT + CNT + CNT + 0x24 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + CNT + Counter value + + + + + PSC + PSC + PSC + 0x28 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + PSC + The value of the pre-divider + + + + + ARR + ARR + ARR + 0x2C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + ARR + The value of automatic reloading + + + + + RCR + RCR + RCR + 0x30 + 0x20 + read-write + 0x00000000 + + + 0 + 8 + REP + Repeat the value of the counter + + + + + CCR1 + CCR1 + CCR1 + 0x34 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR1 + Capture/compare values for channel 1 + + + + + CCR2 + CCR2 + CCR2 + 0x38 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR2 + Capture/compare values for channel 2 + + + + + BDTR + BDTR + BDTR + 0x44 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + MOE + Master output is enabled + + + 14 + 1 + AOE + Automatic output is enabled + + + 13 + 1 + BKP + External IO brake input polarity + + + 12 + 1 + BKE + The brake function is enabled + + + 11 + 1 + OSSR + Off state in run mode + + + 10 + 1 + OSSI + Off state in idle mode + + + 8 + 2 + LOCK + Lock setting + + + 0 + 8 + DTG + Dead zone generator setting + + + + + + + + + + TIMER5 + TIMER5 unit + TIMER5 + 0x40020580 + + 0x0 + 0x60 + registers + + + + CR1 + CR1 + CR1 + 0x00 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + EKE + External IO brake input switch + + + 14 + 1 + SYSE + System error brake switch + + + 13 + 1 + C1BP + Comparator 1 brake polarity + + + 12 + 1 + C1BE + Comparator 1 brake switch + + + 11 + 1 + C0BP + Comparator 0 brake polarity + + + 10 + 1 + C0BE + Comparator 0 brake switch + + + 8 + 2 + CKD + Clock frequency division factor + + + 7 + 1 + ARPE + Automatic reloading preloading allows bits + + + 5 + 2 + CMS + Select the center alignment mode + + + 4 + 1 + DIR + Counting direction + + + 3 + 1 + OPM + Single pulse mode + + + 2 + 1 + URS + Update request source + + + 1 + 1 + UDIS + Forbid updating + + + 0 + 1 + CEN + Enable counter + + + + + CR2 + CR2 + CR2 + 0x04 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ADCBKEN + ADC brake switch + + + 10 + 1 + OIS2 + Output idle status 2 + + + 9 + 1 + OIS1N + Output idle status 1 + + + 8 + 1 + OIS1 + Output idle status 1 + + + 4 + 3 + MMS + Master mode selection + + + 3 + 1 + CCDS + DMA selection for capture/comparison + + + 2 + 1 + CCUS + Capture/compare control update selection + + + 0 + 1 + CCPC + Capture/compare preloaded control bits + + + + + SMCR + SMCR + SMCR + 0x08 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + MSM + Master/slave mode + + + 4 + 3 + TS + Trigger selection + + + 0 + 3 + SMS + Mode selection + + + + + DIER + DIER + DIER + 0x0C + 0x20 + read-write + 0x00000000 + + + 14 + 1 + TDE + Allows DMA requests to be triggered + + + 13 + 1 + COMDE + DMA requests for COM are allowed + + + 10 + 1 + CC2DE + DMA requests for capture/compare 2 are allowed + + + 9 + 1 + CC1DE + DMA requests for capture/compare 1 are allowed + + + 8 + 1 + UDE + DMA requests that allow updates + + + 7 + 1 + BIE + Allow brake break + + + 6 + 1 + TIE + The interrupt function was triggered + + + 5 + 1 + COMIE + Allow COM interrupt + + + 2 + 1 + CC2IE + Allows capture/compare 2 interrupts + + + 1 + 1 + CC1IE + Allows capture/compare 1 interrupts + + + 0 + 1 + UIE + Allow update interrupt + + + + + SR + SR + SR + 0x10 + 0x20 + read-write + 0x00000000 + + + 10 + 1 + CC2OF + Capture 2 Repeat the capture tag + + + 9 + 1 + CC1OF + Capture 1 Repeat the capture tag + + + 7 + 1 + BIF + Brake interrupt flag + + + 6 + 1 + TIF + Trigger interrupt flag + + + 5 + 1 + COMIF + COM interrupt flag + + + 2 + 1 + CC2IF + Capture/compare 2 interrupt flags + + + 1 + 1 + CC1IF + Capture/compare 1 interrupt flags + + + 0 + 1 + UIF + Update interrupt flag + + + + + EGR + EGR + EGR + 0x14 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + BG + Generating brake event + + + 6 + 1 + TG + Generate trigger event + + + 5 + 1 + COMG + Capture/compare event generation control updates + + + 2 + 1 + CC2G + Generate the capture/Compare 2 event + + + 1 + 1 + CC1G + Generate the capture/Compare 1 event + + + 0 + 1 + UG + Generate update event + + + + + CCMR1 + CCMR1 + CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + + + 12 + 3 + OC2M + Output comparison 2 mode + + + 11 + 1 + OC2PE + Output comparison 2 Preload enable + + + 10 + 1 + OC2FE + Output comparison 2 Fast enable + + + 8 + 2 + CC2S + Capture/Compare 2 Select + + + 4 + 3 + OC1M + Output comparison 1 mode + + + 3 + 1 + OC1PE + Output comparison 1 Preload enable + + + 2 + 1 + OC1FE + Output comparison 1 Fast enable + + + 0 + 2 + CC1S + Capture/Compare 1 Select + + + + + CCER + CCER + CCER + 0x20 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + CC2NP + Input/Capture 2 Complementary output polarity + + + 5 + 1 + CC2P + Input/Capture 2 Output polarity + + + 4 + 1 + CC2E + Input/Capture 2 Output Enable + + + 3 + 1 + CC1NP + Input/Capture 1 Complementary output polarity + + + 2 + 1 + CC1NE + Input/Capture 1 Enable complementary output + + + 1 + 1 + CC1P + Input/Capture 1 Output polarity + + + 0 + 1 + CC1E + Input/Capture 1 Output Enable + + + + + CNT + CNT + CNT + 0x24 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + CNT + Counter value + + + + + PSC + PSC + PSC + 0x28 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + PSC + The value of the pre-divider + + + + + ARR + ARR + ARR + 0x2C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + ARR + The value of automatic reloading + + + + + RCR + RCR + RCR + 0x30 + 0x20 + read-write + 0x00000000 + + + 0 + 8 + REP + Repeat the value of the counter + + + + + CCR1 + CCR1 + CCR1 + 0x34 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR1 + Capture/compare values for channel 1 + + + + + CCR2 + CCR2 + CCR2 + 0x38 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR2 + Capture/compare values for channel 2 + + + + + BDTR + BDTR + BDTR + 0x44 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + MOE + Master output is enabled + + + 14 + 1 + AOE + Automatic output is enabled + + + 13 + 1 + BKP + External IO brake input polarity + + + 12 + 1 + BKE + The brake function is enabled + + + 11 + 1 + OSSR + Off state in run mode + + + 10 + 1 + OSSI + Off state in idle mode + + + 8 + 2 + LOCK + Lock setting + + + 0 + 8 + DTG + Dead zone generator setting + + + + + + + + + + TIMER6 + TIMER6 unit + TIMER6 + 0x400205E0 + + 0x0 + 0x60 + registers + + + + CR1 + CR1 + CR1 + 0x00 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + EKE + External IO brake input switch + + + 14 + 1 + SYSE + System error brake switch + + + 13 + 1 + C1BP + Comparator 1 brake polarity + + + 12 + 1 + C1BE + Comparator 1 brake switch + + + 11 + 1 + C0BP + Comparator 0 brake polarity + + + 10 + 1 + C0BE + Comparator 0 brake switch + + + 8 + 2 + CKD + Clock frequency division factor + + + 7 + 1 + ARPE + Automatic reloading preloading allows bits + + + 5 + 2 + CMS + Select the center alignment mode + + + 4 + 1 + DIR + Counting direction + + + 3 + 1 + OPM + Single pulse mode + + + 2 + 1 + URS + Update request source + + + 1 + 1 + UDIS + Forbid updating + + + 0 + 1 + CEN + Enable counter + + + + + CR2 + CR2 + CR2 + 0x04 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + ADCBKEN + ADC brake switch + + + 10 + 1 + OIS2 + Output idle status 2 + + + 9 + 1 + OIS1N + Output idle status 1 + + + 8 + 1 + OIS1 + Output idle status 1 + + + 4 + 3 + MMS + Master mode selection + + + 3 + 1 + CCDS + DMA selection for capture/comparison + + + 2 + 1 + CCUS + Capture/compare control update selection + + + 0 + 1 + CCPC + Capture/compare preloaded control bits + + + + + SMCR + SMCR + SMCR + 0x08 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + MSM + Master/slave mode + + + 4 + 3 + TS + Trigger selection + + + 0 + 3 + SMS + Mode selection + + + + + DIER + DIER + DIER + 0x0C + 0x20 + read-write + 0x00000000 + + + 14 + 1 + TDE + Allows DMA requests to be triggered + + + 13 + 1 + COMDE + DMA requests for COM are allowed + + + 10 + 1 + CC2DE + DMA requests for capture/compare 2 are allowed + + + 9 + 1 + CC1DE + DMA requests for capture/compare 1 are allowed + + + 8 + 1 + UDE + DMA requests that allow updates + + + 7 + 1 + BIE + Allow brake break + + + 6 + 1 + TIE + The interrupt function was triggered + + + 5 + 1 + COMIE + Allow COM interrupt + + + 2 + 1 + CC2IE + Allows capture/compare 2 interrupts + + + 1 + 1 + CC1IE + Allows capture/compare 1 interrupts + + + 0 + 1 + UIE + Allow update interrupt + + + + + SR + SR + SR + 0x10 + 0x20 + read-write + 0x00000000 + + + 10 + 1 + CC2OF + Capture 2 Repeat the capture tag + + + 9 + 1 + CC1OF + Capture 1 Repeat the capture tag + + + 7 + 1 + BIF + Brake interrupt flag + + + 6 + 1 + TIF + Trigger interrupt flag + + + 5 + 1 + COMIF + COM interrupt flag + + + 2 + 1 + CC2IF + Capture/compare 2 interrupt flags + + + 1 + 1 + CC1IF + Capture/compare 1 interrupt flags + + + 0 + 1 + UIF + Update interrupt flag + + + + + EGR + EGR + EGR + 0x14 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + BG + Generating brake event + + + 6 + 1 + TG + Generate trigger event + + + 5 + 1 + COMG + Capture/compare event generation control updates + + + 2 + 1 + CC2G + Generate the capture/Compare 2 event + + + 1 + 1 + CC1G + Generate the capture/Compare 1 event + + + 0 + 1 + UG + Generate update event + + + + + CCMR1 + CCMR1 + CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + + + 12 + 3 + OC2M + Output comparison 2 mode + + + 11 + 1 + OC2PE + Output comparison 2 Preload enable + + + 10 + 1 + OC2FE + Output comparison 2 Fast enable + + + 8 + 2 + CC2S + Capture/Compare 2 Select + + + 4 + 3 + OC1M + Output comparison 1 mode + + + 3 + 1 + OC1PE + Output comparison 1 Preload enable + + + 2 + 1 + OC1FE + Output comparison 1 Fast enable + + + 0 + 2 + CC1S + Capture/Compare 1 Select + + + + + CCER + CCER + CCER + 0x20 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + CC2NP + Input/Capture 2 Complementary output polarity + + + 5 + 1 + CC2P + Input/Capture 2 Output polarity + + + 4 + 1 + CC2E + Input/Capture 2 Output Enable + + + 3 + 1 + CC1NP + Input/Capture 1 Complementary output polarity + + + 2 + 1 + CC1NE + Input/Capture 1 Enable complementary output + + + 1 + 1 + CC1P + Input/Capture 1 Output polarity + + + 0 + 1 + CC1E + Input/Capture 1 Output Enable + + + + + CNT + CNT + CNT + 0x24 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + CNT + Counter value + + + + + PSC + PSC + PSC + 0x28 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + PSC + The value of the pre-divider + + + + + ARR + ARR + ARR + 0x2C + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + ARR + The value of automatic reloading + + + + + RCR + RCR + RCR + 0x30 + 0x20 + read-write + 0x00000000 + + + 0 + 8 + REP + Repeat the value of the counter + + + + + CCR1 + CCR1 + CCR1 + 0x34 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR1 + Capture/compare values for channel 1 + + + + + CCR2 + CCR2 + CCR2 + 0x38 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + CCR2 + Capture/compare values for channel 2 + + + + + BDTR + BDTR + BDTR + 0x44 + 0x20 + read-write + 0x00000000 + + + 15 + 1 + MOE + Master output is enabled + + + 14 + 1 + AOE + Automatic output is enabled + + + 13 + 1 + BKP + External IO brake input polarity + + + 12 + 1 + BKE + The brake function is enabled + + + 11 + 1 + OSSR + Off state in run mode + + + 10 + 1 + OSSI + Off state in idle mode + + + 8 + 2 + LOCK + Lock setting + + + 0 + 8 + DTG + Dead zone generator setting + + + + + + + + + + TIMER7 + TIMER7 unit + TIMER7 + 0x40020310 + + 0x0 + 0x30 + registers + + + + CR1 + CR1 + CR1 + 0x00 + 0x20 + read-write + 0x00000000 + + + 7 + 1 + ARPE + Automatic reloading preloading allows bits + + + 3 + 1 + OPM + Single pulse mode + + + 2 + 1 + URS + Update request source + + + 1 + 1 + UDIS + Forbid updating + + + 0 + 1 + CEN + Enable counter + + + + + CR2 + CR2 + CR2 + 0x04 + 0x20 + read-write + 0x00000000 + + + 4 + 3 + MMS + Master mode selection + + + + + DIER + DIER + DIER + 0x0C + 0x20 + read-write + 0x00000000 + + + 8 + 1 + UDE + DMA requests that allow updates + + + 0 + 1 + UIE + Allow update interrupt + + + + + SR + SR + SR + 0x10 + 0x20 + read-write + 0x00000000 + + + 0 + 1 + UIF + Update interrupt flag + + + + + EGR + EGR + EGR + 0x14 + 0x20 + read-write + 0x00000000 + + + 0 + 1 + UG + Generate update event + + + + + CNT + CNT + CNT + 0x18 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + CNT + Counter value + + + + + PSC + PSC + PSC + 0x1C + 0x20 + read-write + 0x00000000 + + + 0 + 16 + PSC + The value of the pre-divider + + + + + ARR + ARR + ARR + 0x20 + 0x20 + read-write + 0x0000ffff + + + 0 + 16 + ARR + The value of automatic reloading + + + + + + + + + + ADC + ADC unit + ADC + 0x40020140 + + 0x0 + 0x50 + registers + + + + CFG + CFG + CFG + 0x00 + 0x20 + read-write + 0x000040fe + + + 20 + 1 + VCME + Enable VCM in ADC register + + + 19 + 1 + LE + Internal LDO of ADC module + + + 13 + 4 + SMPCYC + The interval between transitions + + + 4 + 6 + PSC + ADC predivision + + + 1 + 3 + VS + ADC reference voltage selection + + + 0 + 1 + EN + ADC enablement + + + + + CR + CR + CR + 0x04 + 0x20 + read-write + 0x00400000 + + + 31 + 1 + SR + The software resets the internal state machine of the module + + + 27 + 1 + OIE + Overrun Interrupt enable bit + + + 26 + 1 + WIE + Threshold Watchdog interrupt enable bit + + + 25 + 1 + IEM + A/D interrupt mode bit + + + 24 + 1 + JIE + Injection channel A/D transition interrupt enable bit + + + 23 + 1 + RIE + Rule channel A/D transition interrupt enable bit + + + 22 + 1 + CE + Hardware data calibration enable bit + + + 21 + 1 + JDEN + Injection channel DMA enabled + + + 20 + 1 + RDEN + Enable regular channel DMA + + + 19 + 1 + CTU + Continuous conversion + + + 18 + 1 + AJC + Automatically starts the injection channel group conversion + + + 17 + 1 + DS + Data expansion bit selection + + + 16 + 1 + ALIGN + Data alignment + + + 15 + 1 + JK + The transformation of the injection channel begins + + + 12 + 3 + JTD + Delay sampling is triggered outside the injection channel + + + 8 + 4 + JTS + Trigger source selection for the injection channel + + + 7 + 1 + RK + The conversion of the regular channel begins + + + 4 + 3 + RTD + Delayed sampling is triggered externally by a regular channel + + + 0 + 4 + RTS + Trigger source selection for a rule channel + + + + + STA + STA + STA + 0x08 + 0x20 + read-write + 0x00000000 + + + 24 + 4 + CHANNEL + Current transfer channel + + + 23 + 1 + BUSY + Busy/idle flag + + + 22 + 1 + WP + Threshold watchdog flag bit + + + 21 + 1 + JEIF + Injection channel A/D conversion end flag bit + + + 20 + 1 + REIF + Rule channel A/D conversion end flag bit + + + 16 + 4 + JP + Injection channel conversion complete flag bit + + + 0 + 16 + RP + Regular channel conversion complete flag bit + + + + + WDGCFG0 + WDGCFG0 + WDGCFG0 + 0x0C + 0x20 + read-write + 0x00000000 + + + 15 + 4 + CHS + Watchdog channel selector bit + + + 14 + 1 + CHM + Watchdog channel selection mode + + + 13 + 1 + RE + Turn on the watchdog in the regular aisle + + + 12 + 1 + JE + Enable watchdog on the injection channel + + + 0 + 12 + HTH + Watchdog high threshold + + + + + WDGCFG1 + WDGCFG1 + WDGCFG1 + 0x10 + 0x20 + read-write + 0x00000000 + + + 0 + 12 + LTH + Watchdog low threshold + + + + + RSEQCFG0 + RSEQCFG0 + RSEQCFG0 + 0x14 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + RSEQ7 + Channel configuration for rule sequence index 7 + + + 24 + 4 + RSEQ6 + Channel configuration for rule sequence index 6 + + + 20 + 4 + RSEQ5 + Channel configuration for rule sequence index 5 + + + 16 + 4 + RSEQ4 + Channel configuration for rule sequence index 4 + + + 12 + 4 + RSEQ3 + Channel configuration for rule sequence index 3 + + + 8 + 4 + RSEQ2 + Channel configuration for rule sequence index 2 + + + 4 + 4 + RSEQ1 + Channel configuration for rule sequence index 1 + + + 0 + 4 + RSEQ0 + Channel configuration for rule sequence index 0 + + + + + RSEQCFG1 + RSEQCFG1 + RSEQCFG1 + 0x18 + 0x20 + read-write + 0x00000000 + + + 28 + 4 + RSEQ15 + Channel configuration for rule sequence index 15 + + + 24 + 4 + RSEQ14 + Channel configuration for rule sequence index 14 + + + 20 + 4 + RSEQ13 + Channel configuration for rule sequence index 13 + + + 16 + 4 + RSEQ12 + Channel configuration for rule sequence index 12 + + + 12 + 4 + RSEQ11 + Channel configuration for rule sequence index 11 + + + 8 + 4 + RSEQ10 + Channel configuration for rule sequence index 10 + + + 4 + 4 + RSEQ9 + Channel configuration for rule sequence index 9 + + + 0 + 4 + RSEQ8 + Channel configuration for rule sequence index 8 + + + + + RSEQCFG2 + RSEQCFG2 + RSEQCFG2 + 0x1C + 0x20 + read-write + 0x00000000 + + + 8 + 4 + RT + Number of indexes for each conversion triggered by a rule sequence + + + 4 + 4 + RE + Regular sequence conversion ends index + + + 0 + 4 + RS + Regular sequence converts start index + + + + + JSEQCFG + JSEQCFG + JSEQCFG + 0x20 + 0x20 + read-write + 0x00000000 + + + 20 + 2 + JT + The number of indexes for each conversion triggered by the injection sequence + + + 18 + 2 + JE + The injection sequence converts the end index + + + 16 + 2 + JS + The injection sequence converts the star index + + + 12 + 4 + JSEQ3 + Channel configuration for injection sequence index 3 + + + 8 + 4 + JSEQ2 + Channel configuration for injection sequence index 2 + + + 4 + 4 + JSEQ1 + Channel configuration for injection sequence index 1 + + + 0 + 4 + JSEQ0 + Channel configuration for injection sequence index 0 + + + + + JDATA0 + JDATA0 + JDATA0 + 0x24 + 0x20 + read-write + 0x00000000 + + + 23 + 1 + VALID + DATA Indicates a valid flag bit + + + 22 + 1 + OP + Data override flag bit + + + 16 + 4 + DC + Displays the channel corresponding to the current data + + + 0 + 16 + DATA + 12-bit A/D conversion result + + + + + JDATA1 + JDATA1 + JDATA1 + 0x28 + 0x20 + read-write + 0x00000000 + + + 23 + 1 + VALID + DATA Indicates a valid flag bit + + + 22 + 1 + OP + Data override flag bit + + + 16 + 4 + DC + Displays the channel corresponding to the current data + + + 0 + 16 + DATA + 12-bit A/D conversion result + + + + + JDATA2 + JDATA2 + JDATA2 + 0x2C + 0x20 + read-write + 0x00000000 + + + 23 + 1 + VALID + DATA Indicates a valid flag bit + + + 22 + 1 + OP + Data override flag bit + + + 16 + 4 + DC + Displays the channel corresponding to the current data + + + 0 + 16 + DATA + 12-bit A/D conversion result + + + + + JDATA3 + JDATA3 + JDATA3 + 0x30 + 0x20 + read-write + 0x00000000 + + + 23 + 1 + VALID + DATA Indicates a valid flag bit + + + 22 + 1 + OP + Data override flag bit + + + 16 + 4 + DC + Displays the channel corresponding to the current data + + + 0 + 16 + DATA + 12-bit A/D conversion result + + + + + DATA + DATA + DATA + 0x34 + 0x20 + read-write + 0x00000000 + + + 23 + 1 + VALID + DATA Indicates a valid flag bit + + + 22 + 1 + OP + Data override flag bit + + + 16 + 4 + DC + Displays the channel corresponding to the current data + + + 0 + 16 + DATA + 12-bit A/D conversion result + + + + + BUFCAL + BUFCAL + BUFCAL + 0x4C + 0x20 + read-write + 0x00000000 + + + 0 + 8 + BUFCAL + Simulates internal buffer offset calibration control + + + + + + + + + + COMP0 + COMP0 unit + COMP0 + 0x40020370 + + 0x0 + 0x10 + registers + + + + CON + CON + CON + 0x00 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + LOCK + Register lock + + + 29 + 1 + WKUPEN + Comparator wake up + + + 27 + 2 + EDGSEL + Edge detection selection + + + 26 + 1 + INTEN + Interrupt switch + + + 21 + 5 + FILTNUM + Filter coefficient + + + 20 + 1 + INVEN + The output of the comparator is inverted + + + 18 + 2 + HYST + Hysteresis voltage selection + + + 16 + 2 + ILPS + Low power control + + + 13 + 3 + MUXN + Negative input + + + 10 + 3 + MUXP + Positive input + + + 4 + 6 + VSRS + Internal 6bit DAC voltage gear + + + 3 + 1 + VRSAO + Internal 6bit DAC output via VRSAOUT + + + 2 + 1 + VRSEL + Internal 6bit DAC reference source + + + 1 + 1 + VRSEN + Internal 6bit DAC switch + + + 0 + 1 + AEN + Comparator module switch + + + + + STA + STA + STA + 0x04 + 0x20 + read-write + 0x00000000 + + + 0 + 1 + PEND + Comparator PEND bit + + + + + + + + + + COMP1 + COMP1 unit + COMP1 + 0x40020380 + + 0x0 + 0x10 + registers + + + + CON + CON + CON + 0x00 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + LOCK + Register lock + + + 29 + 1 + WKUPEN + Comparator wake up + + + 27 + 2 + EDGSEL + Edge detection selection + + + 26 + 1 + INTEN + Interrupt switch + + + 21 + 5 + FILTNUM + Filter coefficient + + + 20 + 1 + INVEN + The output of the comparator is inverted + + + 18 + 2 + HYST + Hysteresis voltage selection + + + 16 + 2 + ILPS + Low power control + + + 13 + 3 + MUXN + Negative input + + + 10 + 3 + MUXP + Positive input + + + 4 + 6 + VSRS + Internal 6bit DAC voltage gear + + + 3 + 1 + VRSAO + Internal 6bit DAC output via VRSAOUT + + + 2 + 1 + VRSEL + Internal 6bit DAC reference source + + + 1 + 1 + VRSEN + Internal 6bit DAC switch + + + 0 + 1 + AEN + Comparator module switch + + + + + STA + STA + STA + 0x04 + 0x20 + read-write + 0x00000000 + + + 0 + 1 + PEND + Comparator PEND bit + + + + + + + + + + OPAM0 + OPAM0 unit + OPAM0 + 0x40020390 + + 0x0 + 0x08 + registers + + + + CON + CON + CON + 0x00 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + LOCK + Register lock + + + 23 + 2 + NEGSEL + Negative input selection + + + 21 + 2 + POSSEL + Positive input selection + + + 18 + 3 + PGASEL + Unipolar/differential internal gain selection + + + 7 + 1 + CMODE + Working mode + + + 6 + 1 + NEGEN + Negative input switch + + + 5 + 1 + OP2VAEN + The op amp outputs to the ADC switch + + + 4 + 1 + OP2VOEN + The op amp outputs to the IO switch + + + 3 + 1 + PGAEN + Internal gain switch + + + 2 + 1 + POSEN + Positive input switch + + + 1 + 1 + VCMEN + VCM voltage mode + + + 0 + 1 + AEN + OPAM module switch + + + + + + + + + + OPAM1 + OPAM1 unit + OPAM1 + 0x40020398 + + 0x0 + 0x08 + registers + + + + CON + CON + CON + 0x00 + 0x20 + read-write + 0x00000000 + + + 31 + 1 + LOCK + Register lock + + + 23 + 2 + NEGSEL + Negative input selection + + + 21 + 2 + POSSEL + Positive input selection + + + 18 + 3 + PGASEL + Unipolar/differential internal gain selection + + + 7 + 1 + CMODE + Working mode + + + 6 + 1 + NEGEN + Negative input switch + + + 5 + 1 + OP2VAEN + The op amp outputs to the ADC switch + + + 4 + 1 + OP2VOEN + The op amp outputs to the IO switch + + + 3 + 1 + PGAEN + Internal gain switch + + + 2 + 1 + POSEN + Positive input switch + + + 1 + 1 + VCMEN + VCM voltage mode + + + 0 + 1 + AEN + OPAM module switch + + + + + + + + + + WDT + WDT unit + WDT + 0x40020190 + + 0x0 + 0x10 + registers + + + + CON + CON + CON + 0x00 + 0x20 + read-write + 0x00000018 + + + 9 + 1 + WE + Wake up enable + + + 6 + 1 + WPEND + The guard dog counts up the signs + + + 5 + 1 + IE + Interrupt enablement + + + 4 + 1 + WES + Watchdog enabled status + + + 0 + 4 + WPSR + Frequency division coefficient + + + + + KEY + KEY + KEY + 0x04 + 0x20 + read-write + 0x00000000 + + + 0 + 16 + KEY + WDT key + + + + + + + + + + WWDG + WWDG unit + WWDG + 0x400201A0 + + 0x0 + 0x10 + registers + + + + CR + CR + CR + 0x00 + 0x20 + read-write + 0x0000007f + + + 7 + 1 + WDGA + Activation bit + + + 0 + 7 + T + 7-bit counter + + + + + CFR + CFR + CFR + 0x04 + 0x20 + read-write + 0x0000007f + + + 9 + 1 + EWI + Wake up early interrupt + + + 7 + 2 + WDGTB + Time base + + + 0 + 7 + W + 7 bit window value + + + + + SR + SR + SR + 0x08 + 0x20 + read-write + 0x0000007f + + + 0 + 1 + EWIF + Wake up early interrupt flag + + + + + + + + + + DMA + DMA unit + DMA + 0x40030000 + + 0x0 + 0x200 + registers + + + + CH0CR + CH0CR + CH0CR + 0x0000 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 0 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 0 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 0 + + + 7 + 1 + SRCAMOD + Channel 0 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 0 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 0 Enable control bit + + + + + CH1CR + CH1CR + CH1CR + 0x0018 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 1 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 1 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 1 + + + 7 + 1 + SRCAMOD + Channel 1 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 1 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 1 Enable control bit + + + + + CH2CR + CH2CR + CH2CR + 0x0030 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 2 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 2 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 2 + + + 7 + 1 + SRCAMOD + Channel 2 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 2 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 2 Enable control bit + + + + + CH3CR + CH3CR + CH3CR + 0x0048 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 3 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 3 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 3 + + + 7 + 1 + SRCAMOD + Channel 3 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 3 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 3 Enable control bit + + + + + CH4CR + CH4CR + CH4CR + 0x0060 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 4 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 4 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 4 + + + 7 + 1 + SRCAMOD + Channel 4 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 4 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 4 Enable control bit + + + + + CH5CR + CH5CR + CH5CR + 0x0078 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 5 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 5 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 5 + + + 7 + 1 + SRCAMOD + Channel 5 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 5 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 5 Enable control bit + + + + + CH6CR + CH6CR + CH6CR + 0x0090 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 6 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 6 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 6 + + + 7 + 1 + SRCAMOD + Channel 6 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 6 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 6 Enable control bit + + + + + CH7CR + CH7CR + CH7CR + 0x00A8 + 0x20 + read-write + 0x00000000 + + + 16 + 6 + TRGSRC + Hardware is sent from peripherals + + + 11 + 1 + AUTORL + Channel 7 Automatic overload enable control bit + + + 10 + 1 + FIXAEN + Channel 7 Fixed address enable control bit + + + 8 + 2 + CHPRI + Priority of channel 7 + + + 7 + 1 + SRCAMOD + Channel 7 Source address mode selection bit + + + 5 + 1 + DSTAMOD + Channel 7 Destination address mode selection bit + + + 2 + 2 + DWIDTH + Data bit width select bit + + + 1 + 1 + SWTRIG + Software trigger control bit + + + 0 + 1 + CHEN + Channel 7 Enable control bit + + + + + CH0SADR + CH0SADR + CH0SADR + 0x0004 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 0 Source address + + + + + CH1SADR + CH1SADR + CH1SADR + 0x001C + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 1 Source address + + + + + CH2SADR + CH2SADR + CH2SADR + 0x0034 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 2 Source address + + + + + CH3SADR + CH3SADR + CH3SADR + 0x004C + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 3 Source address + + + + + CH4SADR + CH4SADR + CH4SADR + 0x0064 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 4 Source address + + + + + CH5SADR + CH5SADR + CH5SADR + 0x007C + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 5 Source address + + + + + CH6SADR + CH6SADR + CH6SADR + 0x0094 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 6 Source address + + + + + CH7SADR + CH7SADR + CH7SADR + 0x00AC + 0x20 + read-write + 0x00000000 + + + 0 + 32 + SADR + Channel 7 Source address + + + + + CH0DADR + CH0DADR + CH0DADR + 0x0008 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 0 Destination address + + + + + CH1DADR + CH1DADR + CH1DADR + 0x0020 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 1 Destination address + + + + + CH2DADR + CH2DADR + CH2DADR + 0x0038 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 2 Destination address + + + + + CH3DADR + CH3DADR + CH3DADR + 0x0050 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 3 Destination address + + + + + CH4DADR + CH4DADR + CH4DADR + 0x0068 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 4 Destination address + + + + + CH5DADR + CH5DADR + CH5DADR + 0x0080 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 5 Destination address + + + + + CH6DADR + CH6DADR + CH6DADR + 0x0098 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 6 Destination address + + + + + CH7DADR + CH7DADR + CH7DADR + 0x00B0 + 0x20 + read-write + 0x00000000 + + + 0 + 32 + DADR + Channel 7 Destination address + + + + + CH0TSR + CH0TSR + CH0TSR + 0x0010 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 0 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 0 block + + + + + CH1TSR + CH1TSR + CH1TSR + 0x0028 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 1 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 1 block + + + + + CH2TSR + CH2TSR + CH2TSR + 0x0040 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 2 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 2 block + + + + + CH3TSR + CH3TSR + CH3TSR + 0x0058 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 3 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 3 block + + + + + CH4TSR + CH4TSR + CH4TSR + 0x0070 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 4 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 4 block + + + + + CH5TSR + CH5TSR + CH5TSR + 0x0088 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 5 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 5 block + + + + + CH6TSR + CH6TSR + CH6TSR + 0x00A0 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 6 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 6 block + + + + + CH7TSR + CH7TSR + CH7TSR + 0x00B8 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + BLKCNT + Number of channel 7 blocks processed + + + 0 + 5 + BLKLEN + Length of the channel 7 block + + + + + CH0CTSR + CH0CTSR + CH0CTSR + 0x0014 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 0 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 0 Indicates the current block length + + + + + CH1CTSR + CH1CTSR + CH1CTSR + 0x002C + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 1 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 1 Indicates the current block length + + + + + CH2CTSR + CH2CTSR + CH2CTSR + 0x0044 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 2 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 2 Indicates the current block length + + + + + CH3CTSR + CH3CTSR + CH3CTSR + 0x005C + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 3 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 3 Indicates the current block length + + + + + CH4CTSR + CH4CTSR + CH4CTSR + 0x0074 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 4 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 4 Indicates the current block length + + + + + CH5CTSR + CH5CTSR + CH5CTSR + 0x008C + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 5 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 5 Indicates the current block length + + + + + CH6CTSR + CH6CTSR + CH6CTSR + 0x00A4 + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 6 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 6 Indicates the current block length + + + + + CH7CTSR + CH7CTSR + CH7CTSR + 0x00BC + 0x20 + read-write + 0x00000000 + + + 12 + 12 + CBLKCNT + Channel 7 Indicates the number of blocks + + + 0 + 5 + CBLKLEN + Channel 7 Indicates the current block length + + + + + ISR0 + ISR0 + ISR0 + 0x0120 + 0x20 + read-write + 0x00000000 + + + 29 + 1 + TEISTA5 + Channel 5 Transmission error interrupt status bit + + + 28 + 1 + TCISTA5 + Channel 5 Transmission completion interrupt status bit + + + 27 + 1 + HTISTA5 + Channel 5 half transmission interrupt status bit + + + 26 + 1 + BEISTA5 + Channel 5 block processing end interrupt status bit + + + 24 + 1 + TEISTA4 + Channel 4 Transmission error interrupt status bit + + + 23 + 1 + TCISTA4 + Channel 4 Transmission completion interrupt status bit + + + 22 + 1 + HTISTA4 + Channel 4 half transmission interrupt status bit + + + 21 + 1 + BEISTA4 + Channel 4 block processing end interrupt status bit + + + 19 + 1 + TEISTA3 + Channel 3 Transmission error interrupt status bit + + + 18 + 1 + TCISTA3 + Channel 3 Transmission completion interrupt status bit + + + 17 + 1 + HTISTA3 + Channel 3 half transmission interrupt status bit + + + 16 + 1 + BEISTA3 + Channel 3 block processing end interrupt status bit + + + 14 + 1 + TEISTA2 + Channel 2 Transmission error interrupt status bit + + + 13 + 1 + TCISTA2 + Channel 2 Transmission completion interrupt status bit + + + 12 + 1 + HTISTA2 + Channel 2 half transmission interrupt status bit + + + 11 + 1 + BEISTA2 + Channel 2 block processing end interrupt status bit + + + 9 + 1 + TEISTA1 + Channel 1 Transmission error interrupt status bit + + + 8 + 1 + TCISTA1 + Channel 1 Transmission completion interrupt status bit + + + 7 + 1 + HTISTA1 + Channel 1 half transmission interrupt status bit + + + 6 + 1 + BEISTA1 + Channel 1 block processing end interrupt status bit + + + 4 + 1 + TEISTA0 + Channel 0 Transmission error interrupt status bit + + + 3 + 1 + TCISTA0 + Channel 0 Transmission completion interrupt status bit + + + 2 + 1 + HTISTA0 + Channel 0 half transmission interrupt status bit + + + 1 + 1 + BEISTA0 + Channel 0 block processing end interrupt status bit + + + + + ISR1 + ISR1 + ISR1 + 0x0124 + 0x20 + read-write + 0x00000000 + + + 9 + 1 + TEISTA7 + Channel 7 Transmission error interrupt status bit + + + 8 + 1 + TCISTA7 + Channel 7 Transmission completion interrupt status bit + + + 7 + 1 + HTISTA7 + Channel 7 half transmission interrupt status bit + + + 6 + 1 + BEISTA7 + Channel 7 block processing end interrupt status bit + + + 4 + 1 + TEISTA6 + Channel 6 Transmission error interrupt status bit + + + 3 + 1 + TCISTA6 + Channel 6 Transmission completion interrupt status bit + + + 2 + 1 + HTISTA6 + Channel 6 half transmission interrupt status bit + + + 1 + 1 + BEISTA6 + Channel 6 block processing end interrupt status bit + + + + + IER0 + IER0 + IER0 + 0x0130 + 0x20 + read-write + 0x00000000 + + + 29 + 1 + TEIE5 + Channel 5 Transmission error interrupt enable control bit + + + 28 + 1 + TCIE5 + Channel 5 Transmission complete interrupt enable control bit + + + 27 + 1 + HTIE5 + Channel 5 half transmission interrupt enable control bit + + + 26 + 1 + BEIE5 + Channel 5 block processing end interrupt enable control bit + + + 24 + 1 + TEIE4 + Channel 4 Transmission error interrupt enable control bit + + + 23 + 1 + TCIE4 + Channel 4 Transmission complete interrupt enable control bit + + + 22 + 1 + HTIE4 + Channel 4 half transmission interrupt enable control bit + + + 21 + 1 + BEIE4 + Channel 4 block processing end interrupt enable control bit + + + 19 + 1 + TEIE3 + Channel 3 Transmission error interrupt enable control bit + + + 18 + 1 + TCIE3 + Channel 3 Transmission complete interrupt enable control bit + + + 17 + 1 + HTIE3 + Channel 3 half transmission interrupt enable control bit + + + 16 + 1 + BEIE3 + Channel 3 block processing end interrupt enable control bit + + + 14 + 1 + TEIE2 + Channel 2 Transmission error interrupt enable control bit + + + 13 + 1 + TCIE2 + Channel 2 Transmission complete interrupt enable control bit + + + 12 + 1 + HTIE2 + Channel 2 half transmission interrupt enable control bit + + + 11 + 1 + BEIE2 + Channel 2 block processing end interrupt enable control bit + + + 9 + 1 + TEIE1 + Channel 1 Transmission error interrupt enable control bit + + + 8 + 1 + TCIE1 + Channel 1 Transmission complete interrupt enable control bit + + + 7 + 1 + HTIE1 + Channel 1 half transmission interrupt enable control bit + + + 6 + 1 + BEIE1 + Channel 1 block processing end interrupt enable control bit + + + 4 + 1 + TEIE0 + Channel 0 Transmission error interrupt enable control bit + + + 3 + 1 + TCIE0 + Channel 0 Transmission complete interrupt enable control bit + + + 2 + 1 + HTIE0 + Channel 0 half transmission interrupt enable control bit + + + 1 + 1 + BEIE0 + Channel 0 block processing end interrupt enable control bit + + + + + IER1 + IER1 + IER1 + 0x0134 + 0x20 + read-write + 0x00000000 + + + 9 + 1 + TEIE7 + Channel 7 Transmission error interrupt enable control bit + + + 8 + 1 + TCIE7 + Channel 7 Transmission complete interrupt enable control bit + + + 7 + 1 + HTIE7 + Channel 7 half transmission interrupt enable control bit + + + 6 + 1 + BEIE7 + Channel 7 block processing end interrupt enable control bit + + + 4 + 1 + TEIE6 + Channel 6 Transmission error interrupt enable control bit + + + 3 + 1 + TCIE6 + Channel 6 Transmission complete interrupt enable control bit + + + 2 + 1 + HTIE6 + Channel 6 half transmission interrupt enable control bit + + + 1 + 1 + BEIE6 + Channel 6 block processing end interrupt enable control bit + + + + + + + + + + SYSTEM + SYSTEM unit + SYSTEM + 0x40020000 + + 0x0 + 0x80 + registers + + + + SYSKEY + SYSKEY + SYSKEY + 0x0000 + 0x20 + read-write + 0x00000001 + + + 0 + 32 + SK + System register write is enabled + + + + + SYSCON0 + SYSCON0 + SYSCON0 + 0x0004 + 0x20 + read-write + 0x069f9040 + + + 31 + 1 + FRE + Quick release reset + + + 30 + 1 + SGE + Reset when the system wakes up + + + 27 + 3 + SDC + IO wake up delay SLEEP_DLY_CNT system clock cycles + + + 26 + 1 + DSR + IO buffeting circuit software reset control + + + 25 + 1 + CRCSR + CRC computing unit software reset control + + + 23 + 1 + HSR + HWDIV software reset control + + + 20 + 1 + GSR + GPIO related register software reset control + + + 19 + 1 + ASR + ADC related register software reset control + + + 18 + 1 + U1SR + UART1 related register software reset control + + + 17 + 1 + U0SR + UART0 related register software reset control + + + 16 + 1 + SI1SR + SPI_IIC1 related register software reset control + + + 15 + 1 + SI0SR + SPI_IIC0 related register software reset control + + + 12 + 1 + CMPSR + COMP_OPAM related register software reset control + + + 6 + 1 + TSR + TIMER related register software reset control + + + + + SYSCON1 + SYSCON1 + SYSCON1 + 0x0008 + 0x20 + read-write + 0x00000300 + + + 31 + 1 + STOF + TIMER Output channel Output is enabled + + + 17 + 1 + CMIS + The MCLR function was enabled in CP mode + + + 13 + 1 + WLGE + The watchdog automatically turns off the clock when it enters sleep/stop mode + + + 12 + 1 + DE + DEBUG enable + + + 11 + 1 + IRE + Map interrupt entry from FLASH to SRAM + + + 10 + 1 + NIS + NMI pin polarity reverse selection + + + 9 + 1 + CMSE + Select the system clock in CP mode + + + 8 + 1 + SWDE + SWD Enables the control function + + + 7 + 1 + LWE + LVDVCC wakes up the system in interrupt mode + + + 5 + 1 + SERE + Returns an error signal to the CPU + + + 4 + 1 + SEIE + The NMI interrupt is triggered + + + 2 + 1 + RXEVE + The CPU received events was enabled + + + 1 + 1 + NIE + PB5 triggers the NMI interrupt function + + + 0 + 1 + LOCKE + The system reset is triggered when an out-of-bounds address is accessed twice + + + + + SYSCON2 + SYSCON2 + SYSCON2 + 0x000C + 0x20 + read-write + 0x00000000 + + + 16 + 16 + PBDE + PB antishudder control + + + 0 + 16 + PADE + PA antishudder control + + + + + SYSCON3 + SYSCON3 + SYSCON3 + 0x0010 + 0x20 + read-write + 0x00000000 + + + 0 + 12 + PCDE + PC antishudder control + + + + + CLKCON0 + CLKCON0 + CLKCON0 + 0x0024 + 0x20 + read-write + 0x00000000 + + + 16 + 2 + LDCS + LVD anti-shake clock selection + + + 6 + 2 + GDCS + GPIO anti-shake clock selection + + + 0 + 2 + SCS + System clock selection + + + + + CLKCON1 + CLKCON1 + CLKCON1 + 0x0028 + 0x20 + read-write + 0xf8000000 + + + 0 + 6 + SCD + System clock frequency division + + + + + CLKCON2 + CLKCON2 + CLKCON2 + 0x002C + 0x20 + read-write + 0x07878ff4 + + + 26 + 1 + COMPCE + The COMP_OPAM clock is enabled + + + 25 + 1 + CRCCE + The CRC clock is enabled + + + 24 + 1 + FMCE + The FLASH erase or write clock function is enabled + + + 23 + 1 + HCE + The HWDIV clock is enabled + + + 18 + 1 + U1CE + The UART1 clock is enabled + + + 17 + 1 + U0CE + The UART0 clock is enabled + + + 16 + 1 + SI1CE + The SPI_IIC1 clock is enabled + + + 15 + 1 + SI0CE + The SPI_IIC0 clock is enabled + + + 11 + 1 + WCE + The WWDG clock is enabled + + + 4 + 7 + TCE + The TIMERx clock is enabled + + + 2 + 1 + SRCE + The SRAM0 clock is enabled + + + + + CLKCON3 + CLKCON3 + CLKCON3 + 0x0030 + 0x20 + read-write + 0x80020240 + + + 31 + 1 + HEF + HIRC_CLK Enables the flag bit + + + 18 + 12 + HFSC + HIRC_CLK frequency control + + + 17 + 1 + HE + HIRC_CLK Enables control + + + 10 + 2 + HFSEL + HIRC frequency selection + + + 7 + 3 + HFT + HIRC temperature compensation coefficient + + + 2 + 5 + HFFS + HIRC fine tune control + + + 1 + 1 + HASEL + HIRC simulation test selection + + + 0 + 1 + HASEN + Enable HIRC simulation test + + + + + SYSERR + SYSERR + SYSERR + 0x0048 + 0x20 + read-write + 0x00000000 + + + 1 + 0 + CE + The clock uses an error flag + + + 0 + 1 + SE + System bus access out of bounds address error flag + + + + + WKUPCON + WKUPCON + WKUPCON + 0x004C + 0x20 + read-write + 0x00000000 + + + 24 + 4 + CWP + Software write 1 Clear WKUP_PEND + + + 16 + 4 + WP + IO edge wake up flag + + + 8 + 4 + WEDGE + Wake up edge selection + + + 0 + 4 + WEN + IO edge detection wakes up + + + + + LPCON + LPCON + LPCON + 0x0050 + 0x20 + read-write + 0x00000020 + + + 8 + 1 + PLSE + PMU_V2IEN is disabled + + + 7 + 1 + PLHE + The hardware automatically disables PMU_V2IEN + + + 5 + 1 + RSE + LIRC_256K is enabled + + + 4 + 1 + RAD + LIRC_256K is automatically closed when you enter sleep mode + + + 3 + 1 + HAD + HIRC is automatically closed when you enter sleep mode + + + 2 + 1 + SAD + SRAM CE is automatically closed when you enter sleep mode + + + 1 + 1 + SCM + STOP mode + + + 0 + 1 + SLEEP + SLEEP mode + + + + + CHIPID_DCN + CHIPID_DCN + CHIPID_DCN + 0x005C + 0x20 + read-write + 0x00000008 + + + 16 + 8 + CDCN + Record version changes + + + 0 + 16 + CID + Chip ID + + + + + MODE + MODE + MODE + 0x0060 + 0x20 + read-write + 0x00000000 + + + + + PMUCON0 + PMUCON0 + PMUCON0 + 0x0064 + 0x20 + read-write + 0x10177800 + + + 25 + 4 + PH + Normal mode BG VREF voltage control + + + 23 + 1 + PIS + The internal temperature sensor was enabled + + + 22 + 1 + HPX + Internal LDO configuration options + + + 21 + 1 + PV + VREFMOM Voltage output + + + 20 + 1 + PHE + Analog bias current enabled + + + 18 + 1 + PHLI + VDD LDO weak pull-down resistance switch + + + 17 + 1 + PHI + VDD LDO pulldown resistance switch + + + 14 + 3 + PLIS + Low power reference current control + + + 13 + 1 + PHL + The LDO function in common mode is enabled + + + 12 + 1 + PHX + Internal LDO was enabled + + + 8 + 4 + PLS + ULPBG VREF voltage control + + + 7 + 1 + PID + Deep sleep current switch + + + 4 + 3 + PLD + Low power mode LDO voltage selection + + + 3 + 1 + PLSS + PMU low power acceleration + + + 0 + 3 + PHP + Normal mode LDO voltage selection + + + + + RPCON + RPCON + RPCON + 0x0068 + 0x20 + read-write + 0x00000000 + + + 18 + 1 + LRC + Software Write 1 Clear LOCK_RESET_PEND + + + 17 + 1 + SRC + Software Write 1 Clear SOFT_RESET_PEND + + + 16 + 1 + SSC + Software Write 1 Clear SLEEP_PEND + + + 2 + 1 + LRP + The CPU LOCK RESET flag bit occurs + + + 1 + 1 + SRP + The software writes 1 to the bit to trigger the system reset + + + 0 + 1 + SP + Enter the sleep mode flag bit + + + + + PMU_BK + PMU_BK + PMU_BK + 0x006C + 0x20 + read-write + 0x00000010 + + + 4 + 3 + PL + Low power mode LDO voltage tap selection + + + + + + + \ No newline at end of file diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 7530ccbc7..2e8f7811b 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -138,6 +138,7 @@ from . import target_Air001 from . import target_Air32F103xx from . import target_AMA3B1KK +from . import target_EG6832 ## @brief Dictionary of all builtin targets. # @@ -314,6 +315,7 @@ 'ytm32b1me0': target_ytm32b1me0.YTM32B1ME0, 'ytm32b1md1': target_ytm32b1md1.YTM32B1MD1, 'air001': target_Air001.Air001, + 'eg6832': target_EG6832.EG6832, 'air32f103xb': target_Air32F103xx.Air32F103xB, 'air32f103xc': target_Air32F103xx.Air32F103xC, 'air32f103xp': target_Air32F103xx.Air32F103xP, diff --git a/pyocd/target/builtin/target_EG6832.py b/pyocd/target/builtin/target_EG6832.py new file mode 100644 index 000000000..3ddd6afdf --- /dev/null +++ b/pyocd/target/builtin/target_EG6832.py @@ -0,0 +1,120 @@ +# pyOCD debugger +# Copyright (c) 2023 microcai +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...debug.svd.loader import SVDFile + +# pyOCD debugger +# Copyright (c) 2024 PyOCD Authors +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x211ab508, 0x90004348, 0xd0012800, 0xe7fa1e40, + 0x493bbd08, 0x22016188, 0xe00003d2, 0x69cb61ca, 0xd5fb041b, 0x0a404770, 0x47704770, 0xb5104770, + 0x48344a35, 0x48326010, 0x69813840, 0x01090909, 0x61811cc9, 0x24016b10, 0x43a00464, 0x200a6310, + 0xffd6f7ff, 0x43206b10, 0x200a6310, 0xffd0f7ff, 0x21036b10, 0x43880289, 0x184011a1, 0x6b106310, + 0xdafc2800, 0xf7ff2032, 0x6a50ffc3, 0x00800880, 0x62501c80, 0xf7ff2032, 0x2000ffbb, 0xbd106010, + 0xb672b500, 0x481e491d, 0x491e6141, 0xf7ff6141, 0x2000ffc6, 0x2000bd00, 0x48154770, 0x3840b510, + 0xf8acf000, 0x49154816, 0x49166141, 0x20006141, 0x01c0bd10, 0x480e0c01, 0x3840b510, 0xf895f000, + 0xbd102000, 0x1cc9b5f8, 0x4f09088c, 0x461500a4, 0x3f404606, 0x4632e008, 0x46382102, 0xf000682b, + 0x1f24f831, 0x1d361d2d, 0xd1f42c00, 0xbdf82000, 0x40020280, 0x3fac87e4, 0x40020000, 0x0000aaaa, + 0x40020180, 0x0000dddd, 0x04122201, 0x68012901, 0x4391d002, 0x47706001, 0xe7fb4311, 0x47706181, + 0x6181496c, 0xe7ef2100, 0xd0012900, 0xe0002100, 0x62014969, 0x29004770, 0x2100d001, 0x4967e000, + 0x47706241, 0x4604b510, 0x21004865, 0x46204002, 0xfff1f7ff, 0x612360e2, 0x064068a0, 0xbd10d5fc, + 0x4604b510, 0x2100485e, 0x46204002, 0xffdcf7ff, 0x07402001, 0x60e01810, 0x68a06123, 0xd5fc0640, + 0x2101bd10, 0x428a0409, 0x2102d201, 0x2102e7da, 0xb500e7e6, 0x4602460b, 0xd20f2980, 0x07c06890, + 0x2100d0fc, 0xf7ff4610, 0x0658ffc6, 0x0e402101, 0x18400789, 0x68906150, 0xd0fc07c0, 0xb500bd00, + 0x4602460b, 0xd20f2909, 0x07c06890, 0x2100d0fc, 0xf7ff4610, 0x0658ffa9, 0x0e402103, 0x18400749, + 0x68906150, 0xd0fc07c0, 0x2980bd00, 0xe7d0d200, 0xd2022989, 0xb2893980, 0x4770e7e1, 0x4602b500, + 0x07806890, 0x2100d5fc, 0xf7ff4610, 0x2001ff94, 0x615007c0, 0x07806890, 0xbd00d5fc, 0x42994b31, + 0x425bd305, 0x4b3018c9, 0x1d1b4019, 0x628118c9, 0x684162c2, 0x43114a2d, 0x68816041, 0xd5fc0549, + 0x47706b00, 0x4926b530, 0x400a9c03, 0x06496881, 0x6801d5fc, 0x02ad2501, 0x60014329, 0x628360c2, + 0x684162c4, 0x43114a21, 0x68816041, 0xd5fc0549, 0x43a96801, 0xbd306001, 0x491bb530, 0x400a9c03, + 0x06496881, 0x6801d5fc, 0x02ad2501, 0x60014329, 0x04eab291, 0x60c11889, 0x62c46283, 0x4a136841, + 0x60414311, 0x05496881, 0x6801d5fc, 0x600143a9, 0x6801bd30, 0x03122201, 0x60014311, 0x68014770, + 0x03122201, 0x60014391, 0x6b004770, 0x6c004770, 0x00004770, 0x00004041, 0x20150931, 0x20170230, + 0x0000fffc, 0x1ff00000, 0x1ffffffc, 0x04000400, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x200000a5, + 'pc_unInit': 0x200000bb, + 'pc_program_page': 0x200000e9, + 'pc_erase_sector': 0x200000d7, + 'pc_eraseAll': 0x200000bf, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000310, + 'begin_stack' : 0x20002000, + 'end_stack' : 0x20001720, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000320, + 0x20000b20 + ], + 'min_program_length' : 0x200, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x310, + 'rw_start': 0x314, + 'rw_size': 0x4, + 'zi_start': 0x318, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x10000, + 'sector_sizes': ( + (0x0, 0x200), + ) +} + +class EG6832(CoreSightTarget): + + VENDOR = "EG6832" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x0000_0000, length=0x10000, + blocksize=0x400, + is_boot_memory=True, algo=FLASH_ALGO), + RamRegion(start=0x2000_0000, length=0x1000) + ) + + def __init__(self, session): + super(EG6832, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("EG32M0x.svd")