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Create stdcell library for dekatronpc project #9

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radiolok opened this issue Jul 10, 2022 · 0 comments

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radiolok commented Jul 10, 2022 •

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На базе #7 разработать библиотеку элементов для дальнейшего синтеза схемотехники в yosys С помощью #8 Довести библиотеку до ума

radiolok added the verilog label

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